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authorJan Beulich <jbeulich@suse.com>2013-09-06 14:48:00 +0200
committerJan Beulich <jbeulich@suse.com>2013-09-06 14:48:00 +0200
commit22143eb77de49ab265f6a00e6413580d0d452594 (patch)
tree934ad0b2a8467784d3934fcfc420d85112715bea
parent334b5924569c6e391d78268b1481b96aa4293b0a (diff)
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x86/Intel: add support for Haswell CPU models
... according to their most recent public documentation. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org> master commit: 3e787021fb2420851c7bdc3911ea53c728ba5ac0 master date: 2013-08-27 11:15:15 +0200
-rw-r--r--xen/arch/x86/acpi/cpu_idle.c2
-rw-r--r--xen/arch/x86/hvm/vmx/vmx.c2
-rw-r--r--xen/arch/x86/hvm/vmx/vpmu_core2.c4
3 files changed, 7 insertions, 1 deletions
diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c
index 71f74abae0..c5c34dfbf0 100644
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -113,7 +113,9 @@ static void do_get_hw_residencies(void *arg)
case 0x3E:
/* Haswell */
case 0x3C:
+ case 0x3F:
case 0x45:
+ case 0x46:
GET_PC2_RES(hw_res->pc2);
GET_CC7_RES(hw_res->cc7);
/* fall through */
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index afcd760b9c..fa43971167 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -1809,7 +1809,7 @@ static const struct lbr_info *last_branch_msr_get(void)
/* Ivy Bridge */
case 58: case 62:
/* Haswell */
- case 60: case 69:
+ case 60: case 63: case 69: case 70:
return nh_lbr;
break;
/* Atom */
diff --git a/xen/arch/x86/hvm/vmx/vpmu_core2.c b/xen/arch/x86/hvm/vmx/vpmu_core2.c
index 01dc518788..290fd9fe0d 100644
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
@@ -747,7 +747,11 @@ int vmx_vpmu_initialise(struct vcpu *v, unsigned int vpmu_flags)
case 46:
case 47:
case 58:
+ case 60:
case 62:
+ case 63:
+ case 69:
+ case 70:
ret = core2_vpmu_initialise(v, vpmu_flags);
if ( !ret )
vpmu->arch_vpmu_ops = &core2_vpmu_ops;