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author | Jan Beulich <jbeulich@novell.com> | 2011-03-18 17:20:57 +0000 |
---|---|---|
committer | Jan Beulich <jbeulich@novell.com> | 2011-03-18 17:20:57 +0000 |
commit | bdfe4e38a790cac60d36f31fa5b15b7bd491c533 (patch) | |
tree | b2b9b684895875792043b371c23f699ed038a1ef | |
parent | 252cb0dc9feab4478d3895e29caf5b1166924637 (diff) | |
download | xen-bdfe4e38a790cac60d36f31fa5b15b7bd491c533.tar.gz xen-bdfe4e38a790cac60d36f31fa5b15b7bd491c533.tar.bz2 xen-bdfe4e38a790cac60d36f31fa5b15b7bd491c533.zip |
x86/mce: CPU notifiers must not be registered a second time during resume
While c/s 22964:f71212f712fd and 23051:93c864c16ab1 fixed issues with
CPU onlining, they introduced a problem with resume: mcheck_init() is
also being called on that path, and hence checking whether it's
running on CPU 0, which is generally not a really good thing, is
particularly inappropriate here.
Signed-off-by: Jan Beulich <jbeulich@novell.com>
xen-unstable changeset: 23060:b59e98bc6ff1
xen-unstable date: Fri Mar 18 17:15:19 2011 +0000
-rw-r--r-- | xen/arch/x86/acpi/power.c | 2 | ||||
-rw-r--r-- | xen/arch/x86/cpu/common.c | 14 | ||||
-rw-r--r-- | xen/arch/x86/cpu/mcheck/mce.c | 6 | ||||
-rw-r--r-- | xen/arch/x86/cpu/mcheck/mce.h | 2 | ||||
-rw-r--r-- | xen/arch/x86/cpu/mcheck/mce_intel.c | 4 | ||||
-rw-r--r-- | xen/include/asm-x86/processor.h | 2 |
6 files changed, 12 insertions, 18 deletions
diff --git a/xen/arch/x86/acpi/power.c b/xen/arch/x86/acpi/power.c index 5dfdeb431f..935c9a1101 100644 --- a/xen/arch/x86/acpi/power.c +++ b/xen/arch/x86/acpi/power.c @@ -187,7 +187,7 @@ static int enter_state(u32 state) device_power_up(); - mcheck_init(&boot_cpu_data); + mcheck_init(&boot_cpu_data, 0); write_cr4(cr4); printk(XENLOG_INFO "Finishing wakeup from ACPI S%d state.\n", state); diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 9223075691..8c5ec06caf 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -466,19 +466,13 @@ void __cpuinit identify_cpu(struct cpuinfo_x86 *c) /* AND the already accumulated flags with these */ for ( i = 0 ; i < NCAPINTS ; i++ ) boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; - } - - /* Init Machine Check Exception if available. */ - mcheck_init(c); -#if 0 - if (c == &boot_cpu_data) - sysenter_setup(); - enable_sep_cpu(); -#endif + mcheck_init(c, 0); + } else { + mcheck_init(c, 1); - if (c == &boot_cpu_data) mtrr_bp_init(); + } } /* cpuid returns the value latched in the HW at reset, not the APIC ID diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c index 0b7458a87e..5e0a6a2866 100644 --- a/xen/arch/x86/cpu/mcheck/mce.c +++ b/xen/arch/x86/cpu/mcheck/mce.c @@ -793,7 +793,7 @@ static struct notifier_block cpu_nfb = { }; /* This has to be run for each processor */ -void mcheck_init(struct cpuinfo_x86 *c) +void mcheck_init(struct cpuinfo_x86 *c, bool_t bsp) { enum mcheck_type inited = mcheck_none; @@ -822,7 +822,7 @@ void mcheck_init(struct cpuinfo_x86 *c) switch (c->x86) { case 6: case 15: - inited = intel_mcheck_init(c); + inited = intel_mcheck_init(c, bsp); break; } break; @@ -844,7 +844,7 @@ void mcheck_init(struct cpuinfo_x86 *c) /* Turn on MCE now */ set_in_cr4(X86_CR4_MCE); - if ( smp_processor_id() == 0 ) + if ( bsp ) { /* Early MCE initialisation for BSP. */ if ( cpu_poll_bankmask_alloc(0) ) diff --git a/xen/arch/x86/cpu/mcheck/mce.h b/xen/arch/x86/cpu/mcheck/mce.h index 26ed4d634d..f87fd08481 100644 --- a/xen/arch/x86/cpu/mcheck/mce.h +++ b/xen/arch/x86/cpu/mcheck/mce.h @@ -42,7 +42,7 @@ enum mcheck_type amd_k7_mcheck_init(struct cpuinfo_x86 *c); enum mcheck_type amd_k8_mcheck_init(struct cpuinfo_x86 *c); enum mcheck_type amd_f10_mcheck_init(struct cpuinfo_x86 *c); -enum mcheck_type intel_mcheck_init(struct cpuinfo_x86 *c); +enum mcheck_type intel_mcheck_init(struct cpuinfo_x86 *c, bool_t bsp); void intel_mcheck_timer(struct cpuinfo_x86 *c); void mce_intel_feature_init(struct cpuinfo_x86 *c); diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c index 8c7634e2d9..603acf7a82 100644 --- a/xen/arch/x86/cpu/mcheck/mce_intel.c +++ b/xen/arch/x86/cpu/mcheck/mce_intel.c @@ -1293,9 +1293,9 @@ static struct notifier_block cpu_nfb = { }; /* p4/p6 family have similar MCA initialization process */ -enum mcheck_type intel_mcheck_init(struct cpuinfo_x86 *c) +enum mcheck_type intel_mcheck_init(struct cpuinfo_x86 *c, bool_t bsp) { - if ( smp_processor_id() == 0 ) + if ( bsp ) { /* Early MCE initialisation for BSP. */ if ( cpu_mcabank_alloc(0) ) diff --git a/xen/include/asm-x86/processor.h b/xen/include/asm-x86/processor.h index b4b3d5cb8b..128295bff0 100644 --- a/xen/include/asm-x86/processor.h +++ b/xen/include/asm-x86/processor.h @@ -555,7 +555,7 @@ void compat_show_guest_stack(struct vcpu *, struct cpu_user_regs *, int lines); extern void mtrr_ap_init(void); extern void mtrr_bp_init(void); -void mcheck_init(struct cpuinfo_x86 *c); +void mcheck_init(struct cpuinfo_x86 *c, bool_t bsp); #define DECLARE_TRAP_HANDLER(_name) \ asmlinkage void _name(void); \ |