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| author | Boris Ostrovsky <boris.ostrovsky@amd.com> | 2013-02-12 13:32:05 +0100 |
|---|---|---|
| committer | Boris Ostrovsky <boris.ostrovsky@amd.com> | 2013-02-12 13:32:05 +0100 |
| commit | 7b4e26e32f0eaea918b11a7de3ef265bc32b6fd3 (patch) | |
| tree | a4570e2854fcb09d84b087d1b0dbae97fc3b76dc | |
| parent | 4d249d79db70dc2756f6c102e2ddaeee14d7ac42 (diff) | |
| download | xen-7b4e26e32f0eaea918b11a7de3ef265bc32b6fd3.tar.gz xen-7b4e26e32f0eaea918b11a7de3ef265bc32b6fd3.tar.bz2 xen-7b4e26e32f0eaea918b11a7de3ef265bc32b6fd3.zip | |
x86/AMD: Enable WC+ memory type on family 10 processors
In some cases BIOS may not enable WC+ memory type on family 10 processors,
instead converting what would be WC+ memory to CD type. On guests using
nested pages this could result in performance degradation. This patch
enables WC+.
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@amd.com>
xen-unstable changeset: 26427:8f6dd5dc5d6c
xen-unstable date: Fri Jan 18 11:20:58 UTC 2013
| -rw-r--r-- | xen/arch/x86/cpu/amd.c | 13 | ||||
| -rw-r--r-- | xen/include/asm-x86/msr-index.h | 5 |
2 files changed, 16 insertions, 2 deletions
diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index 32d51c9bed..bd19c2360d 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -661,6 +661,19 @@ static void __devinit init_amd(struct cpuinfo_x86 *c) } #endif + if (c->x86 == 0x10) { + /* + * On family 10h BIOS may not have properly enabled WC+ + * support, causing it to be converted to CD memtype. This may + * result in performance degradation for certain nested-paging + * guests. Prevent this conversion by clearing bit 24 in + * MSR_F10_BU_CFG2. + */ + rdmsrl(MSR_F10_BU_CFG2, value); + value &= ~(1ULL << 24); + wrmsrl(MSR_F10_BU_CFG2, value); + } + /* * Family 0x12 and above processors have APIC timer * running in deep C states. diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index c69676a949..0b81710c6a 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -254,8 +254,9 @@ #define MSR_F10_MC4_MISC2 0xc0000409 #define MSR_F10_MC4_MISC3 0xc000040A -/* AMD Family10h MMU control MSRs */ -#define MSR_F10_BU_CFG 0xc0011023 +/* AMD Family10h Bus Unit MSRs */ +#define MSR_F10_BU_CFG 0xc0011023 +#define MSR_F10_BU_CFG2 0xc001102a /* Other AMD Fam10h MSRs */ #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 |