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| author | Andre Przywara <osp@andrep.de> | 2013-01-08 10:23:37 +0100 |
|---|---|---|
| committer | Andre Przywara <osp@andrep.de> | 2013-01-08 10:23:37 +0100 |
| commit | 6bb00d9e66c191b86a29e1e3aee253529c16a00e (patch) | |
| tree | 82001d9defd542428338eb62a3d781094f180312 | |
| parent | 89ca76c799accba866a2597499b5fedf220ba843 (diff) | |
| download | xen-6bb00d9e66c191b86a29e1e3aee253529c16a00e.tar.gz xen-6bb00d9e66c191b86a29e1e3aee253529c16a00e.tar.bz2 xen-6bb00d9e66c191b86a29e1e3aee253529c16a00e.zip | |
x86, amd: Disable way access filter on Piledriver CPUs
The Way Access Filter in recent AMD CPUs may hurt the performance of
some workloads, caused by aliasing issues in the L1 cache.
This patch disables it on the affected CPUs.
The issue is similar to that one of last year:
http://lkml.indiana.edu/hypermail/linux/kernel/1107.3/00041.html
This new patch does not replace the old one, we just need another
quirk for newer CPUs.
The performance penalty without the patch depends on the
circumstances, but is a bit less than the last year's 3%.
The workloads affected would be those that access code from the same
physical page under different virtual addresses, so different
processes using the same libraries with ASLR or multiple instances of
PIE-binaries. The code needs to be accessed simultaneously from both
cores of the same compute unit.
More details can be found here:
http://developer.amd.com/Assets/SharedL1InstructionCacheonAMD15hCPU.pdf
CPUs affected are anything with the core known as Piledriver.
That includes the new parts of the AMD A-Series (aka Trinity) and the
just released new CPUs of the FX-Series (aka Vishera).
The model numbering is a bit odd here: FX CPUs have model 2,
A-Series has model 10h, with possible extensions to 1Fh. Hence the
range of model ids.
Signed-off-by: Andre Przywara <osp@andrep.de>
Add and use MSR_AMD64_IC_CFG. Update the value whenever it is found to
not have all bits set, rather than just when it's zero.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Keir Fraser <keir@xen.org>
xen-unstable changeset: 26294:5fb0b8b838da
xen-unstable date: Wed Dec 19 10:42:09 UTC 2012
| -rw-r--r-- | xen/arch/x86/cpu/amd.c | 8 | ||||
| -rw-r--r-- | xen/include/asm-x86/msr-index.h | 1 |
2 files changed, 9 insertions, 0 deletions
diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index 6167f92813..32d51c9bed 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -616,6 +616,14 @@ static void __devinit init_amd(struct cpuinfo_x86 *c) } } + /* + * The way access filter has a performance penalty on some workloads. + * Disable it on the affected CPUs. + */ + if (c->x86 == 0x15 && c->x86_model >= 0x02 && c->x86_model < 0x20 && + !rdmsr_safe(MSR_AMD64_IC_CFG, value) && (value & 0x1e) != 0x1e) + wrmsr_safe(MSR_AMD64_IC_CFG, value | 0x1e); + amd_get_topology(c); /* Pointless to use MWAIT on Family10 as it does not deep sleep. */ diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index f97afd6be2..c69676a949 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -245,6 +245,7 @@ /* AMD64 MSRs */ #define MSR_AMD64_NB_CFG 0xc001001f +#define MSR_AMD64_IC_CFG 0xc0011021 #define MSR_AMD64_DC_CFG 0xc0011022 #define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT 46 |