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authorKeir Fraser <keir@xen.org>2011-01-26 08:45:40 +0000
committerKeir Fraser <keir@xen.org>2011-01-26 08:45:40 +0000
commit16b2a6cf7fb0585fcfd51b0f4febac3be91a91a1 (patch)
treea533246bec518926d8f027703d73c5f0873abba6
parent36d7b2d453e1aebaa76844613a24bde528c68b75 (diff)
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x86: blacklist new AMD CPUID bits for PV domains
there are some new CPUID bits (and leaves) which Dom0 and PV domains should not see to avoid trouble, since we don't emulate the features. The most prominent one is a topology leaf, which contains information specific to the physical CPU, not the virtual one. To avoid confusion (and possibly crashes) due to a confused Dom0 scheduler simply disable these bits. Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Keir Fraser <keir@xen.org>
-rw-r--r--tools/libxc/xc_cpuid_x86.c5
-rw-r--r--xen/arch/x86/traps.c5
2 files changed, 10 insertions, 0 deletions
diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c
index 724ed0f124..407a53543f 100644
--- a/tools/libxc/xc_cpuid_x86.c
+++ b/tools/libxc/xc_cpuid_x86.c
@@ -427,12 +427,17 @@ static void xc_cpuid_pv_policy(
clear_bit(X86_FEATURE_IBS, regs[2]);
clear_bit(X86_FEATURE_SKINIT, regs[2]);
clear_bit(X86_FEATURE_WDT, regs[2]);
+ clear_bit(X86_FEATURE_LWP, regs[2]);
+ clear_bit(X86_FEATURE_NODEID_MSR, regs[2]);
+ clear_bit(X86_FEATURE_TOPOEXT, regs[2]);
break;
case 5: /* MONITOR/MWAIT */
case 0xa: /* Architectural Performance Monitor Features */
case 0xd: /* XSAVE */
case 0x8000000a: /* SVM revision and features */
case 0x8000001b: /* Instruction Based Sampling */
+ case 0x8000001c: /* Light Weight Profiling */
+ case 0x8000001e: /* Extended topology reporting */
regs[0] = regs[1] = regs[2] = regs[3] = 0;
break;
}
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 75d305fa6d..97e3dc4a40 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -802,11 +802,16 @@ static void pv_cpuid(struct cpu_user_regs *regs)
__clear_bit(X86_FEATURE_IBS % 32, &c);
__clear_bit(X86_FEATURE_SKINIT % 32, &c);
__clear_bit(X86_FEATURE_WDT % 32, &c);
+ __clear_bit(X86_FEATURE_LWP % 32, &c);
+ __clear_bit(X86_FEATURE_NODEID_MSR % 32, &c);
+ __clear_bit(X86_FEATURE_TOPOEXT % 32, &c);
break;
case 5: /* MONITOR/MWAIT */
case 0xa: /* Architectural Performance Monitor Features */
case 0x8000000a: /* SVM revision and features */
case 0x8000001b: /* Instruction Based Sampling */
+ case 0x8000001c: /* Light Weight Profiling */
+ case 0x8000001e: /* Extended topology reporting */
a = b = c = d = 0;
break;
default: