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author | Keir Fraser <keir@xen.org> | 2011-01-27 16:17:27 +0000 |
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committer | Keir Fraser <keir@xen.org> | 2011-01-27 16:17:27 +0000 |
commit | 0145b0e442c094e02b698ea998e5c4ff9d346d6a (patch) | |
tree | c826af9240f4387b3895c202069a0b1421f27ad3 | |
parent | 688fe3de6797102afdc265051455f81c86dc211d (diff) | |
download | xen-0145b0e442c094e02b698ea998e5c4ff9d346d6a.tar.gz xen-0145b0e442c094e02b698ea998e5c4ff9d346d6a.tar.bz2 xen-0145b0e442c094e02b698ea998e5c4ff9d346d6a.zip |
hvm: allow pass-through of new FPU/ALU CPUID features
there are some new CPUID features that are safe for guests to see, as
they don't require OS awareness (FPU/ALU related instructions only).
Among features for new AMD CPUs there is also the PCLMULQDQ bit, which
Intel CPU have already for quite a while.
Signed-off-by: Andre Przywara <andre.przywara@amd.com>
-rw-r--r-- | tools/libxc/xc_cpufeature.h | 2 | ||||
-rw-r--r-- | tools/libxc/xc_cpuid_x86.c | 7 | ||||
-rw-r--r-- | tools/libxl/libxl_cpuid.c | 1 | ||||
-rw-r--r-- | xen/include/asm-x86/cpufeature.h | 2 |
4 files changed, 11 insertions, 1 deletions
diff --git a/tools/libxc/xc_cpufeature.h b/tools/libxc/xc_cpufeature.h index 07bdb95f1b..5263774ab3 100644 --- a/tools/libxc/xc_cpufeature.h +++ b/tools/libxc/xc_cpufeature.h @@ -83,6 +83,7 @@ /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ +#define X86_FEATURE_PCLMULQDQ (4*32+ 1) /* Carry-less multiplication */ #define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */ #define X86_FEATURE_MWAIT (4*32+ 3) /* Monitor/Mwait support */ #define X86_FEATURE_DSCPL (4*32+ 4) /* CPL Qualified Debug Store */ @@ -104,6 +105,7 @@ #define X86_FEATURE_AES (4*32+25) /* AES acceleration instructions */ #define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ #define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */ +#define X86_FEATURE_F16C (4*32+29) /* Half-precision convert instruction */ #define X86_FEATURE_HYPERVISOR (4*32+31) /* Running under some hypervisor */ /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c index 407a53543f..150ca18066 100644 --- a/tools/libxc/xc_cpuid_x86.c +++ b/tools/libxc/xc_cpuid_x86.c @@ -101,7 +101,10 @@ static void amd_xc_cpuid_policy( bitmaskof(X86_FEATURE_ABM) | bitmaskof(X86_FEATURE_SSE4A) | bitmaskof(X86_FEATURE_MISALIGNSSE) | - bitmaskof(X86_FEATURE_3DNOWPREFETCH)); + bitmaskof(X86_FEATURE_3DNOWPREFETCH) | + bitmaskof(X86_FEATURE_XOP) | + bitmaskof(X86_FEATURE_FMA4) | + bitmaskof(X86_FEATURE_TBM)); regs[3] &= (0x0183f3ff | /* features shared with 0x00000001:EDX */ (is_pae ? bitmaskof(X86_FEATURE_NX) : 0) | (is_64bit ? bitmaskof(X86_FEATURE_LM) : 0) | @@ -251,12 +254,14 @@ static void xc_cpuid_hvm_policy( regs[1] = (regs[1] & 0x0000ffffu) | ((regs[1] & 0x007f0000u) << 1); regs[2] &= (bitmaskof(X86_FEATURE_XMM3) | + bitmaskof(X86_FEATURE_PCLMULQDQ) | bitmaskof(X86_FEATURE_SSSE3) | bitmaskof(X86_FEATURE_CX16) | bitmaskof(X86_FEATURE_SSE4_1) | bitmaskof(X86_FEATURE_SSE4_2) | bitmaskof(X86_FEATURE_POPCNT) | bitmaskof(X86_FEATURE_AES) | + bitmaskof(X86_FEATURE_F16C) | ((xfeature_mask != 0) ? (bitmaskof(X86_FEATURE_AVX) | bitmaskof(X86_FEATURE_XSAVE)) : 0)); diff --git a/tools/libxl/libxl_cpuid.c b/tools/libxl/libxl_cpuid.c index 16348021a6..5c591f6f63 100644 --- a/tools/libxl/libxl_cpuid.c +++ b/tools/libxl/libxl_cpuid.c @@ -115,6 +115,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str) {"dscpl", 0x00000001, NA, CPUID_REG_ECX, 4, 1}, {"monitor", 0x00000001, NA, CPUID_REG_ECX, 3, 1}, {"dtes64", 0x00000001, NA, CPUID_REG_ECX, 2, 1}, + {"pclmulqdq", 0x00000001, NA, CPUID_REG_ECX, 1, 1}, {"sse3", 0x00000001, NA, CPUID_REG_ECX, 0, 1}, {"pbe", 0x00000001, NA, CPUID_REG_EDX, 31, 1}, {"ia64", 0x00000001, NA, CPUID_REG_EDX, 30, 1}, diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h index 8d9b49d610..9b783ad1da 100644 --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -82,6 +82,7 @@ /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ +#define X86_FEATURE_PCLMULQDQ (4*32+ 1) /* Carry-less mulitplication */ #define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */ #define X86_FEATURE_MWAIT (4*32+ 3) /* Monitor/Mwait support */ #define X86_FEATURE_DSCPL (4*32+ 4) /* CPL Qualified Debug Store */ @@ -103,6 +104,7 @@ #define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ #define X86_FEATURE_OSXSAVE (4*32+27) /* OSXSAVE */ #define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */ +#define X86_FEATURE_F16C (4*32+29) /* Half-precision convert instruction */ #define X86_FEATURE_HYPERVISOR (4*32+31) /* Running under some hypervisor */ /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ |