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authorKeir Fraser <keir.fraser@citrix.com>2010-02-17 12:05:45 +0000
committerKeir Fraser <keir.fraser@citrix.com>2010-02-17 12:05:45 +0000
commitf0f775cad1e258422cac7fb2c3bf97554f35d739 (patch)
tree3e5dc215fb48be36e0387f1ec02d08920b0990b1
parent86fd4176f4c70c830de86503bb5ce72a1f2e76b6 (diff)
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Mask AMD CPUID masks in software before writing them to the MSRs
Mask AMD CPUID masks in software before writing them to the MSRs. Setting bits in the CPUID mask MSR that are not set in the unmasked CPUID response can cause those bits to be set in the masked response. Avoid that by explicitly masking in software. Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com>
-rw-r--r--xen/arch/x86/cpu/amd.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 94f35770e5..aabfd4c9ba 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -130,6 +130,14 @@ static void __devinit set_cpuidmask(struct cpuinfo_x86 *c)
return;
}
+ /* Setting bits in the CPUID mask MSR that are not set in the
+ * unmasked CPUID response can cause those bits to be set in the
+ * masked response. Avoid that by explicitly masking in software. */
+ feat_ecx &= cpuid_ecx(0x00000001);
+ feat_edx &= cpuid_edx(0x00000001);
+ extfeat_ecx &= cpuid_ecx(0x80000001);
+ extfeat_edx &= cpuid_edx(0x80000001);
+
status = set_mask;
printk("Writing CPUID feature mask ECX:EDX -> %08Xh:%08Xh\n",
feat_ecx, feat_edx);