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author | Alex Williamson <alex.williamson@hp.com> | 2007-12-17 09:56:12 -0700 |
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committer | Alex Williamson <alex.williamson@hp.com> | 2007-12-17 09:56:12 -0700 |
commit | ab6f5a6165dd872986fbacd686b6e3635ecefc2c (patch) | |
tree | ac01c1a8d5557b4fb2a6bb4252aff559d2c04f8f | |
parent | 5ba35dee5b802667a5cc9103936b98810c328456 (diff) | |
download | xen-ab6f5a6165dd872986fbacd686b6e3635ecefc2c.tar.gz xen-ab6f5a6165dd872986fbacd686b6e3635ecefc2c.tar.bz2 xen-ab6f5a6165dd872986fbacd686b6e3635ecefc2c.zip |
[IA64] xenoprof: don't modify mPSR.pp. VTi case
Don't modify mPSR.pp for xenoprof. VTi domain case
xenoprof manages mPSR.pp so that mPSR.pp shouldn't be modified.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
-rw-r--r-- | xen/arch/ia64/vmx/optvfault.S | 16 | ||||
-rw-r--r-- | xen/arch/ia64/vmx/vmx_vcpu.c | 17 | ||||
-rw-r--r-- | xen/arch/ia64/xen/domain.c | 8 |
3 files changed, 35 insertions, 6 deletions
diff --git a/xen/arch/ia64/vmx/optvfault.S b/xen/arch/ia64/vmx/optvfault.S index 290f1ebead..1e02ea4076 100644 --- a/xen/arch/ia64/vmx/optvfault.S +++ b/xen/arch/ia64/vmx/optvfault.S @@ -200,7 +200,12 @@ GLOBAL_ENTRY(vmx_asm_rsm) dep r26=r28,r26,23,1 ;; ld8 r18=[r17] - movl r28=IA64_PSR_IC+IA64_PSR_I+IA64_PSR_DT+IA64_PSR_SI + + // xenoprof + // Don't change mPSR.pp. + // It is manipulated by xenoprof. + movl r28=IA64_PSR_IC+IA64_PSR_I+IA64_PSR_DT+IA64_PSR_SI+IA64_PSR_PP + ld1 r23=[r22] sub r27=-1,r26 // ~r26 mov r24=b0 @@ -260,6 +265,9 @@ GLOBAL_ENTRY(vmx_asm_ssm) ;; //r19 vpsr ld8 r29=[r27] mov r24=b0 + dep r17=0,r26,IA64_PSR_PP_BIT,1 // For xenoprof + // Don't change mPSR.pp + // It is maintained by xenoprof. ;; add r22=IA64_VCPU_MMU_MODE_OFFSET,r21 mov r20=cr.ipsr @@ -267,7 +275,7 @@ GLOBAL_ENTRY(vmx_asm_ssm) ;; ld1 r23=[r22] // mmu_mode st8 [r27]=r19 // vpsr - or r20=r20,r26 + or r20=r20,r17 ;; mov cr.ipsr=r20 movl r28=IA64_PSR_DT+IA64_PSR_RT+IA64_PSR_IT @@ -379,6 +387,7 @@ vmx_asm_mov_to_psr_1: mov r20=cr.ipsr movl r28=IA64_PSR_IC+IA64_PSR_I+IA64_PSR_DT+IA64_PSR_SI+IA64_PSR_RT ;; + tbit.nz p7,p0=r20,IA64_PSR_PP_BIT // For xenoprof or r19=r19,r28 dep r20=0,r20,0,32 ;; @@ -386,6 +395,9 @@ vmx_asm_mov_to_psr_1: mov b0=r24 ;; adds r27=IA64_VCPU_FP_PSR_OFFSET,r21 + (p7) dep r20=-1,r20,IA64_PSR_PP_BIT,1 // For xenoprof + // Dom't change mPSR.pp + // It is maintaned by xenoprof ;; ld8 r27=[r27] ;; diff --git a/xen/arch/ia64/vmx/vmx_vcpu.c b/xen/arch/ia64/vmx/vmx_vcpu.c index 577eeeb2b2..6df63e7d6f 100644 --- a/xen/arch/ia64/vmx/vmx_vcpu.c +++ b/xen/arch/ia64/vmx/vmx_vcpu.c @@ -60,7 +60,12 @@ unsigned long guest_psr_index = 0; void vmx_ia64_set_dcr(VCPU *v) { - unsigned long dcr_bits = IA64_DEFAULT_DCR_BITS; + /* xenoprof: + * don't change psr.pp. + * It is manipulated by xenoprof. + */ + unsigned long dcr_bits = (IA64_DEFAULT_DCR_BITS & ~IA64_DCR_PP) | + (ia64_getreg(_IA64_REG_CR_DCR) & IA64_DCR_PP); // if guest is runing on cpl > 0, set dcr.dm=1 // if geust is runing on cpl = 0, set dcr.dm=0 @@ -128,10 +133,16 @@ vmx_vcpu_set_psr(VCPU *vcpu, unsigned long value) * , except for the following bits: * ic/i/dt/si/rt/mc/it/bn/vm */ - mask = IA64_PSR_IC + IA64_PSR_I + IA64_PSR_DT + IA64_PSR_SI + - IA64_PSR_RT + IA64_PSR_MC + IA64_PSR_IT + IA64_PSR_BN + + mask = IA64_PSR_IC | IA64_PSR_I | IA64_PSR_DT | IA64_PSR_SI | + IA64_PSR_RT | IA64_PSR_MC | IA64_PSR_IT | IA64_PSR_BN | IA64_PSR_VM; + /* xenoprof: + * don't change psr.pp. + * It is manipulated by xenoprof. + */ + mask |= IA64_PSR_PP; + regs->cr_ipsr = (regs->cr_ipsr & mask ) | ( value & (~mask) ); if (FP_PSR(vcpu) & IA64_PSR_DFH) diff --git a/xen/arch/ia64/xen/domain.c b/xen/arch/ia64/xen/domain.c index 577721d76c..2ed034079c 100644 --- a/xen/arch/ia64/xen/domain.c +++ b/xen/arch/ia64/xen/domain.c @@ -231,7 +231,13 @@ void context_switch(struct vcpu *prev, struct vcpu *next) if (!VMX_DOMAIN(next)) { /* VMX domains can change the physical cr.dcr. * Restore default to prevent leakage. */ - ia64_setreg(_IA64_REG_CR_DCR, IA64_DEFAULT_DCR_BITS); + uint64_t dcr = ia64_getreg(_IA64_REG_CR_DCR); + /* xenoprof: + * don't change psr.pp. + * It is manipulated by xenoprof. + */ + dcr = (IA64_DEFAULT_DCR_BITS & ~IA64_DCR_PP) | (dcr & IA64_DCR_PP); + ia64_setreg(_IA64_REG_CR_DCR, dcr); } } if (VMX_DOMAIN(next)) |