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| author | awilliam@xenbuild2.aw <awilliam@xenbuild2.aw> | 2006-12-18 10:04:49 -0700 |
|---|---|---|
| committer | awilliam@xenbuild2.aw <awilliam@xenbuild2.aw> | 2006-12-18 10:04:49 -0700 |
| commit | 97e1ae7cfce9b08ed20244a8d0670e0b820dea81 (patch) | |
| tree | d77414eac7f78d03509d34baa9505f03f203a829 | |
| parent | d16bdf4c1d2dd5b3b88a6f45e4ba0d5fcc13259c (diff) | |
| download | xen-97e1ae7cfce9b08ed20244a8d0670e0b820dea81.tar.gz xen-97e1ae7cfce9b08ed20244a8d0670e0b820dea81.tar.bz2 xen-97e1ae7cfce9b08ed20244a8d0670e0b820dea81.zip | |
[IA64] Mask out reserved bits to avoid Reserved Register/Field faults.
Signed-off-by: Dietmar Hahn <dietmar.hahn@fujitsu-siemens.com>
| -rw-r--r-- | xen/arch/ia64/xen/vcpu.c | 1 | ||||
| -rw-r--r-- | xen/include/asm-ia64/linux-xen/asm/pgtable.h | 5 |
2 files changed, 6 insertions, 0 deletions
diff --git a/xen/arch/ia64/xen/vcpu.c b/xen/arch/ia64/xen/vcpu.c index 119fb54b20..6c3861a3a9 100644 --- a/xen/arch/ia64/xen/vcpu.c +++ b/xen/arch/ia64/xen/vcpu.c @@ -2162,6 +2162,7 @@ vcpu_itc_no_srlz(VCPU * vcpu, u64 IorD, u64 vaddr, u64 pte, BUG_ON(logps > PAGE_SHIFT); vcpu_tlb_track_insert_or_dirty(vcpu, vaddr, entry); psr = ia64_clear_ic(); + pte &= ~(_PAGE_RV2 | _PAGE_RV1); // Mask out the reserved bits. ia64_itc(IorD, vaddr, pte, ps); // FIXME: look for bigger mappings ia64_set_psr(psr); // ia64_srlz_i(); // no srls req'd, will rfi later diff --git a/xen/include/asm-ia64/linux-xen/asm/pgtable.h b/xen/include/asm-ia64/linux-xen/asm/pgtable.h index 7e93544785..0ff6784917 100644 --- a/xen/include/asm-ia64/linux-xen/asm/pgtable.h +++ b/xen/include/asm-ia64/linux-xen/asm/pgtable.h @@ -39,6 +39,11 @@ #define _PAGE_P (1 << _PAGE_P_BIT) /* page present bit */ #define _PAGE_MA_WB (0x0 << 2) /* write back memory attribute */ #ifdef XEN +#define _PAGE_RV1_BIT 1 +#define _PAGE_RV2_BIT 50 +#define _PAGE_RV1 (__IA64_UL(1) << _PAGE_RV1_BIT) /* reserved bit */ +#define _PAGE_RV2 (__IA64_UL(3) << _PAGE_RV2_BIT) /* reserved bits */ + #define _PAGE_MA_ST (0x1 << 2) /* is reserved for software use */ #endif #define _PAGE_MA_UC (0x4 << 2) /* uncacheable memory attribute */ |