From 3f2546b2ef55b661fd8dd69682b38992225e86f6 Mon Sep 17 00:00:00 2001 From: fishsoupisgood Date: Mon, 29 Apr 2019 01:17:54 +0100 Subject: Initial import of qemu-2.4.1 --- roms/u-boot/board/esd/pci405/Makefile | 9 + roms/u-boot/board/esd/pci405/cmd_pci405.c | 95 ++ roms/u-boot/board/esd/pci405/flash.c | 85 ++ roms/u-boot/board/esd/pci405/fpgadata.c | 1492 +++++++++++++++++++++++++++++ roms/u-boot/board/esd/pci405/pci405.c | 366 +++++++ roms/u-boot/board/esd/pci405/pci405.h | 16 + roms/u-boot/board/esd/pci405/writeibm.S | 205 ++++ 7 files changed, 2268 insertions(+) create mode 100644 roms/u-boot/board/esd/pci405/Makefile create mode 100644 roms/u-boot/board/esd/pci405/cmd_pci405.c create mode 100644 roms/u-boot/board/esd/pci405/flash.c create mode 100644 roms/u-boot/board/esd/pci405/fpgadata.c create mode 100644 roms/u-boot/board/esd/pci405/pci405.c create mode 100644 roms/u-boot/board/esd/pci405/pci405.h create mode 100644 roms/u-boot/board/esd/pci405/writeibm.S (limited to 'roms/u-boot/board/esd/pci405') diff --git a/roms/u-boot/board/esd/pci405/Makefile b/roms/u-boot/board/esd/pci405/Makefile new file mode 100644 index 00000000..9e659c79 --- /dev/null +++ b/roms/u-boot/board/esd/pci405/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = pci405.o flash.o ../common/misc.o cmd_pci405.o +obj-y += writeibm.o diff --git a/roms/u-boot/board/esd/pci405/cmd_pci405.c b/roms/u-boot/board/esd/pci405/cmd_pci405.c new file mode 100644 index 00000000..55c20d02 --- /dev/null +++ b/roms/u-boot/board/esd/pci405/cmd_pci405.c @@ -0,0 +1,95 @@ +/* + * (C) Copyright 2002-2004 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pci405.h" + +#if defined(CONFIG_CMD_BSP) + +/* + * Command loadpci: wait for signal from host and boot image. + */ +int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned int *ptr = 0; + int count = 0; + int count2 = 0; + int i; + char addr[16]; + char str[] = "\\|/-"; + char *local_args[2]; + + /* + * Mark sync address + */ + ptr = 0; + *ptr = 0xffffffff; + puts("\nWaiting for image from pci host -"); + + /* + * Wait for host to write the start address + */ + while (*ptr == 0xffffffff) { + count++; + if (!(count % 100)) { + count2++; + putc(0x08); /* backspace */ + putc(str[count2 % 4]); + } + + /* Abort if ctrl-c was pressed */ + if (ctrlc()) { + puts("\nAbort\n"); + return 0; + } + + udelay(1000); + } + + if (*ptr == PCI_RECONFIG_MAGIC) { + /* + * Save own pci configuration in PRAM + */ + memset((char *)PCI_REGS_ADDR, 0, PCI_REGS_LEN); + ptr = (unsigned int *)PCI_REGS_ADDR + 1; + for (i=0; i<0x40; i+=4) { + pci_read_config_dword(PCIDEVID_405GP, i, ptr++); + } + ptr = (unsigned int *)PCI_REGS_ADDR; + *ptr = crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4); + + printf("\nStoring PCI Configuration Regs...\n"); + } else { + sprintf(addr, "%08x", *ptr); + + /* + * Boot image via bootm + */ + printf("\nBooting Image at addr 0x%s ...\n", addr); + setenv("loadaddr", addr); + + local_args[0] = argv[0]; + local_args[1] = NULL; + do_bootm (cmdtp, 0, 1, local_args); + } + + return 0; +} +U_BOOT_CMD( + loadpci, 1, 1, do_loadpci, + "Wait for pci-image and boot it", + "" +); +#endif diff --git a/roms/u-boot/board/esd/pci405/flash.c b/roms/u-boot/board/esd/pci405/flash.c new file mode 100644 index 00000000..113111d3 --- /dev/null +++ b/roms/u-boot/board/esd/pci405/flash.c @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); +static void flash_get_offsets (ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + int i; + uint pbcr; + unsigned long base_b0; + int size_val = 0; + + /* Init: no FLASHes known */ + for (i=0; i +#include +#include +#include +#include +#include +#include + +#include "pci405.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* Prototypes */ +unsigned long fpga_done_state(void); +unsigned long fpga_init_state(void); + +#if 0 +#define FPGA_DEBUG +#endif + +/* predefine these here */ +#define FPGA_DONE_STATE (fpga_done_state()) +#define FPGA_INIT_STATE (fpga_init_state()) + +/* fpga configuration data - generated by bin2cc */ +const unsigned char fpgadata[] = +{ +#include "fpgadata.c" +}; + +/* + * include common fpga code (for esd boards) + */ +#include "../common/fpga.c" + +#define FPGA_DONE_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE) +#define FPGA_DONE_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE_V12) + +#define FPGA_INIT_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT) +#define FPGA_INIT_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT_V12) + + +int board_revision(void) +{ + unsigned long CPC0_CR0Reg; + unsigned long value; + + /* + * Get version of PCI405 board from GPIO's + */ + + /* + * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO) + */ + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000); + out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200); + out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200); + udelay(1000); /* wait some time before reading input */ + value = in_be32((void*)GPIO0_IR) & 0x00100200; /* get config bits */ + + /* + * Restore GPIO settings + */ + mtdcr(CPC0_CR0, CPC0_CR0Reg); + + switch (value) { + case 0x00100200: + /* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */ + return 1; + case 0x00000200: + /* CS2==0 && IRQ5==1 -> version 1.2 */ + return 2; + case 0x00000000: + /* CS2==0 && IRQ5==0 -> version 1.3 */ + return 3; +#if 0 /* not yet manufactured ! */ + case 0x00100000: + /* CS2==1 && IRQ5==0 -> version 1.4 */ + return 4; +#endif + default: + /* should not be reached! */ + return 0; + } +} + + +unsigned long fpga_done_state(void) +{ + if (gd->board_type < 2) { + return FPGA_DONE_STATE_V11; + } else { + return FPGA_DONE_STATE_V12; + } +} + + +unsigned long fpga_init_state(void) +{ + if (gd->board_type < 2) { + return FPGA_INIT_STATE_V11; + } else { + return FPGA_INIT_STATE_V12; + } +} + + +int board_early_init_f (void) +{ + unsigned long CPC0_CR0Reg; + + /* + * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board) + */ + out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */ + out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */ + out_be32((void*)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */ + out_be32((void*)GPIO0_OR, 0); /* pull prg low */ + + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive + * IRQ 27 (EXT IRQ 2) CAN2; active low; level sensitive + * IRQ 28 (EXT IRQ 3) CAN3; active low; level sensitive + * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive + * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive + * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive + */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + + /* + * Setup GPIO pins (IRQ4/GPIO21 as GPIO) + */ + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00008000); + + /* + * Setup GPIO pins (CS6+CS7 as GPIO) + */ + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000); + + /* + * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us + */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ + + return 0; +} + +int misc_init_r (void) +{ + unsigned char *dst; + ulong len = sizeof(fpgadata); + int status; + int index; + int i; + unsigned int *ptr; + unsigned int *magic; + + /* + * On PCI-405 the environment is saved in eeprom! + * FPGA can be gzip compressed (malloc) and booted this late. + */ + + dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); + if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + printf ("GUNZIP ERROR - must RESET board to recover\n"); + do_reset (NULL, 0, 0, NULL); + } + + status = fpga_boot(dst, len); + if (status != 0) { + printf("\nFPGA: Booting failed "); + switch (status) { + case ERROR_FPGA_PRG_INIT_LOW: + printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_INIT_HIGH: + printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_DONE: + printf("(Timeout: DONE not high after programming FPGA)\n "); + break; + } + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("FPGA: %s\n", &(dst[index+1])); + index += len+3; + } + putc ('\n'); + /* delayed reboot */ + for (i=20; i>0; i--) { + printf("Rebooting in %2d seconds \r",i); + for (index=0;index<1000;index++) + udelay(1000); + } + putc ('\n'); + do_reset(NULL, 0, 0, NULL); + } + + puts("FPGA: "); + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("%s ", &(dst[index+1])); + index += len+3; + } + putc ('\n'); + + /* + * Reset FPGA via FPGA_DATA pin + */ + SET_FPGA(FPGA_PRG | FPGA_CLK); + udelay(1000); /* wait 1ms */ + SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); + udelay(1000); /* wait 1ms */ + + /* + * Check if magic for pci reconfig is written + */ + magic = (unsigned int *)0x00000004; + if (*magic == PCI_RECONFIG_MAGIC) { + /* + * Rewrite pci config regs (only after soft-reset with magic set) + */ + ptr = (unsigned int *)PCI_REGS_ADDR; + if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) { + puts("Restoring PCI Configurations Regs!\n"); + ptr = (unsigned int *)PCI_REGS_ADDR + 1; + for (i=0; i<0x40; i+=4) { + pci_write_config_dword(PCIDEVID_405GP, i, *ptr++); + } + } + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + + *magic = 0; /* clear pci reconfig magic again */ + } + + /* + * Decrease PLB latency timeout and reduce priority of the PCI bridge master + */ +#define PCI0_BRDGOPT1 0x4a + pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20); + + /* + * Enable fairness and high bus utilization + */ + mtdcr(PLB0_ACR, 0x98000000); + + free(dst); + return (0); +} + + +/* + * Check Board Identity: + */ +int checkboard (void) +{ + char str[64]; + int i = getenv_f("serial#", str, sizeof(str)); + + puts ("Board: "); + + if (i == -1) { + puts ("### No HW ID - assuming PCI405"); + } else { + puts (str); + } + + gd->board_type = board_revision(); + printf(" (Rev 1.%ld", gd->board_type); + + if (gd->board_type >= 2) { + unsigned long CPC0_CR0Reg; + unsigned long value; + + /* + * Setup GPIO pins (Trace/GPIO1 to GPIO) + */ + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg & ~0x08000000); + out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000); + out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000); + udelay(1000); /* wait some time before reading input */ + value = in_be32((void*)GPIO0_IR) & 0x40000000; /* get config bits */ + if (value) { + puts(", 33 MHz PCI"); + } else { + puts(", 66 MHz PCI"); + } + } + + puts(")\n"); + + return 0; +} + +/* ------------------------------------------------------------------------- */ +#define UART1_MCR 0xef600404 +int wpeeprom(int wp) +{ + int wp_state = wp; + + if (wp == 1) { + out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) & ~0x02); + } else if (wp == 0) { + out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) | 0x02); + } else { + if (in_8((void *)UART1_MCR) & 0x02) { + wp_state = 0; + } else { + wp_state = 1; + } + } + return wp_state; +} + +int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int wp = -1; + if (argc >= 2) { + if (argv[1][0] == '1') { + wp = 1; + } else if (argv[1][0] == '0') { + wp = 0; + } + } + + wp = wpeeprom(wp); + printf("EEPROM write protection %s\n", wp ? "ENABLED" : "DISABLED"); + return 0; +} + +U_BOOT_CMD( + wpeeprom, 2, 1, do_wpeeprom, + "Check/Enable/Disable I2C EEPROM write protection", + "wpeeprom\n" + " - check I2C EEPROM write protection state\n" + "wpeeprom 1\n" + " - enable I2C EEPROM write protection\n" + "wpeeprom 0\n" + " - disable I2C EEPROM write protection" +); diff --git a/roms/u-boot/board/esd/pci405/pci405.h b/roms/u-boot/board/esd/pci405/pci405.h new file mode 100644 index 00000000..a62c9c2b --- /dev/null +++ b/roms/u-boot/board/esd/pci405/pci405.h @@ -0,0 +1,16 @@ +/* + * (C) Copyright 2003 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PCI405_H_ +#define _PCI405_H_ + +#define PCI_REGS_LEN 0x100 +#define PCI_REGS_ADDR ((unsigned long)0x01000000 - PCI_REGS_LEN) + +#define PCI_RECONFIG_MAGIC 0x07081967 + +#endif /* _PCI405_H_ */ diff --git a/roms/u-boot/board/esd/pci405/writeibm.S b/roms/u-boot/board/esd/pci405/writeibm.S new file mode 100644 index 00000000..03eaf97b --- /dev/null +++ b/roms/u-boot/board/esd/pci405/writeibm.S @@ -0,0 +1,205 @@ +/* + * SPDX-License-Identifier: GPL-2.0 IBM-pibs + */ +/*----------------------------------------------------------------------------- */ +/* Function: ext_bus_cntlr_init */ +/* Description: Initializes the External Bus Controller for the external */ +/* peripherals. IMPORTANT: For pass1 this code must run from */ +/* cache since you can not reliably change a peripheral banks */ +/* timing register (pbxap) while running code from that bank. */ +/* For ex., since we are running from ROM on bank 0, we can NOT */ +/* execute the code that modifies bank 0 timings from ROM, so */ +/* we run it from cache. */ +/* Bank 0 - Flash and SRAM */ +/* Bank 1 - NVRAM/RTC */ +/* Bank 2 - Keyboard/Mouse controller */ +/* Bank 3 - IR controller */ +/* Bank 4 - not used */ +/* Bank 5 - not used */ +/* Bank 6 - not used */ +/* Bank 7 - FPGA registers */ +/*----------------------------------------------------------------------------- */ +#include + +#include +#include + +#include +#include + + + .globl write_without_sync +write_without_sync: + /* + * Write one values to host via pci busmastering + * ptr = 0xc0000000 -> 0x01000000 (PCI) + * *ptr = 0x01234567; + */ + addi r31,0,0 + lis r31,0xc000 + +start1: + lis r0,0x0123 + ori r0,r0,0x4567 + stw r0,0(r31) + + /* + * Read one value back + * ptr = (volatile unsigned long *)addr; + * val = *ptr; + */ + + lwz r0,0(r31) + + /* + * One pci config write + * ibmPciConfigWrite(0x2e, 2, 0x1234); + */ + /* subsystem id */ + + li r4,0x002C + oris r4,r4,0x8000 + lis r3,0xEEC0 + stwbrx r4,0,r3 + + li r5,0x1234 + ori r3,r3,0x4 + stwbrx r5,0,r3 + + b start1 + + blr /* never reached !!!! */ + + .globl write_with_sync +write_with_sync: + /* + * Write one values to host via pci busmastering + * ptr = 0xc0000000 -> 0x01000000 (PCI) + * *ptr = 0x01234567; + */ + addi r31,0,0 + lis r31,0xc000 + +start2: + lis r0,0x0123 + ori r0,r0,0x4567 + stw r0,0(r31) + + /* + * Read one value back + * ptr = (volatile unsigned long *)addr; + * val = *ptr; + */ + + lwz r0,0(r31) + + /* + * One pci config write + * ibmPciConfigWrite(0x2e, 2, 0x1234); + */ + /* subsystem id */ + + li r4,0x002C + oris r4,r4,0x8000 + lis r3,0xEEC0 + stwbrx r4,0,r3 + sync + + li r5,0x1234 + ori r3,r3,0x4 + stwbrx r5,0,r3 + sync + + b start2 + + blr /* never reached !!!! */ + + .globl write_with_less_sync +write_with_less_sync: + /* + * Write one values to host via pci busmastering + * ptr = 0xc0000000 -> 0x01000000 (PCI) + * *ptr = 0x01234567; + */ + addi r31,0,0 + lis r31,0xc000 + +start2b: + lis r0,0x0123 + ori r0,r0,0x4567 + stw r0,0(r31) + + /* + * Read one value back + * ptr = (volatile unsigned long *)addr; + * val = *ptr; + */ + + lwz r0,0(r31) + + /* + * One pci config write + * ibmPciConfigWrite(0x2e, 2, 0x1234); + */ + /* subsystem id */ + + li r4,0x002C + oris r4,r4,0x8000 + lis r3,0xEEC0 + stwbrx r4,0,r3 + sync + + li r5,0x1234 + ori r3,r3,0x4 + stwbrx r5,0,r3 +/* sync */ + + b start2b + + blr /* never reached !!!! */ + + .globl write_with_more_sync +write_with_more_sync: + /* + * Write one values to host via pci busmastering + * ptr = 0xc0000000 -> 0x01000000 (PCI) + * *ptr = 0x01234567; + */ + addi r31,0,0 + lis r31,0xc000 + +start3: + lis r0,0x0123 + ori r0,r0,0x4567 + stw r0,0(r31) + sync + + /* + * Read one value back + * ptr = (volatile unsigned long *)addr; + * val = *ptr; + */ + + lwz r0,0(r31) + sync + + /* + * One pci config write + * ibmPciConfigWrite(0x2e, 2, 0x1234); + */ + /* subsystem id (PCIC0_SBSYSVID)*/ + + li r4,0x002C + oris r4,r4,0x8000 + lis r3,0xEEC0 + stwbrx r4,0,r3 + sync + + li r5,0x1234 + ori r3,r3,0x4 + stwbrx r5,0,r3 + sync + + b start3 + + blr /* never reached !!!! */ -- cgit v1.2.3