save listing off ; kein Listing über diesen File ;**************************************************************************** ;* * ;* AS 1.41 - Datei REGST9.INC * ;* * ;* Sinn : enthält SFR-, Makro- und Adreßdefinitionen für die ST9-Familie * ;* * ;* letzte Änderungen : 6. 2.1997 * ;* * ;**************************************************************************** ifndef regst9inc ; verhindert Mehrfacheinbindung regst9inc equ 1 if (MOMCPUNAME<>"ST9020")&&(MOMCPUNAME<>"ST9030")&&(MOMCPUNAME<>"ST9040")&&(MOMCPUNAME<>"ST9050") fatal "Falscher Prozessortyp eingestellt: nur ST9020,ST9030,ST9040 oder ST9050 erlaubt!" endif if MOMPASS=1 message "ST9-SFR-Definitionen (C) 1997 Alfred Arnold" endif ;---------------------------------------------------------------------------- ; Registerbänke __CNT set 0 rept 16 BK{"\{__CNT}"}0 equ __CNT*2 BK{"\{__CNT}"}1 equ __CNT*2+1 __CNT set __CNT+1 endm BK_SYS equ BKE0 ; Group system definition BK_F equ BKF0 ; page register definition ;---------------------------------------------------------------------------- ; Definition eines Bits: ; dies nutzt die interne Definition von Bitsymbolen aus: rrrrbbbi __defbit macro NAME,REG,BITPOS NAME bit ((REG&15)<<4)+(BITPOS<<1) {"NAME"}m equ 1<"ST9020" AD0_PG equ 63 ; A/D converter registers page AD1_PG equ 62 ; second A/D unit AD_D0R reg R240 ; Channel 0 data register AD_D1R reg R241 ; Channel 1 data register AD_D2R reg R242 ; Channel 2 data register AD_D3R reg R243 ; Channel 3 data register AD_D4R reg R244 ; Channel 4 data register AD_D5R reg R245 ; Channel 5 data register AD_D6R reg R246 ; Channel 6 data register AD_D7R reg R247 ; Channel 7 data register AD_LT6R reg R248 ; Channel 6 lower threshold register AD_LT7R reg R249 ; Channel 7 lower threshold register AD_UT6R reg R250 ; Channel 6 upper threshold register AD_UT7R reg R251 ; Channel 7 upper threshold register AD_CRR reg R252 ; Compare result register __defbit AD_c6l,AD_CRR,4 ; Compare channel 6 lower bit __defbit AD_c7l,AD_CRR,5 ; Compare channel 7 lower bit __defbit AD_c6u,AD_CRR,6 ; Compare channel 6 upper bit __defbit AD_c7u,AD_CRR,7 ; Compare channel 7 upper bit AD_CLR reg R253 ; Control logic register __defbit AD_st,AD_CLR,0 ; start/stop bit __defbit AD_cont,AD_CLR,1 ; Continuous mode __defbit AD_pow,AD_CLR,2 ; power up/down control __defbit AD_intg,AD_CLR,3 ; internal trigger __defbit AD_extg,AD_CLR,4 ; External trigger sch equ 0E0h ; scan channel selection mask AD_ICR reg R254 ; interrupt control register __defbit AD_awdi,AD_ICR,4 ; analog watch-dog interrupt __defbit AD_eci,AD_ICR,5 ; End of count interrupt __defbit AD_awd,AD_ICR,6 ; analog watch-dog pending flag __defbit AD_ecv,AD_ICR,7 ; End of conversion pending flag AD_prl equ 07h ; priority level mask AD_IVR reg R255 ; interrupt vector register endif ;---------------------------------------------------------------------------- ; Serielle Schnittstelle SCI1_PG equ 24 ; SCI1 control registers page SCI2_PG equ 25 ; SCI2 control registers page SCI3_PG equ 26 ; SCI3 control registers page SCI4_PG equ 27 ; SCI4 control registers page S_RDCPR reg R240 ; receive DMA counter pointer register S_RDAPR reg R241 ; receive DMA address pointer register S_TDCPR reg R242 ; transmit DMA counter pointer register S_TDAPR reg R243 ; transmit DMA address pointer register S_IVR reg R244 ; interrupt vector register S_ACR reg R245 ; address compare register S_IMR reg R246 ; interrupt mask register __defbit S_txdi,S_IMR,0 ; transmitter data interrupt __defbit S_rxdi,S_IMR,1 ; receiver data interrupt __defbit S_rxb,S_IMR,2 ; receiver break __defbit S_rxa,S_IMR,3 ; receiver address __defbit S_rxe,S_IMR,4 ; receiver error __defbit S_txeob,S_IMR,5 ; transmit end of block __defbit S_rxeob,S_IMR,6 ; receive end of block __defbit S_hsn,S_IMR,7 ; Holding or shift register empty. S_ISR reg R247 ; interrupt status register __defbit S_txsem,S_ISR,0 ; transmit shift register empty __defbit S_txhem,S_ISR,1 ; transmit hold register empty __defbit S_rxdp,S_ISR,2 ; received data pending bit __defbit S_rxbp,S_ISR,3 ; received break pending bit __defbit S_rxap,S_ISR,4 ; received address pending bit __defbit S_pe,S_ISR,5 ; parity error pending bit __defbit S_fe,S_ISR,6 ; framing error pending bit __defbit S_oe,S_ISR,7 ; overrun error pending bit S_RXBR reg R248 ; receive buffer register S_TXBR reg R248 ; transmit buffer register S_IDPR reg R249 ; interrupt/DMA priority register __defbit S_txd,S_IDPR,3 ; transmitter DMA __defbit S_rxd,S_IDPR,4 ; receiver DMA __defbit S_sa,S_IDPR,5 ; set address __defbit S_sb,S_IDPR,6 ; set break __defbit S_amen,S_IDPR,7 ; address mode enable S_pri equ 07h ; interrupt/DMA priority mask S_CHCR reg R250 ; Character configuration register wl5 equ 000h ; 5 bits data word mask wl6 equ 001h ; 6 bits data word mask wl7 equ 002h ; 7 bits data word mask wl8 equ 003h ; 8 bits data word mask sb10 equ 000h ; 1.0 stop bit mask sb15 equ 004h ; 1.5 stop bit mask sb20 equ 008h ; 2.0 stop bit mask sb25 equ 00Ch ; 2.5 stop bit mask ab equ 010h ; address bit insertion mask pen equ 020h ; parity enable mask ep equ 040h ; Even parity mask oddp equ 000h ; odd parity mask am equ 080h ; address mode mask S_CCR reg R251 ; Clock configuration register __defbit S_stpen,S_CCR,0 ; stick parity enable __defbit S_lben,S_CCR,1 ; loop back enable __defbit S_aen,S_CCR,2 ; auto echo enable __defbit S_cd,S_CCR,3 ; Clock divider __defbit S_xbrg,S_CCR,4 ; External baud rate generator source __defbit S_xrx,S_CCR,5 ; External receiver source __defbit S_oclk,S_CCR,6 ; output clock selection __defbit S_txclk,S_CCR,7 ; transmit clock selection S_BRGR reg RR252 ; baud rate generator register S_BRGHR reg R252 ; baud rate generator reg. high S_BRGLR reg R253 ; baud rate generator reg. low ;---------------------------------------------------------------------------- ; Security Register: SEC_PG equ 59 ; Security register page SECR reg R255 __defbit tlck,SECR,0 ; test lock bit __defbit wf1,SECR,1 ; write fuse 1 bit __defbit hlck,SECR,2 ; hardware lock bit __defbit wf2,SECR,3 ; write fuse 2 bit __defbit f2tst,SECR,4 ; select fuse 2 bit __defbit slck,SECR,7 ; software lock bit ;---------------------------------------------------------------------------- endif restore ; Listing wieder an