From 333b605b2afd472b823aeda0adf0e8b1ea9843c0 Mon Sep 17 00:00:00 2001 From: fishsoupisgood Date: Mon, 27 May 2019 02:41:51 +0100 Subject: initial commit from asl-1.41r8.tar.gz --- tests/t_32/asflags | 0 tests/t_32/t_32.asm | 39 +++++++++++++++++++++++++++++++++++++++ tests/t_32/t_32.doc | 6 ++++++ tests/t_32/t_32.ori | Bin 0 -> 134 bytes 4 files changed, 45 insertions(+) create mode 100644 tests/t_32/asflags create mode 100644 tests/t_32/t_32.asm create mode 100644 tests/t_32/t_32.doc create mode 100644 tests/t_32/t_32.ori (limited to 'tests/t_32') diff --git a/tests/t_32/asflags b/tests/t_32/asflags new file mode 100644 index 0000000..e69de29 diff --git a/tests/t_32/t_32.asm b/tests/t_32/t_32.asm new file mode 100644 index 0000000..d7738e5 --- /dev/null +++ b/tests/t_32/t_32.asm @@ -0,0 +1,39 @@ + cpu 68340 + supmode on + include reg683xx.inc + page 0 + + lpstop #$55aa + + link a6,#10 + link.l a6,#10 + + bgnd + +Test1 tbls.b (a4),d5 +Test2: tbls.w 30(a6),d1 + Test3: tbls.l 20(a4,d5*1),d6 + Test4: tblsn.b (a4),d5 + tblsn.w 30(a6),d1 + tblsn.l 20(a4,d5*1),d6 + tblu.b (a4),d5 + tblu.w 30(a6),d1 + tblu.l 20(a4,d5*1),d6 + tblun.b (a4),d5 + tblun.w 30(a6),d1 + tblun.l 20(a4,d5*1),d6 + + tbls.b d1:d2,d3 + tbls.w d2:d3,d4 + tbls.l d3:d4,d5 + tblsn.b d1:d2,d3 + tblsn.w d2:d3,d4 + tblsn.l d3:d4,d5 + tblu.b d1:d2,d3 + tblu.w d2:d3,d4 + tblu.l d3:d4,d5 + tblun.b d1:d2,d3 + tblun.w d2:d3,d4 + tblun.l d3:d4,d5 + + move.l (d0.l),d0 diff --git a/tests/t_32/t_32.doc b/tests/t_32/t_32.doc new file mode 100644 index 0000000..e069ffe --- /dev/null +++ b/tests/t_32/t_32.doc @@ -0,0 +1,6 @@ ++-------------------------- Test Application 32 -----------------------------+ +| | +| This is a (synthetic) test of the CPU32's extensions to the 680x0 | +| basic instruction set. | +| | ++----------------------------------------------------------------------------+ diff --git a/tests/t_32/t_32.ori b/tests/t_32/t_32.ori new file mode 100644 index 0000000..1413840 Binary files /dev/null and b/tests/t_32/t_32.ori differ -- cgit v1.2.3