/**CFile**************************************************************** FileName [fraigMan.c] PackageName [FRAIG: Functionally reduced AND-INV graphs.] Synopsis [Implementation of the FRAIG manager.] Author [Alan Mishchenko ] Affiliation [UC Berkeley] Date [Ver. 2.0. Started - October 1, 2004] Revision [$Id: fraigMan.c,v 1.11 2005/07/08 01:01:31 alanmi Exp $] ***********************************************************************/ #include "fraigInt.h" ABC_NAMESPACE_IMPL_START //////////////////////////////////////////////////////////////////////// /// DECLARATIONS /// //////////////////////////////////////////////////////////////////////// abctime timeSelect; abctime timeAssign; //////////////////////////////////////////////////////////////////////// /// FUNCTION DEFINITIONS /// //////////////////////////////////////////////////////////////////////// /**Function************************************************************* Synopsis [Sets the default parameters of the package.] Description [This set of parameters is tuned for equivalence checking.] SideEffects [] SeeAlso [] ***********************************************************************/ void Prove_ParamsSetDefault( Prove_Params_t * pParams ) { // clean the parameter structure memset( pParams, 0, sizeof(Prove_Params_t) ); // general parameters pParams->fUseFraiging = 1; // enables fraiging pParams->fUseRewriting = 1; // enables rewriting pParams->fUseBdds = 0; // enables BDD construction when other methods fail pParams->fVerbose = 0; // prints verbose stats // iterations pParams->nItersMax = 6; // the number of iterations // mitering pParams->nMiteringLimitStart = 5000; // starting mitering limit pParams->nMiteringLimitMulti = 2.0; // multiplicative coefficient to increase the limit in each iteration // rewriting (currently not used) pParams->nRewritingLimitStart = 3; // the number of rewriting iterations pParams->nRewritingLimitMulti = 1.0; // multiplicative coefficient to increase the limit in each iteration // fraiging pParams->nFraigingLimitStart = 2; // starting backtrack(conflict) limit pParams->nFraigingLimitMulti = 8.0; // multiplicative coefficient to increase the limit in each iteration // last-gasp BDD construction pParams->nBddSizeLimit = 1000000; // the number of BDD nodes when construction is aborted pParams->fBddReorder = 1; // enables dynamic BDD variable reordering // last-gasp mitering // pParams->nMiteringLimitLast = 1000000; // final mitering limit pParams->nMiteringLimitLast = 0; // final mitering limit // global SAT solver limits pParams->nTotalBacktrackLimit = 0; // global limit on the number of backtracks pParams->nTotalInspectLimit = 0; // global limit on the number of clause inspects // pParams->nTotalInspectLimit = 100000000; // global limit on the number of clause inspects } /**Function************************************************************* Synopsis [Prints out the current values of CEC engine parameters.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ void Prove_ParamsPrint( Prove_Params_t * pParams ) { printf( "CEC enging parameters:\n" ); printf( "Fraiging enabled: %s\n", pParams->fUseFraiging? "yes":"no" ); printf( "Rewriting enabled: %s\n", pParams->fUseRewriting? "yes":"no" ); printf( "BDD construction enabled: %s\n", pParams->fUseBdds? "yes":"no" ); printf( "Verbose output enabled: %s\n", pParams->fVerbose? "yes":"no" ); printf( "Solver iterations: %d\n", pParams->nItersMax ); printf( "Starting mitering limit: %d\n", pParams->nMiteringLimitStart ); printf( "Multiplicative coeficient for mitering: %.2f\n", pParams->nMiteringLimitMulti ); printf( "Starting number of rewriting iterations: %d\n", pParams->nRewritingLimitStart ); printf( "Multiplicative coeficient for rewriting: %.2f\n", pParams->nRewritingLimitMulti ); printf( "Starting number of conflicts in fraiging: %.2f\n", pParams->nFraigingLimitMulti ); printf( "Multiplicative coeficient for fraiging: %.2f\n", pParams->nRewritingLimitMulti ); printf( "BDD size limit for bailing out: %d\n", pParams->nBddSizeLimit ); printf( "BDD reordering enabled: %s\n", pParams->fBddReorder? "yes":"no" ); printf( "Last-gasp mitering limit: %d\n", pParams->nMiteringLimitLast ); printf( "Total conflict limit: %d\n", (int)pParams->nTotalBacktrackLimit ); printf( "Total inspection limit: %d\n", (int)pParams->nTotalInspectLimit ); printf( "Parameter dump complete.\n" ); } /**Function************************************************************* Synopsis [Sets the default parameters of the package.] Description [This set of parameters is tuned for equivalence checking.] SideEffects [] SeeAlso [] ***********************************************************************/ void Fraig_ParamsSetDefault( Fraig_Params_t * pParams ) { memset( pParams, 0, sizeof(Fraig_Params_t) ); pParams->nPatsRand = FRAIG_PATTERNS_RANDOM; // the number of words of random simulation info pParams->nPatsDyna = FRAIG_PATTERNS_DYNAMIC; // the number of words of dynamic simulation info pParams->nBTLimit = 99; // the max number of backtracks to perform pParams->nSeconds = 20; // the max number of seconds to solve the miter pParams->fFuncRed = 1; // performs only one level hashing pParams->fFeedBack = 1; // enables solver feedback pParams->fDist1Pats = 1; // enables distance-1 patterns pParams->fDoSparse = 0; // performs equiv tests for sparse functions pParams->fChoicing = 0; // enables recording structural choices pParams->fTryProve = 1; // tries to solve the final miter pParams->fVerbose = 0; // the verbosiness flag pParams->fVerboseP = 0; // the verbose flag for reporting the proof pParams->fInternal = 0; // the flag indicates the internal run pParams->nConfLimit = 0; // the limit on the number of conflicts pParams->nInspLimit = 0; // the limit on the number of inspections } /**Function************************************************************* Synopsis [Sets the default parameters of the package.] Description [This set of parameters is tuned for complete FRAIGing.] SideEffects [] SeeAlso [] ***********************************************************************/ void Fraig_ParamsSetDefaultFull( Fraig_Params_t * pParams ) { memset( pParams, 0, sizeof(Fraig_Params_t) ); pParams->nPatsRand = FRAIG_PATTERNS_RANDOM; // the number of words of random simulation info pParams->nPatsDyna = FRAIG_PATTERNS_DYNAMIC; // the number of words of dynamic simulation info pParams->nBTLimit = -1; // the max number of backtracks to perform pParams->nSeconds = 20; // the max number of seconds to solve the miter pParams->fFuncRed = 1; // performs only one level hashing pParams->fFeedBack = 1; // enables solver feedback pParams->fDist1Pats = 1; // enables distance-1 patterns pParams->fDoSparse = 1; // performs equiv tests for sparse functions pParams->fChoicing = 0; // enables recording structural choices pParams->fTryProve = 0; // tries to solve the final miter pParams->fVerbose = 0; // the verbosiness flag pParams->fVerboseP = 0; // the verbose flag for reporting the proof pParams->fInternal = 0; // the flag indicates the internal run pParams->nConfLimit = 0; // the limit on the number of conflicts pParams->nInspLimit = 0; // the limit on the number of inspections } /**Function************************************************************* Synopsis [Creates the new FRAIG manager.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ Fraig_Man_t * Fraig_ManCreate( Fraig_Params_t * pParams ) { Fraig_Params_t Params; Fraig_Man_t * p; // set the random seed for simulation // srand( 0xFEEDDEAF ); // srand( 0xDEADCAFE ); Aig_ManRandom( 1 ); // set parameters for equivalence checking if ( pParams == NULL ) Fraig_ParamsSetDefault( pParams = &Params ); // adjust the amount of simulation info if ( pParams->nPatsRand < 128 ) pParams->nPatsRand = 128; if ( pParams->nPatsRand > 32768 ) pParams->nPatsRand = 32768; if ( pParams->nPatsDyna < 128 ) pParams->nPatsDyna = 128; if ( pParams->nPatsDyna > 32768 ) pParams->nPatsDyna = 32768; // if reduction is not performed, allocate minimum simulation info if ( !pParams->fFuncRed ) pParams->nPatsRand = pParams->nPatsDyna = 128; // start the manager p = ABC_ALLOC( Fraig_Man_t, 1 ); memset( p, 0, sizeof(Fraig_Man_t) ); // set the default parameters p->nWordsRand = FRAIG_NUM_WORDS( pParams->nPatsRand ); // the number of words of random simulation info p->nWordsDyna = FRAIG_NUM_WORDS( pParams->nPatsDyna ); // the number of patterns for dynamic simulation info p->nBTLimit = pParams->nBTLimit; // -1 means infinite backtrack limit p->nSeconds = pParams->nSeconds; // the timeout for the final miter p->fFuncRed = pParams->fFuncRed; // enables functional reduction (otherwise, only one-level hashing is performed) p->fFeedBack = pParams->fFeedBack; // enables solver feedback (the use of counter-examples in simulation) p->fDist1Pats = pParams->fDist1Pats; // enables solver feedback (the use of counter-examples in simulation) p->fDoSparse = pParams->fDoSparse; // performs equivalence checking for sparse functions (whose sim-info is 0) p->fChoicing = pParams->fChoicing; // disable accumulation of structural choices (keeps only the first choice) p->fTryProve = pParams->fTryProve; // disable accumulation of structural choices (keeps only the first choice) p->fVerbose = pParams->fVerbose; // disable verbose output p->fVerboseP = pParams->fVerboseP; // disable verbose output p->nInspLimit = pParams->nInspLimit; // the limit on the number of inspections // start memory managers p->mmNodes = Fraig_MemFixedStart( sizeof(Fraig_Node_t) ); p->mmSims = Fraig_MemFixedStart( sizeof(unsigned) * (p->nWordsRand + p->nWordsDyna) ); // allocate node arrays p->vInputs = Fraig_NodeVecAlloc( 1000 ); // the array of primary inputs p->vOutputs = Fraig_NodeVecAlloc( 1000 ); // the array of primary outputs p->vNodes = Fraig_NodeVecAlloc( 1000 ); // the array of internal nodes // start the tables p->pTableS = Fraig_HashTableCreate( 1000 ); // hashing by structure p->pTableF = Fraig_HashTableCreate( 1000 ); // hashing by function p->pTableF0 = Fraig_HashTableCreate( 1000 ); // hashing by function (for sparse functions) // create the constant node p->pConst1 = Fraig_NodeCreateConst( p ); // initialize SAT solver feedback data structures Fraig_FeedBackInit( p ); // initialize other variables p->vProj = Msat_IntVecAlloc( 10 ); p->nTravIds = 1; p->nTravIds2 = 1; return p; } /**Function************************************************************* Synopsis [Deallocates the mapping manager.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ void Fraig_ManFree( Fraig_Man_t * p ) { int i; if ( p->fVerbose ) { if ( p->fChoicing ) Fraig_ManReportChoices( p ); Fraig_ManPrintStats( p ); // Fraig_TablePrintStatsS( p ); // Fraig_TablePrintStatsF( p ); // Fraig_TablePrintStatsF0( p ); } for ( i = 0; i < p->vNodes->nSize; i++ ) if ( p->vNodes->pArray[i]->vFanins ) { Fraig_NodeVecFree( p->vNodes->pArray[i]->vFanins ); p->vNodes->pArray[i]->vFanins = NULL; } if ( p->vInputs ) Fraig_NodeVecFree( p->vInputs ); if ( p->vNodes ) Fraig_NodeVecFree( p->vNodes ); if ( p->vOutputs ) Fraig_NodeVecFree( p->vOutputs ); if ( p->pTableS ) Fraig_HashTableFree( p->pTableS ); if ( p->pTableF ) Fraig_HashTableFree( p->pTableF ); if ( p->pTableF0 ) Fraig_HashTableFree( p->pTableF0 ); if ( p->pSat ) Msat_SolverFree( p->pSat ); if ( p->vProj ) Msat_IntVecFree( p->vProj ); if ( p->vCones ) Fraig_NodeVecFree( p->vCones ); if ( p->vPatsReal ) Msat_IntVecFree( p->vPatsReal ); if ( p->pModel ) ABC_FREE( p->pModel ); Fraig_MemFixedStop( p->mmNodes, 0 ); Fraig_MemFixedStop( p->mmSims, 0 ); if ( p->pSuppS ) { ABC_FREE( p->pSuppS[0] ); ABC_FREE( p->pSuppS ); } if ( p->pSuppF ) { ABC_FREE( p->pSuppF[0] ); ABC_FREE( p->pSuppF ); } ABC_FREE( p->ppOutputNames ); ABC_FREE( p->ppInputNames ); ABC_FREE( p ); } /**Function************************************************************* Synopsis [Prepares the SAT solver to run on the two nodes.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ void Fraig_ManCreateSolver( Fraig_Man_t * p ) { extern abctime timeSelect; extern abctime timeAssign; assert( p->pSat == NULL ); // allocate data for SAT solving p->pSat = Msat_SolverAlloc( 500, 1, 1, 1, 1, 0 ); p->vVarsInt = Msat_SolverReadConeVars( p->pSat ); p->vAdjacents = Msat_SolverReadAdjacents( p->pSat ); p->vVarsUsed = Msat_SolverReadVarsUsed( p->pSat ); timeSelect = 0; timeAssign = 0; } /**Function************************************************************* Synopsis [Deallocates the mapping manager.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ void Fraig_ManPrintStats( Fraig_Man_t * p ) { double nMemory; nMemory = ((double)(p->vInputs->nSize + p->vNodes->nSize) * (sizeof(Fraig_Node_t) + sizeof(unsigned)*(p->nWordsRand + p->nWordsDyna) /*+ p->nSuppWords*sizeof(unsigned)*/))/(1<<20); printf( "Words: Random = %d. Dynamic = %d. Used = %d. Memory = %0.2f MB.\n", p->nWordsRand, p->nWordsDyna, p->iWordPerm, nMemory ); printf( "Proof = %d. Counter-example = %d. Fail = %d. FailReal = %d. Zero = %d.\n", p->nSatProof, p->nSatCounter, p->nSatFails, p->nSatFailsReal, p->nSatZeros ); printf( "Nodes: Final = %d. Total = %d. Mux = %d. (Exor = %d.) ClaVars = %d.\n", Fraig_CountNodes(p,0), p->vNodes->nSize, Fraig_ManCountMuxes(p), Fraig_ManCountExors(p), p->nVarsClauses ); if ( p->pSat ) Msat_SolverPrintStats( p->pSat ); Fraig_PrintTime( "AIG simulation ", p->timeSims ); Fraig_PrintTime( "AIG traversal ", p->timeTrav ); Fraig_PrintTime( "Solver feedback ", p->timeFeed ); Fraig_PrintTime( "SAT solving ", p->timeSat ); Fraig_PrintTime( "Network update ", p->timeToNet ); Fraig_PrintTime( "TOTAL RUNTIME ", p->timeTotal ); if ( p->time1 > 0 ) { Fraig_PrintTime( "time1", p->time1 ); } if ( p->time2 > 0 ) { Fraig_PrintTime( "time2", p->time2 ); } if ( p->time3 > 0 ) { Fraig_PrintTime( "time3", p->time3 ); } if ( p->time4 > 0 ) { Fraig_PrintTime( "time4", p->time4 ); } // ABC_PRT( "Selection ", timeSelect ); // ABC_PRT( "Assignment", timeAssign ); fflush( stdout ); } /**Function************************************************************* Synopsis [Allocates simulation information for all nodes.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ Fraig_NodeVec_t * Fraig_UtilInfoAlloc( int nSize, int nWords, int fClean ) { Fraig_NodeVec_t * vInfo; unsigned * pUnsigned; int i; assert( nSize > 0 && nWords > 0 ); vInfo = Fraig_NodeVecAlloc( nSize ); pUnsigned = ABC_ALLOC( unsigned, nSize * nWords ); vInfo->pArray[0] = (Fraig_Node_t *)pUnsigned; if ( fClean ) memset( pUnsigned, 0, sizeof(unsigned) * nSize * nWords ); for ( i = 1; i < nSize; i++ ) vInfo->pArray[i] = (Fraig_Node_t *)(((unsigned *)vInfo->pArray[i-1]) + nWords); vInfo->nSize = nSize; return vInfo; } /**Function************************************************************* Synopsis [Returns simulation info of all nodes.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ Fraig_NodeVec_t * Fraig_ManGetSimInfo( Fraig_Man_t * p ) { Fraig_NodeVec_t * vInfo; Fraig_Node_t * pNode; unsigned * pUnsigned; int nRandom, nDynamic; int i, k, nWords; nRandom = Fraig_ManReadPatternNumRandom( p ); nDynamic = Fraig_ManReadPatternNumDynamic( p ); nWords = nRandom / 32 + nDynamic / 32; vInfo = Fraig_UtilInfoAlloc( p->vNodes->nSize, nWords, 0 ); for ( i = 0; i < p->vNodes->nSize; i++ ) { pNode = p->vNodes->pArray[i]; assert( i == pNode->Num ); pUnsigned = (unsigned *)vInfo->pArray[i]; for ( k = 0; k < nRandom / 32; k++ ) pUnsigned[k] = pNode->puSimR[k]; for ( k = 0; k < nDynamic / 32; k++ ) pUnsigned[nRandom / 32 + k] = pNode->puSimD[k]; } return vInfo; } /**Function************************************************************* Synopsis [Returns 1 if A v B is always true based on the siminfo.] Description [A v B is always true iff A' * B' is always false.] SideEffects [] SeeAlso [] ***********************************************************************/ int Fraig_ManCheckClauseUsingSimInfo( Fraig_Man_t * p, Fraig_Node_t * pNode1, Fraig_Node_t * pNode2 ) { int fCompl1, fCompl2, i; fCompl1 = 1 ^ Fraig_IsComplement(pNode1) ^ Fraig_Regular(pNode1)->fInv; fCompl2 = 1 ^ Fraig_IsComplement(pNode2) ^ Fraig_Regular(pNode2)->fInv; pNode1 = Fraig_Regular(pNode1); pNode2 = Fraig_Regular(pNode2); assert( pNode1 != pNode2 ); // check the simulation info if ( fCompl1 && fCompl2 ) { for ( i = 0; i < p->nWordsRand; i++ ) if ( ~pNode1->puSimR[i] & ~pNode2->puSimR[i] ) return 0; for ( i = 0; i < p->iWordStart; i++ ) if ( ~pNode1->puSimD[i] & ~pNode2->puSimD[i] ) return 0; return 1; } if ( !fCompl1 && fCompl2 ) { for ( i = 0; i < p->nWordsRand; i++ ) if ( pNode1->puSimR[i] & ~pNode2->puSimR[i] ) return 0; for ( i = 0; i < p->iWordStart; i++ ) if ( pNode1->puSimD[i] & ~pNode2->puSimD[i] ) return 0; return 1; } if ( fCompl1 && !fCompl2 ) { for ( i = 0; i < p->nWordsRand; i++ ) if ( ~pNode1->puSimR[i] & pNode2->puSimR[i] ) return 0; for ( i = 0; i < p->iWordStart; i++ ) if ( ~pNode1->puSimD[i] & pNode2->puSimD[i] ) return 0; return 1; } // if ( fCompl1 && fCompl2 ) { for ( i = 0; i < p->nWordsRand; i++ ) if ( pNode1->puSimR[i] & pNode2->puSimR[i] ) return 0; for ( i = 0; i < p->iWordStart; i++ ) if ( pNode1->puSimD[i] & pNode2->puSimD[i] ) return 0; return 1; } } /**Function************************************************************* Synopsis [Adds clauses to the solver.] Description [This procedure is used to add external clauses to the solver. The clauses are given by sets of nodes. Each node stands for one literal. If the node is complemented, the literal is negated.] SideEffects [] SeeAlso [] ***********************************************************************/ void Fraig_ManAddClause( Fraig_Man_t * p, Fraig_Node_t ** ppNodes, int nNodes ) { Fraig_Node_t * pNode; int i, fComp, RetValue; if ( p->pSat == NULL ) Fraig_ManCreateSolver( p ); // create four clauses Msat_IntVecC
/**
 * \file
 *
 * \brief Component description for PAC
 *
 * Copyright (c) 2018 Microchip Technology Inc.
 *
 * \asf_license_start
 *
 * \page License
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License"); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the Licence at
 * 
 * http://www.apache.org/licenses/LICENSE-2.0
 * 
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 * \asf_license_stop
 *
 */

#ifndef _SAML22_PAC_COMPONENT_
#define _SAML22_PAC_COMPONENT_

/* ========================================================================== */
/**  SOFTWARE API DEFINITION FOR PAC */
/* ========================================================================== */
/** \addtogroup SAML22_PAC Peripheral Access Controller */
/*@{*/

#define PAC_U2120
#define REV_PAC                     0x110

/* -------- PAC_WRCTRL : (PAC Offset: 0x00) (R/W 32) Write control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t PERID:16;         /*!< bit:  0..15  Peripheral identifier              */
    uint32_t KEY:8;            /*!< bit: 16..23  Peripheral access control key      */
    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
  } bit;                       /*!< Structure used for bit  access                  */
  uint32_t reg;                /*!< Type      used for register access              */
} PAC_WRCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define PAC_WRCTRL_OFFSET           0x00         /**< \brief (PAC_WRCTRL offset) Write control */
#define PAC_WRCTRL_RESETVALUE       _U_(0x00000000) /**< \brief (PAC_WRCTRL reset_value) Write control */

#define PAC_WRCTRL_PERID_Pos        0            /**< \brief (PAC_WRCTRL) Peripheral identifier */
#define PAC_WRCTRL_PERID_Msk        (_U_(0xFFFF) << PAC_WRCTRL_PERID_Pos)
#define PAC_WRCTRL_PERID(value)     (PAC_WRCTRL_PERID_Msk & ((value) << PAC_WRCTRL_PERID_Pos))
#define PAC_WRCTRL_KEY_Pos          16           /**< \brief (PAC_WRCTRL) Peripheral access control key */
#define PAC_WRCTRL_KEY_Msk          (_U_(0xFF) << PAC_WRCTRL_KEY_Pos)
#define PAC_WRCTRL_KEY(value)       (PAC_WRCTRL_KEY_Msk & ((value) << PAC_WRCTRL_KEY_Pos))
#define   PAC_WRCTRL_KEY_OFF_Val          _U_(0x0)   /**< \brief (PAC_WRCTRL) No action */
#define   PAC_WRCTRL_KEY_CLR_Val          _U_(0x1)   /**< \brief (PAC_WRCTRL) Clear protection */
#define   PAC_WRCTRL_KEY_SET_Val          _U_(0x2)   /**< \brief (PAC_WRCTRL) Set protection */
#define   PAC_WRCTRL_KEY_SETLCK_Val       _U_(0x3)   /**< \brief (PAC_WRCTRL) Set and lock protection */
#define PAC_WRCTRL_KEY_OFF          (PAC_WRCTRL_KEY_OFF_Val        << PAC_WRCTRL_KEY_Pos)
#define PAC_WRCTRL_KEY_CLR          (PAC_WRCTRL_KEY_CLR_Val        << PAC_WRCTRL_KEY_Pos)
#define PAC_WRCTRL_KEY_SET          (PAC_WRCTRL_KEY_SET_Val        << PAC_WRCTRL_KEY_Pos)
#define PAC_WRCTRL_KEY_SETLCK       (PAC_WRCTRL_KEY_SETLCK_Val     << PAC_WRCTRL_KEY_Pos)
#define PAC_WRCTRL_MASK             _U_(0x00FFFFFF) /**< \brief (PAC_WRCTRL) MASK Register */

/* -------- PAC_EVCTRL : (PAC Offset: 0x04) (R/W  8) Event control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  ERREO:1;          /*!< bit:      0  Peripheral acess error event output */
    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
  } bit;                       /*!< Structure used for bit  access                  */
  uint8_t reg;                 /*!< Type      used for register access              */
} PAC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define PAC_EVCTRL_OFFSET           0x04         /**< \brief (PAC_EVCTRL offset) Event control */
#define PAC_EVCTRL_RESETVALUE       _U_(0x00)    /**< \brief (PAC_EVCTRL reset_value) Event control */

#define PAC_EVCTRL_ERREO_Pos        0            /**< \brief (PAC_EVCTRL) Peripheral acess error event output */
#define PAC_EVCTRL_ERREO            (_U_(0x1) << PAC_EVCTRL_ERREO_Pos)
#define PAC_EVCTRL_MASK             _U_(0x01)    /**< \brief (PAC_EVCTRL) MASK Register */

/* -------- PAC_INTENCLR : (PAC Offset: 0x08) (R/W  8) Interrupt enable clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  ERR:1;            /*!< bit:      0  Peripheral access error interrupt disable */
    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
  } bit;                       /*!< Structure used for bit  access                  */
  uint8_t reg;                 /*!< Type      used for register access              */
} PAC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define PAC_INTENCLR_OFFSET         0x08         /**< \brief (PAC_INTENCLR offset) Interrupt enable clear */
#define PAC_INTENCLR_RESETVALUE     _U_(0x00)    /**< \brief (PAC_INTENCLR reset_value) Interrupt enable clear */

#define PAC_INTENCLR_ERR_Pos        0            /**< \brief (PAC_INTENCLR) Peripheral access error interrupt disable */
#define PAC_INTENCLR_ERR            (_U_(0x1) << PAC_INTENCLR_ERR_Pos)
#define PAC_INTENCLR_MASK           _U_(0x01)    /**< \brief (PAC_INTENCLR) MASK Register */

/* -------- PAC_INTENSET : (PAC Offset: 0x09) (R/W  8) Interrupt enable set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  ERR:1;            /*!< bit:      0  Peripheral access error interrupt enable */
    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
  } bit;                       /*!< Structure used for bit  access                  */
  uint8_t reg;                 /*!< Type      used for register access              */
} PAC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define PAC_INTENSET_OFFSET         0x09         /**< \brief (PAC_INTENSET offset) Interrupt enable set */
#define PAC_INTENSET_RESETVALUE     _U_(0x00)    /**< \brief (PAC_INTENSET reset_value) Interrupt enable set */

#define PAC_INTENSET_ERR_Pos        0            /**< \brief (PAC_INTENSET) Peripheral access error interrupt enable */
#define PAC_INTENSET_ERR            (_U_(0x1) << PAC_INTENSET_ERR_Pos)
#define PAC_INTENSET_MASK           _U_(0x01)    /**< \brief (PAC_INTENSET) MASK Register */

/* -------- PAC_INTFLAGAHB : (PAC Offset: 0x10) (R/W 32) Bridge interrupt flag status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
  struct {
    __I uint32_t FLASH_:1;         /*!< bit:      0  FLASH                              */
    __I uint32_t HSRAMCM0P_:1;     /*!< bit:      1  HSRAMCM0P                          */
    __I uint32_t HSRAMDSU_:1;      /*!< bit:      2  HSRAMDSU                           */
    __I uint32_t HPB1_:1;          /*!< bit:      3  HPB1                               */
    __I uint32_t HPB0_:1;          /*!< bit:      4  HPB0                               */
    __I uint32_t HPB2_:1;          /*!< bit:      5  HPB2                               */
    __I uint32_t HSRAMDMAC_:1;     /*!< bit:      6  HSRAMDMAC                          */
    __I uint32_t :25;              /*!< bit:  7..31  Reserved                           */
  } bit;                       /*!< Structure used for bit  access                  */
  uint32_t reg;                /*!< Type      used for register access              */
} PAC_INTFLAGAHB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define PAC_INTFLAGAHB_OFFSET       0x10         /**< \brief (PAC_INTFLAGAHB offset) Bridge interrupt flag status */
#define PAC_INTFLAGAHB_RESETVALUE   _U_(0x00000000) /**< \brief (PAC_INTFLAGAHB reset_value) Bridge interrupt flag status */

#define PAC_INTFLAGAHB_FLASH_Pos    0            /**< \brief (PAC_INTFLAGAHB) FLASH */
#define PAC_INTFLAGAHB_FLASH        (_U_(0x1) << PAC_INTFLAGAHB_FLASH_Pos)
#define PAC_INTFLAGAHB_HSRAMCM0P_Pos 1            /**< \brief (PAC_INTFLAGAHB) HSRAMCM0P */
#define PAC_INTFLAGAHB_HSRAMCM0P    (_U_(0x1) << PAC_INTFLAGAHB_HSRAMCM0P_Pos)
#define PAC_INTFLAGAHB_HSRAMDSU_Pos 2            /**< \brief (PAC_INTFLAGAHB) HSRAMDSU */
#define PAC_INTFLAGAHB_HSRAMDSU     (_U_(0x1) << PAC_INTFLAGAHB_HSRAMDSU_Pos)
#define PAC_INTFLAGAHB_HPB1_Pos     3            /**< \brief (PAC_INTFLAGAHB) HPB1 */
#define PAC_INTFLAGAHB_HPB1         (_U_(0x1) << PAC_INTFLAGAHB_HPB1_Pos)
#define PAC_INTFLAGAHB_HPB0_Pos     4            /**< \brief (PAC_INTFLAGAHB) HPB0 */
#define PAC_INTFLAGAHB_HPB0         (_U_(0x1) << PAC_INTFLAGAHB_HPB0_Pos)
#define PAC_INTFLAGAHB_HPB2_Pos     5            /**< \brief (PAC_INTFLAGAHB) HPB2 */
#define PAC_INTFLAGAHB_HPB2         (_U_(0x1) << PAC_INTFLAGAHB_HPB2_Pos)
#define PAC_INTFLAGAHB_HSRAMDMAC_Pos 6            /**< \brief (PAC_INTFLAGAHB) HSRAMDMAC */
#define PAC_INTFLAGAHB_HSRAMDMAC    (_U_(0x1) << PAC_INTFLAGAHB_HSRAMDMAC_Pos)
#define PAC_INTFLAGAHB_MASK         _U_(0x0000007F) /**< \brief (PAC_INTFLAGAHB) MASK Register */

/* -------- PAC_INTFLAGA : (PAC Offset: 0x14) (R/W 32) Peripheral interrupt flag status - Bridge A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
  struct {
    __I uint32_t PAC_:1;           /*!< bit:      0  PAC                                */
    __I uint32_t PM_:1;            /*!< bit:      1  PM                                 */
    __I uint32_t MCLK_:1;          /*!< bit:      2  MCLK                               */
    __I uint32_t RSTC_:1;          /*!< bit:      3  RSTC                               */
    __I uint32_t OSCCTRL_:1;       /*!< bit:      4  OSCCTRL                            */
    __I uint32_t OSC32KCTRL_:1;    /*!< bit:      5  OSC32KCTRL                         */
    __I uint32_t SUPC_:1;          /*!< bit:      6  SUPC                               */
    __I uint32_t GCLK_:1;          /*!< bit:      7  GCLK                               */
    __I uint32_t WDT_:1;           /*!< bit:      8  WDT                                */
    __I uint32_t RTC_:1;           /*!< bit:      9  RTC                                */
    __I uint32_t EIC_:1;           /*!< bit:     10  EIC                                */
    __I uint32_t FREQM_:1;         /*!< bit:     11  FREQM                              */
    __I uint32_t :20;              /*!< bit: 12..31  Reserved                           */
  } bit;                       /*!< Structure used for bit  access                  */
  uint32_t reg;                /*!< Type      used for register access              */
} PAC_INTFLAGA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define PAC_INTFLAGA_OFFSET         0x14         /**< \brief (PAC_INTFLAGA offset) Peripheral interrupt flag status - Bridge A */
#define PAC_INTFLAGA_RESETVALUE     _U_(0x00000000) /**< \brief (PAC_INTFLAGA reset_value) Peripheral interrupt flag status - Bridge A */

#define PAC_INTFLAGA_PAC_Pos        0            /**< \brief (PAC_INTFLAGA) PAC */
#define PAC_INTFLAGA_PAC            (_U_(0x1) << PAC_INTFLAGA_PAC_Pos)
#define PAC_INTFLAGA_PM_Pos         1            /**< \brief (PAC_INTFLAGA) PM */
#define PAC_INTFLAGA_PM             (_U_(0x1) << PAC_INTFLAGA_PM_Pos)
#define PAC_INTFLAGA_MCLK_Pos       2            /**< \brief (PAC_INTFLAGA) MCLK */
#define PAC_INTFLAGA_MCLK           (_U_(0x1) << PAC_INTFLAGA_MCLK_Pos)
#define PAC_INTFLAGA_RSTC_Pos       3            /**< \brief (PAC_INTFLAGA) RSTC */
#define PAC_INTFLAGA_RSTC           (_U_(0x1) << PAC_INTFLAGA_RSTC_Pos)
#define PAC_INTFLAGA_OSCCTRL_Pos    4            /**< \brief (PAC_INTFLAGA) OSCCTRL */
#define PAC_INTFLAGA_OSCCTRL        (_U_(0x1) << PAC_INTFLAGA_OSCCTRL_Pos)
#define PAC_INTFLAGA_OSC32KCTRL_Pos 5            /**< \brief (PAC_INTFLAGA) OSC32KCTRL */
#define PAC_INTFLAGA_OSC32KCTRL     (_U_(0x1) << PAC_INTFLAGA_OSC32KCTRL_Pos)
#define PAC_INTFLAGA_SUPC_Pos       6            /**< \brief (PAC_INTFLAGA) SUPC */
#define PAC_INTFLAGA_SUPC           (_U_(0x1) << PAC_INTFLAGA_SUPC_Pos)
#define PAC_INTFLAGA_GCLK_Pos       7            /**< \brief (PAC_INTFLAGA) GCLK */
#define PAC_INTFLAGA_GCLK           (_U_(0x1) << PAC_INTFLAGA_GCLK_Pos)
#define PAC_INTFLAGA_WDT_Pos        8            /**< \brief (PAC_INTFLAGA) WDT */
#define PAC_INTFLAGA_WDT            (_U_(0x1) << PAC_INTFLAGA_WDT_Pos)
#define PAC_INTFLAGA_RTC_Pos        9            /**< \brief (PAC_INTFLAGA) RTC */
#define PAC_INTFLAGA_RTC            (_U_(0x1) << PAC_INTFLAGA_RTC_Pos)
#define PAC_INTFLAGA_EIC_Pos        10           /**< \brief (PAC_INTFLAGA) EIC */
#define PAC_INTFLAGA_EIC            (_U_(0x1) << PAC_INTFLAGA_EIC_Pos)
#define PAC_INTFLAGA_FREQM_Pos      11           /**< \brief (PAC_INTFLAGA) FREQM */
#define PAC_INTFLAGA_FREQM          (_U_(0x1) << PAC_INTFLAGA_FREQM_Pos)
#define PAC_INTFLAGA_MASK           _U_(0x00000FFF) /**< \brief (PAC_INTFLAGA) MASK Register */

/* -------- PAC_INTFLAGB : (PAC Offset: 0x18) (R/W 32) Peripheral interrupt flag status - Bridge B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
  struct {
    __I uint32_t USB_:1;           /*!< bit:      0  USB                                */
    __I uint32_t DSU_:1;           /*!< bit:      1  DSU                                */
    __I uint32_t NVMCTRL_:1;       /*!< bit:      2  NVMCTRL                            */
    __I uint32_t PORT_:1;          /*!< bit:      3  PORT                               */
    __I uint32_t DMAC_:1;          /*!< bit:      4  DMAC                               */
    __I uint32_t MTB_:1;           /*!< bit:      5  MTB                                */
    __I uint32_t :26;              /*!< bit:  6..31  Reserved                           */
  } bit;                       /*!< Structure used for bit  access                  */
  uint32_t reg;                /*!< Type      used for register access              */
} PAC_INTFLAGB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define PAC_INTFLAGB_OFFSET         0x18         /**< \brief (PAC_INTFLAGB offset) Peripheral interrupt flag status - Bridge B */
#define PAC_INTFLAGB_RESETVALUE     _U_(0x00000000) /**< \brief (PAC_INTFLAGB reset_value) Peripheral interrupt flag status - Bridge B */

#define PAC_INTFLAGB_USB_Pos        0            /**< \brief (PAC_INTFLAGB) USB */
#define PAC_INTFLAGB_USB            (_U_(0x1) << PAC_INTFLAGB_USB_Pos)
#define PAC_INTFLAGB_DSU_Pos        1            /**< \brief (PAC_INTFLAGB) DSU */
#define PAC_INTFLAGB_DSU            (_U_(0x1) << PAC_INTFLAGB_DSU_Pos)
#define PAC_INTFLAGB_NVMCTRL_Pos    2            /**< \brief (PAC_INTFLAGB) NVMCTRL */
#define PAC_INTFLAGB_NVMCTRL        (_U_(0x1) << PAC_INTFLAGB_NVMCTRL_Pos)
#define PAC_INTFLAGB_PORT_Pos       3            /**< \brief (PAC_INTFLAGB) PORT */
#define PAC_INTFLAGB_PORT           (_U_(0x1) << PAC_INTFLAGB_PORT_Pos)
#define PAC_INTFLAGB_DMAC_Pos       4            /**< \brief (PAC_INTFLAGB) DMAC */
#define PAC_INTFLAGB_DMAC           (_U_(0x1) << PAC_INTFLAGB_DMAC_Pos)
#define PAC_INTFLAGB_MTB_Pos        5            /**< \brief (PAC_INTFLAGB) MTB */
#define PAC_INTFLAGB_MTB            (_U_(0x1) << PAC_INTFLAGB_MTB_Pos)
#define PAC_INTFLAGB_MASK           _U_(0x0000003F) /**< \brief (PAC_INTFLAGB) MASK Register */

/* -------- PAC_INTFLAGC : (PAC Offset: 0x1C) (R/W 32) Peripheral interrupt flag status - Bridge C -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
  struct {
    __I uint32_t EVSYS_:1;         /*!< bit:      0  EVSYS                              */
    __I uint32_t SERCOM0_:1;       /*!< bit:      1  SERCOM0                            */
    __I uint32_t SERCOM1_:1;       /*!< bit:      2  SERCOM1                            */
    __I uint32_t SERCOM2_:1;       /*!< bit:      3  SERCOM2                            */
    __I uint32_t SERCOM3_:1;       /*!< bit:      4  SERCOM3                            */
    __I uint32_t SERCOM4_:1;       /*!< bit:      5  SERCOM4                            */
    __I uint32_t SERCOM5_:1;       /*!< bit:      6  SERCOM5                            */
    __I uint32_t TCC0_:1;          /*!< bit:      7  TCC0                               */
    __I uint32_t TC0_:1;           /*!< bit:      8  TC0                                */
    __I uint32_t TC1_:1;           /*!< bit:      9  TC1                                */
    __I uint32_t TC2_:1;           /*!< bit:     10  TC2                                */
    __I uint32_t TC3_:1;           /*!< bit:     11  TC3                                */
    __I uint32_t ADC_:1;           /*!< bit:     12  ADC                                */
    __I uint32_t AC_:1;            /*!< bit:     13  AC                                 */
    __I uint32_t PTC_:1;           /*!< bit:     14  PTC                                */
    __I uint32_t SLCD_:1;          /*!< bit:     15  SLCD                               */
    __I uint32_t AES_:1;           /*!< bit:     16  AES                                */
    __I uint32_t TRNG_:1;          /*!< bit:     17  TRNG                               */
    __I uint32_t CCL_:1;           /*!< bit:     18  CCL                                */
    __I uint32_t :13;              /*!< bit: 19..31  Reserved                           */
  } bit;                       /*!< Structure used for bit  access                  */
  uint32_t reg;                /*!< Type      used for register access              */
} PAC_INTFLAGC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define PAC_INTFLAGC_OFFSET         0x1C         /**< \brief (PAC_INTFLAGC offset) Peripheral interrupt flag status - Bridge C */
#define PAC_INTFLAGC_RESETVALUE     _U_(0x00000000) /**< \brief (PAC_INTFLAGC reset_value) Peripheral interrupt flag status - Bridge C */

#define PAC_INTFLAGC_EVSYS_Pos      0            /**< \brief (PAC_INTFLAGC) EVSYS */
#define PAC_INTFLAGC_EVSYS          (_U_(0x1) << PAC_INTFLAGC_EVSYS_Pos)
#define PAC_INTFLAGC_SERCOM0_Pos    1            /**< \brief (PAC_INTFLAGC) SERCOM0 */
#define PAC_INTFLAGC_SERCOM0        (_U_(0x1) << PAC_INTFLAGC_SERCOM0_Pos)
#define PAC_INTFLAGC_SERCOM1_Pos    2            /**< \brief (PAC_INTFLAGC) SERCOM1 */
#define PAC_INTFLAGC_SERCOM1        (_U_(0x1) << PAC_INTFLAGC_SERCOM1_Pos)
#define PAC_INTFLAGC_SERCOM2_Pos    3            /**< \brief (PAC_INTFLAGC) SERCOM2 */
#define PAC_INTFLAGC_SERCOM2        (_U_(0x1) << PAC_INTFLAGC_SERCOM2_Pos)
#define PAC_INTFLAGC_SERCOM3_Pos    4            /**< \brief (PAC_INTFLAGC) SERCOM3 */
#define PAC_INTFLAGC_SERCOM3        (_U_(0x1) << PAC_INTFLAGC_SERCOM3_Pos)
#define PAC_INTFLAGC_SERCOM4_Pos    5            /**< \brief (PAC_INTFLAGC) SERCOM4 */
#define PAC_INTFLAGC_SERCOM4        (_U_(0x1) << PAC_INTFLAGC_SERCOM4_Pos)
#define PAC_INTFLAGC_SERCOM5_Pos    6            /**< \brief (PAC_INTFLAGC) SERCOM5 */
#define PAC_INTFLAGC_SERCOM5        (_U_(0x1) << PAC_INTFLAGC_SERCOM5_Pos)
#define PAC_INTFLAGC_TCC0_Pos       7            /**< \brief (PAC_INTFLAGC) TCC0 */
#define PAC_INTFLAGC_TCC0           (_U_(0x1) << PAC_INTFLAGC_TCC0_Pos)
#define PAC_INTFLAGC_TC0_Pos        8            /**< \brief (PAC_INTFLAGC) TC0 */
#define PAC_INTFLAGC_TC0            (_U_(0x1) << PAC_INTFLAGC_TC0_Pos)
#define PAC_INTFLAGC_TC1_Pos        9            /**< \brief (PAC_INTFLAGC) TC1 */
#define PAC_INTFLAGC_TC1            (_U_(0x1) << PAC_INTFLAGC_TC1_Pos)
#define PAC_INTFLAGC_TC2_Pos        10           /**< \brief (PAC_INTFLAGC) TC2 */
#define PAC_INTFLAGC_TC2            (_U_(0x1) << PAC_INTFLAGC_TC2_Pos)
#define PAC_INTFLAGC_TC3_Pos        11           /**< \brief (PAC_INTFLAGC) TC3 */
#define PAC_INTFLAGC_TC3            (_U_(0x1) << PAC_INTFLAGC_TC3_Pos)
#define PAC_INTFLAGC_ADC_Pos        12           /**< \brief (PAC_INTFLAGC) ADC */
#define PAC_INTFLAGC_ADC            (_U_(0x1) << PAC_INTFLAGC_ADC_Pos)
#define PAC_INTFLAGC_AC_Pos         13           /**< \brief (PAC_INTFLAGC) AC */
#define PAC_INTFLAGC_AC             (_U_(0x1) << PAC_INTFLAGC_AC_Pos)
#define PAC_INTFLAGC_PTC_Pos        14           /**< \brief (PAC_INTFLAGC) PTC */
#define PAC_INTFLAGC_PTC            (_U_(0x1) << PAC_INTFLAGC_PTC_Pos)
#define PAC_INTFLAGC_SLCD_Pos       15           /**< \brief (PAC_INTFLAGC) SLCD */
#define PAC_INTFLAGC_SLCD           (_U_(0x1) << PAC_INTFLAGC_SLCD_Pos)
#define PAC_INTFLAGC_AES_Pos        16           /**< \brief (PAC_INTFLAGC) AES */
#define PAC_INTFLAGC_AES            (_U_(0x1) << PAC_INTFLAGC_AES_Pos)
#define PAC_INTFLAGC_TRNG_Pos       17           /**< \brief (PAC_INTFLAGC) TRNG */
#define PAC_INTFLAGC_TRNG           (_U_(0x1) << PAC_INTFLAGC_TRNG_Pos)
#define PAC_INTFLAGC_CCL_Pos        18           /**< \brief (PAC_INTFLAGC) CCL */
#define PAC_INTFLAGC_CCL            (_U_(0x1) << PAC_INTFLAGC_CCL_Pos)
#define PAC_INTFLAGC_MASK           _U_(0x0007FFFF) /**< \brief (PAC_INTFLAGC) MASK Register */

/* -------- PAC_STATUSA : (PAC Offset: 0x34) (R/  32) Peripheral write protection status - Bridge A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t PAC_:1;           /*!< bit:      0  PAC APB Protect Enable             */
    uint32_t PM_:1;            /*!< bit:      1  PM APB Protect Enable              */
    uint32_t MCLK_:1;          /*!< bit:      2  MCLK APB Protect Enable            */
    uint32_t RSTC_:1;          /*!< bit:      3  RSTC APB Protect Enable            */
    uint32_t OSCCTRL_:1;       /*!< bit:      4  OSCCTRL APB Protect Enable         */
    uint32_t OSC32KCTRL_:1;    /*!< bit:      5  OSC32KCTRL APB Protect Enable      */
    uint32_t SUPC_:1;          /*!< bit:      6  SUPC APB Protect Enable            */
    uint32_t GCLK_:1;          /*!< bit:      7  GCLK APB Protect Enable            */
    uint32_t WDT_:1;           /*!< bit:      8  WDT APB Protect Enable             */
    uint32_t RTC_:1;           /*!< bit:      9  RTC APB Protect Enable             */
    uint32_t EIC_:1;           /*!< bit:     10  EIC APB Protect Enable             */
    uint32_t FREQM_:1;         /*!< bit:     11  FREQM APB Protect Enable           */
    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
  } bit;                       /*!< Structure used for bit  access                  */
  uint32_t reg;                /*!< Type      used for register access              */
} PAC_STATUSA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define PAC_STATUSA_OFFSET          0x34         /**< \brief (PAC_STATUSA offset) Peripheral write protection status - Bridge A */
#define PAC_STATUSA_RESETVALUE      _U_(0x00000000) /**< \brief (PAC_STATUSA reset_value) Peripheral write protection status - Bridge A */

#define PAC_STATUSA_PAC_Pos         0            /**< \brief (PAC_STATUSA) PAC APB Protect Enable */
#define PAC_STATUSA_PAC             (_U_(0x1) << PAC_STATUSA_PAC_Pos)
#define PAC_STATUSA_PM_Pos          1            /**< \brief (PAC_STATUSA) PM APB Protect Enable */
#define PAC_STATUSA_PM              (_U_(0x1) << PAC_STATUSA_PM_Pos)
#define PAC_STATUSA_MCLK_Pos        2            /**< \brief (PAC_STATUSA) MCLK APB Protect Enable */
#define PAC_STATUSA_MCLK            (_U_(0x1) << PAC_STATUSA_MCLK_Pos)
#define PAC_STATUSA_RSTC_Pos        3            /**< \brief (PAC_STATUSA) RSTC APB Protect Enable */
#define PAC_STATUSA_RSTC            (_U_(0x1) << PAC_STATUSA_RSTC_Pos)
#define PAC_STATUSA_OSCCTRL_Pos     4            /**< \brief (PAC_STATUSA) OSCCTRL APB Protect Enable */
#define PAC_STATUSA_OSCCTRL         (_U_(0x1) << PAC_STATUSA_OSCCTRL_Pos)
#define PAC_STATUSA_OSC32KCTRL_Pos  5            /**< \brief (PAC_STATUSA) OSC32KCTRL APB Protect Enable */
#define PAC_STATUSA_OSC32KCTRL      (_U_(0x1) << PAC_STATUSA_OSC32KCTRL_Pos)
#define PAC_STATUSA_SUPC_Pos        6            /**< \brief (PAC_STATUSA) SUPC APB Protect Enable */
#define PAC_STATUSA_SUPC            (_U_(0x1) << PAC_STATUSA_SUPC_Pos)
#define PAC_STATUSA_GCLK_Pos        7            /**< \brief (PAC_STATUSA) GCLK APB Protect Enable */
#define PAC_STATUSA_GCLK            (_U_(0x1) << PAC_STATUSA_GCLK_Pos)
#define PAC_STATUSA_WDT_Pos         8            /**< \brief (PAC_STATUSA) WDT APB Protect Enable */
#define PAC_STATUSA_WDT             (_U_(0x1) << PAC_STATUSA_WDT_Pos)
#define PAC_STATUSA_RTC_Pos         9            /**< \brief (PAC_STATUSA) RTC APB Protect Enable */
#define PAC_STATUSA_RTC             (_U_(0x1) << PAC_STATUSA_RTC_Pos)
#define PAC_STATUSA_EIC_Pos         10           /**< \brief (PAC_STATUSA) EIC APB Protect Enable */
#define PAC_STATUSA_EIC             (_U_(0x1) << PAC_STATUSA_EIC_Pos)
#define PAC_STATUSA_FREQM_Pos       11           /**< \brief (PAC_STATUSA) FREQM APB Protect Enable */
#define PAC_STATUSA_FREQM           (_U_(0x1) << PAC_STATUSA_FREQM_Pos)
#define PAC_STATUSA_MASK            _U_(0x00000FFF) /**< \brief (PAC_STATUSA) MASK Register */

/* -------- PAC_STATUSB : (PAC Offset: 0x38) (R/  32) Peripheral write protection status - Bridge B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t USB_:1;           /*!< bit:      0  USB APB Protect Enable             */
    uint32_t DSU_:1;           /*!< bit:      1  DSU APB Protect Enable             */
    uint32_t NVMCTRL_:1;       /*!< bit:      2  NVMCTRL APB Protect Enable         */
    uint32_t PORT_:1;          /*!< bit:      3  PORT APB Protect Enable            */
    uint32_t DMAC_:1;          /*!< bit:      4  DMAC APB Protect Enable            */
    uint32_t MTB_:1;           /*!< bit:      5  MTB APB Protect Enable             */
    uint32_t :26;              /*!< bit:  6..31  Reserved                           */
  } bit;                       /*!< Structure used for bit  access                  */
  uint32_t reg;                /*!< Type      used for register access              */
} PAC_STATUSB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define PAC_STATUSB_OFFSET          0x38         /**< \brief (PAC_STATUSB offset) Peripheral write protection status - Bridge B */
#define PAC_STATUSB_RESETVALUE      _U_(0x00000002) /**< \brief (PAC_STATUSB reset_value) Peripheral write protection status - Bridge B */

#define PAC_STATUSB_USB_Pos         0            /**< \brief (PAC_STATUSB) USB APB Protect Enable */
#define PAC_STATUSB_USB             (_U_(0x1) << PAC_STATUSB_USB_Pos)
#define PAC_STATUSB_DSU_Pos         1            /**< \brief (PAC_STATUSB) DSU APB Protect Enable */
#define PAC_STATUSB_DSU             (_U_(0x1) << PAC_STATUSB_DSU_Pos)
#define PAC_STATUSB_NVMCTRL_Pos     2            /**< \brief (PAC_STATUSB) NVMCTRL APB Protect Enable */
#define PAC_STATUSB_NVMCTRL         (_U_(0x1) << PAC_STATUSB_NVMCTRL_Pos)
#define PAC_STATUSB_PORT_Pos        3            /**< \brief (PAC_STATUSB) PORT APB Protect Enable */
#define PAC_STATUSB_PORT            (_U_(0x1) << PAC_STATUSB_PORT_Pos)
#define PAC_STATUSB_DMAC_Pos        4            /**< \brief (PAC_STATUSB) DMAC APB Protect Enable */
#define PAC_STATUSB_DMAC            (_U_(0x1) << PAC_STATUSB_DMAC_Pos)
#define PAC_STATUSB_MTB_Pos         5            /**< \brief (PAC_STATUSB) MTB APB Protect Enable */
#define PAC_STATUSB_MTB             (_U_(0x1) << PAC_STATUSB_MTB_Pos)
#define PAC_STATUSB_MASK            _U_(0x0000003F) /**< \brief (PAC_STATUSB) MASK Register */

/* -------- PAC_STATUSC : (PAC Offset: 0x3C) (R/  32) Peripheral write protection status - Bridge C -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t EVSYS_:1;         /*!< bit:      0  EVSYS APB Protect Enable           */
    uint32_t SERCOM0_:1;       /*!< bit:      1  SERCOM0 APB Protect Enable         */
    uint32_t SERCOM1_:1;       /*!< bit:      2  SERCOM1 APB Protect Enable         */
    uint32_t SERCOM2_:1;       /*!< bit:      3  SERCOM2 APB Protect Enable         */
    uint32_t SERCOM3_:1;       /*!< bit:      4  SERCOM3 APB Protect Enable         */
    uint32_t SERCOM4_:1;       /*!< bit:      5  SERCOM4 APB Protect Enable         */
    uint32_t SERCOM5_:1;       /*!< bit:      6  SERCOM5 APB Protect Enable         */
    uint32_t TCC0_:1;          /*!< bit:      7  TCC0 APB Protect Enable            */
    uint32_t TC0_:1;           /*!< bit:      8  TC0 APB Protect Enable             */
    uint32_t TC1_:1;           /*!< bit:      9  TC1 APB Protect Enable             */
    uint32_t TC2_:1;           /*!< bit:     10  TC2 APB Protect Enable             */
    uint32_t TC3_:1;           /*!< bit:     11  TC3 APB Protect Enable             */
    uint32_t ADC_:1;           /*!< bit:     12  ADC APB Protect Enable             */
    uint32_t AC_:1;            /*!< bit:     13  AC APB Protect Enable              */
    uint32_t PTC_:1;           /*!< bit:     14  PTC APB Protect Enable             */
    uint32_t SLCD_:1;          /*!< bit:     15  SLCD APB Protect Enable            */
    uint32_t AES_:1;           /*!< bit:     16  AES APB Protect Enable             */
    uint32_t TRNG_:1;          /*!< bit:     17  TRNG APB Protect Enable            */
    uint32_t CCL_:1;           /*!< bit:     18  CCL APB Protect Enable             */
    uint32_t :13;              /*!< bit: 19..31  Reserved                           */
  } bit;                       /*!< Structure used for bit  access                  */
  uint32_t reg;                /*!< Type      used for register access              */
} PAC_STATUSC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define PAC_STATUSC_OFFSET          0x3C         /**< \brief (PAC_STATUSC offset) Peripheral write protection status - Bridge C */
#define PAC_STATUSC_RESETVALUE      _U_(0x00080000) /**< \brief (PAC_STATUSC reset_value) Peripheral write protection status - Bridge C */

#define PAC_STATUSC_EVSYS_Pos       0            /**< \brief (PAC_STATUSC) EVSYS APB Protect Enable */
#define PAC_STATUSC_EVSYS           (_U_(0x1) << PAC_STATUSC_EVSYS_Pos)
#define PAC_STATUSC_SERCOM0_Pos     1            /**< \brief (PAC_STATUSC) SERCOM0 APB Protect Enable */
#define PAC_STATUSC_SERCOM0         (_U_(0x1) << PAC_STATUSC_SERCOM0_Pos)
#define PAC_STATUSC_SERCOM1_Pos     2            /**< \brief (PAC_STATUSC) SERCOM1 APB Protect Enable */
#define PAC_STATUSC_SERCOM1         (_U_(0x1) << PAC_STATUSC_SERCOM1_Pos)
#define PAC_STATUSC_SERCOM2_Pos     3            /**< \brief (PAC_STATUSC) SERCOM2 APB Protect Enable */
#define PAC_STATUSC_SERCOM2         (_U_(0x1) << PAC_STATUSC_SERCOM2_Pos)
#define PAC_STATUSC_SERCOM3_Pos     4            /**< \brief (PAC_STATUSC) SERCOM3 APB Protect Enable */
#define PAC_STATUSC_SERCOM3         (_U_(0x1) << PAC_STATUSC_SERCOM3_Pos)
#define PAC_STATUSC_SERCOM4_Pos     5            /**< \brief (PAC_STATUSC) SERCOM4 APB Protect Enable */
#define PAC_STATUSC_SERCOM4         (_U_(0x1) << PAC_STATUSC_SERCOM4_Pos)
#define PAC_STATUSC_SERCOM5_Pos     6            /**< \brief (PAC_STATUSC) SERCOM5 APB Protect Enable */
#define PAC_STATUSC_SERCOM5         (_U_(0x1) << PAC_STATUSC_SERCOM5_Pos)
#define PAC_STATUSC_TCC0_Pos        7            /**< \brief (PAC_STATUSC) TCC0 APB Protect Enable */
#define PAC_STATUSC_TCC0            (_U_(0x1) << PAC_STATUSC_TCC0_Pos)
#define PAC_STATUSC_TC0_Pos         8            /**< \brief (PAC_STATUSC) TC0 APB Protect Enable */
#define PAC_STATUSC_TC0             (_U_(0x1) << PAC_STATUSC_TC0_Pos)
#define PAC_STATUSC_TC1_Pos         9            /**< \brief (PAC_STATUSC) TC1 APB Protect Enable */
#define PAC_STATUSC_TC1             (_U_(0x1) << PAC_STATUSC_TC1_Pos)
#define PAC_STATUSC_TC2_Pos         10           /**< \brief (PAC_STATUSC) TC2 APB Protect Enable */
#define PAC_STATUSC_TC2             (_U_(0x1) << PAC_STATUSC_TC2_Pos)
#define PAC_STATUSC_TC3_Pos         11           /**< \brief (PAC_STATUSC) TC3 APB Protect Enable */
#define PAC_STATUSC_TC3             (_U_(0x1) << PAC_STATUSC_TC3_Pos)
#define PAC_STATUSC_ADC_Pos         12           /**< \brief (PAC_STATUSC) ADC APB Protect Enable */
#define PAC_STATUSC_ADC             (_U_(0x1) << PAC_STATUSC_ADC_Pos)
#define PAC_STATUSC_AC_Pos          13           /**< \brief (PAC_STATUSC) AC APB Protect Enable */
#define PAC_STATUSC_AC              (_U_(0x1) << PAC_STATUSC_AC_Pos)
#define PAC_STATUSC_PTC_Pos         14           /**< \brief (PAC_STATUSC) PTC APB Protect Enable */
#define PAC_STATUSC_PTC             (_U_(0x1) << PAC_STATUSC_PTC_Pos)
#define PAC_STATUSC_SLCD_Pos        15           /**< \brief (PAC_STATUSC) SLCD APB Protect Enable */
#define PAC_STATUSC_SLCD            (_U_(0x1) << PAC_STATUSC_SLCD_Pos)
#define PAC_STATUSC_AES_Pos         16           /**< \brief (PAC_STATUSC) AES APB Protect Enable */
#define PAC_STATUSC_AES             (_U_(0x1) << PAC_STATUSC_AES_Pos)
#define PAC_STATUSC_TRNG_Pos        17           /**< \brief (PAC_STATUSC) TRNG APB Protect Enable */
#define PAC_STATUSC_TRNG            (_U_(0x1) << PAC_STATUSC_TRNG_Pos)
#define PAC_STATUSC_CCL_Pos         18           /**< \brief (PAC_STATUSC) CCL APB Protect Enable */
#define PAC_STATUSC_CCL             (_U_(0x1) << PAC_STATUSC_CCL_Pos)
#define PAC_STATUSC_MASK            _U_(0x0007FFFF) /**< \brief (PAC_STATUSC) MASK Register */

/** \brief PAC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
  __IO PAC_WRCTRL_Type           WRCTRL;      /**< \brief Offset: 0x00 (R/W 32) Write control */
  __IO PAC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x04 (R/W  8) Event control */
       RoReg8                    Reserved1[0x3];
  __IO PAC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x08 (R/W  8) Interrupt enable clear */
  __IO PAC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x09 (R/W  8) Interrupt enable set */
       RoReg8                    Reserved2[0x6];
  __IO PAC_INTFLAGAHB_Type       INTFLAGAHB;  /**< \brief Offset: 0x10 (R/W 32) Bridge interrupt flag status */
  __IO PAC_INTFLAGA_Type         INTFLAGA;    /**< \brief Offset: 0x14 (R/W 32) Peripheral interrupt flag status - Bridge A */
  __IO PAC_INTFLAGB_Type         INTFLAGB;    /**< \brief Offset: 0x18 (R/W 32) Peripheral interrupt flag status - Bridge B */
  __IO PAC_INTFLAGC_Type         INTFLAGC;    /**< \brief Offset: 0x1C (R/W 32) Peripheral interrupt flag status - Bridge C */
       RoReg8                    Reserved3[0x14];
  __I  PAC_STATUSA_Type          STATUSA;     /**< \brief Offset: 0x34 (R/  32) Peripheral write protection status - Bridge A */
  __I  PAC_STATUSB_Type          STATUSB;     /**< \brief Offset: 0x38 (R/  32) Peripheral write protection status - Bridge B */
  __I  PAC_STATUSC_Type          STATUSC;     /**< \brief Offset: 0x3C (R/  32) Peripheral write protection status - Bridge C */
} Pac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

/*@}*/

#endif /* _SAML22_PAC_COMPONENT_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-06 16:27:53 +0000