format_version: '2' name: My Project versions: api: '1.0' backend: 1.8.543 commit: 931b2422bde1a793dea853de68547f48bf245b0f content: unknown content_pack_name: unknown format: '2' frontend: 1.8.543 packs_version_avr8: 1.0.1457 packs_version_qtouch: unknown packs_version_sam: 1.0.1726 version_backend: 1.8.543 version_frontend: '' board: identifier: CustomBoard device: SAML22J18A-AN details: null application: null middlewares: {} drivers: ADC_0: user_label: ADC_0 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::ADC::driver_config_definition::ADC::HAL:Driver:ADC.Sync functionality: ADC api: HAL:Driver:ADC_Sync configuration: adc_advanced_settings: false adc_arch_adjres: 0 adc_arch_corren: false adc_arch_dbgrun: false adc_arch_event_settings: false adc_arch_flushei: false adc_arch_flushinv: false adc_arch_gaincorr: 0 adc_arch_leftadj: false adc_arch_offcomp: false adc_arch_offsetcorr: 0 adc_arch_ondemand: false adc_arch_refcomp: false adc_arch_resrdyeo: false adc_arch_runstdby: false adc_arch_samplen: 0 adc_arch_samplenum: 1 sample adc_arch_seqen: 0 adc_arch_startei: false adc_arch_startinv: false adc_arch_winlt: 0 adc_arch_winmode: No window mode adc_arch_winmoneo: false adc_arch_winut: 0 adc_differential_mode: false adc_freerunning_mode: false adc_pinmux_negative: ADC AIN0 pin adc_pinmux_positive: ADC AIN0 pin adc_prescaler: Peripheral clock divided by 2 adc_reference: Internal bandgap reference adc_resolution: 12-bit optional_signals: - identifier: ADC_0:AIN/9 pad: PB01 mode: Enabled configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::ADC.AIN.9 name: ADC/AIN/9 label: AIN/9 - identifier: ADC_0:AIN/10 pad: PB02 mode: Enabled configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::ADC.AIN.10 name: ADC/AIN/10 label: AIN/10 - identifier: ADC_0:AIN/12 pad: PB04 mode: Enabled configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::ADC.AIN.12 name: ADC/AIN/12 label: AIN/12 variant: null clocks: domain_group: nodes: - name: ADC input: Generic clock generator 0 external: false external_frequency: 0 configuration: adc_gclk_selection: Generic clock generator 0 DMAC: user_label: DMAC definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC functionality: System api: HAL:HPL:DMAC configuration: dmac_beatsize_0: 8-bit bus transfer dmac_beatsize_1: 8-bit bus transfer dmac_beatsize_10: 8-bit bus transfer dmac_beatsize_11: 8-bit bus transfer dmac_beatsize_12: 8-bit bus transfer dmac_beatsize_13: 8-bit bus transfer dmac_beatsize_14: 8-bit bus transfer dmac_beatsize_15: 8-bit bus transfer dmac_beatsize_2: 8-bit bus transfer dmac_beatsize_3: 8-bit bus transfer dmac_beatsize_4: 8-bit bus transfer dmac_beatsize_5: 8-bit bus transfer dmac_beatsize_6: 8-bit bus transfer dmac_beatsize_7: 8-bit bus transfer dmac_beatsize_8: 8-bit bus transfer dmac_beatsize_9: 8-bit bus transfer dmac_blockact_0: Channel will be disabled if it is the last block transfer in the transaction dmac_blockact_1: Channel will be disabled if it is the last block transfer in the transaction dmac_blockact_10: Channel will be disabled if it is the last block transfer in the transaction dmac_blockact_11: Channel will be disabled if it is the last block transfer in the transaction dmac_blockact_12: Channel will be disabled if it is the last block transfer in the transaction dmac_blockact_13: Channel will be disabled if it is the last block transfer in the transaction dmac_blockact_14: Channel will be disabled if it is the last block transfer in the transaction dmac_blockact_15: Channel will be disabled if it is the last block transfer in the transaction dmac_blockact_2: Channel will be disabled if it is the last block transfer in the transaction dmac_blockact_3: Channel will be disabled if it is the last block transfer in the transaction dmac_blockact_4: Channel will be disabled if it is the last block transfer in the transaction dmac_blockact_5: Channel will be disabled if it is the last block transfer in the transaction dmac_blockact_6: Channel will be disabled if it is the last block transfer in the transaction dmac_blockact_7: Channel will be disabled if it is the last block transfer in the transaction dmac_blockact_8: Channel will be disabled if it is the last block transfer in the transaction dmac_blockact_9: Channel will be disabled if it is the last block transfer in the transaction dmac_channel_0_settings: false dmac_channel_10_settings: false dmac_channel_11_settings: false dmac_channel_12_settings: false dmac_channel_13_settings: false dmac_channel_14_settings: false dmac_channel_15_settings: false dmac_channel_1_settings: false dmac_channel_2_settings: false dmac_channel_3_settings: false dmac_channel_4_settings: false dmac_channel_5_settings: false dmac_channel_6_settings: false dmac_channel_7_settings: false dmac_channel_8_settings: false dmac_channel_9_settings: false dmac_dbgrun: false dmac_dqos: Background (no sensitive operation) dmac_dstinc_0: false dmac_dstinc_1: false dmac_dstinc_10: false dmac_dstinc_11: false dmac_dstinc_12: false dmac_dstinc_13: false dmac_dstinc_14: false dmac_dstinc_15: false dmac_dstinc_2: false dmac_dstinc_3: false dmac_dstinc_4: false dmac_dstinc_5: false dmac_dstinc_6: false dmac_dstinc_7: false dmac_dstinc_8: false dmac_dstinc_9: false dmac_enable: false dmac_enable_0: false dmac_enable_1: false dmac_enable_10: false dmac_enable_11: false dmac_enable_12: false dmac_enable_13: false dmac_enable_14: false dmac_enable_15: false dmac_enable_2: false dmac_enable_3: false dmac_enable_4: false dmac_enable_5: false dmac_enable_6: false dmac_enable_7: false dmac_enable_8: false dmac_enable_9: false dmac_evact_0: No action dmac_evact_1: No action dmac_evact_10: No action dmac_evact_11: No action dmac_evact_12: No action dmac_evact_13: No action dmac_evact_14: No action dmac_evact_15: No action dmac_evact_2: No action dmac_evact_3: No action dmac_evact_4: No action dmac_evact_5: No action dmac_evact_6: No action dmac_evact_7: No action dmac_evact_8: No action dmac_evact_9: No action dmac_evie_0: false dmac_evie_1: false dmac_evie_10: false dmac_evie_11: false dmac_evie_12: false dmac_evie_13: false dmac_evie_14: false dmac_evie_15: false dmac_evie_2: false dmac_evie_3: false dmac_evie_4: false dmac_evie_5: false dmac_evie_6: false dmac_evie_7: false dmac_evie_8: false dmac_evie_9: false dmac_evoe_0: false dmac_evoe_1: false dmac_evoe_10: false dmac_evoe_11: false dmac_evoe_12: false dmac_evoe_13: false dmac_evoe_14: false dmac_evoe_15: false dmac_evoe_2: false dmac_evoe_3: false dmac_evoe_4: false dmac_evoe_5: false dmac_evoe_6: false dmac_evoe_7: false dmac_evoe_8: false dmac_evoe_9: false dmac_evosel_0: Event generation disabled dmac_evosel_1: Event generation disabled dmac_evosel_10: Event generation disabled dmac_evosel_11: Event generation disabled dmac_evosel_12: Event generation disabled dmac_evosel_13: Event generation disabled dmac_evosel_14: Event generation disabled dmac_evosel_15: Event generation disabled dmac_evosel_2: Event generation disabled dmac_evosel_3: Event generation disabled dmac_evosel_4: Event generation disabled dmac_evosel_5: Event generation disabled dmac_evosel_6: Event generation disabled dmac_evosel_7: Event generation disabled dmac_evosel_8: Event generation disabled dmac_evosel_9: Event generation disabled dmac_fqos: Background (no sensitive operation) dmac_lvl_0: Channel priority 0 dmac_lvl_1: Channel priority 0 dmac_lvl_10: Channel priority 0 dmac_lvl_11: Channel priority 0 dmac_lvl_12: Channel priority 0 dmac_lvl_13: Channel priority 0 dmac_lvl_14: Channel priority 0 dmac_lvl_15: Channel priority 0 dmac_lvl_2: Channel priority 0 dmac_lvl_3: Channel priority 0 dmac_lvl_4: Channel priority 0 dmac_lvl_5: Channel priority 0 dmac_lvl_6: Channel priority 0 dmac_lvl_7: Channel priority 0 dmac_lvl_8: Channel priority 0 dmac_lvl_9: Channel priority 0 dmac_lvlen0: false dmac_lvlen1: false dmac_lvlen2: false dmac_lvlen3: false dmac_lvlpri0: 0 dmac_lvlpri1: 0 dmac_lvlpri2: 0 dmac_lvlpri3: 0 dmac_rrlvlen0: Static arbitration scheme for channel with priority 0 dmac_rrlvlen1: Static arbitration scheme for channel with priority 1 dmac_rrlvlen2: Static arbitration scheme for channel with priority 2 dmac_rrlvlen3: Static arbitration scheme for channel with priority 3 dmac_runstdby_0: false dmac_runstdby_1: false dmac_runstdby_10: false dmac_runstdby_11: false dmac_runstdby_12: false dmac_runstdby_13: false dmac_runstdby_14: false dmac_runstdby_15: false dmac_runstdby_2: false dmac_runstdby_3: false dmac_runstdby_4: false dmac_runstdby_5: false dmac_runstdby_6: false dmac_runstdby_7: false dmac_runstdby_8: false dmac_runstdby_9: false dmac_srcinc_0: false dmac_srcinc_1: false dmac_srcinc_10: false dmac_srcinc_11: false dmac_srcinc_12: false dmac_srcinc_13: false dmac_srcinc_14: false dmac_srcinc_15: false dmac_srcinc_2: false dmac_srcinc_3: false dmac_srcinc_4: false dmac_srcinc_5: false dmac_srcinc_6: false dmac_srcinc_7: false dmac_srcinc_8: false dmac_srcinc_9: false dmac_stepsel_0: Step size settings apply to the destination address dmac_stepsel_1: Step size settings apply to the destination address dmac_stepsel_10: Step size settings apply to the destination address dmac_stepsel_11: Step size settings apply to the destination address dmac_stepsel_12: Step size settings apply to the destination address dmac_stepsel_13: Step size settings apply to the destination address dmac_stepsel_14: Step size settings apply to the destination address dmac_stepsel_15: Step size settings apply to the destination address dmac_stepsel_2: Step size settings apply to the destination address dmac_stepsel_3: Step size settings apply to the destination address dmac_stepsel_4: Step size settings apply to the destination address dmac_stepsel_5: Step size settings apply to the destination address dmac_stepsel_6: Step size settings apply to the destination address dmac_stepsel_7: Step size settings apply to the destination address dmac_stepsel_8: Step size settings apply to the destination address dmac_stepsel_9: Step size settings apply to the destination address dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1 dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1 dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1 dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1 dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1 dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1 dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1 dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1 dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1 dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1 dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1 dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1 dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1 dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1 dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1 dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1 dmac_trifsrc_0: Only software/event triggers dmac_trifsrc_1: Only software/event triggers dmac_trifsrc_10: Only software/event triggers dmac_trifsrc_11: Only software/event triggers dmac_trifsrc_12: Only software/event triggers dmac_trifsrc_13: Only software/event triggers dmac_trifsrc_14: Only software/event triggers dmac_trifsrc_15: Only software/event triggers dmac_trifsrc_2: Only software/event triggers dmac_trifsrc_3: Only software/event triggers dmac_trifsrc_4: Only software/event triggers dmac_trifsrc_5: Only software/event triggers dmac_trifsrc_6: Only software/event triggers dmac_trifsrc_7: Only software/event triggers dmac_trifsrc_8: Only software/event triggers dmac_trifsrc_9: Only software/event triggers dmac_trigact_0: One trigger required for each block transfer dmac_trigact_1: One trigger required for each block transfer dmac_trigact_10: One trigger required for each block transfer dmac_trigact_11: One trigger required for each block transfer dmac_trigact_12: One trigger required for each block transfer dmac_trigact_13: One trigger required for each block transfer dmac_trigact_14: One trigger required for each block transfer dmac_trigact_15: One trigger required for each block transfer dmac_trigact_2: One trigger required for each block transfer dmac_trigact_3: One trigger required for each block transfer dmac_trigact_4: One trigger required for each block transfer dmac_trigact_5: One trigger required for each block transfer dmac_trigact_6: One trigger required for each block transfer dmac_trigact_7: One trigger required for each block transfer dmac_trigact_8: One trigger required for each block transfer dmac_trigact_9: One trigger required for each block transfer dmac_wrbqos: Background (no sensitive operation) optional_signals: [] variant: null clocks: domain_group: null EXTERNAL_IRQ_0: user_label: EXTERNAL_IRQ_0 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::EIC::driver_config_definition::Default::HAL:Driver:Ext.IRQ functionality: External_IRQ api: HAL:Driver:Ext_IRQ configuration: eic_arch_asynch0: false eic_arch_asynch1: false eic_arch_asynch10: false eic_arch_asynch11: false eic_arch_asynch12: false eic_arch_asynch13: false eic_arch_asynch14: false eic_arch_asynch15: false eic_arch_asynch2: false eic_arch_asynch3: false eic_arch_asynch4: false eic_arch_asynch5: false eic_arch_asynch6: false eic_arch_asynch7: false eic_arch_asynch8: false eic_arch_asynch9: false eic_arch_cksel: Clocked by GCLK eic_arch_enable_irq_setting0: false eic_arch_enable_irq_setting1: false eic_arch_enable_irq_setting10: false eic_arch_enable_irq_setting11: false eic_arch_enable_irq_setting12: false eic_arch_enable_irq_setting13: false eic_arch_enable_irq_setting14: false eic_arch_enable_irq_setting15: false eic_arch_enable_irq_setting2: false eic_arch_enable_irq_setting3: false eic_arch_enable_irq_setting4: false eic_arch_enable_irq_setting5: true eic_arch_enable_irq_setting6: true eic_arch_enable_irq_setting7: true eic_arch_enable_irq_setting8: false eic_arch_enable_irq_setting9: false eic_arch_extinteo0: false eic_arch_extinteo1: false eic_arch_extinteo10: false eic_arch_extinteo11: false eic_arch_extinteo12: false eic_arch_extinteo13: false eic_arch_extinteo14: false eic_arch_extinteo15: false eic_arch_extinteo2: false eic_arch_extinteo3: false eic_arch_extinteo4: false eic_arch_extinteo5: false eic_arch_extinteo6: false eic_arch_extinteo7: false eic_arch_extinteo8: false eic_arch_extinteo9: false eic_arch_filten0: false eic_arch_filten1: false eic_arch_filten10: false eic_arch_filten11: false eic_arch_filten12: false eic_arch_filten13: false eic_arch_filten14: false eic_arch_filten15: false eic_arch_filten2: false eic_arch_filten3: false eic_arch_filten4: false eic_arch_filten5: false eic_arch_filten6: false eic_arch_filten7: false eic_arch_filten8: false eic_arch_filten9: false eic_arch_nmi_ctrl: false eic_arch_nmiasynch: false eic_arch_nmifilten: false eic_arch_nmisense: No detection eic_arch_sense0: No detection eic_arch_sense1: No detection eic_arch_sense10: No detection eic_arch_sense11: No detection eic_arch_sense12: No detection eic_arch_sense13: No detection eic_arch_sense14: No detection eic_arch_sense15: No detection eic_arch_sense2: No detection eic_arch_sense3: No detection eic_arch_sense4: No detection eic_arch_sense5: Rising-edge detection eic_arch_sense6: Rising-edge detection eic_arch_sense7: Rising-edge detection eic_arch_sense8: No detection eic_arch_sense9: No detection optional_signals: - identifier: EXTERNAL_IRQ_0:EXTINT/5 pad: PB05 mode: Enabled configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::EIC.EXTINT.5 name: EIC/EXTINT/5 label: EXTINT/5 - identifier: EXTERNAL_IRQ_0:EXTINT/6 pad: PA22 mode: Enabled configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::EIC.EXTINT.6 name: EIC/EXTINT/6 label: EXTINT/6 - identifier: EXTERNAL_IRQ_0:EXTINT/7 pad: PA23 mode: Enabled configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::EIC.EXTINT.7 name: EIC/EXTINT/7 label: EXTINT/7 variant: null clocks: domain_group: nodes: - name: EIC input: Generic clock generator 3 external: false external_frequency: 0 configuration: eic_gclk_selection: Generic clock generator 3 GCLK: user_label: GCLK definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK functionality: System api: HAL:HPL:GCLK configuration: $input: 400000 $input_id: External Crystal Oscillator 0.4-32MHz (XOSC) RESERVED_InputFreq: 400000 RESERVED_InputFreq_id: External Crystal Oscillator 0.4-32MHz (XOSC) _$freq_output_Generic clock generator 0: 4000000 _$freq_output_Generic clock generator 1: 400000 _$freq_output_Generic clock generator 2: 400000 _$freq_output_Generic clock generator 3: 32768 _$freq_output_Generic clock generator 4: 400000 enable_gclk_gen_0: true enable_gclk_gen_0__externalclock: 1000000 enable_gclk_gen_1: false enable_gclk_gen_1__externalclock: 1000000 enable_gclk_gen_2: false enable_gclk_gen_2__externalclock: 1000000 enable_gclk_gen_3: true enable_gclk_gen_3__externalclock: 1000000 enable_gclk_gen_4: false enable_gclk_gen_4__externalclock: 1000000 gclk_arch_gen_0_enable: true gclk_arch_gen_0_idc: false gclk_arch_gen_0_oe: false gclk_arch_gen_0_oov: false gclk_arch_gen_0_runstdby: false gclk_arch_gen_1_enable: false gclk_arch_gen_1_idc: false gclk_arch_gen_1_oe: false gclk_arch_gen_1_oov: false gclk_arch_gen_1_runstdby: false gclk_arch_gen_2_enable: false gclk_arch_gen_2_idc: false gclk_arch_gen_2_oe: false gclk_arch_gen_2_oov: false gclk_arch_gen_2_runstdby: false gclk_arch_gen_3_enable: true gclk_arch_gen_3_idc: true gclk_arch_gen_3_oe: false gclk_arch_gen_3_oov: false gclk_arch_gen_3_runstdby: true gclk_arch_gen_4_enable: false gclk_arch_gen_4_idc: false gclk_arch_gen_4_oe: false gclk_arch_gen_4_oov: false gclk_arch_gen_4_runstdby: false gclk_gen_0_div: 1 gclk_gen_0_div_sel: false gclk_gen_0_oscillator: 16MHz Internal Oscillator (OSC16M) gclk_gen_1_div: 1 gclk_gen_1_div_sel: false gclk_gen_1_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) gclk_gen_2_div: 1 gclk_gen_2_div_sel: false gclk_gen_2_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) gclk_gen_3_div: 1 gclk_gen_3_div_sel: false gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K) gclk_gen_4_div: 1 gclk_gen_4_div_sel: false gclk_gen_4_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) optional_signals: [] variant: null clocks: domain_group: null MCLK: user_label: MCLK definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK functionality: System api: HAL:HPL:MCLK configuration: $input: 4000000 $input_id: Generic clock generator 0 RESERVED_InputFreq: 4000000 RESERVED_InputFreq_id: Generic clock generator 0 _$freq_output_CPU: 4000000 cpu_clock_source: Generic clock generator 0 cpu_div: '1' enable_cpu_clock: true mclk_arch_bupdiv: Divide by 1 nvm_wait_states: '0' optional_signals: [] variant: null clocks: domain_group: nodes: - name: CPU input: CPU external: false external_frequency: 0 configuration: {} OSC32KCTRL: user_label: OSC32KCTRL definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL functionality: System api: HAL:HPL:OSC32KCTRL configuration: $input: 32768 $input_id: 32kHz External Crystal Oscillator (XOSC32K) RESERVED_InputFreq: 32768 RESERVED_InputFreq_id: 32kHz External Crystal Oscillator (XOSC32K) _$freq_output_RTC source: 1024 enable_osculp32k: true enable_rtc_source: false enable_slcd_source: false enable_xosc32k: true osculp32k_calib: 0 osculp32k_calib_enable: false rtc_1khz_selection: true rtc_source_oscillator: 32kHz External Crystal Oscillator (XOSC32K) slcd_source_oscillator: 32kHz External Crystal Oscillator (XOSC32K) xosc32k_arch_cfden: false xosc32k_arch_cfdeo: false xosc32k_arch_en1k: true xosc32k_arch_en32k: true xosc32k_arch_enable: true xosc32k_arch_ondemand: false xosc32k_arch_runstdby: true xosc32k_arch_startup: 1000092us xosc32k_arch_swben: false xosc32k_arch_xtalen: true optional_signals: [] variant: null clocks: domain_group: null OSCCTRL: user_label: OSCCTRL definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL functionality: System api: HAL:HPL:OSCCTRL configuration: $input: 32768 $input_id: 32kHz External Crystal Oscillator (XOSC32K) RESERVED_InputFreq: 32768 RESERVED_InputFreq_id: 32kHz External Crystal Oscillator (XOSC32K) _$freq_output_16MHz Internal Oscillator (OSC16M): 4000000 _$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000 _$freq_output_External Crystal Oscillator 0.4-32MHz (XOSC): 400000 _$freq_output_Fractional Digital Phase Locked Loop (FDPLL96M): 47998976 dfll48m_arch_enable: false dfll48m_mode: Open Loop Mode dfll48m_mul: 0 dfll48m_ref_clock: Generic clock generator 3 dfll_arch_bplckc: false dfll_arch_calibration: false dfll_arch_ccdis: false dfll_arch_coarse: 31 dfll_arch_cstep: 1 dfll_arch_fine: 512 dfll_arch_fstep: 1 dfll_arch_llaw: false dfll_arch_ondemand: true dfll_arch_qldis: false dfll_arch_runstdby: false dfll_arch_stable: false dfll_arch_usbcrm: false dfll_arch_waitlock: false enable_dfll48m: false enable_fdpll96m: false enable_osc16m: true enable_xosc: false fdpll96m_arch_enable: false fdpll96m_arch_filter: Default filter mode fdpll96m_arch_lbypass: false fdpll96m_arch_lpen: false fdpll96m_arch_ltime: No time-out, automatic lock fdpll96m_arch_ondemand: true fdpll96m_arch_refclk: XOSC32K clock reference fdpll96m_arch_runstdby: false fdpll96m_arch_wuf: false fdpll96m_clock_div: 0 fdpll96m_ldr: 1463 fdpll96m_ldrfrac: 13 fdpll96m_presc: '1' fdpll96m_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) osc16m_arch_12m_fcal: 0 osc16m_arch_12m_tcal: 0 osc16m_arch_16m_tcal: 0 osc16m_arch_4m_fcal: 0 osc16m_arch_4m_tcal: 0 osc16m_arch_8m_fcal: 0 osc16m_arch_8m_tcal: 0 osc16m_arch_calib_enable: false osc16m_arch_enable: true osc16m_arch_fcal: 0 osc16m_arch_ondemand: true osc16m_arch_runstdby: false osc16m_freq: '4' xosc_arch_ampgc: false xosc_arch_cfden: false xosc_arch_cfdeo: false xosc_arch_enable: false xosc_arch_gain: 2MHz xosc_arch_ondemand: true xosc_arch_runstdby: false xosc_arch_startup: 31us xosc_arch_swben: false xosc_arch_xtalen: false xosc_frequency: 400000 optional_signals: [] variant: null clocks: domain_group: null PORT: user_label: PORT definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::PORT::driver_config_definition::PORT::HAL:HPL:PORT functionality: System api: HAL:HPL:PORT configuration: enable_port_input_event_0: false enable_port_input_event_1: false enable_port_input_event_2: false enable_port_input_event_3: false porta_event_action_0: Output register of pin will be set to level of event porta_event_action_1: Output register of pin will be set to level of event porta_event_action_2: Output register of pin will be set to level of event porta_event_action_3: Output register of pin will be set to level of event porta_event_pin_identifier_0: 0 porta_event_pin_identifier_1: 0 porta_event_pin_identifier_2: 0 porta_event_pin_identifier_3: 0 porta_input_event_enable_0: false porta_input_event_enable_1: false porta_input_event_enable_2: false porta_input_event_enable_3: false portb_event_action_0: Output register of pin will be set to level of event portb_event_action_1: Output register of pin will be set to level of event portb_event_action_2: Output register of pin will be set to level of event portb_event_action_3: Output register of pin will be set to level of event portb_event_pin_identifier_0: 0 portb_event_pin_identifier_1: 0 portb_event_pin_identifier_2: 0 portb_event_pin_identifier_3: 0 portb_input_event_enable_0: false portb_input_event_enable_1: false portb_input_event_enable_2: false portb_input_event_enable_3: false optional_signals: [] variant: null clocks: domain_group: null CALENDAR_0: user_label: CALENDAR_0 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::RTC::driver_config_definition::Calendar::HAL:Driver:Calendar functionality: Calendar api: HAL:Driver:Calendar configuration: rtc_arch_init_reset: false rtc_arch_prescaler: Peripheral clock divided by 1024 rtc_cmpeo0: false rtc_event_control: false rtc_ovfeo: false rtc_pereo0: false rtc_pereo1: false rtc_pereo2: false rtc_pereo3: false rtc_pereo4: false rtc_pereo5: false rtc_pereo6: false rtc_pereo7: false rtc_tamper_active_layer_frequency_prescalar: DIV2 CLK_RTC_OUT is CLK_RTC /2 rtc_tamper_debounce_frequency_prescalar: DIV2 CLK_RTC_DEB is CLK_RTC /2 rtc_tamper_input_action_0: OFF(Disabled) rtc_tamper_input_action_1: OFF(Disabled) rtc_tamper_input_action_2: OFF(Disabled) rtc_tamper_input_action_3: OFF(Disabled) rtc_tamper_input_action_4: OFF(Disabled) tamper_debounce_enable_0: false tamper_debounce_enable_1: false tamper_debounce_enable_2: false tamper_debounce_enable_3: false tamper_debounce_enable_4: false tamper_input_0_settings: false tamper_input_1_settings: false tamper_input_2_settings: false tamper_input_3_settings: false tamper_input_4_settings: false tamper_level_0: false tamper_level_1: false tamper_level_2: false tamper_level_3: false tamper_level_4: false optional_signals: [] variant: null clocks: domain_group: nodes: - name: RTC input: RTC source external: false external_frequency: 0 configuration: rtc_clk_selection: RTC source I2C_0: user_label: I2C_0 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::SERCOM1::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync functionality: I2C api: HAL:Driver:I2C_Master_Sync configuration: i2c_master_advanced: false i2c_master_arch_dbgstop: Keep running i2c_master_arch_inactout: Disabled i2c_master_arch_lowtout: false i2c_master_arch_mexttoen: false i2c_master_arch_runstdby: false i2c_master_arch_sdahold: 300-600ns hold time i2c_master_arch_sexttoen: false i2c_master_arch_trise: 215 i2c_master_baud_rate: 100000 optional_signals: [] variant: specification: SDA=0, SCL=1 required_signals: - name: SERCOM1/PAD/0 pad: PB30 label: SDA - name: SERCOM1/PAD/1 pad: PB31 label: SCL clocks: domain_group: nodes: - name: Core input: Generic clock generator 0 external: false external_frequency: 0 - name: Slow input: Generic clock generator 3 external: false external_frequency: 0 configuration: core_gclk_selection: Generic clock generator 0 slow_gclk_selection: Generic clock generator 3 DELAY_0: user_label: DELAY_0 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::SysTick::driver_config_definition::Delay::HAL:Driver:Delay functionality: Delay api: HAL:Driver:Delay configuration: systick_arch_tickint: false optional_signals: [] variant: null clocks: domain_group: null PWM_0: user_label: PWM_0 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::TC3::driver_config_definition::8-bit.Waveform.Mode::Lite:TC:PWM functionality: PWM api: Lite:TC:PWM configuration: cc_cc0: 0 cc_cc1: 0 cc_control: false count_control: false count_count: 0 ctrla_alock: false ctrla_capten0: false ctrla_capten1: false ctrla_control: false ctrla_copen0: false ctrla_copen1: false ctrla_enable: true ctrla_mode: 1 ctrla_ondemand: false ctrla_prescaler: DIV1 ctrla_prescsync: GCLK ctrla_runstdby: false ctrlbset_cmd: NONE ctrlbset_control: false ctrlbset_dir: false ctrlbset_lupd: false ctrlbset_oneshot: false ctrlc_inven0: false ctrlc_inven1: false dbgctrl_control: false dbgctrl_dbgrun: false drvctrl_control: false evctrl_control: false evctrl_evact: 'OFF' evctrl_mceo0: false evctrl_mceo1: false evctrl_ovfeo: false evctrl_tcei: false evctrl_tcinv: false intenset_control: false intenset_err: false intenset_mc0: false intenset_mc1: false intenset_ovf: false per_control: false per_per: 0 wave_control: false wave_wavegen: NFRQ optional_signals: - identifier: PWM_0:WO/0 pad: PA20 mode: PWM output configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::TC3.WO.0 name: TC3/WO/0 label: WO/0 - identifier: PWM_0:WO/1 pad: PA21 mode: PWM output configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::TC3.WO.1 name: TC3/WO/1 label: WO/1 variant: null clocks: domain_group: nodes: - name: TC input: Generic clock generator 0 external: false external_frequency: 0 configuration: tc_gclk_selection: Generic clock generator 0 PWM_1: user_label: PWM_1 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::TCC0::driver_config_definition::PWM::HAL:Driver:PWM functionality: PWM api: HAL:Driver:PWM configuration: tcc_arch_alock: false tcc_arch_cc0: 0 tcc_arch_cc1: 0 tcc_arch_cc2: 0 tcc_arch_cc3: 0 tcc_arch_cnteo: false tcc_arch_cntsel: An interrupt/event is generated when a new counter cycle starts tcc_arch_cpten0: false tcc_arch_cpten1: false tcc_arch_cpten2: false tcc_arch_cpten3: false tcc_arch_cpten4: false tcc_arch_cpten5: false tcc_arch_cpten6: false tcc_arch_cpten7: false tcc_arch_dbgrun: false tcc_arch_evact0: Event action disabled tcc_arch_evact1: Event action disabled tcc_arch_lupd: true tcc_arch_mcei0: false tcc_arch_mcei1: false tcc_arch_mcei2: false tcc_arch_mcei3: false tcc_arch_mceo0: false tcc_arch_mceo1: false tcc_arch_mceo2: false tcc_arch_mceo3: false tcc_arch_ovfeo: false tcc_arch_prescsync: Reload or reset counter on next GCLK tcc_arch_runstdby: false tcc_arch_sel_ch: 1 tcc_arch_tcei0: false tcc_arch_tcei1: false tcc_arch_tceinv0: false tcc_arch_tceinv1: false tcc_arch_trgeo: false tcc_arch_wave_duty_val: 500 tcc_arch_wave_per_val: 1000 tcc_arch_wavegen: Single-slope PWM tcc_per: 10000 tcc_prescaler: Divide by 8 timer_event_control: false optional_signals: - identifier: PWM_1:WO/5 pad: PA27 mode: PWM output configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::TCC0.WO.5 name: TCC0/WO/5 label: WO/5 variant: null clocks: domain_group: nodes: - name: TCC input: Generic clock generator 0 external: false external_frequency: 0 configuration: tcc_gclk_selection: Generic clock generator 0 SEGMENT_LCD_0: user_label: SEGMENT_LCD_0 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::SLCD::driver_config_definition::SLCD::HAL:Driver:SLCD.Sync functionality: Segment_LCD api: HAL:Driver:SLCD_Sync configuration: slcd_arch_advanced_settings: true slcd_arch_bbd: 2 slcd_arch_bben: true slcd_arch_bias: THIRD slcd_arch_char0_com_idx: 0 slcd_arch_char0_mapping_table: 7 Segments Mapping Table slcd_arch_char0_seg_idx: 1 slcd_arch_char0_seg_num: 1 slcd_arch_char0_setting: false slcd_arch_char10_com_idx: 0 slcd_arch_char10_mapping_table: 7 Segments Mapping Table slcd_arch_char10_seg_idx: 1 slcd_arch_char10_seg_num: 1 slcd_arch_char10_setting: false slcd_arch_char11_com_idx: 0 slcd_arch_char11_mapping_table: 7 Segments Mapping Table slcd_arch_char11_seg_idx: 1 slcd_arch_char11_seg_num: 1 slcd_arch_char11_setting: false slcd_arch_char12_com_idx: 0 slcd_arch_char12_mapping_table: 7 Segments Mapping Table slcd_arch_char12_seg_idx: 1 slcd_arch_char12_seg_num: 1 slcd_arch_char12_setting: false slcd_arch_char13_com_idx: 0 slcd_arch_char13_mapping_table: 7 Segments Mapping Table slcd_arch_char13_seg_idx: 1 slcd_arch_char13_seg_num: 1 slcd_arch_char13_setting: false slcd_arch_char14_com_idx: 0 slcd_arch_char14_mapping_table: 7 Segments Mapping Table slcd_arch_char14_seg_idx: 1 slcd_arch_char14_seg_num: 1 slcd_arch_char14_setting: false slcd_arch_char15_com_idx: 0 slcd_arch_char15_mapping_table: 7 Segments Mapping Table slcd_arch_char15_seg_idx: 1 slcd_arch_char15_seg_num: 1 slcd_arch_char15_setting: false slcd_arch_char16_com_idx: 0 slcd_arch_char16_mapping_table: 7 Segments Mapping Table slcd_arch_char16_seg_idx: 1 slcd_arch_char16_seg_num: 1 slcd_arch_char16_setting: false slcd_arch_char17_com_idx: 0 slcd_arch_char17_mapping_table: 7 Segments Mapping Table slcd_arch_char17_seg_idx: 1 slcd_arch_char17_seg_num: 1 slcd_arch_char17_setting: false slcd_arch_char18_com_idx: 0 slcd_arch_char18_mapping_table: 7 Segments Mapping Table slcd_arch_char18_seg_idx: 1 slcd_arch_char18_seg_num: 1 slcd_arch_char18_setting: false slcd_arch_char19_com_idx: 0 slcd_arch_char19_mapping_table: 7 Segments Mapping Table slcd_arch_char19_seg_idx: 1 slcd_arch_char19_seg_num: 1 slcd_arch_char19_setting: false slcd_arch_char1_com_idx: 0 slcd_arch_char1_mapping_table: 7 Segments Mapping Table slcd_arch_char1_seg_idx: 1 slcd_arch_char1_seg_num: 1 slcd_arch_char1_setting: false slcd_arch_char20_com_idx: 0 slcd_arch_char20_mapping_table: 7 Segments Mapping Table slcd_arch_char20_seg_idx: 1 slcd_arch_char20_seg_num: 1 slcd_arch_char20_setting: false slcd_arch_char21_com_idx: 0 slcd_arch_char21_mapping_table: 7 Segments Mapping Table slcd_arch_char21_seg_idx: 1 slcd_arch_char21_seg_num: 1 slcd_arch_char21_setting: false slcd_arch_char22_com_idx: 0 slcd_arch_char22_mapping_table: 7 Segments Mapping Table slcd_arch_char22_seg_idx: 1 slcd_arch_char22_seg_num: 1 slcd_arch_char22_setting: false slcd_arch_char23_com_idx: 0 slcd_arch_char23_mapping_table: 7 Segments Mapping Table slcd_arch_char23_seg_idx: 1 slcd_arch_char23_seg_num: 1 slcd_arch_char23_setting: false slcd_arch_char24_com_idx: 0 slcd_arch_char24_mapping_table: 7 Segments Mapping Table slcd_arch_char24_seg_idx: 1 slcd_arch_char24_seg_num: 1 slcd_arch_char24_setting: false slcd_arch_char25_com_idx: 0 slcd_arch_char25_mapping_table: 7 Segments Mapping Table slcd_arch_char25_seg_idx: 1 slcd_arch_char25_seg_num: 1 slcd_arch_char25_setting: false slcd_arch_char26_com_idx: 0 slcd_arch_char26_mapping_table: 7 Segments Mapping Table slcd_arch_char26_seg_idx: 1 slcd_arch_char26_seg_num: 1 slcd_arch_char26_setting: false slcd_arch_char27_com_idx: 0 slcd_arch_char27_mapping_table: 7 Segments Mapping Table slcd_arch_char27_seg_idx: 1 slcd_arch_char27_seg_num: 1 slcd_arch_char27_setting: false slcd_arch_char28_com_idx: 0 slcd_arch_char28_mapping_table: 7 Segments Mapping Table slcd_arch_char28_seg_idx: 1 slcd_arch_char28_seg_num: 1 slcd_arch_char28_setting: false slcd_arch_char29_com_idx: 0 slcd_arch_char29_mapping_table: 7 Segments Mapping Table slcd_arch_char29_seg_idx: 1 slcd_arch_char29_seg_num: 1 slcd_arch_char29_setting: false slcd_arch_char2_com_idx: 0 slcd_arch_char2_mapping_table: 7 Segments Mapping Table slcd_arch_char2_seg_idx: 1 slcd_arch_char2_seg_num: 1 slcd_arch_char2_setting: false slcd_arch_char30_com_idx: 0 slcd_arch_char30_mapping_table: 7 Segments Mapping Table slcd_arch_char30_seg_idx: 1 slcd_arch_char30_seg_num: 1 slcd_arch_char30_setting: false slcd_arch_char31_com_idx: 0 slcd_arch_char31_mapping_table: 7 Segments Mapping Table slcd_arch_char31_seg_idx: 1 slcd_arch_char31_seg_num: 1 slcd_arch_char31_setting: false slcd_arch_char32_com_idx: 0 slcd_arch_char32_mapping_table: 7 Segments Mapping Table slcd_arch_char32_seg_idx: 1 slcd_arch_char32_seg_num: 1 slcd_arch_char32_setting: false slcd_arch_char33_com_idx: 0 slcd_arch_char33_mapping_table: 7 Segments Mapping Table slcd_arch_char33_seg_idx: 1 slcd_arch_char33_seg_num: 1 slcd_arch_char33_setting: false slcd_arch_char34_com_idx: 0 slcd_arch_char34_mapping_table: 7 Segments Mapping Table slcd_arch_char34_seg_idx: 1 slcd_arch_char34_seg_num: 1 slcd_arch_char34_setting: false slcd_arch_char35_com_idx: 0 slcd_arch_char35_mapping_table: 7 Segments Mapping Table slcd_arch_char35_seg_idx: 1 slcd_arch_char35_seg_num: 1 slcd_arch_char35_setting: false slcd_arch_char36_com_idx: 0 slcd_arch_char36_mapping_table: 7 Segments Mapping Table slcd_arch_char36_seg_idx: 1 slcd_arch_char36_seg_num: 1 slcd_arch_char36_setting: false slcd_arch_char37_com_idx: 0 slcd_arch_char37_mapping_table: 7 Segments Mapping Table slcd_arch_char37_seg_idx: 1 slcd_arch_char37_seg_num: 1 slcd_arch_char37_setting: false slcd_arch_char38_com_idx: 0 slcd_arch_char38_mapping_table: 7 Segments Mapping Table slcd_arch_char38_seg_idx: 1 slcd_arch_char38_seg_num: 1 slcd_arch_char38_setting: false slcd_arch_char39_com_idx: 0 slcd_arch_char39_mapping_table: 7 Segments Mapping Table slcd_arch_char39_seg_idx: 1 slcd_arch_char39_seg_num: 1 slcd_arch_char39_setting: false slcd_arch_char3_com_idx: 0 slcd_arch_char3_mapping_table: 7 Segments Mapping Table slcd_arch_char3_seg_idx: 1 slcd_arch_char3_seg_num: 1 slcd_arch_char3_setting: false slcd_arch_char40_com_idx: 0 slcd_arch_char40_mapping_table: 7 Segments Mapping Table slcd_arch_char40_seg_idx: 1 slcd_arch_char40_seg_num: 1 slcd_arch_char40_setting: false slcd_arch_char41_com_idx: 0 slcd_arch_char41_mapping_table: 7 Segments Mapping Table slcd_arch_char41_seg_idx: 1 slcd_arch_char41_seg_num: 1 slcd_arch_char41_setting: false slcd_arch_char42_com_idx: 0 slcd_arch_char42_mapping_table: 7 Segments Mapping Table slcd_arch_char42_seg_idx: 1 slcd_arch_char42_seg_num: 1 slcd_arch_char42_setting: false slcd_arch_char43_com_idx: 0 slcd_arch_char43_mapping_table: 7 Segments Mapping Table slcd_arch_char43_seg_idx: 1 slcd_arch_char43_seg_num: 1 slcd_arch_char43_setting: false slcd_arch_char4_com_idx: 0 slcd_arch_char4_mapping_table: 7 Segments Mapping Table slcd_arch_char4_seg_idx: 1 slcd_arch_char4_seg_num: 1 slcd_arch_char4_setting: false slcd_arch_char5_com_idx: 0 slcd_arch_char5_mapping_table: 7 Segments Mapping Table slcd_arch_char5_seg_idx: 1 slcd_arch_char5_seg_num: 1 slcd_arch_char5_setting: false slcd_arch_char6_com_idx: 0 slcd_arch_char6_mapping_table: 7 Segments Mapping Table slcd_arch_char6_seg_idx: 1 slcd_arch_char6_seg_num: 1 slcd_arch_char6_setting: false slcd_arch_char7_com_idx: 0 slcd_arch_char7_mapping_table: 7 Segments Mapping Table slcd_arch_char7_seg_idx: 1 slcd_arch_char7_seg_num: 1 slcd_arch_char7_setting: false slcd_arch_char8_com_idx: 0 slcd_arch_char8_mapping_table: 7 Segments Mapping Table slcd_arch_char8_seg_idx: 1 slcd_arch_char8_seg_num: 1 slcd_arch_char8_setting: false slcd_arch_char9_com_idx: 0 slcd_arch_char9_mapping_table: 7 Segments Mapping Table slcd_arch_char9_seg_idx: 1 slcd_arch_char9_seg_num: 1 slcd_arch_char9_setting: false slcd_arch_ckdiv: '4' slcd_arch_cm_14segs_0_mapping_setting: '0' slcd_arch_cm_14segs_10_mapping_setting: '10' slcd_arch_cm_14segs_11_mapping_setting: '11' slcd_arch_cm_14segs_12_mapping_setting: '12' slcd_arch_cm_14segs_13_mapping_setting: '13' slcd_arch_cm_14segs_1_mapping_setting: '1' slcd_arch_cm_14segs_2_mapping_setting: '2' slcd_arch_cm_14segs_3_mapping_setting: '3' slcd_arch_cm_14segs_4_mapping_setting: '4' slcd_arch_cm_14segs_5_mapping_setting: '5' slcd_arch_cm_14segs_6_mapping_setting: '6' slcd_arch_cm_14segs_7_mapping_setting: '7' slcd_arch_cm_14segs_8_mapping_setting: '8' slcd_arch_cm_14segs_9_mapping_setting: '9' slcd_arch_cm_14segs_enable: false slcd_arch_cm_7segs_0_mapping_setting: '0' slcd_arch_cm_7segs_1_mapping_setting: '1' slcd_arch_cm_7segs_2_mapping_setting: '2' slcd_arch_cm_7segs_3_mapping_setting: '3' slcd_arch_cm_7segs_4_mapping_setting: '4' slcd_arch_cm_7segs_5_mapping_setting: '5' slcd_arch_cm_7segs_6_mapping_setting: '6' slcd_arch_cm_7segs_setting: false slcd_arch_cm_setting: false slcd_arch_com_num: '3' slcd_arch_contrast_adjust: 3.4398V slcd_arch_presc: '64' slcd_arch_prf: 250Hz slcd_arch_rrf: 2kHz slcd_arch_runstdby: true slcd_arch_seg_num: 24 slcd_arch_wmod: Low Power Waveform(frame-inversion) slcd_arch_xvlcd: false optional_signals: - identifier: SEGMENT_LCD_0:LP/0 pad: PB06 mode: LCD pin configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.0 name: SLCD/LP/0 label: LP/0 - identifier: SEGMENT_LCD_0:LP/1 pad: PB07 mode: LCD pin configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.1 name: SLCD/LP/1 label: LP/1 - identifier: SEGMENT_LCD_0:LP/2 pad: PB08 mode: LCD pin configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.2 name: SLCD/LP/2 label: LP/2 - identifier: SEGMENT_LCD_0:LP/3 pad: PB09 mode: LCD pin configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.3 name: SLCD/LP/3 label: LP/3 - identifier: SEGMENT_LCD_0:LP/4 pad: PA04 mode: LCD pin configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.4 name: SLCD/LP/4 label: LP/4 - identifier: SEGMENT_LCD_0:LP/5 pad: PA05 mode: LCD pin configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.5 name: SLCD/LP/5 label: LP/5 - identifier: SEGMENT_LCD_0:LP/6 pad: PA06 mode: LCD pin configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.6 name: SLCD/LP/6 label: LP/6 - identifier: SEGMENT_LCD_0:LP/7 pad: PA07 mode: LCD pin configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.7 name: SLCD/LP/7 label: LP/7 - identifier: SEGMENT_LCD_0:LP/11 pad: PA08 mode: LCD pin configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.11 name: SLCD/LP/11 label: LP/11 - identifier: SEGMENT_LCD_0:LP/12 pad: PA09 mode: LCD pin configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.12 name: SLCD/LP/12 label: LP/12 - identifier: SEGMENT_LCD_0:LP/13 pad: PA10 mode: LCD pin configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.13 name: SLCD/LP/13 label: LP/13 - identifier: SEGMENT_LCD_0:LP/14 pad: PA11 mode: LCD pin configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.14 name: SLCD/LP/14 label: LP/14 - identifier: SEGMENT_LCD_0:LP/21 pad: PB11 mode: LCD pin configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.21 name: SLCD/LP/21 label: LP/21 - identifier: SEGMENT_LCD_0:LP/22 pad: PB12 mode: LCD pin configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.22 name: SLCD/LP/22 label: LP/22 - identifier: SEGMENT_LCD_0:LP/23 pad: PB13 mode: LCD pin configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.23 name: SLCD/LP/23 label: LP/23 - identifier: SEGMENT_LCD_0:LP/24 pad: PB14 mode: LCD pin configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.24 name: SLCD/LP/24 label: LP/24 - identifier: SEGMENT_LCD_0:LP/25 pad: PB15 mode: LCD pin configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.25 name: SLCD/LP/25 label: LP/25 - identifier: SEGMENT_LCD_0:LP/28 pad: PA12 mode: LCD pin configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.28 name: SLCD/LP/28 label: LP/28 - identifier: SEGMENT_LCD_0:LP/29 pad: PA13 mode: LCD pin configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.29 name: SLCD/LP/29 label: LP/29 - identifier: SEGMENT_LCD_0:LP/30 pad: PA14 mode: LCD pin configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.30 name: SLCD/LP/30 label: LP/30 - identifier: SEGMENT_LCD_0:LP/31 pad: PA15 mode: LCD pin configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.31 name: SLCD/LP/31 label: LP/31 - identifier: SEGMENT_LCD_0:LP/32 pad: PA16 mode: LCD pin configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.32 name: SLCD/LP/32 label: LP/32 - identifier: SEGMENT_LCD_0:LP/33 pad: PA17 mode: LCD pin configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.33 name: SLCD/LP/33 label: LP/33 - identifier: SEGMENT_LCD_0:LP/34 pad: PA18 mode: LCD pin configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.34 name: SLCD/LP/34 label: LP/34 - identifier: SEGMENT_LCD_0:LP/35 pad: PA19 mode: LCD pin configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.35 name: SLCD/LP/35 label: LP/35 - identifier: SEGMENT_LCD_0:LP/42 pad: PB16 mode: LCD pin configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.42 name: SLCD/LP/42 label: LP/42 - identifier: SEGMENT_LCD_0:LP/43 pad: PB17 mode: LCD pin configuration: null definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::optional_signal_definition::SLCD.LP.43 name: SLCD/LP/43 label: LP/43 variant: null clocks: domain_group: nodes: - name: SLCD input: SLCD source external: false external_frequency: 0 configuration: slcd_clk_selection: SLCD source pads: VBUS_DET: name: PA02 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA02 mode: Digital input user_label: VBUS_DET configuration: pad_pull_config: Pull-down A0: name: PB04 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB04 mode: Analog user_label: A0 configuration: null BTN_ALARM: name: PB05 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB05 mode: Digital input user_label: BTN_ALARM configuration: pad_pull_config: Pull-down COM0: name: PB06 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB06 mode: Peripheral IO user_label: COM0 configuration: null COM1: name: PB07 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB07 mode: Peripheral IO user_label: COM1 configuration: null COM2: name: PB08 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB08 mode: Peripheral IO user_label: COM2 configuration: null SEG0: name: PB09 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB09 mode: Peripheral IO user_label: SEG0 configuration: null SEG1: name: PA04 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA04 mode: Peripheral IO user_label: SEG1 configuration: null SEG2: name: PA05 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA05 mode: Peripheral IO user_label: SEG2 configuration: null SEG3: name: PA06 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA06 mode: Peripheral IO user_label: SEG3 configuration: null SEG4: name: PA07 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA07 mode: Peripheral IO user_label: SEG4 configuration: null SEG5: name: PA08 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA08 mode: Peripheral IO user_label: SEG5 configuration: null SEG6: name: PA09 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA09 mode: Peripheral IO user_label: SEG6 configuration: null SEG7: name: PA10 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA10 mode: Peripheral IO user_label: SEG7 configuration: null SEG8: name: PA11 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA11 mode: Peripheral IO user_label: SEG8 configuration: null SEG9: name: PB11 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB11 mode: Peripheral IO user_label: SEG9 configuration: null SEG10: name: PB12 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB12 mode: Peripheral IO user_label: SEG10 configuration: null SEG11: name: PB13 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB13 mode: Peripheral IO user_label: SEG11 configuration: null SEG12: name: PB14 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB14 mode: Peripheral IO user_label: SEG12 configuration: null SEG13: name: PB15 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB15 mode: Peripheral IO user_label: SEG13 configuration: null SEG14: name: PA12 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA12 mode: Peripheral IO user_label: SEG14 configuration: null SEG15: name: PA13 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA13 mode: Peripheral IO user_label: SEG15 configuration: null SEG16: name: PA14 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA14 mode: Peripheral IO user_label: SEG16 configuration: null SEG17: name: PA15 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA15 mode: Peripheral IO user_label: SEG17 configuration: null SEG18: name: PA16 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA16 mode: Peripheral IO user_label: SEG18 configuration: null SEG19: name: PA17 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA17 mode: Peripheral IO user_label: SEG19 configuration: null SEG20: name: PA18 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA18 mode: Peripheral IO user_label: SEG20 configuration: null SEG21: name: PA19 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA19 mode: Peripheral IO user_label: SEG21 configuration: null SEG22: name: PB16 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB16 mode: Peripheral IO user_label: SEG22 configuration: null SEG23: name: PB17 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB17 mode: Peripheral IO user_label: SEG23 configuration: null RED: name: PA20 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA20 mode: Peripheral IO user_label: RED configuration: null GREEN: name: PA21 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA21 mode: Peripheral IO user_label: GREEN configuration: null BTN_LIGHT: name: PA22 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA22 mode: Digital input user_label: BTN_LIGHT configuration: pad_pull_config: Pull-down BTN_MODE: name: PA23 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA23 mode: Digital input user_label: BTN_MODE configuration: pad_pull_config: Pull-down BUZZER: name: PA27 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PA27 mode: Peripheral IO user_label: BUZZER configuration: null SDA: name: PB30 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB30 mode: I2C user_label: SDA configuration: null SCL: name: PB31 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB31 mode: I2C user_label: SCL configuration: null D1: name: PB00 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB00 mode: Digital output user_label: D1 configuration: null A1: name: PB01 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB01 mode: Analog user_label: A1 configuration: null A2: name: PB02 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB02 mode: Analog user_label: A2 configuration: null D0: name: PB03 definition: Atmel:SAML22_Drivers:0.0.1::SAML22J18A-AN::pad::PB03 mode: Digital output user_label: D0 configuration: null toolchain_options: []