diff options
Diffstat (limited to 'Smol Watch Project/My Project/Debug/My Project.lss')
| -rw-r--r-- | Smol Watch Project/My Project/Debug/My Project.lss | 5931 |
1 files changed, 5931 insertions, 0 deletions
diff --git a/Smol Watch Project/My Project/Debug/My Project.lss b/Smol Watch Project/My Project/Debug/My Project.lss new file mode 100644 index 00000000..b6e56b2d --- /dev/null +++ b/Smol Watch Project/My Project/Debug/My Project.lss @@ -0,0 +1,5931 @@ +
+My Project.elf: file format elf32-littlearm
+
+Sections:
+Idx Name Size VMA LMA File off Algn
+ 0 .text 00002140 00000000 00000000 00010000 2**2
+ CONTENTS, ALLOC, LOAD, READONLY, CODE
+ 1 .relocate 00000038 20000000 00002140 00020000 2**2
+ CONTENTS, ALLOC, LOAD, DATA
+ 2 .bss 000000e4 20000038 00002178 00020038 2**2
+ ALLOC
+ 3 .stack 00002004 2000011c 0000225c 00020038 2**0
+ ALLOC
+ 4 .ARM.attributes 00000028 00000000 00000000 00020038 2**0
+ CONTENTS, READONLY
+ 5 .comment 00000059 00000000 00000000 00020060 2**0
+ CONTENTS, READONLY
+ 6 .debug_info 000315e1 00000000 00000000 000200b9 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 7 .debug_abbrev 00004084 00000000 00000000 0005169a 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 8 .debug_loc 00011a80 00000000 00000000 0005571e 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 9 .debug_aranges 00000d00 00000000 00000000 0006719e 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 10 .debug_ranges 00000d80 00000000 00000000 00067e9e 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 11 .debug_macro 0001de3f 00000000 00000000 00068c1e 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 12 .debug_line 00015702 00000000 00000000 00086a5d 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 13 .debug_str 000912d9 00000000 00000000 0009c15f 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 14 .debug_frame 000020dc 00000000 00000000 0012d438 2**2
+ CONTENTS, READONLY, DEBUGGING
+
+Disassembly of section .text:
+
+00000000 <exception_table>:
+ 0: 20 21 00 20 21 01 00 00 1d 01 00 00 1d 01 00 00 !. !...........
+ ...
+ 2c: 1d 01 00 00 00 00 00 00 00 00 00 00 1d 01 00 00 ................
+ 3c: 1d 01 00 00 1d 01 00 00 1d 01 00 00 89 0e 00 00 ................
+ 4c: 35 0c 00 00 1d 01 00 00 1d 01 00 00 1d 01 00 00 5...............
+ 5c: 1d 01 00 00 1d 01 00 00 1d 01 00 00 1d 01 00 00 ................
+ 6c: 1d 01 00 00 1d 01 00 00 00 00 00 00 00 00 00 00 ................
+ 7c: ad 15 00 00 1d 01 00 00 1d 01 00 00 1d 01 00 00 ................
+ 8c: e5 19 00 00 1d 01 00 00 1d 01 00 00 1d 01 00 00 ................
+ 9c: 1d 01 00 00 1d 01 00 00 1d 01 00 00 ............
+
+000000a8 <__do_global_dtors_aux>:
+ a8: b510 push {r4, lr}
+ aa: 4c06 ldr r4, [pc, #24] ; (c4 <__do_global_dtors_aux+0x1c>)
+ ac: 7823 ldrb r3, [r4, #0]
+ ae: 2b00 cmp r3, #0
+ b0: d107 bne.n c2 <__do_global_dtors_aux+0x1a>
+ b2: 4b05 ldr r3, [pc, #20] ; (c8 <__do_global_dtors_aux+0x20>)
+ b4: 2b00 cmp r3, #0
+ b6: d002 beq.n be <__do_global_dtors_aux+0x16>
+ b8: 4804 ldr r0, [pc, #16] ; (cc <__do_global_dtors_aux+0x24>)
+ ba: e000 b.n be <__do_global_dtors_aux+0x16>
+ bc: bf00 nop
+ be: 2301 movs r3, #1
+ c0: 7023 strb r3, [r4, #0]
+ c2: bd10 pop {r4, pc}
+ c4: 20000038 .word 0x20000038
+ c8: 00000000 .word 0x00000000
+ cc: 00002140 .word 0x00002140
+
+000000d0 <frame_dummy>:
+ d0: 4b08 ldr r3, [pc, #32] ; (f4 <frame_dummy+0x24>)
+ d2: b510 push {r4, lr}
+ d4: 2b00 cmp r3, #0
+ d6: d003 beq.n e0 <frame_dummy+0x10>
+ d8: 4907 ldr r1, [pc, #28] ; (f8 <frame_dummy+0x28>)
+ da: 4808 ldr r0, [pc, #32] ; (fc <frame_dummy+0x2c>)
+ dc: e000 b.n e0 <frame_dummy+0x10>
+ de: bf00 nop
+ e0: 4807 ldr r0, [pc, #28] ; (100 <frame_dummy+0x30>)
+ e2: 6803 ldr r3, [r0, #0]
+ e4: 2b00 cmp r3, #0
+ e6: d100 bne.n ea <frame_dummy+0x1a>
+ e8: bd10 pop {r4, pc}
+ ea: 4b06 ldr r3, [pc, #24] ; (104 <frame_dummy+0x34>)
+ ec: 2b00 cmp r3, #0
+ ee: d0fb beq.n e8 <frame_dummy+0x18>
+ f0: 4798 blx r3
+ f2: e7f9 b.n e8 <frame_dummy+0x18>
+ f4: 00000000 .word 0x00000000
+ f8: 2000003c .word 0x2000003c
+ fc: 00002140 .word 0x00002140
+ 100: 00002140 .word 0x00002140
+ 104: 00000000 .word 0x00000000
+
+00000108 <atmel_start_init>:
+
+/**
+ * Initializes MCU, drivers and middleware in the project
+ **/
+void atmel_start_init(void)
+{
+ 108: b510 push {r4, lr}
+ system_init();
+ 10a: 4b02 ldr r3, [pc, #8] ; (114 <atmel_start_init+0xc>)
+ 10c: 4798 blx r3
+ sleep_manager_init();
+ 10e: 4b02 ldr r3, [pc, #8] ; (118 <atmel_start_init+0x10>)
+ 110: 4798 blx r3
+}
+ 112: bd10 pop {r4, pc}
+ 114: 00000309 .word 0x00000309
+ 118: 00001b8d .word 0x00001b8d
+
+0000011c <Dummy_Handler>:
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+ 11c: e7fe b.n 11c <Dummy_Handler>
+ ...
+
+00000120 <Reset_Handler>:
+{
+ 120: b510 push {r4, lr}
+ if (pSrc != pDest) {
+ 122: 4a10 ldr r2, [pc, #64] ; (164 <Reset_Handler+0x44>)
+ 124: 4b10 ldr r3, [pc, #64] ; (168 <Reset_Handler+0x48>)
+ 126: 429a cmp r2, r3
+ 128: d009 beq.n 13e <Reset_Handler+0x1e>
+ 12a: 4b0f ldr r3, [pc, #60] ; (168 <Reset_Handler+0x48>)
+ 12c: 4a0d ldr r2, [pc, #52] ; (164 <Reset_Handler+0x44>)
+ 12e: e003 b.n 138 <Reset_Handler+0x18>
+ *pDest++ = *pSrc++;
+ 130: 6811 ldr r1, [r2, #0]
+ 132: 6019 str r1, [r3, #0]
+ 134: 3304 adds r3, #4
+ 136: 3204 adds r2, #4
+ for (; pDest < &_erelocate;) {
+ 138: 490c ldr r1, [pc, #48] ; (16c <Reset_Handler+0x4c>)
+ 13a: 428b cmp r3, r1
+ 13c: d3f8 bcc.n 130 <Reset_Handler+0x10>
+ *pDest++ = *pSrc++;
+ 13e: 4b0c ldr r3, [pc, #48] ; (170 <Reset_Handler+0x50>)
+ 140: e002 b.n 148 <Reset_Handler+0x28>
+ *pDest++ = 0;
+ 142: 2200 movs r2, #0
+ 144: 601a str r2, [r3, #0]
+ 146: 3304 adds r3, #4
+ for (pDest = &_szero; pDest < &_ezero;) {
+ 148: 4a0a ldr r2, [pc, #40] ; (174 <Reset_Handler+0x54>)
+ 14a: 4293 cmp r3, r2
+ 14c: d3f9 bcc.n 142 <Reset_Handler+0x22>
+ SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+ 14e: 4a0a ldr r2, [pc, #40] ; (178 <Reset_Handler+0x58>)
+ 150: 21ff movs r1, #255 ; 0xff
+ 152: 4b0a ldr r3, [pc, #40] ; (17c <Reset_Handler+0x5c>)
+ 154: 438b bics r3, r1
+ 156: 6093 str r3, [r2, #8]
+ __libc_init_array();
+ 158: 4b09 ldr r3, [pc, #36] ; (180 <Reset_Handler+0x60>)
+ 15a: 4798 blx r3
+ main();
+ 15c: 4b09 ldr r3, [pc, #36] ; (184 <Reset_Handler+0x64>)
+ 15e: 4798 blx r3
+ 160: e7fe b.n 160 <Reset_Handler+0x40>
+ 162: 46c0 nop ; (mov r8, r8)
+ 164: 00002140 .word 0x00002140
+ 168: 20000000 .word 0x20000000
+ 16c: 20000038 .word 0x20000038
+ 170: 20000038 .word 0x20000038
+ 174: 2000011c .word 0x2000011c
+ 178: e000ed00 .word 0xe000ed00
+ 17c: 00000000 .word 0x00000000
+ 180: 00001eb1 .word 0x00001eb1
+ 184: 000019f9 .word 0x000019f9
+
+00000188 <CALENDAR_0_CLOCK_init>:
+ uint8_t tmp;
+ PORT_CRITICAL_SECTION_ENTER();
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 188: 4a03 ldr r2, [pc, #12] ; (198 <CALENDAR_0_CLOCK_init+0x10>)
+ tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+ 18a: 6951 ldr r1, [r2, #20]
+ 18c: 2380 movs r3, #128 ; 0x80
+ tmp &= ~PORT_PMUX_PMUXE_Msk;
+ 18e: 009b lsls r3, r3, #2
+ 190: 430b orrs r3, r1
+ tmp |= PORT_PMUX_PMUXE(data);
+ 192: 6153 str r3, [r2, #20]
+ 194: 4770 bx lr
+ ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+ 196: 46c0 nop ; (mov r8, r8)
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 198: 40000800 .word 0x40000800
+
+0000019c <CALENDAR_0_init>:
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ 19c: b510 push {r4, lr}
+ tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+ 19e: 4b03 ldr r3, [pc, #12] ; (1ac <CALENDAR_0_init+0x10>)
+ 1a0: 4798 blx r3
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 1a2: 4903 ldr r1, [pc, #12] ; (1b0 <CALENDAR_0_init+0x14>)
+ tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+ 1a4: 4803 ldr r0, [pc, #12] ; (1b4 <CALENDAR_0_init+0x18>)
+ tmp &= ~PORT_PMUX_PMUXO_Msk;
+ 1a6: 4b04 ldr r3, [pc, #16] ; (1b8 <CALENDAR_0_init+0x1c>)
+ tmp |= PORT_PMUX_PMUXO(data);
+ 1a8: 4798 blx r3
+ 1aa: bd10 pop {r4, pc}
+ ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+ 1ac: 00000189 .word 0x00000189
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 1b0: 40002400 .word 0x40002400
+ tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+ 1b4: 200000b4 .word 0x200000b4
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 1b8: 000006b5 .word 0x000006b5
+
+000001bc <I2C_0_PORT_init>:
+ tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+ 1bc: b570 push {r4, r5, r6, lr}
+ tmp &= ~PORT_PMUX_PMUXE_Msk;
+ 1be: 4b13 ldr r3, [pc, #76] ; (20c <I2C_0_PORT_init+0x50>)
+ 1c0: 20de movs r0, #222 ; 0xde
+ tmp |= PORT_PMUX_PMUXE(data);
+ 1c2: 5c19 ldrb r1, [r3, r0]
+ 1c4: 2204 movs r2, #4
+ ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+ 1c6: 4391 bics r1, r2
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 1c8: 5419 strb r1, [r3, r0]
+ 1ca: 5c19 ldrb r1, [r3, r0]
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ 1cc: 2501 movs r5, #1
+ tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+ 1ce: 43a9 bics r1, r5
+ 1d0: 2401 movs r4, #1
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 1d2: 4321 orrs r1, r4
+ tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+ 1d4: b2c9 uxtb r1, r1
+ tmp &= ~PORT_PMUX_PMUXO_Msk;
+ 1d6: 5419 strb r1, [r3, r0]
+ tmp |= PORT_PMUX_PMUXO(data);
+ 1d8: 381f subs r0, #31
+ 1da: 5c19 ldrb r1, [r3, r0]
+ ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+ 1dc: 260f movs r6, #15
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 1de: 43b1 bics r1, r6
+ 1e0: 2602 movs r6, #2
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ 1e2: 4331 orrs r1, r6
+ tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+ 1e4: b2c9 uxtb r1, r1
+ 1e6: 5419 strb r1, [r3, r0]
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 1e8: 21df movs r1, #223 ; 0xdf
+ tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+ 1ea: 5c5e ldrb r6, [r3, r1]
+ 1ec: 4396 bics r6, r2
+ tmp &= ~PORT_PMUX_PMUXE_Msk;
+ 1ee: 545e strb r6, [r3, r1]
+ 1f0: 5c5a ldrb r2, [r3, r1]
+ tmp |= PORT_PMUX_PMUXE(data);
+ 1f2: 43aa bics r2, r5
+ 1f4: 4322 orrs r2, r4
+ ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+ 1f6: b2d2 uxtb r2, r2
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 1f8: 545a strb r2, [r3, r1]
+ 1fa: 5c1a ldrb r2, [r3, r0]
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ 1fc: 39d0 subs r1, #208 ; 0xd0
+ tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+ 1fe: 400a ands r2, r1
+ 200: 2120 movs r1, #32
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 202: 430a orrs r2, r1
+ tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+ 204: b2d2 uxtb r2, r2
+ tmp &= ~PORT_PMUX_PMUXO_Msk;
+ 206: 541a strb r2, [r3, r0]
+ tmp |= PORT_PMUX_PMUXO(data);
+ 208: bd70 pop {r4, r5, r6, pc}
+ 20a: 46c0 nop ; (mov r8, r8)
+ ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+ 20c: 41006000 .word 0x41006000
+
+00000210 <I2C_0_CLOCK_init>:
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 210: 4b06 ldr r3, [pc, #24] ; (22c <I2C_0_CLOCK_init+0x1c>)
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ 212: 2140 movs r1, #64 ; 0x40
+ tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+ 214: 22c4 movs r2, #196 ; 0xc4
+ 216: 5099 str r1, [r3, r2]
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 218: 3103 adds r1, #3
+ tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+ 21a: 3a08 subs r2, #8
+ 21c: 5099 str r1, [r3, r2]
+ tmp &= ~PORT_PMUX_PMUXE_Msk;
+ 21e: 4a04 ldr r2, [pc, #16] ; (230 <I2C_0_CLOCK_init+0x20>)
+ 220: 69d3 ldr r3, [r2, #28]
+ tmp |= PORT_PMUX_PMUXE(data);
+ 222: 393f subs r1, #63 ; 0x3f
+ 224: 430b orrs r3, r1
+ ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+ 226: 61d3 str r3, [r2, #28]
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 228: 4770 bx lr
+ 22a: 46c0 nop ; (mov r8, r8)
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ 22c: 40001c00 .word 0x40001c00
+ tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+ 230: 40000800 .word 0x40000800
+
+00000234 <I2C_0_init>:
+ tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+ 234: b510 push {r4, lr}
+ tmp &= ~PORT_PMUX_PMUXO_Msk;
+ 236: 4b04 ldr r3, [pc, #16] ; (248 <I2C_0_init+0x14>)
+ tmp |= PORT_PMUX_PMUXO(data);
+ 238: 4798 blx r3
+ 23a: 4904 ldr r1, [pc, #16] ; (24c <I2C_0_init+0x18>)
+ ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+ 23c: 4804 ldr r0, [pc, #16] ; (250 <I2C_0_init+0x1c>)
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 23e: 4b05 ldr r3, [pc, #20] ; (254 <I2C_0_init+0x20>)
+ 240: 4798 blx r3
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ 242: 4b05 ldr r3, [pc, #20] ; (258 <I2C_0_init+0x24>)
+ tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+ 244: 4798 blx r3
+ 246: bd10 pop {r4, pc}
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 248: 00000211 .word 0x00000211
+ tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+ 24c: 42000800 .word 0x42000800
+ tmp &= ~PORT_PMUX_PMUXE_Msk;
+ 250: 200000f8 .word 0x200000f8
+ tmp |= PORT_PMUX_PMUXE(data);
+ 254: 000008a9 .word 0x000008a9
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 258: 000001bd .word 0x000001bd
+
+0000025c <delay_driver_init>:
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ 25c: b510 push {r4, lr}
+ tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+ 25e: 4802 ldr r0, [pc, #8] ; (268 <delay_driver_init+0xc>)
+ 260: 4b02 ldr r3, [pc, #8] ; (26c <delay_driver_init+0x10>)
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 262: 4798 blx r3
+ tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+ 264: bd10 pop {r4, pc}
+ tmp &= ~PORT_PMUX_PMUXO_Msk;
+ 266: 46c0 nop ; (mov r8, r8)
+ tmp |= PORT_PMUX_PMUXO(data);
+ 268: e000e010 .word 0xe000e010
+ ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+ 26c: 0000082d .word 0x0000082d
+
+00000270 <PWM_0_PORT_init>:
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 270: b530 push {r4, r5, lr}
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ 272: 4b0f ldr r3, [pc, #60] ; (2b0 <PWM_0_PORT_init+0x40>)
+ tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+ 274: 2254 movs r2, #84 ; 0x54
+ 276: 5c99 ldrb r1, [r3, r2]
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 278: 2501 movs r5, #1
+ tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+ 27a: 43a9 bics r1, r5
+ 27c: 2401 movs r4, #1
+ tmp &= ~PORT_PMUX_PMUXE_Msk;
+ 27e: 4321 orrs r1, r4
+ 280: b2c9 uxtb r1, r1
+ 282: 5499 strb r1, [r3, r2]
+ tmp |= PORT_PMUX_PMUXE(data);
+ 284: 203a movs r0, #58 ; 0x3a
+ 286: 5c19 ldrb r1, [r3, r0]
+ ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+ 288: 3a45 subs r2, #69 ; 0x45
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 28a: 4391 bics r1, r2
+ 28c: 2204 movs r2, #4
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ 28e: 4311 orrs r1, r2
+ tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+ 290: b2c9 uxtb r1, r1
+ 292: 5419 strb r1, [r3, r0]
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 294: 2155 movs r1, #85 ; 0x55
+ tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+ 296: 5c5a ldrb r2, [r3, r1]
+ tmp &= ~PORT_PMUX_PMUXO_Msk;
+ 298: 43aa bics r2, r5
+ tmp |= PORT_PMUX_PMUXO(data);
+ 29a: 4322 orrs r2, r4
+ 29c: b2d2 uxtb r2, r2
+ ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+ 29e: 545a strb r2, [r3, r1]
+ gpio_set_pin_function(SEG21, PINMUX_PA19B_SLCD_LP35);
+
+ gpio_set_pin_function(SEG22, PINMUX_PB16B_SLCD_LP42);
+
+ gpio_set_pin_function(SEG23, PINMUX_PB17B_SLCD_LP43);
+}
+ 2a0: 5c1a ldrb r2, [r3, r0]
+ 2a2: 3946 subs r1, #70 ; 0x46
+ 2a4: 400a ands r2, r1
+ 2a6: 2140 movs r1, #64 ; 0x40
+ 2a8: 430a orrs r2, r1
+ 2aa: b2d2 uxtb r2, r2
+ 2ac: 541a strb r2, [r3, r0]
+}
+ 2ae: bd30 pop {r4, r5, pc}
+ 2b0: 41006000 .word 0x41006000
+
+000002b4 <PWM_0_CLOCK_init>:
+}
+
+static inline void hri_mclk_set_APBCMASK_TC3_bit(const void *const hw)
+{
+ MCLK_CRITICAL_SECTION_ENTER();
+ ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC3;
+ 2b4: 4a05 ldr r2, [pc, #20] ; (2cc <PWM_0_CLOCK_init+0x18>)
+ 2b6: 69d1 ldr r1, [r2, #28]
+ 2b8: 2380 movs r3, #128 ; 0x80
+ 2ba: 011b lsls r3, r3, #4
+ 2bc: 430b orrs r3, r1
+ 2be: 61d3 str r3, [r2, #28]
+}
+
+static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data)
+{
+ GCLK_CRITICAL_SECTION_ENTER();
+ ((Gclk *)hw)->PCHCTRL[index].reg = data;
+ 2c0: 2140 movs r1, #64 ; 0x40
+ 2c2: 23e0 movs r3, #224 ; 0xe0
+ 2c4: 4a02 ldr r2, [pc, #8] ; (2d0 <PWM_0_CLOCK_init+0x1c>)
+ 2c6: 50d1 str r1, [r2, r3]
+}
+ 2c8: 4770 bx lr
+ 2ca: 46c0 nop ; (mov r8, r8)
+ 2cc: 40000800 .word 0x40000800
+ 2d0: 40001c00 .word 0x40001c00
+
+000002d4 <PWM_0_init>:
+{
+ 2d4: b510 push {r4, lr}
+ PWM_0_CLOCK_init();
+ 2d6: 4b06 ldr r3, [pc, #24] ; (2f0 <PWM_0_init+0x1c>)
+ 2d8: 4798 blx r3
+ PWM_0_PORT_init();
+ 2da: 4b06 ldr r3, [pc, #24] ; (2f4 <PWM_0_init+0x20>)
+ 2dc: 4798 blx r3
+ pwm_init(&PWM_0, TC3, _tc_get_pwm());
+ 2de: 4b06 ldr r3, [pc, #24] ; (2f8 <PWM_0_init+0x24>)
+ 2e0: 4798 blx r3
+ 2e2: 0002 movs r2, r0
+ 2e4: 4905 ldr r1, [pc, #20] ; (2fc <PWM_0_init+0x28>)
+ 2e6: 4806 ldr r0, [pc, #24] ; (300 <PWM_0_init+0x2c>)
+ 2e8: 4b06 ldr r3, [pc, #24] ; (304 <PWM_0_init+0x30>)
+ 2ea: 4798 blx r3
+}
+ 2ec: bd10 pop {r4, pc}
+ 2ee: 46c0 nop ; (mov r8, r8)
+ 2f0: 000002b5 .word 0x000002b5
+ 2f4: 00000271 .word 0x00000271
+ 2f8: 000019d9 .word 0x000019d9
+ 2fc: 42002c00 .word 0x42002c00
+ 300: 20000090 .word 0x20000090
+ 304: 00000999 .word 0x00000999
+
+00000308 <system_init>:
+ slcd_sync_init(&SEGMENT_LCD_0, SLCD);
+ SEGMENT_LCD_0_PORT_init();
+}
+
+void system_init(void)
+{
+ 308: b5f0 push {r4, r5, r6, r7, lr}
+ 30a: 46c6 mov lr, r8
+ 30c: b500 push {lr}
+ * Currently the following initialization functions are supported:
+ * - System clock initialization
+ */
+static inline void init_mcu(void)
+{
+ _init_chip();
+ 30e: 4b1c ldr r3, [pc, #112] ; (380 <system_init+0x78>)
+ 310: 4798 blx r3
+ ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask;
+ 312: 22c0 movs r2, #192 ; 0xc0
+ 314: 05d2 lsls r2, r2, #23
+ 316: 2404 movs r4, #4
+ 318: 6054 str r4, [r2, #4]
+
+static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index,
+ hri_port_wrconfig_reg_t data)
+{
+ PORT_CRITICAL_SECTION_ENTER();
+ ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
+ 31a: 4b1a ldr r3, [pc, #104] ; (384 <system_init+0x7c>)
+ 31c: 491a ldr r1, [pc, #104] ; (388 <system_init+0x80>)
+ 31e: 6299 str r1, [r3, #40] ; 0x28
+ 320: 491a ldr r1, [pc, #104] ; (38c <system_init+0x84>)
+ 322: 6299 str r1, [r3, #40] ; 0x28
+ ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask;
+ 324: 6054 str r4, [r2, #4]
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN;
+ 326: 2042 movs r0, #66 ; 0x42
+ 328: 5c19 ldrb r1, [r3, r0]
+ 32a: 2504 movs r5, #4
+ 32c: 4329 orrs r1, r5
+ 32e: b2c9 uxtb r1, r1
+ 330: 5419 strb r1, [r3, r0]
+ ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
+ 332: 6154 str r4, [r2, #20]
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 334: 5c1c ldrb r4, [r3, r0]
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ 336: 2101 movs r1, #1
+ 338: 438c bics r4, r1
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 33a: 541c strb r4, [r3, r0]
+ ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
+ 33c: 2794 movs r7, #148 ; 0x94
+ 33e: 51d1 str r1, [r2, r7]
+ ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
+ 340: 2688 movs r6, #136 ; 0x88
+ 342: 5191 str r1, [r2, r6]
+ ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
+ 344: 3066 adds r0, #102 ; 0x66
+ 346: 4c12 ldr r4, [pc, #72] ; (390 <system_init+0x88>)
+ 348: 501c str r4, [r3, r0]
+ 34a: 24c0 movs r4, #192 ; 0xc0
+ 34c: 0624 lsls r4, r4, #24
+ 34e: 46a0 mov r8, r4
+ 350: 501c str r4, [r3, r0]
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 352: 24c0 movs r4, #192 ; 0xc0
+ 354: 46a4 mov ip, r4
+ 356: 5d1c ldrb r4, [r3, r4]
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ 358: 438c bics r4, r1
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 35a: 4665 mov r5, ip
+ 35c: 555c strb r4, [r3, r5]
+ ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
+ 35e: 2408 movs r4, #8
+ 360: 51d4 str r4, [r2, r7]
+ ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
+ 362: 5194 str r4, [r2, r6]
+ ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
+ 364: 4a0b ldr r2, [pc, #44] ; (394 <system_init+0x8c>)
+ 366: 501a str r2, [r3, r0]
+ 368: 4642 mov r2, r8
+ 36a: 501a str r2, [r3, r0]
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 36c: 301b adds r0, #27
+ 36e: 5c1a ldrb r2, [r3, r0]
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ 370: 438a bics r2, r1
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 372: 541a strb r2, [r3, r0]
+ // Set pin direction to output
+ gpio_set_pin_direction(D0, GPIO_DIRECTION_OUT);
+
+ gpio_set_pin_function(D0, GPIO_PIN_FUNCTION_OFF);
+
+ delay_driver_init();
+ 374: 4b08 ldr r3, [pc, #32] ; (398 <system_init+0x90>)
+ 376: 4798 blx r3
+ PWM_0_init();
+
+ PWM_1_init();
+ SEGMENT_LCD_0_init();
+*/
+}
+ 378: bc04 pop {r2}
+ 37a: 4690 mov r8, r2
+ 37c: bdf0 pop {r4, r5, r6, r7, pc}
+ 37e: 46c0 nop ; (mov r8, r8)
+ 380: 00000b3d .word 0x00000b3d
+ 384: 41006000 .word 0x41006000
+ 388: 40020004 .word 0x40020004
+ 38c: c0020000 .word 0xc0020000
+ 390: 40000001 .word 0x40000001
+ 394: 40000008 .word 0x40000008
+ 398: 0000025d .word 0x0000025d
+
+0000039c <leap_year>:
+ * \retval false not leap year.
+ * \retval true leap year.
+ */
+static bool leap_year(uint16_t year)
+{
+ if (year & 3) {
+ 39c: 0783 lsls r3, r0, #30
+ 39e: d101 bne.n 3a4 <leap_year+0x8>
+ return false;
+ } else {
+ return true;
+ 3a0: 2001 movs r0, #1
+ }
+}
+ 3a2: 4770 bx lr
+ return false;
+ 3a4: 2000 movs r0, #0
+ 3a6: e7fc b.n 3a2 <leap_year+0x6>
+
+000003a8 <get_secs_in_month>:
+
+/** \brief calculate the seconds in specified year/month
+ * \retval 0 month error.
+ */
+static uint32_t get_secs_in_month(uint32_t year, uint8_t month)
+{
+ 3a8: b510 push {r4, lr}
+ 3aa: 000c movs r4, r1
+ uint32_t sec_in_month = 0;
+
+ if (leap_year(year)) {
+ 3ac: b280 uxth r0, r0
+ 3ae: 4b10 ldr r3, [pc, #64] ; (3f0 <get_secs_in_month+0x48>)
+ 3b0: 4798 blx r3
+ 3b2: 2800 cmp r0, #0
+ 3b4: d00b beq.n 3ce <get_secs_in_month+0x26>
+ switch (month) {
+ 3b6: 2c0c cmp r4, #12
+ 3b8: d803 bhi.n 3c2 <get_secs_in_month+0x1a>
+ 3ba: 00a4 lsls r4, r4, #2
+ 3bc: 4b0d ldr r3, [pc, #52] ; (3f4 <get_secs_in_month+0x4c>)
+ 3be: 591b ldr r3, [r3, r4]
+ 3c0: 469f mov pc, r3
+ uint32_t sec_in_month = 0;
+ 3c2: 2000 movs r0, #0
+ 3c4: e010 b.n 3e8 <get_secs_in_month+0x40>
+ case 10:
+ case 12:
+ sec_in_month = SECS_IN_31DAYS;
+ break;
+ case 2:
+ sec_in_month = SECS_IN_29DAYS;
+ 3c6: 480c ldr r0, [pc, #48] ; (3f8 <get_secs_in_month+0x50>)
+ break;
+ 3c8: e00e b.n 3e8 <get_secs_in_month+0x40>
+ case 4:
+ case 6:
+ case 9:
+ case 11:
+ sec_in_month = SECS_IN_30DAYS;
+ 3ca: 480c ldr r0, [pc, #48] ; (3fc <get_secs_in_month+0x54>)
+ break;
+ 3cc: e00c b.n 3e8 <get_secs_in_month+0x40>
+ default:
+ break;
+ }
+ } else {
+ switch (month) {
+ 3ce: 2c0c cmp r4, #12
+ 3d0: d803 bhi.n 3da <get_secs_in_month+0x32>
+ 3d2: 00a4 lsls r4, r4, #2
+ 3d4: 4b0a ldr r3, [pc, #40] ; (400 <get_secs_in_month+0x58>)
+ 3d6: 591b ldr r3, [r3, r4]
+ 3d8: 469f mov pc, r3
+ uint32_t sec_in_month = 0;
+ 3da: 2000 movs r0, #0
+ 3dc: e004 b.n 3e8 <get_secs_in_month+0x40>
+ case 10:
+ case 12:
+ sec_in_month = SECS_IN_31DAYS;
+ break;
+ case 2:
+ sec_in_month = SECS_IN_28DAYS;
+ 3de: 4809 ldr r0, [pc, #36] ; (404 <get_secs_in_month+0x5c>)
+ break;
+ 3e0: e002 b.n 3e8 <get_secs_in_month+0x40>
+ case 4:
+ case 6:
+ case 9:
+ case 11:
+ sec_in_month = SECS_IN_30DAYS;
+ 3e2: 4806 ldr r0, [pc, #24] ; (3fc <get_secs_in_month+0x54>)
+ break;
+ 3e4: e000 b.n 3e8 <get_secs_in_month+0x40>
+ sec_in_month = SECS_IN_31DAYS;
+ 3e6: 4808 ldr r0, [pc, #32] ; (408 <get_secs_in_month+0x60>)
+ break;
+ }
+ }
+
+ return sec_in_month;
+}
+ 3e8: bd10 pop {r4, pc}
+ sec_in_month = SECS_IN_31DAYS;
+ 3ea: 4807 ldr r0, [pc, #28] ; (408 <get_secs_in_month+0x60>)
+ return sec_in_month;
+ 3ec: e7fc b.n 3e8 <get_secs_in_month+0x40>
+ 3ee: 46c0 nop ; (mov r8, r8)
+ 3f0: 0000039d .word 0x0000039d
+ 3f4: 00001ef8 .word 0x00001ef8
+ 3f8: 00263b80 .word 0x00263b80
+ 3fc: 00278d00 .word 0x00278d00
+ 400: 00001f2c .word 0x00001f2c
+ 404: 0024ea00 .word 0x0024ea00
+ 408: 0028de80 .word 0x0028de80
+
+0000040c <convert_timestamp_to_datetime>:
+
+/** \brief convert timestamp to date/time
+ */
+static int32_t convert_timestamp_to_datetime(struct calendar_descriptor *const calendar, uint32_t ts,
+ struct calendar_date_time *dt)
+{
+ 40c: b5f0 push {r4, r5, r6, r7, lr}
+ 40e: 46c6 mov lr, r8
+ 410: b500 push {lr}
+ 412: 000c movs r4, r1
+ 414: 4690 mov r8, r2
+ uint32_t tmp, sec_in_year, sec_in_month;
+ uint32_t tmp_year = calendar->base_year;
+ 416: 6986 ldr r6, [r0, #24]
+ 418: e004 b.n 424 <convert_timestamp_to_datetime+0x18>
+
+ tmp = ts;
+
+ /* Find year */
+ while (true) {
+ sec_in_year = leap_year(tmp_year) ? SECS_IN_LEAP_YEAR : SECS_IN_NON_LEAP_YEAR;
+ 41a: 4b1f ldr r3, [pc, #124] ; (498 <convert_timestamp_to_datetime+0x8c>)
+
+ if (tmp >= sec_in_year) {
+ 41c: 429c cmp r4, r3
+ 41e: d309 bcc.n 434 <convert_timestamp_to_datetime+0x28>
+ tmp -= sec_in_year;
+ 420: 1ae4 subs r4, r4, r3
+ tmp_year++;
+ 422: 3601 adds r6, #1
+ sec_in_year = leap_year(tmp_year) ? SECS_IN_LEAP_YEAR : SECS_IN_NON_LEAP_YEAR;
+ 424: b2b7 uxth r7, r6
+ 426: 0038 movs r0, r7
+ 428: 4b1c ldr r3, [pc, #112] ; (49c <convert_timestamp_to_datetime+0x90>)
+ 42a: 4798 blx r3
+ 42c: 2800 cmp r0, #0
+ 42e: d0f4 beq.n 41a <convert_timestamp_to_datetime+0xe>
+ 430: 4b1b ldr r3, [pc, #108] ; (4a0 <convert_timestamp_to_datetime+0x94>)
+ 432: e7f3 b.n 41c <convert_timestamp_to_datetime+0x10>
+ 434: 2501 movs r5, #1
+ break;
+ }
+ }
+ /* Find month of year */
+ while (true) {
+ sec_in_month = get_secs_in_month(tmp_year, tmp_month);
+ 436: 0029 movs r1, r5
+ 438: 0030 movs r0, r6
+ 43a: 4b1a ldr r3, [pc, #104] ; (4a4 <convert_timestamp_to_datetime+0x98>)
+ 43c: 4798 blx r3
+
+ if (tmp >= sec_in_month) {
+ 43e: 4284 cmp r4, r0
+ 440: d303 bcc.n 44a <convert_timestamp_to_datetime+0x3e>
+ tmp -= sec_in_month;
+ 442: 1a24 subs r4, r4, r0
+ tmp_month++;
+ 444: 3501 adds r5, #1
+ 446: b2ed uxtb r5, r5
+ sec_in_month = get_secs_in_month(tmp_year, tmp_month);
+ 448: e7f5 b.n 436 <convert_timestamp_to_datetime+0x2a>
+ 44a: 2101 movs r1, #1
+ break;
+ }
+ }
+ /* Find day of month */
+ while (true) {
+ if (tmp >= SECS_IN_DAY) {
+ 44c: 4b16 ldr r3, [pc, #88] ; (4a8 <convert_timestamp_to_datetime+0x9c>)
+ 44e: 429c cmp r4, r3
+ 450: d905 bls.n 45e <convert_timestamp_to_datetime+0x52>
+ tmp -= SECS_IN_DAY;
+ 452: 4b16 ldr r3, [pc, #88] ; (4ac <convert_timestamp_to_datetime+0xa0>)
+ 454: 469c mov ip, r3
+ 456: 4464 add r4, ip
+ tmp_day++;
+ 458: 3101 adds r1, #1
+ 45a: b2c9 uxtb r1, r1
+ if (tmp >= SECS_IN_DAY) {
+ 45c: e7f6 b.n 44c <convert_timestamp_to_datetime+0x40>
+ 45e: 2200 movs r2, #0
+ break;
+ }
+ }
+ /* Find hour of day */
+ while (true) {
+ if (tmp >= SECS_IN_HOUR) {
+ 460: 4b13 ldr r3, [pc, #76] ; (4b0 <convert_timestamp_to_datetime+0xa4>)
+ 462: 429c cmp r4, r3
+ 464: d905 bls.n 472 <convert_timestamp_to_datetime+0x66>
+ tmp -= SECS_IN_HOUR;
+ 466: 4b13 ldr r3, [pc, #76] ; (4b4 <convert_timestamp_to_datetime+0xa8>)
+ 468: 469c mov ip, r3
+ 46a: 4464 add r4, ip
+ tmp_hour++;
+ 46c: 3201 adds r2, #1
+ 46e: b2d2 uxtb r2, r2
+ if (tmp >= SECS_IN_HOUR) {
+ 470: e7f6 b.n 460 <convert_timestamp_to_datetime+0x54>
+ 472: 2300 movs r3, #0
+ break;
+ }
+ }
+ /* Find minute in hour */
+ while (true) {
+ if (tmp >= SECS_IN_MINUTE) {
+ 474: 2c3b cmp r4, #59 ; 0x3b
+ 476: d903 bls.n 480 <convert_timestamp_to_datetime+0x74>
+ tmp -= SECS_IN_MINUTE;
+ 478: 3c3c subs r4, #60 ; 0x3c
+ tmp_minutes++;
+ 47a: 3301 adds r3, #1
+ 47c: b2db uxtb r3, r3
+ if (tmp >= SECS_IN_MINUTE) {
+ 47e: e7f9 b.n 474 <convert_timestamp_to_datetime+0x68>
+ } else {
+ break;
+ }
+ }
+
+ dt->date.year = tmp_year;
+ 480: 4640 mov r0, r8
+ 482: 80c7 strh r7, [r0, #6]
+ dt->date.month = tmp_month;
+ 484: 7145 strb r5, [r0, #5]
+ dt->date.day = tmp_day;
+ 486: 7101 strb r1, [r0, #4]
+ dt->time.hour = tmp_hour;
+ 488: 7082 strb r2, [r0, #2]
+ dt->time.min = tmp_minutes;
+ 48a: 7043 strb r3, [r0, #1]
+ dt->time.sec = tmp;
+ 48c: 7004 strb r4, [r0, #0]
+
+ return ERR_NONE;
+}
+ 48e: 2000 movs r0, #0
+ 490: bc04 pop {r2}
+ 492: 4690 mov r8, r2
+ 494: bdf0 pop {r4, r5, r6, r7, pc}
+ 496: 46c0 nop ; (mov r8, r8)
+ 498: 01e13380 .word 0x01e13380
+ 49c: 0000039d .word 0x0000039d
+ 4a0: 01e28500 .word 0x01e28500
+ 4a4: 000003a9 .word 0x000003a9
+ 4a8: 0001517f .word 0x0001517f
+ 4ac: fffeae80 .word 0xfffeae80
+ 4b0: 00000e0f .word 0x00000e0f
+ 4b4: fffff1f0 .word 0xfffff1f0
+
+000004b8 <convert_datetime_to_timestamp>:
+
+/** \brief convert date/time to timestamp
+ * \return timestamp
+ */
+static uint32_t convert_datetime_to_timestamp(struct calendar_descriptor *const calendar, struct calendar_date_time *dt)
+{
+ 4b8: b5f0 push {r4, r5, r6, r7, lr}
+ 4ba: 46de mov lr, fp
+ 4bc: 4657 mov r7, sl
+ 4be: 464e mov r6, r9
+ 4c0: 4645 mov r5, r8
+ 4c2: b5e0 push {r5, r6, r7, lr}
+ 4c4: b083 sub sp, #12
+ uint32_t tmp = 0;
+ uint32_t i = 0;
+ uint8_t year, month, day, hour, minutes, seconds;
+
+ year = dt->date.year - calendar->base_year;
+ 4c6: 88cb ldrh r3, [r1, #6]
+ 4c8: 9300 str r3, [sp, #0]
+ 4ca: b2de uxtb r6, r3
+ 4cc: 6983 ldr r3, [r0, #24]
+ 4ce: 4699 mov r9, r3
+ 4d0: 466a mov r2, sp
+ 4d2: 7113 strb r3, [r2, #4]
+ 4d4: 7913 ldrb r3, [r2, #4]
+ 4d6: 1af6 subs r6, r6, r3
+ 4d8: b2f6 uxtb r6, r6
+ month = dt->date.month;
+ 4da: 794f ldrb r7, [r1, #5]
+ day = dt->date.day;
+ 4dc: 790b ldrb r3, [r1, #4]
+ 4de: 469a mov sl, r3
+ hour = dt->time.hour;
+ 4e0: 788b ldrb r3, [r1, #2]
+ 4e2: 4698 mov r8, r3
+ minutes = dt->time.min;
+ 4e4: 784b ldrb r3, [r1, #1]
+ 4e6: 469b mov fp, r3
+ seconds = dt->time.sec;
+ 4e8: 780b ldrb r3, [r1, #0]
+ 4ea: 9301 str r3, [sp, #4]
+
+ /* tot up year field */
+ for (i = 0; i < year; ++i) {
+ 4ec: 2500 movs r5, #0
+ uint32_t tmp = 0;
+ 4ee: 2400 movs r4, #0
+ for (i = 0; i < year; ++i) {
+ 4f0: e003 b.n 4fa <convert_datetime_to_timestamp+0x42>
+ if (leap_year(calendar->base_year + i)) {
+ tmp += SECS_IN_LEAP_YEAR;
+ } else {
+ tmp += SECS_IN_NON_LEAP_YEAR;
+ 4f2: 4b1a ldr r3, [pc, #104] ; (55c <convert_datetime_to_timestamp+0xa4>)
+ 4f4: 469c mov ip, r3
+ 4f6: 4464 add r4, ip
+ for (i = 0; i < year; ++i) {
+ 4f8: 3501 adds r5, #1
+ 4fa: 42b5 cmp r5, r6
+ 4fc: d20a bcs.n 514 <convert_datetime_to_timestamp+0x5c>
+ if (leap_year(calendar->base_year + i)) {
+ 4fe: 464b mov r3, r9
+ 500: 1958 adds r0, r3, r5
+ 502: b280 uxth r0, r0
+ 504: 4b16 ldr r3, [pc, #88] ; (560 <convert_datetime_to_timestamp+0xa8>)
+ 506: 4798 blx r3
+ 508: 2800 cmp r0, #0
+ 50a: d0f2 beq.n 4f2 <convert_datetime_to_timestamp+0x3a>
+ tmp += SECS_IN_LEAP_YEAR;
+ 50c: 4b15 ldr r3, [pc, #84] ; (564 <convert_datetime_to_timestamp+0xac>)
+ 50e: 469c mov ip, r3
+ 510: 4464 add r4, ip
+ 512: e7f1 b.n 4f8 <convert_datetime_to_timestamp+0x40>
+ 514: 2501 movs r5, #1
+ 516: e005 b.n 524 <convert_datetime_to_timestamp+0x6c>
+ }
+ }
+
+ /* tot up month field */
+ for (i = 1; i < month; ++i) {
+ tmp += get_secs_in_month(dt->date.year, i);
+ 518: b2e9 uxtb r1, r5
+ 51a: 9800 ldr r0, [sp, #0]
+ 51c: 4b12 ldr r3, [pc, #72] ; (568 <convert_datetime_to_timestamp+0xb0>)
+ 51e: 4798 blx r3
+ 520: 1824 adds r4, r4, r0
+ for (i = 1; i < month; ++i) {
+ 522: 3501 adds r5, #1
+ 524: 42bd cmp r5, r7
+ 526: d3f7 bcc.n 518 <convert_datetime_to_timestamp+0x60>
+ }
+
+ /* tot up day/hour/minute/second fields */
+ tmp += (day - 1) * SECS_IN_DAY;
+ 528: 4653 mov r3, sl
+ 52a: 3b01 subs r3, #1
+ 52c: 480f ldr r0, [pc, #60] ; (56c <convert_datetime_to_timestamp+0xb4>)
+ 52e: 4358 muls r0, r3
+ 530: 1824 adds r4, r4, r0
+ tmp += hour * SECS_IN_HOUR;
+ 532: 20e1 movs r0, #225 ; 0xe1
+ 534: 0100 lsls r0, r0, #4
+ 536: 4643 mov r3, r8
+ 538: 4358 muls r0, r3
+ 53a: 1820 adds r0, r4, r0
+ tmp += minutes * SECS_IN_MINUTE;
+ 53c: 465b mov r3, fp
+ 53e: 011b lsls r3, r3, #4
+ 540: 465a mov r2, fp
+ 542: 1a9b subs r3, r3, r2
+ 544: 009c lsls r4, r3, #2
+ 546: 1900 adds r0, r0, r4
+ tmp += seconds;
+ 548: 9b01 ldr r3, [sp, #4]
+ 54a: 469c mov ip, r3
+ 54c: 4460 add r0, ip
+
+ return tmp;
+}
+ 54e: b003 add sp, #12
+ 550: bc3c pop {r2, r3, r4, r5}
+ 552: 4690 mov r8, r2
+ 554: 4699 mov r9, r3
+ 556: 46a2 mov sl, r4
+ 558: 46ab mov fp, r5
+ 55a: bdf0 pop {r4, r5, r6, r7, pc}
+ 55c: 01e13380 .word 0x01e13380
+ 560: 0000039d .word 0x0000039d
+ 564: 01e28500 .word 0x01e28500
+ 568: 000003a9 .word 0x000003a9
+ 56c: 00015180 .word 0x00015180
+
+00000570 <calibrate_timestamp>:
+
+/** \brief calibrate timestamp to make desired timestamp ahead of current timestamp
+ */
+static void calibrate_timestamp(struct calendar_descriptor *const calendar, struct calendar_alarm *alarm,
+ struct calendar_alarm *current_dt)
+{
+ 570: b570 push {r4, r5, r6, lr}
+ 572: 000c movs r4, r1
+ uint32_t alarm_ts;
+ uint32_t current_ts = current_dt->cal_alarm.timestamp;
+ 574: 68d0 ldr r0, [r2, #12]
+
+ alarm_ts = alarm->cal_alarm.timestamp;
+ 576: 68cd ldr r5, [r1, #12]
+
+ /* calibrate timestamp */
+ switch (alarm->cal_alarm.option) {
+ 578: 7c0b ldrb r3, [r1, #16]
+ 57a: 2b05 cmp r3, #5
+ 57c: d806 bhi.n 58c <calibrate_timestamp+0x1c>
+ 57e: 009b lsls r3, r3, #2
+ 580: 4915 ldr r1, [pc, #84] ; (5d8 <calibrate_timestamp+0x68>)
+ 582: 58cb ldr r3, [r1, r3]
+ 584: 469f mov pc, r3
+ case CALENDAR_ALARM_MATCH_SEC:
+
+ if (alarm_ts <= current_ts) {
+ 586: 42a8 cmp r0, r5
+ 588: d300 bcc.n 58c <calibrate_timestamp+0x1c>
+ alarm_ts += SECS_IN_MINUTE;
+ 58a: 353c adds r5, #60 ; 0x3c
+ default:
+ break;
+ }
+
+ /* desired timestamp after calibration */
+ alarm->cal_alarm.timestamp = alarm_ts;
+ 58c: 60e5 str r5, [r4, #12]
+}
+ 58e: bd70 pop {r4, r5, r6, pc}
+ if (alarm_ts <= current_ts) {
+ 590: 42a8 cmp r0, r5
+ 592: d3fb bcc.n 58c <calibrate_timestamp+0x1c>
+ alarm_ts += SECS_IN_HOUR;
+ 594: 23e1 movs r3, #225 ; 0xe1
+ 596: 011b lsls r3, r3, #4
+ 598: 469c mov ip, r3
+ 59a: 4465 add r5, ip
+ 59c: e7f6 b.n 58c <calibrate_timestamp+0x1c>
+ if (alarm_ts <= current_ts) {
+ 59e: 42a8 cmp r0, r5
+ 5a0: d3f4 bcc.n 58c <calibrate_timestamp+0x1c>
+ alarm_ts += SECS_IN_DAY;
+ 5a2: 4b0e ldr r3, [pc, #56] ; (5dc <calibrate_timestamp+0x6c>)
+ 5a4: 469c mov ip, r3
+ 5a6: 4465 add r5, ip
+ 5a8: e7f0 b.n 58c <calibrate_timestamp+0x1c>
+ if (alarm_ts <= current_ts) {
+ 5aa: 42a8 cmp r0, r5
+ 5ac: d3ee bcc.n 58c <calibrate_timestamp+0x1c>
+ alarm_ts += get_secs_in_month(current_dt->cal_alarm.datetime.date.year,
+ 5ae: 8950 ldrh r0, [r2, #10]
+ 5b0: 7a51 ldrb r1, [r2, #9]
+ 5b2: 4b0b ldr r3, [pc, #44] ; (5e0 <calibrate_timestamp+0x70>)
+ 5b4: 4798 blx r3
+ 5b6: 182d adds r5, r5, r0
+ 5b8: e7e8 b.n 58c <calibrate_timestamp+0x1c>
+ if (alarm_ts <= current_ts) {
+ 5ba: 42a8 cmp r0, r5
+ 5bc: d3e6 bcc.n 58c <calibrate_timestamp+0x1c>
+ if (leap_year(current_dt->cal_alarm.datetime.date.year)) {
+ 5be: 8950 ldrh r0, [r2, #10]
+ 5c0: 4b08 ldr r3, [pc, #32] ; (5e4 <calibrate_timestamp+0x74>)
+ 5c2: 4798 blx r3
+ 5c4: 2800 cmp r0, #0
+ 5c6: d103 bne.n 5d0 <calibrate_timestamp+0x60>
+ alarm_ts += SECS_IN_NON_LEAP_YEAR;
+ 5c8: 4b07 ldr r3, [pc, #28] ; (5e8 <calibrate_timestamp+0x78>)
+ 5ca: 469c mov ip, r3
+ 5cc: 4465 add r5, ip
+ 5ce: e7dd b.n 58c <calibrate_timestamp+0x1c>
+ alarm_ts += SECS_IN_LEAP_YEAR;
+ 5d0: 4b06 ldr r3, [pc, #24] ; (5ec <calibrate_timestamp+0x7c>)
+ 5d2: 469c mov ip, r3
+ 5d4: 4465 add r5, ip
+ 5d6: e7d9 b.n 58c <calibrate_timestamp+0x1c>
+ 5d8: 00001f60 .word 0x00001f60
+ 5dc: 00015180 .word 0x00015180
+ 5e0: 000003a9 .word 0x000003a9
+ 5e4: 0000039d .word 0x0000039d
+ 5e8: 01e13380 .word 0x01e13380
+ 5ec: 01e28500 .word 0x01e28500
+
+000005f0 <fill_alarm>:
+
+/** \brief complete alarm to absolute date/time, then fill up the timestamp
+ */
+static void fill_alarm(struct calendar_descriptor *const calendar, struct calendar_alarm *alarm)
+{
+ 5f0: b570 push {r4, r5, r6, lr}
+ 5f2: b086 sub sp, #24
+ 5f4: 0005 movs r5, r0
+ 5f6: 000c movs r4, r1
+ struct calendar_alarm current_dt;
+ uint32_t tmp, current_ts;
+
+ /* get current date/time */
+ current_ts = _calendar_get_counter(&calendar->device);
+ 5f8: 4b29 ldr r3, [pc, #164] ; (6a0 <fill_alarm+0xb0>)
+ 5fa: 4798 blx r3
+ 5fc: 0006 movs r6, r0
+ convert_timestamp_to_datetime(calendar, current_ts, ¤t_dt.cal_alarm.datetime);
+ 5fe: aa01 add r2, sp, #4
+ 600: 0001 movs r1, r0
+ 602: 0028 movs r0, r5
+ 604: 4b27 ldr r3, [pc, #156] ; (6a4 <fill_alarm+0xb4>)
+ 606: 4798 blx r3
+
+ current_dt.cal_alarm.timestamp = current_ts;
+ 608: 9603 str r6, [sp, #12]
+
+ /* complete alarm */
+ switch (alarm->cal_alarm.option) {
+ 60a: 7c23 ldrb r3, [r4, #16]
+ 60c: 2b05 cmp r3, #5
+ 60e: d812 bhi.n 636 <fill_alarm+0x46>
+ 610: 009b lsls r3, r3, #2
+ 612: 4a25 ldr r2, [pc, #148] ; (6a8 <fill_alarm+0xb8>)
+ 614: 58d3 ldr r3, [r2, r3]
+ 616: 469f mov pc, r3
+ case CALENDAR_ALARM_MATCH_SEC:
+ alarm->cal_alarm.datetime.date.year = current_dt.cal_alarm.datetime.date.year;
+ 618: 466b mov r3, sp
+ 61a: 895b ldrh r3, [r3, #10]
+ 61c: 8163 strh r3, [r4, #10]
+ alarm->cal_alarm.datetime.date.month = current_dt.cal_alarm.datetime.date.month;
+ 61e: 466b mov r3, sp
+ 620: 7a5b ldrb r3, [r3, #9]
+ 622: 7263 strb r3, [r4, #9]
+ alarm->cal_alarm.datetime.date.day = current_dt.cal_alarm.datetime.date.day;
+ 624: 466b mov r3, sp
+ 626: 7a1b ldrb r3, [r3, #8]
+ 628: 7223 strb r3, [r4, #8]
+ alarm->cal_alarm.datetime.time.hour = current_dt.cal_alarm.datetime.time.hour;
+ 62a: 466b mov r3, sp
+ 62c: 799b ldrb r3, [r3, #6]
+ 62e: 71a3 strb r3, [r4, #6]
+ alarm->cal_alarm.datetime.time.min = current_dt.cal_alarm.datetime.time.min;
+ 630: 466b mov r3, sp
+ 632: 795b ldrb r3, [r3, #5]
+ 634: 7163 strb r3, [r4, #5]
+ default:
+ break;
+ }
+
+ /* fill up the timestamp */
+ tmp = convert_datetime_to_timestamp(calendar, &alarm->cal_alarm.datetime);
+ 636: 1d26 adds r6, r4, #4
+ 638: 0031 movs r1, r6
+ 63a: 0028 movs r0, r5
+ 63c: 4b1b ldr r3, [pc, #108] ; (6ac <fill_alarm+0xbc>)
+ 63e: 4798 blx r3
+ alarm->cal_alarm.timestamp = tmp;
+ 640: 60e0 str r0, [r4, #12]
+
+ /* calibrate the timestamp */
+ calibrate_timestamp(calendar, alarm, ¤t_dt);
+ 642: 466a mov r2, sp
+ 644: 0021 movs r1, r4
+ 646: 0028 movs r0, r5
+ 648: 4b19 ldr r3, [pc, #100] ; (6b0 <fill_alarm+0xc0>)
+ 64a: 4798 blx r3
+ convert_timestamp_to_datetime(calendar, alarm->cal_alarm.timestamp, &alarm->cal_alarm.datetime);
+ 64c: 68e1 ldr r1, [r4, #12]
+ 64e: 0032 movs r2, r6
+ 650: 0028 movs r0, r5
+ 652: 4b14 ldr r3, [pc, #80] ; (6a4 <fill_alarm+0xb4>)
+ 654: 4798 blx r3
+}
+ 656: b006 add sp, #24
+ 658: bd70 pop {r4, r5, r6, pc}
+ alarm->cal_alarm.datetime.date.year = current_dt.cal_alarm.datetime.date.year;
+ 65a: 466b mov r3, sp
+ 65c: 895b ldrh r3, [r3, #10]
+ 65e: 8163 strh r3, [r4, #10]
+ alarm->cal_alarm.datetime.date.month = current_dt.cal_alarm.datetime.date.month;
+ 660: 466b mov r3, sp
+ 662: 7a5b ldrb r3, [r3, #9]
+ 664: 7263 strb r3, [r4, #9]
+ alarm->cal_alarm.datetime.date.day = current_dt.cal_alarm.datetime.date.day;
+ 666: 466b mov r3, sp
+ 668: 7a1b ldrb r3, [r3, #8]
+ 66a: 7223 strb r3, [r4, #8]
+ alarm->cal_alarm.datetime.time.hour = current_dt.cal_alarm.datetime.time.hour;
+ 66c: 466b mov r3, sp
+ 66e: 799b ldrb r3, [r3, #6]
+ 670: 71a3 strb r3, [r4, #6]
+ break;
+ 672: e7e0 b.n 636 <fill_alarm+0x46>
+ alarm->cal_alarm.datetime.date.year = current_dt.cal_alarm.datetime.date.year;
+ 674: 466b mov r3, sp
+ 676: 895b ldrh r3, [r3, #10]
+ 678: 8163 strh r3, [r4, #10]
+ alarm->cal_alarm.datetime.date.month = current_dt.cal_alarm.datetime.date.month;
+ 67a: 466b mov r3, sp
+ 67c: 7a5b ldrb r3, [r3, #9]
+ 67e: 7263 strb r3, [r4, #9]
+ alarm->cal_alarm.datetime.date.day = current_dt.cal_alarm.datetime.date.day;
+ 680: 466b mov r3, sp
+ 682: 7a1b ldrb r3, [r3, #8]
+ 684: 7223 strb r3, [r4, #8]
+ break;
+ 686: e7d6 b.n 636 <fill_alarm+0x46>
+ alarm->cal_alarm.datetime.date.year = current_dt.cal_alarm.datetime.date.year;
+ 688: 466b mov r3, sp
+ 68a: 895b ldrh r3, [r3, #10]
+ 68c: 8163 strh r3, [r4, #10]
+ alarm->cal_alarm.datetime.date.month = current_dt.cal_alarm.datetime.date.month;
+ 68e: 466b mov r3, sp
+ 690: 7a5b ldrb r3, [r3, #9]
+ 692: 7263 strb r3, [r4, #9]
+ break;
+ 694: e7cf b.n 636 <fill_alarm+0x46>
+ alarm->cal_alarm.datetime.date.year = current_dt.cal_alarm.datetime.date.year;
+ 696: 466b mov r3, sp
+ 698: 895b ldrh r3, [r3, #10]
+ 69a: 8163 strh r3, [r4, #10]
+ break;
+ 69c: e7cb b.n 636 <fill_alarm+0x46>
+ 69e: 46c0 nop ; (mov r8, r8)
+ 6a0: 00000e55 .word 0x00000e55
+ 6a4: 0000040d .word 0x0000040d
+ 6a8: 00001f78 .word 0x00001f78
+ 6ac: 000004b9 .word 0x000004b9
+ 6b0: 00000571 .word 0x00000571
+
+000006b4 <calendar_init>:
+}
+
+/** \brief Initialize Calendar
+ */
+int32_t calendar_init(struct calendar_descriptor *const calendar, const void *hw)
+{
+ 6b4: b570 push {r4, r5, r6, lr}
+ 6b6: 0004 movs r4, r0
+ 6b8: 000d movs r5, r1
+ int32_t ret = 0;
+
+ /* Sanity check arguments */
+ ASSERT(calendar);
+ 6ba: 1e43 subs r3, r0, #1
+ 6bc: 4198 sbcs r0, r3
+ 6be: b2c0 uxtb r0, r0
+ 6c0: 22e0 movs r2, #224 ; 0xe0
+ 6c2: 0052 lsls r2, r2, #1
+ 6c4: 4909 ldr r1, [pc, #36] ; (6ec <calendar_init+0x38>)
+ 6c6: 4b0a ldr r3, [pc, #40] ; (6f0 <calendar_init+0x3c>)
+ 6c8: 4798 blx r3
+
+ if (calendar->device.hw == hw) {
+ 6ca: 6823 ldr r3, [r4, #0]
+ 6cc: 42ab cmp r3, r5
+ 6ce: d008 beq.n 6e2 <calendar_init+0x2e>
+ /* Already initialized with current configuration */
+ return ERR_NONE;
+ } else if (calendar->device.hw != NULL) {
+ 6d0: 2b00 cmp r3, #0
+ 6d2: d108 bne.n 6e6 <calendar_init+0x32>
+ /* Initialized with another configuration */
+ return ERR_ALREADY_INITIALIZED;
+ }
+ calendar->device.hw = (void *)hw;
+ 6d4: 6025 str r5, [r4, #0]
+ ret = _calendar_init(&calendar->device);
+ 6d6: 0020 movs r0, r4
+ 6d8: 4b06 ldr r3, [pc, #24] ; (6f4 <calendar_init+0x40>)
+ 6da: 4798 blx r3
+ calendar->base_year = DEFAULT_BASE_YEAR;
+ 6dc: 4b06 ldr r3, [pc, #24] ; (6f8 <calendar_init+0x44>)
+ 6de: 61a3 str r3, [r4, #24]
+
+ return ret;
+}
+ 6e0: bd70 pop {r4, r5, r6, pc}
+ return ERR_NONE;
+ 6e2: 2000 movs r0, #0
+ 6e4: e7fc b.n 6e0 <calendar_init+0x2c>
+ return ERR_ALREADY_INITIALIZED;
+ 6e6: 2012 movs r0, #18
+ 6e8: 4240 negs r0, r0
+ 6ea: e7f9 b.n 6e0 <calendar_init+0x2c>
+ 6ec: 00001f90 .word 0x00001f90
+ 6f0: 00000a69 .word 0x00000a69
+ 6f4: 00000d49 .word 0x00000d49
+ 6f8: 000007b2 .word 0x000007b2
+
+000006fc <calendar_enable>:
+}
+
+/** \brief Enable the Calendar
+ */
+int32_t calendar_enable(struct calendar_descriptor *const calendar)
+{
+ 6fc: b510 push {r4, lr}
+ 6fe: 0004 movs r4, r0
+ /* Sanity check arguments */
+ ASSERT(calendar);
+ 700: 1e43 subs r3, r0, #1
+ 702: 4198 sbcs r0, r3
+ 704: b2c0 uxtb r0, r0
+ 706: 22e6 movs r2, #230 ; 0xe6
+ 708: 32ff adds r2, #255 ; 0xff
+ 70a: 4904 ldr r1, [pc, #16] ; (71c <calendar_enable+0x20>)
+ 70c: 4b04 ldr r3, [pc, #16] ; (720 <calendar_enable+0x24>)
+ 70e: 4798 blx r3
+
+ _calendar_enable(&calendar->device);
+ 710: 0020 movs r0, r4
+ 712: 4b04 ldr r3, [pc, #16] ; (724 <calendar_enable+0x28>)
+ 714: 4798 blx r3
+
+ return ERR_NONE;
+}
+ 716: 2000 movs r0, #0
+ 718: bd10 pop {r4, pc}
+ 71a: 46c0 nop ; (mov r8, r8)
+ 71c: 00001f90 .word 0x00001f90
+ 720: 00000a69 .word 0x00000a69
+ 724: 00000dd9 .word 0x00000dd9
+
+00000728 <calendar_set_time>:
+}
+
+/** \brief Set time for calendar
+ */
+int32_t calendar_set_time(struct calendar_descriptor *const calendar, struct calendar_time *const p_calendar_time)
+{
+ 728: b530 push {r4, r5, lr}
+ 72a: b083 sub sp, #12
+ 72c: 0004 movs r4, r0
+ 72e: 000d movs r5, r1
+ struct calendar_date_time dt;
+ uint32_t current_ts, new_ts;
+
+ /* Sanity check arguments */
+ ASSERT(calendar);
+ 730: 1e43 subs r3, r0, #1
+ 732: 4198 sbcs r0, r3
+ 734: b2c0 uxtb r0, r0
+ 736: 2283 movs r2, #131 ; 0x83
+ 738: 0092 lsls r2, r2, #2
+ 73a: 490e ldr r1, [pc, #56] ; (774 <calendar_set_time+0x4c>)
+ 73c: 4b0e ldr r3, [pc, #56] ; (778 <calendar_set_time+0x50>)
+ 73e: 4798 blx r3
+
+ /* convert time to timestamp */
+ current_ts = _calendar_get_counter(&calendar->device);
+ 740: 0020 movs r0, r4
+ 742: 4b0e ldr r3, [pc, #56] ; (77c <calendar_set_time+0x54>)
+ 744: 4798 blx r3
+ 746: 0001 movs r1, r0
+ convert_timestamp_to_datetime(calendar, current_ts, &dt);
+ 748: 466a mov r2, sp
+ 74a: 0020 movs r0, r4
+ 74c: 4b0c ldr r3, [pc, #48] ; (780 <calendar_set_time+0x58>)
+ 74e: 4798 blx r3
+ dt.time.sec = p_calendar_time->sec;
+ 750: 782b ldrb r3, [r5, #0]
+ 752: 466a mov r2, sp
+ 754: 7013 strb r3, [r2, #0]
+ dt.time.min = p_calendar_time->min;
+ 756: 786b ldrb r3, [r5, #1]
+ 758: 7053 strb r3, [r2, #1]
+ dt.time.hour = p_calendar_time->hour;
+ 75a: 78ab ldrb r3, [r5, #2]
+ 75c: 7093 strb r3, [r2, #2]
+
+ new_ts = convert_datetime_to_timestamp(calendar, &dt);
+ 75e: 4669 mov r1, sp
+ 760: 0020 movs r0, r4
+ 762: 4b08 ldr r3, [pc, #32] ; (784 <calendar_set_time+0x5c>)
+ 764: 4798 blx r3
+ 766: 0001 movs r1, r0
+
+ _calendar_set_counter(&calendar->device, new_ts);
+ 768: 0020 movs r0, r4
+ 76a: 4b07 ldr r3, [pc, #28] ; (788 <calendar_set_time+0x60>)
+ 76c: 4798 blx r3
+
+ return ERR_NONE;
+}
+ 76e: 2000 movs r0, #0
+ 770: b003 add sp, #12
+ 772: bd30 pop {r4, r5, pc}
+ 774: 00001f90 .word 0x00001f90
+ 778: 00000a69 .word 0x00000a69
+ 77c: 00000e55 .word 0x00000e55
+ 780: 0000040d .word 0x0000040d
+ 784: 000004b9 .word 0x000004b9
+ 788: 00000e1d .word 0x00000e1d
+
+0000078c <calendar_set_date>:
+
+/** \brief Set date for calendar
+ */
+int32_t calendar_set_date(struct calendar_descriptor *const calendar, struct calendar_date *const p_calendar_date)
+{
+ 78c: b530 push {r4, r5, lr}
+ 78e: b083 sub sp, #12
+ 790: 0004 movs r4, r0
+ 792: 000d movs r5, r1
+ struct calendar_date_time dt;
+ uint32_t current_ts, new_ts;
+
+ /* Sanity check arguments */
+ ASSERT(calendar);
+ 794: 1e43 subs r3, r0, #1
+ 796: 4198 sbcs r0, r3
+ 798: b2c0 uxtb r0, r0
+ 79a: 2289 movs r2, #137 ; 0x89
+ 79c: 0092 lsls r2, r2, #2
+ 79e: 490e ldr r1, [pc, #56] ; (7d8 <calendar_set_date+0x4c>)
+ 7a0: 4b0e ldr r3, [pc, #56] ; (7dc <calendar_set_date+0x50>)
+ 7a2: 4798 blx r3
+
+ /* convert date to timestamp */
+ current_ts = _calendar_get_counter(&calendar->device);
+ 7a4: 0020 movs r0, r4
+ 7a6: 4b0e ldr r3, [pc, #56] ; (7e0 <calendar_set_date+0x54>)
+ 7a8: 4798 blx r3
+ 7aa: 0001 movs r1, r0
+ convert_timestamp_to_datetime(calendar, current_ts, &dt);
+ 7ac: 466a mov r2, sp
+ 7ae: 0020 movs r0, r4
+ 7b0: 4b0c ldr r3, [pc, #48] ; (7e4 <calendar_set_date+0x58>)
+ 7b2: 4798 blx r3
+ dt.date.day = p_calendar_date->day;
+ 7b4: 782b ldrb r3, [r5, #0]
+ 7b6: 466a mov r2, sp
+ 7b8: 7113 strb r3, [r2, #4]
+ dt.date.month = p_calendar_date->month;
+ 7ba: 786b ldrb r3, [r5, #1]
+ 7bc: 7153 strb r3, [r2, #5]
+ dt.date.year = p_calendar_date->year;
+ 7be: 886b ldrh r3, [r5, #2]
+ 7c0: 80d3 strh r3, [r2, #6]
+
+ new_ts = convert_datetime_to_timestamp(calendar, &dt);
+ 7c2: 4669 mov r1, sp
+ 7c4: 0020 movs r0, r4
+ 7c6: 4b08 ldr r3, [pc, #32] ; (7e8 <calendar_set_date+0x5c>)
+ 7c8: 4798 blx r3
+ 7ca: 0001 movs r1, r0
+
+ _calendar_set_counter(&calendar->device, new_ts);
+ 7cc: 0020 movs r0, r4
+ 7ce: 4b07 ldr r3, [pc, #28] ; (7ec <calendar_set_date+0x60>)
+ 7d0: 4798 blx r3
+
+ return ERR_NONE;
+}
+ 7d2: 2000 movs r0, #0
+ 7d4: b003 add sp, #12
+ 7d6: bd30 pop {r4, r5, pc}
+ 7d8: 00001f90 .word 0x00001f90
+ 7dc: 00000a69 .word 0x00000a69
+ 7e0: 00000e55 .word 0x00000e55
+ 7e4: 0000040d .word 0x0000040d
+ 7e8: 000004b9 .word 0x000004b9
+ 7ec: 00000e1d .word 0x00000e1d
+
+000007f0 <calendar_get_date_time>:
+
+/** \brief Get date/time for calendar
+ */
+int32_t calendar_get_date_time(struct calendar_descriptor *const calendar, struct calendar_date_time *const date_time)
+{
+ 7f0: b570 push {r4, r5, r6, lr}
+ 7f2: 0004 movs r4, r0
+ 7f4: 000d movs r5, r1
+ uint32_t current_ts;
+
+ /* Sanity check arguments */
+ ASSERT(calendar);
+ 7f6: 1e43 subs r3, r0, #1
+ 7f8: 4198 sbcs r0, r3
+ 7fa: b2c0 uxtb r0, r0
+ 7fc: 4a06 ldr r2, [pc, #24] ; (818 <calendar_get_date_time+0x28>)
+ 7fe: 4907 ldr r1, [pc, #28] ; (81c <calendar_get_date_time+0x2c>)
+ 800: 4b07 ldr r3, [pc, #28] ; (820 <calendar_get_date_time+0x30>)
+ 802: 4798 blx r3
+
+ /* convert current timestamp to date/time */
+ current_ts = _calendar_get_counter(&calendar->device);
+ 804: 0020 movs r0, r4
+ 806: 4b07 ldr r3, [pc, #28] ; (824 <calendar_get_date_time+0x34>)
+ 808: 4798 blx r3
+ 80a: 0001 movs r1, r0
+ convert_timestamp_to_datetime(calendar, current_ts, date_time);
+ 80c: 002a movs r2, r5
+ 80e: 0020 movs r0, r4
+ 810: 4b05 ldr r3, [pc, #20] ; (828 <calendar_get_date_time+0x38>)
+ 812: 4798 blx r3
+
+ return ERR_NONE;
+}
+ 814: 2000 movs r0, #0
+ 816: bd70 pop {r4, r5, r6, pc}
+ 818: 0000023b .word 0x0000023b
+ 81c: 00001f90 .word 0x00001f90
+ 820: 00000a69 .word 0x00000a69
+ 824: 00000e55 .word 0x00000e55
+ 828: 0000040d .word 0x0000040d
+
+0000082c <delay_init>:
+
+/**
+ * \brief Initialize Delay driver
+ */
+void delay_init(void *const hw)
+{
+ 82c: b510 push {r4, lr}
+ _delay_init(hardware = hw);
+ 82e: 4b02 ldr r3, [pc, #8] ; (838 <delay_init+0xc>)
+ 830: 6018 str r0, [r3, #0]
+ 832: 4b02 ldr r3, [pc, #8] ; (83c <delay_init+0x10>)
+ 834: 4798 blx r3
+}
+ 836: bd10 pop {r4, pc}
+ 838: 20000054 .word 0x20000054
+ 83c: 00001571 .word 0x00001571
+
+00000840 <i2c_m_sync_write>:
+
+/**
+ * \brief Sync version of I2C I/O write
+ */
+static int32_t i2c_m_sync_write(struct io_descriptor *io, const uint8_t *buf, const uint16_t n)
+{
+ 840: b510 push {r4, lr}
+ 842: b084 sub sp, #16
+ struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io);
+ struct _i2c_m_msg msg;
+ int32_t ret;
+
+ msg.addr = i2c->slave_addr;
+ 844: 3814 subs r0, #20
+ 846: 8b84 ldrh r4, [r0, #28]
+ 848: ab01 add r3, sp, #4
+ 84a: 801c strh r4, [r3, #0]
+ msg.len = n;
+ 84c: 0014 movs r4, r2
+ 84e: 9202 str r2, [sp, #8]
+ msg.flags = I2C_M_STOP;
+ 850: 4a06 ldr r2, [pc, #24] ; (86c <i2c_m_sync_write+0x2c>)
+ 852: 805a strh r2, [r3, #2]
+ msg.buffer = (uint8_t *)buf;
+ 854: 9103 str r1, [sp, #12]
+
+ ret = _i2c_m_sync_transfer(&i2c->device, &msg);
+ 856: 0019 movs r1, r3
+ 858: 4b05 ldr r3, [pc, #20] ; (870 <i2c_m_sync_write+0x30>)
+ 85a: 4798 blx r3
+
+ if (ret) {
+ 85c: 2800 cmp r0, #0
+ 85e: d102 bne.n 866 <i2c_m_sync_write+0x26>
+ return ret;
+ }
+
+ return n;
+}
+ 860: 0020 movs r0, r4
+ 862: b004 add sp, #16
+ 864: bd10 pop {r4, pc}
+ return ret;
+ 866: 0004 movs r4, r0
+ 868: e7fa b.n 860 <i2c_m_sync_write+0x20>
+ 86a: 46c0 nop ; (mov r8, r8)
+ 86c: ffff8000 .word 0xffff8000
+ 870: 000012e1 .word 0x000012e1
+
+00000874 <i2c_m_sync_read>:
+{
+ 874: b510 push {r4, lr}
+ 876: b084 sub sp, #16
+ msg.addr = i2c->slave_addr;
+ 878: 3814 subs r0, #20
+ 87a: 8b84 ldrh r4, [r0, #28]
+ 87c: ab01 add r3, sp, #4
+ 87e: 801c strh r4, [r3, #0]
+ msg.len = n;
+ 880: 0014 movs r4, r2
+ 882: 9202 str r2, [sp, #8]
+ msg.flags = I2C_M_STOP | I2C_M_RD;
+ 884: 4a06 ldr r2, [pc, #24] ; (8a0 <i2c_m_sync_read+0x2c>)
+ 886: 805a strh r2, [r3, #2]
+ msg.buffer = buf;
+ 888: 9103 str r1, [sp, #12]
+ ret = _i2c_m_sync_transfer(&i2c->device, &msg);
+ 88a: 0019 movs r1, r3
+ 88c: 4b05 ldr r3, [pc, #20] ; (8a4 <i2c_m_sync_read+0x30>)
+ 88e: 4798 blx r3
+ if (ret) {
+ 890: 2800 cmp r0, #0
+ 892: d102 bne.n 89a <i2c_m_sync_read+0x26>
+}
+ 894: 0020 movs r0, r4
+ 896: b004 add sp, #16
+ 898: bd10 pop {r4, pc}
+ return ret;
+ 89a: 0004 movs r4, r0
+ 89c: e7fa b.n 894 <i2c_m_sync_read+0x20>
+ 89e: 46c0 nop ; (mov r8, r8)
+ 8a0: ffff8001 .word 0xffff8001
+ 8a4: 000012e1 .word 0x000012e1
+
+000008a8 <i2c_m_sync_init>:
+
+/**
+ * \brief Sync version of i2c initialize
+ */
+int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw)
+{
+ 8a8: b570 push {r4, r5, r6, lr}
+ 8aa: 0004 movs r4, r0
+ 8ac: 000d movs r5, r1
+ int32_t init_status;
+ ASSERT(i2c);
+ 8ae: 1e43 subs r3, r0, #1
+ 8b0: 4198 sbcs r0, r3
+ 8b2: b2c0 uxtb r0, r0
+ 8b4: 225e movs r2, #94 ; 0x5e
+ 8b6: 4907 ldr r1, [pc, #28] ; (8d4 <i2c_m_sync_init+0x2c>)
+ 8b8: 4b07 ldr r3, [pc, #28] ; (8d8 <i2c_m_sync_init+0x30>)
+ 8ba: 4798 blx r3
+
+ init_status = _i2c_m_sync_init(&i2c->device, hw);
+ 8bc: 0029 movs r1, r5
+ 8be: 0020 movs r0, r4
+ 8c0: 4b06 ldr r3, [pc, #24] ; (8dc <i2c_m_sync_init+0x34>)
+ 8c2: 4798 blx r3
+ if (init_status) {
+ 8c4: 2800 cmp r0, #0
+ 8c6: d103 bne.n 8d0 <i2c_m_sync_init+0x28>
+ return init_status;
+ }
+
+ /* Init I/O */
+ i2c->io.read = i2c_m_sync_read;
+ 8c8: 4b05 ldr r3, [pc, #20] ; (8e0 <i2c_m_sync_init+0x38>)
+ 8ca: 61a3 str r3, [r4, #24]
+ i2c->io.write = i2c_m_sync_write;
+ 8cc: 4b05 ldr r3, [pc, #20] ; (8e4 <i2c_m_sync_init+0x3c>)
+ 8ce: 6163 str r3, [r4, #20]
+
+ return ERR_NONE;
+}
+ 8d0: bd70 pop {r4, r5, r6, pc}
+ 8d2: 46c0 nop ; (mov r8, r8)
+ 8d4: 00001fac .word 0x00001fac
+ 8d8: 00000a69 .word 0x00000a69
+ 8dc: 00001231 .word 0x00001231
+ 8e0: 00000875 .word 0x00000875
+ 8e4: 00000841 .word 0x00000841
+
+000008e8 <i2c_m_sync_enable>:
+
+/**
+ * \brief Sync version of i2c enable
+ */
+int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c)
+{
+ 8e8: b510 push {r4, lr}
+ return _i2c_m_sync_enable(&i2c->device);
+ 8ea: 4b01 ldr r3, [pc, #4] ; (8f0 <i2c_m_sync_enable+0x8>)
+ 8ec: 4798 blx r3
+}
+ 8ee: bd10 pop {r4, pc}
+ 8f0: 00001261 .word 0x00001261
+
+000008f4 <i2c_m_sync_set_slaveaddr>:
+/**
+ * \brief Sync version of i2c set slave address
+ */
+int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len)
+{
+ return i2c->slave_addr = (addr & 0x3ff) | (addr_len & I2C_M_TEN);
+ 8f4: 0589 lsls r1, r1, #22
+ 8f6: 0d89 lsrs r1, r1, #22
+ 8f8: 2380 movs r3, #128 ; 0x80
+ 8fa: 00db lsls r3, r3, #3
+ 8fc: 401a ands r2, r3
+ 8fe: 430a orrs r2, r1
+ 900: 8382 strh r2, [r0, #28]
+}
+ 902: 0010 movs r0, r2
+ 904: 4770 bx lr
+
+00000906 <i2c_m_sync_get_io_descriptor>:
+/**
+ * \brief Retrieve I/O descriptor
+ */
+int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io)
+{
+ *io = &i2c->io;
+ 906: 3014 adds r0, #20
+ 908: 6008 str r0, [r1, #0]
+ return ERR_NONE;
+}
+ 90a: 2000 movs r0, #0
+ 90c: 4770 bx lr
+ ...
+
+00000910 <io_write>:
+
+/**
+ * \brief I/O write interface
+ */
+int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length)
+{
+ 910: b570 push {r4, r5, r6, lr}
+ 912: 0004 movs r4, r0
+ 914: 000d movs r5, r1
+ 916: 0016 movs r6, r2
+ ASSERT(io_descr && buf);
+ 918: 2800 cmp r0, #0
+ 91a: d00e beq.n 93a <io_write+0x2a>
+ 91c: 2900 cmp r1, #0
+ 91e: d00a beq.n 936 <io_write+0x26>
+ 920: 2001 movs r0, #1
+ 922: 2234 movs r2, #52 ; 0x34
+ 924: 4906 ldr r1, [pc, #24] ; (940 <io_write+0x30>)
+ 926: 4b07 ldr r3, [pc, #28] ; (944 <io_write+0x34>)
+ 928: 4798 blx r3
+ return io_descr->write(io_descr, buf, length);
+ 92a: 6823 ldr r3, [r4, #0]
+ 92c: 0032 movs r2, r6
+ 92e: 0029 movs r1, r5
+ 930: 0020 movs r0, r4
+ 932: 4798 blx r3
+}
+ 934: bd70 pop {r4, r5, r6, pc}
+ ASSERT(io_descr && buf);
+ 936: 2000 movs r0, #0
+ 938: e7f3 b.n 922 <io_write+0x12>
+ 93a: 2000 movs r0, #0
+ 93c: e7f1 b.n 922 <io_write+0x12>
+ 93e: 46c0 nop ; (mov r8, r8)
+ 940: 00001fc8 .word 0x00001fc8
+ 944: 00000a69 .word 0x00000a69
+
+00000948 <io_read>:
+
+/**
+ * \brief I/O read interface
+ */
+int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length)
+{
+ 948: b570 push {r4, r5, r6, lr}
+ 94a: 0004 movs r4, r0
+ 94c: 000d movs r5, r1
+ 94e: 0016 movs r6, r2
+ ASSERT(io_descr && buf);
+ 950: 2800 cmp r0, #0
+ 952: d00e beq.n 972 <io_read+0x2a>
+ 954: 2900 cmp r1, #0
+ 956: d00a beq.n 96e <io_read+0x26>
+ 958: 2001 movs r0, #1
+ 95a: 223d movs r2, #61 ; 0x3d
+ 95c: 4906 ldr r1, [pc, #24] ; (978 <io_read+0x30>)
+ 95e: 4b07 ldr r3, [pc, #28] ; (97c <io_read+0x34>)
+ 960: 4798 blx r3
+ return io_descr->read(io_descr, buf, length);
+ 962: 6863 ldr r3, [r4, #4]
+ 964: 0032 movs r2, r6
+ 966: 0029 movs r1, r5
+ 968: 0020 movs r0, r4
+ 96a: 4798 blx r3
+}
+ 96c: bd70 pop {r4, r5, r6, pc}
+ ASSERT(io_descr && buf);
+ 96e: 2000 movs r0, #0
+ 970: e7f3 b.n 95a <io_read+0x12>
+ 972: 2000 movs r0, #0
+ 974: e7f1 b.n 95a <io_read+0x12>
+ 976: 46c0 nop ; (mov r8, r8)
+ 978: 00001fc8 .word 0x00001fc8
+ 97c: 00000a69 .word 0x00000a69
+
+00000980 <pwm_period_expired>:
+
+/**
+ * \internal Process interrupts caused by period experied
+ */
+static void pwm_period_expired(struct _pwm_device *device)
+{
+ 980: b510 push {r4, lr}
+ struct pwm_descriptor *const descr = CONTAINER_OF(device, struct pwm_descriptor, device);
+
+ if (descr->pwm_cb.period) {
+ 982: 6943 ldr r3, [r0, #20]
+ 984: 2b00 cmp r3, #0
+ 986: d000 beq.n 98a <pwm_period_expired+0xa>
+ descr->pwm_cb.period(descr);
+ 988: 4798 blx r3
+ }
+}
+ 98a: bd10 pop {r4, pc}
+
+0000098c <pwm_detect_fault>:
+
+/**
+ * \internal Process interrupts caused by pwm fault
+ */
+static void pwm_detect_fault(struct _pwm_device *device)
+{
+ 98c: b510 push {r4, lr}
+ struct pwm_descriptor *const descr = CONTAINER_OF(device, struct pwm_descriptor, device);
+
+ if (descr->pwm_cb.error) {
+ 98e: 6983 ldr r3, [r0, #24]
+ 990: 2b00 cmp r3, #0
+ 992: d000 beq.n 996 <pwm_detect_fault+0xa>
+ descr->pwm_cb.error(descr);
+ 994: 4798 blx r3
+ }
+}
+ 996: bd10 pop {r4, pc}
+
+00000998 <pwm_init>:
+{
+ 998: b570 push {r4, r5, r6, lr}
+ 99a: 0004 movs r4, r0
+ 99c: 000d movs r5, r1
+ 99e: 0016 movs r6, r2
+ ASSERT(descr && hw && func);
+ 9a0: 2800 cmp r0, #0
+ 9a2: d015 beq.n 9d0 <pwm_init+0x38>
+ 9a4: 2900 cmp r1, #0
+ 9a6: d015 beq.n 9d4 <pwm_init+0x3c>
+ 9a8: 2a00 cmp r2, #0
+ 9aa: d00f beq.n 9cc <pwm_init+0x34>
+ 9ac: 2001 movs r0, #1
+ 9ae: 2233 movs r2, #51 ; 0x33
+ 9b0: 4909 ldr r1, [pc, #36] ; (9d8 <pwm_init+0x40>)
+ 9b2: 4b0a ldr r3, [pc, #40] ; (9dc <pwm_init+0x44>)
+ 9b4: 4798 blx r3
+ descr->func = func;
+ 9b6: 61e6 str r6, [r4, #28]
+ descr->func->init(&descr->device, hw);
+ 9b8: 6833 ldr r3, [r6, #0]
+ 9ba: 0029 movs r1, r5
+ 9bc: 0020 movs r0, r4
+ 9be: 4798 blx r3
+ descr->device.callback.pwm_period_cb = pwm_period_expired;
+ 9c0: 4b07 ldr r3, [pc, #28] ; (9e0 <pwm_init+0x48>)
+ 9c2: 6023 str r3, [r4, #0]
+ descr->device.callback.pwm_error_cb = pwm_detect_fault;
+ 9c4: 4b07 ldr r3, [pc, #28] ; (9e4 <pwm_init+0x4c>)
+ 9c6: 6063 str r3, [r4, #4]
+}
+ 9c8: 2000 movs r0, #0
+ 9ca: bd70 pop {r4, r5, r6, pc}
+ ASSERT(descr && hw && func);
+ 9cc: 2000 movs r0, #0
+ 9ce: e7ee b.n 9ae <pwm_init+0x16>
+ 9d0: 2000 movs r0, #0
+ 9d2: e7ec b.n 9ae <pwm_init+0x16>
+ 9d4: 2000 movs r0, #0
+ 9d6: e7ea b.n 9ae <pwm_init+0x16>
+ 9d8: 00001fdc .word 0x00001fdc
+ 9dc: 00000a69 .word 0x00000a69
+ 9e0: 00000981 .word 0x00000981
+ 9e4: 0000098d .word 0x0000098d
+
+000009e8 <pwm_enable>:
+{
+ 9e8: b510 push {r4, lr}
+ 9ea: 1e04 subs r4, r0, #0
+ ASSERT(descr && descr->func);
+ 9ec: d015 beq.n a1a <pwm_enable+0x32>
+ 9ee: 69c3 ldr r3, [r0, #28]
+ 9f0: 2b00 cmp r3, #0
+ 9f2: d010 beq.n a16 <pwm_enable+0x2e>
+ 9f4: 2001 movs r0, #1
+ 9f6: 224b movs r2, #75 ; 0x4b
+ 9f8: 490a ldr r1, [pc, #40] ; (a24 <pwm_enable+0x3c>)
+ 9fa: 4b0b ldr r3, [pc, #44] ; (a28 <pwm_enable+0x40>)
+ 9fc: 4798 blx r3
+ if (descr->func->is_pwm_enabled(&descr->device)) {
+ 9fe: 69e3 ldr r3, [r4, #28]
+ a00: 695b ldr r3, [r3, #20]
+ a02: 0020 movs r0, r4
+ a04: 4798 blx r3
+ a06: 2800 cmp r0, #0
+ a08: d109 bne.n a1e <pwm_enable+0x36>
+ descr->func->start_pwm(&descr->device);
+ a0a: 69e3 ldr r3, [r4, #28]
+ a0c: 689b ldr r3, [r3, #8]
+ a0e: 0020 movs r0, r4
+ a10: 4798 blx r3
+ return ERR_NONE;
+ a12: 2000 movs r0, #0
+}
+ a14: bd10 pop {r4, pc}
+ ASSERT(descr && descr->func);
+ a16: 2000 movs r0, #0
+ a18: e7ed b.n 9f6 <pwm_enable+0xe>
+ a1a: 2000 movs r0, #0
+ a1c: e7eb b.n 9f6 <pwm_enable+0xe>
+ return ERR_DENIED;
+ a1e: 2011 movs r0, #17
+ a20: 4240 negs r0, r0
+ a22: e7f7 b.n a14 <pwm_enable+0x2c>
+ a24: 00001fdc .word 0x00001fdc
+ a28: 00000a69 .word 0x00000a69
+
+00000a2c <pwm_set_parameters>:
+{
+ a2c: b570 push {r4, r5, r6, lr}
+ a2e: 0004 movs r4, r0
+ a30: 000d movs r5, r1
+ a32: 0016 movs r6, r2
+ ASSERT(descr && descr->func);
+ a34: 2800 cmp r0, #0
+ a36: d011 beq.n a5c <pwm_set_parameters+0x30>
+ a38: 69c3 ldr r3, [r0, #28]
+ a3a: 2b00 cmp r3, #0
+ a3c: d00c beq.n a58 <pwm_set_parameters+0x2c>
+ a3e: 2001 movs r0, #1
+ a40: 227d movs r2, #125 ; 0x7d
+ a42: 4907 ldr r1, [pc, #28] ; (a60 <pwm_set_parameters+0x34>)
+ a44: 4b07 ldr r3, [pc, #28] ; (a64 <pwm_set_parameters+0x38>)
+ a46: 4798 blx r3
+ descr->func->set_pwm_param(&descr->device, period, duty_cycle);
+ a48: 69e3 ldr r3, [r4, #28]
+ a4a: 691b ldr r3, [r3, #16]
+ a4c: 0032 movs r2, r6
+ a4e: 0029 movs r1, r5
+ a50: 0020 movs r0, r4
+ a52: 4798 blx r3
+}
+ a54: 2000 movs r0, #0
+ a56: bd70 pop {r4, r5, r6, pc}
+ ASSERT(descr && descr->func);
+ a58: 2000 movs r0, #0
+ a5a: e7f1 b.n a40 <pwm_set_parameters+0x14>
+ a5c: 2000 movs r0, #0
+ a5e: e7ef b.n a40 <pwm_set_parameters+0x14>
+ a60: 00001fdc .word 0x00001fdc
+ a64: 00000a69 .word 0x00000a69
+
+00000a68 <assert>:
+/**
+ * \brief Assert function
+ */
+void assert(const bool condition, const char *const file, const int line)
+{
+ if (!(condition)) {
+ a68: 2800 cmp r0, #0
+ a6a: d100 bne.n a6e <assert+0x6>
+ __asm("BKPT #0");
+ a6c: be00 bkpt 0x0000
+ }
+ (void)file;
+ (void)line;
+}
+ a6e: 4770 bx lr
+
+00000a70 <event_subscribe>:
+
+static struct list_descriptor events;
+static uint8_t subscribed[EVENT_MASK_SIZE];
+
+int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb)
+{
+ a70: b5f8 push {r3, r4, r5, r6, r7, lr}
+ a72: 0005 movs r5, r0
+ a74: 0017 movs r7, r2
+ /* get byte and bit number of the given event in the event mask */
+ const uint8_t position = id >> 3;
+ a76: 08ce lsrs r6, r1, #3
+ const uint8_t mask = 1 << (id & 0x7);
+ a78: 2307 movs r3, #7
+ a7a: 400b ands r3, r1
+ a7c: 2401 movs r4, #1
+ a7e: 409c lsls r4, r3
+ a80: b2e4 uxtb r4, r4
+
+ ASSERT(event && cb && (id < EVENT_MAX_AMOUNT));
+ a82: 2800 cmp r0, #0
+ a84: d01e beq.n ac4 <event_subscribe+0x54>
+ a86: 2a00 cmp r2, #0
+ a88: d01e beq.n ac8 <event_subscribe+0x58>
+ a8a: 2907 cmp r1, #7
+ a8c: d91e bls.n acc <event_subscribe+0x5c>
+ a8e: 2000 movs r0, #0
+ a90: 2231 movs r2, #49 ; 0x31
+ a92: 4914 ldr r1, [pc, #80] ; (ae4 <event_subscribe+0x74>)
+ a94: 4b14 ldr r3, [pc, #80] ; (ae8 <event_subscribe+0x78>)
+ a96: 4798 blx r3
+
+ if (event->mask[position] & mask) {
+ a98: 19ab adds r3, r5, r6
+ a9a: 791b ldrb r3, [r3, #4]
+ a9c: 4223 tst r3, r4
+ a9e: d11e bne.n ade <event_subscribe+0x6e>
+ return ERR_NO_CHANGE; /* Already subscribed */
+ }
+
+ if (!is_list_element(&events, event)) {
+ aa0: 0029 movs r1, r5
+ aa2: 4812 ldr r0, [pc, #72] ; (aec <event_subscribe+0x7c>)
+ aa4: 4b12 ldr r3, [pc, #72] ; (af0 <event_subscribe+0x80>)
+ aa6: 4798 blx r3
+ aa8: 2800 cmp r0, #0
+ aaa: d011 beq.n ad0 <event_subscribe+0x60>
+ memset(event->mask, 0, EVENT_MASK_SIZE);
+ list_insert_as_head(&events, event);
+ }
+ event->cb = cb;
+ aac: 60af str r7, [r5, #8]
+ event->mask[position] |= mask;
+ aae: 19ad adds r5, r5, r6
+ ab0: 792b ldrb r3, [r5, #4]
+ ab2: 4323 orrs r3, r4
+ ab4: 712b strb r3, [r5, #4]
+
+ subscribed[position] |= mask;
+ ab6: 4b0d ldr r3, [pc, #52] ; (aec <event_subscribe+0x7c>)
+ ab8: 199b adds r3, r3, r6
+ aba: 791a ldrb r2, [r3, #4]
+ abc: 4314 orrs r4, r2
+ abe: 711c strb r4, [r3, #4]
+
+ return ERR_NONE;
+ ac0: 2000 movs r0, #0
+}
+ ac2: bdf8 pop {r3, r4, r5, r6, r7, pc}
+ ASSERT(event && cb && (id < EVENT_MAX_AMOUNT));
+ ac4: 2000 movs r0, #0
+ ac6: e7e3 b.n a90 <event_subscribe+0x20>
+ ac8: 2000 movs r0, #0
+ aca: e7e1 b.n a90 <event_subscribe+0x20>
+ acc: 2001 movs r0, #1
+ ace: e7df b.n a90 <event_subscribe+0x20>
+ memset(event->mask, 0, EVENT_MASK_SIZE);
+ ad0: 2300 movs r3, #0
+ ad2: 712b strb r3, [r5, #4]
+ list_insert_as_head(&events, event);
+ ad4: 0029 movs r1, r5
+ ad6: 4805 ldr r0, [pc, #20] ; (aec <event_subscribe+0x7c>)
+ ad8: 4b06 ldr r3, [pc, #24] ; (af4 <event_subscribe+0x84>)
+ ada: 4798 blx r3
+ adc: e7e6 b.n aac <event_subscribe+0x3c>
+ return ERR_NO_CHANGE; /* Already subscribed */
+ ade: 2002 movs r0, #2
+ ae0: 4240 negs r0, r0
+ ae2: e7ee b.n ac2 <event_subscribe+0x52>
+ ae4: 00001ff4 .word 0x00001ff4
+ ae8: 00000a69 .word 0x00000a69
+ aec: 20000058 .word 0x20000058
+ af0: 00000af9 .word 0x00000af9
+ af4: 00000b11 .word 0x00000b11
+
+00000af8 <is_list_element>:
+ * \brief Check whether element belongs to list
+ */
+bool is_list_element(const struct list_descriptor *const list, const void *const element)
+{
+ struct list_element *it;
+ for (it = list->head; it; it = it->next) {
+ af8: 6803 ldr r3, [r0, #0]
+ afa: 2b00 cmp r3, #0
+ afc: d003 beq.n b06 <is_list_element+0xe>
+ if (it == element) {
+ afe: 428b cmp r3, r1
+ b00: d003 beq.n b0a <is_list_element+0x12>
+ for (it = list->head; it; it = it->next) {
+ b02: 681b ldr r3, [r3, #0]
+ b04: e7f9 b.n afa <is_list_element+0x2>
+ return true;
+ }
+ }
+
+ return false;
+ b06: 2000 movs r0, #0
+}
+ b08: 4770 bx lr
+ return true;
+ b0a: 2001 movs r0, #1
+ b0c: e7fc b.n b08 <is_list_element+0x10>
+ ...
+
+00000b10 <list_insert_as_head>:
+
+/**
+ * \brief Insert an element as list head
+ */
+void list_insert_as_head(struct list_descriptor *const list, void *const element)
+{
+ b10: b570 push {r4, r5, r6, lr}
+ b12: 0004 movs r4, r0
+ b14: 000d movs r5, r1
+ ASSERT(!is_list_element(list, element));
+ b16: 4b06 ldr r3, [pc, #24] ; (b30 <list_insert_as_head+0x20>)
+ b18: 4798 blx r3
+ b1a: 2301 movs r3, #1
+ b1c: 4058 eors r0, r3
+ b1e: b2c0 uxtb r0, r0
+ b20: 2239 movs r2, #57 ; 0x39
+ b22: 4904 ldr r1, [pc, #16] ; (b34 <list_insert_as_head+0x24>)
+ b24: 4b04 ldr r3, [pc, #16] ; (b38 <list_insert_as_head+0x28>)
+ b26: 4798 blx r3
+
+ ((struct list_element *)element)->next = list->head;
+ b28: 6823 ldr r3, [r4, #0]
+ b2a: 602b str r3, [r5, #0]
+ list->head = (struct list_element *)element;
+ b2c: 6025 str r5, [r4, #0]
+}
+ b2e: bd70 pop {r4, r5, r6, pc}
+ b30: 00000af9 .word 0x00000af9
+ b34: 00002014 .word 0x00002014
+ b38: 00000a69 .word 0x00000a69
+
+00000b3c <_init_chip>:
+
+/**
+ * \brief Initialize the hardware abstraction layer
+ */
+void _init_chip(void)
+{
+ b3c: b510 push {r4, lr}
+}
+
+static inline void hri_nvmctrl_set_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+ NVMCTRL_CRITICAL_SECTION_ENTER();
+ ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_RWS(mask);
+ b3e: 4b09 ldr r3, [pc, #36] ; (b64 <_init_chip+0x28>)
+ b40: 685a ldr r2, [r3, #4]
+ b42: 605a str r2, [r3, #4]
+ hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE);
+
+ _set_performance_level(2);
+ b44: 2002 movs r0, #2
+ b46: 4b08 ldr r3, [pc, #32] ; (b68 <_init_chip+0x2c>)
+ b48: 4798 blx r3
+
+ _osc32kctrl_init_sources();
+ b4a: 4b08 ldr r3, [pc, #32] ; (b6c <_init_chip+0x30>)
+ b4c: 4798 blx r3
+ _oscctrl_init_sources();
+ b4e: 4b08 ldr r3, [pc, #32] ; (b70 <_init_chip+0x34>)
+ b50: 4798 blx r3
+ _mclk_init();
+ b52: 4b08 ldr r3, [pc, #32] ; (b74 <_init_chip+0x38>)
+ b54: 4798 blx r3
+#if _GCLK_INIT_1ST
+ _gclk_init_generators_by_fref(_GCLK_INIT_1ST);
+#endif
+ _oscctrl_init_referenced_generators();
+ b56: 4b08 ldr r3, [pc, #32] ; (b78 <_init_chip+0x3c>)
+ b58: 4798 blx r3
+ _gclk_init_generators_by_fref(_GCLK_INIT_LAST);
+ b5a: 201f movs r0, #31
+ b5c: 4b07 ldr r3, [pc, #28] ; (b7c <_init_chip+0x40>)
+ b5e: 4798 blx r3
+#endif
+
+#if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3)
+ _port_event_init();
+#endif
+}
+ b60: bd10 pop {r4, pc}
+ b62: 46c0 nop ; (mov r8, r8)
+ b64: 41004000 .word 0x41004000
+ b68: 00000ce9 .word 0x00000ce9
+ b6c: 00000c89 .word 0x00000c89
+ b70: 00000cad .word 0x00000cad
+ b74: 00000c79 .word 0x00000c79
+ b78: 00000ce5 .word 0x00000ce5
+ b7c: 00000c41 .word 0x00000c41
+
+00000b80 <_ext_irq_handler>:
+
+/**
+ * \brief Inter EIC interrupt handler
+ */
+static void _ext_irq_handler(void)
+{
+ b80: b5f0 push {r4, r5, r6, r7, lr}
+ b82: b083 sub sp, #12
+ return tmp;
+}
+
+static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw)
+{
+ return ((Eic *)hw)->INTFLAG.reg;
+ b84: 4b25 ldr r3, [pc, #148] ; (c1c <_ext_irq_handler+0x9c>)
+ b86: 695a ldr r2, [r3, #20]
+ volatile uint32_t flags = hri_eic_read_INTFLAG_reg(EIC);
+ b88: 9201 str r2, [sp, #4]
+ int8_t pos;
+ uint32_t pin = INVALID_PIN_NUMBER;
+
+ hri_eic_clear_INTFLAG_reg(EIC, flags);
+ b8a: 9a01 ldr r2, [sp, #4]
+}
+
+static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask)
+{
+ ((Eic *)hw)->INTFLAG.reg = mask;
+ b8c: 615a str r2, [r3, #20]
+
+ ASSERT(callback);
+ b8e: 4b24 ldr r3, [pc, #144] ; (c20 <_ext_irq_handler+0xa0>)
+ b90: 6818 ldr r0, [r3, #0]
+ b92: 1e43 subs r3, r0, #1
+ b94: 4198 sbcs r0, r3
+ b96: b2c0 uxtb r0, r0
+ b98: 22da movs r2, #218 ; 0xda
+ b9a: 4922 ldr r1, [pc, #136] ; (c24 <_ext_irq_handler+0xa4>)
+ b9c: 4b22 ldr r3, [pc, #136] ; (c28 <_ext_irq_handler+0xa8>)
+ b9e: 4798 blx r3
+ uint32_t pin = INVALID_PIN_NUMBER;
+ ba0: 2501 movs r5, #1
+ ba2: 426d negs r5, r5
+
+ while (flags) {
+ ba4: e02f b.n c06 <_ext_irq_handler+0x86>
+ uint8_t lower = 0, middle, upper = EXT_IRQ_AMOUNT;
+
+ while (upper >= lower) {
+ middle = (upper + lower) >> 1;
+ if (_map[middle].extint == pos) {
+ pin = _map[middle].pin;
+ ba6: 00db lsls r3, r3, #3
+ ba8: 4a20 ldr r2, [pc, #128] ; (c2c <_ext_irq_handler+0xac>)
+ baa: 18d3 adds r3, r2, r3
+ bac: 685d ldr r5, [r3, #4]
+ } else {
+ upper = middle - 1;
+ }
+ }
+
+ if (INVALID_PIN_NUMBER != pin) {
+ bae: 1c6b adds r3, r5, #1
+ bb0: d003 beq.n bba <_ext_irq_handler+0x3a>
+ callback(pin);
+ bb2: 4b1b ldr r3, [pc, #108] ; (c20 <_ext_irq_handler+0xa0>)
+ bb4: 681b ldr r3, [r3, #0]
+ bb6: 0028 movs r0, r5
+ bb8: 4798 blx r3
+ }
+ flags &= ~(1ul << pos);
+ bba: 2201 movs r2, #1
+ bbc: 40a2 lsls r2, r4
+ bbe: 9b01 ldr r3, [sp, #4]
+ bc0: 4393 bics r3, r2
+ bc2: 9301 str r3, [sp, #4]
+ pos = ffs(flags) - 1;
+ bc4: 9801 ldr r0, [sp, #4]
+ bc6: 4b1a ldr r3, [pc, #104] ; (c30 <_ext_irq_handler+0xb0>)
+ bc8: 4798 blx r3
+ bca: 3801 subs r0, #1
+ bcc: b244 sxtb r4, r0
+ while (-1 != pos) {
+ bce: 1c63 adds r3, r4, #1
+ bd0: d014 beq.n bfc <_ext_irq_handler+0x7c>
+ bd2: 2603 movs r6, #3
+ bd4: 2000 movs r0, #0
+ bd6: e001 b.n bdc <_ext_irq_handler+0x5c>
+ upper = middle - 1;
+ bd8: 3901 subs r1, #1
+ bda: b2ce uxtb r6, r1
+ while (upper >= lower) {
+ bdc: 42b0 cmp r0, r6
+ bde: d8e6 bhi.n bae <_ext_irq_handler+0x2e>
+ middle = (upper + lower) >> 1;
+ be0: 1833 adds r3, r6, r0
+ be2: 105b asrs r3, r3, #1
+ be4: b2d9 uxtb r1, r3
+ be6: 22ff movs r2, #255 ; 0xff
+ be8: 4013 ands r3, r2
+ if (_map[middle].extint == pos) {
+ bea: 00df lsls r7, r3, #3
+ bec: 4a0f ldr r2, [pc, #60] ; (c2c <_ext_irq_handler+0xac>)
+ bee: 5cba ldrb r2, [r7, r2]
+ bf0: 42a2 cmp r2, r4
+ bf2: d0d8 beq.n ba6 <_ext_irq_handler+0x26>
+ if (_map[middle].extint < pos) {
+ bf4: daf0 bge.n bd8 <_ext_irq_handler+0x58>
+ lower = middle + 1;
+ bf6: 3101 adds r1, #1
+ bf8: b2c8 uxtb r0, r1
+ bfa: e7ef b.n bdc <_ext_irq_handler+0x5c>
+ return ((Eic *)hw)->INTFLAG.reg;
+ bfc: 4b07 ldr r3, [pc, #28] ; (c1c <_ext_irq_handler+0x9c>)
+ bfe: 695a ldr r2, [r3, #20]
+ }
+ flags = hri_eic_read_INTFLAG_reg(EIC);
+ c00: 9201 str r2, [sp, #4]
+ hri_eic_clear_INTFLAG_reg(EIC, flags);
+ c02: 9a01 ldr r2, [sp, #4]
+ ((Eic *)hw)->INTFLAG.reg = mask;
+ c04: 615a str r2, [r3, #20]
+ while (flags) {
+ c06: 9b01 ldr r3, [sp, #4]
+ c08: 2b00 cmp r3, #0
+ c0a: d005 beq.n c18 <_ext_irq_handler+0x98>
+ pos = ffs(flags) - 1;
+ c0c: 9801 ldr r0, [sp, #4]
+ c0e: 4b08 ldr r3, [pc, #32] ; (c30 <_ext_irq_handler+0xb0>)
+ c10: 4798 blx r3
+ c12: 3801 subs r0, #1
+ c14: b244 sxtb r4, r0
+ while (-1 != pos) {
+ c16: e7da b.n bce <_ext_irq_handler+0x4e>
+ }
+}
+ c18: b003 add sp, #12
+ c1a: bdf0 pop {r4, r5, r6, r7, pc}
+ c1c: 40002800 .word 0x40002800
+ c20: 20000060 .word 0x20000060
+ c24: 0000204c .word 0x0000204c
+ c28: 00000a69 .word 0x00000a69
+ c2c: 00002034 .word 0x00002034
+ c30: 00001e5d .word 0x00001e5d
+
+00000c34 <EIC_Handler>:
+
+/**
+ * \brief EIC interrupt handler
+ */
+void EIC_Handler(void)
+{
+ c34: b510 push {r4, lr}
+ _ext_irq_handler();
+ c36: 4b01 ldr r3, [pc, #4] ; (c3c <EIC_Handler+0x8>)
+ c38: 4798 blx r3
+}
+ c3a: bd10 pop {r4, pc}
+ c3c: 00000b81 .word 0x00000b81
+
+00000c40 <_gclk_init_generators_by_fref>:
+
+void _gclk_init_generators_by_fref(uint32_t bm)
+{
+
+#if CONF_GCLK_GENERATOR_0_CONFIG == 1
+ if (bm & (1ul << 0)) {
+ c40: 07c3 lsls r3, r0, #31
+ c42: d507 bpl.n c54 <_gclk_init_generators_by_fref+0x14>
+ ((Gclk *)hw)->GENCTRL[index].reg = data;
+ c44: 4a09 ldr r2, [pc, #36] ; (c6c <_gclk_init_generators_by_fref+0x2c>)
+ c46: 4b0a ldr r3, [pc, #40] ; (c70 <_gclk_init_generators_by_fref+0x30>)
+ c48: 621a str r2, [r3, #32]
+ while (((Gclk *)hw)->SYNCBUSY.reg & reg) {
+ c4a: 4b09 ldr r3, [pc, #36] ; (c70 <_gclk_init_generators_by_fref+0x30>)
+ c4c: 685b ldr r3, [r3, #4]
+ c4e: 227d movs r2, #125 ; 0x7d
+ c50: 421a tst r2, r3
+ c52: d1fa bne.n c4a <_gclk_init_generators_by_fref+0xa>
+ | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE);
+ }
+#endif
+
+#if CONF_GCLK_GENERATOR_3_CONFIG == 1
+ if (bm & (1ul << 3)) {
+ c54: 0703 lsls r3, r0, #28
+ c56: d507 bpl.n c68 <_gclk_init_generators_by_fref+0x28>
+ ((Gclk *)hw)->GENCTRL[index].reg = data;
+ c58: 4a06 ldr r2, [pc, #24] ; (c74 <_gclk_init_generators_by_fref+0x34>)
+ c5a: 4b05 ldr r3, [pc, #20] ; (c70 <_gclk_init_generators_by_fref+0x30>)
+ c5c: 62da str r2, [r3, #44] ; 0x2c
+ while (((Gclk *)hw)->SYNCBUSY.reg & reg) {
+ c5e: 4b04 ldr r3, [pc, #16] ; (c70 <_gclk_init_generators_by_fref+0x30>)
+ c60: 685b ldr r3, [r3, #4]
+ c62: 227d movs r2, #125 ; 0x7d
+ c64: 421a tst r2, r3
+ c66: d1fa bne.n c5e <_gclk_init_generators_by_fref+0x1e>
+ | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos)
+ | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos)
+ | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE);
+ }
+#endif
+}
+ c68: 4770 bx lr
+ c6a: 46c0 nop ; (mov r8, r8)
+ c6c: 00010105 .word 0x00010105
+ c70: 40001c00 .word 0x40001c00
+ c74: 00012304 .word 0x00012304
+
+00000c78 <_mclk_init>:
+ ((Mclk *)hw)->BUPDIV.reg = data;
+ c78: 4b02 ldr r3, [pc, #8] ; (c84 <_mclk_init+0xc>)
+ c7a: 2208 movs r2, #8
+ c7c: 719a strb r2, [r3, #6]
+ ((Mclk *)hw)->CPUDIV.reg = data;
+ c7e: 3a07 subs r2, #7
+ c80: 711a strb r2, [r3, #4]
+void _mclk_init(void)
+{
+ void *hw = (void *)MCLK;
+ hri_mclk_write_BUPDIV_reg(hw, MCLK_BUPDIV_BUPDIV(CONF_MCLK_BUPDIV));
+ hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_CPUDIV(CONF_MCLK_CPUDIV));
+}
+ c82: 4770 bx lr
+ c84: 40000800 .word 0x40000800
+
+00000c88 <_osc32kctrl_init_sources>:
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data)
+{
+ OSC32KCTRL_CRITICAL_SECTION_ENTER();
+ ((Osc32kctrl *)hw)->XOSC32K.reg = data;
+ c88: 4a07 ldr r2, [pc, #28] ; (ca8 <_osc32kctrl_init_sources+0x20>)
+ c8a: 239e movs r3, #158 ; 0x9e
+ c8c: 8293 strh r3, [r2, #20]
+}
+
+static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data)
+{
+ OSC32KCTRL_CRITICAL_SECTION_ENTER();
+ ((Osc32kctrl *)hw)->CFDCTRL.reg = data;
+ c8e: 2300 movs r3, #0
+ c90: 7593 strb r3, [r2, #22]
+}
+
+static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data)
+{
+ OSC32KCTRL_CRITICAL_SECTION_ENTER();
+ ((Osc32kctrl *)hw)->EVCTRL.reg = data;
+ c92: 75d3 strb r3, [r2, #23]
+}
+
+static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw)
+{
+ uint32_t tmp;
+ tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+ c94: 69d3 ldr r3, [r2, #28]
+ tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB_Msk) >> OSC32KCTRL_OSCULP32K_CALIB_Pos;
+ c96: 0a1b lsrs r3, r3, #8
+ calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw);
+ hri_osc32kctrl_write_OSCULP32K_reg(hw,
+#if CONF_OSC32K_CALIB_ENABLE == 1
+ OSC32KCTRL_OSCULP32K_CALIB(CONF_OSC32K_CALIB)
+#else
+ OSC32KCTRL_OSCULP32K_CALIB(calib)
+ c98: 021b lsls r3, r3, #8
+ c9a: 21f8 movs r1, #248 ; 0xf8
+ c9c: 0149 lsls r1, r1, #5
+ c9e: 400b ands r3, r1
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data)
+{
+ OSC32KCTRL_CRITICAL_SECTION_ENTER();
+ ((Osc32kctrl *)hw)->OSCULP32K.reg = data;
+ ca0: 61d3 str r3, [r2, #28]
+ ((Osc32kctrl *)hw)->RTCCTRL.reg = data;
+ ca2: 2304 movs r3, #4
+ ca4: 7413 strb r3, [r2, #16]
+#endif
+#endif
+
+ hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL));
+ (void)calib;
+}
+ ca6: 4770 bx lr
+ ca8: 40001400 .word 0x40001400
+
+00000cac <_oscctrl_init_sources>:
+}
+
+static inline void hri_oscctrl_write_OSC16MCTRL_reg(const void *const hw, hri_oscctrl_osc16mctrl_reg_t data)
+{
+ OSCCTRL_CRITICAL_SECTION_ENTER();
+ ((Oscctrl *)hw)->OSC16MCTRL.reg = data;
+ cac: 2282 movs r2, #130 ; 0x82
+ cae: 4b0c ldr r3, [pc, #48] ; (ce0 <_oscctrl_init_sources+0x34>)
+ cb0: 751a strb r2, [r3, #20]
+ while (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & reg) {
+ cb2: 2338 movs r3, #56 ; 0x38
+ cb4: 4a0a ldr r2, [pc, #40] ; (ce0 <_oscctrl_init_sources+0x34>)
+ cb6: 5cd3 ldrb r3, [r2, r3]
+ cb8: 079b lsls r3, r3, #30
+ cba: d4fa bmi.n cb2 <_oscctrl_init_sources+0x6>
+ return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_OSC16MRDY) >> OSCCTRL_STATUS_OSC16MRDY_Pos;
+ cbc: 4b08 ldr r3, [pc, #32] ; (ce0 <_oscctrl_init_sources+0x34>)
+ cbe: 68db ldr r3, [r3, #12]
+#endif
+#endif
+
+#if CONF_OSC16M_CONFIG == 1
+#if CONF_OSC16M_ENABLE == 1
+ while (!hri_oscctrl_get_STATUS_OSC16MRDY_bit(hw))
+ cc0: 06db lsls r3, r3, #27
+ cc2: d5fb bpl.n cbc <_oscctrl_init_sources+0x10>
+ ((Oscctrl *)hw)->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_ONDEMAND;
+ cc4: 4a06 ldr r2, [pc, #24] ; (ce0 <_oscctrl_init_sources+0x34>)
+ cc6: 7d13 ldrb r3, [r2, #20]
+ cc8: 2180 movs r1, #128 ; 0x80
+ cca: 4249 negs r1, r1
+ ccc: 430b orrs r3, r1
+ cce: b2db uxtb r3, r3
+ cd0: 7513 strb r3, [r2, #20]
+ while (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & reg) {
+ cd2: 2338 movs r3, #56 ; 0x38
+ cd4: 4a02 ldr r2, [pc, #8] ; (ce0 <_oscctrl_init_sources+0x34>)
+ cd6: 5cd2 ldrb r2, [r2, r3]
+ cd8: 3b2a subs r3, #42 ; 0x2a
+ cda: 421a tst r2, r3
+ cdc: d1f9 bne.n cd2 <_oscctrl_init_sources+0x26>
+#if CONF_OSC16M_ONDEMAND == 1
+ hri_oscctrl_set_OSC16MCTRL_ONDEMAND_bit(hw);
+#endif
+#endif
+ (void)hw;
+}
+ cde: 4770 bx lr
+ ce0: 40001000 .word 0x40001000
+
+00000ce4 <_oscctrl_init_referenced_generators>:
+#if CONF_DFLL_CONFIG == 1
+ while (hri_gclk_read_SYNCBUSY_reg(GCLK))
+ ;
+#endif
+ (void)hw, (void)tmp;
+}
+ ce4: 4770 bx lr
+ ...
+
+00000ce8 <_set_performance_level>:
+}
+
+static inline hri_pm_plcfg_reg_t hri_pm_get_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask)
+{
+ uint8_t tmp;
+ tmp = ((Pm *)hw)->PLCFG.reg;
+ ce8: 4b09 ldr r3, [pc, #36] ; (d10 <_set_performance_level+0x28>)
+ cea: 789b ldrb r3, [r3, #2]
+ tmp = (tmp & PM_PLCFG_PLSEL(mask)) >> PM_PLCFG_PLSEL_Pos;
+ cec: 2203 movs r2, #3
+ cee: 4013 ands r3, r2
+/**
+ * \brief Set performance level
+ */
+void _set_performance_level(const uint8_t level)
+{
+ if (hri_pm_get_PLCFG_PLSEL_bf(PM, PM_PLCFG_PLSEL_Msk) != level) {
+ cf0: 4298 cmp r0, r3
+ cf2: d00c beq.n d0e <_set_performance_level+0x26>
+ ((Pm *)hw)->INTFLAG.reg = mask;
+ cf4: 4a06 ldr r2, [pc, #24] ; (d10 <_set_performance_level+0x28>)
+ cf6: 23ff movs r3, #255 ; 0xff
+ cf8: 7193 strb r3, [r2, #6]
+
+static inline void hri_pm_write_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t data)
+{
+ uint8_t tmp;
+ PM_CRITICAL_SECTION_ENTER();
+ tmp = ((Pm *)hw)->PLCFG.reg;
+ cfa: 7893 ldrb r3, [r2, #2]
+ tmp &= ~PM_PLCFG_PLSEL_Msk;
+ cfc: 2103 movs r1, #3
+ cfe: 438b bics r3, r1
+ tmp |= PM_PLCFG_PLSEL(data);
+ d00: 4008 ands r0, r1
+ d02: 4318 orrs r0, r3
+ ((Pm *)hw)->PLCFG.reg = tmp;
+ d04: 7090 strb r0, [r2, #2]
+ return ((Pm *)hw)->INTFLAG.reg;
+ d06: 4b02 ldr r3, [pc, #8] ; (d10 <_set_performance_level+0x28>)
+ d08: 799b ldrb r3, [r3, #6]
+ hri_pm_clear_INTFLAG_reg(PM, 0xFF);
+ hri_pm_write_PLCFG_PLSEL_bf(PM, level);
+ while (!hri_pm_read_INTFLAG_reg(PM))
+ d0a: 2b00 cmp r3, #0
+ d0c: d0fb beq.n d06 <_set_performance_level+0x1e>
+ ;
+ }
+}
+ d0e: 4770 bx lr
+ d10: 40000400 .word 0x40000400
+
+00000d14 <_rtc_interrupt_handler>:
+ * \brief RTC interrupt handler
+ *
+ * \param[in] dev The pointer to calendar device struct
+ */
+static void _rtc_interrupt_handler(struct calendar_dev *dev)
+{
+ d14: b510 push {r4, lr}
+ d16: 0004 movs r4, r0
+ /* Read and mask interrupt flag register */
+ uint16_t interrupt_status = hri_rtcmode0_read_INTFLAG_reg(dev->hw);
+ d18: 6802 ldr r2, [r0, #0]
+ return tmp;
+}
+
+static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_read_INTFLAG_reg(const void *const hw)
+{
+ return ((Rtc *)hw)->MODE0.INTFLAG.reg;
+ d1a: 8991 ldrh r1, [r2, #12]
+ return tmp;
+}
+
+static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_read_INTEN_reg(const void *const hw)
+{
+ return ((Rtc *)hw)->MODE0.INTENSET.reg;
+ d1c: 8953 ldrh r3, [r2, #10]
+ uint16_t interrupt_enabled = hri_rtcmode0_read_INTEN_reg(dev->hw);
+
+ if ((interrupt_status & interrupt_enabled) & RTC_MODE2_INTFLAG_ALARM0) {
+ d1e: 400b ands r3, r1
+ d20: 05da lsls r2, r3, #23
+ d22: d402 bmi.n d2a <_rtc_interrupt_handler+0x16>
+ dev->callback(dev);
+
+ /* Clear interrupt flag */
+ hri_rtcmode0_clear_interrupt_CMP0_bit(dev->hw);
+ } else if ((interrupt_status & interrupt_enabled) & RTC_MODE2_INTFLAG_TAMPER) {
+ d24: 045b lsls r3, r3, #17
+ d26: d407 bmi.n d38 <_rtc_interrupt_handler+0x24>
+ dev->callback_tamper(dev);
+
+ /* Clear interrupt flag */
+ hri_rtcmode0_clear_interrupt_TAMPER_bit(dev->hw);
+ }
+}
+ d28: bd10 pop {r4, pc}
+ dev->callback(dev);
+ d2a: 6843 ldr r3, [r0, #4]
+ d2c: 4798 blx r3
+ hri_rtcmode0_clear_interrupt_CMP0_bit(dev->hw);
+ d2e: 6823 ldr r3, [r4, #0]
+ ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0;
+ d30: 2280 movs r2, #128 ; 0x80
+ d32: 0052 lsls r2, r2, #1
+ d34: 819a strh r2, [r3, #12]
+ d36: e7f7 b.n d28 <_rtc_interrupt_handler+0x14>
+ dev->callback_tamper(dev);
+ d38: 6883 ldr r3, [r0, #8]
+ d3a: 4798 blx r3
+ hri_rtcmode0_clear_interrupt_TAMPER_bit(dev->hw);
+ d3c: 6823 ldr r3, [r4, #0]
+ ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER;
+ d3e: 2280 movs r2, #128 ; 0x80
+ d40: 01d2 lsls r2, r2, #7
+ d42: 819a strh r2, [r3, #12]
+}
+ d44: e7f0 b.n d28 <_rtc_interrupt_handler+0x14>
+ ...
+
+00000d48 <_calendar_init>:
+{
+ d48: b510 push {r4, lr}
+ d4a: 1e04 subs r4, r0, #0
+ ASSERT(dev && dev->hw);
+ d4c: d037 beq.n dbe <_calendar_init+0x76>
+ d4e: 6803 ldr r3, [r0, #0]
+ d50: 2b00 cmp r3, #0
+ d52: d032 beq.n dba <_calendar_init+0x72>
+ d54: 2001 movs r0, #1
+ d56: 222f movs r2, #47 ; 0x2f
+ d58: 491a ldr r1, [pc, #104] ; (dc4 <_calendar_init+0x7c>)
+ d5a: 4b1b ldr r3, [pc, #108] ; (dc8 <_calendar_init+0x80>)
+ d5c: 4798 blx r3
+ _rtc_dev = dev;
+ d5e: 4b1b ldr r3, [pc, #108] ; (dcc <_calendar_init+0x84>)
+ d60: 601c str r4, [r3, #0]
+ if (hri_rtcmode0_get_CTRLA_ENABLE_bit(dev->hw)) {
+ d62: 6821 ldr r1, [r4, #0]
+ while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) {
+ d64: 690a ldr r2, [r1, #16]
+ d66: 4b1a ldr r3, [pc, #104] ; (dd0 <_calendar_init+0x88>)
+ d68: 421a tst r2, r3
+ d6a: d1fb bne.n d64 <_calendar_init+0x1c>
+
+static inline bool hri_rtcmode0_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+ uint16_t tmp;
+ hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+ tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+ d6c: 880b ldrh r3, [r1, #0]
+ d6e: 079b lsls r3, r3, #30
+ d70: d50b bpl.n d8a <_calendar_init+0x42>
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+ RTC_CRITICAL_SECTION_ENTER();
+ ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE;
+ d72: 880b ldrh r3, [r1, #0]
+ d74: 2202 movs r2, #2
+ d76: 4393 bics r3, r2
+ d78: 800b strh r3, [r1, #0]
+ while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) {
+ d7a: 690a ldr r2, [r1, #16]
+ d7c: 4b14 ldr r3, [pc, #80] ; (dd0 <_calendar_init+0x88>)
+ d7e: 421a tst r2, r3
+ d80: d1fb bne.n d7a <_calendar_init+0x32>
+ hri_rtcmode0_wait_for_sync(dev->hw, RTC_MODE0_SYNCBUSY_ENABLE);
+ d82: 6822 ldr r2, [r4, #0]
+ d84: 6913 ldr r3, [r2, #16]
+ d86: 079b lsls r3, r3, #30
+ d88: d4fc bmi.n d84 <_calendar_init+0x3c>
+ hri_rtcmode0_set_CTRLA_SWRST_bit(dev->hw);
+ d8a: 6822 ldr r2, [r4, #0]
+ ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST;
+ d8c: 8813 ldrh r3, [r2, #0]
+ d8e: 2101 movs r1, #1
+ d90: 430b orrs r3, r1
+ d92: b29b uxth r3, r3
+ d94: 8013 strh r3, [r2, #0]
+ while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) {
+ d96: 6913 ldr r3, [r2, #16]
+ d98: 07db lsls r3, r3, #31
+ d9a: d4fc bmi.n d96 <_calendar_init+0x4e>
+ hri_rtcmode0_wait_for_sync(dev->hw, RTC_MODE0_SYNCBUSY_SWRST);
+ d9c: 6823 ldr r3, [r4, #0]
+ d9e: 691a ldr r2, [r3, #16]
+ da0: 07d2 lsls r2, r2, #31
+ da2: d4fc bmi.n d9e <_calendar_init+0x56>
+}
+
+static inline void hri_rtcmode0_write_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t data)
+{
+ RTC_CRITICAL_SECTION_ENTER();
+ ((Rtc *)hw)->MODE0.CTRLA.reg = data;
+ da4: 4a0b ldr r2, [pc, #44] ; (dd4 <_calendar_init+0x8c>)
+ da6: 801a strh r2, [r3, #0]
+ while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) {
+ da8: 6919 ldr r1, [r3, #16]
+ daa: 4a09 ldr r2, [pc, #36] ; (dd0 <_calendar_init+0x88>)
+ dac: 4211 tst r1, r2
+ dae: d1fb bne.n da8 <_calendar_init+0x60>
+ dev->hw,
+ db0: 6823 ldr r3, [r4, #0]
+}
+
+static inline void hri_rtc_write_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+ RTC_CRITICAL_SECTION_ENTER();
+ ((Rtc *)hw)->MODE0.TAMPCTRL.reg = data;
+ db2: 2200 movs r2, #0
+ db4: 661a str r2, [r3, #96] ; 0x60
+}
+ db6: 2000 movs r0, #0
+ db8: bd10 pop {r4, pc}
+ ASSERT(dev && dev->hw);
+ dba: 2000 movs r0, #0
+ dbc: e7cb b.n d56 <_calendar_init+0xe>
+ dbe: 2000 movs r0, #0
+ dc0: e7c9 b.n d56 <_calendar_init+0xe>
+ dc2: 46c0 nop ; (mov r8, r8)
+ dc4: 00002064 .word 0x00002064
+ dc8: 00000a69 .word 0x00000a69
+ dcc: 20000064 .word 0x20000064
+ dd0: 00008003 .word 0x00008003
+ dd4: ffff8b00 .word 0xffff8b00
+
+00000dd8 <_calendar_enable>:
+{
+ dd8: b510 push {r4, lr}
+ dda: 1e04 subs r4, r0, #0
+ ASSERT(dev && dev->hw);
+ ddc: d015 beq.n e0a <_calendar_enable+0x32>
+ dde: 6803 ldr r3, [r0, #0]
+ de0: 2b00 cmp r3, #0
+ de2: d010 beq.n e06 <_calendar_enable+0x2e>
+ de4: 2001 movs r0, #1
+ de6: 2273 movs r2, #115 ; 0x73
+ de8: 4909 ldr r1, [pc, #36] ; (e10 <_calendar_enable+0x38>)
+ dea: 4b0a ldr r3, [pc, #40] ; (e14 <_calendar_enable+0x3c>)
+ dec: 4798 blx r3
+ hri_rtcmode0_set_CTRLA_ENABLE_bit(dev->hw);
+ dee: 6821 ldr r1, [r4, #0]
+ ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE;
+ df0: 880b ldrh r3, [r1, #0]
+ df2: 2202 movs r2, #2
+ df4: 4313 orrs r3, r2
+ df6: b29b uxth r3, r3
+ df8: 800b strh r3, [r1, #0]
+ while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) {
+ dfa: 690a ldr r2, [r1, #16]
+ dfc: 4b06 ldr r3, [pc, #24] ; (e18 <_calendar_enable+0x40>)
+ dfe: 421a tst r2, r3
+ e00: d1fb bne.n dfa <_calendar_enable+0x22>
+}
+ e02: 2000 movs r0, #0
+ e04: bd10 pop {r4, pc}
+ ASSERT(dev && dev->hw);
+ e06: 2000 movs r0, #0
+ e08: e7ed b.n de6 <_calendar_enable+0xe>
+ e0a: 2000 movs r0, #0
+ e0c: e7eb b.n de6 <_calendar_enable+0xe>
+ e0e: 46c0 nop ; (mov r8, r8)
+ e10: 00002064 .word 0x00002064
+ e14: 00000a69 .word 0x00000a69
+ e18: 00008003 .word 0x00008003
+
+00000e1c <_calendar_set_counter>:
+{
+ e1c: b570 push {r4, r5, r6, lr}
+ e1e: 0004 movs r4, r0
+ e20: 000d movs r5, r1
+ ASSERT(dev && dev->hw);
+ e22: 2800 cmp r0, #0
+ e24: d010 beq.n e48 <_calendar_set_counter+0x2c>
+ e26: 6803 ldr r3, [r0, #0]
+ e28: 2b00 cmp r3, #0
+ e2a: d00b beq.n e44 <_calendar_set_counter+0x28>
+ e2c: 2001 movs r0, #1
+ e2e: 228b movs r2, #139 ; 0x8b
+ e30: 4906 ldr r1, [pc, #24] ; (e4c <_calendar_set_counter+0x30>)
+ e32: 4b07 ldr r3, [pc, #28] ; (e50 <_calendar_set_counter+0x34>)
+ e34: 4798 blx r3
+ hri_rtcmode0_write_COUNT_reg(dev->hw, counter);
+ e36: 6822 ldr r2, [r4, #0]
+ ((Rtc *)hw)->MODE0.COUNT.reg = data;
+ e38: 6195 str r5, [r2, #24]
+ while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) {
+ e3a: 6913 ldr r3, [r2, #16]
+ e3c: 071b lsls r3, r3, #28
+ e3e: d4fc bmi.n e3a <_calendar_set_counter+0x1e>
+}
+ e40: 2000 movs r0, #0
+ e42: bd70 pop {r4, r5, r6, pc}
+ ASSERT(dev && dev->hw);
+ e44: 2000 movs r0, #0
+ e46: e7f2 b.n e2e <_calendar_set_counter+0x12>
+ e48: 2000 movs r0, #0
+ e4a: e7f0 b.n e2e <_calendar_set_counter+0x12>
+ e4c: 00002064 .word 0x00002064
+ e50: 00000a69 .word 0x00000a69
+
+00000e54 <_calendar_get_counter>:
+{
+ e54: b510 push {r4, lr}
+ e56: 1e04 subs r4, r0, #0
+ ASSERT(dev && dev->hw);
+ e58: d00f beq.n e7a <_calendar_get_counter+0x26>
+ e5a: 6803 ldr r3, [r0, #0]
+ e5c: 2b00 cmp r3, #0
+ e5e: d00a beq.n e76 <_calendar_get_counter+0x22>
+ e60: 2001 movs r0, #1
+ e62: 2297 movs r2, #151 ; 0x97
+ e64: 4906 ldr r1, [pc, #24] ; (e80 <_calendar_get_counter+0x2c>)
+ e66: 4b07 ldr r3, [pc, #28] ; (e84 <_calendar_get_counter+0x30>)
+ e68: 4798 blx r3
+ return hri_rtcmode0_read_COUNT_reg(dev->hw);
+ e6a: 6822 ldr r2, [r4, #0]
+ e6c: 6913 ldr r3, [r2, #16]
+ e6e: 071b lsls r3, r3, #28
+ e70: d4fc bmi.n e6c <_calendar_get_counter+0x18>
+ return ((Rtc *)hw)->MODE0.COUNT.reg;
+ e72: 6990 ldr r0, [r2, #24]
+}
+ e74: bd10 pop {r4, pc}
+ ASSERT(dev && dev->hw);
+ e76: 2000 movs r0, #0
+ e78: e7f3 b.n e62 <_calendar_get_counter+0xe>
+ e7a: 2000 movs r0, #0
+ e7c: e7f1 b.n e62 <_calendar_get_counter+0xe>
+ e7e: 46c0 nop ; (mov r8, r8)
+ e80: 00002064 .word 0x00002064
+ e84: 00000a69 .word 0x00000a69
+
+00000e88 <RTC_Handler>:
+
+/**
+ * \brief Rtc interrupt handler
+ */
+void RTC_Handler(void)
+{
+ e88: b510 push {r4, lr}
+ _rtc_interrupt_handler(_rtc_dev);
+ e8a: 4b02 ldr r3, [pc, #8] ; (e94 <RTC_Handler+0xc>)
+ e8c: 6818 ldr r0, [r3, #0]
+ e8e: 4b02 ldr r3, [pc, #8] ; (e98 <RTC_Handler+0x10>)
+ e90: 4798 blx r3
+}
+ e92: bd10 pop {r4, pc}
+ e94: 20000064 .word 0x20000064
+ e98: 00000d15 .word 0x00000d15
+
+00000e9c <_sercom_get_hardware_index>:
+{
+#ifdef _UNIT_TEST_
+ return ((uint32_t)hw - (uint32_t)SERCOM0) / sizeof(Sercom);
+#endif
+
+ return ((uint32_t)hw - (uint32_t)SERCOM0) >> 10;
+ e9c: 4b02 ldr r3, [pc, #8] ; (ea8 <_sercom_get_hardware_index+0xc>)
+ e9e: 469c mov ip, r3
+ ea0: 4460 add r0, ip
+ ea2: 0a80 lsrs r0, r0, #10
+ ea4: b2c0 uxtb r0, r0
+}
+ ea6: 4770 bx lr
+ ea8: bdfffc00 .word 0xbdfffc00
+
+00000eac <_get_i2cm_index>:
+ * \param[in] hw The pointer to hardware instance
+
+ * \return The ordinal number of the given sercom hardware instance
+ */
+static int8_t _get_i2cm_index(const void *const hw)
+{
+ eac: b510 push {r4, lr}
+ uint8_t sercom_offset = _sercom_get_hardware_index(hw);
+ eae: 4b0d ldr r3, [pc, #52] ; (ee4 <_get_i2cm_index+0x38>)
+ eb0: 4798 blx r3
+ uint8_t i;
+
+ for (i = 0; i < ARRAY_SIZE(_i2cms); i++) {
+ eb2: 2300 movs r3, #0
+ eb4: 2b00 cmp r3, #0
+ eb6: d008 beq.n eca <_get_i2cm_index+0x1e>
+ if (_i2cms[i].number == sercom_offset) {
+ return i;
+ }
+ }
+
+ ASSERT(false);
+ eb8: 22e6 movs r2, #230 ; 0xe6
+ eba: 0092 lsls r2, r2, #2
+ ebc: 490a ldr r1, [pc, #40] ; (ee8 <_get_i2cm_index+0x3c>)
+ ebe: 2000 movs r0, #0
+ ec0: 4b0a ldr r3, [pc, #40] ; (eec <_get_i2cm_index+0x40>)
+ ec2: 4798 blx r3
+ return -1;
+ ec4: 2001 movs r0, #1
+ ec6: 4240 negs r0, r0
+}
+ ec8: bd10 pop {r4, pc}
+ if (_i2cms[i].number == sercom_offset) {
+ eca: 005a lsls r2, r3, #1
+ ecc: 18d2 adds r2, r2, r3
+ ece: 00d1 lsls r1, r2, #3
+ ed0: 4a07 ldr r2, [pc, #28] ; (ef0 <_get_i2cm_index+0x44>)
+ ed2: 1852 adds r2, r2, r1
+ ed4: 7d12 ldrb r2, [r2, #20]
+ ed6: 4290 cmp r0, r2
+ ed8: d002 beq.n ee0 <_get_i2cm_index+0x34>
+ for (i = 0; i < ARRAY_SIZE(_i2cms); i++) {
+ eda: 3301 adds r3, #1
+ edc: b2db uxtb r3, r3
+ ede: e7e9 b.n eb4 <_get_i2cm_index+0x8>
+ return i;
+ ee0: b258 sxtb r0, r3
+ ee2: e7f1 b.n ec8 <_get_i2cm_index+0x1c>
+ ee4: 00000e9d .word 0x00000e9d
+ ee8: 000020cc .word 0x000020cc
+ eec: 00000a69 .word 0x00000a69
+ ef0: 0000207c .word 0x0000207c
+
+00000ef4 <_i2c_m_sync_init_impl>:
+ }
+ return ERR_NONE;
+}
+
+static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw)
+{
+ ef4: b570 push {r4, r5, r6, lr}
+ ef6: 0005 movs r5, r0
+ ef8: 000c movs r4, r1
+ uint8_t i = _get_i2cm_index(hw);
+ efa: 0008 movs r0, r1
+ efc: 4b2d ldr r3, [pc, #180] ; (fb4 <_i2c_m_sync_init_impl+0xc0>)
+ efe: 4798 blx r3
+ f00: b2c0 uxtb r0, r0
+ };
+}
+
+static inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg)
+{
+ return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg;
+ f02: 69e3 ldr r3, [r4, #28]
+
+ if (!hri_sercomi2cm_is_syncing(hw, SERCOM_I2CM_SYNCBUSY_SWRST)) {
+ f04: 07db lsls r3, r3, #31
+ f06: d41d bmi.n f44 <_i2c_m_sync_init_impl+0x50>
+ uint32_t mode = _i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_MODE_Msk;
+ f08: 0043 lsls r3, r0, #1
+ f0a: 181b adds r3, r3, r0
+ f0c: 00da lsls r2, r3, #3
+ f0e: 4b2a ldr r3, [pc, #168] ; (fb8 <_i2c_m_sync_init_impl+0xc4>)
+ f10: 189b adds r3, r3, r2
+ f12: 699a ldr r2, [r3, #24]
+ f14: 231c movs r3, #28
+ f16: 401a ands r2, r3
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ f18: 69e3 ldr r3, [r4, #28]
+ f1a: 079b lsls r3, r3, #30
+ f1c: d1fc bne.n f18 <_i2c_m_sync_init_impl+0x24>
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_reg(const void *const hw,
+ hri_sercomi2cm_ctrla_reg_t mask)
+{
+ uint32_t tmp;
+ hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+ tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+ f1e: 6823 ldr r3, [r4, #0]
+ if (hri_sercomi2cm_get_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_ENABLE)) {
+ f20: 079b lsls r3, r3, #30
+ f22: d509 bpl.n f38 <_i2c_m_sync_init_impl+0x44>
+ ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE;
+ f24: 6823 ldr r3, [r4, #0]
+ f26: 2102 movs r1, #2
+ f28: 438b bics r3, r1
+ f2a: 6023 str r3, [r4, #0]
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ f2c: 69e3 ldr r3, [r4, #28]
+ f2e: 079b lsls r3, r3, #30
+ f30: d1fc bne.n f2c <_i2c_m_sync_init_impl+0x38>
+ f32: 69e3 ldr r3, [r4, #28]
+ f34: 079b lsls r3, r3, #30
+ f36: d4fc bmi.n f32 <_i2c_m_sync_init_impl+0x3e>
+ hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw);
+ hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_ENABLE);
+ }
+ hri_sercomi2cm_write_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_SWRST | mode);
+ f38: 2301 movs r3, #1
+ f3a: 4313 orrs r3, r2
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+ SERCOM_CRITICAL_SECTION_ENTER();
+ ((Sercom *)hw)->I2CM.CTRLA.reg = data;
+ f3c: 6023 str r3, [r4, #0]
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ f3e: 69e3 ldr r3, [r4, #28]
+ f40: 079b lsls r3, r3, #30
+ f42: d1fc bne.n f3e <_i2c_m_sync_init_impl+0x4a>
+ f44: 69e3 ldr r3, [r4, #28]
+ f46: 07db lsls r3, r3, #31
+ f48: d4fc bmi.n f44 <_i2c_m_sync_init_impl+0x50>
+ }
+ hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST);
+
+ hri_sercomi2cm_write_CTRLA_reg(hw, _i2cms[i].ctrl_a);
+ f4a: 0043 lsls r3, r0, #1
+ f4c: 181b adds r3, r3, r0
+ f4e: 00da lsls r2, r3, #3
+ f50: 4b19 ldr r3, [pc, #100] ; (fb8 <_i2c_m_sync_init_impl+0xc4>)
+ f52: 189b adds r3, r3, r2
+ f54: 699b ldr r3, [r3, #24]
+ ((Sercom *)hw)->I2CM.CTRLA.reg = data;
+ f56: 6023 str r3, [r4, #0]
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ f58: 69e3 ldr r3, [r4, #28]
+ f5a: 079b lsls r3, r3, #30
+ f5c: d1fc bne.n f58 <_i2c_m_sync_init_impl+0x64>
+ hri_sercomi2cm_write_CTRLB_reg(hw, _i2cms[i].ctrl_b);
+ f5e: 0043 lsls r3, r0, #1
+ f60: 181b adds r3, r3, r0
+ f62: 00da lsls r2, r3, #3
+ f64: 4b14 ldr r3, [pc, #80] ; (fb8 <_i2c_m_sync_init_impl+0xc4>)
+ f66: 189b adds r3, r3, r2
+ f68: 69db ldr r3, [r3, #28]
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data)
+{
+ SERCOM_CRITICAL_SECTION_ENTER();
+ ((Sercom *)hw)->I2CM.CTRLB.reg = data;
+ f6a: 6063 str r3, [r4, #4]
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ f6c: 69e3 ldr r3, [r4, #28]
+ f6e: 075b lsls r3, r3, #29
+ f70: d4fc bmi.n f6c <_i2c_m_sync_init_impl+0x78>
+ hri_sercomi2cm_write_BAUD_reg(hw, _i2cms[i].baud);
+ f72: 0042 lsls r2, r0, #1
+ f74: 1812 adds r2, r2, r0
+ f76: 00d1 lsls r1, r2, #3
+ f78: 4b0f ldr r3, [pc, #60] ; (fb8 <_i2c_m_sync_init_impl+0xc4>)
+ f7a: 185b adds r3, r3, r1
+}
+
+static inline void hri_sercomi2cm_write_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+ SERCOM_CRITICAL_SECTION_ENTER();
+ ((Sercom *)hw)->I2CM.BAUD.reg = data;
+ f7c: 6a1a ldr r2, [r3, #32]
+ f7e: 60e2 str r2, [r4, #12]
+
+ service->mode = (_i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos;
+ f80: 7eda ldrb r2, [r3, #27]
+ f82: 2303 movs r3, #3
+ f84: 401a ands r2, r3
+ f86: 81aa strh r2, [r5, #12]
+ hri_sercomi2cm_write_ADDR_HS_bit(hw, service->mode < I2C_HS ? 0 : 1);
+ f88: 3b02 subs r3, #2
+ f8a: 4293 cmp r3, r2
+ f8c: 419b sbcs r3, r3
+ f8e: 425b negs r3, r3
+
+static inline void hri_sercomi2cm_write_ADDR_HS_bit(const void *const hw, bool value)
+{
+ uint32_t tmp;
+ SERCOM_CRITICAL_SECTION_ENTER();
+ tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+ f90: 6a62 ldr r2, [r4, #36] ; 0x24
+ tmp &= ~SERCOM_I2CM_ADDR_HS;
+ f92: 490a ldr r1, [pc, #40] ; (fbc <_i2c_m_sync_init_impl+0xc8>)
+ f94: 400a ands r2, r1
+ tmp |= value << SERCOM_I2CM_ADDR_HS_Pos;
+ f96: 039b lsls r3, r3, #14
+ f98: 4313 orrs r3, r2
+ ((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+ f9a: 6263 str r3, [r4, #36] ; 0x24
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ f9c: 69e3 ldr r3, [r4, #28]
+ f9e: 075b lsls r3, r3, #29
+ fa0: d4fc bmi.n f9c <_i2c_m_sync_init_impl+0xa8>
+
+ service->trise = _i2cms[i].trise;
+ fa2: 0043 lsls r3, r0, #1
+ fa4: 1818 adds r0, r3, r0
+ fa6: 00c2 lsls r2, r0, #3
+ fa8: 4b03 ldr r3, [pc, #12] ; (fb8 <_i2c_m_sync_init_impl+0xc4>)
+ faa: 189b adds r3, r3, r2
+ fac: 8cdb ldrh r3, [r3, #38] ; 0x26
+ fae: 81eb strh r3, [r5, #14]
+
+ return ERR_NONE;
+}
+ fb0: 2000 movs r0, #0
+ fb2: bd70 pop {r4, r5, r6, pc}
+ fb4: 00000ead .word 0x00000ead
+ fb8: 0000207c .word 0x0000207c
+ fbc: ffffbfff .word 0xffffbfff
+
+00000fc0 <_sercom_i2c_sync_send_address>:
+{
+ fc0: b570 push {r4, r5, r6, lr}
+ fc2: 0005 movs r5, r0
+ void * hw = i2c_dev->hw;
+ fc4: 6904 ldr r4, [r0, #16]
+ tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+ fc6: 6823 ldr r3, [r4, #0]
+ tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos;
+ fc8: 0edb lsrs r3, r3, #27
+ fca: 2601 movs r6, #1
+ fcc: 401e ands r6, r3
+ ASSERT(i2c_dev);
+ fce: 1e43 subs r3, r0, #1
+ fd0: 4198 sbcs r0, r3
+ fd2: b2c0 uxtb r0, r0
+ fd4: 4a8e ldr r2, [pc, #568] ; (1210 <_sercom_i2c_sync_send_address+0x250>)
+ fd6: 498f ldr r1, [pc, #572] ; (1214 <_sercom_i2c_sync_send_address+0x254>)
+ fd8: 4b8f ldr r3, [pc, #572] ; (1218 <_sercom_i2c_sync_send_address+0x258>)
+ fda: 4798 blx r3
+ if (msg->len == 1 && sclsm) {
+ fdc: 686b ldr r3, [r5, #4]
+ fde: 2b01 cmp r3, #1
+ fe0: d04d beq.n 107e <_sercom_i2c_sync_send_address+0xbe>
+ ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+ fe2: 6863 ldr r3, [r4, #4]
+ fe4: 4a8d ldr r2, [pc, #564] ; (121c <_sercom_i2c_sync_send_address+0x25c>)
+ fe6: 4013 ands r3, r2
+ fe8: 6063 str r3, [r4, #4]
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ fea: 69e3 ldr r3, [r4, #28]
+ fec: 075b lsls r3, r3, #29
+ fee: d4fc bmi.n fea <_sercom_i2c_sync_send_address+0x2a>
+ if (msg->addr & I2C_M_TEN) {
+ ff0: 882b ldrh r3, [r5, #0]
+ ff2: 055a lsls r2, r3, #21
+ ff4: d54e bpl.n 1094 <_sercom_i2c_sync_send_address+0xd4>
+ if (msg->flags & I2C_M_RD) {
+ ff6: 886a ldrh r2, [r5, #2]
+ ff8: 07d2 lsls r2, r2, #31
+ ffa: d504 bpl.n 1006 <_sercom_i2c_sync_send_address+0x46>
+ msg->flags |= I2C_M_TEN;
+ ffc: 886a ldrh r2, [r5, #2]
+ ffe: 2180 movs r1, #128 ; 0x80
+ 1000: 00c9 lsls r1, r1, #3
+ 1002: 430a orrs r2, r1
+ 1004: 806a strh r2, [r5, #2]
+ ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN
+ 1006: 005b lsls r3, r3, #1
+ | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS));
+ 1008: 4a85 ldr r2, [pc, #532] ; (1220 <_sercom_i2c_sync_send_address+0x260>)
+ 100a: 401a ands r2, r3
+ 100c: 69e3 ldr r3, [r4, #28]
+ 100e: 075b lsls r3, r3, #29
+ 1010: d4fc bmi.n 100c <_sercom_i2c_sync_send_address+0x4c>
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_reg(const void *const hw)
+{
+ hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+ return ((Sercom *)hw)->I2CM.ADDR.reg;
+ 1012: 6a63 ldr r3, [r4, #36] ; 0x24
+ 1014: 2180 movs r1, #128 ; 0x80
+ 1016: 01c9 lsls r1, r1, #7
+ 1018: 400b ands r3, r1
+ 101a: 4313 orrs r3, r2
+ hri_sercomi2cm_write_ADDR_reg(hw,
+ 101c: 2280 movs r2, #128 ; 0x80
+ 101e: 0212 lsls r2, r2, #8
+ 1020: 4313 orrs r3, r2
+ ((Sercom *)hw)->I2CM.ADDR.reg = data;
+ 1022: 6263 str r3, [r4, #36] ; 0x24
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ 1024: 69e3 ldr r3, [r4, #28]
+ 1026: 075b lsls r3, r3, #29
+ 1028: d4fc bmi.n 1024 <_sercom_i2c_sync_send_address+0x64>
+ void * hw = i2c_dev->hw;
+ 102a: 692e ldr r6, [r5, #16]
+ uint32_t timeout = 65535;
+ 102c: 4a7d ldr r2, [pc, #500] ; (1224 <_sercom_i2c_sync_send_address+0x264>)
+ return ((Sercom *)hw)->I2CM.INTFLAG.reg;
+ 102e: 7e33 ldrb r3, [r6, #24]
+ 1030: b2db uxtb r3, r3
+ *flags = hri_sercomi2cm_read_INTFLAG_reg(hw);
+ 1032: 0018 movs r0, r3
+ if (timeout-- == 0) {
+ 1034: 1e51 subs r1, r2, #1
+ 1036: 2a00 cmp r2, #0
+ 1038: d002 beq.n 1040 <_sercom_i2c_sync_send_address+0x80>
+ 103a: 000a movs r2, r1
+ } while (!(*flags & MB_FLAG) && !(*flags & SB_FLAG));
+ 103c: 079b lsls r3, r3, #30
+ 103e: d0f6 beq.n 102e <_sercom_i2c_sync_send_address+0x6e>
+ tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+ 1040: 6823 ldr r3, [r4, #0]
+ tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos;
+ 1042: 0edb lsrs r3, r3, #27
+ 1044: 2201 movs r2, #1
+ 1046: 401a ands r2, r3
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ 1048: 69e3 ldr r3, [r4, #28]
+ 104a: 075b lsls r3, r3, #29
+ 104c: d4fc bmi.n 1048 <_sercom_i2c_sync_send_address+0x88>
+}
+
+static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw)
+{
+ hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+ return ((Sercom *)hw)->I2CM.STATUS.reg;
+ 104e: 8b63 ldrh r3, [r4, #26]
+ 1050: b29b uxth r3, r3
+ if (flags & MB_FLAG) {
+ 1052: 07c1 lsls r1, r0, #31
+ 1054: d400 bmi.n 1058 <_sercom_i2c_sync_send_address+0x98>
+ 1056: e08f b.n 1178 <_sercom_i2c_sync_send_address+0x1b8>
+ if (status & SERCOM_I2CM_STATUS_ARBLOST) {
+ 1058: 079a lsls r2, r3, #30
+ 105a: d52f bpl.n 10bc <_sercom_i2c_sync_send_address+0xfc>
+ ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB;
+ 105c: 2201 movs r2, #1
+ 105e: 7622 strb r2, [r4, #24]
+ msg->flags |= I2C_M_FAIL;
+ 1060: 886a ldrh r2, [r5, #2]
+ 1062: 2180 movs r1, #128 ; 0x80
+ 1064: 0149 lsls r1, r1, #5
+ 1066: 430a orrs r2, r1
+ 1068: 806a strh r2, [r5, #2]
+ msg->flags &= ~I2C_M_BUSY;
+ 106a: 886a ldrh r2, [r5, #2]
+ 106c: 496e ldr r1, [pc, #440] ; (1228 <_sercom_i2c_sync_send_address+0x268>)
+ 106e: 400a ands r2, r1
+ 1070: 806a strh r2, [r5, #2]
+ if (status & SERCOM_I2CM_STATUS_BUSERR) {
+ 1072: 07db lsls r3, r3, #31
+ 1074: d400 bmi.n 1078 <_sercom_i2c_sync_send_address+0xb8>
+ 1076: e0c6 b.n 1206 <_sercom_i2c_sync_send_address+0x246>
+ return I2C_ERR_BUS;
+ 1078: 2005 movs r0, #5
+ 107a: 4240 negs r0, r0
+ 107c: e0a2 b.n 11c4 <_sercom_i2c_sync_send_address+0x204>
+ if (msg->len == 1 && sclsm) {
+ 107e: 2e00 cmp r6, #0
+ 1080: d0af beq.n fe2 <_sercom_i2c_sync_send_address+0x22>
+ ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+ 1082: 6862 ldr r2, [r4, #4]
+ 1084: 2380 movs r3, #128 ; 0x80
+ 1086: 02db lsls r3, r3, #11
+ 1088: 4313 orrs r3, r2
+ 108a: 6063 str r3, [r4, #4]
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ 108c: 69e3 ldr r3, [r4, #28]
+ 108e: 075b lsls r3, r3, #29
+ 1090: d4fc bmi.n 108c <_sercom_i2c_sync_send_address+0xcc>
+ 1092: e7ad b.n ff0 <_sercom_i2c_sync_send_address+0x30>
+ ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0)
+ 1094: 005b lsls r3, r3, #1
+ 1096: 22ff movs r2, #255 ; 0xff
+ 1098: 4013 ands r3, r2
+ 109a: 886a ldrh r2, [r5, #2]
+ 109c: 2101 movs r1, #1
+ 109e: 400a ands r2, r1
+ 10a0: 431a orrs r2, r3
+ 10a2: 69e3 ldr r3, [r4, #28]
+ 10a4: 075b lsls r3, r3, #29
+ 10a6: d4fc bmi.n 10a2 <_sercom_i2c_sync_send_address+0xe2>
+ return ((Sercom *)hw)->I2CM.ADDR.reg;
+ 10a8: 6a63 ldr r3, [r4, #36] ; 0x24
+ | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS));
+ 10aa: 2180 movs r1, #128 ; 0x80
+ 10ac: 01c9 lsls r1, r1, #7
+ 10ae: 400b ands r3, r1
+ hri_sercomi2cm_write_ADDR_reg(hw,
+ 10b0: 4313 orrs r3, r2
+ ((Sercom *)hw)->I2CM.ADDR.reg = data;
+ 10b2: 6263 str r3, [r4, #36] ; 0x24
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ 10b4: 69e3 ldr r3, [r4, #28]
+ 10b6: 075b lsls r3, r3, #29
+ 10b8: d4fc bmi.n 10b4 <_sercom_i2c_sync_send_address+0xf4>
+ 10ba: e7b6 b.n 102a <_sercom_i2c_sync_send_address+0x6a>
+ if (status & SERCOM_I2CM_STATUS_RXNACK) {
+ 10bc: 075b lsls r3, r3, #29
+ 10be: d41b bmi.n 10f8 <_sercom_i2c_sync_send_address+0x138>
+ if (msg->flags & I2C_M_TEN) {
+ 10c0: 886b ldrh r3, [r5, #2]
+ 10c2: 055b lsls r3, r3, #21
+ 10c4: d534 bpl.n 1130 <_sercom_i2c_sync_send_address+0x170>
+ ((((msg->addr & TEN_ADDR_MASK) >> 8) | TEN_ADDR_FRAME) << 1) | I2C_M_RD
+ 10c6: 882a ldrh r2, [r5, #0]
+ 10c8: 1212 asrs r2, r2, #8
+ 10ca: 0052 lsls r2, r2, #1
+ | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS));
+ 10cc: 2306 movs r3, #6
+ 10ce: 401a ands r2, r3
+ 10d0: 69e3 ldr r3, [r4, #28]
+ 10d2: 075b lsls r3, r3, #29
+ 10d4: d4fc bmi.n 10d0 <_sercom_i2c_sync_send_address+0x110>
+ return ((Sercom *)hw)->I2CM.ADDR.reg;
+ 10d6: 6a63 ldr r3, [r4, #36] ; 0x24
+ 10d8: 2180 movs r1, #128 ; 0x80
+ 10da: 01c9 lsls r1, r1, #7
+ 10dc: 400b ands r3, r1
+ 10de: 4313 orrs r3, r2
+ hri_sercomi2cm_write_ADDR_reg(hw,
+ 10e0: 22f1 movs r2, #241 ; 0xf1
+ 10e2: 4313 orrs r3, r2
+ ((Sercom *)hw)->I2CM.ADDR.reg = data;
+ 10e4: 6263 str r3, [r4, #36] ; 0x24
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ 10e6: 69e3 ldr r3, [r4, #28]
+ 10e8: 075b lsls r3, r3, #29
+ 10ea: d4fc bmi.n 10e6 <_sercom_i2c_sync_send_address+0x126>
+ msg->flags &= ~I2C_M_TEN;
+ 10ec: 886b ldrh r3, [r5, #2]
+ 10ee: 4a4f ldr r2, [pc, #316] ; (122c <_sercom_i2c_sync_send_address+0x26c>)
+ 10f0: 4013 ands r3, r2
+ 10f2: 806b strh r3, [r5, #2]
+ return I2C_OK;
+ 10f4: 2000 movs r0, #0
+ 10f6: e065 b.n 11c4 <_sercom_i2c_sync_send_address+0x204>
+ if (msg->len > 0) {
+ 10f8: 686b ldr r3, [r5, #4]
+ 10fa: 2b00 cmp r3, #0
+ 10fc: dd04 ble.n 1108 <_sercom_i2c_sync_send_address+0x148>
+ msg->flags |= I2C_M_FAIL;
+ 10fe: 886b ldrh r3, [r5, #2]
+ 1100: 2280 movs r2, #128 ; 0x80
+ 1102: 0152 lsls r2, r2, #5
+ 1104: 4313 orrs r3, r2
+ 1106: 806b strh r3, [r5, #2]
+ if (msg->flags & I2C_M_STOP) {
+ 1108: 886b ldrh r3, [r5, #2]
+ 110a: b21b sxth r3, r3
+ 110c: 2b00 cmp r3, #0
+ 110e: db06 blt.n 111e <_sercom_i2c_sync_send_address+0x15e>
+ msg->flags &= ~I2C_M_BUSY;
+ 1110: 886b ldrh r3, [r5, #2]
+ 1112: 4a45 ldr r2, [pc, #276] ; (1228 <_sercom_i2c_sync_send_address+0x268>)
+ 1114: 4013 ands r3, r2
+ 1116: 806b strh r3, [r5, #2]
+ return I2C_NACK;
+ 1118: 2002 movs r0, #2
+ 111a: 4240 negs r0, r0
+ 111c: e052 b.n 11c4 <_sercom_i2c_sync_send_address+0x204>
+ ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask);
+ 111e: 6862 ldr r2, [r4, #4]
+ 1120: 23c0 movs r3, #192 ; 0xc0
+ 1122: 029b lsls r3, r3, #10
+ 1124: 4313 orrs r3, r2
+ 1126: 6063 str r3, [r4, #4]
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ 1128: 69e3 ldr r3, [r4, #28]
+ 112a: 075b lsls r3, r3, #29
+ 112c: d4fc bmi.n 1128 <_sercom_i2c_sync_send_address+0x168>
+ 112e: e7ef b.n 1110 <_sercom_i2c_sync_send_address+0x150>
+ if (msg->len == 0) {
+ 1130: 6868 ldr r0, [r5, #4]
+ 1132: 2800 cmp r0, #0
+ 1134: d111 bne.n 115a <_sercom_i2c_sync_send_address+0x19a>
+ if (msg->flags & I2C_M_STOP) {
+ 1136: 886b ldrh r3, [r5, #2]
+ 1138: b21b sxth r3, r3
+ 113a: 2b00 cmp r3, #0
+ 113c: db04 blt.n 1148 <_sercom_i2c_sync_send_address+0x188>
+ msg->flags &= ~I2C_M_BUSY;
+ 113e: 886b ldrh r3, [r5, #2]
+ 1140: 4a39 ldr r2, [pc, #228] ; (1228 <_sercom_i2c_sync_send_address+0x268>)
+ 1142: 4013 ands r3, r2
+ 1144: 806b strh r3, [r5, #2]
+ 1146: e03d b.n 11c4 <_sercom_i2c_sync_send_address+0x204>
+ ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask);
+ 1148: 6862 ldr r2, [r4, #4]
+ 114a: 23c0 movs r3, #192 ; 0xc0
+ 114c: 029b lsls r3, r3, #10
+ 114e: 4313 orrs r3, r2
+ 1150: 6063 str r3, [r4, #4]
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ 1152: 69e3 ldr r3, [r4, #28]
+ 1154: 075b lsls r3, r3, #29
+ 1156: d4fc bmi.n 1152 <_sercom_i2c_sync_send_address+0x192>
+ 1158: e7f1 b.n 113e <_sercom_i2c_sync_send_address+0x17e>
+ hri_sercomi2cm_write_DATA_reg(hw, *msg->buffer);
+ 115a: 68ab ldr r3, [r5, #8]
+ 115c: 781a ldrb r2, [r3, #0]
+ ((Sercom *)hw)->I2CM.DATA.reg = data;
+ 115e: 2328 movs r3, #40 ; 0x28
+ 1160: 54e2 strb r2, [r4, r3]
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ 1162: 69e3 ldr r3, [r4, #28]
+ 1164: 075b lsls r3, r3, #29
+ 1166: d4fc bmi.n 1162 <_sercom_i2c_sync_send_address+0x1a2>
+ msg->buffer++;
+ 1168: 68ab ldr r3, [r5, #8]
+ 116a: 3301 adds r3, #1
+ 116c: 60ab str r3, [r5, #8]
+ msg->len--;
+ 116e: 686b ldr r3, [r5, #4]
+ 1170: 3b01 subs r3, #1
+ 1172: 606b str r3, [r5, #4]
+ return I2C_OK;
+ 1174: 2000 movs r0, #0
+ 1176: e025 b.n 11c4 <_sercom_i2c_sync_send_address+0x204>
+ } else if (flags & SB_FLAG) {
+ 1178: 0781 lsls r1, r0, #30
+ 117a: d547 bpl.n 120c <_sercom_i2c_sync_send_address+0x24c>
+ if ((msg->len) && !(status & SERCOM_I2CM_STATUS_RXNACK)) {
+ 117c: 6869 ldr r1, [r5, #4]
+ 117e: 2900 cmp r1, #0
+ 1180: d03c beq.n 11fc <_sercom_i2c_sync_send_address+0x23c>
+ 1182: 075b lsls r3, r3, #29
+ 1184: d43a bmi.n 11fc <_sercom_i2c_sync_send_address+0x23c>
+ msg->len--;
+ 1186: 3901 subs r1, #1
+ 1188: 6069 str r1, [r5, #4]
+ if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) {
+ 118a: 2900 cmp r1, #0
+ 118c: d101 bne.n 1192 <_sercom_i2c_sync_send_address+0x1d2>
+ 118e: 2a00 cmp r2, #0
+ 1190: d01b beq.n 11ca <_sercom_i2c_sync_send_address+0x20a>
+ 1192: 2901 cmp r1, #1
+ 1194: d017 beq.n 11c6 <_sercom_i2c_sync_send_address+0x206>
+ if (msg->len == 0) {
+ 1196: 686b ldr r3, [r5, #4]
+ 1198: 2b00 cmp r3, #0
+ 119a: d107 bne.n 11ac <_sercom_i2c_sync_send_address+0x1ec>
+ if (msg->flags & I2C_M_STOP) {
+ 119c: 886b ldrh r3, [r5, #2]
+ 119e: b21b sxth r3, r3
+ 11a0: 2b00 cmp r3, #0
+ 11a2: db1b blt.n 11dc <_sercom_i2c_sync_send_address+0x21c>
+ msg->flags &= ~I2C_M_BUSY;
+ 11a4: 886b ldrh r3, [r5, #2]
+ 11a6: 4a20 ldr r2, [pc, #128] ; (1228 <_sercom_i2c_sync_send_address+0x268>)
+ 11a8: 4013 ands r3, r2
+ 11aa: 806b strh r3, [r5, #2]
+ *msg->buffer++ = hri_sercomi2cm_read_DATA_reg(hw);
+ 11ac: 68aa ldr r2, [r5, #8]
+ 11ae: 1c53 adds r3, r2, #1
+ 11b0: 60ab str r3, [r5, #8]
+ 11b2: 69e3 ldr r3, [r4, #28]
+ 11b4: 075b lsls r3, r3, #29
+ 11b6: d4fc bmi.n 11b2 <_sercom_i2c_sync_send_address+0x1f2>
+ return ((Sercom *)hw)->I2CM.DATA.reg;
+ 11b8: 2328 movs r3, #40 ; 0x28
+ 11ba: 5ce3 ldrb r3, [r4, r3]
+ 11bc: 7013 strb r3, [r2, #0]
+ ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+ 11be: 2302 movs r3, #2
+ 11c0: 7623 strb r3, [r4, #24]
+ return I2C_OK;
+ 11c2: 2000 movs r0, #0
+}
+ 11c4: bd70 pop {r4, r5, r6, pc}
+ if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) {
+ 11c6: 2a00 cmp r2, #0
+ 11c8: d0e5 beq.n 1196 <_sercom_i2c_sync_send_address+0x1d6>
+ ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+ 11ca: 6862 ldr r2, [r4, #4]
+ 11cc: 2380 movs r3, #128 ; 0x80
+ 11ce: 02db lsls r3, r3, #11
+ 11d0: 4313 orrs r3, r2
+ 11d2: 6063 str r3, [r4, #4]
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ 11d4: 69e3 ldr r3, [r4, #28]
+ 11d6: 075b lsls r3, r3, #29
+ 11d8: d4fc bmi.n 11d4 <_sercom_i2c_sync_send_address+0x214>
+ 11da: e7dc b.n 1196 <_sercom_i2c_sync_send_address+0x1d6>
+ ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN;
+ 11dc: 6863 ldr r3, [r4, #4]
+ 11de: 4a12 ldr r2, [pc, #72] ; (1228 <_sercom_i2c_sync_send_address+0x268>)
+ 11e0: 4013 ands r3, r2
+ 11e2: 6063 str r3, [r4, #4]
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ 11e4: 69e3 ldr r3, [r4, #28]
+ 11e6: 075b lsls r3, r3, #29
+ 11e8: d4fc bmi.n 11e4 <_sercom_i2c_sync_send_address+0x224>
+ ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask);
+ 11ea: 6862 ldr r2, [r4, #4]
+ 11ec: 23c0 movs r3, #192 ; 0xc0
+ 11ee: 029b lsls r3, r3, #10
+ 11f0: 4313 orrs r3, r2
+ 11f2: 6063 str r3, [r4, #4]
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ 11f4: 69e3 ldr r3, [r4, #28]
+ 11f6: 075b lsls r3, r3, #29
+ 11f8: d4fc bmi.n 11f4 <_sercom_i2c_sync_send_address+0x234>
+ 11fa: e7d3 b.n 11a4 <_sercom_i2c_sync_send_address+0x1e4>
+ ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+ 11fc: 2302 movs r3, #2
+ 11fe: 7623 strb r3, [r4, #24]
+ return I2C_NACK;
+ 1200: 2002 movs r0, #2
+ 1202: 4240 negs r0, r0
+ 1204: e7de b.n 11c4 <_sercom_i2c_sync_send_address+0x204>
+ return I2C_ERR_BAD_ADDRESS;
+ 1206: 2004 movs r0, #4
+ 1208: 4240 negs r0, r0
+ 120a: e7db b.n 11c4 <_sercom_i2c_sync_send_address+0x204>
+ return I2C_OK;
+ 120c: 2000 movs r0, #0
+ return _sercom_i2c_sync_analyse_flags(hw, flags, msg);
+ 120e: e7d9 b.n 11c4 <_sercom_i2c_sync_send_address+0x204>
+ 1210: 00000594 .word 0x00000594
+ 1214: 000020cc .word 0x000020cc
+ 1218: 00000a69 .word 0x00000a69
+ 121c: fffbffff .word 0xfffbffff
+ 1220: 000007fe .word 0x000007fe
+ 1224: 0000ffff .word 0x0000ffff
+ 1228: fffffeff .word 0xfffffeff
+ 122c: fffffbff .word 0xfffffbff
+
+00001230 <_i2c_m_sync_init>:
+{
+ 1230: b570 push {r4, r5, r6, lr}
+ 1232: 0004 movs r4, r0
+ 1234: 000d movs r5, r1
+ ASSERT(i2c_dev);
+ 1236: 1e43 subs r3, r0, #1
+ 1238: 4198 sbcs r0, r3
+ 123a: b2c0 uxtb r0, r0
+ 123c: 4a04 ldr r2, [pc, #16] ; (1250 <_i2c_m_sync_init+0x20>)
+ 123e: 4905 ldr r1, [pc, #20] ; (1254 <_i2c_m_sync_init+0x24>)
+ 1240: 4b05 ldr r3, [pc, #20] ; (1258 <_i2c_m_sync_init+0x28>)
+ 1242: 4798 blx r3
+ i2c_dev->hw = hw;
+ 1244: 6125 str r5, [r4, #16]
+ return _i2c_m_sync_init_impl(&i2c_dev->service, hw);
+ 1246: 0029 movs r1, r5
+ 1248: 0020 movs r0, r4
+ 124a: 4b04 ldr r3, [pc, #16] ; (125c <_i2c_m_sync_init+0x2c>)
+ 124c: 4798 blx r3
+}
+ 124e: bd70 pop {r4, r5, r6, pc}
+ 1250: 00000507 .word 0x00000507
+ 1254: 000020cc .word 0x000020cc
+ 1258: 00000a69 .word 0x00000a69
+ 125c: 00000ef5 .word 0x00000ef5
+
+00001260 <_i2c_m_sync_enable>:
+{
+ 1260: b570 push {r4, r5, r6, lr}
+ 1262: 0004 movs r4, r0
+ ASSERT(i2c_dev);
+ 1264: 4d19 ldr r5, [pc, #100] ; (12cc <_i2c_m_sync_enable+0x6c>)
+ 1266: 1e43 subs r3, r0, #1
+ 1268: 4198 sbcs r0, r3
+ 126a: b2c0 uxtb r0, r0
+ 126c: 4a18 ldr r2, [pc, #96] ; (12d0 <_i2c_m_sync_enable+0x70>)
+ 126e: 0029 movs r1, r5
+ 1270: 4e18 ldr r6, [pc, #96] ; (12d4 <_i2c_m_sync_enable+0x74>)
+ 1272: 47b0 blx r6
+ return _i2c_m_enable_implementation(i2c_dev->hw);
+ 1274: 6924 ldr r4, [r4, #16]
+ ASSERT(hw);
+ 1276: 0020 movs r0, r4
+ 1278: 1e43 subs r3, r0, #1
+ 127a: 4198 sbcs r0, r3
+ 127c: b2c0 uxtb r0, r0
+ 127e: 4a16 ldr r2, [pc, #88] ; (12d8 <_i2c_m_sync_enable+0x78>)
+ 1280: 0029 movs r1, r5
+ 1282: 47b0 blx r6
+ ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE;
+ 1284: 6823 ldr r3, [r4, #0]
+ 1286: 2202 movs r2, #2
+ 1288: 4313 orrs r3, r2
+ 128a: 6023 str r3, [r4, #0]
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ 128c: 69e3 ldr r3, [r4, #28]
+ 128e: 079b lsls r3, r3, #30
+ 1290: d1fc bne.n 128c <_i2c_m_sync_enable+0x2c>
+ 1292: 2004 movs r0, #4
+ 1294: 4911 ldr r1, [pc, #68] ; (12dc <_i2c_m_sync_enable+0x7c>)
+ 1296: 69e3 ldr r3, [r4, #28]
+ 1298: 075b lsls r3, r3, #29
+ 129a: d4fc bmi.n 1296 <_i2c_m_sync_enable+0x36>
+ return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE_Msk) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos;
+ 129c: 8b62 ldrh r2, [r4, #26]
+ 129e: 0912 lsrs r2, r2, #4
+ 12a0: 2303 movs r3, #3
+ 12a2: 4013 ands r3, r2
+ while (hri_sercomi2cm_read_STATUS_BUSSTATE_bf(hw) != I2C_IDLE) {
+ 12a4: 2b01 cmp r3, #1
+ 12a6: d00b beq.n 12c0 <_i2c_m_sync_enable+0x60>
+ timeout--;
+ 12a8: 3901 subs r1, #1
+ if (timeout <= 0) {
+ 12aa: 2900 cmp r1, #0
+ 12ac: dcf3 bgt.n 1296 <_i2c_m_sync_enable+0x36>
+ if (--timeout_attempt)
+ 12ae: 3801 subs r0, #1
+ 12b0: 2800 cmp r0, #0
+ 12b2: d007 beq.n 12c4 <_i2c_m_sync_enable+0x64>
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+ SERCOM_CRITICAL_SECTION_ENTER();
+ ((Sercom *)hw)->I2CM.STATUS.reg = mask;
+ 12b4: 2310 movs r3, #16
+ 12b6: 8363 strh r3, [r4, #26]
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ 12b8: 69e3 ldr r3, [r4, #28]
+ 12ba: 075b lsls r3, r3, #29
+ 12bc: d4fc bmi.n 12b8 <_i2c_m_sync_enable+0x58>
+ 12be: e7e9 b.n 1294 <_i2c_m_sync_enable+0x34>
+ return ERR_NONE;
+ 12c0: 2000 movs r0, #0
+}
+ 12c2: bd70 pop {r4, r5, r6, pc}
+ return I2C_ERR_BUSY;
+ 12c4: 2006 movs r0, #6
+ 12c6: 4240 negs r0, r0
+ return _i2c_m_enable_implementation(i2c_dev->hw);
+ 12c8: e7fb b.n 12c2 <_i2c_m_sync_enable+0x62>
+ 12ca: 46c0 nop ; (mov r8, r8)
+ 12cc: 000020cc .word 0x000020cc
+ 12d0: 00000524 .word 0x00000524
+ 12d4: 00000a69 .word 0x00000a69
+ 12d8: 000005f4 .word 0x000005f4
+ 12dc: 0000ffff .word 0x0000ffff
+
+000012e0 <_i2c_m_sync_transfer>:
+{
+ 12e0: b5f8 push {r3, r4, r5, r6, r7, lr}
+ 12e2: 0005 movs r5, r0
+ 12e4: 000e movs r6, r1
+ void * hw = i2c_dev->hw;
+ 12e6: 6904 ldr r4, [r0, #16]
+ ASSERT(i2c_dev);
+ 12e8: 1e43 subs r3, r0, #1
+ 12ea: 4198 sbcs r0, r3
+ 12ec: b2c0 uxtb r0, r0
+ 12ee: 4a93 ldr r2, [pc, #588] ; (153c <_i2c_m_sync_transfer+0x25c>)
+ 12f0: 4993 ldr r1, [pc, #588] ; (1540 <_i2c_m_sync_transfer+0x260>)
+ 12f2: 4f94 ldr r7, [pc, #592] ; (1544 <_i2c_m_sync_transfer+0x264>)
+ 12f4: 47b8 blx r7
+ ASSERT(i2c_dev->hw);
+ 12f6: 6928 ldr r0, [r5, #16]
+ 12f8: 1e43 subs r3, r0, #1
+ 12fa: 4198 sbcs r0, r3
+ 12fc: b2c0 uxtb r0, r0
+ 12fe: 22b8 movs r2, #184 ; 0xb8
+ 1300: 00d2 lsls r2, r2, #3
+ 1302: 498f ldr r1, [pc, #572] ; (1540 <_i2c_m_sync_transfer+0x260>)
+ 1304: 47b8 blx r7
+ ASSERT(msg);
+ 1306: 0030 movs r0, r6
+ 1308: 1e43 subs r3, r0, #1
+ 130a: 4198 sbcs r0, r3
+ 130c: b2c0 uxtb r0, r0
+ 130e: 4a8e ldr r2, [pc, #568] ; (1548 <_i2c_m_sync_transfer+0x268>)
+ 1310: 498b ldr r1, [pc, #556] ; (1540 <_i2c_m_sync_transfer+0x260>)
+ 1312: 47b8 blx r7
+ if (i2c_dev->service.msg.flags & I2C_M_BUSY) {
+ 1314: 886b ldrh r3, [r5, #2]
+ 1316: 05db lsls r3, r3, #23
+ 1318: d500 bpl.n 131c <_i2c_m_sync_transfer+0x3c>
+ 131a: e10b b.n 1534 <_i2c_m_sync_transfer+0x254>
+ msg->flags |= I2C_M_BUSY;
+ 131c: 8872 ldrh r2, [r6, #2]
+ 131e: 2380 movs r3, #128 ; 0x80
+ 1320: 005b lsls r3, r3, #1
+ 1322: 469c mov ip, r3
+ 1324: 431a orrs r2, r3
+ 1326: 8072 strh r2, [r6, #2]
+ i2c_dev->service.msg = *msg;
+ 1328: 002a movs r2, r5
+ 132a: 0031 movs r1, r6
+ 132c: c989 ldmia r1!, {r0, r3, r7}
+ 132e: c289 stmia r2!, {r0, r3, r7}
+ ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN;
+ 1330: 6862 ldr r2, [r4, #4]
+ 1332: 4663 mov r3, ip
+ 1334: 4313 orrs r3, r2
+ 1336: 6063 str r3, [r4, #4]
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ 1338: 69e3 ldr r3, [r4, #28]
+ 133a: 075b lsls r3, r3, #29
+ 133c: d4fc bmi.n 1338 <_i2c_m_sync_transfer+0x58>
+ ret = _sercom_i2c_sync_send_address(i2c_dev);
+ 133e: 0028 movs r0, r5
+ 1340: 4b82 ldr r3, [pc, #520] ; (154c <_i2c_m_sync_transfer+0x26c>)
+ 1342: 4798 blx r3
+ if (ret) {
+ 1344: 2800 cmp r0, #0
+ 1346: d100 bne.n 134a <_i2c_m_sync_transfer+0x6a>
+ 1348: e09d b.n 1486 <_i2c_m_sync_transfer+0x1a6>
+ i2c_dev->service.msg.flags &= ~I2C_M_BUSY;
+ 134a: 886b ldrh r3, [r5, #2]
+ 134c: 4a80 ldr r2, [pc, #512] ; (1550 <_i2c_m_sync_transfer+0x270>)
+ 134e: 4013 ands r3, r2
+ 1350: 806b strh r3, [r5, #2]
+}
+ 1352: bdf8 pop {r3, r4, r5, r6, r7, pc}
+ return I2C_ERR_BUS;
+ 1354: 2005 movs r0, #5
+ 1356: 4240 negs r0, r0
+ 1358: e0a6 b.n 14a8 <_i2c_m_sync_transfer+0x1c8>
+ if (msg->flags & I2C_M_STOP) {
+ 135a: 8873 ldrh r3, [r6, #2]
+ 135c: b21b sxth r3, r3
+ 135e: 2b00 cmp r3, #0
+ 1360: db04 blt.n 136c <_i2c_m_sync_transfer+0x8c>
+ i2c_dev->service.msg.flags &= ~I2C_M_BUSY;
+ 1362: 886b ldrh r3, [r5, #2]
+ 1364: 4a7a ldr r2, [pc, #488] ; (1550 <_i2c_m_sync_transfer+0x270>)
+ 1366: 4013 ands r3, r2
+ 1368: 806b strh r3, [r5, #2]
+ return ret;
+ 136a: e7f2 b.n 1352 <_i2c_m_sync_transfer+0x72>
+ ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask);
+ 136c: 6862 ldr r2, [r4, #4]
+ 136e: 23c0 movs r3, #192 ; 0xc0
+ 1370: 029b lsls r3, r3, #10
+ 1372: 4313 orrs r3, r2
+ 1374: 6063 str r3, [r4, #4]
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ 1376: 69e3 ldr r3, [r4, #28]
+ 1378: 075b lsls r3, r3, #29
+ 137a: d4fc bmi.n 1376 <_i2c_m_sync_transfer+0x96>
+ 137c: e7f1 b.n 1362 <_i2c_m_sync_transfer+0x82>
+ if (status & SERCOM_I2CM_STATUS_RXNACK) {
+ 137e: 0753 lsls r3, r2, #29
+ 1380: d41b bmi.n 13ba <_i2c_m_sync_transfer+0xda>
+ if (msg->flags & I2C_M_TEN) {
+ 1382: 886b ldrh r3, [r5, #2]
+ 1384: 055b lsls r3, r3, #21
+ 1386: d534 bpl.n 13f2 <_i2c_m_sync_transfer+0x112>
+ ((((msg->addr & TEN_ADDR_MASK) >> 8) | TEN_ADDR_FRAME) << 1) | I2C_M_RD
+ 1388: 882a ldrh r2, [r5, #0]
+ 138a: 1212 asrs r2, r2, #8
+ 138c: 0052 lsls r2, r2, #1
+ | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS));
+ 138e: 2306 movs r3, #6
+ 1390: 401a ands r2, r3
+ 1392: 69e3 ldr r3, [r4, #28]
+ 1394: 075b lsls r3, r3, #29
+ 1396: d4fc bmi.n 1392 <_i2c_m_sync_transfer+0xb2>
+ return ((Sercom *)hw)->I2CM.ADDR.reg;
+ 1398: 6a63 ldr r3, [r4, #36] ; 0x24
+ 139a: 2180 movs r1, #128 ; 0x80
+ 139c: 01c9 lsls r1, r1, #7
+ 139e: 400b ands r3, r1
+ 13a0: 4313 orrs r3, r2
+ hri_sercomi2cm_write_ADDR_reg(hw,
+ 13a2: 22f1 movs r2, #241 ; 0xf1
+ 13a4: 4313 orrs r3, r2
+ ((Sercom *)hw)->I2CM.ADDR.reg = data;
+ 13a6: 6263 str r3, [r4, #36] ; 0x24
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ 13a8: 69e3 ldr r3, [r4, #28]
+ 13aa: 075b lsls r3, r3, #29
+ 13ac: d4fc bmi.n 13a8 <_i2c_m_sync_transfer+0xc8>
+ msg->flags &= ~I2C_M_TEN;
+ 13ae: 886b ldrh r3, [r5, #2]
+ 13b0: 4a68 ldr r2, [pc, #416] ; (1554 <_i2c_m_sync_transfer+0x274>)
+ 13b2: 4013 ands r3, r2
+ 13b4: 806b strh r3, [r5, #2]
+ return I2C_OK;
+ 13b6: 2000 movs r0, #0
+ 13b8: e065 b.n 1486 <_i2c_m_sync_transfer+0x1a6>
+ if (msg->len > 0) {
+ 13ba: 686b ldr r3, [r5, #4]
+ 13bc: 2b00 cmp r3, #0
+ 13be: dd04 ble.n 13ca <_i2c_m_sync_transfer+0xea>
+ msg->flags |= I2C_M_FAIL;
+ 13c0: 886b ldrh r3, [r5, #2]
+ 13c2: 2280 movs r2, #128 ; 0x80
+ 13c4: 0152 lsls r2, r2, #5
+ 13c6: 4313 orrs r3, r2
+ 13c8: 806b strh r3, [r5, #2]
+ if (msg->flags & I2C_M_STOP) {
+ 13ca: 886b ldrh r3, [r5, #2]
+ 13cc: b21b sxth r3, r3
+ 13ce: 2b00 cmp r3, #0
+ 13d0: db06 blt.n 13e0 <_i2c_m_sync_transfer+0x100>
+ msg->flags &= ~I2C_M_BUSY;
+ 13d2: 886b ldrh r3, [r5, #2]
+ 13d4: 4a5e ldr r2, [pc, #376] ; (1550 <_i2c_m_sync_transfer+0x270>)
+ 13d6: 4013 ands r3, r2
+ 13d8: 806b strh r3, [r5, #2]
+ return I2C_NACK;
+ 13da: 2002 movs r0, #2
+ 13dc: 4240 negs r0, r0
+ 13de: e052 b.n 1486 <_i2c_m_sync_transfer+0x1a6>
+ ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask);
+ 13e0: 6862 ldr r2, [r4, #4]
+ 13e2: 23c0 movs r3, #192 ; 0xc0
+ 13e4: 029b lsls r3, r3, #10
+ 13e6: 4313 orrs r3, r2
+ 13e8: 6063 str r3, [r4, #4]
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ 13ea: 69e3 ldr r3, [r4, #28]
+ 13ec: 075b lsls r3, r3, #29
+ 13ee: d4fc bmi.n 13ea <_i2c_m_sync_transfer+0x10a>
+ 13f0: e7ef b.n 13d2 <_i2c_m_sync_transfer+0xf2>
+ if (msg->len == 0) {
+ 13f2: 6868 ldr r0, [r5, #4]
+ 13f4: 2800 cmp r0, #0
+ 13f6: d111 bne.n 141c <_i2c_m_sync_transfer+0x13c>
+ if (msg->flags & I2C_M_STOP) {
+ 13f8: 886b ldrh r3, [r5, #2]
+ 13fa: b21b sxth r3, r3
+ 13fc: 2b00 cmp r3, #0
+ 13fe: db04 blt.n 140a <_i2c_m_sync_transfer+0x12a>
+ msg->flags &= ~I2C_M_BUSY;
+ 1400: 886b ldrh r3, [r5, #2]
+ 1402: 4a53 ldr r2, [pc, #332] ; (1550 <_i2c_m_sync_transfer+0x270>)
+ 1404: 4013 ands r3, r2
+ 1406: 806b strh r3, [r5, #2]
+ 1408: e03d b.n 1486 <_i2c_m_sync_transfer+0x1a6>
+ ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask);
+ 140a: 6862 ldr r2, [r4, #4]
+ 140c: 23c0 movs r3, #192 ; 0xc0
+ 140e: 029b lsls r3, r3, #10
+ 1410: 4313 orrs r3, r2
+ 1412: 6063 str r3, [r4, #4]
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ 1414: 69e3 ldr r3, [r4, #28]
+ 1416: 075b lsls r3, r3, #29
+ 1418: d4fc bmi.n 1414 <_i2c_m_sync_transfer+0x134>
+ 141a: e7f1 b.n 1400 <_i2c_m_sync_transfer+0x120>
+ hri_sercomi2cm_write_DATA_reg(hw, *msg->buffer);
+ 141c: 68ab ldr r3, [r5, #8]
+ 141e: 781a ldrb r2, [r3, #0]
+ ((Sercom *)hw)->I2CM.DATA.reg = data;
+ 1420: 2328 movs r3, #40 ; 0x28
+ 1422: 54e2 strb r2, [r4, r3]
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ 1424: 69e3 ldr r3, [r4, #28]
+ 1426: 075b lsls r3, r3, #29
+ 1428: d4fc bmi.n 1424 <_i2c_m_sync_transfer+0x144>
+ msg->buffer++;
+ 142a: 68ab ldr r3, [r5, #8]
+ 142c: 3301 adds r3, #1
+ 142e: 60ab str r3, [r5, #8]
+ msg->len--;
+ 1430: 686b ldr r3, [r5, #4]
+ 1432: 3b01 subs r3, #1
+ 1434: 606b str r3, [r5, #4]
+ return I2C_OK;
+ 1436: 2000 movs r0, #0
+ 1438: e025 b.n 1486 <_i2c_m_sync_transfer+0x1a6>
+ } else if (flags & SB_FLAG) {
+ 143a: 07bb lsls r3, r7, #30
+ 143c: d578 bpl.n 1530 <_i2c_m_sync_transfer+0x250>
+ if ((msg->len) && !(status & SERCOM_I2CM_STATUS_RXNACK)) {
+ 143e: 686b ldr r3, [r5, #4]
+ 1440: 2b00 cmp r3, #0
+ 1442: d06d beq.n 1520 <_i2c_m_sync_transfer+0x240>
+ 1444: 0752 lsls r2, r2, #29
+ 1446: d46b bmi.n 1520 <_i2c_m_sync_transfer+0x240>
+ msg->len--;
+ 1448: 3b01 subs r3, #1
+ 144a: 606b str r3, [r5, #4]
+ if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) {
+ 144c: 2b00 cmp r3, #0
+ 144e: d101 bne.n 1454 <_i2c_m_sync_transfer+0x174>
+ 1450: 2900 cmp r1, #0
+ 1452: d04c beq.n 14ee <_i2c_m_sync_transfer+0x20e>
+ 1454: 2b01 cmp r3, #1
+ 1456: d048 beq.n 14ea <_i2c_m_sync_transfer+0x20a>
+ if (msg->len == 0) {
+ 1458: 686b ldr r3, [r5, #4]
+ 145a: 2b00 cmp r3, #0
+ 145c: d107 bne.n 146e <_i2c_m_sync_transfer+0x18e>
+ if (msg->flags & I2C_M_STOP) {
+ 145e: 886b ldrh r3, [r5, #2]
+ 1460: b21b sxth r3, r3
+ 1462: 2b00 cmp r3, #0
+ 1464: db4c blt.n 1500 <_i2c_m_sync_transfer+0x220>
+ msg->flags &= ~I2C_M_BUSY;
+ 1466: 886b ldrh r3, [r5, #2]
+ 1468: 4a39 ldr r2, [pc, #228] ; (1550 <_i2c_m_sync_transfer+0x270>)
+ 146a: 4013 ands r3, r2
+ 146c: 806b strh r3, [r5, #2]
+ *msg->buffer++ = hri_sercomi2cm_read_DATA_reg(hw);
+ 146e: 68aa ldr r2, [r5, #8]
+ 1470: 1c53 adds r3, r2, #1
+ 1472: 60ab str r3, [r5, #8]
+ 1474: 69e3 ldr r3, [r4, #28]
+ 1476: 075b lsls r3, r3, #29
+ 1478: d4fc bmi.n 1474 <_i2c_m_sync_transfer+0x194>
+ return ((Sercom *)hw)->I2CM.DATA.reg;
+ 147a: 2328 movs r3, #40 ; 0x28
+ 147c: 5ce3 ldrb r3, [r4, r3]
+ 147e: 7013 strb r3, [r2, #0]
+ ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+ 1480: 2302 movs r3, #2
+ 1482: 7623 strb r3, [r4, #24]
+ return I2C_OK;
+ 1484: 2000 movs r0, #0
+ while (i2c_dev->service.msg.flags & I2C_M_BUSY) {
+ 1486: 886b ldrh r3, [r5, #2]
+ 1488: 05db lsls r3, r3, #23
+ 148a: d400 bmi.n 148e <_i2c_m_sync_transfer+0x1ae>
+ 148c: e761 b.n 1352 <_i2c_m_sync_transfer+0x72>
+ void * hw = i2c_dev->hw;
+ 148e: 6928 ldr r0, [r5, #16]
+ uint32_t timeout = 65535;
+ 1490: 4a31 ldr r2, [pc, #196] ; (1558 <_i2c_m_sync_transfer+0x278>)
+ return ((Sercom *)hw)->I2CM.INTFLAG.reg;
+ 1492: 7e03 ldrb r3, [r0, #24]
+ 1494: b2db uxtb r3, r3
+ *flags = hri_sercomi2cm_read_INTFLAG_reg(hw);
+ 1496: 001f movs r7, r3
+ if (timeout-- == 0) {
+ 1498: 1e51 subs r1, r2, #1
+ 149a: 2a00 cmp r2, #0
+ 149c: d100 bne.n 14a0 <_i2c_m_sync_transfer+0x1c0>
+ 149e: e759 b.n 1354 <_i2c_m_sync_transfer+0x74>
+ 14a0: 000a movs r2, r1
+ } while (!(*flags & MB_FLAG) && !(*flags & SB_FLAG));
+ 14a2: 079b lsls r3, r3, #30
+ 14a4: d0f5 beq.n 1492 <_i2c_m_sync_transfer+0x1b2>
+ return I2C_OK;
+ 14a6: 2000 movs r0, #0
+ if (ret) {
+ 14a8: 2800 cmp r0, #0
+ 14aa: d000 beq.n 14ae <_i2c_m_sync_transfer+0x1ce>
+ 14ac: e755 b.n 135a <_i2c_m_sync_transfer+0x7a>
+ tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+ 14ae: 6823 ldr r3, [r4, #0]
+ tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos;
+ 14b0: 0edb lsrs r3, r3, #27
+ 14b2: 2101 movs r1, #1
+ 14b4: 4019 ands r1, r3
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ 14b6: 69e3 ldr r3, [r4, #28]
+ 14b8: 075b lsls r3, r3, #29
+ 14ba: d4fc bmi.n 14b6 <_i2c_m_sync_transfer+0x1d6>
+ return ((Sercom *)hw)->I2CM.STATUS.reg;
+ 14bc: 8b62 ldrh r2, [r4, #26]
+ 14be: b292 uxth r2, r2
+ if (flags & MB_FLAG) {
+ 14c0: 07fb lsls r3, r7, #31
+ 14c2: d5ba bpl.n 143a <_i2c_m_sync_transfer+0x15a>
+ if (status & SERCOM_I2CM_STATUS_ARBLOST) {
+ 14c4: 0793 lsls r3, r2, #30
+ 14c6: d400 bmi.n 14ca <_i2c_m_sync_transfer+0x1ea>
+ 14c8: e759 b.n 137e <_i2c_m_sync_transfer+0x9e>
+ ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB;
+ 14ca: 2301 movs r3, #1
+ 14cc: 7623 strb r3, [r4, #24]
+ msg->flags |= I2C_M_FAIL;
+ 14ce: 886b ldrh r3, [r5, #2]
+ 14d0: 2180 movs r1, #128 ; 0x80
+ 14d2: 0149 lsls r1, r1, #5
+ 14d4: 430b orrs r3, r1
+ 14d6: 806b strh r3, [r5, #2]
+ msg->flags &= ~I2C_M_BUSY;
+ 14d8: 886b ldrh r3, [r5, #2]
+ 14da: 491d ldr r1, [pc, #116] ; (1550 <_i2c_m_sync_transfer+0x270>)
+ 14dc: 400b ands r3, r1
+ 14de: 806b strh r3, [r5, #2]
+ if (status & SERCOM_I2CM_STATUS_BUSERR) {
+ 14e0: 07d3 lsls r3, r2, #31
+ 14e2: d522 bpl.n 152a <_i2c_m_sync_transfer+0x24a>
+ return I2C_ERR_BUS;
+ 14e4: 2005 movs r0, #5
+ 14e6: 4240 negs r0, r0
+ 14e8: e7cd b.n 1486 <_i2c_m_sync_transfer+0x1a6>
+ if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) {
+ 14ea: 2900 cmp r1, #0
+ 14ec: d0b4 beq.n 1458 <_i2c_m_sync_transfer+0x178>
+ ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+ 14ee: 6862 ldr r2, [r4, #4]
+ 14f0: 2380 movs r3, #128 ; 0x80
+ 14f2: 02db lsls r3, r3, #11
+ 14f4: 4313 orrs r3, r2
+ 14f6: 6063 str r3, [r4, #4]
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ 14f8: 69e3 ldr r3, [r4, #28]
+ 14fa: 075b lsls r3, r3, #29
+ 14fc: d4fc bmi.n 14f8 <_i2c_m_sync_transfer+0x218>
+ 14fe: e7ab b.n 1458 <_i2c_m_sync_transfer+0x178>
+ ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN;
+ 1500: 6863 ldr r3, [r4, #4]
+ 1502: 4a13 ldr r2, [pc, #76] ; (1550 <_i2c_m_sync_transfer+0x270>)
+ 1504: 4013 ands r3, r2
+ 1506: 6063 str r3, [r4, #4]
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ 1508: 69e3 ldr r3, [r4, #28]
+ 150a: 075b lsls r3, r3, #29
+ 150c: d4fc bmi.n 1508 <_i2c_m_sync_transfer+0x228>
+ ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask);
+ 150e: 6862 ldr r2, [r4, #4]
+ 1510: 23c0 movs r3, #192 ; 0xc0
+ 1512: 029b lsls r3, r3, #10
+ 1514: 4313 orrs r3, r2
+ 1516: 6063 str r3, [r4, #4]
+ while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+ 1518: 69e3 ldr r3, [r4, #28]
+ 151a: 075b lsls r3, r3, #29
+ 151c: d4fc bmi.n 1518 <_i2c_m_sync_transfer+0x238>
+ 151e: e7a2 b.n 1466 <_i2c_m_sync_transfer+0x186>
+ ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+ 1520: 2302 movs r3, #2
+ 1522: 7623 strb r3, [r4, #24]
+ return I2C_NACK;
+ 1524: 2002 movs r0, #2
+ 1526: 4240 negs r0, r0
+ 1528: e7ad b.n 1486 <_i2c_m_sync_transfer+0x1a6>
+ return I2C_ERR_BAD_ADDRESS;
+ 152a: 2004 movs r0, #4
+ 152c: 4240 negs r0, r0
+ 152e: e7aa b.n 1486 <_i2c_m_sync_transfer+0x1a6>
+ return I2C_OK;
+ 1530: 2000 movs r0, #0
+ 1532: e7a8 b.n 1486 <_i2c_m_sync_transfer+0x1a6>
+ return I2C_ERR_BUSY;
+ 1534: 2006 movs r0, #6
+ 1536: 4240 negs r0, r0
+ 1538: e70b b.n 1352 <_i2c_m_sync_transfer+0x72>
+ 153a: 46c0 nop ; (mov r8, r8)
+ 153c: 000005bf .word 0x000005bf
+ 1540: 000020cc .word 0x000020cc
+ 1544: 00000a69 .word 0x00000a69
+ 1548: 000005c1 .word 0x000005c1
+ 154c: 00000fc1 .word 0x00000fc1
+ 1550: fffffeff .word 0xfffffeff
+ 1554: fffffbff .word 0xfffffbff
+ 1558: 0000ffff .word 0x0000ffff
+
+0000155c <_system_time_init>:
+ * \brief Initialize system time module
+ */
+void _system_time_init(void *const hw)
+{
+ (void)hw;
+ SysTick->LOAD = (0xFFFFFF << SysTick_LOAD_RELOAD_Pos);
+ 155c: 4b02 ldr r3, [pc, #8] ; (1568 <_system_time_init+0xc>)
+ 155e: 4a03 ldr r2, [pc, #12] ; (156c <_system_time_init+0x10>)
+ 1560: 605a str r2, [r3, #4]
+ SysTick->CTRL = (1 << SysTick_CTRL_ENABLE_Pos) | (CONF_SYSTICK_TICKINT << SysTick_CTRL_TICKINT_Pos)
+ 1562: 2205 movs r2, #5
+ 1564: 601a str r2, [r3, #0]
+ | (1 << SysTick_CTRL_CLKSOURCE_Pos);
+}
+ 1566: 4770 bx lr
+ 1568: e000e010 .word 0xe000e010
+ 156c: 00ffffff .word 0x00ffffff
+
+00001570 <_delay_init>:
+/**
+ * \brief Initialize delay functionality
+ */
+void _delay_init(void *const hw)
+{
+ 1570: b510 push {r4, lr}
+ _system_time_init(hw);
+ 1572: 4b01 ldr r3, [pc, #4] ; (1578 <_delay_init+0x8>)
+ 1574: 4798 blx r3
+}
+ 1576: bd10 pop {r4, pc}
+ 1578: 0000155d .word 0x0000155d
+
+0000157c <tcc_pwm_interrupt_handler>:
+ * \internal TC interrupt handler for PWM
+ *
+ * \param[in] instance TC instance number
+ */
+static void tcc_pwm_interrupt_handler(struct _pwm_device *device)
+{
+ 157c: b570 push {r4, r5, r6, lr}
+ 157e: 0005 movs r5, r0
+ void *const hw = device->hw;
+ 1580: 6904 ldr r4, [r0, #16]
+ ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3;
+}
+
+static inline bool hri_tcc_get_interrupt_OVF_bit(const void *const hw)
+{
+ return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos;
+ 1582: 6ae3 ldr r3, [r4, #44] ; 0x2c
+
+ if (hri_tcc_get_interrupt_OVF_bit(hw)) {
+ 1584: 07db lsls r3, r3, #31
+ 1586: d505 bpl.n 1594 <tcc_pwm_interrupt_handler+0x18>
+}
+
+static inline void hri_tcc_clear_interrupt_OVF_bit(const void *const hw)
+{
+ ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF;
+ 1588: 2301 movs r3, #1
+ 158a: 62e3 str r3, [r4, #44] ; 0x2c
+ hri_tcc_clear_interrupt_OVF_bit(hw);
+ if (NULL != device->callback.pwm_period_cb) {
+ 158c: 6803 ldr r3, [r0, #0]
+ 158e: 2b00 cmp r3, #0
+ 1590: d000 beq.n 1594 <tcc_pwm_interrupt_handler+0x18>
+ device->callback.pwm_period_cb(device);
+ 1592: 4798 blx r3
+ ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR;
+}
+
+static inline bool hri_tcc_get_INTEN_ERR_bit(const void *const hw)
+{
+ return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_ERR) >> TCC_INTENSET_ERR_Pos;
+ 1594: 6aa3 ldr r3, [r4, #40] ; 0x28
+ }
+ }
+ if (hri_tcc_get_INTEN_ERR_bit(hw)) {
+ 1596: 071b lsls r3, r3, #28
+ 1598: d506 bpl.n 15a8 <tcc_pwm_interrupt_handler+0x2c>
+ ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR;
+ 159a: 2308 movs r3, #8
+ 159c: 62e3 str r3, [r4, #44] ; 0x2c
+ hri_tcc_clear_interrupt_ERR_bit(hw);
+ if (NULL != device->callback.pwm_error_cb) {
+ 159e: 686b ldr r3, [r5, #4]
+ 15a0: 2b00 cmp r3, #0
+ 15a2: d001 beq.n 15a8 <tcc_pwm_interrupt_handler+0x2c>
+ device->callback.pwm_error_cb(device);
+ 15a4: 0028 movs r0, r5
+ 15a6: 4798 blx r3
+ }
+ }
+}
+ 15a8: bd70 pop {r4, r5, r6, pc}
+ ...
+
+000015ac <TCC0_Handler>:
+
+/**
+ * \brief TCC interrupt handler
+ */
+void TCC0_Handler(void)
+{
+ 15ac: b510 push {r4, lr}
+ tcc_pwm_interrupt_handler(_tcc0_dev);
+ 15ae: 4b02 ldr r3, [pc, #8] ; (15b8 <TCC0_Handler+0xc>)
+ 15b0: 6818 ldr r0, [r3, #0]
+ 15b2: 4b02 ldr r3, [pc, #8] ; (15bc <TCC0_Handler+0x10>)
+ 15b4: 4798 blx r3
+}
+ 15b6: bd10 pop {r4, pc}
+ 15b8: 20000068 .word 0x20000068
+ 15bc: 0000157d .word 0x0000157d
+
+000015c0 <_tc_start_pwm>:
+/**
+ * \brief Start PWM
+ */
+void _tc_start_pwm(struct _pwm_device *const device)
+{
+ hri_tc_set_CTRLA_ENABLE_bit(device->hw);
+ 15c0: 6902 ldr r2, [r0, #16]
+}
+
+static inline void hri_tc_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+ TC_CRITICAL_SECTION_ENTER();
+ ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE;
+ 15c2: 6813 ldr r3, [r2, #0]
+ 15c4: 2102 movs r1, #2
+ 15c6: 430b orrs r3, r1
+ 15c8: 6013 str r3, [r2, #0]
+ while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+ 15ca: 6913 ldr r3, [r2, #16]
+ 15cc: 079b lsls r3, r3, #30
+ 15ce: d1fc bne.n 15ca <_tc_start_pwm+0xa>
+}
+ 15d0: 4770 bx lr
+
+000015d2 <_tc_stop_pwm>:
+/**
+ * \brief Stop PWM
+ */
+void _tc_stop_pwm(struct _pwm_device *const device)
+{
+ hri_tc_clear_CTRLA_ENABLE_bit(device->hw);
+ 15d2: 6902 ldr r2, [r0, #16]
+}
+
+static inline void hri_tc_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+ TC_CRITICAL_SECTION_ENTER();
+ ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE;
+ 15d4: 6813 ldr r3, [r2, #0]
+ 15d6: 2102 movs r1, #2
+ 15d8: 438b bics r3, r1
+ 15da: 6013 str r3, [r2, #0]
+ while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+ 15dc: 6913 ldr r3, [r2, #16]
+ 15de: 079b lsls r3, r3, #30
+ 15e0: d1fc bne.n 15dc <_tc_stop_pwm+0xa>
+}
+ 15e2: 4770 bx lr
+
+000015e4 <_tc_is_pwm_enabled>:
+/**
+ * \brief Check if PWM is running
+ */
+bool _tc_is_pwm_enabled(const struct _pwm_device *const device)
+{
+ return hri_tc_get_CTRLA_ENABLE_bit(device->hw);
+ 15e4: 6902 ldr r2, [r0, #16]
+ 15e6: 6913 ldr r3, [r2, #16]
+ 15e8: 079b lsls r3, r3, #30
+ 15ea: d1fc bne.n 15e6 <_tc_is_pwm_enabled+0x2>
+ tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+ 15ec: 6813 ldr r3, [r2, #0]
+ tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos;
+ 15ee: 085b lsrs r3, r3, #1
+ return (bool)tmp;
+ 15f0: 2001 movs r0, #1
+ 15f2: 4018 ands r0, r3
+}
+ 15f4: 4770 bx lr
+
+000015f6 <tc_pwm_interrupt_handler>:
+ * \internal TC interrupt handler for PWM
+ *
+ * \param[in] instance TC instance number
+ */
+static void tc_pwm_interrupt_handler(struct _pwm_device *device)
+{
+ 15f6: b570 push {r4, r5, r6, lr}
+ 15f8: 0005 movs r5, r0
+ void *const hw = device->hw;
+ 15fa: 6904 ldr r4, [r0, #16]
+ return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos;
+ 15fc: 7aa3 ldrb r3, [r4, #10]
+
+ if (hri_tc_get_interrupt_OVF_bit(hw)) {
+ 15fe: 07db lsls r3, r3, #31
+ 1600: d505 bpl.n 160e <tc_pwm_interrupt_handler+0x18>
+ ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF;
+ 1602: 2301 movs r3, #1
+ 1604: 72a3 strb r3, [r4, #10]
+ hri_tc_clear_interrupt_OVF_bit(hw);
+ if (NULL != device->callback.pwm_period_cb) {
+ 1606: 6803 ldr r3, [r0, #0]
+ 1608: 2b00 cmp r3, #0
+ 160a: d000 beq.n 160e <tc_pwm_interrupt_handler+0x18>
+ device->callback.pwm_period_cb(device);
+ 160c: 4798 blx r3
+ return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_ERR) >> TC_INTENSET_ERR_Pos;
+ 160e: 7a63 ldrb r3, [r4, #9]
+ }
+ }
+ if (hri_tc_get_INTEN_ERR_bit(hw)) {
+ 1610: 079b lsls r3, r3, #30
+ 1612: d506 bpl.n 1622 <tc_pwm_interrupt_handler+0x2c>
+ ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR;
+ 1614: 2302 movs r3, #2
+ 1616: 72a3 strb r3, [r4, #10]
+ hri_tc_clear_interrupt_ERR_bit(hw);
+ if (NULL != device->callback.pwm_error_cb) {
+ 1618: 686b ldr r3, [r5, #4]
+ 161a: 2b00 cmp r3, #0
+ 161c: d001 beq.n 1622 <tc_pwm_interrupt_handler+0x2c>
+ device->callback.pwm_error_cb(device);
+ 161e: 0028 movs r0, r5
+ 1620: 4798 blx r3
+ }
+ }
+}
+ 1622: bd70 pop {r4, r5, r6, pc}
+
+00001624 <_tc_init_irq_param>:
+/**
+ * \brief Init irq param with the given tc hardware instance
+ */
+static void _tc_init_irq_param(const void *const hw, void *dev)
+{
+ if (hw == TC3) {
+ 1624: 4b03 ldr r3, [pc, #12] ; (1634 <_tc_init_irq_param+0x10>)
+ 1626: 4298 cmp r0, r3
+ 1628: d000 beq.n 162c <_tc_init_irq_param+0x8>
+ _tc3_dev = (struct _pwm_device *)dev;
+ }
+}
+ 162a: 4770 bx lr
+ _tc3_dev = (struct _pwm_device *)dev;
+ 162c: 4b02 ldr r3, [pc, #8] ; (1638 <_tc_init_irq_param+0x14>)
+ 162e: 6019 str r1, [r3, #0]
+}
+ 1630: e7fb b.n 162a <_tc_init_irq_param+0x6>
+ 1632: 46c0 nop ; (mov r8, r8)
+ 1634: 42002c00 .word 0x42002c00
+ 1638: 2000006c .word 0x2000006c
+
+0000163c <get_tc_index>:
+{
+ 163c: b510 push {r4, lr}
+ *
+ * \param[in] hw The pointer to hardware instance
+ */
+static inline uint8_t _get_hardware_offset(const void *const hw)
+{
+ return (((uint32_t)hw - (uint32_t)TC0) >> 10);
+ 163e: 4b0e ldr r3, [pc, #56] ; (1678 <get_tc_index+0x3c>)
+ 1640: 469c mov ip, r3
+ 1642: 4460 add r0, ip
+ 1644: 0a80 lsrs r0, r0, #10
+ 1646: b2c3 uxtb r3, r0
+ for (i = 0; i < ARRAY_SIZE(_tcs); i++) {
+ 1648: 2000 movs r0, #0
+ 164a: 2800 cmp r0, #0
+ 164c: d008 beq.n 1660 <get_tc_index+0x24>
+ ASSERT(false);
+ 164e: 22b0 movs r2, #176 ; 0xb0
+ 1650: 0052 lsls r2, r2, #1
+ 1652: 490a ldr r1, [pc, #40] ; (167c <get_tc_index+0x40>)
+ 1654: 2000 movs r0, #0
+ 1656: 4b0a ldr r3, [pc, #40] ; (1680 <get_tc_index+0x44>)
+ 1658: 4798 blx r3
+ return -1;
+ 165a: 2001 movs r0, #1
+ 165c: 4240 negs r0, r0
+}
+ 165e: bd10 pop {r4, pc}
+ if (_tcs[i].number == index) {
+ 1660: 0082 lsls r2, r0, #2
+ 1662: 1812 adds r2, r2, r0
+ 1664: 0091 lsls r1, r2, #2
+ 1666: 4a07 ldr r2, [pc, #28] ; (1684 <get_tc_index+0x48>)
+ 1668: 5c8a ldrb r2, [r1, r2]
+ 166a: 429a cmp r2, r3
+ 166c: d002 beq.n 1674 <get_tc_index+0x38>
+ for (i = 0; i < ARRAY_SIZE(_tcs); i++) {
+ 166e: 3001 adds r0, #1
+ 1670: b2c0 uxtb r0, r0
+ 1672: e7ea b.n 164a <get_tc_index+0xe>
+ return i;
+ 1674: b240 sxtb r0, r0
+ 1676: e7f2 b.n 165e <get_tc_index+0x22>
+ 1678: bdffe000 .word 0xbdffe000
+ 167c: 000020e8 .word 0x000020e8
+ 1680: 00000a69 .word 0x00000a69
+ 1684: 20000000 .word 0x20000000
+
+00001688 <_tc_pwm_init>:
+{
+ 1688: b570 push {r4, r5, r6, lr}
+ 168a: 0006 movs r6, r0
+ 168c: 000c movs r4, r1
+ int8_t i = get_tc_index(hw);
+ 168e: 0008 movs r0, r1
+ 1690: 4b53 ldr r3, [pc, #332] ; (17e0 <_tc_pwm_init+0x158>)
+ 1692: 4798 blx r3
+ 1694: 0005 movs r5, r0
+ device->hw = hw;
+ 1696: 6134 str r4, [r6, #16]
+ return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg;
+ 1698: 6923 ldr r3, [r4, #16]
+ if (!hri_tc_is_syncing(hw, TC_SYNCBUSY_SWRST)) {
+ 169a: 07db lsls r3, r3, #31
+ 169c: d414 bmi.n 16c8 <_tc_pwm_init+0x40>
+ while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+ 169e: 6923 ldr r3, [r4, #16]
+ 16a0: 079b lsls r3, r3, #30
+ 16a2: d1fc bne.n 169e <_tc_pwm_init+0x16>
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+ uint32_t tmp;
+ hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+ tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+ 16a4: 6823 ldr r3, [r4, #0]
+ if (hri_tc_get_CTRLA_reg(hw, TC_CTRLA_ENABLE)) {
+ 16a6: 079b lsls r3, r3, #30
+ 16a8: d509 bpl.n 16be <_tc_pwm_init+0x36>
+ ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE;
+ 16aa: 6823 ldr r3, [r4, #0]
+ 16ac: 2202 movs r2, #2
+ 16ae: 4393 bics r3, r2
+ 16b0: 6023 str r3, [r4, #0]
+ while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+ 16b2: 6923 ldr r3, [r4, #16]
+ 16b4: 079b lsls r3, r3, #30
+ 16b6: d1fc bne.n 16b2 <_tc_pwm_init+0x2a>
+ 16b8: 6923 ldr r3, [r4, #16]
+ 16ba: 079b lsls r3, r3, #30
+ 16bc: d4fc bmi.n 16b8 <_tc_pwm_init+0x30>
+}
+
+static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+ TC_CRITICAL_SECTION_ENTER();
+ ((Tc *)hw)->COUNT16.CTRLA.reg = data;
+ 16be: 2301 movs r3, #1
+ 16c0: 6023 str r3, [r4, #0]
+ while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+ 16c2: 6923 ldr r3, [r4, #16]
+ 16c4: 079b lsls r3, r3, #30
+ 16c6: d1fc bne.n 16c2 <_tc_pwm_init+0x3a>
+ 16c8: 6923 ldr r3, [r4, #16]
+ 16ca: 07db lsls r3, r3, #31
+ 16cc: d4fc bmi.n 16c8 <_tc_pwm_init+0x40>
+ hri_tc_write_CTRLA_reg(hw, _tcs[i].ctrl_a);
+ 16ce: 00ab lsls r3, r5, #2
+ 16d0: 195b adds r3, r3, r5
+ 16d2: 009a lsls r2, r3, #2
+ 16d4: 4b43 ldr r3, [pc, #268] ; (17e4 <_tc_pwm_init+0x15c>)
+ 16d6: 189b adds r3, r3, r2
+ 16d8: 685b ldr r3, [r3, #4]
+ ((Tc *)hw)->COUNT16.CTRLA.reg = data;
+ 16da: 6023 str r3, [r4, #0]
+ while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+ 16dc: 6923 ldr r3, [r4, #16]
+ 16de: 079b lsls r3, r3, #30
+ 16e0: d1fc bne.n 16dc <_tc_pwm_init+0x54>
+ hri_tc_write_DBGCTRL_reg(hw, _tcs[i].dbg_ctrl);
+ 16e2: 00aa lsls r2, r5, #2
+ 16e4: 1952 adds r2, r2, r5
+ 16e6: 0091 lsls r1, r2, #2
+ 16e8: 4b3e ldr r3, [pc, #248] ; (17e4 <_tc_pwm_init+0x15c>)
+ 16ea: 185b adds r3, r3, r1
+ 16ec: 7a9a ldrb r2, [r3, #10]
+}
+
+static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data)
+{
+ TC_CRITICAL_SECTION_ENTER();
+ ((Tc *)hw)->COUNT16.DBGCTRL.reg = data;
+ 16ee: 73e2 strb r2, [r4, #15]
+ hri_tc_write_EVCTRL_reg(hw, _tcs[i].event_ctrl);
+ 16f0: 891a ldrh r2, [r3, #8]
+ ((Tc *)hw)->COUNT16.EVCTRL.reg = data;
+ 16f2: 80e2 strh r2, [r4, #6]
+ ((Tc *)hw)->COUNT16.WAVE.reg = data;
+ 16f4: 2203 movs r2, #3
+ 16f6: 7322 strb r2, [r4, #12]
+ if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) {
+ 16f8: 685a ldr r2, [r3, #4]
+ 16fa: 230c movs r3, #12
+ 16fc: 4013 ands r3, r2
+ 16fe: 2b08 cmp r3, #8
+ 1700: d054 beq.n 17ac <_tc_pwm_init+0x124>
+ } else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT16) {
+ 1702: 2b00 cmp r3, #0
+ 1704: d166 bne.n 17d4 <_tc_pwm_init+0x14c>
+ hri_tccount16_write_CC_reg(hw, 0, (uint16_t)_tcs[i].cc0);
+ 1706: 00ab lsls r3, r5, #2
+ 1708: 195b adds r3, r3, r5
+ 170a: 009a lsls r2, r3, #2
+ 170c: 4b35 ldr r3, [pc, #212] ; (17e4 <_tc_pwm_init+0x15c>)
+ 170e: 189b adds r3, r3, r2
+ 1710: 899b ldrh r3, [r3, #12]
+}
+
+static inline void hri_tccount16_write_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data)
+{
+ TC_CRITICAL_SECTION_ENTER();
+ ((Tc *)hw)->COUNT16.CC[index].reg = data;
+ 1712: 83a3 strh r3, [r4, #28]
+ while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+ 1714: 6923 ldr r3, [r4, #16]
+ 1716: 22c0 movs r2, #192 ; 0xc0
+ 1718: 421a tst r2, r3
+ 171a: d1fb bne.n 1714 <_tc_pwm_init+0x8c>
+ hri_tccount16_write_CC_reg(hw, 1, (uint16_t)_tcs[i].cc1);
+ 171c: 00ab lsls r3, r5, #2
+ 171e: 195b adds r3, r3, r5
+ 1720: 009a lsls r2, r3, #2
+ 1722: 4b30 ldr r3, [pc, #192] ; (17e4 <_tc_pwm_init+0x15c>)
+ 1724: 189b adds r3, r3, r2
+ 1726: 8a1b ldrh r3, [r3, #16]
+ ((Tc *)hw)->COUNT16.CC[index].reg = data;
+ 1728: 83e3 strh r3, [r4, #30]
+ while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+ 172a: 6923 ldr r3, [r4, #16]
+ 172c: 22c0 movs r2, #192 ; 0xc0
+ 172e: 421a tst r2, r3
+ 1730: d1fb bne.n 172a <_tc_pwm_init+0xa2>
+ _tc_init_irq_param(hw, (void *)device);
+ 1732: 0031 movs r1, r6
+ 1734: 0020 movs r0, r4
+ 1736: 4b2c ldr r3, [pc, #176] ; (17e8 <_tc_pwm_init+0x160>)
+ 1738: 4798 blx r3
+ NVIC_DisableIRQ(_tcs[i].irq);
+ 173a: 00ab lsls r3, r5, #2
+ 173c: 195b adds r3, r3, r5
+ 173e: 009a lsls r2, r3, #2
+ 1740: 4b28 ldr r3, [pc, #160] ; (17e4 <_tc_pwm_init+0x15c>)
+ 1742: 189b adds r3, r3, r2
+ 1744: 785b ldrb r3, [r3, #1]
+ 1746: b25b sxtb r3, r3
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ 1748: 2b00 cmp r3, #0
+ 174a: db0b blt.n 1764 <_tc_pwm_init+0xdc>
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ 174c: 221f movs r2, #31
+ 174e: 4013 ands r3, r2
+ 1750: 3a1e subs r2, #30
+ 1752: 409a lsls r2, r3
+ 1754: 0013 movs r3, r2
+ 1756: 2280 movs r2, #128 ; 0x80
+ 1758: 4924 ldr r1, [pc, #144] ; (17ec <_tc_pwm_init+0x164>)
+ 175a: 508b str r3, [r1, r2]
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+ 175c: f3bf 8f4f dsb sy
+ __ASM volatile ("isb 0xF":::"memory");
+ 1760: f3bf 8f6f isb sy
+ NVIC_ClearPendingIRQ(_tcs[i].irq);
+ 1764: 00ab lsls r3, r5, #2
+ 1766: 195b adds r3, r3, r5
+ 1768: 009a lsls r2, r3, #2
+ 176a: 4b1e ldr r3, [pc, #120] ; (17e4 <_tc_pwm_init+0x15c>)
+ 176c: 189b adds r3, r3, r2
+ 176e: 785b ldrb r3, [r3, #1]
+ 1770: b25b sxtb r3, r3
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ 1772: 2b00 cmp r3, #0
+ 1774: db08 blt.n 1788 <_tc_pwm_init+0x100>
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ 1776: 221f movs r2, #31
+ 1778: 4013 ands r3, r2
+ 177a: 3a1e subs r2, #30
+ 177c: 409a lsls r2, r3
+ 177e: 0013 movs r3, r2
+ 1780: 22c0 movs r2, #192 ; 0xc0
+ 1782: 0052 lsls r2, r2, #1
+ 1784: 4919 ldr r1, [pc, #100] ; (17ec <_tc_pwm_init+0x164>)
+ 1786: 508b str r3, [r1, r2]
+ NVIC_EnableIRQ(_tcs[i].irq);
+ 1788: 00ab lsls r3, r5, #2
+ 178a: 195d adds r5, r3, r5
+ 178c: 00aa lsls r2, r5, #2
+ 178e: 4b15 ldr r3, [pc, #84] ; (17e4 <_tc_pwm_init+0x15c>)
+ 1790: 189b adds r3, r3, r2
+ 1792: 785b ldrb r3, [r3, #1]
+ 1794: b25b sxtb r3, r3
+ if ((int32_t)(IRQn) >= 0)
+ 1796: 2b00 cmp r3, #0
+ 1798: db1f blt.n 17da <_tc_pwm_init+0x152>
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ 179a: 221f movs r2, #31
+ 179c: 4013 ands r3, r2
+ 179e: 3a1e subs r2, #30
+ 17a0: 409a lsls r2, r3
+ 17a2: 0013 movs r3, r2
+ 17a4: 4a11 ldr r2, [pc, #68] ; (17ec <_tc_pwm_init+0x164>)
+ 17a6: 6013 str r3, [r2, #0]
+ return 0;
+ 17a8: 2000 movs r0, #0
+}
+ 17aa: bd70 pop {r4, r5, r6, pc}
+ hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0);
+ 17ac: 4b0d ldr r3, [pc, #52] ; (17e4 <_tc_pwm_init+0x15c>)
+ 17ae: 185b adds r3, r3, r1
+ 17b0: 68db ldr r3, [r3, #12]
+}
+
+static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data)
+{
+ TC_CRITICAL_SECTION_ENTER();
+ ((Tc *)hw)->COUNT32.CC[index].reg = data;
+ 17b2: 61e3 str r3, [r4, #28]
+ while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+ 17b4: 6923 ldr r3, [r4, #16]
+ 17b6: 22c0 movs r2, #192 ; 0xc0
+ 17b8: 421a tst r2, r3
+ 17ba: d1fb bne.n 17b4 <_tc_pwm_init+0x12c>
+ hri_tccount32_write_CC_reg(hw, 1, _tcs[i].cc1);
+ 17bc: 00ab lsls r3, r5, #2
+ 17be: 195b adds r3, r3, r5
+ 17c0: 009a lsls r2, r3, #2
+ 17c2: 4b08 ldr r3, [pc, #32] ; (17e4 <_tc_pwm_init+0x15c>)
+ 17c4: 189b adds r3, r3, r2
+ 17c6: 691b ldr r3, [r3, #16]
+ ((Tc *)hw)->COUNT32.CC[index].reg = data;
+ 17c8: 6223 str r3, [r4, #32]
+ while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+ 17ca: 6923 ldr r3, [r4, #16]
+ 17cc: 22c0 movs r2, #192 ; 0xc0
+ 17ce: 421a tst r2, r3
+ 17d0: d1fb bne.n 17ca <_tc_pwm_init+0x142>
+ 17d2: e7ae b.n 1732 <_tc_pwm_init+0xaa>
+ return -1;
+ 17d4: 2001 movs r0, #1
+ 17d6: 4240 negs r0, r0
+ 17d8: e7e7 b.n 17aa <_tc_pwm_init+0x122>
+ return 0;
+ 17da: 2000 movs r0, #0
+ 17dc: e7e5 b.n 17aa <_tc_pwm_init+0x122>
+ 17de: 46c0 nop ; (mov r8, r8)
+ 17e0: 0000163d .word 0x0000163d
+ 17e4: 20000000 .word 0x20000000
+ 17e8: 00001625 .word 0x00001625
+ 17ec: e000e100 .word 0xe000e100
+
+000017f0 <_tc_set_pwm_param>:
+{
+ 17f0: b570 push {r4, r5, r6, lr}
+ 17f2: 000e movs r6, r1
+ 17f4: 0015 movs r5, r2
+ void *const hw = device->hw;
+ 17f6: 6904 ldr r4, [r0, #16]
+ int8_t i = get_tc_index(hw);
+ 17f8: 0020 movs r0, r4
+ 17fa: 4b1b ldr r3, [pc, #108] ; (1868 <_tc_set_pwm_param+0x78>)
+ 17fc: 4798 blx r3
+ _tcs[i].cc0 = period;
+ 17fe: 0082 lsls r2, r0, #2
+ 1800: 1812 adds r2, r2, r0
+ 1802: 0091 lsls r1, r2, #2
+ 1804: 4b19 ldr r3, [pc, #100] ; (186c <_tc_set_pwm_param+0x7c>)
+ 1806: 185b adds r3, r3, r1
+ 1808: 60de str r6, [r3, #12]
+ _tcs[i].cc1 = duty_cycle;
+ 180a: 611d str r5, [r3, #16]
+ if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) {
+ 180c: 685a ldr r2, [r3, #4]
+ 180e: 230c movs r3, #12
+ 1810: 4013 ands r3, r2
+ 1812: 2b08 cmp r3, #8
+ 1814: d016 beq.n 1844 <_tc_set_pwm_param+0x54>
+ hri_tccount16_write_CC_reg(hw, 0, _tcs[i].cc0);
+ 1816: 0083 lsls r3, r0, #2
+ 1818: 181b adds r3, r3, r0
+ 181a: 009a lsls r2, r3, #2
+ 181c: 4b13 ldr r3, [pc, #76] ; (186c <_tc_set_pwm_param+0x7c>)
+ 181e: 189b adds r3, r3, r2
+ 1820: 899b ldrh r3, [r3, #12]
+ ((Tc *)hw)->COUNT16.CC[index].reg = data;
+ 1822: 83a3 strh r3, [r4, #28]
+ while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+ 1824: 6923 ldr r3, [r4, #16]
+ 1826: 22c0 movs r2, #192 ; 0xc0
+ 1828: 421a tst r2, r3
+ 182a: d1fb bne.n 1824 <_tc_set_pwm_param+0x34>
+ hri_tccount16_write_CC_reg(hw, 1, _tcs[i].cc1);
+ 182c: 0083 lsls r3, r0, #2
+ 182e: 1818 adds r0, r3, r0
+ 1830: 0082 lsls r2, r0, #2
+ 1832: 4b0e ldr r3, [pc, #56] ; (186c <_tc_set_pwm_param+0x7c>)
+ 1834: 189b adds r3, r3, r2
+ 1836: 8a1b ldrh r3, [r3, #16]
+ ((Tc *)hw)->COUNT16.CC[index].reg = data;
+ 1838: 83e3 strh r3, [r4, #30]
+ while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+ 183a: 6923 ldr r3, [r4, #16]
+ 183c: 22c0 movs r2, #192 ; 0xc0
+ 183e: 421a tst r2, r3
+ 1840: d1fb bne.n 183a <_tc_set_pwm_param+0x4a>
+}
+ 1842: bd70 pop {r4, r5, r6, pc}
+ ((Tc *)hw)->COUNT32.CC[index].reg = data;
+ 1844: 61e6 str r6, [r4, #28]
+ while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+ 1846: 6923 ldr r3, [r4, #16]
+ 1848: 22c0 movs r2, #192 ; 0xc0
+ 184a: 421a tst r2, r3
+ 184c: d1fb bne.n 1846 <_tc_set_pwm_param+0x56>
+ hri_tccount32_write_CC_reg(hw, 1, _tcs[i].cc1);
+ 184e: 0083 lsls r3, r0, #2
+ 1850: 1818 adds r0, r3, r0
+ 1852: 0082 lsls r2, r0, #2
+ 1854: 4b05 ldr r3, [pc, #20] ; (186c <_tc_set_pwm_param+0x7c>)
+ 1856: 189b adds r3, r3, r2
+ 1858: 691b ldr r3, [r3, #16]
+ ((Tc *)hw)->COUNT32.CC[index].reg = data;
+ 185a: 6223 str r3, [r4, #32]
+ while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+ 185c: 6923 ldr r3, [r4, #16]
+ 185e: 22c0 movs r2, #192 ; 0xc0
+ 1860: 421a tst r2, r3
+ 1862: d1fb bne.n 185c <_tc_set_pwm_param+0x6c>
+ 1864: e7ed b.n 1842 <_tc_set_pwm_param+0x52>
+ 1866: 46c0 nop ; (mov r8, r8)
+ 1868: 0000163d .word 0x0000163d
+ 186c: 20000000 .word 0x20000000
+
+00001870 <_tc_pwm_get_period>:
+{
+ 1870: b510 push {r4, lr}
+ void *const hw = device->hw;
+ 1872: 6904 ldr r4, [r0, #16]
+ int8_t i = get_tc_index(hw);
+ 1874: 0020 movs r0, r4
+ 1876: 4b0c ldr r3, [pc, #48] ; (18a8 <_tc_pwm_get_period+0x38>)
+ 1878: 4798 blx r3
+ if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) {
+ 187a: 0083 lsls r3, r0, #2
+ 187c: 1818 adds r0, r3, r0
+ 187e: 0082 lsls r2, r0, #2
+ 1880: 4b0a ldr r3, [pc, #40] ; (18ac <_tc_pwm_get_period+0x3c>)
+ 1882: 189b adds r3, r3, r2
+ 1884: 685a ldr r2, [r3, #4]
+ 1886: 230c movs r3, #12
+ 1888: 4013 ands r3, r2
+ 188a: 2b08 cmp r3, #8
+ 188c: d006 beq.n 189c <_tc_pwm_get_period+0x2c>
+ 188e: 6923 ldr r3, [r4, #16]
+ 1890: 22c0 movs r2, #192 ; 0xc0
+ 1892: 421a tst r2, r3
+ 1894: d1fb bne.n 188e <_tc_pwm_get_period+0x1e>
+ return ((Tc *)hw)->COUNT16.CC[index].reg;
+ 1896: 8ba0 ldrh r0, [r4, #28]
+ 1898: b280 uxth r0, r0
+}
+ 189a: bd10 pop {r4, pc}
+ while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+ 189c: 6923 ldr r3, [r4, #16]
+ 189e: 22c0 movs r2, #192 ; 0xc0
+ 18a0: 421a tst r2, r3
+ 18a2: d1fb bne.n 189c <_tc_pwm_get_period+0x2c>
+}
+
+static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_reg(const void *const hw, uint8_t index)
+{
+ hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+ return ((Tc *)hw)->COUNT32.CC[index].reg;
+ 18a4: 69e0 ldr r0, [r4, #28]
+ return (pwm_period_t)(hri_tccount32_read_CC_reg(hw, 0));
+ 18a6: e7f8 b.n 189a <_tc_pwm_get_period+0x2a>
+ 18a8: 0000163d .word 0x0000163d
+ 18ac: 20000000 .word 0x20000000
+
+000018b0 <_tc_pwm_get_duty>:
+{
+ 18b0: b510 push {r4, lr}
+ void *const hw = device->hw;
+ 18b2: 6904 ldr r4, [r0, #16]
+ int8_t i = get_tc_index(hw);
+ 18b4: 0020 movs r0, r4
+ 18b6: 4b14 ldr r3, [pc, #80] ; (1908 <_tc_pwm_get_duty+0x58>)
+ 18b8: 4798 blx r3
+ if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) {
+ 18ba: 0083 lsls r3, r0, #2
+ 18bc: 1818 adds r0, r3, r0
+ 18be: 0082 lsls r2, r0, #2
+ 18c0: 4b12 ldr r3, [pc, #72] ; (190c <_tc_pwm_get_duty+0x5c>)
+ 18c2: 189b adds r3, r3, r2
+ 18c4: 685a ldr r2, [r3, #4]
+ 18c6: 230c movs r3, #12
+ 18c8: 4013 ands r3, r2
+ 18ca: 2b08 cmp r3, #8
+ 18cc: d011 beq.n 18f2 <_tc_pwm_get_duty+0x42>
+ while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+ 18ce: 6923 ldr r3, [r4, #16]
+ 18d0: 22c0 movs r2, #192 ; 0xc0
+ 18d2: 421a tst r2, r3
+ 18d4: d1fb bne.n 18ce <_tc_pwm_get_duty+0x1e>
+ return ((Tc *)hw)->COUNT16.CC[index].reg;
+ 18d6: 8ba1 ldrh r1, [r4, #28]
+ 18d8: b289 uxth r1, r1
+ while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+ 18da: 6923 ldr r3, [r4, #16]
+ 18dc: 22c0 movs r2, #192 ; 0xc0
+ 18de: 421a tst r2, r3
+ 18e0: d1fb bne.n 18da <_tc_pwm_get_duty+0x2a>
+ return ((Tc *)hw)->COUNT16.CC[index].reg;
+ 18e2: 8be3 ldrh r3, [r4, #30]
+ 18e4: b29b uxth r3, r3
+ return ((duty_cycle * 1000) / per);
+ 18e6: 20fa movs r0, #250 ; 0xfa
+ 18e8: 0080 lsls r0, r0, #2
+ 18ea: 4358 muls r0, r3
+ 18ec: 4b08 ldr r3, [pc, #32] ; (1910 <_tc_pwm_get_duty+0x60>)
+ 18ee: 4798 blx r3
+}
+ 18f0: bd10 pop {r4, pc}
+ while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+ 18f2: 6923 ldr r3, [r4, #16]
+ 18f4: 22c0 movs r2, #192 ; 0xc0
+ 18f6: 421a tst r2, r3
+ 18f8: d1fb bne.n 18f2 <_tc_pwm_get_duty+0x42>
+ return ((Tc *)hw)->COUNT32.CC[index].reg;
+ 18fa: 69e1 ldr r1, [r4, #28]
+ while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+ 18fc: 6923 ldr r3, [r4, #16]
+ 18fe: 22c0 movs r2, #192 ; 0xc0
+ 1900: 421a tst r2, r3
+ 1902: d1fb bne.n 18fc <_tc_pwm_get_duty+0x4c>
+ return ((Tc *)hw)->COUNT32.CC[index].reg;
+ 1904: 6a23 ldr r3, [r4, #32]
+ 1906: e7ee b.n 18e6 <_tc_pwm_get_duty+0x36>
+ 1908: 0000163d .word 0x0000163d
+ 190c: 20000000 .word 0x20000000
+ 1910: 00001d45 .word 0x00001d45
+
+00001914 <_tc_pwm_deinit>:
+{
+ 1914: b570 push {r4, r5, r6, lr}
+ void *const hw = device->hw;
+ 1916: 6904 ldr r4, [r0, #16]
+ int8_t i = get_tc_index(hw);
+ 1918: 0020 movs r0, r4
+ 191a: 4b16 ldr r3, [pc, #88] ; (1974 <_tc_pwm_deinit+0x60>)
+ 191c: 4798 blx r3
+ 191e: 0005 movs r5, r0
+ ASSERT(ARRAY_SIZE(_tcs));
+ 1920: 22c2 movs r2, #194 ; 0xc2
+ 1922: 4915 ldr r1, [pc, #84] ; (1978 <_tc_pwm_deinit+0x64>)
+ 1924: 2001 movs r0, #1
+ 1926: 4b15 ldr r3, [pc, #84] ; (197c <_tc_pwm_deinit+0x68>)
+ 1928: 4798 blx r3
+ NVIC_DisableIRQ(_tcs[i].irq);
+ 192a: 00a8 lsls r0, r5, #2
+ 192c: 1940 adds r0, r0, r5
+ 192e: 0082 lsls r2, r0, #2
+ 1930: 4b13 ldr r3, [pc, #76] ; (1980 <_tc_pwm_deinit+0x6c>)
+ 1932: 189b adds r3, r3, r2
+ 1934: 785b ldrb r3, [r3, #1]
+ 1936: b25b sxtb r3, r3
+ if ((int32_t)(IRQn) >= 0)
+ 1938: 2b00 cmp r3, #0
+ 193a: db0b blt.n 1954 <_tc_pwm_deinit+0x40>
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ 193c: 221f movs r2, #31
+ 193e: 4013 ands r3, r2
+ 1940: 3a1e subs r2, #30
+ 1942: 409a lsls r2, r3
+ 1944: 0013 movs r3, r2
+ 1946: 2280 movs r2, #128 ; 0x80
+ 1948: 490e ldr r1, [pc, #56] ; (1984 <_tc_pwm_deinit+0x70>)
+ 194a: 508b str r3, [r1, r2]
+ __ASM volatile ("dsb 0xF":::"memory");
+ 194c: f3bf 8f4f dsb sy
+ __ASM volatile ("isb 0xF":::"memory");
+ 1950: f3bf 8f6f isb sy
+ ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE;
+ 1954: 6823 ldr r3, [r4, #0]
+ 1956: 2202 movs r2, #2
+ 1958: 4393 bics r3, r2
+ 195a: 6023 str r3, [r4, #0]
+ while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+ 195c: 6923 ldr r3, [r4, #16]
+ 195e: 079b lsls r3, r3, #30
+ 1960: d1fc bne.n 195c <_tc_pwm_deinit+0x48>
+ ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_SWRST;
+ 1962: 6823 ldr r3, [r4, #0]
+ 1964: 2201 movs r2, #1
+ 1966: 4313 orrs r3, r2
+ 1968: 6023 str r3, [r4, #0]
+ while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+ 196a: 6923 ldr r3, [r4, #16]
+ 196c: 07db lsls r3, r3, #31
+ 196e: d4fc bmi.n 196a <_tc_pwm_deinit+0x56>
+}
+ 1970: bd70 pop {r4, r5, r6, pc}
+ 1972: 46c0 nop ; (mov r8, r8)
+ 1974: 0000163d .word 0x0000163d
+ 1978: 000020e8 .word 0x000020e8
+ 197c: 00000a69 .word 0x00000a69
+ 1980: 20000000 .word 0x20000000
+ 1984: e000e100 .word 0xe000e100
+
+00001988 <_tc_pwm_set_irq_state>:
+{
+ 1988: b570 push {r4, r5, r6, lr}
+ 198a: 0004 movs r4, r0
+ 198c: 000e movs r6, r1
+ 198e: 0015 movs r5, r2
+ ASSERT(device);
+ 1990: 1e43 subs r3, r0, #1
+ 1992: 4198 sbcs r0, r3
+ 1994: b2c0 uxtb r0, r0
+ 1996: 2218 movs r2, #24
+ 1998: 32ff adds r2, #255 ; 0xff
+ 199a: 490d ldr r1, [pc, #52] ; (19d0 <_tc_pwm_set_irq_state+0x48>)
+ 199c: 4b0d ldr r3, [pc, #52] ; (19d4 <_tc_pwm_set_irq_state+0x4c>)
+ 199e: 4798 blx r3
+ if (PWM_DEVICE_PERIOD_CB == type) {
+ 19a0: 2e00 cmp r6, #0
+ 19a2: d108 bne.n 19b6 <_tc_pwm_set_irq_state+0x2e>
+ hri_tc_write_INTEN_OVF_bit(device->hw, disable);
+ 19a4: 6923 ldr r3, [r4, #16]
+ if (value == 0x0) {
+ 19a6: 2d00 cmp r5, #0
+ 19a8: d102 bne.n 19b0 <_tc_pwm_set_irq_state+0x28>
+ ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF;
+ 19aa: 2201 movs r2, #1
+ 19ac: 721a strb r2, [r3, #8]
+ 19ae: e004 b.n 19ba <_tc_pwm_set_irq_state+0x32>
+ ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF;
+ 19b0: 2201 movs r2, #1
+ 19b2: 725a strb r2, [r3, #9]
+ 19b4: e001 b.n 19ba <_tc_pwm_set_irq_state+0x32>
+ } else if (PWM_DEVICE_ERROR_CB == type) {
+ 19b6: 2e01 cmp r6, #1
+ 19b8: d000 beq.n 19bc <_tc_pwm_set_irq_state+0x34>
+}
+ 19ba: bd70 pop {r4, r5, r6, pc}
+ hri_tc_write_INTEN_ERR_bit(device->hw, disable);
+ 19bc: 6923 ldr r3, [r4, #16]
+ if (value == 0x0) {
+ 19be: 2d00 cmp r5, #0
+ 19c0: d002 beq.n 19c8 <_tc_pwm_set_irq_state+0x40>
+ ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR;
+ 19c2: 2202 movs r2, #2
+ 19c4: 725a strb r2, [r3, #9]
+}
+ 19c6: e7f8 b.n 19ba <_tc_pwm_set_irq_state+0x32>
+ ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR;
+ 19c8: 2202 movs r2, #2
+ 19ca: 721a strb r2, [r3, #8]
+ 19cc: e7f5 b.n 19ba <_tc_pwm_set_irq_state+0x32>
+ 19ce: 46c0 nop ; (mov r8, r8)
+ 19d0: 000020e8 .word 0x000020e8
+ 19d4: 00000a69 .word 0x00000a69
+
+000019d8 <_tc_get_pwm>:
+ return &_tc_pwm_functions;
+ 19d8: 4801 ldr r0, [pc, #4] ; (19e0 <_tc_get_pwm+0x8>)
+}
+ 19da: 3014 adds r0, #20
+ 19dc: 4770 bx lr
+ 19de: 46c0 nop ; (mov r8, r8)
+ 19e0: 20000000 .word 0x20000000
+
+000019e4 <TC3_Handler>:
+{
+ 19e4: b510 push {r4, lr}
+ tc_pwm_interrupt_handler(_tc3_dev);
+ 19e6: 4b02 ldr r3, [pc, #8] ; (19f0 <TC3_Handler+0xc>)
+ 19e8: 6818 ldr r0, [r3, #0]
+ 19ea: 4b02 ldr r3, [pc, #8] ; (19f4 <TC3_Handler+0x10>)
+ 19ec: 4798 blx r3
+}
+ 19ee: bd10 pop {r4, pc}
+ 19f0: 2000006c .word 0x2000006c
+ 19f4: 000015f7 .word 0x000015f7
+
+000019f8 <main>:
+#include <atmel_start.h>
+#include "watch-library/watch.h"
+
+int main(void)
+{
+ 19f8: b530 push {r4, r5, lr}
+ 19fa: b08b sub sp, #44 ; 0x2c
+ atmel_start_init();
+ 19fc: 4b23 ldr r3, [pc, #140] ; (1a8c <main+0x94>)
+ 19fe: 4798 blx r3
+
+ Watch watch;
+ struct calendar_date_time date_time;
+ date_time.date.year = 2021;
+ 1a00: ac02 add r4, sp, #8
+ 1a02: 4b23 ldr r3, [pc, #140] ; (1a90 <main+0x98>)
+ 1a04: 80e3 strh r3, [r4, #6]
+ date_time.date.month = 4;
+ 1a06: 2304 movs r3, #4
+ 1a08: 7163 strb r3, [r4, #5]
+ date_time.date.day = 25;
+ 1a0a: 2219 movs r2, #25
+ 1a0c: 7122 strb r2, [r4, #4]
+ date_time.time.hour = 4;
+ 1a0e: 70a3 strb r3, [r4, #2]
+ date_time.time.min = 0;
+ 1a10: 2500 movs r5, #0
+ 1a12: 7065 strb r5, [r4, #1]
+ date_time.time.sec = 0;
+ 1a14: 7025 strb r5, [r4, #0]
+
+ watch_init(&watch);
+ 1a16: a804 add r0, sp, #16
+ 1a18: 4b1e ldr r3, [pc, #120] ; (1a94 <main+0x9c>)
+ 1a1a: 4798 blx r3
+ watch_enable_led();
+ 1a1c: 4b1e ldr r3, [pc, #120] ; (1a98 <main+0xa0>)
+ 1a1e: 4798 blx r3
+ watch_enable_date_time();
+ 1a20: 4b1e ldr r3, [pc, #120] ; (1a9c <main+0xa4>)
+ 1a22: 4798 blx r3
+ watch_set_date_time(date_time);
+ 1a24: 9802 ldr r0, [sp, #8]
+ 1a26: 6861 ldr r1, [r4, #4]
+ 1a28: 4b1d ldr r3, [pc, #116] ; (1aa0 <main+0xa8>)
+ 1a2a: 4798 blx r3
+ watch_enable_digital_output(A0);
+ 1a2c: 2024 movs r0, #36 ; 0x24
+ 1a2e: 4b1d ldr r3, [pc, #116] ; (1aa4 <main+0xac>)
+ 1a30: 4798 blx r3
+ ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask;
+ 1a32: 2110 movs r1, #16
+ 1a34: 2398 movs r3, #152 ; 0x98
+ 1a36: 22c0 movs r2, #192 ; 0xc0
+ 1a38: 05d2 lsls r2, r2, #23
+ 1a3a: 50d1 str r1, [r2, r3]
+ gpio_set_pin_level(A0, true);
+ watch_enable_i2c();
+ 1a3c: 4b1a ldr r3, [pc, #104] ; (1aa8 <main+0xb0>)
+ 1a3e: 4798 blx r3
+
+ uint8_t chipID = 0;
+ 1a40: 466b mov r3, sp
+ 1a42: 1ddc adds r4, r3, #7
+ 1a44: 71dd strb r5, [r3, #7]
+ uint8_t ChipIdRegister = 0xD0;
+ 1a46: 1d99 adds r1, r3, #6
+ 1a48: 23d0 movs r3, #208 ; 0xd0
+ 1a4a: 700b strb r3, [r1, #0]
+ watch_i2c_send(0x77, &ChipIdRegister, 1);
+ 1a4c: 2201 movs r2, #1
+ 1a4e: 2077 movs r0, #119 ; 0x77
+ 1a50: 4b16 ldr r3, [pc, #88] ; (1aac <main+0xb4>)
+ 1a52: 4798 blx r3
+ watch_i2c_receive(0x77, &chipID, 1);
+ 1a54: 2201 movs r2, #1
+ 1a56: 0021 movs r1, r4
+ 1a58: 2077 movs r0, #119 ; 0x77
+ 1a5a: 4b15 ldr r3, [pc, #84] ; (1ab0 <main+0xb8>)
+ 1a5c: 4798 blx r3
+ if (chipID == 0x60) {
+ 1a5e: 7823 ldrb r3, [r4, #0]
+ 1a60: 2b60 cmp r3, #96 ; 0x60
+ 1a62: d101 bne.n 1a68 <main+0x70>
+ watch_set_led_green();
+ 1a64: 4b13 ldr r3, [pc, #76] ; (1ab4 <main+0xbc>)
+ 1a66: 4798 blx r3
+ }
+
+ uint8_t last = date_time.time.sec;
+ 1a68: ab02 add r3, sp, #8
+ 1a6a: 781c ldrb r4, [r3, #0]
+ 1a6c: e001 b.n 1a72 <main+0x7a>
+ if (date_time.time.sec != last) {
+ last = date_time.time.sec;
+ if (last % 2 == 0) {
+ watch_set_led_red();
+ } else {
+ watch_set_led_green();
+ 1a6e: 4b11 ldr r3, [pc, #68] ; (1ab4 <main+0xbc>)
+ 1a70: 4798 blx r3
+{
+ 1a72: 0025 movs r5, r4
+ watch_get_date_time(&date_time);
+ 1a74: ac02 add r4, sp, #8
+ 1a76: 0020 movs r0, r4
+ 1a78: 4b0f ldr r3, [pc, #60] ; (1ab8 <main+0xc0>)
+ 1a7a: 4798 blx r3
+ if (date_time.time.sec != last) {
+ 1a7c: 7824 ldrb r4, [r4, #0]
+ 1a7e: 42a5 cmp r5, r4
+ 1a80: d0f8 beq.n 1a74 <main+0x7c>
+ if (last % 2 == 0) {
+ 1a82: 07e3 lsls r3, r4, #31
+ 1a84: d4f3 bmi.n 1a6e <main+0x76>
+ watch_set_led_red();
+ 1a86: 4b0d ldr r3, [pc, #52] ; (1abc <main+0xc4>)
+ 1a88: 4798 blx r3
+ 1a8a: e7f2 b.n 1a72 <main+0x7a>
+ 1a8c: 00000109 .word 0x00000109
+ 1a90: 000007e5 .word 0x000007e5
+ 1a94: 00001bb1 .word 0x00001bb1
+ 1a98: 00001bb5 .word 0x00001bb5
+ 1a9c: 00001c19 .word 0x00001c19
+ 1aa0: 00001c35 .word 0x00001c35
+ 1aa4: 00001c75 .word 0x00001c75
+ 1aa8: 00001cb9 .word 0x00001cb9
+ 1aac: 00001ce5 .word 0x00001ce5
+ 1ab0: 00001d15 .word 0x00001d15
+ 1ab4: 00001c05 .word 0x00001c05
+ 1ab8: 00001c61 .word 0x00001c61
+ 1abc: 00001bf1 .word 0x00001bf1
+
+00001ac0 <sleepmgr_event_callback>:
+ *
+ * \param[in] id The event ID to process
+ * \param[in] data Not used
+ */
+static void sleepmgr_event_callback(event_id_t id, event_data_t data)
+{
+ 1ac0: b570 push {r4, r5, r6, lr}
+ 1ac2: b082 sub sp, #8
+ 1ac4: 000e movs r6, r1
+ if (EVENT_IS_READY_TO_SLEEP_ID == id) {
+ 1ac6: 2800 cmp r0, #0
+ 1ac8: d113 bne.n 1af2 <sleepmgr_event_callback+0x32>
+ * \return A pointer to the head of the given list or NULL if the list is
+ * empty
+ */
+static inline void *list_get_head(const struct list_descriptor *const list)
+{
+ return (void *)list->head;
+ 1aca: 4b16 ldr r3, [pc, #88] ; (1b24 <sleepmgr_event_callback+0x64>)
+ 1acc: 681d ldr r5, [r3, #0]
+ struct sleepmgr_ready_to_sleep_cb *cur;
+ struct sleepmgr_ready_to_sleep * ret_val = (struct sleepmgr_ready_to_sleep *)data;
+ struct sleepmgr_ready_to_sleep ready;
+
+ for (cur = (struct sleepmgr_ready_to_sleep_cb *)list_get_head(&ready_to_sleep_cbs); cur;
+ 1ace: e00c b.n 1aea <sleepmgr_event_callback+0x2a>
+ cur = (struct sleepmgr_ready_to_sleep_cb *)list_get_next_element(cur)) {
+ ready.mode = ret_val->mode;
+ 1ad0: 7873 ldrb r3, [r6, #1]
+ 1ad2: ac01 add r4, sp, #4
+ 1ad4: 7063 strb r3, [r4, #1]
+ ready.ready = true;
+ 1ad6: 2301 movs r3, #1
+ 1ad8: 7023 strb r3, [r4, #0]
+ cur->cb(&ready);
+ 1ada: 0020 movs r0, r4
+ 1adc: 686b ldr r3, [r5, #4]
+ 1ade: 4798 blx r3
+ ret_val->ready &= ready.ready;
+ 1ae0: 7832 ldrb r2, [r6, #0]
+ 1ae2: 7823 ldrb r3, [r4, #0]
+ 1ae4: 4013 ands r3, r2
+ 1ae6: 7033 strb r3, [r6, #0]
+ * \return A pointer to the next list element or NULL if there is not next
+ * element
+ */
+static inline void *list_get_next_element(const void *const element)
+{
+ return element ? ((struct list_element *)element)->next : NULL;
+ 1ae8: 682d ldr r5, [r5, #0]
+ for (cur = (struct sleepmgr_ready_to_sleep_cb *)list_get_head(&ready_to_sleep_cbs); cur;
+ 1aea: 2d00 cmp r5, #0
+ 1aec: d1f0 bne.n 1ad0 <sleepmgr_event_callback+0x10>
+ for (cur = (struct sleepmgr_prepare_to_sleep_cb *)list_get_head(&prepare_to_sleep_cbs); cur;
+ cur = (struct sleepmgr_prepare_to_sleep_cb *)list_get_next_element(cur)) {
+ cur->cb(data);
+ }
+ }
+}
+ 1aee: b002 add sp, #8
+ 1af0: bd70 pop {r4, r5, r6, pc}
+ } else if (EVENT_WOKEN_UP_ID == id) {
+ 1af2: 2802 cmp r0, #2
+ 1af4: d004 beq.n 1b00 <sleepmgr_event_callback+0x40>
+ } else if (EVENT_PREPARE_TO_SLEEP_ID == id) {
+ 1af6: 2801 cmp r0, #1
+ 1af8: d1f9 bne.n 1aee <sleepmgr_event_callback+0x2e>
+ return (void *)list->head;
+ 1afa: 4b0a ldr r3, [pc, #40] ; (1b24 <sleepmgr_event_callback+0x64>)
+ 1afc: 689c ldr r4, [r3, #8]
+ for (cur = (struct sleepmgr_prepare_to_sleep_cb *)list_get_head(&prepare_to_sleep_cbs); cur;
+ 1afe: e00d b.n 1b1c <sleepmgr_event_callback+0x5c>
+ 1b00: 4b08 ldr r3, [pc, #32] ; (1b24 <sleepmgr_event_callback+0x64>)
+ 1b02: 685c ldr r4, [r3, #4]
+ for (cur = (struct sleepmgr_wake_up_cb *)list_get_head(&wake_up_cbs); cur;
+ 1b04: e003 b.n 1b0e <sleepmgr_event_callback+0x4e>
+ cur->cb((const enum sleepmgr_wakeup_source)data);
+ 1b06: b2f0 uxtb r0, r6
+ 1b08: 6863 ldr r3, [r4, #4]
+ 1b0a: 4798 blx r3
+ return element ? ((struct list_element *)element)->next : NULL;
+ 1b0c: 6824 ldr r4, [r4, #0]
+ for (cur = (struct sleepmgr_wake_up_cb *)list_get_head(&wake_up_cbs); cur;
+ 1b0e: 2c00 cmp r4, #0
+ 1b10: d1f9 bne.n 1b06 <sleepmgr_event_callback+0x46>
+ 1b12: e7ec b.n 1aee <sleepmgr_event_callback+0x2e>
+ cur->cb(data);
+ 1b14: b2f0 uxtb r0, r6
+ 1b16: 6863 ldr r3, [r4, #4]
+ 1b18: 4798 blx r3
+ 1b1a: 6824 ldr r4, [r4, #0]
+ for (cur = (struct sleepmgr_prepare_to_sleep_cb *)list_get_head(&prepare_to_sleep_cbs); cur;
+ 1b1c: 2c00 cmp r4, #0
+ 1b1e: d1f9 bne.n 1b14 <sleepmgr_event_callback+0x54>
+ 1b20: e7e5 b.n 1aee <sleepmgr_event_callback+0x2e>
+ 1b22: 46c0 nop ; (mov r8, r8)
+ 1b24: 20000070 .word 0x20000070
+
+00001b28 <sleepmgr_init>:
+{
+ 1b28: b570 push {r4, r5, r6, lr}
+ event_subscribe(&sleepmgr_event, EVENT_PREPARE_TO_SLEEP_ID, sleepmgr_event_callback);
+ 1b2a: 4e08 ldr r6, [pc, #32] ; (1b4c <sleepmgr_init+0x24>)
+ 1b2c: 4c08 ldr r4, [pc, #32] ; (1b50 <sleepmgr_init+0x28>)
+ 1b2e: 340c adds r4, #12
+ 1b30: 0032 movs r2, r6
+ 1b32: 2101 movs r1, #1
+ 1b34: 0020 movs r0, r4
+ 1b36: 4d07 ldr r5, [pc, #28] ; (1b54 <sleepmgr_init+0x2c>)
+ 1b38: 47a8 blx r5
+ event_subscribe(&sleepmgr_event, EVENT_IS_READY_TO_SLEEP_ID, sleepmgr_event_callback);
+ 1b3a: 0032 movs r2, r6
+ 1b3c: 2100 movs r1, #0
+ 1b3e: 0020 movs r0, r4
+ 1b40: 47a8 blx r5
+ event_subscribe(&sleepmgr_event, EVENT_WOKEN_UP_ID, sleepmgr_event_callback);
+ 1b42: 0032 movs r2, r6
+ 1b44: 2102 movs r1, #2
+ 1b46: 0020 movs r0, r4
+ 1b48: 47a8 blx r5
+}
+ 1b4a: bd70 pop {r4, r5, r6, pc}
+ 1b4c: 00001ac1 .word 0x00001ac1
+ 1b50: 20000070 .word 0x20000070
+ 1b54: 00000a71 .word 0x00000a71
+
+00001b58 <sleepmgr_register_ready_to_sleep_callback>:
+{
+ 1b58: b510 push {r4, lr}
+ 1b5a: 0004 movs r4, r0
+ ASSERT(cb);
+ 1b5c: 1e43 subs r3, r0, #1
+ 1b5e: 4198 sbcs r0, r3
+ 1b60: b2c0 uxtb r0, r0
+ 1b62: 2240 movs r2, #64 ; 0x40
+ 1b64: 4903 ldr r1, [pc, #12] ; (1b74 <sleepmgr_register_ready_to_sleep_callback+0x1c>)
+ 1b66: 4b04 ldr r3, [pc, #16] ; (1b78 <sleepmgr_register_ready_to_sleep_callback+0x20>)
+ 1b68: 4798 blx r3
+ list_insert_as_head(&ready_to_sleep_cbs, cb);
+ 1b6a: 0021 movs r1, r4
+ 1b6c: 4803 ldr r0, [pc, #12] ; (1b7c <sleepmgr_register_ready_to_sleep_callback+0x24>)
+ 1b6e: 4b04 ldr r3, [pc, #16] ; (1b80 <sleepmgr_register_ready_to_sleep_callback+0x28>)
+ 1b70: 4798 blx r3
+}
+ 1b72: bd10 pop {r4, pc}
+ 1b74: 000020fc .word 0x000020fc
+ 1b78: 00000a69 .word 0x00000a69
+ 1b7c: 20000070 .word 0x20000070
+ 1b80: 00000b11 .word 0x00000b11
+
+00001b84 <sleep_cb>:
+
+static struct sleepmgr_ready_to_sleep_cb sleepmgr_cb;
+
+static void sleep_cb(struct sleepmgr_ready_to_sleep *const ready)
+{
+ ready->ready = false;
+ 1b84: 2300 movs r3, #0
+ 1b86: 7003 strb r3, [r0, #0]
+}
+ 1b88: 4770 bx lr
+ ...
+
+00001b8c <sleep_manager_init>:
+
+void sleep_manager_init(void)
+{
+ 1b8c: b510 push {r4, lr}
+ sleepmgr_init();
+ 1b8e: 4b04 ldr r3, [pc, #16] ; (1ba0 <sleep_manager_init+0x14>)
+ 1b90: 4798 blx r3
+
+ sleepmgr_cb.cb = sleep_cb;
+ 1b92: 4804 ldr r0, [pc, #16] ; (1ba4 <sleep_manager_init+0x18>)
+ 1b94: 4b04 ldr r3, [pc, #16] ; (1ba8 <sleep_manager_init+0x1c>)
+ 1b96: 6043 str r3, [r0, #4]
+ sleepmgr_register_ready_to_sleep_callback(&sleepmgr_cb);
+ 1b98: 4b04 ldr r3, [pc, #16] ; (1bac <sleep_manager_init+0x20>)
+ 1b9a: 4798 blx r3
+}
+ 1b9c: bd10 pop {r4, pc}
+ 1b9e: 46c0 nop ; (mov r8, r8)
+ 1ba0: 00001b29 .word 0x00001b29
+ 1ba4: 20000088 .word 0x20000088
+ 1ba8: 00001b85 .word 0x00001b85
+ 1bac: 00001b59 .word 0x00001b59
+
+00001bb0 <watch_init>:
+
+#include "watch.h"
+#include "driver_init.h"
+
+void watch_init(Watch *watch) {
+}
+ 1bb0: 4770 bx lr
+ ...
+
+00001bb4 <watch_enable_led>:
+
+void watch_enable_led() {
+ 1bb4: b510 push {r4, lr}
+ PWM_0_init();
+ 1bb6: 4b06 ldr r3, [pc, #24] ; (1bd0 <watch_enable_led+0x1c>)
+ 1bb8: 4798 blx r3
+ pwm_set_parameters(&PWM_0, 10000, 0);
+ 1bba: 4c06 ldr r4, [pc, #24] ; (1bd4 <watch_enable_led+0x20>)
+ 1bbc: 2200 movs r2, #0
+ 1bbe: 4906 ldr r1, [pc, #24] ; (1bd8 <watch_enable_led+0x24>)
+ 1bc0: 0020 movs r0, r4
+ 1bc2: 4b06 ldr r3, [pc, #24] ; (1bdc <watch_enable_led+0x28>)
+ 1bc4: 4798 blx r3
+ pwm_enable(&PWM_0);
+ 1bc6: 0020 movs r0, r4
+ 1bc8: 4b05 ldr r3, [pc, #20] ; (1be0 <watch_enable_led+0x2c>)
+ 1bca: 4798 blx r3
+}
+ 1bcc: bd10 pop {r4, pc}
+ 1bce: 46c0 nop ; (mov r8, r8)
+ 1bd0: 000002d5 .word 0x000002d5
+ 1bd4: 20000090 .word 0x20000090
+ 1bd8: 00002710 .word 0x00002710
+ 1bdc: 00000a2d .word 0x00000a2d
+ 1be0: 000009e9 .word 0x000009e9
+
+00001be4 <watch_set_led_color>:
+
+ pwm_disable(&PWM_0);
+}
+
+void watch_set_led_color(uint16_t red, uint16_t green) {
+ TC3->COUNT16.CC[0].reg = red;
+ 1be4: 4b01 ldr r3, [pc, #4] ; (1bec <watch_set_led_color+0x8>)
+ 1be6: 8398 strh r0, [r3, #28]
+ TC3->COUNT16.CC[1].reg = green;
+ 1be8: 83d9 strh r1, [r3, #30]
+}
+ 1bea: 4770 bx lr
+ 1bec: 42002c00 .word 0x42002c00
+
+00001bf0 <watch_set_led_red>:
+
+void watch_set_led_red() {
+ 1bf0: b510 push {r4, lr}
+ watch_set_led_color(65535, 0);
+ 1bf2: 2100 movs r1, #0
+ 1bf4: 4801 ldr r0, [pc, #4] ; (1bfc <watch_set_led_red+0xc>)
+ 1bf6: 4b02 ldr r3, [pc, #8] ; (1c00 <watch_set_led_red+0x10>)
+ 1bf8: 4798 blx r3
+}
+ 1bfa: bd10 pop {r4, pc}
+ 1bfc: 0000ffff .word 0x0000ffff
+ 1c00: 00001be5 .word 0x00001be5
+
+00001c04 <watch_set_led_green>:
+
+void watch_set_led_green() {
+ 1c04: b510 push {r4, lr}
+ watch_set_led_color(0, 65535);
+ 1c06: 4902 ldr r1, [pc, #8] ; (1c10 <watch_set_led_green+0xc>)
+ 1c08: 2000 movs r0, #0
+ 1c0a: 4b02 ldr r3, [pc, #8] ; (1c14 <watch_set_led_green+0x10>)
+ 1c0c: 4798 blx r3
+}
+ 1c0e: bd10 pop {r4, pc}
+ 1c10: 0000ffff .word 0x0000ffff
+ 1c14: 00001be5 .word 0x00001be5
+
+00001c18 <watch_enable_date_time>:
+
+void watch_enable_date_time() {
+ 1c18: b510 push {r4, lr}
+ CALENDAR_0_init();
+ 1c1a: 4b03 ldr r3, [pc, #12] ; (1c28 <watch_enable_date_time+0x10>)
+ 1c1c: 4798 blx r3
+ calendar_enable(&CALENDAR_0);
+ 1c1e: 4803 ldr r0, [pc, #12] ; (1c2c <watch_enable_date_time+0x14>)
+ 1c20: 4b03 ldr r3, [pc, #12] ; (1c30 <watch_enable_date_time+0x18>)
+ 1c22: 4798 blx r3
+}
+ 1c24: bd10 pop {r4, pc}
+ 1c26: 46c0 nop ; (mov r8, r8)
+ 1c28: 0000019d .word 0x0000019d
+ 1c2c: 200000b4 .word 0x200000b4
+ 1c30: 000006fd .word 0x000006fd
+
+00001c34 <watch_set_date_time>:
+
+void watch_set_date_time(struct calendar_date_time date_time) {
+ 1c34: b510 push {r4, lr}
+ 1c36: b082 sub sp, #8
+ 1c38: 9000 str r0, [sp, #0]
+ 1c3a: 9101 str r1, [sp, #4]
+ calendar_set_date(&CALENDAR_0, &date_time.date);
+ 1c3c: 4c05 ldr r4, [pc, #20] ; (1c54 <watch_set_date_time+0x20>)
+ 1c3e: a901 add r1, sp, #4
+ 1c40: 0020 movs r0, r4
+ 1c42: 4b05 ldr r3, [pc, #20] ; (1c58 <watch_set_date_time+0x24>)
+ 1c44: 4798 blx r3
+ calendar_set_time(&CALENDAR_0, &date_time.time);
+ 1c46: 4669 mov r1, sp
+ 1c48: 0020 movs r0, r4
+ 1c4a: 4b04 ldr r3, [pc, #16] ; (1c5c <watch_set_date_time+0x28>)
+ 1c4c: 4798 blx r3
+}
+ 1c4e: b002 add sp, #8
+ 1c50: bd10 pop {r4, pc}
+ 1c52: 46c0 nop ; (mov r8, r8)
+ 1c54: 200000b4 .word 0x200000b4
+ 1c58: 0000078d .word 0x0000078d
+ 1c5c: 00000729 .word 0x00000729
+
+00001c60 <watch_get_date_time>:
+
+void watch_get_date_time(struct calendar_date_time *date_time) {
+ 1c60: b510 push {r4, lr}
+ 1c62: 0001 movs r1, r0
+ calendar_get_date_time(&CALENDAR_0, date_time);
+ 1c64: 4801 ldr r0, [pc, #4] ; (1c6c <watch_get_date_time+0xc>)
+ 1c66: 4b02 ldr r3, [pc, #8] ; (1c70 <watch_get_date_time+0x10>)
+ 1c68: 4798 blx r3
+}
+ 1c6a: bd10 pop {r4, pc}
+ 1c6c: 200000b4 .word 0x200000b4
+ 1c70: 000007f1 .word 0x000007f1
+
+00001c74 <watch_enable_digital_output>:
+void watch_enable_digital_input(const uint8_t pin) {
+ gpio_set_pin_direction(pin, GPIO_DIRECTION_IN);
+ gpio_set_pin_function(pin, GPIO_PIN_FUNCTION_OFF);
+}
+
+void watch_enable_digital_output(const uint8_t pin) {
+ 1c74: b570 push {r4, r5, r6, lr}
+ * GPIO_DIRECTION_OFF = Disables the pin
+ * (low power state)
+ */
+static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction)
+{
+ _gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction);
+ 1c76: 0943 lsrs r3, r0, #5
+ 1c78: 241f movs r4, #31
+ 1c7a: 4004 ands r4, r0
+ 1c7c: 2501 movs r5, #1
+ 1c7e: 0029 movs r1, r5
+ 1c80: 40a1 lsls r1, r4
+ ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
+ 1c82: 01da lsls r2, r3, #7
+ 1c84: 20c0 movs r0, #192 ; 0xc0
+ 1c86: 05c0 lsls r0, r0, #23
+ 1c88: 1810 adds r0, r2, r0
+ 1c8a: 6081 str r1, [r0, #8]
+ | ((mask & 0xffff0000) >> 16));
+ break;
+
+ case GPIO_DIRECTION_OUT:
+ hri_port_set_DIR_reg(PORT_IOBUS, port, mask);
+ hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff));
+ 1c8c: 040e lsls r6, r1, #16
+ 1c8e: 0c36 lsrs r6, r6, #16
+ 1c90: 2080 movs r0, #128 ; 0x80
+ 1c92: 05c0 lsls r0, r0, #23
+ 1c94: 4330 orrs r0, r6
+ ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
+ 1c96: 4e07 ldr r6, [pc, #28] ; (1cb4 <watch_enable_digital_output+0x40>)
+ 1c98: 46b4 mov ip, r6
+ 1c9a: 4462 add r2, ip
+ 1c9c: 6290 str r0, [r2, #40] ; 0x28
+ hri_port_write_WRCONFIG_reg(
+ PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16));
+ 1c9e: 0c09 lsrs r1, r1, #16
+ hri_port_write_WRCONFIG_reg(
+ 1ca0: 20c0 movs r0, #192 ; 0xc0
+ 1ca2: 0600 lsls r0, r0, #24
+ 1ca4: 4301 orrs r1, r0
+ 1ca6: 6291 str r1, [r2, #40] ; 0x28
+ tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+ 1ca8: 1910 adds r0, r2, r4
+ 1caa: 3040 adds r0, #64 ; 0x40
+ 1cac: 7803 ldrb r3, [r0, #0]
+ tmp &= ~PORT_PINCFG_PMUXEN;
+ 1cae: 43ab bics r3, r5
+ ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+ 1cb0: 7003 strb r3, [r0, #0]
+ gpio_set_pin_direction(pin, GPIO_DIRECTION_OUT);
+ gpio_set_pin_function(pin, GPIO_PIN_FUNCTION_OFF);
+}
+ 1cb2: bd70 pop {r4, r5, r6, pc}
+ 1cb4: 41006000 .word 0x41006000
+
+00001cb8 <watch_enable_i2c>:
+
+struct io_descriptor *I2C_0_io;
+
+void watch_enable_i2c() {
+ 1cb8: b510 push {r4, lr}
+ I2C_0_init();
+ 1cba: 4b05 ldr r3, [pc, #20] ; (1cd0 <watch_enable_i2c+0x18>)
+ 1cbc: 4798 blx r3
+ i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io);
+ 1cbe: 4c05 ldr r4, [pc, #20] ; (1cd4 <watch_enable_i2c+0x1c>)
+ 1cc0: 4905 ldr r1, [pc, #20] ; (1cd8 <watch_enable_i2c+0x20>)
+ 1cc2: 0020 movs r0, r4
+ 1cc4: 4b05 ldr r3, [pc, #20] ; (1cdc <watch_enable_i2c+0x24>)
+ 1cc6: 4798 blx r3
+ i2c_m_sync_enable(&I2C_0);
+ 1cc8: 0020 movs r0, r4
+ 1cca: 4b05 ldr r3, [pc, #20] ; (1ce0 <watch_enable_i2c+0x28>)
+ 1ccc: 4798 blx r3
+}
+ 1cce: bd10 pop {r4, pc}
+ 1cd0: 00000235 .word 0x00000235
+ 1cd4: 200000f8 .word 0x200000f8
+ 1cd8: 20000118 .word 0x20000118
+ 1cdc: 00000907 .word 0x00000907
+ 1ce0: 000008e9 .word 0x000008e9
+
+00001ce4 <watch_i2c_send>:
+
+void watch_i2c_send(int16_t addr, uint8_t *buf, uint16_t length) {
+ 1ce4: b570 push {r4, r5, r6, lr}
+ 1ce6: 000c movs r4, r1
+ 1ce8: 0015 movs r5, r2
+ i2c_m_sync_set_slaveaddr(&I2C_0, addr, I2C_M_SEVEN);
+ 1cea: 2280 movs r2, #128 ; 0x80
+ 1cec: 0112 lsls r2, r2, #4
+ 1cee: 0001 movs r1, r0
+ 1cf0: 4804 ldr r0, [pc, #16] ; (1d04 <watch_i2c_send+0x20>)
+ 1cf2: 4b05 ldr r3, [pc, #20] ; (1d08 <watch_i2c_send+0x24>)
+ 1cf4: 4798 blx r3
+ io_write(I2C_0_io, buf, length);
+ 1cf6: 4b05 ldr r3, [pc, #20] ; (1d0c <watch_i2c_send+0x28>)
+ 1cf8: 6818 ldr r0, [r3, #0]
+ 1cfa: 002a movs r2, r5
+ 1cfc: 0021 movs r1, r4
+ 1cfe: 4b04 ldr r3, [pc, #16] ; (1d10 <watch_i2c_send+0x2c>)
+ 1d00: 4798 blx r3
+}
+ 1d02: bd70 pop {r4, r5, r6, pc}
+ 1d04: 200000f8 .word 0x200000f8
+ 1d08: 000008f5 .word 0x000008f5
+ 1d0c: 20000118 .word 0x20000118
+ 1d10: 00000911 .word 0x00000911
+
+00001d14 <watch_i2c_receive>:
+
+void watch_i2c_receive(int16_t addr, uint8_t *buf, uint16_t length) {
+ 1d14: b570 push {r4, r5, r6, lr}
+ 1d16: 000c movs r4, r1
+ 1d18: 0015 movs r5, r2
+ i2c_m_sync_set_slaveaddr(&I2C_0, addr, I2C_M_SEVEN);
+ 1d1a: 2280 movs r2, #128 ; 0x80
+ 1d1c: 0112 lsls r2, r2, #4
+ 1d1e: 0001 movs r1, r0
+ 1d20: 4804 ldr r0, [pc, #16] ; (1d34 <watch_i2c_receive+0x20>)
+ 1d22: 4b05 ldr r3, [pc, #20] ; (1d38 <watch_i2c_receive+0x24>)
+ 1d24: 4798 blx r3
+ io_read(I2C_0_io, buf, length);
+ 1d26: 4b05 ldr r3, [pc, #20] ; (1d3c <watch_i2c_receive+0x28>)
+ 1d28: 6818 ldr r0, [r3, #0]
+ 1d2a: 002a movs r2, r5
+ 1d2c: 0021 movs r1, r4
+ 1d2e: 4b04 ldr r3, [pc, #16] ; (1d40 <watch_i2c_receive+0x2c>)
+ 1d30: 4798 blx r3
+}
+ 1d32: bd70 pop {r4, r5, r6, pc}
+ 1d34: 200000f8 .word 0x200000f8
+ 1d38: 000008f5 .word 0x000008f5
+ 1d3c: 20000118 .word 0x20000118
+ 1d40: 00000949 .word 0x00000949
+
+00001d44 <__udivsi3>:
+ 1d44: 2200 movs r2, #0
+ 1d46: 0843 lsrs r3, r0, #1
+ 1d48: 428b cmp r3, r1
+ 1d4a: d374 bcc.n 1e36 <__udivsi3+0xf2>
+ 1d4c: 0903 lsrs r3, r0, #4
+ 1d4e: 428b cmp r3, r1
+ 1d50: d35f bcc.n 1e12 <__udivsi3+0xce>
+ 1d52: 0a03 lsrs r3, r0, #8
+ 1d54: 428b cmp r3, r1
+ 1d56: d344 bcc.n 1de2 <__udivsi3+0x9e>
+ 1d58: 0b03 lsrs r3, r0, #12
+ 1d5a: 428b cmp r3, r1
+ 1d5c: d328 bcc.n 1db0 <__udivsi3+0x6c>
+ 1d5e: 0c03 lsrs r3, r0, #16
+ 1d60: 428b cmp r3, r1
+ 1d62: d30d bcc.n 1d80 <__udivsi3+0x3c>
+ 1d64: 22ff movs r2, #255 ; 0xff
+ 1d66: 0209 lsls r1, r1, #8
+ 1d68: ba12 rev r2, r2
+ 1d6a: 0c03 lsrs r3, r0, #16
+ 1d6c: 428b cmp r3, r1
+ 1d6e: d302 bcc.n 1d76 <__udivsi3+0x32>
+ 1d70: 1212 asrs r2, r2, #8
+ 1d72: 0209 lsls r1, r1, #8
+ 1d74: d065 beq.n 1e42 <__udivsi3+0xfe>
+ 1d76: 0b03 lsrs r3, r0, #12
+ 1d78: 428b cmp r3, r1
+ 1d7a: d319 bcc.n 1db0 <__udivsi3+0x6c>
+ 1d7c: e000 b.n 1d80 <__udivsi3+0x3c>
+ 1d7e: 0a09 lsrs r1, r1, #8
+ 1d80: 0bc3 lsrs r3, r0, #15
+ 1d82: 428b cmp r3, r1
+ 1d84: d301 bcc.n 1d8a <__udivsi3+0x46>
+ 1d86: 03cb lsls r3, r1, #15
+ 1d88: 1ac0 subs r0, r0, r3
+ 1d8a: 4152 adcs r2, r2
+ 1d8c: 0b83 lsrs r3, r0, #14
+ 1d8e: 428b cmp r3, r1
+ 1d90: d301 bcc.n 1d96 <__udivsi3+0x52>
+ 1d92: 038b lsls r3, r1, #14
+ 1d94: 1ac0 subs r0, r0, r3
+ 1d96: 4152 adcs r2, r2
+ 1d98: 0b43 lsrs r3, r0, #13
+ 1d9a: 428b cmp r3, r1
+ 1d9c: d301 bcc.n 1da2 <__udivsi3+0x5e>
+ 1d9e: 034b lsls r3, r1, #13
+ 1da0: 1ac0 subs r0, r0, r3
+ 1da2: 4152 adcs r2, r2
+ 1da4: 0b03 lsrs r3, r0, #12
+ 1da6: 428b cmp r3, r1
+ 1da8: d301 bcc.n 1dae <__udivsi3+0x6a>
+ 1daa: 030b lsls r3, r1, #12
+ 1dac: 1ac0 subs r0, r0, r3
+ 1dae: 4152 adcs r2, r2
+ 1db0: 0ac3 lsrs r3, r0, #11
+ 1db2: 428b cmp r3, r1
+ 1db4: d301 bcc.n 1dba <__udivsi3+0x76>
+ 1db6: 02cb lsls r3, r1, #11
+ 1db8: 1ac0 subs r0, r0, r3
+ 1dba: 4152 adcs r2, r2
+ 1dbc: 0a83 lsrs r3, r0, #10
+ 1dbe: 428b cmp r3, r1
+ 1dc0: d301 bcc.n 1dc6 <__udivsi3+0x82>
+ 1dc2: 028b lsls r3, r1, #10
+ 1dc4: 1ac0 subs r0, r0, r3
+ 1dc6: 4152 adcs r2, r2
+ 1dc8: 0a43 lsrs r3, r0, #9
+ 1dca: 428b cmp r3, r1
+ 1dcc: d301 bcc.n 1dd2 <__udivsi3+0x8e>
+ 1dce: 024b lsls r3, r1, #9
+ 1dd0: 1ac0 subs r0, r0, r3
+ 1dd2: 4152 adcs r2, r2
+ 1dd4: 0a03 lsrs r3, r0, #8
+ 1dd6: 428b cmp r3, r1
+ 1dd8: d301 bcc.n 1dde <__udivsi3+0x9a>
+ 1dda: 020b lsls r3, r1, #8
+ 1ddc: 1ac0 subs r0, r0, r3
+ 1dde: 4152 adcs r2, r2
+ 1de0: d2cd bcs.n 1d7e <__udivsi3+0x3a>
+ 1de2: 09c3 lsrs r3, r0, #7
+ 1de4: 428b cmp r3, r1
+ 1de6: d301 bcc.n 1dec <__udivsi3+0xa8>
+ 1de8: 01cb lsls r3, r1, #7
+ 1dea: 1ac0 subs r0, r0, r3
+ 1dec: 4152 adcs r2, r2
+ 1dee: 0983 lsrs r3, r0, #6
+ 1df0: 428b cmp r3, r1
+ 1df2: d301 bcc.n 1df8 <__udivsi3+0xb4>
+ 1df4: 018b lsls r3, r1, #6
+ 1df6: 1ac0 subs r0, r0, r3
+ 1df8: 4152 adcs r2, r2
+ 1dfa: 0943 lsrs r3, r0, #5
+ 1dfc: 428b cmp r3, r1
+ 1dfe: d301 bcc.n 1e04 <__udivsi3+0xc0>
+ 1e00: 014b lsls r3, r1, #5
+ 1e02: 1ac0 subs r0, r0, r3
+ 1e04: 4152 adcs r2, r2
+ 1e06: 0903 lsrs r3, r0, #4
+ 1e08: 428b cmp r3, r1
+ 1e0a: d301 bcc.n 1e10 <__udivsi3+0xcc>
+ 1e0c: 010b lsls r3, r1, #4
+ 1e0e: 1ac0 subs r0, r0, r3
+ 1e10: 4152 adcs r2, r2
+ 1e12: 08c3 lsrs r3, r0, #3
+ 1e14: 428b cmp r3, r1
+ 1e16: d301 bcc.n 1e1c <__udivsi3+0xd8>
+ 1e18: 00cb lsls r3, r1, #3
+ 1e1a: 1ac0 subs r0, r0, r3
+ 1e1c: 4152 adcs r2, r2
+ 1e1e: 0883 lsrs r3, r0, #2
+ 1e20: 428b cmp r3, r1
+ 1e22: d301 bcc.n 1e28 <__udivsi3+0xe4>
+ 1e24: 008b lsls r3, r1, #2
+ 1e26: 1ac0 subs r0, r0, r3
+ 1e28: 4152 adcs r2, r2
+ 1e2a: 0843 lsrs r3, r0, #1
+ 1e2c: 428b cmp r3, r1
+ 1e2e: d301 bcc.n 1e34 <__udivsi3+0xf0>
+ 1e30: 004b lsls r3, r1, #1
+ 1e32: 1ac0 subs r0, r0, r3
+ 1e34: 4152 adcs r2, r2
+ 1e36: 1a41 subs r1, r0, r1
+ 1e38: d200 bcs.n 1e3c <__udivsi3+0xf8>
+ 1e3a: 4601 mov r1, r0
+ 1e3c: 4152 adcs r2, r2
+ 1e3e: 4610 mov r0, r2
+ 1e40: 4770 bx lr
+ 1e42: e7ff b.n 1e44 <__udivsi3+0x100>
+ 1e44: b501 push {r0, lr}
+ 1e46: 2000 movs r0, #0
+ 1e48: f000 f806 bl 1e58 <__aeabi_idiv0>
+ 1e4c: bd02 pop {r1, pc}
+ 1e4e: 46c0 nop ; (mov r8, r8)
+
+00001e50 <__aeabi_uidivmod>:
+ 1e50: 2900 cmp r1, #0
+ 1e52: d0f7 beq.n 1e44 <__udivsi3+0x100>
+ 1e54: e776 b.n 1d44 <__udivsi3>
+ 1e56: 4770 bx lr
+
+00001e58 <__aeabi_idiv0>:
+ 1e58: 4770 bx lr
+ 1e5a: 46c0 nop ; (mov r8, r8)
+
+00001e5c <__ffssi2>:
+ 1e5c: b510 push {r4, lr}
+ 1e5e: 2300 movs r3, #0
+ 1e60: 2800 cmp r0, #0
+ 1e62: d002 beq.n 1e6a <__ffssi2+0xe>
+ 1e64: f000 f804 bl 1e70 <__ctzsi2>
+ 1e68: 1c43 adds r3, r0, #1
+ 1e6a: 0018 movs r0, r3
+ 1e6c: bd10 pop {r4, pc}
+ 1e6e: 46c0 nop ; (mov r8, r8)
+
+00001e70 <__ctzsi2>:
+ 1e70: 4241 negs r1, r0
+ 1e72: 4008 ands r0, r1
+ 1e74: 211c movs r1, #28
+ 1e76: 2301 movs r3, #1
+ 1e78: 041b lsls r3, r3, #16
+ 1e7a: 4298 cmp r0, r3
+ 1e7c: d301 bcc.n 1e82 <__ctzsi2+0x12>
+ 1e7e: 0c00 lsrs r0, r0, #16
+ 1e80: 3910 subs r1, #16
+ 1e82: 0a1b lsrs r3, r3, #8
+ 1e84: 4298 cmp r0, r3
+ 1e86: d301 bcc.n 1e8c <__ctzsi2+0x1c>
+ 1e88: 0a00 lsrs r0, r0, #8
+ 1e8a: 3908 subs r1, #8
+ 1e8c: 091b lsrs r3, r3, #4
+ 1e8e: 4298 cmp r0, r3
+ 1e90: d301 bcc.n 1e96 <__ctzsi2+0x26>
+ 1e92: 0900 lsrs r0, r0, #4
+ 1e94: 3904 subs r1, #4
+ 1e96: a202 add r2, pc, #8 ; (adr r2, 1ea0 <__ctzsi2+0x30>)
+ 1e98: 5c10 ldrb r0, [r2, r0]
+ 1e9a: 1a40 subs r0, r0, r1
+ 1e9c: 4770 bx lr
+ 1e9e: 46c0 nop ; (mov r8, r8)
+ 1ea0: 1d1d1c1b .word 0x1d1d1c1b
+ 1ea4: 1e1e1e1e .word 0x1e1e1e1e
+ 1ea8: 1f1f1f1f .word 0x1f1f1f1f
+ 1eac: 1f1f1f1f .word 0x1f1f1f1f
+
+00001eb0 <__libc_init_array>:
+ 1eb0: b570 push {r4, r5, r6, lr}
+ 1eb2: 2600 movs r6, #0
+ 1eb4: 4d0c ldr r5, [pc, #48] ; (1ee8 <__libc_init_array+0x38>)
+ 1eb6: 4c0d ldr r4, [pc, #52] ; (1eec <__libc_init_array+0x3c>)
+ 1eb8: 1b64 subs r4, r4, r5
+ 1eba: 10a4 asrs r4, r4, #2
+ 1ebc: 42a6 cmp r6, r4
+ 1ebe: d109 bne.n 1ed4 <__libc_init_array+0x24>
+ 1ec0: 2600 movs r6, #0
+ 1ec2: f000 f92d bl 2120 <_init>
+ 1ec6: 4d0a ldr r5, [pc, #40] ; (1ef0 <__libc_init_array+0x40>)
+ 1ec8: 4c0a ldr r4, [pc, #40] ; (1ef4 <__libc_init_array+0x44>)
+ 1eca: 1b64 subs r4, r4, r5
+ 1ecc: 10a4 asrs r4, r4, #2
+ 1ece: 42a6 cmp r6, r4
+ 1ed0: d105 bne.n 1ede <__libc_init_array+0x2e>
+ 1ed2: bd70 pop {r4, r5, r6, pc}
+ 1ed4: 00b3 lsls r3, r6, #2
+ 1ed6: 58eb ldr r3, [r5, r3]
+ 1ed8: 4798 blx r3
+ 1eda: 3601 adds r6, #1
+ 1edc: e7ee b.n 1ebc <__libc_init_array+0xc>
+ 1ede: 00b3 lsls r3, r6, #2
+ 1ee0: 58eb ldr r3, [r5, r3]
+ 1ee2: 4798 blx r3
+ 1ee4: 3601 adds r6, #1
+ 1ee6: e7f2 b.n 1ece <__libc_init_array+0x1e>
+ 1ee8: 0000212c .word 0x0000212c
+ 1eec: 0000212c .word 0x0000212c
+ 1ef0: 0000212c .word 0x0000212c
+ 1ef4: 00002130 .word 0x00002130
+ 1ef8: 000003c2 .word 0x000003c2
+ 1efc: 000003e6 .word 0x000003e6
+ 1f00: 000003c6 .word 0x000003c6
+ 1f04: 000003e6 .word 0x000003e6
+ 1f08: 000003ca .word 0x000003ca
+ 1f0c: 000003e6 .word 0x000003e6
+ 1f10: 000003ca .word 0x000003ca
+ 1f14: 000003e6 .word 0x000003e6
+ 1f18: 000003e6 .word 0x000003e6
+ 1f1c: 000003ca .word 0x000003ca
+ 1f20: 000003e6 .word 0x000003e6
+ 1f24: 000003ca .word 0x000003ca
+ 1f28: 000003e6 .word 0x000003e6
+ 1f2c: 000003da .word 0x000003da
+ 1f30: 000003ea .word 0x000003ea
+ 1f34: 000003de .word 0x000003de
+ 1f38: 000003ea .word 0x000003ea
+ 1f3c: 000003e2 .word 0x000003e2
+ 1f40: 000003ea .word 0x000003ea
+ 1f44: 000003e2 .word 0x000003e2
+ 1f48: 000003ea .word 0x000003ea
+ 1f4c: 000003ea .word 0x000003ea
+ 1f50: 000003e2 .word 0x000003e2
+ 1f54: 000003ea .word 0x000003ea
+ 1f58: 000003e2 .word 0x000003e2
+ 1f5c: 000003ea .word 0x000003ea
+ 1f60: 0000058c .word 0x0000058c
+ 1f64: 00000586 .word 0x00000586
+ 1f68: 00000590 .word 0x00000590
+ 1f6c: 0000059e .word 0x0000059e
+ 1f70: 000005aa .word 0x000005aa
+ 1f74: 000005ba .word 0x000005ba
+ 1f78: 00000636 .word 0x00000636
+ 1f7c: 00000618 .word 0x00000618
+ 1f80: 0000065a .word 0x0000065a
+ 1f84: 00000674 .word 0x00000674
+ 1f88: 00000688 .word 0x00000688
+ 1f8c: 00000696 .word 0x00000696
+ 1f90: 682f2e2e .word 0x682f2e2e
+ 1f94: 732f6c61 .word 0x732f6c61
+ 1f98: 682f6372 .word 0x682f6372
+ 1f9c: 635f6c61 .word 0x635f6c61
+ 1fa0: 6e656c61 .word 0x6e656c61
+ 1fa4: 2e726164 .word 0x2e726164
+ 1fa8: 00000063 .word 0x00000063
+ 1fac: 682f2e2e .word 0x682f2e2e
+ 1fb0: 732f6c61 .word 0x732f6c61
+ 1fb4: 682f6372 .word 0x682f6372
+ 1fb8: 695f6c61 .word 0x695f6c61
+ 1fbc: 6d5f6332 .word 0x6d5f6332
+ 1fc0: 6e79735f .word 0x6e79735f
+ 1fc4: 00632e63 .word 0x00632e63
+ 1fc8: 682f2e2e .word 0x682f2e2e
+ 1fcc: 732f6c61 .word 0x732f6c61
+ 1fd0: 682f6372 .word 0x682f6372
+ 1fd4: 695f6c61 .word 0x695f6c61
+ 1fd8: 00632e6f .word 0x00632e6f
+ 1fdc: 682f2e2e .word 0x682f2e2e
+ 1fe0: 732f6c61 .word 0x732f6c61
+ 1fe4: 682f6372 .word 0x682f6372
+ 1fe8: 705f6c61 .word 0x705f6c61
+ 1fec: 632e6d77 .word 0x632e6d77
+ 1ff0: 00000000 .word 0x00000000
+ 1ff4: 682f2e2e .word 0x682f2e2e
+ 1ff8: 752f6c61 .word 0x752f6c61
+ 1ffc: 736c6974 .word 0x736c6974
+ 2000: 6372732f .word 0x6372732f
+ 2004: 6974752f .word 0x6974752f
+ 2008: 655f736c .word 0x655f736c
+ 200c: 746e6576 .word 0x746e6576
+ 2010: 0000632e .word 0x0000632e
+ 2014: 682f2e2e .word 0x682f2e2e
+ 2018: 752f6c61 .word 0x752f6c61
+ 201c: 736c6974 .word 0x736c6974
+ 2020: 6372732f .word 0x6372732f
+ 2024: 6974752f .word 0x6974752f
+ 2028: 6c5f736c .word 0x6c5f736c
+ 202c: 2e747369 .word 0x2e747369
+ 2030: 00000063 .word 0x00000063
+
+00002034 <_map>:
+ 2034: 00000005 00000025 00000006 00000016 ....%...........
+ 2044: 00000007 00000017 682f2e2e 652f6c70 ........../hpl/e
+ 2054: 682f6369 655f6c70 632e6369 00000000 ic/hpl_eic.c....
+ 2064: 682f2e2e 722f6c70 682f6374 725f6c70 ../hpl/rtc/hpl_r
+ 2074: 632e6374 00000000 tc.c....
+
+0000207c <_usarts>:
+ ...
+
+00002090 <_i2cms>:
+ 2090: 00000001 00200014 00000100 00000f0e ...... .........
+ 20a0: 00d70000 003d0900 ......=.
+
+000020a8 <_i2css>:
+ ...
+
+000020b8 <sercomspi_regs>:
+ ...
+ 20cc: 682f2e2e 732f6c70 6f637265 70682f6d ../hpl/sercom/hp
+ 20dc: 65735f6c 6d6f6372 0000632e 682f2e2e l_sercom.c..../h
+ 20ec: 742f6c70 70682f63 63745f6c 0000632e pl/tc/hpl_tc.c..
+ 20fc: 732f2e2e 7065656c 6e616d5f 72656761 ../sleep_manager
+ 210c: 656c732f 6d5f7065 67616e61 632e7265 /sleep_manager.c
+ 211c: 00000000 ....
+
+00002120 <_init>:
+ 2120: b5f8 push {r3, r4, r5, r6, r7, lr}
+ 2122: 46c0 nop ; (mov r8, r8)
+ 2124: bcf8 pop {r3, r4, r5, r6, r7}
+ 2126: bc08 pop {r3}
+ 2128: 469e mov lr, r3
+ 212a: 4770 bx lr
+
+0000212c <__init_array_start>:
+ 212c: 000000d1 .word 0x000000d1
+
+00002130 <_fini>:
+ 2130: b5f8 push {r3, r4, r5, r6, r7, lr}
+ 2132: 46c0 nop ; (mov r8, r8)
+ 2134: bcf8 pop {r3, r4, r5, r6, r7}
+ 2136: bc08 pop {r3}
+ 2138: 469e mov lr, r3
+ 213a: 4770 bx lr
+
+0000213c <__fini_array_start>:
+ 213c: 000000a9 .word 0x000000a9
|