Precision watch update (#152)

* Intermediate changes

* Databank working

* Main commit for precision timing

First version where all functions are supposed to be working

* Fix math error in nanosec. File storage for location.

* Remove obsolete comments

* Missing page name on pages rotation - thanks to jeremy

* Delete file.diff

* Cleanup+tempchart

1) finetune must always reset last calibration time when doing non-0 time correction, even when you are not applying ppm correction.
2) Dithers over 31 periods not 10, more resolution with still no risk of overflow
3) Minute-boundery finetune fix. I also just got this 1-minute error after finetune...
4) Write frequency calibration value in 1 operation rather than 2. All RTC writes must be single operations to avoid partially correct data.
5) Some code cleanup
6) Tempchart face is added for temperature statistics

* Update set_time_hackwatch_face.c

* Math error in display code of finetune, allow to update correction time even without correction - by long alarm press

* Increase reliability of stopping & starting RTC timer

As it's quite dangerous operation

* hackwatch - days adjust down fix by long alarm

* unify style

* More comments & last style change

* Simulator support

RTC operations (watch_rtc_enable and watch_rtc_freqcorr_write) are in common libs.

* Unicode fix

* Crystal aging is now adjustable (AA page in nanosec - annual aging, ppm/year)

Aging is baked into fixed offset every time finetune is performed, as it relies on last adjustment time.

* Blink on non-0 page every minute in finetune to measure clock error

* Rolling back private changes

* Cleanup

* Cleanup

* Quality of life changes in nanosec

1. Does not calculate & apply ppm correction if less than 6 hours passed since previous adjustment (as it gives very high correction values which are unrealistic and unhelpful)
2. Idle timeout resets to face 0 only if no correction was made

* unify style

* Fix low-power errors in nanosec infrastructure, faster display in finetune

* Merge fix

* unify style

Co-authored-by: Jeremy O'Brien <neutral@fastmail.com>
Co-authored-by: joeycastillo <joeycastillo@utexas.edu>

1 files changed, 26 insertions, 1 deletions

diff --git a/watch-library/hardware/watch/watch_rtc.c b/watch-library/hardware/watch/watch_rtc.c
index 8382e571..881e2575 100644
--- a/watch-library/hardware/watch/watch_rtc.c
+++ b/watch-library/hardware/watch/watch_rtc.c
@@ -57,6 +57,7 @@ void _watch_rtc_init(void) {
 }
 
 void watch_rtc_set_date_time(watch_date_time date_time) {
+    _sync_rtc(); // Double sync as without it at high Hz faces setting time is unrealiable (specifically, set_time_hackwatch)
     RTC->MODE2.CLOCK.reg = date_time.reg;
     _sync_rtc();
 }
@@ -137,7 +138,7 @@ void RTC_Handler(void) {
                     tick_callbacks[i]();
                 }
                 RTC->MODE2.INTFLAG.reg = 1 << i;
-                break;
+//                break; Uncertain if this fix is requried. We were discussing in discord. Might slightly increase power consumption. 
             }
         }
     } else if ((interrupt_status & interrupt_enabled) & RTC_MODE2_INTFLAG_TAMPER) {
@@ -160,3 +161,27 @@ void RTC_Handler(void) {
         RTC->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0;
     }
 }
+
+void watch_rtc_enable(bool en)
+{
+    // Writing it twice - as it's quite dangerous operation.
+    // If write fails - we might hang with RTC off, which means no recovery possible
+    while (RTC->MODE2.SYNCBUSY.reg);
+    RTC->MODE2.CTRLA.bit.ENABLE = en ? 1 : 0;
+    while (RTC->MODE2.SYNCBUSY.reg);
+    RTC->MODE2.CTRLA.bit.ENABLE = en ? 1 : 0;
+    while (RTC->MODE2.SYNCBUSY.reg);
+}
+
+void watch_rtc_freqcorr_write(int16_t value, int16_t sign)
+{
+    RTC_FREQCORR_Type data;
+
+    data.bit.VALUE = value;
+    data.bit.SIGN = sign;
+
+    RTC->MODE2.FREQCORR.reg = data.reg; // Setting correction in single write operation
+
+    // We do not sycnronize. We are not in a hurry
+}
+