work around silicon erratum in TRNG

1 files changed, 10 insertions, 1 deletions

diff --git a/watch-library/hardware/watch/watch_private.c b/watch-library/hardware/watch/watch_private.c
index cd607b8e..4cae3ccb 100644
--- a/watch-library/hardware/watch/watch_private.c
+++ b/watch-library/hardware/watch/watch_private.c
@@ -106,12 +106,21 @@ int getentropy(void *buf, size_t buflen) {
         }
     }
 
-    hri_trng_clear_CTRLA_ENABLE_bit(TRNG);
+    watch_disable_TRNG(TRNG);
     hri_mclk_clear_APBCMASK_TRNG_bit(MCLK);
 
     return 0;
 }
 
+void watch_disable_TRNG(Trng *hw) {
+    hri_trng_clear_CTRLA_ENABLE_bit(hw);
+    // silicon erratum: the TRNG may leave internal components powered after disable.
+    // the workaround is to clear the register twice.
+    hri_trng_write_CTRLA_reg(hw, 0);
+    hri_trng_write_CTRLA_reg(hw, 0);
+}
+
+
 void _watch_enable_tcc(void) {
     // clock TCC0 with the main clock (8 MHz) and enable the peripheral clock.
     hri_gclk_write_PCHCTRL_reg(GCLK, TCC0_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK0_Val | GCLK_PCHCTRL_CHEN);