remove tinyusb directory

466 files changed, 0 insertions, 83801 deletions

diff --git a/tinyusb/hw/bsp/ansi_escape.h b/tinyusb/hw/bsp/ansi_escape.h
deleted file mode 100755
index 35342cfe..00000000
--- a/tinyusb/hw/bsp/ansi_escape.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-/** \ingroup group_board
- *  \defgroup group_ansi_esc ANSI Esacpe Code
- *  @{ */
-
-#ifndef _TUSB_ANSI_ESC_CODE_H_
-#define _TUSB_ANSI_ESC_CODE_H_
-
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define CSI_CODE(seq)   "\33[" seq
-#define CSI_SGR(x)      CSI_CODE(#x) "m"
-
-//------------- Cursor movement -------------//
-/** \defgroup group_ansi_cursor Cursor Movement
- *  @{ */
-#define ANSI_CURSOR_UP(n)        CSI_CODE(#n "A")          ///< Move cursor up
-#define ANSI_CURSOR_DOWN(n)      CSI_CODE(#n "B")          ///< Move cursor down
-#define ANSI_CURSOR_FORWARD(n)   CSI_CODE(#n "C")          ///< Move cursor forward
-#define ANSI_CURSOR_BACKWARD(n)  CSI_CODE(#n "D")          ///< Move cursor backward
-#define ANSI_CURSOR_LINE_DOWN(n) CSI_CODE(#n "E")          ///< Move cursor to the beginning of the line (n) down
-#define ANSI_CURSOR_LINE_UP(n)   CSI_CODE(#n "F")          ///< Move cursor to the beginning of the line (n) up
-#define ANSI_CURSOR_POSITION(n, m) CSI_CODE(#n ";" #m "H") ///< Move cursor to position (n, m)
-/** @} */
-
-//------------- Screen -------------//
-/** \defgroup group_ansi_screen Screen Control
- *  @{ */
-#define ANSI_ERASE_SCREEN(n)     CSI_CODE(#n "J") ///< Erase the screen
-#define ANSI_ERASE_LINE(n)       CSI_CODE(#n "K") ///< Erase the line (n)
-#define ANSI_SCROLL_UP(n)        CSI_CODE(#n "S") ///< Scroll the whole page up (n) lines
-#define ANSI_SCROLL_DOWN(n)      CSI_CODE(#n "T") ///< Scroll the whole page down (n) lines
-/** @} */
-
-//------------- Text Color -------------//
-/** \defgroup group_ansi_text Text Color
- *  @{ */
-#define ANSI_TEXT_BLACK          CSI_SGR(30)
-#define ANSI_TEXT_RED            CSI_SGR(31)
-#define ANSI_TEXT_GREEN          CSI_SGR(32)
-#define ANSI_TEXT_YELLOW         CSI_SGR(33)
-#define ANSI_TEXT_BLUE           CSI_SGR(34)
-#define ANSI_TEXT_MAGENTA        CSI_SGR(35)
-#define ANSI_TEXT_CYAN           CSI_SGR(36)
-#define ANSI_TEXT_WHITE          CSI_SGR(37)
-#define ANSI_TEXT_DEFAULT        CSI_SGR(39)
-/** @} */
-
-//------------- Background Color -------------//
-/** \defgroup group_ansi_background Background Color
- *  @{ */
-#define ANSI_BG_BLACK            CSI_SGR(40)
-#define ANSI_BG_RED              CSI_SGR(41)
-#define ANSI_BG_GREEN            CSI_SGR(42)
-#define ANSI_BG_YELLOW           CSI_SGR(43)
-#define ANSI_BG_BLUE             CSI_SGR(44)
-#define ANSI_BG_MAGENTA          CSI_SGR(45)
-#define ANSI_BG_CYAN             CSI_SGR(46)
-#define ANSI_BG_WHITE            CSI_SGR(47)
-#define ANSI_BG_DEFAULT          CSI_SGR(49)
-/** @} */
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* _TUSB_ANSI_ESC_CODE_H_ */
-
-/** @} */
diff --git a/tinyusb/hw/bsp/board.c b/tinyusb/hw/bsp/board.c
deleted file mode 100755
index 6a26f55b..00000000
--- a/tinyusb/hw/bsp/board.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2018, hathach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- */
-
-#include "board.h"
-
-#if 0
-#define LED_PHASE_MAX   8
-
-static struct
-{
-  uint32_t phase[LED_PHASE_MAX];
-  uint8_t phase_count;
-
-  bool led_state;
-  uint8_t current_phase;
-  uint32_t current_ms;
-}led_pattern;
-
-void board_led_pattern(uint32_t const phase_ms[], uint8_t count)
-{
-  memcpy(led_pattern.phase, phase_ms, 4*count);
-  led_pattern.phase_count = count;
-
-  // reset with 1st phase is on
-  led_pattern.current_ms = board_millis();
-  led_pattern.current_phase = 0;
-  led_pattern.led_state = true;
-  board_led_on();
-}
-
-void board_led_task(void)
-{
-  if ( led_pattern.phase_count == 0 ) return;
-
-  uint32_t const duration = led_pattern.phase[led_pattern.current_phase];
-
-  // return if not enough time
-  if (board_millis() - led_pattern.current_ms < duration) return;
-
-  led_pattern.led_state = !led_pattern.led_state;
-  board_led_write(led_pattern.led_state);
-
-  led_pattern.current_ms += duration;
-  led_pattern.current_phase++;
-
-  if (led_pattern.current_phase == led_pattern.phase_count)
-  {
-    led_pattern.current_phase = 0;
-    led_pattern.led_state = true;
-    board_led_on();
-  }
-}
-#endif
-
-//--------------------------------------------------------------------+
-// newlib read()/write() retarget
-//--------------------------------------------------------------------+
-
-#if defined(__MSP430__) || defined(__RX__)
-  #define sys_write   write
-  #define sys_read    read
-#else
-  #define sys_write   _write
-  #define sys_read    _read
-#endif
-
-#if defined(LOGGER_RTT)
-// Logging with RTT
-
-// If using SES IDE, use the Syscalls/SEGGER_RTT_Syscalls_SES.c instead
-#if !(defined __SES_ARM) && !(defined __SES_RISCV) && !(defined __CROSSWORKS_ARM)
-#include "SEGGER_RTT.h"
-
-TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count)
-{
-  (void) fhdl;
-  SEGGER_RTT_Write(0, (char*) buf, (int) count);
-  return count;
-}
-
-TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
-{
-  (void) fhdl;
-  return SEGGER_RTT_Read(0, buf, count);
-}
-#endif
-
-#elif defined(LOGGER_SWO)
-// Logging with SWO for ARM Cortex
-
-#include "board_mcu.h"
-
-TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count)
-{
-  (void) fhdl;
-  uint8_t const* buf8 = (uint8_t const*) buf;
-  for(size_t i=0; i<count; i++)
-  {
-    ITM_SendChar(buf8[i]);
-  }
-  return count;
-}
-
-TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
-{
-  (void) fhdl;
-  return 0;
-}
-
-#else
-
-// Default logging with on-board UART
-TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count)
-{
-  (void) fhdl;
-  return board_uart_write(buf, count);
-}
-
-TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
-{
-  (void) fhdl;
-  return board_uart_read((uint8_t*) buf, count);
-}
-
-#endif
diff --git a/tinyusb/hw/bsp/board.h b/tinyusb/hw/bsp/board.h
deleted file mode 100755
index 782e0939..00000000
--- a/tinyusb/hw/bsp/board.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-/** \ingroup group_demo
- * \defgroup group_board Boards Abstraction Layer
- *  @{ */
-
-#ifndef _BSP_BOARD_H_
-#define _BSP_BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "ansi_escape.h"
-#include "tusb.h"
-
-#define CFG_BOARD_UART_BAUDRATE    115200
-
-//--------------------------------------------------------------------+
-// Board Porting API
-// For simplicity, only one LED and one Button are used
-//--------------------------------------------------------------------+
-
-// Initialize on-board peripherals : led, button, uart and USB
-void board_init(void);
-
-// Turn LED on or off
-void board_led_write(bool state);
-
-// Control led pattern using phase duration in ms.
-// For each phase, LED is toggle then repeated, board_led_task() is required to be called
-//void board_led_pattern(uint32_t const phase_ms[], uint8_t count);
-
-// Get the current state of button
-// a '1' means active (pressed), a '0' means inactive.
-uint32_t board_button_read(void);
-
-// Get characters from UART
-int board_uart_read(uint8_t* buf, int len);
-
-// Send characters to UART
-int board_uart_write(void const * buf, int len);
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // Get current milliseconds, must be implemented when no RTOS is used
-  uint32_t board_millis(void);
-
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  static inline uint32_t board_millis(void)
-  {
-    return ( ( ((uint64_t) xTaskGetTickCount()) * 1000) / configTICK_RATE_HZ );
-  }
-
-#elif CFG_TUSB_OS == OPT_OS_MYNEWT
-  static inline uint32_t board_millis(void)
-  {
-    return os_time_ticks_to_ms32( os_time_get() );
-  }
-
-#elif CFG_TUSB_OS == OPT_OS_PICO
-  #include "pico/time.h"
-  static inline uint32_t board_millis(void)
-  {
-    return to_ms_since_boot(get_absolute_time());
-  }
-
-#elif CFG_TUSB_OS == OPT_OS_RTTHREAD
-  static inline uint32_t board_millis(void)
-  {
-    return (((uint64_t)rt_tick_get()) * 1000 / RT_TICK_PER_SECOND);
-  }
-
-#else
-  #error "board_millis() is not implemented for this OS"
-#endif
-
-//--------------------------------------------------------------------+
-// Helper functions
-//--------------------------------------------------------------------+
-static inline void board_led_on(void)
-{
-  board_led_write(true);
-}
-
-static inline void board_led_off(void)
-{
-  board_led_write(false);
-}
-
-// TODO remove
-static inline void board_delay(uint32_t ms)
-{
-  uint32_t start_ms = board_millis();
-  while (board_millis() - start_ms < ms)
-  {
-    #if TUSB_OPT_DEVICE_ENABLED
-    // take chance to run usb background
-    tud_task();
-    #endif
-  }
-}
-
-static inline int board_uart_getchar(void)
-{
-  uint8_t c;
-  return board_uart_read(&c, 1) ? (int) c : (-1);
-}
-
-static inline int board_uart_putchar(uint8_t c)
-{
-  return board_uart_write(&c, 1);
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* _BSP_BOARD_H_ */
-
-/** @} */
diff --git a/tinyusb/hw/bsp/board_mcu.h b/tinyusb/hw/bsp/board_mcu.h
deleted file mode 100755
index 8cc50c80..00000000
--- a/tinyusb/hw/bsp/board_mcu.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-
-#ifndef BOARD_MCU_H_
-#define BOARD_MCU_H_
-
-#include "tusb_option.h"
-
-//--------------------------------------------------------------------+
-// Low Level MCU header include. TinyUSB stack and example should be
-// platform independent and mostly doens't need to include this file.
-// However there are still certain situation where this file is needed:
-// - FreeRTOSConfig.h to set up correct clock and NVIC interrupts for ARM Cortex
-// - SWO logging for Cortex M with ITM_SendChar() / ITM_ReceiveChar()
-//--------------------------------------------------------------------+
-
-// Include order follows OPT_MCU_ number
-#if   CFG_TUSB_MCU == OPT_MCU_LPC11UXX   || CFG_TUSB_MCU == OPT_MCU_LPC13XX    || \
-      CFG_TUSB_MCU == OPT_MCU_LPC15XX    || CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || \
-      CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC18XX    || \
-      CFG_TUSB_MCU == OPT_MCU_LPC40XX    || CFG_TUSB_MCU == OPT_MCU_LPC43XX
-  #include "chip.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_LPC51UXX || CFG_TUSB_MCU == OPT_MCU_LPC54XXX || \
-      CFG_TUSB_MCU == OPT_MCU_LPC55XX  || CFG_TUSB_MCU == OPT_MCU_MKL25ZXX || \
-      CFG_TUSB_MCU == OPT_MCU_K32L2BXX
-  #include "fsl_device_registers.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_NRF5X
-  #include "nrf.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || \
-      CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X || \
-      CFG_TUSB_MCU == OPT_MCU_SAML22 || CFG_TUSB_MCU == OPT_MCU_SAML21
-  #include "sam.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG
-  #undef LITTLE_ENDIAN // hack to suppress "LITTLE_ENDIAN" redefined
-  #include "sam.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F0
-  #include "stm32f0xx.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F1
-  #include "stm32f1xx.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F2
-  #include "stm32f2xx.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F3
-  #include "stm32f3xx.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F4
-  #include "stm32f4xx.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F7
-  #include "stm32f7xx.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32H7
-  #include "stm32h7xx.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32L0
-  #include "stm32l0xx.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32L1
-  #include "stm32l1xx.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32L4
-  #include "stm32l4xx.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_CXD56
-  // no header needed
-
-#elif CFG_TUSB_MCU == OPT_MCU_MSP430x5xx
-  #include "msp430.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_VALENTYUSB_EPTRI
-  // no header needed
-
-#elif CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
-  #include "fsl_device_registers.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_NUC120
-  #include "NUC100Series.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_NUC121 || CFG_TUSB_MCU == OPT_MCU_NUC126
-  #include "NuMicro.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_NUC505
-  #include "NUC505Series.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_ESP32S2
-  // no header needed
-
-#elif CFG_TUSB_MCU == OPT_MCU_ESP32S3
-  // no header needed
-
-#elif CFG_TUSB_MCU == OPT_MCU_DA1469X
-  #include "DA1469xAB.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_RP2040
-  #include "pico.h"
-  
-#elif CFG_TUSB_MCU == OPT_MCU_EFM32GG || CFG_TUSB_MCU == OPT_MCU_EFM32GG11 || CFG_TUSB_MCU == OPT_MCU_EFM32GG12
-  #include "em_device.h"
-
-#elif CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X
-  // no header needed
-
-#elif CFG_TUSB_MCU == OPT_MCU_GD32VF103
-  #include "gd32vf103.h"
-
-#else
-  #error "Missing MCU header"
-#endif
-
-
-#endif /* BOARD_MCU_H_ */
diff --git a/tinyusb/hw/bsp/d5035_01/board.mk b/tinyusb/hw/bsp/d5035_01/board.mk
deleted file mode 100755
index 1d09bd3d..00000000
--- a/tinyusb/hw/bsp/d5035_01/board.mk
+++ /dev/null
@@ -1,58 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/microchip
-HWREV ?= 1
-
-CFLAGS += \
-  -mthumb \
-  -mabi=aapcs \
-  -mlong-calls \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib -nostartfiles \
-  -D__SAME51J19A__ \
-  -DCONF_CPU_FREQUENCY=80000000 \
-  -DCONF_GCLK_USB_FREQUENCY=48000000 \
-  -DCFG_TUSB_MCU=OPT_MCU_SAME5X \
-  -DD5035_01=1 \
-  -DBOARD_NAME="\"D5035-01\"" \
-  -DSVC_Handler=SVCall_Handler \
-  -DHWREV=$(HWREV)
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/same51j19a_flash.ld
-
-SRC_C += \
-  src/portable/microchip/samd/dcd_samd.c \
-  hw/mcu/microchip/same51/gcc/gcc/startup_same51.c \
-  hw/mcu/microchip/same51/gcc/system_same51.c
-
-ifdef SYSCALLS
-ifneq ($(SYSCALLS),0)
-  SRC_C += hw/mcu/microchip/same51/hal/utils/src/utils_syscalls.c
-endif
-endif
-
-ifdef LOG
-ifneq ($(LOG),0)
-  SRC_C += hw/mcu/microchip/same51/hal/utils/src/utils_syscalls.c
-endif
-endif
-
-INC += \
-	$(TOP)/hw/mcu/microchip/same51/ \
-	$(TOP)/hw/mcu/microchip/same51/config \
-	$(TOP)/hw/mcu/microchip/same51/include \
-	$(TOP)/hw/mcu/microchip/same51/hal/include \
-	$(TOP)/hw/mcu/microchip/same51/hal/utils/include \
-	$(TOP)/hw/mcu/microchip/same51/hpl/port \
-	$(TOP)/hw/mcu/microchip/same51/hri \
-	$(TOP)/hw/mcu/microchip/same51/CMSIS/Include
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAME51J19
-
-# flash using jlink
-flash: flash-jlink
diff --git a/tinyusb/hw/bsp/d5035_01/d5035_01.c b/tinyusb/hw/bsp/d5035_01/d5035_01.c
deleted file mode 100755
index 5685ff16..00000000
--- a/tinyusb/hw/bsp/d5035_01/d5035_01.c
+++ /dev/null
@@ -1,353 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2020 Jean Gressmann <jean@0x42.de>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- */
-
-#include <sam.h>
-#include "bsp/board.h"
-
-#include <hal/include/hal_gpio.h>
-
-#if CONF_CPU_FREQUENCY != 80000000
-#	error "CONF_CPU_FREQUENCY" must 80000000
-#endif
-
-#if CONF_GCLK_USB_FREQUENCY != 48000000
-#	error "CONF_GCLK_USB_FREQUENCY" must 48000000
-#endif
-
-#if !defined(HWREV)
-#	error Define "HWREV"
-#endif
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_0_Handler (void)
-{
-	tud_int_handler(0);
-}
-
-void USB_1_Handler (void)
-{
-	tud_int_handler(0);
-}
-
-void USB_2_Handler (void)
-{
-	tud_int_handler(0);
-}
-
-void USB_3_Handler (void)
-{
-	tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-#define LED_PIN PIN_PA02
-
-#if HWREV < 3
-# define BOARD_SERCOM SERCOM5
-#else
-# define BOARD_SERCOM SERCOM0
-#endif
-
-static inline void init_clock(void)
-{
-	/* AUTOWS is enabled by default in REG_NVMCTRL_CTRLA - no need to change the number of wait states when changing the core clock */
-#if HWREV == 1
-	/* configure XOSC1 for a 16MHz crystal connected to XIN1/XOUT1 */
-	OSCCTRL->XOSCCTRL[1].reg =
-		OSCCTRL_XOSCCTRL_STARTUP(6) |    // 1,953 ms
-		OSCCTRL_XOSCCTRL_RUNSTDBY |
-		OSCCTRL_XOSCCTRL_ENALC |
-		OSCCTRL_XOSCCTRL_IMULT(4) |
-		OSCCTRL_XOSCCTRL_IPTAT(3) |
-		OSCCTRL_XOSCCTRL_XTALEN |
-		OSCCTRL_XOSCCTRL_ENABLE;
-	while(0 == OSCCTRL->STATUS.bit.XOSCRDY1);
-
-	OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(3) | OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val); /* pre-scaler = 8, input = XOSC1 */
-	OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(39); /* multiply by 40 -> 80 MHz */
-	OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
-	while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL0 to be ready */
-
-	OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(7) | OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val); /* pre-scaler = 16, input = XOSC1 */
-	OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(47); /* multiply by 48 -> 48 MHz */
-	OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
-	while(0 == OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL1 to be ready */
-#else // HWREV >= 1
-	/* configure XOSC0 for a 16MHz crystal connected to XIN0/XOUT0 */
-	OSCCTRL->XOSCCTRL[0].reg =
-		OSCCTRL_XOSCCTRL_STARTUP(6) |    // 1,953 ms
-		OSCCTRL_XOSCCTRL_RUNSTDBY |
-		OSCCTRL_XOSCCTRL_ENALC |
-		OSCCTRL_XOSCCTRL_IMULT(4) |
-		OSCCTRL_XOSCCTRL_IPTAT(3) |
-		OSCCTRL_XOSCCTRL_XTALEN |
-		OSCCTRL_XOSCCTRL_ENABLE;
-	while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
-
-	OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(3) | OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val); /* pre-scaler = 8, input = XOSC1 */
-	OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(39); /* multiply by 40 -> 80 MHz */
-	OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
-	while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL0 to be ready */
-
-	OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(7) | OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val); /* pre-scaler = 16, input = XOSC1 */
-	OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(47); /* multiply by 48 -> 48 MHz */
-	OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
-	while(0 == OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL1 to be ready */
-#endif // HWREV
-
-	/* configure clock-generator 0 to use DPLL0 as source -> GCLK0 is used for the core */
-	GCLK->GENCTRL[0].reg =
-		GCLK_GENCTRL_DIV(0) |
-		GCLK_GENCTRL_RUNSTDBY |
-		GCLK_GENCTRL_GENEN |
-		GCLK_GENCTRL_SRC_DPLL0 |  /* DPLL0 */
-		GCLK_GENCTRL_IDC ;
-	while(1 == GCLK->SYNCBUSY.bit.GENCTRL0); /* wait for the synchronization between clock domains to be complete */
-
-	/* configure clock-generator 1 to use DPLL1 as source -> for use with some peripheral */
-	GCLK->GENCTRL[1].reg =
-		GCLK_GENCTRL_DIV(0) |
-		GCLK_GENCTRL_RUNSTDBY |
-		GCLK_GENCTRL_GENEN |
-		GCLK_GENCTRL_SRC_DPLL1 |
-		GCLK_GENCTRL_IDC ;
-	while(1 == GCLK->SYNCBUSY.bit.GENCTRL1); /* wait for the synchronization between clock domains to be complete */
-
-	/* configure clock-generator 2 to use DPLL0 as source -> for use with SERCOM */
-	GCLK->GENCTRL[2].reg =
-		GCLK_GENCTRL_DIV(1) |	/* 80MHz */
-		GCLK_GENCTRL_RUNSTDBY |
-		GCLK_GENCTRL_GENEN |
-		GCLK_GENCTRL_SRC_DPLL0 |
-		GCLK_GENCTRL_IDC ;
-	while(1 == GCLK->SYNCBUSY.bit.GENCTRL2); /* wait for the synchronization between clock domains to be complete */
-}
-
-static inline void uart_init(void)
-{
-#if HWREV < 3
-	/* configure SERCOM5 on PB02 */
-	PORT->Group[1].WRCONFIG.reg =
-		PORT_WRCONFIG_WRPINCFG |
-		PORT_WRCONFIG_WRPMUX |
-		PORT_WRCONFIG_PMUX(3) |    /* function D */
-		PORT_WRCONFIG_DRVSTR |
-		PORT_WRCONFIG_PINMASK(0x0004) | /* PB02 */
-		PORT_WRCONFIG_PMUXEN;
-
-	MCLK->APBDMASK.bit.SERCOM5_ = 1;
-	GCLK->PCHCTRL[SERCOM5_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK2 | GCLK_PCHCTRL_CHEN; /* setup SERCOM to use GLCK2 -> 80MHz */
-
-	SERCOM5->USART.CTRLA.reg = 0x00; /* disable SERCOM -> enable config */
-	while(SERCOM5->USART.SYNCBUSY.bit.ENABLE);
-
-	SERCOM5->USART.CTRLA.reg  =  /* CMODE = 0 -> async, SAMPA = 0, FORM = 0 -> USART frame, SMPR = 0 -> arithmetic baud rate */
-		SERCOM_USART_CTRLA_SAMPR(1) | /* 0 = 16x / arithmetic baud rate, 1 = 16x / fractional baud rate */
-//    SERCOM_USART_CTRLA_FORM(0) | /* 0 = USART Frame, 2 = LIN Master */
-		SERCOM_USART_CTRLA_DORD | /* LSB first */
-		SERCOM_USART_CTRLA_MODE(1) | /* 0 = Asynchronous, 1 = USART with internal clock */
-		SERCOM_USART_CTRLA_RXPO(1) | /* SERCOM PAD[1] is used for data reception */
-		SERCOM_USART_CTRLA_TXPO(0); /* SERCOM PAD[0] is used for data transmission */
-
-	SERCOM5->USART.CTRLB.reg = /* RXEM = 0 -> receiver disabled, LINCMD = 0 -> normal USART transmission, SFDE = 0 -> start-of-frame detection disabled, SBMODE = 0 -> one stop bit, CHSIZE = 0 -> 8 bits */
-		SERCOM_USART_CTRLB_TXEN; /* transmitter enabled */
-	SERCOM5->USART.CTRLC.reg = 0x00;
-	// 21.701388889 @ baud rate of 230400 bit/s, table 33-2, p 918 of DS60001507E
-	SERCOM5->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(7) | SERCOM_USART_BAUD_FRAC_BAUD(21);
-
-//  SERCOM5->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC;
-	SERCOM5->SPI.CTRLA.bit.ENABLE = 1; /* activate SERCOM */
-	while(SERCOM5->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */
-#else
-/* configure SERCOM0 on PA08 */
-	PORT->Group[0].WRCONFIG.reg =
-		PORT_WRCONFIG_WRPINCFG |
-		PORT_WRCONFIG_WRPMUX |
-		PORT_WRCONFIG_PMUX(2) |    /* function C */
-		PORT_WRCONFIG_DRVSTR |
-		PORT_WRCONFIG_PINMASK(0x0100) | /* PA08 */
-		PORT_WRCONFIG_PMUXEN;
-
-	MCLK->APBAMASK.bit.SERCOM0_ = 1;
-	GCLK->PCHCTRL[SERCOM0_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK2 | GCLK_PCHCTRL_CHEN; /* setup SERCOM to use GLCK2 -> 80MHz */
-
-	SERCOM0->USART.CTRLA.reg = 0x00; /* disable SERCOM -> enable config */
-	while(SERCOM0->USART.SYNCBUSY.bit.ENABLE);
-
-	SERCOM0->USART.CTRLA.reg  =  /* CMODE = 0 -> async, SAMPA = 0, FORM = 0 -> USART frame, SMPR = 0 -> arithmetic baud rate */
-		SERCOM_USART_CTRLA_SAMPR(1) | /* 0 = 16x / arithmetic baud rate, 1 = 16x / fractional baud rate */
-//    SERCOM_USART_CTRLA_FORM(0) | /* 0 = USART Frame, 2 = LIN Master */
-		SERCOM_USART_CTRLA_DORD | /* LSB first */
-		SERCOM_USART_CTRLA_MODE(1) | /* 0 = Asynchronous, 1 = USART with internal clock */
-		SERCOM_USART_CTRLA_RXPO(1) | /* SERCOM PAD[1] is used for data reception */
-		SERCOM_USART_CTRLA_TXPO(0); /* SERCOM PAD[0] is used for data transmission */
-
-	SERCOM0->USART.CTRLB.reg = /* RXEM = 0 -> receiver disabled, LINCMD = 0 -> normal USART transmission, SFDE = 0 -> start-of-frame detection disabled, SBMODE = 0 -> one stop bit, CHSIZE = 0 -> 8 bits */
-		SERCOM_USART_CTRLB_TXEN; /* transmitter enabled */
-	SERCOM0->USART.CTRLC.reg = 0x00;
-	// 21.701388889 @ baud rate of 230400 bit/s, table 33-2, p 918 of DS60001507E
-	SERCOM0->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(7) | SERCOM_USART_BAUD_FRAC_BAUD(21);
-
-//  SERCOM0->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC;
-	SERCOM0->SPI.CTRLA.bit.ENABLE = 1; /* activate SERCOM */
-	while(SERCOM0->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */
-#endif
-}
-
-static inline void uart_send_buffer(uint8_t const *text, size_t len)
-{
-	for (size_t i = 0; i < len; ++i) {
-		BOARD_SERCOM->USART.DATA.reg = text[i];
-		while((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) == 0);
-	}
-}
-
-static inline void uart_send_str(const char* text)
-{
-	while (*text) {
-		BOARD_SERCOM->USART.DATA.reg = *text++;
-		while((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) == 0);
-	}
-}
-
-
-void board_init(void)
-{
-	init_clock();
-
-	SystemCoreClock = CONF_CPU_FREQUENCY;
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-	SysTick_Config(CONF_CPU_FREQUENCY / 1000);
-#endif
-
-	uart_init();
-#if CFG_TUSB_DEBUG >= 2
-	uart_send_str(BOARD_NAME " UART initialized\n");
-	tu_printf(BOARD_NAME " reset cause %#02x\n", RSTC->RCAUSE.reg);
-#endif
-
-	// Led init
-	gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
-	gpio_set_pin_level(LED_PIN, 0);
-
-#if CFG_TUSB_DEBUG >= 2
-	uart_send_str(BOARD_NAME " LED pin configured\n");
-#endif
-
-#if CFG_TUSB_OS == OPT_OS_FREERTOS
-	// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-	NVIC_SetPriority(USB_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-	NVIC_SetPriority(USB_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-	NVIC_SetPriority(USB_2_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-	NVIC_SetPriority(USB_3_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-#endif
-
-
-#if TUSB_OPT_DEVICE_ENABLED
-#if CFG_TUSB_DEBUG >= 2
-	uart_send_str(BOARD_NAME " USB device enabled\n");
-#endif
-
-	/* USB clock init
-	 * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock
-	 * for low speed and full speed operation. */
-	hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN);
-	hri_mclk_set_AHBMASK_USB_bit(MCLK);
-	hri_mclk_set_APBBMASK_USB_bit(MCLK);
-
-	// USB pin init
-	gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT);
-	gpio_set_pin_level(PIN_PA24, false);
-	gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF);
-	gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT);
-	gpio_set_pin_level(PIN_PA25, false);
-	gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF);
-
-	gpio_set_pin_function(PIN_PA24, PINMUX_PA24H_USB_DM);
-	gpio_set_pin_function(PIN_PA25, PINMUX_PA25H_USB_DP);
-
-
-#if CFG_TUSB_DEBUG >= 2
-	uart_send_str(BOARD_NAME " USB device configured\n");
-#endif
-#endif
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-	gpio_set_pin_level(LED_PIN, state);
-}
-
-uint32_t board_button_read(void)
-{
-	// this board has no button
-	return 0;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-	(void) buf; (void) len;
-	return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-	if (len < 0) {
-		uart_send_str(buf);
-	} else {
-		uart_send_buffer(buf, len);
-	}
-	return len;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-
-void SysTick_Handler(void)
-{
-	system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-	return system_ticks;
-}
-#endif
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
-}
diff --git a/tinyusb/hw/bsp/d5035_01/same51j19a_flash.ld b/tinyusb/hw/bsp/d5035_01/same51j19a_flash.ld
deleted file mode 100755
index 328d1c72..00000000
--- a/tinyusb/hw/bsp/d5035_01/same51j19a_flash.ld
+++ /dev/null
@@ -1,163 +0,0 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAME51J19A
- *
- * Copyright (c) 2019 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-SEARCH_DIR(.)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00080000
-  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
-  bkupram  (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
-  qspi     (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
-}
-
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
-
-/* Section Definitions */
-SECTIONS
-{
-    .text :
-    {
-        . = ALIGN(4);
-        _sfixed = .;
-        KEEP(*(.vectors .vectors.*))
-        *(.text .text.* .gnu.linkonce.t.*)
-        *(.glue_7t) *(.glue_7)
-        *(.rodata .rodata* .gnu.linkonce.r.*)
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-
-        /* Support C constructors, and C destructors in both user code
-           and the C library. This also provides support for C++ code. */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-
-        . = ALIGN(4);
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-
-        . = ALIGN(4);
-        KEEP(*(.fini))
-
-        . = ALIGN(4);
-        __fini_array_start = .;
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        __fini_array_end = .;
-
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-
-        . = ALIGN(4);
-        _efixed = .;            /* End of text section */
-    } > rom
-
-    /* .ARM.exidx is sorted, so has to go in its own output section.  */
-    PROVIDE_HIDDEN (__exidx_start = .);
-    .ARM.exidx :
-    {
-      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > rom
-    PROVIDE_HIDDEN (__exidx_end = .);
-
-    . = ALIGN(4);
-    _etext = .;
-
-    .relocate : AT (_etext)
-    {
-        . = ALIGN(4);
-        _srelocate = .;
-        *(.ramfunc .ramfunc.*);
-        *(.data .data.*);
-        . = ALIGN(4);
-        _erelocate = .;
-    } > ram
-
-    .bkupram (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sbkupram = .;
-        *(.bkupram .bkupram.*);
-        . = ALIGN(8);
-        _ebkupram = .;
-    } > bkupram
-
-    .qspi (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sqspi = .;
-        *(.qspi .qspi.*);
-        . = ALIGN(8);
-        _eqspi = .;
-    } > qspi
-
-    /* .bss section which is used for uninitialized data */
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        _sbss = . ;
-        _szero = .;
-        *(.bss .bss.*)
-        *(COMMON)
-        . = ALIGN(4);
-        _ebss = . ;
-        _ezero = .;
-    } > ram
-
-    /* stack section */
-    .stack (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sstack = .;
-        . = . + STACK_SIZE;
-        . = ALIGN(8);
-        _estack = .;
-    } > ram
-
-    . = ALIGN(4);
-    _end = . ;
-}
diff --git a/tinyusb/hw/bsp/da14695_dk_usb/board.mk b/tinyusb/hw/bsp/da14695_dk_usb/board.mk
deleted file mode 100755
index e969c79c..00000000
--- a/tinyusb/hw/bsp/da14695_dk_usb/board.mk
+++ /dev/null
@@ -1,55 +0,0 @@
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mthumb-interwork \
-  -mabi=aapcs \
-  -mcpu=cortex-m33+nodsp \
-  -mfloat-abi=hard \
-  -mfpu=fpv5-sp-d16 \
-  -nostdlib \
-  -DCORE_M33 \
-  -DCFG_TUSB_MCU=OPT_MCU_DA1469X \
-  -DCFG_TUD_ENDPOINT0_SIZE=8\
-
-MCU_FAMILY_DIR = hw/mcu/dialog/da1469x
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/da1469x.ld
-
-# While this is for da1469x chip, there is chance that da1468x chip family will also work
-SRC_C += \
-	src/portable/dialog/da146xx/dcd_da146xx.c \
-	$(MCU_FAMILY_DIR)/src/system_da1469x.c \
-	$(MCU_FAMILY_DIR)/src/da1469x_clock.c \
-	$(MCU_FAMILY_DIR)/src/hal_gpio.c \
-
-SRC_S += hw/bsp/$(BOARD)/gcc_startup_da1469x.S
-
-INC += \
-	$(TOP)/hw/bsp/$(BOARD) \
-	$(TOP)/$(MCU_FAMILY_DIR)/include \
-	$(TOP)/$(MCU_FAMILY_DIR)/SDK_10.0.8.105/sdk/bsp/include
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM33_NTZ/non_secure
-
-# For flash-jlink target
-JLINK_DEVICE = DA14695
-
-# flash using jlink but with some twists
-flash: flash-dialog
-
-flash-dialog: $(BUILD)/$(PROJECT).bin
-	@echo '#define SW_VERSION "v_1.0.0.1"' >$(BUILD)/version.h
-	@echo '#define SW_VERSION_DATE "'`date +"%Y-%m-%d %H:%M"`'"' >>$(BUILD)/version.h
-	mkimage da1469x $(BUILD)/$(PROJECT).bin $(BUILD)/version.h $^.img
-	cp $(TOP)/hw/bsp/$(BOARD)/product_header.dump $(BUILD)/$(BOARD)-image.bin
-	cat $^.img >> $(BUILD)/$(BOARD)-image.bin
-	@echo r > $(BUILD)/$(BOARD).jlink
-	@echo halt >> $(BUILD)/$(BOARD).jlink
-	@echo loadfile $(BUILD)/$(BOARD)-image.bin 0x16000000 >> $(BUILD)/$(BOARD).jlink
-	@echo r >> $(BUILD)/$(BOARD).jlink
-	@echo go >> $(BUILD)/$(BOARD).jlink
-	@echo exit >> $(BUILD)/$(BOARD).jlink
-	$(JLINKEXE) -device $(JLINK_DEVICE) -if $(JLINK_IF) -JTAGConf -1,-1 -speed auto -CommandFile $(BUILD)/$(BOARD).jlink
-
diff --git a/tinyusb/hw/bsp/da14695_dk_usb/da14695_dk_usb.c b/tinyusb/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
deleted file mode 100755
index e7c7ae36..00000000
--- a/tinyusb/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020 Jerzy Kasenberg
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "bsp/board.h"
-#include <hal/hal_gpio.h>
-#include <mcu/mcu.h>
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-#define LED_PIN         33 // P1.1
-#define LED_STATE_ON    1
-#define LED_STATE_OFF   (1-LED_STATE_ON)
-
-#define BUTTON_PIN      6
-
-void UnhandledIRQ(void)
-{
-  CRG_TOP->SYS_CTRL_REG = 0x80;
-  __BKPT(1);
-  while(1);
-}
-
-void board_init(void)
-{
-  // LED
-  hal_gpio_init_out(LED_PIN, LED_STATE_ON);
-
-  hal_gpio_init_out(1, 0);
-  hal_gpio_init_out(2, 0);
-  hal_gpio_init_out(3, 0);
-  hal_gpio_init_out(4, 0);
-  hal_gpio_init_out(5, 0);
-
-  // Button
-  hal_gpio_init_in(BUTTON_PIN, HAL_GPIO_PULL_NONE);
-
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-
-  NVIC_SetPriority(USB_IRQn, 2);
-
-  /* Setup USB IRQ */
-  NVIC_SetPriority(USB_IRQn, 2);
-  NVIC_EnableIRQ(USB_IRQn);
-
-  /* Use PLL96 / 2 clock not HCLK */
-  CRG_TOP->CLK_CTRL_REG &= ~CRG_TOP_CLK_CTRL_REG_USB_CLK_SRC_Msk;
-
-  mcu_gpio_set_pin_function(14, MCU_GPIO_MODE_INPUT, MCU_GPIO_FUNC_USB);
-  mcu_gpio_set_pin_function(15, MCU_GPIO_MODE_INPUT, MCU_GPIO_FUNC_USB);
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  hal_gpio_write(LED_PIN, state ? LED_STATE_ON : LED_STATE_OFF);
-}
-
-uint32_t board_button_read(void)
-{
-  // button is active LOW
-  return hal_gpio_read(BUTTON_PIN) ^ 1;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void)buf;
-  (void)len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void)buf;
-  (void)len;
-
-  return 0;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/tinyusb/hw/bsp/da14695_dk_usb/da1469x.ld b/tinyusb/hw/bsp/da14695_dk_usb/da1469x.ld
deleted file mode 100755
index 96507d6e..00000000
--- a/tinyusb/hw/bsp/da14695_dk_usb/da1469x.ld
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements.  See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership.  The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License.  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied.  See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-MEMORY
-{
-    /*
-     * Flash is remapped at 0x0 by 1st stage bootloader, but this is done with
-     * an offset derived from image header thus it is safer to use remapped
-     * address space at 0x0 instead of QSPI_M address space at 0x16000000.
-     * Bootloader partition is 32K, but 9K is currently reserved for product
-     * header (8K) and image header (1K).
-     * First 512 bytes of SYSRAM are remapped at 0x0 and used as ISR vector
-     * (there's no need to reallocate ISR vector) and thus cannot be used by
-     * application.
-     */
-
-    FLASH (r)  : ORIGIN = (0x00000000), LENGTH = (1024 * 1024)
-    RAM (rw)   : ORIGIN = (0x20000000), LENGTH = (512 * 1024)
-}
-
-OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __HeapBase
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   __bssnz_start__
- *   __bssnz_end__
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
-    __text = .;
-
-    .text :
-    {
-        __isr_vector_start = .;
-        KEEP(*(.isr_vector))
-        /* ISR vector shall have exactly 512 bytes */
-        . = __isr_vector_start + 0x200;
-        __isr_vector_end = .;
-
-        *(.text)
-        *(.text.*)
-
-        *(.libcmac.rom)
-
-        KEEP(*(.init))
-        KEEP(*(.fini))
-
-        /* .ctors */
-        *crtbegin.o(.ctors)
-        *crtbegin?.o(.ctors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-        *(SORT(.ctors.*))
-        *(.ctors)
-
-        /* .dtors */
-        *crtbegin.o(.dtors)
-        *crtbegin?.o(.dtors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
-        *(SORT(.dtors.*))
-        *(.dtors)
-
-        *(.rodata*)
-
-        *(.eh_frame*)
-        . = ALIGN(4);
-    } > FLASH
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-        . = ALIGN(4);
-    } > FLASH
-
-    __exidx_start = .;
-    .ARM :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        . = ALIGN(4);
-    } > FLASH
-    __exidx_end = .;
-
-    .intvect :
-    {
-        . = ALIGN(4);
-        __intvect_start__ = .;
-        . = . + (__isr_vector_end - __isr_vector_start);
-        . = ALIGN(4);
-    } > RAM
-
-    .sleep_state (NOLOAD) :
-    {
-        . = ALIGN(4);
-        *(sleep_state)
-    } > RAM
-
-    /* This section will be zeroed by RTT package init */
-    .rtt (NOLOAD):
-    {
-        . = ALIGN(4);
-        *(.rtt)
-        . = ALIGN(4);
-    } > RAM
-
-    __text_ram_addr = LOADADDR(.text_ram);
-
-    .text_ram :
-    {
-        . = ALIGN(4);
-        __text_ram_start__ = .;
-        *(.text_ram*)
-        . = ALIGN(4);
-        __text_ram_end__ = .;
-    } > RAM AT > FLASH
-
-    __etext = LOADADDR(.data);
-
-    .data :
-    {
-        __data_start__ = .;
-        *(vtable)
-        *(.data*)
-
-        . = ALIGN(4);
-        /* preinit data */
-        PROVIDE_HIDDEN (__preinit_array_start = .);
-        *(.preinit_array)
-        PROVIDE_HIDDEN (__preinit_array_end = .);
-
-        . = ALIGN(4);
-        /* init data */
-        PROVIDE_HIDDEN (__init_array_start = .);
-        *(SORT(.init_array.*))
-        *(.init_array)
-        PROVIDE_HIDDEN (__init_array_end = .);
-
-
-        . = ALIGN(4);
-        /* finit data */
-        PROVIDE_HIDDEN (__fini_array_start = .);
-        *(SORT(.fini_array.*))
-        *(.fini_array)
-        PROVIDE_HIDDEN (__fini_array_end = .);
-
-        *(.jcr)
-        . = ALIGN(4);
-        /* All data end */
-        __data_end__ = .;
-    } > RAM AT > FLASH
-
-    .bssnz :
-    {
-        . = ALIGN(4);
-        __bssnz_start__ = .;
-        *(.bss.core.nz*)
-        . = ALIGN(4);
-        __bssnz_end__ = .;
-    } > RAM
-
-    .bss :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > RAM
-
-    .cmac (NOLOAD) :
-    {
-        . = ALIGN(0x400);
-        *(.libcmac.ram)
-    } > RAM
-
-    /* Heap starts after BSS */
-    . = ALIGN(8);
-    __HeapBase = .;
-
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (COPY):
-    {
-        *(.stack*)
-    } > RAM
-
-    _ram_start = ORIGIN(RAM);
-
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    PROVIDE(__stack = __StackTop);
-
-    /* Top of head is the bottom of the stack */
-    __HeapLimit = __StackLimit;
-    end = __HeapLimit;
-
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__HeapBase <= __HeapLimit, "region RAM overflowed with stack")
-
-    /* Check that intvect is at the beginning of RAM */
-    ASSERT(__intvect_start__ == ORIGIN(RAM), "intvect is not at beginning of RAM")
-}
-
diff --git a/tinyusb/hw/bsp/da14695_dk_usb/gcc_startup_da1469x.S b/tinyusb/hw/bsp/da14695_dk_usb/gcc_startup_da1469x.S
deleted file mode 100755
index d47fbcd9..00000000
--- a/tinyusb/hw/bsp/da14695_dk_usb/gcc_startup_da1469x.S
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements.  See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership.  The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License.  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied.  See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
- #include "syscfg/syscfg.h"
-
-    .syntax unified
-    .arch   armv7-m
-
-    .section .stack
-    .align  3
-#ifdef __STACK_SIZE
-    .equ    Stack_Size, __STACK_SIZE
-#else
-    .equ    Stack_Size, 0xC00
-#endif
-    .equ    SYS_CTRL_REG,       0x50000024
-    .equ    CACHE_FLASH_REG,    0x100C0040
-    .equ    RESET_STAT_REG,     0x500000BC
-
-    .globl  __StackTop
-    .globl  __StackLimit
-__StackLimit:
-    .space  Stack_Size
-    .size   __StackLimit, . - __StackLimit
-__StackTop:
-    .size   __StackTop, . - __StackTop
-
-    .section .heap
-    .align  3
-#ifdef __HEAP_SIZE
-    .equ    Heap_Size, __HEAP_SIZE
-#else
-    .equ    Heap_Size, 0
-#endif
-    .globl  __HeapBase
-    .globl  __HeapLimit
-__HeapBase:
-    .if     Heap_Size
-    .space  Heap_Size
-    .endif
-    .size   __HeapBase, . - __HeapBase
-__HeapLimit:
-    .size   __HeapLimit, . - __HeapLimit
-
-    .section .isr_vector
-    .align 2
-    .globl  __isr_vector
-__isr_vector:
-    .long   __StackTop
-    .long   Reset_Handler
-    /* Cortex-M33 interrupts */
-    .long   NMI_Handler
-    .long   HardFault_Handler
-    .long   MemoryManagement_Handler
-    .long   BusFault_Handler
-    .long   UsageFault_Handler
-    .long   SecureFault_Handler
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   SVC_Handler
-    .long   DebugMonitor_Handler
-    .long   0                       /* Reserved */
-    .long   PendSV_Handler
-    .long   SysTick_Handler
-    /* DA1469x interrupts */
-    .long   SENSOR_NODE_IRQHandler
-    .long   DMA_IRQHandler
-    .long   CHARGER_STATE_IRQHandler
-    .long   CHARGER_ERROR_IRQHandler
-    .long   CMAC2SYS_IRQHandler
-    .long   UART_IRQHandler
-    .long   UART2_IRQHandler
-    .long   UART3_IRQHandler
-    .long   I2C_IRQHandler
-    .long   I2C2_IRQHandler
-    .long   SPI_IRQHandler
-    .long   SPI2_IRQHandler
-    .long   PCM_IRQHandler
-    .long   SRC_IN_IRQHandler
-    .long   SRC_OUT_IRQHandler
-    .long   USB_IRQHandler
-    .long   TIMER_IRQHandler
-    .long   TIMER2_IRQHandler
-    .long   RTC_IRQHandler
-    .long   KEY_WKUP_GPIO_IRQHandler
-    .long   PDC_IRQHandler
-    .long   VBUS_IRQHandler
-    .long   MRM_IRQHandler
-    .long   MOTOR_CONTROLLER_IRQHandler
-    .long   TRNG_IRQHandler
-    .long   DCDC_IRQHandler
-    .long   XTAL32M_RDY_IRQHandler
-    .long   ADC_IRQHandler
-    .long   ADC2_IRQHandler
-    .long   CRYPTO_IRQHandler
-    .long   CAPTIMER1_IRQHandler
-    .long   RFDIAG_IRQHandler
-    .long   LCD_CONTROLLER_IRQHandler
-    .long   PLL_LOCK_IRQHandler
-    .long   TIMER3_IRQHandler
-    .long   TIMER4_IRQHandler
-    .long   LRA_IRQHandler
-    .long   RTC_EVENT_IRQHandler
-    .long   GPIO_P0_IRQHandler
-    .long   GPIO_P1_IRQHandler
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .size   __isr_vector, . - __isr_vector
-
-    .text
-    .thumb
-    .thumb_func
-    .align 2
-    .globl Reset_Handler
-    .type  Reset_Handler, %function
-Reset_Handler:
- /* Make sure interrupt vector is remapped at 0x0 */
-    ldr     r1, =SYS_CTRL_REG
-    ldrh    r2, [r1, #0]
-    orrs    r2, r2, #8
-    strh    r2, [r1, #0]
-
-#if !MYNEWT_VAL(RAM_RESIDENT)
-/*
- * Flash is remapped at 0x0 with an offset, i.e. 0x0 does not correspond to
- * 0x16000000 but to start of an image on flash. This is calculated from product
- * header by 1st state bootloader and configured in CACHE_FLASH_REG. We need to
- * retrieve proper offset value for calculations later.
- */
-    ldr     r1, =CACHE_FLASH_REG
-    ldr     r4, [r1, #0]
-    mov     r2, r4
-    mov     r3, #0xFFFF
-    bic     r4, r4, r3      /* CACHE_FLASH_REG[FLASH_REGION_BASE] */
-    mov     r3, #0xFFF0
-    and     r2, r2, r3      /* CACHE_FLASH_REG[FLASH_REGION_OFFSET] */
-    lsr     r2, r2, #2
-    orr     r4, r4, r2
-
-/* Copy ISR vector from flash to RAM */
-    ldr     r1, =__isr_vector_start     /* src ptr */
-    ldr     r2, =__isr_vector_end       /* src end */
-    ldr     r3, =__intvect_start__      /* dst ptr */
-/* Make sure we copy from QSPIC address range, not from remapped range */
-    cmp     r1, r4
-    itt     lt
-    addlt   r1, r1, r4
-    addlt   r2, r2, r4
-.loop_isr_copy:
-    cmp     r1, r2
-    ittt    lt
-    ldrlt   r0, [r1], #4
-    strlt   r0, [r3], #4
-    blt     .loop_isr_copy
-
-/* Copy QSPI code from flash to RAM */
-    ldr     r1, =__text_ram_addr        /* src ptr */
-    ldr     r2, =__text_ram_start__     /* ptr */
-    ldr     r3, =__text_ram_end__       /* dst end */
-.loop_code_text_ram_copy:
-    cmp     r2, r3
-    ittt    lt
-    ldrlt   r0, [r1], #4
-    strlt   r0, [r2], #4
-    blt     .loop_code_text_ram_copy
-
-/* Copy data from flash to RAM */
-    ldr     r1, =__etext                /* src ptr */
-    ldr     r2, =__data_start__         /* dst ptr */
-    ldr     r3, =__data_end__           /* dst end */
-.loop_data_copy:
-    cmp     r2, r3
-    ittt    lt
-    ldrlt   r0, [r1], #4
-    strlt   r0, [r2], #4
-    blt     .loop_data_copy
-#endif
-
-/* Clear BSS */
-    movs    r0, 0
-    ldr     r1, =__bss_start__
-    ldr     r2, =__bss_end__
-.loop_bss_clear:
-    cmp     r1, r2
-    itt     lt
-    strlt   r0, [r1], #4
-    blt     .loop_bss_clear
-
-    ldr     r0, =__HeapBase
-    ldr     r1, =__HeapLimit
-/* Call static constructors */
-    bl __libc_init_array
-
-    bl      SystemInit
-    bl      main
-
-    .pool
-    .size   Reset_Handler, . - Reset_Handler
-
-/* Default interrupt handler */
-    .type   Default_Handler, %function
-Default_Handler:
-    ldr     r1, =SYS_CTRL_REG
-    ldrh    r2, [r1, #0]
-    orrs    r2, r2, #0x80   /* DEBUGGER_ENABLE */
-    strh    r2, [r1, #0]
-    b       .
-
-    .size   Default_Handler, . - Default_Handler
-
-/* Default handlers for all interrupts */
-    .macro  IRQ handler
-    .weak   \handler
-    .set    \handler, Default_Handler
-    .endm
-
-    /* Cortex-M33 interrupts */
-    IRQ  NMI_Handler
-    IRQ  HardFault_Handler
-    IRQ  MemoryManagement_Handler
-    IRQ  BusFault_Handler
-    IRQ  UsageFault_Handler
-    IRQ  SecureFault_Handler
-    IRQ  SVC_Handler
-    IRQ  DebugMonitor_Handler
-    IRQ  PendSV_Handler
-    IRQ  SysTick_Handler
-    /* DA1469x interrupts */
-    IRQ  SENSOR_NODE_IRQHandler
-    IRQ  DMA_IRQHandler
-    IRQ  CHARGER_STATE_IRQHandler
-    IRQ  CHARGER_ERROR_IRQHandler
-    IRQ  CMAC2SYS_IRQHandler
-    IRQ  UART_IRQHandler
-    IRQ  UART2_IRQHandler
-    IRQ  UART3_IRQHandler
-    IRQ  I2C_IRQHandler
-    IRQ  I2C2_IRQHandler
-    IRQ  SPI_IRQHandler
-    IRQ  SPI2_IRQHandler
-    IRQ  PCM_IRQHandler
-    IRQ  SRC_IN_IRQHandler
-    IRQ  SRC_OUT_IRQHandler
-    IRQ  USB_IRQHandler
-    IRQ  TIMER_IRQHandler
-    IRQ  TIMER2_IRQHandler
-    IRQ  RTC_IRQHandler
-    IRQ  KEY_WKUP_GPIO_IRQHandler
-    IRQ  PDC_IRQHandler
-    IRQ  VBUS_IRQHandler
-    IRQ  MRM_IRQHandler
-    IRQ  MOTOR_CONTROLLER_IRQHandler
-    IRQ  TRNG_IRQHandler
-    IRQ  DCDC_IRQHandler
-    IRQ  XTAL32M_RDY_IRQHandler
-    IRQ  ADC_IRQHandler
-    IRQ  ADC2_IRQHandler
-    IRQ  CRYPTO_IRQHandler
-    IRQ  CAPTIMER1_IRQHandler
-    IRQ  RFDIAG_IRQHandler
-    IRQ  LCD_CONTROLLER_IRQHandler
-    IRQ  PLL_LOCK_IRQHandler
-    IRQ  TIMER3_IRQHandler
-    IRQ  TIMER4_IRQHandler
-    IRQ  LRA_IRQHandler
-    IRQ  RTC_EVENT_IRQHandler
-    IRQ  GPIO_P0_IRQHandler
-    IRQ  GPIO_P1_IRQHandler
-    IRQ  RESERVED40_IRQHandler
-    IRQ  RESERVED41_IRQHandler
-    IRQ  RESERVED42_IRQHandler
-    IRQ  RESERVED43_IRQHandler
-    IRQ  RESERVED44_IRQHandler
-    IRQ  RESERVED45_IRQHandler
-    IRQ  RESERVED46_IRQHandler
-    IRQ  RESERVED47_IRQHandler
-
-.end
diff --git a/tinyusb/hw/bsp/da14695_dk_usb/product_header.dump b/tinyusb/hw/bsp/da14695_dk_usb/product_header.dump
deleted file mode 100755
index ea484224..00000000
--- a/tinyusb/hw/bsp/da14695_dk_usb/product_header.dump
+++ /dev/null
diff --git a/tinyusb/hw/bsp/da14695_dk_usb/syscfg/syscfg.h b/tinyusb/hw/bsp/da14695_dk_usb/syscfg/syscfg.h
deleted file mode 100755
index 6cbb4319..00000000
--- a/tinyusb/hw/bsp/da14695_dk_usb/syscfg/syscfg.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/**
- * This file was generated by Apache newt version: 1.9.0-dev
- */
-
-#ifndef H_MYNEWT_SYSCFG_
-#define H_MYNEWT_SYSCFG_
-
-/**
- * This macro exists to ensure code includes this header when needed.  If code
- * checks the existence of a setting directly via ifdef without including this
- * header, the setting macro will silently evaluate to 0.  In contrast, an
- * attempt to use these macros without including this header will result in a
- * compiler error.
- */
-#define MYNEWT_VAL(_name)                       MYNEWT_VAL_ ## _name
-#define MYNEWT_VAL_CHOICE(_name, _val)          MYNEWT_VAL_ ## _name ## __ ## _val
-
-#ifndef MYNEWT_VAL_RAM_RESIDENT
-#define MYNEWT_VAL_RAM_RESIDENT (0)
-#endif
-
-#ifndef MYNEWT_VAL_MCU_GPIO_MAX_IRQ
-#define MYNEWT_VAL_MCU_GPIO_MAX_IRQ (4)
-#endif
-
-#ifndef MYNEWT_VAL_MCU_GPIO_RETAINABLE_NUM
-#define MYNEWT_VAL_MCU_GPIO_RETAINABLE_NUM (-1)
-#endif
-
-#ifndef MYNEWT_VAL_MCU_CLOCK_XTAL32M_SETTLE_TIME_US
-#define MYNEWT_VAL_MCU_CLOCK_XTAL32M_SETTLE_TIME_US (2000)
-#endif
-
-#endif
diff --git a/tinyusb/hw/bsp/da1469x_dk_pro/board.mk b/tinyusb/hw/bsp/da1469x_dk_pro/board.mk
deleted file mode 100755
index 980fc422..00000000
--- a/tinyusb/hw/bsp/da1469x_dk_pro/board.mk
+++ /dev/null
@@ -1,55 +0,0 @@
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mthumb-interwork \
-  -mabi=aapcs \
-  -mcpu=cortex-m33+nodsp \
-  -mfloat-abi=hard \
-  -mfpu=fpv5-sp-d16 \
-  -nostdlib \
-  -DCORE_M33 \
-  -DCFG_TUSB_MCU=OPT_MCU_DA1469X \
-  -DCFG_TUD_ENDPOINT0_SIZE=8\
-
-MCU_FAMILY_DIR = hw/mcu/dialog/da1469x
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/da1469x.ld
-
-# While this is for da1469x chip, there is chance that da1468x chip family will also work
-SRC_C += \
-	src/portable/dialog/da146xx/dcd_da146xx.c \
-	$(MCU_FAMILY_DIR)/src/system_da1469x.c \
-	$(MCU_FAMILY_DIR)/src/da1469x_clock.c \
-	$(MCU_FAMILY_DIR)/src/hal_gpio.c \
-
-SRC_S += hw/bsp/$(BOARD)/gcc_startup_da1469x.S
-
-INC += \
-	$(TOP)/hw/bsp/$(BOARD) \
-	$(TOP)/$(MCU_FAMILY_DIR)/include \
-	$(TOP)/$(MCU_FAMILY_DIR)/SDK_10.0.8.105/sdk/bsp/include
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM33_NTZ/non_secure
-
-# For flash-jlink target
-JLINK_DEVICE = DA14699
-
-# flash using jlink but with some twists
-flash: flash-dialog
-
-flash-dialog: $(BUILD)/$(PROJECT).bin
-	@echo '#define SW_VERSION "v_1.0.0.1"' >$(BUILD)/version.h
-	@echo '#define SW_VERSION_DATE "'`date +"%Y-%m-%d %H:%M"`'"' >>$(BUILD)/version.h
-	mkimage da1469x $(BUILD)/$(PROJECT).bin $(BUILD)/version.h $^.img
-	cp $(TOP)/hw/bsp/$(BOARD)/product_header.dump $(BUILD)/$(BOARD)-image.bin
-	cat $^.img >> $(BUILD)/$(BOARD)-image.bin
-	@echo r > $(BUILD)/$(BOARD).jlink
-	@echo halt >> $(BUILD)/$(BOARD).jlink
-	@echo loadfile $(BUILD)/$(BOARD)-image.bin 0x16000000 >> $(BUILD)/$(BOARD).jlink
-	@echo r >> $(BUILD)/$(BOARD).jlink
-	@echo go >> $(BUILD)/$(BOARD).jlink
-	@echo exit >> $(BUILD)/$(BOARD).jlink
-	$(JLINKEXE) -device $(JLINK_DEVICE) -if $(JLINK_IF) -JTAGConf -1,-1 -speed auto -CommandFile $(BUILD)/$(BOARD).jlink
-
diff --git a/tinyusb/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c b/tinyusb/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c
deleted file mode 100755
index 85fa1715..00000000
--- a/tinyusb/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020 Jerzy Kasenberg
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "bsp/board.h"
-#include <hal/hal_gpio.h>
-#include <mcu/mcu.h>
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-#define LED_PIN         33
-#define LED_STATE_ON    1
-#define LED_STATE_OFF   0
-
-#define BUTTON_PIN      6
-
-void UnhandledIRQ(void)
-{
-  CRG_TOP->SYS_CTRL_REG = 0x80;
-  __BKPT(1);
-  while(1);
-}
-
-void board_init(void)
-{
-  // LED
-  hal_gpio_init_out(LED_PIN, LED_STATE_ON);
-
-  hal_gpio_init_out(1, 0);
-  hal_gpio_init_out(2, 0);
-  hal_gpio_init_out(3, 0);
-  hal_gpio_init_out(4, 0);
-  hal_gpio_init_out(5, 0);
-
-  // Button
-  hal_gpio_init_in(BUTTON_PIN, HAL_GPIO_PULL_NONE);
-
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-
-  NVIC_SetPriority(USB_IRQn, 2);
-
-  /* Setup USB IRQ */
-  NVIC_SetPriority(USB_IRQn, 2);
-  NVIC_EnableIRQ(USB_IRQn);
-
-  /* Use PLL96 / 2 clock not HCLK */
-  CRG_TOP->CLK_CTRL_REG &= ~CRG_TOP_CLK_CTRL_REG_USB_CLK_SRC_Msk;
-
-  mcu_gpio_set_pin_function(14, MCU_GPIO_MODE_INPUT, MCU_GPIO_FUNC_USB);
-  mcu_gpio_set_pin_function(15, MCU_GPIO_MODE_INPUT, MCU_GPIO_FUNC_USB);
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  hal_gpio_write(LED_PIN, state ? LED_STATE_ON : LED_STATE_OFF);
-}
-
-uint32_t board_button_read(void)
-{
-  // button is active LOW
-  return hal_gpio_read(BUTTON_PIN) ^ 1;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void)buf;
-  (void)len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void)buf;
-  (void)len;
-
-  return 0;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/tinyusb/hw/bsp/da1469x_dk_pro/da1469x.ld b/tinyusb/hw/bsp/da1469x_dk_pro/da1469x.ld
deleted file mode 100755
index 96507d6e..00000000
--- a/tinyusb/hw/bsp/da1469x_dk_pro/da1469x.ld
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements.  See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership.  The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License.  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied.  See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-MEMORY
-{
-    /*
-     * Flash is remapped at 0x0 by 1st stage bootloader, but this is done with
-     * an offset derived from image header thus it is safer to use remapped
-     * address space at 0x0 instead of QSPI_M address space at 0x16000000.
-     * Bootloader partition is 32K, but 9K is currently reserved for product
-     * header (8K) and image header (1K).
-     * First 512 bytes of SYSRAM are remapped at 0x0 and used as ISR vector
-     * (there's no need to reallocate ISR vector) and thus cannot be used by
-     * application.
-     */
-
-    FLASH (r)  : ORIGIN = (0x00000000), LENGTH = (1024 * 1024)
-    RAM (rw)   : ORIGIN = (0x20000000), LENGTH = (512 * 1024)
-}
-
-OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __HeapBase
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   __bssnz_start__
- *   __bssnz_end__
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
-    __text = .;
-
-    .text :
-    {
-        __isr_vector_start = .;
-        KEEP(*(.isr_vector))
-        /* ISR vector shall have exactly 512 bytes */
-        . = __isr_vector_start + 0x200;
-        __isr_vector_end = .;
-
-        *(.text)
-        *(.text.*)
-
-        *(.libcmac.rom)
-
-        KEEP(*(.init))
-        KEEP(*(.fini))
-
-        /* .ctors */
-        *crtbegin.o(.ctors)
-        *crtbegin?.o(.ctors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-        *(SORT(.ctors.*))
-        *(.ctors)
-
-        /* .dtors */
-        *crtbegin.o(.dtors)
-        *crtbegin?.o(.dtors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
-        *(SORT(.dtors.*))
-        *(.dtors)
-
-        *(.rodata*)
-
-        *(.eh_frame*)
-        . = ALIGN(4);
-    } > FLASH
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-        . = ALIGN(4);
-    } > FLASH
-
-    __exidx_start = .;
-    .ARM :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        . = ALIGN(4);
-    } > FLASH
-    __exidx_end = .;
-
-    .intvect :
-    {
-        . = ALIGN(4);
-        __intvect_start__ = .;
-        . = . + (__isr_vector_end - __isr_vector_start);
-        . = ALIGN(4);
-    } > RAM
-
-    .sleep_state (NOLOAD) :
-    {
-        . = ALIGN(4);
-        *(sleep_state)
-    } > RAM
-
-    /* This section will be zeroed by RTT package init */
-    .rtt (NOLOAD):
-    {
-        . = ALIGN(4);
-        *(.rtt)
-        . = ALIGN(4);
-    } > RAM
-
-    __text_ram_addr = LOADADDR(.text_ram);
-
-    .text_ram :
-    {
-        . = ALIGN(4);
-        __text_ram_start__ = .;
-        *(.text_ram*)
-        . = ALIGN(4);
-        __text_ram_end__ = .;
-    } > RAM AT > FLASH
-
-    __etext = LOADADDR(.data);
-
-    .data :
-    {
-        __data_start__ = .;
-        *(vtable)
-        *(.data*)
-
-        . = ALIGN(4);
-        /* preinit data */
-        PROVIDE_HIDDEN (__preinit_array_start = .);
-        *(.preinit_array)
-        PROVIDE_HIDDEN (__preinit_array_end = .);
-
-        . = ALIGN(4);
-        /* init data */
-        PROVIDE_HIDDEN (__init_array_start = .);
-        *(SORT(.init_array.*))
-        *(.init_array)
-        PROVIDE_HIDDEN (__init_array_end = .);
-
-
-        . = ALIGN(4);
-        /* finit data */
-        PROVIDE_HIDDEN (__fini_array_start = .);
-        *(SORT(.fini_array.*))
-        *(.fini_array)
-        PROVIDE_HIDDEN (__fini_array_end = .);
-
-        *(.jcr)
-        . = ALIGN(4);
-        /* All data end */
-        __data_end__ = .;
-    } > RAM AT > FLASH
-
-    .bssnz :
-    {
-        . = ALIGN(4);
-        __bssnz_start__ = .;
-        *(.bss.core.nz*)
-        . = ALIGN(4);
-        __bssnz_end__ = .;
-    } > RAM
-
-    .bss :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > RAM
-
-    .cmac (NOLOAD) :
-    {
-        . = ALIGN(0x400);
-        *(.libcmac.ram)
-    } > RAM
-
-    /* Heap starts after BSS */
-    . = ALIGN(8);
-    __HeapBase = .;
-
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (COPY):
-    {
-        *(.stack*)
-    } > RAM
-
-    _ram_start = ORIGIN(RAM);
-
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    PROVIDE(__stack = __StackTop);
-
-    /* Top of head is the bottom of the stack */
-    __HeapLimit = __StackLimit;
-    end = __HeapLimit;
-
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__HeapBase <= __HeapLimit, "region RAM overflowed with stack")
-
-    /* Check that intvect is at the beginning of RAM */
-    ASSERT(__intvect_start__ == ORIGIN(RAM), "intvect is not at beginning of RAM")
-}
-
diff --git a/tinyusb/hw/bsp/da1469x_dk_pro/gcc_startup_da1469x.S b/tinyusb/hw/bsp/da1469x_dk_pro/gcc_startup_da1469x.S
deleted file mode 100755
index d47fbcd9..00000000
--- a/tinyusb/hw/bsp/da1469x_dk_pro/gcc_startup_da1469x.S
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements.  See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership.  The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License.  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied.  See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
- #include "syscfg/syscfg.h"
-
-    .syntax unified
-    .arch   armv7-m
-
-    .section .stack
-    .align  3
-#ifdef __STACK_SIZE
-    .equ    Stack_Size, __STACK_SIZE
-#else
-    .equ    Stack_Size, 0xC00
-#endif
-    .equ    SYS_CTRL_REG,       0x50000024
-    .equ    CACHE_FLASH_REG,    0x100C0040
-    .equ    RESET_STAT_REG,     0x500000BC
-
-    .globl  __StackTop
-    .globl  __StackLimit
-__StackLimit:
-    .space  Stack_Size
-    .size   __StackLimit, . - __StackLimit
-__StackTop:
-    .size   __StackTop, . - __StackTop
-
-    .section .heap
-    .align  3
-#ifdef __HEAP_SIZE
-    .equ    Heap_Size, __HEAP_SIZE
-#else
-    .equ    Heap_Size, 0
-#endif
-    .globl  __HeapBase
-    .globl  __HeapLimit
-__HeapBase:
-    .if     Heap_Size
-    .space  Heap_Size
-    .endif
-    .size   __HeapBase, . - __HeapBase
-__HeapLimit:
-    .size   __HeapLimit, . - __HeapLimit
-
-    .section .isr_vector
-    .align 2
-    .globl  __isr_vector
-__isr_vector:
-    .long   __StackTop
-    .long   Reset_Handler
-    /* Cortex-M33 interrupts */
-    .long   NMI_Handler
-    .long   HardFault_Handler
-    .long   MemoryManagement_Handler
-    .long   BusFault_Handler
-    .long   UsageFault_Handler
-    .long   SecureFault_Handler
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   SVC_Handler
-    .long   DebugMonitor_Handler
-    .long   0                       /* Reserved */
-    .long   PendSV_Handler
-    .long   SysTick_Handler
-    /* DA1469x interrupts */
-    .long   SENSOR_NODE_IRQHandler
-    .long   DMA_IRQHandler
-    .long   CHARGER_STATE_IRQHandler
-    .long   CHARGER_ERROR_IRQHandler
-    .long   CMAC2SYS_IRQHandler
-    .long   UART_IRQHandler
-    .long   UART2_IRQHandler
-    .long   UART3_IRQHandler
-    .long   I2C_IRQHandler
-    .long   I2C2_IRQHandler
-    .long   SPI_IRQHandler
-    .long   SPI2_IRQHandler
-    .long   PCM_IRQHandler
-    .long   SRC_IN_IRQHandler
-    .long   SRC_OUT_IRQHandler
-    .long   USB_IRQHandler
-    .long   TIMER_IRQHandler
-    .long   TIMER2_IRQHandler
-    .long   RTC_IRQHandler
-    .long   KEY_WKUP_GPIO_IRQHandler
-    .long   PDC_IRQHandler
-    .long   VBUS_IRQHandler
-    .long   MRM_IRQHandler
-    .long   MOTOR_CONTROLLER_IRQHandler
-    .long   TRNG_IRQHandler
-    .long   DCDC_IRQHandler
-    .long   XTAL32M_RDY_IRQHandler
-    .long   ADC_IRQHandler
-    .long   ADC2_IRQHandler
-    .long   CRYPTO_IRQHandler
-    .long   CAPTIMER1_IRQHandler
-    .long   RFDIAG_IRQHandler
-    .long   LCD_CONTROLLER_IRQHandler
-    .long   PLL_LOCK_IRQHandler
-    .long   TIMER3_IRQHandler
-    .long   TIMER4_IRQHandler
-    .long   LRA_IRQHandler
-    .long   RTC_EVENT_IRQHandler
-    .long   GPIO_P0_IRQHandler
-    .long   GPIO_P1_IRQHandler
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .size   __isr_vector, . - __isr_vector
-
-    .text
-    .thumb
-    .thumb_func
-    .align 2
-    .globl Reset_Handler
-    .type  Reset_Handler, %function
-Reset_Handler:
- /* Make sure interrupt vector is remapped at 0x0 */
-    ldr     r1, =SYS_CTRL_REG
-    ldrh    r2, [r1, #0]
-    orrs    r2, r2, #8
-    strh    r2, [r1, #0]
-
-#if !MYNEWT_VAL(RAM_RESIDENT)
-/*
- * Flash is remapped at 0x0 with an offset, i.e. 0x0 does not correspond to
- * 0x16000000 but to start of an image on flash. This is calculated from product
- * header by 1st state bootloader and configured in CACHE_FLASH_REG. We need to
- * retrieve proper offset value for calculations later.
- */
-    ldr     r1, =CACHE_FLASH_REG
-    ldr     r4, [r1, #0]
-    mov     r2, r4
-    mov     r3, #0xFFFF
-    bic     r4, r4, r3      /* CACHE_FLASH_REG[FLASH_REGION_BASE] */
-    mov     r3, #0xFFF0
-    and     r2, r2, r3      /* CACHE_FLASH_REG[FLASH_REGION_OFFSET] */
-    lsr     r2, r2, #2
-    orr     r4, r4, r2
-
-/* Copy ISR vector from flash to RAM */
-    ldr     r1, =__isr_vector_start     /* src ptr */
-    ldr     r2, =__isr_vector_end       /* src end */
-    ldr     r3, =__intvect_start__      /* dst ptr */
-/* Make sure we copy from QSPIC address range, not from remapped range */
-    cmp     r1, r4
-    itt     lt
-    addlt   r1, r1, r4
-    addlt   r2, r2, r4
-.loop_isr_copy:
-    cmp     r1, r2
-    ittt    lt
-    ldrlt   r0, [r1], #4
-    strlt   r0, [r3], #4
-    blt     .loop_isr_copy
-
-/* Copy QSPI code from flash to RAM */
-    ldr     r1, =__text_ram_addr        /* src ptr */
-    ldr     r2, =__text_ram_start__     /* ptr */
-    ldr     r3, =__text_ram_end__       /* dst end */
-.loop_code_text_ram_copy:
-    cmp     r2, r3
-    ittt    lt
-    ldrlt   r0, [r1], #4
-    strlt   r0, [r2], #4
-    blt     .loop_code_text_ram_copy
-
-/* Copy data from flash to RAM */
-    ldr     r1, =__etext                /* src ptr */
-    ldr     r2, =__data_start__         /* dst ptr */
-    ldr     r3, =__data_end__           /* dst end */
-.loop_data_copy:
-    cmp     r2, r3
-    ittt    lt
-    ldrlt   r0, [r1], #4
-    strlt   r0, [r2], #4
-    blt     .loop_data_copy
-#endif
-
-/* Clear BSS */
-    movs    r0, 0
-    ldr     r1, =__bss_start__
-    ldr     r2, =__bss_end__
-.loop_bss_clear:
-    cmp     r1, r2
-    itt     lt
-    strlt   r0, [r1], #4
-    blt     .loop_bss_clear
-
-    ldr     r0, =__HeapBase
-    ldr     r1, =__HeapLimit
-/* Call static constructors */
-    bl __libc_init_array
-
-    bl      SystemInit
-    bl      main
-
-    .pool
-    .size   Reset_Handler, . - Reset_Handler
-
-/* Default interrupt handler */
-    .type   Default_Handler, %function
-Default_Handler:
-    ldr     r1, =SYS_CTRL_REG
-    ldrh    r2, [r1, #0]
-    orrs    r2, r2, #0x80   /* DEBUGGER_ENABLE */
-    strh    r2, [r1, #0]
-    b       .
-
-    .size   Default_Handler, . - Default_Handler
-
-/* Default handlers for all interrupts */
-    .macro  IRQ handler
-    .weak   \handler
-    .set    \handler, Default_Handler
-    .endm
-
-    /* Cortex-M33 interrupts */
-    IRQ  NMI_Handler
-    IRQ  HardFault_Handler
-    IRQ  MemoryManagement_Handler
-    IRQ  BusFault_Handler
-    IRQ  UsageFault_Handler
-    IRQ  SecureFault_Handler
-    IRQ  SVC_Handler
-    IRQ  DebugMonitor_Handler
-    IRQ  PendSV_Handler
-    IRQ  SysTick_Handler
-    /* DA1469x interrupts */
-    IRQ  SENSOR_NODE_IRQHandler
-    IRQ  DMA_IRQHandler
-    IRQ  CHARGER_STATE_IRQHandler
-    IRQ  CHARGER_ERROR_IRQHandler
-    IRQ  CMAC2SYS_IRQHandler
-    IRQ  UART_IRQHandler
-    IRQ  UART2_IRQHandler
-    IRQ  UART3_IRQHandler
-    IRQ  I2C_IRQHandler
-    IRQ  I2C2_IRQHandler
-    IRQ  SPI_IRQHandler
-    IRQ  SPI2_IRQHandler
-    IRQ  PCM_IRQHandler
-    IRQ  SRC_IN_IRQHandler
-    IRQ  SRC_OUT_IRQHandler
-    IRQ  USB_IRQHandler
-    IRQ  TIMER_IRQHandler
-    IRQ  TIMER2_IRQHandler
-    IRQ  RTC_IRQHandler
-    IRQ  KEY_WKUP_GPIO_IRQHandler
-    IRQ  PDC_IRQHandler
-    IRQ  VBUS_IRQHandler
-    IRQ  MRM_IRQHandler
-    IRQ  MOTOR_CONTROLLER_IRQHandler
-    IRQ  TRNG_IRQHandler
-    IRQ  DCDC_IRQHandler
-    IRQ  XTAL32M_RDY_IRQHandler
-    IRQ  ADC_IRQHandler
-    IRQ  ADC2_IRQHandler
-    IRQ  CRYPTO_IRQHandler
-    IRQ  CAPTIMER1_IRQHandler
-    IRQ  RFDIAG_IRQHandler
-    IRQ  LCD_CONTROLLER_IRQHandler
-    IRQ  PLL_LOCK_IRQHandler
-    IRQ  TIMER3_IRQHandler
-    IRQ  TIMER4_IRQHandler
-    IRQ  LRA_IRQHandler
-    IRQ  RTC_EVENT_IRQHandler
-    IRQ  GPIO_P0_IRQHandler
-    IRQ  GPIO_P1_IRQHandler
-    IRQ  RESERVED40_IRQHandler
-    IRQ  RESERVED41_IRQHandler
-    IRQ  RESERVED42_IRQHandler
-    IRQ  RESERVED43_IRQHandler
-    IRQ  RESERVED44_IRQHandler
-    IRQ  RESERVED45_IRQHandler
-    IRQ  RESERVED46_IRQHandler
-    IRQ  RESERVED47_IRQHandler
-
-.end
diff --git a/tinyusb/hw/bsp/da1469x_dk_pro/product_header.dump b/tinyusb/hw/bsp/da1469x_dk_pro/product_header.dump
deleted file mode 100755
index ea484224..00000000
--- a/tinyusb/hw/bsp/da1469x_dk_pro/product_header.dump
+++ /dev/null
diff --git a/tinyusb/hw/bsp/da1469x_dk_pro/syscfg/syscfg.h b/tinyusb/hw/bsp/da1469x_dk_pro/syscfg/syscfg.h
deleted file mode 100755
index 6cbb4319..00000000
--- a/tinyusb/hw/bsp/da1469x_dk_pro/syscfg/syscfg.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/**
- * This file was generated by Apache newt version: 1.9.0-dev
- */
-
-#ifndef H_MYNEWT_SYSCFG_
-#define H_MYNEWT_SYSCFG_
-
-/**
- * This macro exists to ensure code includes this header when needed.  If code
- * checks the existence of a setting directly via ifdef without including this
- * header, the setting macro will silently evaluate to 0.  In contrast, an
- * attempt to use these macros without including this header will result in a
- * compiler error.
- */
-#define MYNEWT_VAL(_name)                       MYNEWT_VAL_ ## _name
-#define MYNEWT_VAL_CHOICE(_name, _val)          MYNEWT_VAL_ ## _name ## __ ## _val
-
-#ifndef MYNEWT_VAL_RAM_RESIDENT
-#define MYNEWT_VAL_RAM_RESIDENT (0)
-#endif
-
-#ifndef MYNEWT_VAL_MCU_GPIO_MAX_IRQ
-#define MYNEWT_VAL_MCU_GPIO_MAX_IRQ (4)
-#endif
-
-#ifndef MYNEWT_VAL_MCU_GPIO_RETAINABLE_NUM
-#define MYNEWT_VAL_MCU_GPIO_RETAINABLE_NUM (-1)
-#endif
-
-#ifndef MYNEWT_VAL_MCU_CLOCK_XTAL32M_SETTLE_TIME_US
-#define MYNEWT_VAL_MCU_CLOCK_XTAL32M_SETTLE_TIME_US (2000)
-#endif
-
-#endif
diff --git a/tinyusb/hw/bsp/ea4088qs/board.mk b/tinyusb/hw/bsp/ea4088qs/board.mk
deleted file mode 100755
index c624a5cf..00000000
--- a/tinyusb/hw/bsp/ea4088qs/board.mk
+++ /dev/null
@@ -1,46 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib \
-  -DCORE_M4 \
-  -D__USE_LPCOPEN \
-  -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
-  -DCFG_TUSB_MCU=OPT_MCU_LPC40XX
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter
-
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc4088.ld
-
-SRC_C += \
-	src/portable/nxp/lpc17_40/dcd_lpc17_40.c \
-	$(MCU_DIR)/../gcc/cr_startup_lpc40xx.c \
-	$(MCU_DIR)/src/chip_17xx_40xx.c \
-	$(MCU_DIR)/src/clock_17xx_40xx.c \
-	$(MCU_DIR)/src/gpio_17xx_40xx.c \
-	$(MCU_DIR)/src/iocon_17xx_40xx.c \
-	$(MCU_DIR)/src/sysctl_17xx_40xx.c \
-	$(MCU_DIR)/src/sysinit_17xx_40xx.c \
-	$(MCU_DIR)/src/uart_17xx_40xx.c \
-	$(MCU_DIR)/src/fpu_init.c
-
-INC += \
-	$(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = LPC4088
-
-# flash using jlink
-flash: flash-jlink
diff --git a/tinyusb/hw/bsp/ea4088qs/ea4088qs.c b/tinyusb/hw/bsp/ea4088qs/ea4088qs.c
deleted file mode 100755
index b25f9101..00000000
--- a/tinyusb/hw/bsp/ea4088qs/ea4088qs.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "chip.h"
-#include "../board.h"
-
-//--------------------------------------------------------------------+
-// USB Interrupt Handler
-//--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
-    tuh_int_handler(0);
-  #endif
-
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-    tud_int_handler(0);
-  #endif
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-#define LED_PORT      2
-#define LED_PIN       19
-
-#define BUTTON_PORT   2
-#define BUTTON_PIN    10
-
-/* System oscillator rate and RTC oscillator rate */
-const uint32_t OscRateIn = 12000000;
-const uint32_t RTCOscRateIn = 32768;
-
-/* Pin muxing configuration */
-static const PINMUX_GRP_T pinmuxing[] =
-{
-  // LED
-  {2, 19, (IOCON_FUNC0 | IOCON_MODE_INACT)},
-
-  // Button
-  {2, 10, (IOCON_FUNC0 | IOCON_MODE_INACT | IOCON_MODE_PULLUP)},
-};
-
-static const PINMUX_GRP_T pin_usb_mux[] =
-{
-  // USB1 as Host
-  {0, 29, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // D+1
-  {0, 30, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // D-1
-  {1, 18, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // UP LED1
-  {1, 19, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // PPWR1
-//  {2, 14, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // VBUS1
-//  {2, 15, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // OVRCR1
-
-  // USB2 as Device
-  {0, 31, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // D+2
-  {0, 13, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // UP LED
-  {0, 14, (IOCON_FUNC3 | IOCON_MODE_INACT)}, // CONNECT2
-
-  /* VBUS is not connected on this board, so leave the pin at default setting. */
-  /*Chip_IOCON_PinMux(LPC_IOCON, 1, 30, IOCON_MODE_INACT, IOCON_FUNC2);*/ /* USB VBUS */
-};
-
-// Invoked by startup code
-void SystemInit(void)
-{
-#ifdef __USE_LPCOPEN
-	extern void (* const g_pfnVectors[])(void);
-  unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
-	*pSCB_VTOR = (unsigned int) g_pfnVectors;
-
-#if __FPU_USED == 1
-	fpuInit();
-#endif
-#endif // __USE_LPCOPEN
-
-  Chip_IOCON_Init(LPC_IOCON);
-  Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
-
-	/* CPU clock source starts with IRC */
-	/* Enable PBOOST for CPU clock over 100MHz */
-	Chip_SYSCTL_EnableBoost();
-
-  Chip_SetupXtalClocking();
-}
-
-void board_init(void)
-{
-  SystemCoreClockUpdate();
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  Chip_GPIO_Init(LPC_GPIO);
-
-  // LED
-  Chip_GPIO_SetPinDIROutput(LPC_GPIO, LED_PORT, LED_PIN);
-
-  // Button
-  Chip_GPIO_SetPinDIRInput(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
-
-  // UART
-
-  //------------- USB -------------//
-  Chip_IOCON_SetPinMuxing(LPC_IOCON, pin_usb_mux, sizeof(pin_usb_mux) / sizeof(PINMUX_GRP_T));
-
-  // Port1 as Host, Port2: Device
-  Chip_USB_Init();
-
-  enum {
-    USBCLK_DEVCIE = 0x12, // AHB + Device
-    USBCLK_HOST = 0x19 ,  // AHB + OTG + Host
-    USBCLK_ALL  = 0x1B    // Host + Device + OTG + AHB
-  };
-
-  LPC_USB->OTGClkCtrl = USBCLK_ALL;
-  while ( (LPC_USB->OTGClkSt & USBCLK_ALL) != USBCLK_ALL ) {}
-
-  // set portfunc: USB1 = host, USB2 = device
-  LPC_USB->StCtrl = 0x3;
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state);
-}
-
-uint32_t board_button_read(void)
-{
-  // active low
-  return Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN) ? 0 : 1;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  //return UART_ReceiveByte(BOARD_UART_PORT);
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  //UART_Send(BOARD_UART_PORT, &c, 1, BLOCKING);
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/tinyusb/hw/bsp/ea4088qs/lpc4088.ld b/tinyusb/hw/bsp/ea4088qs/lpc4088.ld
deleted file mode 100755
index 4b1cddd6..00000000
--- a/tinyusb/hw/bsp/ea4088qs/lpc4088.ld
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * GENERATED FILE - DO NOT EDIT
- * (c) Code Red Technologies Ltd, 2008-2013
- * (c) NXP Semiconductors 2013-2019
- * Generated linker script file for LPC4088
- * Created from linkscript.ldt by FMCreateLinkLibraries
- * Using Freemarker v2.3.23
- * MCUXpresso IDE v10.2.1 [Build 795] [2018-07-25] on May 15, 2019 5:16:07 PM
- */
-
-MEMORY
-{
-  /* Define each memory region */
-  MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */  
-  RamLoc64 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x10000 /* 64K bytes (alias RAM) */  
-  RamPeriph32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */  
-}
-
-  /* Define a symbol for the top of each memory region */
-  __base_MFlash512 = 0x0  ; /* MFlash512 */  
-  __base_Flash = 0x0 ; /* Flash */  
-  __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */  
-  __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */  
-  __base_RamLoc64 = 0x10000000  ; /* RamLoc64 */  
-  __base_RAM = 0x10000000 ; /* RAM */  
-  __top_RamLoc64 = 0x10000000 + 0x10000 ; /* 64K bytes */  
-  __top_RAM = 0x10000000 + 0x10000 ; /* 64K bytes */  
-  __base_RamPeriph32 = 0x20000000  ; /* RamPeriph32 */  
-  __base_RAM2 = 0x20000000 ; /* RAM2 */  
-  __top_RamPeriph32 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-  __top_RAM2 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-
-ENTRY(ResetISR)
-
-SECTIONS
-{
-    /* MAIN TEXT SECTION */
-    .text : ALIGN(4)
-    {
-        FILL(0xff)
-        __vectors_start__ = ABSOLUTE(.) ;
-        KEEP(*(.isr_vector))
-        /* Global Section Table */
-        . = ALIGN(4) ;
-        __section_table_start = .;
-        __data_section_table = .;
-        LONG(LOADADDR(.data));
-        LONG(    ADDR(.data));
-        LONG(  SIZEOF(.data));
-        LONG(LOADADDR(.data_RAM2));
-        LONG(    ADDR(.data_RAM2));
-        LONG(  SIZEOF(.data_RAM2));
-        __data_section_table_end = .;
-        __bss_section_table = .;
-        LONG(    ADDR(.bss));
-        LONG(  SIZEOF(.bss));
-        LONG(    ADDR(.bss_RAM2));
-        LONG(  SIZEOF(.bss_RAM2));
-        __bss_section_table_end = .;
-        __section_table_end = . ;
-        /* End of Global Section Table */
-
-        *(.after_vectors*)
-
-    } > MFlash512
-
-    .text : ALIGN(4)
-    {
-       *(.text*)
-       *(.rodata .rodata.* .constdata .constdata.*)
-       . = ALIGN(4);
-    } > MFlash512
-    /*
-     * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
-     */
-    .ARM.extab : ALIGN(4) 
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > MFlash512
-
-    __exidx_start = .;
-
-    .ARM.exidx : ALIGN(4)
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > MFlash512
-    __exidx_end = .;
-
-    _etext = .;
-        
-    /* DATA section for RamPeriph32 */
-
-    .data_RAM2 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM2 = .) ;
-        *(.ramfunc.$RAM2)
-        *(.ramfunc.$RamPeriph32)
-        *(.data.$RAM2*)
-        *(.data.$RamPeriph32*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM2 = .) ;
-     } > RamPeriph32 AT>MFlash512
-    /* MAIN DATA SECTION */
-    .uninit_RESERVED : ALIGN(4)
-    {
-        KEEP(*(.bss.$RESERVED*))
-        . = ALIGN(4) ;
-        _end_uninit_RESERVED = .;
-    } > RamLoc64
-
-    /* Main DATA section (RamLoc64) */
-    .data : ALIGN(4)
-    {
-       FILL(0xff)
-       _data = . ;
-       *(vtable)
-       *(.ramfunc*)
-       *(.data*)
-       . = ALIGN(4) ;
-       _edata = . ;
-    } > RamLoc64 AT>MFlash512
-
-    /* BSS section for RamPeriph32 */
-    .bss_RAM2 : ALIGN(4)
-    {
-       PROVIDE(__start_bss_RAM2 = .) ;
-       *(.bss.$RAM2*)
-       *(.bss.$RamPeriph32*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM2 = .) ;
-    } > RamPeriph32 
-
-    /* MAIN BSS SECTION */
-    .bss : ALIGN(4)
-    {
-        _bss = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4) ;
-        _ebss = .;
-        PROVIDE(end = .);
-    } > RamLoc64
-
-    /* NOINIT section for RamPeriph32 */
-    .noinit_RAM2 (NOLOAD) : ALIGN(4)
-    {
-       *(.noinit.$RAM2*)
-       *(.noinit.$RamPeriph32*)
-       . = ALIGN(4) ;
-    } > RamPeriph32 
-
-    /* DEFAULT NOINIT SECTION */
-    .noinit (NOLOAD): ALIGN(4)
-    {
-        _noinit = .;
-        *(.noinit*) 
-         . = ALIGN(4) ;
-        _end_noinit = .;
-    } > RamLoc64
-    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
-    PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc64 - 0);
-
-    /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (NMI_Handler + 1) 
-                                         + (HardFault_Handler + 1) 
-                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
-                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
-                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
-                                         ) );
-
-    /* Provide basic symbols giving location and size of main text
-     * block, including initial values of RW data sections. Note that
-     * these will need extending to give a complete picture with
-     * complex images (e.g multiple Flash banks).
-     */
-    _image_start = LOADADDR(.text);
-    _image_end = LOADADDR(.data) + SIZEOF(.data);
-    _image_size = _image_end - _image_start;
-}
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/ea4357/board.mk b/tinyusb/hw/bsp/ea4357/board.mk
deleted file mode 100755
index 86391ab5..00000000
--- a/tinyusb/hw/bsp/ea4357/board.mk
+++ /dev/null
@@ -1,46 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib \
-  -DCORE_M4 \
-  -D__USE_LPCOPEN \
-  -DCFG_TUSB_MCU=OPT_MCU_LPC43XX
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes
-
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc4357.ld
-
-SRC_C += \
-	src/portable/nxp/transdimension/dcd_transdimension.c \
-	$(MCU_DIR)/../gcc/cr_startup_lpc43xx.c \
-	$(MCU_DIR)/src/chip_18xx_43xx.c \
-	$(MCU_DIR)/src/clock_18xx_43xx.c \
-	$(MCU_DIR)/src/gpio_18xx_43xx.c \
-	$(MCU_DIR)/src/sysinit_18xx_43xx.c \
-	$(MCU_DIR)/src/i2c_18xx_43xx.c \
-	$(MCU_DIR)/src/i2cm_18xx_43xx.c \
-	$(MCU_DIR)/src/uart_18xx_43xx.c \
-	$(MCU_DIR)/src/fpu_init.c
-
-INC += \
-	$(TOP)/$(MCU_DIR)/inc \
-	$(TOP)/$(MCU_DIR)/inc/config_43xx
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = LPC4357_M4
-
-# flash using jlink
-flash: flash-jlink
diff --git a/tinyusb/hw/bsp/ea4357/ea4357.c b/tinyusb/hw/bsp/ea4357/ea4357.c
deleted file mode 100755
index aa206a28..00000000
--- a/tinyusb/hw/bsp/ea4357/ea4357.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "chip.h"
-#include "../board.h"
-#include "pca9532.h"
-
-#define UART_DEV        LPC_USART0
-#define UART_PORT       0x0f
-#define UART_PIN_TX     10
-#define UART_PIN_RX     11
-
-// P9_1 joystick down
-#define BUTTON_PORT     4
-#define BUTTON_PIN      13
-
-//static const struct {
-//  uint8_t mux_port;
-//  uint8_t mux_pin;
-//
-//  uint8_t gpio_port;
-//  uint8_t gpio_pin;
-//}buttons[] =
-//{
-//    {0x0a, 3, 4, 10 }, // Joystick up
-//    {0x09, 1, 4, 13 }, // Joystick down
-//    {0x0a, 2, 4, 9  }, // Joystick left
-//    {0x09, 0, 4, 12 }, // Joystick right
-//    {0x0a, 1, 4, 8  }, // Joystick press
-//    {0x02, 7, 0, 7  }, // SW6
-//};
-
-/*------------------------------------------------------------------*/
-/* BOARD API
- *------------------------------------------------------------------*/
-
-/* System configuration variables used by chip driver */
-const uint32_t OscRateIn = 12000000;
-const uint32_t ExtRateIn = 0;
-
-static const PINMUX_GRP_T pinmuxing[] =
-{
-  // Button ( Joystick down )
-  {0x9, 1,  (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0 | SCU_MODE_PULLUP)},
-
-  // UART
-  {UART_PORT, UART_PIN_TX, SCU_MODE_PULLDOWN | SCU_MODE_FUNC1},
-  {UART_PORT, UART_PIN_RX, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC1},
-
-  // USB
-};
-
-/* Pin clock mux values, re-used structure, value in first index is meaningless */
-static const PINMUX_GRP_T pinclockmuxing[] =
-{
-  {0, 0,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
-  {0, 1,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
-  {0, 2,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
-  {0, 3,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
-};
-
-// Invoked by startup code
-void SystemInit(void)
-{
-#ifdef __USE_LPCOPEN
-	extern void (* const g_pfnVectors[])(void);
-  unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
-	*pSCB_VTOR = (unsigned int) g_pfnVectors;
-
-#if __FPU_USED == 1
-	fpuInit();
-#endif
-#endif // __USE_LPCOPEN
-
-	/* Setup system level pin muxing */
-	Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
-
-	/* Clock pins only, group field not used */
-	for (int i = 0; i <(int)  (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++)
-	{
-		Chip_SCU_ClockPinMuxSet(pinclockmuxing[i].pinnum, pinclockmuxing[i].modefunc);
-	}
-
-  Chip_SetupXtalClocking();
-}
-
-void board_init(void)
-{
-  SystemCoreClockUpdate();
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  //NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  Chip_GPIO_Init(LPC_GPIO_PORT);
-
-  // LED via pca9532 I2C
-  Chip_SCU_I2C0PinConfig(I2C0_STANDARD_FAST_MODE);
-  Chip_I2C_Init(I2C0);
-  Chip_I2C_SetClockRate(I2C0, 100000);
-  Chip_I2C_SetMasterEventHandler(I2C0, Chip_I2C_EventHandlerPolling);
-
-  pca9532_init();
-
-  // Button
-  Chip_GPIO_SetPinDIRInput(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN);
-
-  //------------- UART -------------//
-	Chip_UART_Init(UART_DEV);
-	Chip_UART_SetBaud(UART_DEV, CFG_BOARD_UART_BAUDRATE);
-	Chip_UART_ConfigData(UART_DEV, UART_LCR_WLEN8 | UART_LCR_SBS_1BIT | UART_LCR_PARITY_DIS);
-	Chip_UART_TXEnable(UART_DEV);
-
-  //------------- USB -------------//
-  enum {
-    USBMODE_DEVICE = 2,
-    USBMODE_HOST   = 3
-  };
-
-  enum {
-    USBMODE_VBUS_LOW  = 0,
-    USBMODE_VBUS_HIGH = 1
-  };
-
-  /* From EA4357 user manual
-   *
-   * USB0 Device operation:
-   * - Insert jumpers in position 1-2 in JP17/JP18/JP19.
-   * - GPIO28 controls USB connect functionality
-   * - LED32 lights when the USB Device is connected. SJ4 has pads 1-2 shorted by default.
-   * - LED33 is controlled by GPIO27 and signals USB-up state. GPIO54 is used for VBUS
-   * sensing.
-   *
-   * USB0 Host operation:
-   * - insert jumpers in position 2-3 in JP17/JP18/JP19.
-   * - USB Host power is controlled via distribution switch U20 (found in schematic page 11).
-   * - Signal GPIO26 is active low and enables +5V on VBUS2.
-   * - LED35 light whenever +5V is present on VBUS2.
-   * - GPIO55 is connected to status feedback from the distribution switch.
-   * - GPIO54 is used for VBUS sensing. 15Kohm pull-down resistors are always active
-   *
-   * Note:
-   * - Insert jumpers in position 2-3 in JP17/JP18/JP19
-   * - Insert jumpers in JP31 (OTG)
-   */
-#if CFG_TUSB_RHPORT0_MODE
-  Chip_USB0_Init();
-#endif
-
-  /* From EA4357 user manual
-   *
-   * For USB1 Device:
-   * - a 1.5Kohm pull-up resistor is needed on the USB DP data signal. There are two methods to create this.
-   * JP15 is inserted and the pull-up resistor is always enabled. Alternatively, the pull-up resistor is activated
-   * inside the USB OTG chip (U31), and this has to be done via the I2C interface of GPIO52/GPIO53. In the latter case,
-   * JP15 shall not be inserted.
-   * - J19 is the connector to use when USB Device is used. Normally it should be a USB-B connector for
-   * creating a USB Device interface, but the mini-AB connector can also be used in this case. The status
-   * of VBUS can be read via U31.
-   * - JP16 shall not be inserted.
-   *
-   * For USB1 Host:
-   * - 15Kohm pull-down resistors are needed on the USB data signals. These are activated inside the USB OTG chip (U31),
-   * and this has to be done via the I2C interface of GPIO52/GPIO53.
-   * - J20 is the connector to use when USB Host is used. In order to provide +5V to the external USB
-   * device connected to this connector (J20), channel A of U20 must be enabled. It is enabled by default
-   * since SJ5 is normally connected between pin 1-2.
-   * - LED34 lights green when +5V is available on J20.
-   * - JP15 shall not be inserted. JP16 has no effect
-   */
-#if CFG_TUSB_RHPORT1_MODE
-  Chip_USB1_Init();
-#endif
-
-  // USB0 Vbus Power: P2_3 on EA4357 channel B U20 GPIO26 active low (base board)
-  Chip_SCU_PinMuxSet(2, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC7);
-
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-  // P9_5 (GPIO5[18]) (GPIO28 on oem base) as USB connect, active low.
-  Chip_SCU_PinMuxSet(9, 5, SCU_MODE_PULLDOWN | SCU_MODE_FUNC4);
-  Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 5, 18);
-  #endif
-
-  // USB1 Power: EA4357 channel A U20 is enabled by SJ5 connected to pad 1-2, no more action required
-  // TODO Remove R170, R171, solder a pair of 15K to USB1 D+/D- to test with USB1 Host
-}
-
-//--------------------------------------------------------------------+
-// USB Interrupt Handler
-//--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
-    tuh_int_handler(0);
-  #endif
-
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-    tud_int_handler(0);
-  #endif
-}
-
-void USB1_IRQHandler(void)
-{
-  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
-    tuh_int_handler(1);
-  #endif
-
-  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE
-    tud_int_handler(1);
-  #endif
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  if (state)
-  {
-    pca9532_setLeds( LED1, 0 );
-  }else
-  {
-    pca9532_setLeds( 0, LED1);
-  }
-}
-
-uint32_t board_button_read(void)
-{
-  // active low
-  return Chip_GPIO_GetPinState(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN) ? 0 : 1;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  //return UART_ReceiveByte(BOARD_UART_DEV);
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  uint8_t const* buf8 = (uint8_t const*) buf;
-  for(int i=0; i<len; i++)
-  {
-    while ((Chip_UART_ReadLineStatus(UART_DEV) & UART_LSR_THRE) == 0) {}
-    Chip_UART_SendByte(UART_DEV, buf8[i]);
-  }
-
-  return len;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/tinyusb/hw/bsp/ea4357/lpc4357.ld b/tinyusb/hw/bsp/ea4357/lpc4357.ld
deleted file mode 100755
index 14a0df32..00000000
--- a/tinyusb/hw/bsp/ea4357/lpc4357.ld
+++ /dev/null
@@ -1,324 +0,0 @@
-/*
- * GENERATED FILE - DO NOT EDIT
- * (c) Code Red Technologies Ltd, 2008-2013
- * (c) NXP Semiconductors 2013-2019
- * Generated linker script file for LPC4357
- * Created from linkscript.ldt by FMCreateLinkLibraries
- * Using Freemarker v2.3.23
- * MCUXpresso IDE v10.2.1 [Build 795] [2018-07-25] on May 15, 2019 5:48:43 PM
- */
-
-MEMORY
-{
-  /* Define each memory region */
-  MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */  
-  MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */  
-  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */  
-  RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */  
-  RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */  
-  RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */  
-  RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */  
-}
-
-  /* Define a symbol for the top of each memory region */
-  __base_MFlashA512 = 0x1a000000  ; /* MFlashA512 */  
-  __base_Flash = 0x1a000000 ; /* Flash */  
-  __top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */  
-  __top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */  
-  __base_MFlashB512 = 0x1b000000  ; /* MFlashB512 */  
-  __base_Flash2 = 0x1b000000 ; /* Flash2 */  
-  __top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */  
-  __top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */  
-  __base_RamLoc32 = 0x10000000  ; /* RamLoc32 */  
-  __base_RAM = 0x10000000 ; /* RAM */  
-  __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */  
-  __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */  
-  __base_RamLoc40 = 0x10080000  ; /* RamLoc40 */  
-  __base_RAM2 = 0x10080000 ; /* RAM2 */  
-  __top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */  
-  __top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */  
-  __base_RamAHB32 = 0x20000000  ; /* RamAHB32 */  
-  __base_RAM3 = 0x20000000 ; /* RAM3 */  
-  __top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-  __top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-  __base_RamAHB16 = 0x20008000  ; /* RamAHB16 */  
-  __base_RAM4 = 0x20008000 ; /* RAM4 */  
-  __top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */  
-  __top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */  
-  __base_RamAHB_ETB16 = 0x2000c000  ; /* RamAHB_ETB16 */  
-  __base_RAM5 = 0x2000c000 ; /* RAM5 */  
-  __top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */  
-  __top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */  
-
-
-ENTRY(ResetISR)
-
-SECTIONS
-{
-    .text_Flash2 : ALIGN(4)
-    {
-       FILL(0xff)
-        *(.text_Flash2*) /* for compatibility with previous releases */
-        *(.text_MFlashB512*) /* for compatibility with previous releases */
-        *(.text.$Flash2*)
-        *(.text.$MFlashB512*)
-        *(.rodata.$Flash2*)
-        *(.rodata.$MFlashB512*)
-    } > MFlashB512
-
-    /* MAIN TEXT SECTION */
-    .text : ALIGN(4)
-    {
-        FILL(0xff)
-        __vectors_start__ = ABSOLUTE(.) ;
-        KEEP(*(.isr_vector))
-        /* Global Section Table */
-        . = ALIGN(4) ;
-        __section_table_start = .;
-        __data_section_table = .;
-        LONG(LOADADDR(.data));
-        LONG(    ADDR(.data));
-        LONG(  SIZEOF(.data));
-        LONG(LOADADDR(.data_RAM2));
-        LONG(    ADDR(.data_RAM2));
-        LONG(  SIZEOF(.data_RAM2));
-        LONG(LOADADDR(.data_RAM3));
-        LONG(    ADDR(.data_RAM3));
-        LONG(  SIZEOF(.data_RAM3));
-        LONG(LOADADDR(.data_RAM4));
-        LONG(    ADDR(.data_RAM4));
-        LONG(  SIZEOF(.data_RAM4));
-        LONG(LOADADDR(.data_RAM5));
-        LONG(    ADDR(.data_RAM5));
-        LONG(  SIZEOF(.data_RAM5));
-        __data_section_table_end = .;
-        __bss_section_table = .;
-        LONG(    ADDR(.bss));
-        LONG(  SIZEOF(.bss));
-        LONG(    ADDR(.bss_RAM2));
-        LONG(  SIZEOF(.bss_RAM2));
-        LONG(    ADDR(.bss_RAM3));
-        LONG(  SIZEOF(.bss_RAM3));
-        LONG(    ADDR(.bss_RAM4));
-        LONG(  SIZEOF(.bss_RAM4));
-        LONG(    ADDR(.bss_RAM5));
-        LONG(  SIZEOF(.bss_RAM5));
-        __bss_section_table_end = .;
-        __section_table_end = . ;
-        /* End of Global Section Table */
-
-        *(.after_vectors*)
-
-    } > MFlashA512
-
-    .text : ALIGN(4)
-    {
-       *(.text*)
-       *(.rodata .rodata.* .constdata .constdata.*)
-       . = ALIGN(4);
-    } > MFlashA512
-    /*
-     * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
-     */
-    .ARM.extab : ALIGN(4) 
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > MFlashA512
-
-    __exidx_start = .;
-
-    .ARM.exidx : ALIGN(4)
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > MFlashA512
-    __exidx_end = .;
-
-    _etext = .;
-        
-    /* DATA section for RamLoc40 */
-
-    .data_RAM2 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM2 = .) ;
-        *(.ramfunc.$RAM2)
-        *(.ramfunc.$RamLoc40)
-        *(.data.$RAM2*)
-        *(.data.$RamLoc40*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM2 = .) ;
-     } > RamLoc40 AT>MFlashA512
-    /* DATA section for RamAHB32 */
-
-    .data_RAM3 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM3 = .) ;
-        *(.ramfunc.$RAM3)
-        *(.ramfunc.$RamAHB32)
-        *(.data.$RAM3*)
-        *(.data.$RamAHB32*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM3 = .) ;
-     } > RamAHB32 AT>MFlashA512
-    /* DATA section for RamAHB16 */
-
-    .data_RAM4 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM4 = .) ;
-        *(.ramfunc.$RAM4)
-        *(.ramfunc.$RamAHB16)
-        *(.data.$RAM4*)
-        *(.data.$RamAHB16*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM4 = .) ;
-     } > RamAHB16 AT>MFlashA512
-    /* DATA section for RamAHB_ETB16 */
-
-    .data_RAM5 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM5 = .) ;
-        *(.ramfunc.$RAM5)
-        *(.ramfunc.$RamAHB_ETB16)
-        *(.data.$RAM5*)
-        *(.data.$RamAHB_ETB16*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM5 = .) ;
-     } > RamAHB_ETB16 AT>MFlashA512
-    /* MAIN DATA SECTION */
-    .uninit_RESERVED : ALIGN(4)
-    {
-        KEEP(*(.bss.$RESERVED*))
-        . = ALIGN(4) ;
-        _end_uninit_RESERVED = .;
-    } > RamLoc32
-
-    /* Main DATA section (RamLoc32) */
-    .data : ALIGN(4)
-    {
-       FILL(0xff)
-       _data = . ;
-       *(vtable)
-       *(.ramfunc*)
-       *(.data*)
-       . = ALIGN(4) ;
-       _edata = . ;
-    } > RamLoc32 AT>MFlashA512
-
-    /* BSS section for RamLoc40 */
-    .bss_RAM2 : ALIGN(4)
-    {
-       PROVIDE(__start_bss_RAM2 = .) ;
-       *(.bss.$RAM2*)
-       *(.bss.$RamLoc40*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM2 = .) ;
-    } > RamLoc40 
-
-    /* BSS section for RamAHB32 */
-    .bss_RAM3 : ALIGN(4)
-    {
-       PROVIDE(__start_bss_RAM3 = .) ;
-       *(.bss.$RAM3*)
-       *(.bss.$RamAHB32*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM3 = .) ;
-    } > RamAHB32 
-
-    /* BSS section for RamAHB16 */
-    .bss_RAM4 : ALIGN(4)
-    {
-       PROVIDE(__start_bss_RAM4 = .) ;
-       *(.bss.$RAM4*)
-       *(.bss.$RamAHB16*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM4 = .) ;
-    } > RamAHB16 
-
-    /* BSS section for RamAHB_ETB16 */
-    .bss_RAM5 : ALIGN(4)
-    {
-       PROVIDE(__start_bss_RAM5 = .) ;
-       *(.bss.$RAM5*)
-       *(.bss.$RamAHB_ETB16*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM5 = .) ;
-    } > RamAHB_ETB16 
-
-    /* MAIN BSS SECTION */
-    .bss : ALIGN(4)
-    {
-        _bss = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4) ;
-        _ebss = .;
-        PROVIDE(end = .);
-    } > RamLoc32
-
-    /* NOINIT section for RamLoc40 */
-    .noinit_RAM2 (NOLOAD) : ALIGN(4)
-    {
-       *(.noinit.$RAM2*)
-       *(.noinit.$RamLoc40*)
-       . = ALIGN(4) ;
-    } > RamLoc40 
-
-    /* NOINIT section for RamAHB32 */
-    .noinit_RAM3 (NOLOAD) : ALIGN(4)
-    {
-       *(.noinit.$RAM3*)
-       *(.noinit.$RamAHB32*)
-       . = ALIGN(4) ;
-    } > RamAHB32 
-
-    /* NOINIT section for RamAHB16 */
-    .noinit_RAM4 (NOLOAD) : ALIGN(4)
-    {
-       *(.noinit.$RAM4*)
-       *(.noinit.$RamAHB16*)
-       . = ALIGN(4) ;
-    } > RamAHB16 
-
-    /* NOINIT section for RamAHB_ETB16 */
-    .noinit_RAM5 (NOLOAD) : ALIGN(4)
-    {
-       *(.noinit.$RAM5*)
-       *(.noinit.$RamAHB_ETB16*)
-       . = ALIGN(4) ;
-    } > RamAHB_ETB16 
-
-    /* DEFAULT NOINIT SECTION */
-    .noinit (NOLOAD): ALIGN(4)
-    {
-        _noinit = .;
-        *(.noinit*) 
-         . = ALIGN(4) ;
-        _end_noinit = .;
-    } > RamLoc32
-    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
-    PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
-
-    /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (NMI_Handler + 1) 
-                                         + (HardFault_Handler + 1) 
-                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
-                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
-                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
-                                         ) );
-
-    /* Provide basic symbols giving location and size of main text
-     * block, including initial values of RW data sections. Note that
-     * these will need extending to give a complete picture with
-     * complex images (e.g multiple Flash banks).
-     */
-    _image_start = LOADADDR(.text);
-    _image_end = LOADADDR(.data) + SIZEOF(.data);
-    _image_size = _image_end - _image_start;
-}
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/ea4357/pca9532.c b/tinyusb/hw/bsp/ea4357/pca9532.c
deleted file mode 100755
index eae3805c..00000000
--- a/tinyusb/hw/bsp/ea4357/pca9532.c
+++ /dev/null
@@ -1,352 +0,0 @@
-/*****************************************************************************
- *
- *   Copyright(C) 2011, Embedded Artists AB
- *   All rights reserved.
- *
- ******************************************************************************
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * products. This software is supplied "AS IS" without any warranties.
- * Embedded Artists AB assumes no responsibility or liability for the
- * use of the software, conveys no license or title under any patent,
- * copyright, or mask work right to the product. Embedded Artists AB
- * reserves the right to make changes in the software without
- * notification. Embedded Artists AB also make no representation or
- * warranty that such application will be suitable for the specified
- * use without further testing or modification.
- *****************************************************************************/
-
-/*
- * NOTE: I2C must have been initialized before calling any functions in this
- * file.
- */
-
-/******************************************************************************
- * Includes
- *****************************************************************************/
-
-//#include "board.h"
-#include "chip.h"
-
-#include "pca9532.h"
-
-/******************************************************************************
- * Defines and typedefs
- *****************************************************************************/
-
-#define I2C_PORT (LPC_I2C0)
-
-#define LS_MODE_ON     0x01
-#define LS_MODE_BLINK0 0x02
-#define LS_MODE_BLINK1 0x03
-
-/******************************************************************************
- * External global variables
- *****************************************************************************/
-
-
-/******************************************************************************
- * Local variables
- *****************************************************************************/
-
-static uint16_t blink0Shadow = 0;
-static uint16_t blink1Shadow = 0;
-static uint16_t ledStateShadow = 0;
-
-/******************************************************************************
- * Local Functions
- *****************************************************************************/
-
-static Status I2CWrite(uint32_t addr, uint8_t* buf, uint32_t len) 
-{
-	I2CM_XFER_T i2cData;
-
-	i2cData.slaveAddr = addr;
-	i2cData.options = 0;
-	i2cData.status = 0;
-	i2cData.txBuff = buf;
-	i2cData.txSz = len;
-	i2cData.rxBuff = NULL;
-	i2cData.rxSz = 0;
-
-	if (Chip_I2CM_XferBlocking(LPC_I2C0, &i2cData) == 0) {
-		return ERROR;
-	}
-	return SUCCESS;
-}
-
-static Status I2CRead(uint32_t addr, uint8_t* buf, uint32_t len) 
-{
-	I2CM_XFER_T i2cData;
-
-	i2cData.slaveAddr = addr;
-	i2cData.options = 0;
-	i2cData.status = 0;
-	i2cData.txBuff = NULL;
-	i2cData.txSz = 0;
-	i2cData.rxBuff = buf;
-	i2cData.rxSz = len;
-
-	if (Chip_I2CM_XferBlocking(LPC_I2C0, &i2cData) == 0) {
-		return ERROR;
-	}
-	return SUCCESS;
-}
-
-static void setLsStates(uint16_t states, uint8_t* ls, uint8_t mode)
-{
-#define IS_LED_SET(bit, x) ( ( ((x) & (bit)) != 0 ) ? 1 : 0 )
-
-    int i = 0;
-
-    for (i = 0; i < 4; i++) {
-
-        ls[i] |= ( (IS_LED_SET(0x0001, states)*mode << 0)
-                | (IS_LED_SET(0x0002, states)*mode << 2)
-                | (IS_LED_SET(0x0004, states)*mode << 4)
-                | (IS_LED_SET(0x0008, states)*mode << 6) );
-
-        states >>= 4;
-    }
-}
-
-static void setLeds(void)
-{
-    uint8_t buf[5];
-    uint8_t ls[4] = {0,0,0,0};
-    uint16_t states = ledStateShadow;
-
-    /* LEDs in On/Off state */
-    setLsStates(states, ls, LS_MODE_ON);
-
-    /* set the LEDs that should blink */
-    setLsStates(blink0Shadow, ls, LS_MODE_BLINK0);
-    setLsStates(blink1Shadow, ls, LS_MODE_BLINK1);
-
-
-    buf[0] = PCA9532_LS0 | PCA9532_AUTO_INC;
-    buf[1] = ls[0];
-    buf[2] = ls[1];
-    buf[3] = ls[2];
-    buf[4] = ls[3];
-    I2CWrite(PCA9532_I2C_ADDR, buf, 5);
-}
-
-/******************************************************************************
- * Public Functions
- *****************************************************************************/
-
-/******************************************************************************
- *
- * Description:
- *    Initialize the PCA9532 Device
- *
- *****************************************************************************/
-void pca9532_init (void)
-{
-    /* nothing to initialize */
-}
-
-/******************************************************************************
- *
- * Description:
- *    Get the LED states
- *
- * Params:
- *    [in]  shadow  - TRUE if the states should be retrieved from the shadow
- *                    variables. The shadow variable are updated when any
- *                    of setLeds, setBlink0Leds and/or setBlink1Leds are
- *                    called.
- *
- *                    FALSE if the state should be retrieved from the PCA9532
- *                    device. A blinkin LED may be reported as on or off
- *                    depending on the state when calling the function.
- *
- * Returns:
- *      A mask where a 1 indicates that a LED is on (or blinking).
- *
- *****************************************************************************/
-uint16_t pca9532_getLedState (uint32_t shadow)
-{
-    uint8_t buf[2];
-    uint16_t ret = 0;
-
-    if (shadow) {
-        /* a blink LED is reported as on*/
-        ret = (ledStateShadow | blink0Shadow | blink1Shadow);
-    }
-    else {
-
-        /*
-         * A blinking LED may be reported as on or off depending on
-         * its state when reading the Input register.
-         */
-        
-        buf[0] = PCA9532_INPUT0;
-        I2CWrite(PCA9532_I2C_ADDR, buf, 1);
-
-        I2CRead(PCA9532_I2C_ADDR, buf, 1);
-        ret = buf[0];
-
-
-        buf[0] = PCA9532_INPUT1;
-        I2CWrite(PCA9532_I2C_ADDR, buf, 1);
-
-        I2CRead(PCA9532_I2C_ADDR, buf, 1);
-        ret |= (buf[0] << 8);
-
-
-        /* invert since LEDs are active low */
-        ret = ((~ret) & 0xFFFF);
-    }
-
-    return (ret & ~PCA9532_NOT_USED);
-}
-
-
-/******************************************************************************
- *
- * Description:
- *    Set LED states (on or off).
- *
- * Params:
- *    [in]  ledOnMask  - The LEDs that should be turned on. This mask has
- *                       priority over ledOffMask
- *    [in]  ledOffMask - The LEDs that should be turned off.
- *
- *****************************************************************************/
-void pca9532_setLeds (uint16_t ledOnMask, uint16_t ledOffMask)
-{
-    /* turn off leds */
-    ledStateShadow &= (~(ledOffMask) & 0xffff);
-
-    /* ledOnMask has priority over ledOffMask */
-    ledStateShadow |= ledOnMask;
-
-    /* turn off blinking */
-    blink0Shadow &= (~(ledOffMask) & 0xffff);
-    blink1Shadow &= (~(ledOffMask) & 0xffff);
-
-    setLeds();
-}
-
-/******************************************************************************
- *
- * Description:
- *    Set the blink period for PWM0. Valid values are 0 - 255 where 0
- *    means 152 Hz and 255 means 0.59 Hz. A value of 151 means 1 Hz.
- *
- * Params:
- *    [in]  period  - the period for pwm0
- *
- *****************************************************************************/
-void pca9532_setBlink0Period(uint8_t period)
-{
-    uint8_t buf[2];
-
-    buf[0] = PCA9532_PSC0;
-    buf[1] = period;
-    I2CWrite(PCA9532_I2C_ADDR, buf, 2);
-}
-
-/******************************************************************************
- *
- * Description:
- *    Set the duty cycle for PWM0. Valid values are 0 - 100. 25 means the LED
- *    is on 25% of the period.
- *
- * Params:
- *    [in]  duty  - duty cycle
- *
- *****************************************************************************/
-void pca9532_setBlink0Duty(uint8_t duty)
-{
-    uint8_t buf[2];
-    uint32_t tmp = duty;
-    if (tmp > 100) {
-        tmp = 100;
-    }
-
-    tmp = (256 * tmp)/100;
-
-    buf[0] = PCA9532_PWM0;
-    buf[1] = tmp;
-    I2CWrite(PCA9532_I2C_ADDR, buf, 2);
-}
-
-/******************************************************************************
- *
- * Description:
- *    Set the LEDs that should blink with rate and duty cycle from PWM0.
- *    Blinking is turned off with pca9532_setLeds.
- *
- * Params:
- *    [in]  ledMask  - LEDs that should blink.
- *
- *****************************************************************************/
-void pca9532_setBlink0Leds(uint16_t ledMask)
-{
-    blink0Shadow |= ledMask;
-    setLeds();
-}
-
-/******************************************************************************
- *
- * Description:
- *    Set the blink period for PWM1. Valid values are 0 - 255 where 0
- *    means 152 Hz and 255 means 0.59 Hz. A value of 151 means 1 Hz.
- *
- * Params:
- *    [in]  period  - The period for PWM1
- *
- *****************************************************************************/
-void pca9532_setBlink1Period(uint8_t period)
-{
-    uint8_t buf[2];
-
-    buf[0] = PCA9532_PSC1;
-    buf[1] = period;
-    I2CWrite(PCA9532_I2C_ADDR, buf, 2);
-}
-
-/******************************************************************************
- *
- * Description:
- *    Set the duty cycle for PWM1. Valid values are 0 - 100. 25 means the LED
- *    is on 25% of the period.
- *
- * Params:
- *    [in]  duty  - duty cycle.
- *
- *****************************************************************************/
-void pca9532_setBlink1Duty(uint8_t duty)
-{
-    uint8_t buf[2];
-
-    uint32_t tmp = duty;
-    if (tmp > 100) {
-        tmp = 100;
-    }
-
-    tmp = (256 * tmp)/100;
-
-    buf[0] = PCA9532_PWM1;
-    buf[1] = tmp;
-    I2CWrite(PCA9532_I2C_ADDR, buf, 2);
-}
-
-/******************************************************************************
- *
- * Description:
- *    Set the LEDs that should blink with rate and duty cycle from PWM1.
- *    Blinking is turned off with pca9532_setLeds.
- *
- * Params:
- *    [in]  ledMask  - LEDs that should blink.
- *
- *****************************************************************************/
-void pca9532_setBlink1Leds(uint16_t ledMask)
-{
-    blink1Shadow |= ledMask;
-    setLeds();
-}
diff --git a/tinyusb/hw/bsp/ea4357/pca9532.h b/tinyusb/hw/bsp/ea4357/pca9532.h
deleted file mode 100755
index 7a7c6e14..00000000
--- a/tinyusb/hw/bsp/ea4357/pca9532.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*****************************************************************************
- *
- *   Copyright(C) 2011, Embedded Artists AB
- *   All rights reserved.
- *
- ******************************************************************************
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * products. This software is supplied "AS IS" without any warranties.
- * Embedded Artists AB assumes no responsibility or liability for the
- * use of the software, conveys no license or title under any patent,
- * copyright, or mask work right to the product. Embedded Artists AB
- * reserves the right to make changes in the software without
- * notification. Embedded Artists AB also make no representation or
- * warranty that such application will be suitable for the specified
- * use without further testing or modification.
- *****************************************************************************/
-#ifndef __PCA9532C_H
-#define __PCA9532C_H
-
-
-#define PCA9532_I2C_ADDR    (0xC0>>1)
-
-#define PCA9532_INPUT0 0x00
-#define PCA9532_INPUT1 0x01
-#define PCA9532_PSC0   0x02
-#define PCA9532_PWM0   0x03
-#define PCA9532_PSC1   0x04
-#define PCA9532_PWM1   0x05
-#define PCA9532_LS0    0x06
-#define PCA9532_LS1    0x07
-#define PCA9532_LS2    0x08
-#define PCA9532_LS3    0x09
-
-#define PCA9532_AUTO_INC 0x10
-
-
-/*
- * The Keys on the base board are mapped to LED0 -> LED3 on
- * the PCA9532.
- */
-
-#define KEY1 0x0001
-#define KEY2 0x0002
-#define KEY3 0x0004
-#define KEY4 0x0008
-
-#define KEY_MASK 0x000F
-
-/*
- * MMC Card Detect and MMC Write Protect are mapped to LED4 
- * and LED5 on the PCA9532. Please note that WP is active low.
- */
-
-#define MMC_CD 0x0010
-#define MMC_WP 0x0020
-
-#define MMC_MASK  0x30
-
-/* NOTE: LED6 and LED7 on PCA9532 are not connected to anything */
-#define PCA9532_NOT_USED 0xC0
-
-/*
- * Below are the LED constants to use when enabling/disabling a LED.
- * The LED names are the names printed on the base board and not
- * the names from the PCA9532 device. base_LED1 -> LED8 on PCA9532,
- * base_LED2 -> LED9, and so on.
- */
-
-#define LED1 0x0100
-#define LED2 0x0200
-#define LED3 0x0400
-#define LED4 0x0800
-#define LED5 0x1000
-#define LED6 0x2000
-#define LED7 0x4000
-#define LED8 0x8000
-
-#define LED_MASK 0xFF00
-
-void pca9532_init (void);
-uint16_t pca9532_getLedState (uint32_t shadow);
-void pca9532_setLeds (uint16_t ledOnMask, uint16_t ledOffMask);
-void pca9532_setBlink0Period(uint8_t period);
-void pca9532_setBlink0Duty(uint8_t duty);
-void pca9532_setBlink0Leds(uint16_t ledMask);
-void pca9532_setBlink1Period(uint8_t period);
-void pca9532_setBlink1Duty(uint8_t duty);
-void pca9532_setBlink1Leds(uint16_t ledMask);
-
-#endif /* end __PCA9532C_H */
-/****************************************************************************
-**                            End Of File
-*****************************************************************************/
diff --git a/tinyusb/hw/bsp/esp32s2/boards/CMakeLists.txt b/tinyusb/hw/bsp/esp32s2/boards/CMakeLists.txt
deleted file mode 100755
index 71753012..00000000
--- a/tinyusb/hw/bsp/esp32s2/boards/CMakeLists.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-idf_component_register(SRCS esp32s2.c
-                    INCLUDE_DIRS "." "${BOARD}"
-                    PRIV_REQUIRES "driver"
-                    REQUIRES freertos src led_strip)
-
-# Apply board specific content
-include("${BOARD}/board.cmake")
-
-idf_component_get_property( FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH)
-target_include_directories(${COMPONENT_TARGET} PUBLIC
-  "${FREERTOS_ORIG_INCLUDE_PATH}"
-  "${TOP}/hw"
-  "${TOP}/src"  
-)
diff --git a/tinyusb/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.cmake b/tinyusb/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.cmake
deleted file mode 100755
index d3396267..00000000
--- a/tinyusb/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.cmake
+++ /dev/null
@@ -1,17 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-idf_build_get_property(idf_target IDF_TARGET)
-
-message(STATUS "Apply ${BOARD}(${idf_target}) specific options for component: ${COMPONENT_TARGET}")
-
-if(NOT ${idf_target} STREQUAL "esp32s2")
-    message(FATAL_ERROR "Incorrect target for board ${BOARD}: $ENV{IDF_TARGET}(${idf_target}), try to clean the build first." )
-endif()
-
-set(IDF_TARGET "esp32s2" FORCE)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
-  "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2"
-  "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.h b/tinyusb/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.h
deleted file mode 100755
index 43e00901..00000000
--- a/tinyusb/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define NEOPIXEL_PIN          33
-#define NEOPIXEL_POWER_PIN    21
-#define NEOPIXEL_POWER_STATE  1
-
-#define BUTTON_PIN            0
-#define BUTTON_STATE_ACTIVE   0
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.cmake b/tinyusb/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.cmake
deleted file mode 100755
index d3396267..00000000
--- a/tinyusb/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.cmake
+++ /dev/null
@@ -1,17 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-idf_build_get_property(idf_target IDF_TARGET)
-
-message(STATUS "Apply ${BOARD}(${idf_target}) specific options for component: ${COMPONENT_TARGET}")
-
-if(NOT ${idf_target} STREQUAL "esp32s2")
-    message(FATAL_ERROR "Incorrect target for board ${BOARD}: $ENV{IDF_TARGET}(${idf_target}), try to clean the build first." )
-endif()
-
-set(IDF_TARGET "esp32s2" FORCE)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
-  "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2"
-  "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.h b/tinyusb/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.h
deleted file mode 100755
index 16e30b68..00000000
--- a/tinyusb/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define NEOPIXEL_PIN          1
-#define NEOPIXEL_POWER_PIN    21
-#define NEOPIXEL_POWER_STATE  0
-
-#define BUTTON_PIN            0
-#define BUTTON_STATE_ACTIVE   0
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.cmake b/tinyusb/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.cmake
deleted file mode 100755
index d5c17b9b..00000000
--- a/tinyusb/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.cmake
+++ /dev/null
@@ -1,17 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-idf_build_get_property(idf_target IDF_TARGET)
-
-message(STATUS "Apply ${BOARD}(${idf_target}) specific options for component: ${COMPONENT_TARGET}")
-
-if(NOT ${idf_target} STREQUAL "esp32s2")
-    message(FATAL_ERROR "Incorrect target for board ${BOARD}: (${idf_target}), try to clean the build first." )
-endif()
-
-set(IDF_TARGET "esp32s2" FORCE)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
-  "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2"
-  "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.h b/tinyusb/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.h
deleted file mode 100755
index 49a2474b..00000000
--- a/tinyusb/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define NEOPIXEL_PIN          45
-
-#define BUTTON_PIN            0
-#define BUTTON_STATE_ACTIVE   0
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/esp32s2/boards/esp32s2.c b/tinyusb/hw/bsp/esp32s2/boards/esp32s2.c
deleted file mode 100755
index 358c0c80..00000000
--- a/tinyusb/hw/bsp/esp32s2/boards/esp32s2.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "../../board.h"
-#include "board.h"
-
-#include "esp_rom_gpio.h"
-#include "hal/gpio_ll.h"
-#include "hal/usb_hal.h"
-#include "soc/usb_periph.h"
-
-#include "driver/periph_ctrl.h"
-#include "driver/rmt.h"
-
-#ifdef NEOPIXEL_PIN
-#include "led_strip.h"
-static led_strip_t *strip;
-#endif
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-
-static void configure_pins(usb_hal_context_t *usb);
-
-// Initialize on-board peripherals : led, button, uart and USB
-void board_init(void)
-{
-
-#ifdef NEOPIXEL_PIN
-  #ifdef NEOPIXEL_POWER_PIN
-  gpio_reset_pin(NEOPIXEL_POWER_PIN);
-  gpio_set_direction(NEOPIXEL_POWER_PIN, GPIO_MODE_OUTPUT);
-  gpio_set_level(NEOPIXEL_POWER_PIN, NEOPIXEL_POWER_STATE);
-  #endif
-
-  // WS2812 Neopixel driver with RMT peripheral
-  rmt_config_t config = RMT_DEFAULT_CONFIG_TX(NEOPIXEL_PIN, RMT_CHANNEL_0);
-  config.clk_div = 2; // set counter clock to 40MHz
-
-  rmt_config(&config);
-  rmt_driver_install(config.channel, 0, 0);
-
-  led_strip_config_t strip_config = LED_STRIP_DEFAULT_CONFIG(1, (led_strip_dev_t) config.channel);
-  strip = led_strip_new_rmt_ws2812(&strip_config);
-  strip->clear(strip, 100); // off led
-#endif
-
-  // Button
-  gpio_pad_select_gpio(BUTTON_PIN);
-  gpio_set_direction(BUTTON_PIN, GPIO_MODE_INPUT);
-  gpio_set_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN_ONLY : GPIO_PULLUP_ONLY);
-
-  // USB Controller Hal init
-  periph_module_reset(PERIPH_USB_MODULE);
-  periph_module_enable(PERIPH_USB_MODULE);
-
-  usb_hal_context_t hal = {
-    .use_external_phy = false // use built-in PHY
-  };
-  usb_hal_init(&hal);
-  configure_pins(&hal);
-}
-
-static void configure_pins(usb_hal_context_t *usb)
-{
-  /* usb_periph_iopins currently configures USB_OTG as USB Device.
-   * Introduce additional parameters in usb_hal_context_t when adding support
-   * for USB Host.
-   */
-  for (const usb_iopin_dsc_t *iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) {
-    if ((usb->use_external_phy) || (iopin->ext_phy_only == 0)) {
-      esp_rom_gpio_pad_select_gpio(iopin->pin);
-      if (iopin->is_output) {
-        esp_rom_gpio_connect_out_signal(iopin->pin, iopin->func, false, false);
-      } else {
-        esp_rom_gpio_connect_in_signal(iopin->pin, iopin->func, false);
-        if ((iopin->pin != GPIO_FUNC_IN_LOW) && (iopin->pin != GPIO_FUNC_IN_HIGH)) {
-          gpio_ll_input_enable(&GPIO, iopin->pin);
-        }
-      }
-      esp_rom_gpio_pad_unhold(iopin->pin);
-    }
-  }
-  if (!usb->use_external_phy) {
-    gpio_set_drive_capability(USBPHY_DM_NUM, GPIO_DRIVE_CAP_3);
-    gpio_set_drive_capability(USBPHY_DP_NUM, GPIO_DRIVE_CAP_3);
-  }
-}
-
-// Turn LED on or off
-void board_led_write(bool state)
-{
-#ifdef NEOPIXEL_PIN
-  strip->set_pixel(strip, 0, (state ? 0x88 : 0x00), 0x00, 0x00);
-  strip->refresh(strip, 100);
-#endif
-}
-
-// Get the current state of button
-// a '1' means active (pressed), a '0' means inactive.
-uint32_t board_button_read(void)
-{
-  return gpio_get_level(BUTTON_PIN) == BUTTON_STATE_ACTIVE;
-}
-
-// Get characters from UART
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-// Send characters to UART
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
diff --git a/tinyusb/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.cmake b/tinyusb/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.cmake
deleted file mode 100755
index d5c17b9b..00000000
--- a/tinyusb/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.cmake
+++ /dev/null
@@ -1,17 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-idf_build_get_property(idf_target IDF_TARGET)
-
-message(STATUS "Apply ${BOARD}(${idf_target}) specific options for component: ${COMPONENT_TARGET}")
-
-if(NOT ${idf_target} STREQUAL "esp32s2")
-    message(FATAL_ERROR "Incorrect target for board ${BOARD}: (${idf_target}), try to clean the build first." )
-endif()
-
-set(IDF_TARGET "esp32s2" FORCE)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
-  "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2"
-  "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.h b/tinyusb/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.h
deleted file mode 100755
index 6bb44f76..00000000
--- a/tinyusb/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// Note: need to insert jumper next to WS2812 pixel
-#define NEOPIXEL_PIN          45
-
-#define BUTTON_PIN            0
-#define BUTTON_STATE_ACTIVE   0
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/esp32s2/boards/espressif_saola_1/board.cmake b/tinyusb/hw/bsp/esp32s2/boards/espressif_saola_1/board.cmake
deleted file mode 100755
index d5c17b9b..00000000
--- a/tinyusb/hw/bsp/esp32s2/boards/espressif_saola_1/board.cmake
+++ /dev/null
@@ -1,17 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-idf_build_get_property(idf_target IDF_TARGET)
-
-message(STATUS "Apply ${BOARD}(${idf_target}) specific options for component: ${COMPONENT_TARGET}")
-
-if(NOT ${idf_target} STREQUAL "esp32s2")
-    message(FATAL_ERROR "Incorrect target for board ${BOARD}: (${idf_target}), try to clean the build first." )
-endif()
-
-set(IDF_TARGET "esp32s2" FORCE)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
-  "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2"
-  "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/esp32s2/boards/espressif_saola_1/board.h b/tinyusb/hw/bsp/esp32s2/boards/espressif_saola_1/board.h
deleted file mode 100755
index f450b9a8..00000000
--- a/tinyusb/hw/bsp/esp32s2/boards/espressif_saola_1/board.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// Note: On the production version (v1.2) WS2812 is connected to GPIO 18,
-// however earlier revision v1.1 WS2812 is connected to GPIO 17
-#define NEOPIXEL_PIN          18
-
-#define BUTTON_PIN            0
-#define BUTTON_STATE_ACTIVE   0
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/esp32s2/components/led_strip/CMakeLists.txt b/tinyusb/hw/bsp/esp32s2/components/led_strip/CMakeLists.txt
deleted file mode 100755
index 6d0fcbc8..00000000
--- a/tinyusb/hw/bsp/esp32s2/components/led_strip/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-set(component_srcs "src/led_strip_rmt_ws2812.c")
-
-idf_component_register(SRCS "${component_srcs}"
-                       INCLUDE_DIRS "include"
-                       PRIV_INCLUDE_DIRS ""
-                       PRIV_REQUIRES "driver"
-                       REQUIRES "")
-
diff --git a/tinyusb/hw/bsp/esp32s2/components/led_strip/include/led_strip.h b/tinyusb/hw/bsp/esp32s2/components/led_strip/include/led_strip.h
deleted file mode 100755
index a9dffc32..00000000
--- a/tinyusb/hw/bsp/esp32s2/components/led_strip/include/led_strip.h
+++ /dev/null
@@ -1,126 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "esp_err.h"
-
-/**
-* @brief LED Strip Type
-*
-*/
-typedef struct led_strip_s led_strip_t;
-
-/**
-* @brief LED Strip Device Type
-*
-*/
-typedef void *led_strip_dev_t;
-
-/**
-* @brief Declare of LED Strip Type
-*
-*/
-struct led_strip_s {
-    /**
-    * @brief Set RGB for a specific pixel
-    *
-    * @param strip: LED strip
-    * @param index: index of pixel to set
-    * @param red: red part of color
-    * @param green: green part of color
-    * @param blue: blue part of color
-    *
-    * @return
-    *      - ESP_OK: Set RGB for a specific pixel successfully
-    *      - ESP_ERR_INVALID_ARG: Set RGB for a specific pixel failed because of invalid parameters
-    *      - ESP_FAIL: Set RGB for a specific pixel failed because other error occurred
-    */
-    esp_err_t (*set_pixel)(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue);
-
-    /**
-    * @brief Refresh memory colors to LEDs
-    *
-    * @param strip: LED strip
-    * @param timeout_ms: timeout value for refreshing task
-    *
-    * @return
-    *      - ESP_OK: Refresh successfully
-    *      - ESP_ERR_TIMEOUT: Refresh failed because of timeout
-    *      - ESP_FAIL: Refresh failed because some other error occurred
-    *
-    * @note:
-    *      After updating the LED colors in the memory, a following invocation of this API is needed to flush colors to strip.
-    */
-    esp_err_t (*refresh)(led_strip_t *strip, uint32_t timeout_ms);
-
-    /**
-    * @brief Clear LED strip (turn off all LEDs)
-    *
-    * @param strip: LED strip
-    * @param timeout_ms: timeout value for clearing task
-    *
-    * @return
-    *      - ESP_OK: Clear LEDs successfully
-    *      - ESP_ERR_TIMEOUT: Clear LEDs failed because of timeout
-    *      - ESP_FAIL: Clear LEDs failed because some other error occurred
-    */
-    esp_err_t (*clear)(led_strip_t *strip, uint32_t timeout_ms);
-
-    /**
-    * @brief Free LED strip resources
-    *
-    * @param strip: LED strip
-    *
-    * @return
-    *      - ESP_OK: Free resources successfully
-    *      - ESP_FAIL: Free resources failed because error occurred
-    */
-    esp_err_t (*del)(led_strip_t *strip);
-};
-
-/**
-* @brief LED Strip Configuration Type
-*
-*/
-typedef struct {
-    uint32_t max_leds;   /*!< Maximum LEDs in a single strip */
-    led_strip_dev_t dev; /*!< LED strip device (e.g. RMT channel, PWM channel, etc) */
-} led_strip_config_t;
-
-/**
- * @brief Default configuration for LED strip
- *
- */
-#define LED_STRIP_DEFAULT_CONFIG(number, dev_hdl) \
-    {                                             \
-        .max_leds = number,                       \
-        .dev = dev_hdl,                           \
-    }
-
-/**
-* @brief Install a new ws2812 driver (based on RMT peripheral)
-*
-* @param config: LED strip configuration
-* @return
-*      LED strip instance or NULL
-*/
-led_strip_t *led_strip_new_rmt_ws2812(const led_strip_config_t *config);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tinyusb/hw/bsp/esp32s2/components/led_strip/src/led_strip_rmt_ws2812.c b/tinyusb/hw/bsp/esp32s2/components/led_strip/src/led_strip_rmt_ws2812.c
deleted file mode 100755
index 025d3c59..00000000
--- a/tinyusb/hw/bsp/esp32s2/components/led_strip/src/led_strip_rmt_ws2812.c
+++ /dev/null
@@ -1,171 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#include <stdlib.h>
-#include <string.h>
-#include <sys/cdefs.h>
-#include "esp_log.h"
-#include "esp_attr.h"
-#include "led_strip.h"
-#include "driver/rmt.h"
-
-static const char *TAG = "ws2812";
-#define STRIP_CHECK(a, str, goto_tag, ret_value, ...)                             \
-    do                                                                            \
-    {                                                                             \
-        if (!(a))                                                                 \
-        {                                                                         \
-            ESP_LOGE(TAG, "%s(%d): " str, __FUNCTION__, __LINE__, ##__VA_ARGS__); \
-            ret = ret_value;                                                      \
-            goto goto_tag;                                                        \
-        }                                                                         \
-    } while (0)
-
-#define WS2812_T0H_NS (350)
-#define WS2812_T0L_NS (1000)
-#define WS2812_T1H_NS (1000)
-#define WS2812_T1L_NS (350)
-#define WS2812_RESET_US (280)
-
-static uint32_t ws2812_t0h_ticks = 0;
-static uint32_t ws2812_t1h_ticks = 0;
-static uint32_t ws2812_t0l_ticks = 0;
-static uint32_t ws2812_t1l_ticks = 0;
-
-typedef struct {
-    led_strip_t parent;
-    rmt_channel_t rmt_channel;
-    uint32_t strip_len;
-    uint8_t buffer[0];
-} ws2812_t;
-
-/**
- * @brief Conver RGB data to RMT format.
- *
- * @note For WS2812, R,G,B each contains 256 different choices (i.e. uint8_t)
- *
- * @param[in] src: source data, to converted to RMT format
- * @param[in] dest: place where to store the convert result
- * @param[in] src_size: size of source data
- * @param[in] wanted_num: number of RMT items that want to get
- * @param[out] translated_size: number of source data that got converted
- * @param[out] item_num: number of RMT items which are converted from source data
- */
-static void IRAM_ATTR ws2812_rmt_adapter(const void *src, rmt_item32_t *dest, size_t src_size,
-        size_t wanted_num, size_t *translated_size, size_t *item_num)
-{
-    if (src == NULL || dest == NULL) {
-        *translated_size = 0;
-        *item_num = 0;
-        return;
-    }
-    const rmt_item32_t bit0 = {{{ ws2812_t0h_ticks, 1, ws2812_t0l_ticks, 0 }}}; //Logical 0
-    const rmt_item32_t bit1 = {{{ ws2812_t1h_ticks, 1, ws2812_t1l_ticks, 0 }}}; //Logical 1
-    size_t size = 0;
-    size_t num = 0;
-    uint8_t *psrc = (uint8_t *)src;
-    rmt_item32_t *pdest = dest;
-    while (size < src_size && num < wanted_num) {
-        for (int i = 0; i < 8; i++) {
-            // MSB first
-            if (*psrc & (1 << (7 - i))) {
-                pdest->val =  bit1.val;
-            } else {
-                pdest->val =  bit0.val;
-            }
-            num++;
-            pdest++;
-        }
-        size++;
-        psrc++;
-    }
-    *translated_size = size;
-    *item_num = num;
-}
-
-static esp_err_t ws2812_set_pixel(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue)
-{
-    esp_err_t ret = ESP_OK;
-    ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
-    STRIP_CHECK(index < ws2812->strip_len, "index out of the maximum number of leds", err, ESP_ERR_INVALID_ARG);
-    uint32_t start = index * 3;
-    // In thr order of GRB
-    ws2812->buffer[start + 0] = green & 0xFF;
-    ws2812->buffer[start + 1] = red & 0xFF;
-    ws2812->buffer[start + 2] = blue & 0xFF;
-    return ESP_OK;
-err:
-    return ret;
-}
-
-static esp_err_t ws2812_refresh(led_strip_t *strip, uint32_t timeout_ms)
-{
-    esp_err_t ret = ESP_OK;
-    ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
-    STRIP_CHECK(rmt_write_sample(ws2812->rmt_channel, ws2812->buffer, ws2812->strip_len * 3, true) == ESP_OK,
-                "transmit RMT samples failed", err, ESP_FAIL);
-    return rmt_wait_tx_done(ws2812->rmt_channel, pdMS_TO_TICKS(timeout_ms));
-err:
-    return ret;
-}
-
-static esp_err_t ws2812_clear(led_strip_t *strip, uint32_t timeout_ms)
-{
-    ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
-    // Write zero to turn off all leds
-    memset(ws2812->buffer, 0, ws2812->strip_len * 3);
-    return ws2812_refresh(strip, timeout_ms);
-}
-
-static esp_err_t ws2812_del(led_strip_t *strip)
-{
-    ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
-    free(ws2812);
-    return ESP_OK;
-}
-
-led_strip_t *led_strip_new_rmt_ws2812(const led_strip_config_t *config)
-{
-    led_strip_t *ret = NULL;
-    STRIP_CHECK(config, "configuration can't be null", err, NULL);
-
-    // 24 bits per led
-    uint32_t ws2812_size = sizeof(ws2812_t) + config->max_leds * 3;
-    ws2812_t *ws2812 = calloc(1, ws2812_size);
-    STRIP_CHECK(ws2812, "request memory for ws2812 failed", err, NULL);
-
-    uint32_t counter_clk_hz = 0;
-    STRIP_CHECK(rmt_get_counter_clock((rmt_channel_t)config->dev, &counter_clk_hz) == ESP_OK,
-                "get rmt counter clock failed", err, NULL);
-    // ns -> ticks
-    float ratio = (float)counter_clk_hz / 1e9;
-    ws2812_t0h_ticks = (uint32_t)(ratio * WS2812_T0H_NS);
-    ws2812_t0l_ticks = (uint32_t)(ratio * WS2812_T0L_NS);
-    ws2812_t1h_ticks = (uint32_t)(ratio * WS2812_T1H_NS);
-    ws2812_t1l_ticks = (uint32_t)(ratio * WS2812_T1L_NS);
-
-    // set ws2812 to rmt adapter
-    rmt_translator_init((rmt_channel_t)config->dev, ws2812_rmt_adapter);
-
-    ws2812->rmt_channel = (rmt_channel_t)config->dev;
-    ws2812->strip_len = config->max_leds;
-
-    ws2812->parent.set_pixel = ws2812_set_pixel;
-    ws2812->parent.refresh = ws2812_refresh;
-    ws2812->parent.clear = ws2812_clear;
-    ws2812->parent.del = ws2812_del;
-
-    return &ws2812->parent;
-err:
-    return ret;
-}
diff --git a/tinyusb/hw/bsp/esp32s2/family.cmake b/tinyusb/hw/bsp/esp32s2/family.cmake
deleted file mode 100755
index f3d41d04..00000000
--- a/tinyusb/hw/bsp/esp32s2/family.cmake
+++ /dev/null
@@ -1,7 +0,0 @@
-cmake_minimum_required(VERSION 3.5)
-
-# Add example src and bsp directories
-set(EXTRA_COMPONENT_DIRS "src" "${TOP}/hw/bsp/esp32s2/boards" "${TOP}/hw/bsp/esp32s2/components")  
-include($ENV{IDF_PATH}/tools/cmake/project.cmake)
-set(SUPPORTED_TARGETS esp32s2)
-set(FAMILY_MCUS ESP32S2)
diff --git a/tinyusb/hw/bsp/esp32s2/family.mk b/tinyusb/hw/bsp/esp32s2/family.mk
deleted file mode 100755
index fb9b2164..00000000
--- a/tinyusb/hw/bsp/esp32s2/family.mk
+++ /dev/null
@@ -1,26 +0,0 @@
-#DEPS_SUBMODULES +=
-
-.PHONY: all clean flash bootloader-flash app-flash erase monitor dfu-flash dfu
-
-all:
-	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) -DIDF_TARGET=esp32s2 build
-
-build: all
-
-clean:
-	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) clean
-
-fullclean:
-	if test -f sdkconfig; then $(RM) -f sdkconfig ; fi
-	if test -d $(BUILD); then $(RM) -rf $(BUILD) ; fi
-
-flash bootloader-flash app-flash erase monitor dfu-flash dfu:
-	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) $@
-
-uf2: $(BUILD)/$(PROJECT).uf2
-
-UF2_FAMILY_ID = 0xbfdd4eee
-$(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).bin
-	@echo CREATE $@
-	$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID) -b 0x0 -c -o $@ $^
-
diff --git a/tinyusb/hw/bsp/esp32s3/boards/CMakeLists.txt b/tinyusb/hw/bsp/esp32s3/boards/CMakeLists.txt
deleted file mode 100755
index e1b921ae..00000000
--- a/tinyusb/hw/bsp/esp32s3/boards/CMakeLists.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-idf_component_register(SRCS esp32s3.c
-                    INCLUDE_DIRS "." "${BOARD}"
-                    PRIV_REQUIRES "driver"
-                    REQUIRES freertos src led_strip)
-
-# Apply board specific content
-include("${BOARD}/board.cmake")
-
-idf_component_get_property( FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH)
-target_include_directories(${COMPONENT_TARGET} PUBLIC
-  "${FREERTOS_ORIG_INCLUDE_PATH}"
-  "${TOP}/hw"
-  "${TOP}/src"  
-)
diff --git a/tinyusb/hw/bsp/esp32s3/boards/esp32s3.c b/tinyusb/hw/bsp/esp32s3/boards/esp32s3.c
deleted file mode 100755
index 358c0c80..00000000
--- a/tinyusb/hw/bsp/esp32s3/boards/esp32s3.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "../../board.h"
-#include "board.h"
-
-#include "esp_rom_gpio.h"
-#include "hal/gpio_ll.h"
-#include "hal/usb_hal.h"
-#include "soc/usb_periph.h"
-
-#include "driver/periph_ctrl.h"
-#include "driver/rmt.h"
-
-#ifdef NEOPIXEL_PIN
-#include "led_strip.h"
-static led_strip_t *strip;
-#endif
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-
-static void configure_pins(usb_hal_context_t *usb);
-
-// Initialize on-board peripherals : led, button, uart and USB
-void board_init(void)
-{
-
-#ifdef NEOPIXEL_PIN
-  #ifdef NEOPIXEL_POWER_PIN
-  gpio_reset_pin(NEOPIXEL_POWER_PIN);
-  gpio_set_direction(NEOPIXEL_POWER_PIN, GPIO_MODE_OUTPUT);
-  gpio_set_level(NEOPIXEL_POWER_PIN, NEOPIXEL_POWER_STATE);
-  #endif
-
-  // WS2812 Neopixel driver with RMT peripheral
-  rmt_config_t config = RMT_DEFAULT_CONFIG_TX(NEOPIXEL_PIN, RMT_CHANNEL_0);
-  config.clk_div = 2; // set counter clock to 40MHz
-
-  rmt_config(&config);
-  rmt_driver_install(config.channel, 0, 0);
-
-  led_strip_config_t strip_config = LED_STRIP_DEFAULT_CONFIG(1, (led_strip_dev_t) config.channel);
-  strip = led_strip_new_rmt_ws2812(&strip_config);
-  strip->clear(strip, 100); // off led
-#endif
-
-  // Button
-  gpio_pad_select_gpio(BUTTON_PIN);
-  gpio_set_direction(BUTTON_PIN, GPIO_MODE_INPUT);
-  gpio_set_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN_ONLY : GPIO_PULLUP_ONLY);
-
-  // USB Controller Hal init
-  periph_module_reset(PERIPH_USB_MODULE);
-  periph_module_enable(PERIPH_USB_MODULE);
-
-  usb_hal_context_t hal = {
-    .use_external_phy = false // use built-in PHY
-  };
-  usb_hal_init(&hal);
-  configure_pins(&hal);
-}
-
-static void configure_pins(usb_hal_context_t *usb)
-{
-  /* usb_periph_iopins currently configures USB_OTG as USB Device.
-   * Introduce additional parameters in usb_hal_context_t when adding support
-   * for USB Host.
-   */
-  for (const usb_iopin_dsc_t *iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) {
-    if ((usb->use_external_phy) || (iopin->ext_phy_only == 0)) {
-      esp_rom_gpio_pad_select_gpio(iopin->pin);
-      if (iopin->is_output) {
-        esp_rom_gpio_connect_out_signal(iopin->pin, iopin->func, false, false);
-      } else {
-        esp_rom_gpio_connect_in_signal(iopin->pin, iopin->func, false);
-        if ((iopin->pin != GPIO_FUNC_IN_LOW) && (iopin->pin != GPIO_FUNC_IN_HIGH)) {
-          gpio_ll_input_enable(&GPIO, iopin->pin);
-        }
-      }
-      esp_rom_gpio_pad_unhold(iopin->pin);
-    }
-  }
-  if (!usb->use_external_phy) {
-    gpio_set_drive_capability(USBPHY_DM_NUM, GPIO_DRIVE_CAP_3);
-    gpio_set_drive_capability(USBPHY_DP_NUM, GPIO_DRIVE_CAP_3);
-  }
-}
-
-// Turn LED on or off
-void board_led_write(bool state)
-{
-#ifdef NEOPIXEL_PIN
-  strip->set_pixel(strip, 0, (state ? 0x88 : 0x00), 0x00, 0x00);
-  strip->refresh(strip, 100);
-#endif
-}
-
-// Get the current state of button
-// a '1' means active (pressed), a '0' means inactive.
-uint32_t board_button_read(void)
-{
-  return gpio_get_level(BUTTON_PIN) == BUTTON_STATE_ACTIVE;
-}
-
-// Get characters from UART
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-// Send characters to UART
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
diff --git a/tinyusb/hw/bsp/esp32s3/boards/espressif_addax_1/board.cmake b/tinyusb/hw/bsp/esp32s3/boards/espressif_addax_1/board.cmake
deleted file mode 100755
index 60f7d19c..00000000
--- a/tinyusb/hw/bsp/esp32s3/boards/espressif_addax_1/board.cmake
+++ /dev/null
@@ -1,17 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-idf_build_get_property(idf_target IDF_TARGET)
-
-message(STATUS "Apply ${BOARD}(${idf_target}) specific options for component: ${COMPONENT_TARGET}")
-
-if(NOT ${idf_target} STREQUAL "esp32s3")
-    message(FATAL_ERROR "Incorrect target for board ${BOARD}: (${idf_target}), try to clean the build first." )
-endif()
-
-set(IDF_TARGET "esp32s3" FORCE)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
-  "-DCFG_TUSB_MCU=OPT_MCU_ESP32S3"
-  "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/esp32s3/boards/espressif_addax_1/board.h b/tinyusb/hw/bsp/esp32s3/boards/espressif_addax_1/board.h
deleted file mode 100755
index fff24ba4..00000000
--- a/tinyusb/hw/bsp/esp32s3/boards/espressif_addax_1/board.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// Note: On the production version (v1.1) WS2812 is connected to GPIO 47
-#define NEOPIXEL_PIN          47
-
-#define BUTTON_PIN            0
-#define BUTTON_STATE_ACTIVE   0
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/esp32s3/components/led_strip/CMakeLists.txt b/tinyusb/hw/bsp/esp32s3/components/led_strip/CMakeLists.txt
deleted file mode 100755
index 6d0fcbc8..00000000
--- a/tinyusb/hw/bsp/esp32s3/components/led_strip/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-set(component_srcs "src/led_strip_rmt_ws2812.c")
-
-idf_component_register(SRCS "${component_srcs}"
-                       INCLUDE_DIRS "include"
-                       PRIV_INCLUDE_DIRS ""
-                       PRIV_REQUIRES "driver"
-                       REQUIRES "")
-
diff --git a/tinyusb/hw/bsp/esp32s3/components/led_strip/include/led_strip.h b/tinyusb/hw/bsp/esp32s3/components/led_strip/include/led_strip.h
deleted file mode 100755
index a9dffc32..00000000
--- a/tinyusb/hw/bsp/esp32s3/components/led_strip/include/led_strip.h
+++ /dev/null
@@ -1,126 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "esp_err.h"
-
-/**
-* @brief LED Strip Type
-*
-*/
-typedef struct led_strip_s led_strip_t;
-
-/**
-* @brief LED Strip Device Type
-*
-*/
-typedef void *led_strip_dev_t;
-
-/**
-* @brief Declare of LED Strip Type
-*
-*/
-struct led_strip_s {
-    /**
-    * @brief Set RGB for a specific pixel
-    *
-    * @param strip: LED strip
-    * @param index: index of pixel to set
-    * @param red: red part of color
-    * @param green: green part of color
-    * @param blue: blue part of color
-    *
-    * @return
-    *      - ESP_OK: Set RGB for a specific pixel successfully
-    *      - ESP_ERR_INVALID_ARG: Set RGB for a specific pixel failed because of invalid parameters
-    *      - ESP_FAIL: Set RGB for a specific pixel failed because other error occurred
-    */
-    esp_err_t (*set_pixel)(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue);
-
-    /**
-    * @brief Refresh memory colors to LEDs
-    *
-    * @param strip: LED strip
-    * @param timeout_ms: timeout value for refreshing task
-    *
-    * @return
-    *      - ESP_OK: Refresh successfully
-    *      - ESP_ERR_TIMEOUT: Refresh failed because of timeout
-    *      - ESP_FAIL: Refresh failed because some other error occurred
-    *
-    * @note:
-    *      After updating the LED colors in the memory, a following invocation of this API is needed to flush colors to strip.
-    */
-    esp_err_t (*refresh)(led_strip_t *strip, uint32_t timeout_ms);
-
-    /**
-    * @brief Clear LED strip (turn off all LEDs)
-    *
-    * @param strip: LED strip
-    * @param timeout_ms: timeout value for clearing task
-    *
-    * @return
-    *      - ESP_OK: Clear LEDs successfully
-    *      - ESP_ERR_TIMEOUT: Clear LEDs failed because of timeout
-    *      - ESP_FAIL: Clear LEDs failed because some other error occurred
-    */
-    esp_err_t (*clear)(led_strip_t *strip, uint32_t timeout_ms);
-
-    /**
-    * @brief Free LED strip resources
-    *
-    * @param strip: LED strip
-    *
-    * @return
-    *      - ESP_OK: Free resources successfully
-    *      - ESP_FAIL: Free resources failed because error occurred
-    */
-    esp_err_t (*del)(led_strip_t *strip);
-};
-
-/**
-* @brief LED Strip Configuration Type
-*
-*/
-typedef struct {
-    uint32_t max_leds;   /*!< Maximum LEDs in a single strip */
-    led_strip_dev_t dev; /*!< LED strip device (e.g. RMT channel, PWM channel, etc) */
-} led_strip_config_t;
-
-/**
- * @brief Default configuration for LED strip
- *
- */
-#define LED_STRIP_DEFAULT_CONFIG(number, dev_hdl) \
-    {                                             \
-        .max_leds = number,                       \
-        .dev = dev_hdl,                           \
-    }
-
-/**
-* @brief Install a new ws2812 driver (based on RMT peripheral)
-*
-* @param config: LED strip configuration
-* @return
-*      LED strip instance or NULL
-*/
-led_strip_t *led_strip_new_rmt_ws2812(const led_strip_config_t *config);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tinyusb/hw/bsp/esp32s3/components/led_strip/src/led_strip_rmt_ws2812.c b/tinyusb/hw/bsp/esp32s3/components/led_strip/src/led_strip_rmt_ws2812.c
deleted file mode 100755
index 025d3c59..00000000
--- a/tinyusb/hw/bsp/esp32s3/components/led_strip/src/led_strip_rmt_ws2812.c
+++ /dev/null
@@ -1,171 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#include <stdlib.h>
-#include <string.h>
-#include <sys/cdefs.h>
-#include "esp_log.h"
-#include "esp_attr.h"
-#include "led_strip.h"
-#include "driver/rmt.h"
-
-static const char *TAG = "ws2812";
-#define STRIP_CHECK(a, str, goto_tag, ret_value, ...)                             \
-    do                                                                            \
-    {                                                                             \
-        if (!(a))                                                                 \
-        {                                                                         \
-            ESP_LOGE(TAG, "%s(%d): " str, __FUNCTION__, __LINE__, ##__VA_ARGS__); \
-            ret = ret_value;                                                      \
-            goto goto_tag;                                                        \
-        }                                                                         \
-    } while (0)
-
-#define WS2812_T0H_NS (350)
-#define WS2812_T0L_NS (1000)
-#define WS2812_T1H_NS (1000)
-#define WS2812_T1L_NS (350)
-#define WS2812_RESET_US (280)
-
-static uint32_t ws2812_t0h_ticks = 0;
-static uint32_t ws2812_t1h_ticks = 0;
-static uint32_t ws2812_t0l_ticks = 0;
-static uint32_t ws2812_t1l_ticks = 0;
-
-typedef struct {
-    led_strip_t parent;
-    rmt_channel_t rmt_channel;
-    uint32_t strip_len;
-    uint8_t buffer[0];
-} ws2812_t;
-
-/**
- * @brief Conver RGB data to RMT format.
- *
- * @note For WS2812, R,G,B each contains 256 different choices (i.e. uint8_t)
- *
- * @param[in] src: source data, to converted to RMT format
- * @param[in] dest: place where to store the convert result
- * @param[in] src_size: size of source data
- * @param[in] wanted_num: number of RMT items that want to get
- * @param[out] translated_size: number of source data that got converted
- * @param[out] item_num: number of RMT items which are converted from source data
- */
-static void IRAM_ATTR ws2812_rmt_adapter(const void *src, rmt_item32_t *dest, size_t src_size,
-        size_t wanted_num, size_t *translated_size, size_t *item_num)
-{
-    if (src == NULL || dest == NULL) {
-        *translated_size = 0;
-        *item_num = 0;
-        return;
-    }
-    const rmt_item32_t bit0 = {{{ ws2812_t0h_ticks, 1, ws2812_t0l_ticks, 0 }}}; //Logical 0
-    const rmt_item32_t bit1 = {{{ ws2812_t1h_ticks, 1, ws2812_t1l_ticks, 0 }}}; //Logical 1
-    size_t size = 0;
-    size_t num = 0;
-    uint8_t *psrc = (uint8_t *)src;
-    rmt_item32_t *pdest = dest;
-    while (size < src_size && num < wanted_num) {
-        for (int i = 0; i < 8; i++) {
-            // MSB first
-            if (*psrc & (1 << (7 - i))) {
-                pdest->val =  bit1.val;
-            } else {
-                pdest->val =  bit0.val;
-            }
-            num++;
-            pdest++;
-        }
-        size++;
-        psrc++;
-    }
-    *translated_size = size;
-    *item_num = num;
-}
-
-static esp_err_t ws2812_set_pixel(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue)
-{
-    esp_err_t ret = ESP_OK;
-    ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
-    STRIP_CHECK(index < ws2812->strip_len, "index out of the maximum number of leds", err, ESP_ERR_INVALID_ARG);
-    uint32_t start = index * 3;
-    // In thr order of GRB
-    ws2812->buffer[start + 0] = green & 0xFF;
-    ws2812->buffer[start + 1] = red & 0xFF;
-    ws2812->buffer[start + 2] = blue & 0xFF;
-    return ESP_OK;
-err:
-    return ret;
-}
-
-static esp_err_t ws2812_refresh(led_strip_t *strip, uint32_t timeout_ms)
-{
-    esp_err_t ret = ESP_OK;
-    ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
-    STRIP_CHECK(rmt_write_sample(ws2812->rmt_channel, ws2812->buffer, ws2812->strip_len * 3, true) == ESP_OK,
-                "transmit RMT samples failed", err, ESP_FAIL);
-    return rmt_wait_tx_done(ws2812->rmt_channel, pdMS_TO_TICKS(timeout_ms));
-err:
-    return ret;
-}
-
-static esp_err_t ws2812_clear(led_strip_t *strip, uint32_t timeout_ms)
-{
-    ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
-    // Write zero to turn off all leds
-    memset(ws2812->buffer, 0, ws2812->strip_len * 3);
-    return ws2812_refresh(strip, timeout_ms);
-}
-
-static esp_err_t ws2812_del(led_strip_t *strip)
-{
-    ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
-    free(ws2812);
-    return ESP_OK;
-}
-
-led_strip_t *led_strip_new_rmt_ws2812(const led_strip_config_t *config)
-{
-    led_strip_t *ret = NULL;
-    STRIP_CHECK(config, "configuration can't be null", err, NULL);
-
-    // 24 bits per led
-    uint32_t ws2812_size = sizeof(ws2812_t) + config->max_leds * 3;
-    ws2812_t *ws2812 = calloc(1, ws2812_size);
-    STRIP_CHECK(ws2812, "request memory for ws2812 failed", err, NULL);
-
-    uint32_t counter_clk_hz = 0;
-    STRIP_CHECK(rmt_get_counter_clock((rmt_channel_t)config->dev, &counter_clk_hz) == ESP_OK,
-                "get rmt counter clock failed", err, NULL);
-    // ns -> ticks
-    float ratio = (float)counter_clk_hz / 1e9;
-    ws2812_t0h_ticks = (uint32_t)(ratio * WS2812_T0H_NS);
-    ws2812_t0l_ticks = (uint32_t)(ratio * WS2812_T0L_NS);
-    ws2812_t1h_ticks = (uint32_t)(ratio * WS2812_T1H_NS);
-    ws2812_t1l_ticks = (uint32_t)(ratio * WS2812_T1L_NS);
-
-    // set ws2812 to rmt adapter
-    rmt_translator_init((rmt_channel_t)config->dev, ws2812_rmt_adapter);
-
-    ws2812->rmt_channel = (rmt_channel_t)config->dev;
-    ws2812->strip_len = config->max_leds;
-
-    ws2812->parent.set_pixel = ws2812_set_pixel;
-    ws2812->parent.refresh = ws2812_refresh;
-    ws2812->parent.clear = ws2812_clear;
-    ws2812->parent.del = ws2812_del;
-
-    return &ws2812->parent;
-err:
-    return ret;
-}
diff --git a/tinyusb/hw/bsp/esp32s3/family.cmake b/tinyusb/hw/bsp/esp32s3/family.cmake
deleted file mode 100755
index 511dd58b..00000000
--- a/tinyusb/hw/bsp/esp32s3/family.cmake
+++ /dev/null
@@ -1,7 +0,0 @@
-cmake_minimum_required(VERSION 3.5)
-
-# Add example src and bsp directories
-set(EXTRA_COMPONENT_DIRS "src" "${TOP}/hw/bsp/esp32s3/boards" "${TOP}/hw/bsp/esp32s3/components")  
-include($ENV{IDF_PATH}/tools/cmake/project.cmake)
-set(SUPPORTED_TARGETS esp32s3)
-set(FAMILY_MCUS ESP32S3)
diff --git a/tinyusb/hw/bsp/esp32s3/family.mk b/tinyusb/hw/bsp/esp32s3/family.mk
deleted file mode 100755
index cf153ffc..00000000
--- a/tinyusb/hw/bsp/esp32s3/family.mk
+++ /dev/null
@@ -1,26 +0,0 @@
-#DEPS_SUBMODULES +=
-
-.PHONY: all clean flash bootloader-flash app-flash erase monitor dfu-flash dfu
-
-all:
-	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) -DIDF_TARGET=esp32s3 build
-
-build: all
-
-clean:
-	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) clean
-
-fullclean:
-	if test -f sdkconfig; then $(RM) -f sdkconfig ; fi
-	if test -d $(BUILD); then $(RM) -rf $(BUILD) ; fi
-
-flash bootloader-flash app-flash erase monitor dfu-flash dfu:
-	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) $@
-
-uf2: $(BUILD)/$(PROJECT).uf2
-
-UF2_FAMILY_ID = 0xc47e5767
-$(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).bin
-	@echo CREATE $@
-	$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID) -b 0x0 -c -o $@ $^
-
diff --git a/tinyusb/hw/bsp/family_support.cmake b/tinyusb/hw/bsp/family_support.cmake
deleted file mode 100755
index af0e00b2..00000000
--- a/tinyusb/hw/bsp/family_support.cmake
+++ /dev/null
@@ -1,71 +0,0 @@
-if (NOT TARGET _family_support_marker)
-    add_library(_family_support_marker INTERFACE)
-
-    if (NOT FAMILY)
-        message(FATAL_ERROR "You must set a FAMILY variable for the build (e.g. rp2040, eps32s2, esp32s3). You can do this via -DFAMILY=xxx on the camke command line")
-    endif()
-
-    if (NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
-        message(FATAL_ERROR "Family '${FAMILY}' is not known/supported")
-    endif()
-
-    function(family_filter RESULT DIR)
-        get_filename_component(DIR ${DIR} ABSOLUTE BASE_DIR ${CMAKE_CURRENT_SOURCE_DIR})
-        file(GLOB ONLYS "${DIR}/.only.MCU_*")
-        if (ONLYS)
-            foreach(MCU IN LISTS FAMILY_MCUS)
-                if (EXISTS ${DIR}/.only.MCU_${MCU})
-                    set(${RESULT} 1 PARENT_SCOPE)
-                    return()
-                endif()
-            endforeach()
-        else()
-            foreach(MCU IN LISTS FAMILY_MCUS)
-                if (EXISTS ${DIR}/.skip.MCU_${MCU})
-                    set(${RESULT} 0 PARENT_SCOPE)
-                    return()
-                endif()
-            endforeach()
-        endif()
-        set(${RESULT} 1 PARENT_SCOPE)
-    endfunction()
-
-    function(family_add_subdirectory DIR)
-        family_filter(SHOULD_ADD "${DIR}")
-        if (SHOULD_ADD)
-            add_subdirectory(${DIR})
-        endif()
-    endfunction()
-
-    function(family_get_project_name OUTPUT_NAME DIR)
-        get_filename_component(SHORT_NAME ${DIR} NAME)
-        set(${OUTPUT_NAME} ${TINYUSB_FAMILY_PROJECT_NAME_PREFIX}${SHORT_NAME} PARENT_SCOPE)
-    endfunction()
-
-    function(family_initialize_project PROJECT DIR)
-        family_filter(ALLOWED "${DIR}")
-        if (NOT ALLOWED)
-            get_filename_component(SHORT_NAME ${DIR} NAME)
-            message(FATAL_ERROR "${SHORT_NAME} is not supported on FAMILY=${FAMILY}")
-        endif()
-    endfunction()
-
-    # configure an executable target to link to tinyusb in device mode, and add the board implementation
-    function(family_configure_device_example TARGET)
-        # default implentation is empty, the function should be redefined in the FAMILY/family.cmake
-    endfunction()
-
-    # configure an executable target to link to tinyusb in host mode, and add the board implementation
-    function(family_configure_host_example TARGET)
-        # default implentation is empty, the function should be redefined in the FAMILY/family.cmake
-    endfunction()
-
-    include(${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
-
-    if (NOT FAMILY_MCUS)
-        set(FAMILY_MCUS ${FAMILY})
-    endif()
-
-    # save it in case of re-inclusion
-    set(FAMILY_MCUS ${FAMILY_MCUS} CACHE INTERNAL "")
-endif()
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/fomu/boards/fomu/board.h b/tinyusb/hw/bsp/fomu/boards/fomu/board.h
deleted file mode 100755
index 666ba1d9..00000000
--- a/tinyusb/hw/bsp/fomu/boards/fomu/board.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// Place holder only
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif
diff --git a/tinyusb/hw/bsp/fomu/boards/fomu/board.mk b/tinyusb/hw/bsp/fomu/boards/fomu/board.mk
deleted file mode 100755
index 8ced1141..00000000
--- a/tinyusb/hw/bsp/fomu/boards/fomu/board.mk
+++ /dev/null
@@ -1 +0,0 @@
-# place holder
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/fomu/crt0-vexriscv.S b/tinyusb/hw/bsp/fomu/crt0-vexriscv.S
deleted file mode 100755
index d80a29e0..00000000
--- a/tinyusb/hw/bsp/fomu/crt0-vexriscv.S
+++ /dev/null
@@ -1,83 +0,0 @@
-.global main
-.global isr
-
-.section .text.start
-.global _start
-
-_start:
-  j crt_init
-
-.section .text
-.global  trap_entry
-trap_entry:
-  sw x1,  - 1*4(sp)
-  sw x5,  - 2*4(sp)
-  sw x6,  - 3*4(sp)
-  sw x7,  - 4*4(sp)
-  sw x10, - 5*4(sp)
-  sw x11, - 6*4(sp)
-  sw x12, - 7*4(sp)
-  sw x13, - 8*4(sp)
-  sw x14, - 9*4(sp)
-  sw x15, -10*4(sp)
-  sw x16, -11*4(sp)
-  sw x17, -12*4(sp)
-  sw x28, -13*4(sp)
-  sw x29, -14*4(sp)
-  sw x30, -15*4(sp)
-  sw x31, -16*4(sp)
-  addi sp,sp,-16*4
-  call isr
-  lw x1 , 15*4(sp)
-  lw x5,  14*4(sp)
-  lw x6,  13*4(sp)
-  lw x7,  12*4(sp)
-  lw x10, 11*4(sp)
-  lw x11, 10*4(sp)
-  lw x12,  9*4(sp)
-  lw x13,  8*4(sp)
-  lw x14,  7*4(sp)
-  lw x15,  6*4(sp)
-  lw x16,  5*4(sp)
-  lw x17,  4*4(sp)
-  lw x28,  3*4(sp)
-  lw x29,  2*4(sp)
-  lw x30,  1*4(sp)
-  lw x31,  0*4(sp)
-  addi sp,sp,16*4
-  mret
-
-.text
-crt_init:
-  la sp, _estack - 4
-  la a0, trap_entry
-  csrw mtvec, a0
-
-bss_init:
-  la a0, _sbss
-  la a1, _ebss + 4
-bss_loop:
-  beq a0,a1,bss_done
-  sw zero,0(a0)
-  add a0,a0,4
-  j bss_loop
-bss_done:
-
-  /* Load DATA */
-  la t0, _etext
-  la t1, _srelocate
-  la t2, _erelocate + 4
-3:
-  lw t3, 0(t0)
-  sw t3, 0(t1)
-  /* _edata is aligned to 4 bytes. Use word-xfers. */
-  addi t0, t0, 4
-  addi t1, t1, 4
-  bltu t1, t2, 3b
-
-  li a0, 0x880  //880 enable timer + external interrupt sources (until mstatus.MIE is set, they will never trigger an interrupt)
-  csrw mie,a0
-
-  call main
-infinite_loop:
-  j infinite_loop
diff --git a/tinyusb/hw/bsp/fomu/dfu.py b/tinyusb/hw/bsp/fomu/dfu.py
deleted file mode 100755
index 32479350..00000000
--- a/tinyusb/hw/bsp/fomu/dfu.py
+++ /dev/null
@@ -1,95 +0,0 @@
-#!/usr/bin/python
-
-# Written by Antonio Galea - 2010/11/18
-# Updated for DFU 1.1 by Sean Cross - 2020/03/31
-# Distributed under Gnu LGPL 3.0
-# see http://www.gnu.org/licenses/lgpl-3.0.txt
-
-import sys,struct,zlib,os
-from optparse import OptionParser
-
-DEFAULT_DEVICE="0x1209:0x5bf0"
-
-def named(tuple,names):
-  return dict(zip(names.split(),tuple))
-def consume(fmt,data,names):
-  n = struct.calcsize(fmt)
-  return named(struct.unpack(fmt,data[:n]),names),data[n:]
-def cstring(string):
-  return string.split('\0',1)[0]
-def compute_crc(data):
-  return 0xFFFFFFFF & -zlib.crc32(data) -1
-
-def parse(file,dump_images=False):
-  print ('File: "%s"' % file)
-  data = open(file,'rb').read()
-  crc = compute_crc(data[:-4])
-  data = data[len(data)-16:]
-  suffix = named(struct.unpack('<4H3sBI',data[:16]),'device product vendor dfu ufd len crc')
-  print ('usb: %(vendor)04x:%(product)04x, device: 0x%(device)04x, dfu: 0x%(dfu)04x, %(ufd)s, %(len)d, 0x%(crc)08x' % suffix)
-  if crc != suffix['crc']:
-    print ("CRC ERROR: computed crc32 is 0x%08x" % crc)
-  data = data[16:]
-  if data:
-    print ("PARSE ERROR")
-
-def build(file,data,device=DEFAULT_DEVICE):
-  # Parse the VID and PID from the `device` argument
-  v,d=map(lambda x: int(x,0) & 0xFFFF, device.split(':',1))
-
-  # Generate the DFU suffix, consisting of these fields:
-  #  Field name     | Length  |  Description
-  # ================+=========+================================
-  #  bcdDevice      |    2    | The release number of this firmware (0xffff - don't care)
-  #  idProduct      |    2    | PID of this device
-  #  idVendor       |    2    | VID of this device
-  #  bcdDFU         |    2    | Version of this DFU spec (0x01 0x00)
-  #  ucDfuSignature |    3    | The characters 'DFU', printed in reverse order
-  #  bLength        |    1    | The length of this suffix (16 bytes)
-  #  dwCRC          |    4    | A CRC32 of the data, including this suffix
-  data += struct.pack('<4H3sB',0xffff,d,v,0x0100,b'UFD',16)
-  crc   = compute_crc(data)
-  # Append the CRC32 of the entire block
-  data += struct.pack('<I',crc)
-  open(file,'wb').write(data)
-
-if __name__=="__main__":
-  usage = """
-%prog [-d|--dump] infile.dfu
-%prog {-b|--build} file.bin [{-D|--device}=vendor:device] outfile.dfu"""
-  parser = OptionParser(usage=usage)
-  parser.add_option("-b", "--build", action="store", dest="binfile",
-    help="build a DFU file from given BINFILE", metavar="BINFILE")
-  parser.add_option("-D", "--device", action="store", dest="device",
-    help="build for DEVICE, defaults to %s" % DEFAULT_DEVICE, metavar="DEVICE")
-  parser.add_option("-d", "--dump", action="store_true", dest="dump_images",
-    default=False, help="dump contained images to current directory")
-  (options, args) = parser.parse_args()
-
-  if options.binfile and len(args)==1:
-    binfile = options.binfile
-    if not os.path.isfile(binfile):
-      print ("Unreadable file '%s'." % binfile)
-      sys.exit(1)
-    target = open(binfile,'rb').read()
-    outfile = args[0]
-    device = DEFAULT_DEVICE
-    # If a device is specified, parse the pair into a VID:PID pair
-    # in order to validate them.
-    if options.device:
-      device=options.device
-    try:
-      v,d=map(lambda x: int(x,0) & 0xFFFF, device.split(':',1))
-    except:
-      print ("Invalid device '%s'." % device)
-      sys.exit(1)
-    build(outfile,target,device)
-  elif len(args)==1:
-    infile = args[0]
-    if not os.path.isfile(infile):
-      print ("Unreadable file '%s'." % infile)
-      sys.exit(1)
-    parse(infile, dump_images=options.dump_images)
-  else:
-    parser.print_help()
-    sys.exit(1)
diff --git a/tinyusb/hw/bsp/fomu/family.mk b/tinyusb/hw/bsp/fomu/family.mk
deleted file mode 100755
index 165535c6..00000000
--- a/tinyusb/hw/bsp/fomu/family.mk
+++ /dev/null
@@ -1,30 +0,0 @@
-CFLAGS += \
-  -flto \
-  -march=rv32i \
-  -mabi=ilp32 \
-  -nostdlib \
-  -DCFG_TUSB_MCU=OPT_MCU_VALENTYUSB_EPTRI
-
-# Toolchain from https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack
-CROSS_COMPILE = riscv-none-embed-
-
-# All source paths should be relative to the top level.
-LD_FILE = $(FAMILY_PATH)/fomu.ld
-
-SRC_C += src/portable/valentyusb/eptri/dcd_eptri.c
-
-SRC_S += $(FAMILY_PATH)/crt0-vexriscv.S
-
-INC += \
-	$(TOP)/$(FAMILY_PATH)/include
-
-# For freeRTOS port source
-FREERTOS_PORT = RISC-V
-
-# flash using dfu-util
-$(BUILD)/$(PROJECT).dfu: $(BUILD)/$(PROJECT).bin
-	@echo "Create $@"
-	python $(TOP)/hw/bsp/$(BOARD)/dfu.py -b $^ -D 0x1209:0x5bf0 $@
-	
-flash: $(BUILD)/$(PROJECT).dfu
-	dfu-util -D $^
diff --git a/tinyusb/hw/bsp/fomu/fomu.c b/tinyusb/hw/bsp/fomu/fomu.c
deleted file mode 100755
index 25e5e961..00000000
--- a/tinyusb/hw/bsp/fomu/fomu.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "../board.h"
-#include "csr.h"
-#include "irq.h"
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void fomu_error(uint32_t line)
-{
-  (void)line;
-  TU_BREAKPOINT();
-}
-
-volatile uint32_t system_ticks = 0;
-static void timer_init(void)
-{
-	int t;
-
-	timer0_en_write(0);
-	t = CONFIG_CLOCK_FREQUENCY / 1000; // 1000 kHz tick
-	timer0_reload_write(t);
-	timer0_load_write(t);
-	timer0_en_write(1);
-  timer0_ev_enable_write(1);
-  timer0_ev_pending_write(1);
-	irq_setmask(irq_getmask() | (1 << TIMER0_INTERRUPT));
-}
-
-void isr(void)
-{
-  unsigned int irqs;
-
-  irqs = irq_pending() & irq_getmask();
-
-#if CFG_TUSB_RHPORT0_MODE == OPT_MODE_DEVICE
-  if (irqs & (1 << USB_INTERRUPT)) {
-    tud_int_handler(0);
-  }
-#endif
-  if (irqs & (1 << TIMER0_INTERRUPT)) {
-    system_ticks++;
-    timer0_ev_pending_write(1);
-  }
-}
-
-void board_init(void)
-{
-  irq_setmask(0);
-  irq_setie(1);
-  timer_init();
-  return;
-}
-
-void board_led_write(bool state)
-{
-  rgb_ctrl_write(0xff);
-  rgb_raw_write(state);
-}
-
-uint32_t board_button_read(void)
-{
-  return 0;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf;
-  (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  int32_t offset = 0;
-  for (offset = 0; offset < len; offset++)
-    if (! (messible_status_read() & CSR_MESSIBLE_STATUS_FULL_OFFSET))
-      messible_in_write(((uint8_t *)buf)[offset]);
-  return len;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/tinyusb/hw/bsp/fomu/fomu.ld b/tinyusb/hw/bsp/fomu/fomu.ld
deleted file mode 100755
index 13278d2a..00000000
--- a/tinyusb/hw/bsp/fomu/fomu.ld
+++ /dev/null
@@ -1,104 +0,0 @@
-OUTPUT_FORMAT("elf32-littleriscv")
-ENTRY(_start)
-
-__DYNAMIC = 0;
-
-MEMORY {
-	csr : ORIGIN = 0x60000000, LENGTH = 0x01000000
-	vexriscv_debug : ORIGIN = 0xf00f0000, LENGTH = 0x00000100
-	ram : ORIGIN = 0x10000000, LENGTH = 0x00020000
-	rom : ORIGIN = 0x20040000, LENGTH = 0x00200000 - 0x40000
-}
-
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
-
-/* Section Definitions */
-SECTIONS
-{
-    .text :
-    {
-        . = ALIGN(4);
-        _ftext = .;
-		*(.text.start)
-        *(.text .text.* .gnu.linkonce.t.*)
-        *(.glue_7t) *(.glue_7)
-        *(.rodata .rodata* .gnu.linkonce.r.*)
-
-        /* Support C constructors, and C destructors in both user code
-           and the C library. This also provides support for C++ code. */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-
-        . = ALIGN(4);
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-
-        . = ALIGN(4);
-        KEEP(*(.fini))
-
-        . = ALIGN(4);
-        __fini_array_start = .;
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        __fini_array_end = .;
-
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-    } > rom
-
-    . = ALIGN(4);
-    _etext = .;            /* End of text section */
-
-    .relocate : AT (_etext)
-    {
-        . = ALIGN(4);
-        _srelocate = .;
-        *(.ramfunc .ramfunc.*);
-        *(.data .data.*);
-        . = ALIGN(4);
-        _erelocate = .;
-    } > ram
-
-    /* .bss section which is used for uninitialized data */
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        _sbss = . ;
-        _szero = .;
-        *(.bss .bss.*)
-        *(.sbss .sbss.*)
-        *(COMMON)
-        . = ALIGN(4);
-        _ebss = . ;
-        _ezero = .;
-        end = .;
-    } > ram
-
-    /* stack section */
-    .stack (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sstack = .;
-        . = . + STACK_SIZE;
-        . = ALIGN(8);
-        _estack = .;
-    } > ram
-
-    . = ALIGN(4);
-    _end = . ;
-}
diff --git a/tinyusb/hw/bsp/fomu/include/csr.h b/tinyusb/hw/bsp/fomu/include/csr.h
deleted file mode 100755
index a2f60ecf..00000000
--- a/tinyusb/hw/bsp/fomu/include/csr.h
+++ /dev/null
@@ -1,750 +0,0 @@
-//--------------------------------------------------------------------------------
-// Auto-generated by Migen (f4fcd10) & LiteX (1425a68d) on 2019-11-12 19:41:49
-//--------------------------------------------------------------------------------
-#ifndef __GENERATED_CSR_H
-#define __GENERATED_CSR_H
-#include <stdint.h>
-#ifdef CSR_ACCESSORS_DEFINED
-extern void csr_writeb(uint8_t value, unsigned long addr);
-extern uint8_t csr_readb(unsigned long addr);
-extern void csr_writew(uint16_t value, unsigned long addr);
-extern uint16_t csr_readw(unsigned long addr);
-extern void csr_writel(uint32_t value, unsigned long addr);
-extern uint32_t csr_readl(unsigned long addr);
-#else /* ! CSR_ACCESSORS_DEFINED */
-#include <hw/common.h>
-#endif /* ! CSR_ACCESSORS_DEFINED */
-
-/* ctrl */
-#define CSR_CTRL_BASE 0xe0000000L
-#define CSR_CTRL_RESET_ADDR 0xe0000000L
-#define CSR_CTRL_RESET_SIZE 1
-static inline unsigned char ctrl_reset_read(void) {
-	unsigned char r = csr_readl(0xe0000000L);
-	return r;
-}
-static inline void ctrl_reset_write(unsigned char value) {
-	csr_writel(value, 0xe0000000L);
-}
-#define CSR_CTRL_SCRATCH_ADDR 0xe0000004L
-#define CSR_CTRL_SCRATCH_SIZE 4
-static inline unsigned int ctrl_scratch_read(void) {
-	unsigned int r = csr_readl(0xe0000004L);
-	r <<= 8;
-	r |= csr_readl(0xe0000008L);
-	r <<= 8;
-	r |= csr_readl(0xe000000cL);
-	r <<= 8;
-	r |= csr_readl(0xe0000010L);
-	return r;
-}
-static inline void ctrl_scratch_write(unsigned int value) {
-	csr_writel(value >> 24, 0xe0000004L);
-	csr_writel(value >> 16, 0xe0000008L);
-	csr_writel(value >> 8, 0xe000000cL);
-	csr_writel(value, 0xe0000010L);
-}
-#define CSR_CTRL_BUS_ERRORS_ADDR 0xe0000014L
-#define CSR_CTRL_BUS_ERRORS_SIZE 4
-static inline unsigned int ctrl_bus_errors_read(void) {
-	unsigned int r = csr_readl(0xe0000014L);
-	r <<= 8;
-	r |= csr_readl(0xe0000018L);
-	r <<= 8;
-	r |= csr_readl(0xe000001cL);
-	r <<= 8;
-	r |= csr_readl(0xe0000020L);
-	return r;
-}
-
-/* messible */
-#define CSR_MESSIBLE_BASE 0xe0008000L
-#define CSR_MESSIBLE_IN_ADDR 0xe0008000L
-#define CSR_MESSIBLE_IN_SIZE 1
-static inline unsigned char messible_in_read(void) {
-	unsigned char r = csr_readl(0xe0008000L);
-	return r;
-}
-static inline void messible_in_write(unsigned char value) {
-	csr_writel(value, 0xe0008000L);
-}
-#define CSR_MESSIBLE_OUT_ADDR 0xe0008004L
-#define CSR_MESSIBLE_OUT_SIZE 1
-static inline unsigned char messible_out_read(void) {
-	unsigned char r = csr_readl(0xe0008004L);
-	return r;
-}
-#define CSR_MESSIBLE_STATUS_ADDR 0xe0008008L
-#define CSR_MESSIBLE_STATUS_SIZE 1
-static inline unsigned char messible_status_read(void) {
-	unsigned char r = csr_readl(0xe0008008L);
-	return r;
-}
-#define CSR_MESSIBLE_STATUS_FULL_OFFSET 0
-#define CSR_MESSIBLE_STATUS_FULL_SIZE 1
-#define CSR_MESSIBLE_STATUS_HAVE_OFFSET 1
-#define CSR_MESSIBLE_STATUS_HAVE_SIZE 1
-
-/* picorvspi */
-#define CSR_PICORVSPI_BASE 0xe0005000L
-#define CSR_PICORVSPI_CFG1_ADDR 0xe0005000L
-#define CSR_PICORVSPI_CFG1_SIZE 1
-static inline unsigned char picorvspi_cfg1_read(void) {
-	unsigned char r = csr_readl(0xe0005000L);
-	return r;
-}
-static inline void picorvspi_cfg1_write(unsigned char value) {
-	csr_writel(value, 0xe0005000L);
-}
-#define CSR_PICORVSPI_CFG1_BB_OUT_OFFSET 0
-#define CSR_PICORVSPI_CFG1_BB_OUT_SIZE 4
-#define CSR_PICORVSPI_CFG1_BB_CLK_OFFSET 4
-#define CSR_PICORVSPI_CFG1_BB_CLK_SIZE 1
-#define CSR_PICORVSPI_CFG1_BB_CS_OFFSET 5
-#define CSR_PICORVSPI_CFG1_BB_CS_SIZE 1
-#define CSR_PICORVSPI_CFG2_ADDR 0xe0005004L
-#define CSR_PICORVSPI_CFG2_SIZE 1
-static inline unsigned char picorvspi_cfg2_read(void) {
-	unsigned char r = csr_readl(0xe0005004L);
-	return r;
-}
-static inline void picorvspi_cfg2_write(unsigned char value) {
-	csr_writel(value, 0xe0005004L);
-}
-#define CSR_PICORVSPI_CFG2_BB_OE_OFFSET 0
-#define CSR_PICORVSPI_CFG2_BB_OE_SIZE 4
-#define CSR_PICORVSPI_CFG3_ADDR 0xe0005008L
-#define CSR_PICORVSPI_CFG3_SIZE 1
-static inline unsigned char picorvspi_cfg3_read(void) {
-	unsigned char r = csr_readl(0xe0005008L);
-	return r;
-}
-static inline void picorvspi_cfg3_write(unsigned char value) {
-	csr_writel(value, 0xe0005008L);
-}
-#define CSR_PICORVSPI_CFG3_RLAT_OFFSET 0
-#define CSR_PICORVSPI_CFG3_RLAT_SIZE 4
-#define CSR_PICORVSPI_CFG3_CRM_OFFSET 4
-#define CSR_PICORVSPI_CFG3_CRM_SIZE 1
-#define CSR_PICORVSPI_CFG3_QSPI_OFFSET 5
-#define CSR_PICORVSPI_CFG3_QSPI_SIZE 1
-#define CSR_PICORVSPI_CFG3_DDR_OFFSET 6
-#define CSR_PICORVSPI_CFG3_DDR_SIZE 1
-#define CSR_PICORVSPI_CFG4_ADDR 0xe000500cL
-#define CSR_PICORVSPI_CFG4_SIZE 1
-static inline unsigned char picorvspi_cfg4_read(void) {
-	unsigned char r = csr_readl(0xe000500cL);
-	return r;
-}
-static inline void picorvspi_cfg4_write(unsigned char value) {
-	csr_writel(value, 0xe000500cL);
-}
-#define CSR_PICORVSPI_CFG4_MEMIO_OFFSET 7
-#define CSR_PICORVSPI_CFG4_MEMIO_SIZE 1
-#define CSR_PICORVSPI_STAT1_ADDR 0xe0005010L
-#define CSR_PICORVSPI_STAT1_SIZE 1
-static inline unsigned char picorvspi_stat1_read(void) {
-	unsigned char r = csr_readl(0xe0005010L);
-	return r;
-}
-#define CSR_PICORVSPI_STAT1_BB_IN_OFFSET 0
-#define CSR_PICORVSPI_STAT1_BB_IN_SIZE 4
-#define CSR_PICORVSPI_STAT2_ADDR 0xe0005014L
-#define CSR_PICORVSPI_STAT2_SIZE 1
-static inline unsigned char picorvspi_stat2_read(void) {
-	unsigned char r = csr_readl(0xe0005014L);
-	return r;
-}
-#define CSR_PICORVSPI_STAT3_ADDR 0xe0005018L
-#define CSR_PICORVSPI_STAT3_SIZE 1
-static inline unsigned char picorvspi_stat3_read(void) {
-	unsigned char r = csr_readl(0xe0005018L);
-	return r;
-}
-#define CSR_PICORVSPI_STAT4_ADDR 0xe000501cL
-#define CSR_PICORVSPI_STAT4_SIZE 1
-static inline unsigned char picorvspi_stat4_read(void) {
-	unsigned char r = csr_readl(0xe000501cL);
-	return r;
-}
-
-/* reboot */
-#define CSR_REBOOT_BASE 0xe0006000L
-#define CSR_REBOOT_CTRL_ADDR 0xe0006000L
-#define CSR_REBOOT_CTRL_SIZE 1
-static inline unsigned char reboot_ctrl_read(void) {
-	unsigned char r = csr_readl(0xe0006000L);
-	return r;
-}
-static inline void reboot_ctrl_write(unsigned char value) {
-	csr_writel(value, 0xe0006000L);
-}
-#define CSR_REBOOT_CTRL_IMAGE_OFFSET 0
-#define CSR_REBOOT_CTRL_IMAGE_SIZE 2
-#define CSR_REBOOT_CTRL_KEY_OFFSET 2
-#define CSR_REBOOT_CTRL_KEY_SIZE 6
-#define CSR_REBOOT_ADDR_ADDR 0xe0006004L
-#define CSR_REBOOT_ADDR_SIZE 4
-static inline unsigned int reboot_addr_read(void) {
-	unsigned int r = csr_readl(0xe0006004L);
-	r <<= 8;
-	r |= csr_readl(0xe0006008L);
-	r <<= 8;
-	r |= csr_readl(0xe000600cL);
-	r <<= 8;
-	r |= csr_readl(0xe0006010L);
-	return r;
-}
-static inline void reboot_addr_write(unsigned int value) {
-	csr_writel(value >> 24, 0xe0006004L);
-	csr_writel(value >> 16, 0xe0006008L);
-	csr_writel(value >> 8, 0xe000600cL);
-	csr_writel(value, 0xe0006010L);
-}
-
-/* rgb */
-#define CSR_RGB_BASE 0xe0006800L
-#define CSR_RGB_DAT_ADDR 0xe0006800L
-#define CSR_RGB_DAT_SIZE 1
-static inline unsigned char rgb_dat_read(void) {
-	unsigned char r = csr_readl(0xe0006800L);
-	return r;
-}
-static inline void rgb_dat_write(unsigned char value) {
-	csr_writel(value, 0xe0006800L);
-}
-#define CSR_RGB_ADDR_ADDR 0xe0006804L
-#define CSR_RGB_ADDR_SIZE 1
-static inline unsigned char rgb_addr_read(void) {
-	unsigned char r = csr_readl(0xe0006804L);
-	return r;
-}
-static inline void rgb_addr_write(unsigned char value) {
-	csr_writel(value, 0xe0006804L);
-}
-#define CSR_RGB_CTRL_ADDR 0xe0006808L
-#define CSR_RGB_CTRL_SIZE 1
-static inline unsigned char rgb_ctrl_read(void) {
-	unsigned char r = csr_readl(0xe0006808L);
-	return r;
-}
-static inline void rgb_ctrl_write(unsigned char value) {
-	csr_writel(value, 0xe0006808L);
-}
-#define CSR_RGB_CTRL_EXE_OFFSET 0
-#define CSR_RGB_CTRL_EXE_SIZE 1
-#define CSR_RGB_CTRL_CURREN_OFFSET 1
-#define CSR_RGB_CTRL_CURREN_SIZE 1
-#define CSR_RGB_CTRL_RGBLEDEN_OFFSET 2
-#define CSR_RGB_CTRL_RGBLEDEN_SIZE 1
-#define CSR_RGB_CTRL_RRAW_OFFSET 3
-#define CSR_RGB_CTRL_RRAW_SIZE 1
-#define CSR_RGB_CTRL_GRAW_OFFSET 4
-#define CSR_RGB_CTRL_GRAW_SIZE 1
-#define CSR_RGB_CTRL_BRAW_OFFSET 5
-#define CSR_RGB_CTRL_BRAW_SIZE 1
-#define CSR_RGB_RAW_ADDR 0xe000680cL
-#define CSR_RGB_RAW_SIZE 1
-static inline unsigned char rgb_raw_read(void) {
-	unsigned char r = csr_readl(0xe000680cL);
-	return r;
-}
-static inline void rgb_raw_write(unsigned char value) {
-	csr_writel(value, 0xe000680cL);
-}
-#define CSR_RGB_RAW_R_OFFSET 0
-#define CSR_RGB_RAW_R_SIZE 1
-#define CSR_RGB_RAW_G_OFFSET 1
-#define CSR_RGB_RAW_G_SIZE 1
-#define CSR_RGB_RAW_B_OFFSET 2
-#define CSR_RGB_RAW_B_SIZE 1
-
-/* timer0 */
-#define CSR_TIMER0_BASE 0xe0002800L
-#define CSR_TIMER0_LOAD_ADDR 0xe0002800L
-#define CSR_TIMER0_LOAD_SIZE 4
-static inline unsigned int timer0_load_read(void) {
-	unsigned int r = csr_readl(0xe0002800L);
-	r <<= 8;
-	r |= csr_readl(0xe0002804L);
-	r <<= 8;
-	r |= csr_readl(0xe0002808L);
-	r <<= 8;
-	r |= csr_readl(0xe000280cL);
-	return r;
-}
-static inline void timer0_load_write(unsigned int value) {
-	csr_writel(value >> 24, 0xe0002800L);
-	csr_writel(value >> 16, 0xe0002804L);
-	csr_writel(value >> 8, 0xe0002808L);
-	csr_writel(value, 0xe000280cL);
-}
-#define CSR_TIMER0_RELOAD_ADDR 0xe0002810L
-#define CSR_TIMER0_RELOAD_SIZE 4
-static inline unsigned int timer0_reload_read(void) {
-	unsigned int r = csr_readl(0xe0002810L);
-	r <<= 8;
-	r |= csr_readl(0xe0002814L);
-	r <<= 8;
-	r |= csr_readl(0xe0002818L);
-	r <<= 8;
-	r |= csr_readl(0xe000281cL);
-	return r;
-}
-static inline void timer0_reload_write(unsigned int value) {
-	csr_writel(value >> 24, 0xe0002810L);
-	csr_writel(value >> 16, 0xe0002814L);
-	csr_writel(value >> 8, 0xe0002818L);
-	csr_writel(value, 0xe000281cL);
-}
-#define CSR_TIMER0_EN_ADDR 0xe0002820L
-#define CSR_TIMER0_EN_SIZE 1
-static inline unsigned char timer0_en_read(void) {
-	unsigned char r = csr_readl(0xe0002820L);
-	return r;
-}
-static inline void timer0_en_write(unsigned char value) {
-	csr_writel(value, 0xe0002820L);
-}
-#define CSR_TIMER0_UPDATE_VALUE_ADDR 0xe0002824L
-#define CSR_TIMER0_UPDATE_VALUE_SIZE 1
-static inline unsigned char timer0_update_value_read(void) {
-	unsigned char r = csr_readl(0xe0002824L);
-	return r;
-}
-static inline void timer0_update_value_write(unsigned char value) {
-	csr_writel(value, 0xe0002824L);
-}
-#define CSR_TIMER0_VALUE_ADDR 0xe0002828L
-#define CSR_TIMER0_VALUE_SIZE 4
-static inline unsigned int timer0_value_read(void) {
-	unsigned int r = csr_readl(0xe0002828L);
-	r <<= 8;
-	r |= csr_readl(0xe000282cL);
-	r <<= 8;
-	r |= csr_readl(0xe0002830L);
-	r <<= 8;
-	r |= csr_readl(0xe0002834L);
-	return r;
-}
-#define CSR_TIMER0_EV_STATUS_ADDR 0xe0002838L
-#define CSR_TIMER0_EV_STATUS_SIZE 1
-static inline unsigned char timer0_ev_status_read(void) {
-	unsigned char r = csr_readl(0xe0002838L);
-	return r;
-}
-static inline void timer0_ev_status_write(unsigned char value) {
-	csr_writel(value, 0xe0002838L);
-}
-#define CSR_TIMER0_EV_PENDING_ADDR 0xe000283cL
-#define CSR_TIMER0_EV_PENDING_SIZE 1
-static inline unsigned char timer0_ev_pending_read(void) {
-	unsigned char r = csr_readl(0xe000283cL);
-	return r;
-}
-static inline void timer0_ev_pending_write(unsigned char value) {
-	csr_writel(value, 0xe000283cL);
-}
-#define CSR_TIMER0_EV_ENABLE_ADDR 0xe0002840L
-#define CSR_TIMER0_EV_ENABLE_SIZE 1
-static inline unsigned char timer0_ev_enable_read(void) {
-	unsigned char r = csr_readl(0xe0002840L);
-	return r;
-}
-static inline void timer0_ev_enable_write(unsigned char value) {
-	csr_writel(value, 0xe0002840L);
-}
-
-/* touch */
-#define CSR_TOUCH_BASE 0xe0005800L
-#define CSR_TOUCH_O_ADDR 0xe0005800L
-#define CSR_TOUCH_O_SIZE 1
-static inline unsigned char touch_o_read(void) {
-	unsigned char r = csr_readl(0xe0005800L);
-	return r;
-}
-static inline void touch_o_write(unsigned char value) {
-	csr_writel(value, 0xe0005800L);
-}
-#define CSR_TOUCH_O_O_OFFSET 0
-#define CSR_TOUCH_O_O_SIZE 4
-#define CSR_TOUCH_OE_ADDR 0xe0005804L
-#define CSR_TOUCH_OE_SIZE 1
-static inline unsigned char touch_oe_read(void) {
-	unsigned char r = csr_readl(0xe0005804L);
-	return r;
-}
-static inline void touch_oe_write(unsigned char value) {
-	csr_writel(value, 0xe0005804L);
-}
-#define CSR_TOUCH_OE_OE_OFFSET 0
-#define CSR_TOUCH_OE_OE_SIZE 4
-#define CSR_TOUCH_I_ADDR 0xe0005808L
-#define CSR_TOUCH_I_SIZE 1
-static inline unsigned char touch_i_read(void) {
-	unsigned char r = csr_readl(0xe0005808L);
-	return r;
-}
-#define CSR_TOUCH_I_I_OFFSET 0
-#define CSR_TOUCH_I_I_SIZE 4
-
-/* usb */
-#define CSR_USB_BASE 0xe0004800L
-#define CSR_USB_PULLUP_OUT_ADDR 0xe0004800L
-#define CSR_USB_PULLUP_OUT_SIZE 1
-static inline unsigned char usb_pullup_out_read(void) {
-	unsigned char r = csr_readl(0xe0004800L);
-	return r;
-}
-static inline void usb_pullup_out_write(unsigned char value) {
-	csr_writel(value, 0xe0004800L);
-}
-#define CSR_USB_ADDRESS_ADDR 0xe0004804L
-#define CSR_USB_ADDRESS_SIZE 1
-static inline unsigned char usb_address_read(void) {
-	unsigned char r = csr_readl(0xe0004804L);
-	return r;
-}
-static inline void usb_address_write(unsigned char value) {
-	csr_writel(value, 0xe0004804L);
-}
-#define CSR_USB_ADDRESS_ADDR_OFFSET 0
-#define CSR_USB_ADDRESS_ADDR_SIZE 7
-#define CSR_USB_NEXT_EV_ADDR 0xe0004808L
-#define CSR_USB_NEXT_EV_SIZE 1
-static inline unsigned char usb_next_ev_read(void) {
-	unsigned char r = csr_readl(0xe0004808L);
-	return r;
-}
-#define CSR_USB_NEXT_EV_IN_OFFSET 0
-#define CSR_USB_NEXT_EV_IN_SIZE 1
-#define CSR_USB_NEXT_EV_OUT_OFFSET 1
-#define CSR_USB_NEXT_EV_OUT_SIZE 1
-#define CSR_USB_NEXT_EV_SETUP_OFFSET 2
-#define CSR_USB_NEXT_EV_SETUP_SIZE 1
-#define CSR_USB_NEXT_EV_RESET_OFFSET 3
-#define CSR_USB_NEXT_EV_RESET_SIZE 1
-#define CSR_USB_SETUP_DATA_ADDR 0xe000480cL
-#define CSR_USB_SETUP_DATA_SIZE 1
-static inline unsigned char usb_setup_data_read(void) {
-	unsigned char r = csr_readl(0xe000480cL);
-	return r;
-}
-#define CSR_USB_SETUP_DATA_DATA_OFFSET 0
-#define CSR_USB_SETUP_DATA_DATA_SIZE 8
-#define CSR_USB_SETUP_CTRL_ADDR 0xe0004810L
-#define CSR_USB_SETUP_CTRL_SIZE 1
-static inline unsigned char usb_setup_ctrl_read(void) {
-	unsigned char r = csr_readl(0xe0004810L);
-	return r;
-}
-static inline void usb_setup_ctrl_write(unsigned char value) {
-	csr_writel(value, 0xe0004810L);
-}
-#define CSR_USB_SETUP_CTRL_RESET_OFFSET 5
-#define CSR_USB_SETUP_CTRL_RESET_SIZE 1
-#define CSR_USB_SETUP_STATUS_ADDR 0xe0004814L
-#define CSR_USB_SETUP_STATUS_SIZE 1
-static inline unsigned char usb_setup_status_read(void) {
-	unsigned char r = csr_readl(0xe0004814L);
-	return r;
-}
-#define CSR_USB_SETUP_STATUS_EPNO_OFFSET 0
-#define CSR_USB_SETUP_STATUS_EPNO_SIZE 4
-#define CSR_USB_SETUP_STATUS_HAVE_OFFSET 4
-#define CSR_USB_SETUP_STATUS_HAVE_SIZE 1
-#define CSR_USB_SETUP_STATUS_PEND_OFFSET 5
-#define CSR_USB_SETUP_STATUS_PEND_SIZE 1
-#define CSR_USB_SETUP_STATUS_IS_IN_OFFSET 6
-#define CSR_USB_SETUP_STATUS_IS_IN_SIZE 1
-#define CSR_USB_SETUP_STATUS_DATA_OFFSET 7
-#define CSR_USB_SETUP_STATUS_DATA_SIZE 1
-#define CSR_USB_SETUP_EV_STATUS_ADDR 0xe0004818L
-#define CSR_USB_SETUP_EV_STATUS_SIZE 1
-static inline unsigned char usb_setup_ev_status_read(void) {
-	unsigned char r = csr_readl(0xe0004818L);
-	return r;
-}
-static inline void usb_setup_ev_status_write(unsigned char value) {
-	csr_writel(value, 0xe0004818L);
-}
-#define CSR_USB_SETUP_EV_PENDING_ADDR 0xe000481cL
-#define CSR_USB_SETUP_EV_PENDING_SIZE 1
-static inline unsigned char usb_setup_ev_pending_read(void) {
-	unsigned char r = csr_readl(0xe000481cL);
-	return r;
-}
-static inline void usb_setup_ev_pending_write(unsigned char value) {
-	csr_writel(value, 0xe000481cL);
-}
-#define CSR_USB_SETUP_EV_ENABLE_ADDR 0xe0004820L
-#define CSR_USB_SETUP_EV_ENABLE_SIZE 1
-static inline unsigned char usb_setup_ev_enable_read(void) {
-	unsigned char r = csr_readl(0xe0004820L);
-	return r;
-}
-static inline void usb_setup_ev_enable_write(unsigned char value) {
-	csr_writel(value, 0xe0004820L);
-}
-#define CSR_USB_IN_DATA_ADDR 0xe0004824L
-#define CSR_USB_IN_DATA_SIZE 1
-static inline unsigned char usb_in_data_read(void) {
-	unsigned char r = csr_readl(0xe0004824L);
-	return r;
-}
-static inline void usb_in_data_write(unsigned char value) {
-	csr_writel(value, 0xe0004824L);
-}
-#define CSR_USB_IN_DATA_DATA_OFFSET 0
-#define CSR_USB_IN_DATA_DATA_SIZE 8
-#define CSR_USB_IN_CTRL_ADDR 0xe0004828L
-#define CSR_USB_IN_CTRL_SIZE 1
-static inline unsigned char usb_in_ctrl_read(void) {
-	unsigned char r = csr_readl(0xe0004828L);
-	return r;
-}
-static inline void usb_in_ctrl_write(unsigned char value) {
-	csr_writel(value, 0xe0004828L);
-}
-#define CSR_USB_IN_CTRL_EPNO_OFFSET 0
-#define CSR_USB_IN_CTRL_EPNO_SIZE 4
-#define CSR_USB_IN_CTRL_RESET_OFFSET 5
-#define CSR_USB_IN_CTRL_RESET_SIZE 1
-#define CSR_USB_IN_CTRL_STALL_OFFSET 6
-#define CSR_USB_IN_CTRL_STALL_SIZE 1
-#define CSR_USB_IN_STATUS_ADDR 0xe000482cL
-#define CSR_USB_IN_STATUS_SIZE 1
-static inline unsigned char usb_in_status_read(void) {
-	unsigned char r = csr_readl(0xe000482cL);
-	return r;
-}
-#define CSR_USB_IN_STATUS_IDLE_OFFSET 0
-#define CSR_USB_IN_STATUS_IDLE_SIZE 1
-#define CSR_USB_IN_STATUS_HAVE_OFFSET 4
-#define CSR_USB_IN_STATUS_HAVE_SIZE 1
-#define CSR_USB_IN_STATUS_PEND_OFFSET 5
-#define CSR_USB_IN_STATUS_PEND_SIZE 1
-#define CSR_USB_IN_EV_STATUS_ADDR 0xe0004830L
-#define CSR_USB_IN_EV_STATUS_SIZE 1
-static inline unsigned char usb_in_ev_status_read(void) {
-	unsigned char r = csr_readl(0xe0004830L);
-	return r;
-}
-static inline void usb_in_ev_status_write(unsigned char value) {
-	csr_writel(value, 0xe0004830L);
-}
-#define CSR_USB_IN_EV_PENDING_ADDR 0xe0004834L
-#define CSR_USB_IN_EV_PENDING_SIZE 1
-static inline unsigned char usb_in_ev_pending_read(void) {
-	unsigned char r = csr_readl(0xe0004834L);
-	return r;
-}
-static inline void usb_in_ev_pending_write(unsigned char value) {
-	csr_writel(value, 0xe0004834L);
-}
-#define CSR_USB_IN_EV_ENABLE_ADDR 0xe0004838L
-#define CSR_USB_IN_EV_ENABLE_SIZE 1
-static inline unsigned char usb_in_ev_enable_read(void) {
-	unsigned char r = csr_readl(0xe0004838L);
-	return r;
-}
-static inline void usb_in_ev_enable_write(unsigned char value) {
-	csr_writel(value, 0xe0004838L);
-}
-#define CSR_USB_OUT_DATA_ADDR 0xe000483cL
-#define CSR_USB_OUT_DATA_SIZE 1
-static inline unsigned char usb_out_data_read(void) {
-	unsigned char r = csr_readl(0xe000483cL);
-	return r;
-}
-#define CSR_USB_OUT_DATA_DATA_OFFSET 0
-#define CSR_USB_OUT_DATA_DATA_SIZE 8
-#define CSR_USB_OUT_CTRL_ADDR 0xe0004840L
-#define CSR_USB_OUT_CTRL_SIZE 1
-static inline unsigned char usb_out_ctrl_read(void) {
-	unsigned char r = csr_readl(0xe0004840L);
-	return r;
-}
-static inline void usb_out_ctrl_write(unsigned char value) {
-	csr_writel(value, 0xe0004840L);
-}
-#define CSR_USB_OUT_CTRL_EPNO_OFFSET 0
-#define CSR_USB_OUT_CTRL_EPNO_SIZE 4
-#define CSR_USB_OUT_CTRL_ENABLE_OFFSET 4
-#define CSR_USB_OUT_CTRL_ENABLE_SIZE 1
-#define CSR_USB_OUT_CTRL_RESET_OFFSET 5
-#define CSR_USB_OUT_CTRL_RESET_SIZE 1
-#define CSR_USB_OUT_CTRL_STALL_OFFSET 6
-#define CSR_USB_OUT_CTRL_STALL_SIZE 1
-#define CSR_USB_OUT_STATUS_ADDR 0xe0004844L
-#define CSR_USB_OUT_STATUS_SIZE 1
-static inline unsigned char usb_out_status_read(void) {
-	unsigned char r = csr_readl(0xe0004844L);
-	return r;
-}
-#define CSR_USB_OUT_STATUS_EPNO_OFFSET 0
-#define CSR_USB_OUT_STATUS_EPNO_SIZE 4
-#define CSR_USB_OUT_STATUS_HAVE_OFFSET 4
-#define CSR_USB_OUT_STATUS_HAVE_SIZE 1
-#define CSR_USB_OUT_STATUS_PEND_OFFSET 5
-#define CSR_USB_OUT_STATUS_PEND_SIZE 1
-#define CSR_USB_OUT_EV_STATUS_ADDR 0xe0004848L
-#define CSR_USB_OUT_EV_STATUS_SIZE 1
-static inline unsigned char usb_out_ev_status_read(void) {
-	unsigned char r = csr_readl(0xe0004848L);
-	return r;
-}
-static inline void usb_out_ev_status_write(unsigned char value) {
-	csr_writel(value, 0xe0004848L);
-}
-#define CSR_USB_OUT_EV_PENDING_ADDR 0xe000484cL
-#define CSR_USB_OUT_EV_PENDING_SIZE 1
-static inline unsigned char usb_out_ev_pending_read(void) {
-	unsigned char r = csr_readl(0xe000484cL);
-	return r;
-}
-static inline void usb_out_ev_pending_write(unsigned char value) {
-	csr_writel(value, 0xe000484cL);
-}
-#define CSR_USB_OUT_EV_ENABLE_ADDR 0xe0004850L
-#define CSR_USB_OUT_EV_ENABLE_SIZE 1
-static inline unsigned char usb_out_ev_enable_read(void) {
-	unsigned char r = csr_readl(0xe0004850L);
-	return r;
-}
-static inline void usb_out_ev_enable_write(unsigned char value) {
-	csr_writel(value, 0xe0004850L);
-}
-#define CSR_USB_OUT_ENABLE_STATUS_ADDR 0xe0004854L
-#define CSR_USB_OUT_ENABLE_STATUS_SIZE 1
-static inline unsigned char usb_out_enable_status_read(void) {
-	unsigned char r = csr_readl(0xe0004854L);
-	return r;
-}
-#define CSR_USB_OUT_STALL_STATUS_ADDR 0xe0004858L
-#define CSR_USB_OUT_STALL_STATUS_SIZE 1
-static inline unsigned char usb_out_stall_status_read(void) {
-	unsigned char r = csr_readl(0xe0004858L);
-	return r;
-}
-
-/* version */
-#define CSR_VERSION_BASE 0xe0007000L
-#define CSR_VERSION_MAJOR_ADDR 0xe0007000L
-#define CSR_VERSION_MAJOR_SIZE 1
-static inline unsigned char version_major_read(void) {
-	unsigned char r = csr_readl(0xe0007000L);
-	return r;
-}
-#define CSR_VERSION_MINOR_ADDR 0xe0007004L
-#define CSR_VERSION_MINOR_SIZE 1
-static inline unsigned char version_minor_read(void) {
-	unsigned char r = csr_readl(0xe0007004L);
-	return r;
-}
-#define CSR_VERSION_REVISION_ADDR 0xe0007008L
-#define CSR_VERSION_REVISION_SIZE 1
-static inline unsigned char version_revision_read(void) {
-	unsigned char r = csr_readl(0xe0007008L);
-	return r;
-}
-#define CSR_VERSION_GITREV_ADDR 0xe000700cL
-#define CSR_VERSION_GITREV_SIZE 4
-static inline unsigned int version_gitrev_read(void) {
-	unsigned int r = csr_readl(0xe000700cL);
-	r <<= 8;
-	r |= csr_readl(0xe0007010L);
-	r <<= 8;
-	r |= csr_readl(0xe0007014L);
-	r <<= 8;
-	r |= csr_readl(0xe0007018L);
-	return r;
-}
-#define CSR_VERSION_GITEXTRA_ADDR 0xe000701cL
-#define CSR_VERSION_GITEXTRA_SIZE 2
-static inline unsigned short int version_gitextra_read(void) {
-	unsigned short int r = csr_readl(0xe000701cL);
-	r <<= 8;
-	r |= csr_readl(0xe0007020L);
-	return r;
-}
-#define CSR_VERSION_DIRTY_ADDR 0xe0007024L
-#define CSR_VERSION_DIRTY_SIZE 1
-static inline unsigned char version_dirty_read(void) {
-	unsigned char r = csr_readl(0xe0007024L);
-	return r;
-}
-#define CSR_VERSION_DIRTY_DIRTY_OFFSET 0
-#define CSR_VERSION_DIRTY_DIRTY_SIZE 1
-#define CSR_VERSION_MODEL_ADDR 0xe0007028L
-#define CSR_VERSION_MODEL_SIZE 1
-static inline unsigned char version_model_read(void) {
-	unsigned char r = csr_readl(0xe0007028L);
-	return r;
-}
-#define CSR_VERSION_MODEL_MODEL_OFFSET 0
-#define CSR_VERSION_MODEL_MODEL_SIZE 8
-#define CSR_VERSION_SEED_ADDR 0xe000702cL
-#define CSR_VERSION_SEED_SIZE 4
-static inline unsigned int version_seed_read(void) {
-	unsigned int r = csr_readl(0xe000702cL);
-	r <<= 8;
-	r |= csr_readl(0xe0007030L);
-	r <<= 8;
-	r |= csr_readl(0xe0007034L);
-	r <<= 8;
-	r |= csr_readl(0xe0007038L);
-	return r;
-}
-
-/* constants */
-#define TIMER0_INTERRUPT 2
-static inline int timer0_interrupt_read(void) {
-	return 2;
-}
-#define USB_INTERRUPT 3
-static inline int usb_interrupt_read(void) {
-	return 3;
-}
-#define CONFIG_BITSTREAM_SYNC_HEADER1 2123999870
-static inline int config_bitstream_sync_header1_read(void) {
-	return 2123999870;
-}
-#define CONFIG_BITSTREAM_SYNC_HEADER2 2125109630
-static inline int config_bitstream_sync_header2_read(void) {
-	return 2125109630;
-}
-#define CONFIG_CLOCK_FREQUENCY 12000000
-static inline int config_clock_frequency_read(void) {
-	return 12000000;
-}
-#define CONFIG_CPU_RESET_ADDR 0
-static inline int config_cpu_reset_addr_read(void) {
-	return 0;
-}
-#define CONFIG_CPU_TYPE "VEXRISCV"
-static inline const char * config_cpu_type_read(void) {
-	return "VEXRISCV";
-}
-#define CONFIG_CPU_TYPE_VEXRISCV 1
-static inline int config_cpu_type_vexriscv_read(void) {
-	return 1;
-}
-#define CONFIG_CPU_VARIANT "MIN"
-static inline const char * config_cpu_variant_read(void) {
-	return "MIN";
-}
-#define CONFIG_CPU_VARIANT_MIN 1
-static inline int config_cpu_variant_min_read(void) {
-	return 1;
-}
-#define CONFIG_CSR_ALIGNMENT 32
-static inline int config_csr_alignment_read(void) {
-	return 32;
-}
-#define CONFIG_CSR_DATA_WIDTH 8
-static inline int config_csr_data_width_read(void) {
-	return 8;
-}
-
-#endif
diff --git a/tinyusb/hw/bsp/fomu/include/hw/common.h b/tinyusb/hw/bsp/fomu/include/hw/common.h
deleted file mode 100755
index 6a97ca2e..00000000
--- a/tinyusb/hw/bsp/fomu/include/hw/common.h
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifndef _HW_COMMON_H_
-#define _HW_COMMON_H_
-#include <stdint.h>
-static inline void csr_writeb(uint8_t value, uint32_t addr)
-{
-	*((volatile uint8_t *)addr) = value;
-}
-
-static inline uint8_t csr_readb(uint32_t addr)
-{
-	return *(volatile uint8_t *)addr;
-}
-
-static inline void csr_writew(uint16_t value, uint32_t addr)
-{
-	*((volatile uint16_t *)addr) = value;
-}
-
-static inline uint16_t csr_readw(uint32_t addr)
-{
-	return *(volatile uint16_t *)addr;
-}
-
-static inline void csr_writel(uint32_t value, uint32_t addr)
-{
-	*((volatile uint32_t *)addr) = value;
-}
-
-static inline uint32_t csr_readl(uint32_t addr)
-{
-	return *(volatile uint32_t *)addr;
-}
-#endif /* _HW_COMMON_H_ */
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/fomu/include/irq.h b/tinyusb/hw/bsp/fomu/include/irq.h
deleted file mode 100755
index a8221890..00000000
--- a/tinyusb/hw/bsp/fomu/include/irq.h
+++ /dev/null
@@ -1,71 +0,0 @@
-#ifndef __IRQ_H
-#define __IRQ_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-#define CSR_MSTATUS_MIE 0x8
-
-#define CSR_IRQ_MASK 0xBC0
-#define CSR_IRQ_PENDING 0xFC0
-
-#define CSR_DCACHE_INFO 0xCC0
-
-#define csrr(reg) ({ unsigned long __tmp; \
-  asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
-  __tmp; })
-
-#define csrw(reg, val) ({ \
-  if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
-	asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
-  else \
-	asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
-
-#define csrs(reg, bit) ({ \
-  if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
-	asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \
-  else \
-	asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); })
-
-#define csrc(reg, bit) ({ \
-  if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
-	asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \
-  else \
-	asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); })
-
-static inline unsigned int irq_getie(void)
-{
-	return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
-}
-
-static inline void irq_setie(unsigned int ie)
-{
-	if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);
-}
-
-static inline unsigned int irq_getmask(void)
-{
-	unsigned int mask;
-	asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK));
-	return mask;
-}
-
-static inline void irq_setmask(unsigned int mask)
-{
-	asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask));
-}
-
-static inline unsigned int irq_pending(void)
-{
-	unsigned int pending;
-	asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING));
-	return pending;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __IRQ_H */
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/fomu/output_format.ld b/tinyusb/hw/bsp/fomu/output_format.ld
deleted file mode 100755
index 5e76f5f4..00000000
--- a/tinyusb/hw/bsp/fomu/output_format.ld
+++ /dev/null
@@ -1 +0,0 @@
-OUTPUT_FORMAT("elf32-littleriscv")
diff --git a/tinyusb/hw/bsp/fomu/regions.ld b/tinyusb/hw/bsp/fomu/regions.ld
deleted file mode 100755
index 51811f66..00000000
--- a/tinyusb/hw/bsp/fomu/regions.ld
+++ /dev/null
@@ -1,6 +0,0 @@
-MEMORY {
-	csr : ORIGIN = 0x60000000, LENGTH = 0x01000000
-	vexriscv_debug : ORIGIN = 0xf00f0000, LENGTH = 0x00000100
-	sram : ORIGIN = 0x10000000, LENGTH = 0x00020000
-	rom : ORIGIN = 0x00000000, LENGTH = 0x00002000
-}
diff --git a/tinyusb/hw/bsp/frdm_k32l2b/board.h b/tinyusb/hw/bsp/frdm_k32l2b/board.h
deleted file mode 100755
index 82536791..00000000
--- a/tinyusb/hw/bsp/frdm_k32l2b/board.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#include "fsl_device_registers.h"
-
-// LED
-#define LED_PIN_CLOCK         kCLOCK_PortD
-#define LED_GPIO              GPIOD
-#define LED_PORT              PORTD
-#define LED_PIN               5
-#define LED_STATE_ON          0
-
-// SW3 button1
-#define BUTTON_PIN_CLOCK      kCLOCK_PortC
-#define BUTTON_GPIO           GPIOC
-#define BUTTON_PORT           PORTC
-#define BUTTON_PIN            3
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_PORT             LPUART0
-#define UART_PIN_CLOCK        kCLOCK_PortA
-#define UART_PIN_PORT         PORTA
-#define UART_PIN_RX           1u
-#define UART_PIN_TX           2u
-#define SOPT5_LPUART0RXSRC_LPUART_RX 0x00u /*!<@brief LPUART0 Receive Data Source Select: LPUART_RX pin */
-#define SOPT5_LPUART0TXSRC_LPUART_TX 0x00u /*!<@brief LPUART0 Transmit Data Source Select: LPUART0_TX pin */
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/frdm_k32l2b/board.mk b/tinyusb/hw/bsp/frdm_k32l2b/board.mk
deleted file mode 100755
index 56df553d..00000000
--- a/tinyusb/hw/bsp/frdm_k32l2b/board.mk
+++ /dev/null
@@ -1,51 +0,0 @@
-SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += $(SDK_DIR)
-
-CFLAGS += \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
-  -DCPU_K32L2B31VLH0A \
-  -DCFG_TUSB_MCU=OPT_MCU_K32L2BXX
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter
-
-MCU_DIR = $(SDK_DIR)/devices/K32L2B31A
-
-# All source paths should be relative to the top level.
-LD_FILE = $(MCU_DIR)/gcc/K32L2B31xxxxA_flash.ld
-
-SRC_C += \
-	src/portable/nxp/khci/dcd_khci.c \
-	$(MCU_DIR)/system_K32L2B31A.c \
-	$(MCU_DIR)/project_template/clock_config.c \
-	$(MCU_DIR)/drivers/fsl_clock.c \
-	$(SDK_DIR)/drivers/gpio/fsl_gpio.c \
-	$(SDK_DIR)/drivers/lpuart/fsl_lpuart.c
-
-INC += \
-	$(TOP)/hw/bsp/$(BOARD) \
-	$(TOP)/$(SDK_DIR)/CMSIS/Include \
-	$(TOP)/$(SDK_DIR)/drivers/smc \
-	$(TOP)/$(SDK_DIR)/drivers/common \
-	$(TOP)/$(SDK_DIR)/drivers/gpio \
-	$(TOP)/$(SDK_DIR)/drivers/port \
-	$(TOP)/$(SDK_DIR)/drivers/lpuart \
-	$(TOP)/$(MCU_DIR) \
-	$(TOP)/$(MCU_DIR)/drivers \
-	$(TOP)/$(MCU_DIR)/project_template \
-
-SRC_S += $(MCU_DIR)/gcc/startup_K32L2B31A.S
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
-
-# For flash-jlink target
-JLINK_DEVICE = MKL25Z128xxx4
-
-# For flash-pyocd target
-PYOCD_TARGET = K32L2B
-
-# flash using pyocd
-flash: flash-pyocd
diff --git a/tinyusb/hw/bsp/frdm_k32l2b/frdm_k32l2b.c b/tinyusb/hw/bsp/frdm_k32l2b/frdm_k32l2b.c
deleted file mode 100755
index c45095ca..00000000
--- a/tinyusb/hw/bsp/frdm_k32l2b/frdm_k32l2b.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2018, hathach (tinyusb.org)
- * Copyright (c) 2020, Koji Kitayama
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "../board.h"
-#include "board.h"
-#include "fsl_gpio.h"
-#include "fsl_port.h"
-#include "fsl_clock.h"
-#include "fsl_lpuart.h"
-
-#include "clock_config.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-void board_init(void)
-{
-  /* Enable port clocks for UART/LED/Button pins */
-  CLOCK_EnableClock(UART_PIN_CLOCK);
-  CLOCK_EnableClock(LED_PIN_CLOCK);
-  CLOCK_EnableClock(BUTTON_PIN_CLOCK);
-
-  gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 };
-  GPIO_PinInit(LED_GPIO, LED_PIN, &led_config);
-  PORT_SetPinMux(LED_PORT, LED_PIN, kPORT_MuxAsGpio);
-
-  gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 };
-  GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config);
-  const port_pin_config_t BUTTON_CFG = {
-    kPORT_PullUp, 
-    kPORT_FastSlewRate, 
-    kPORT_PassiveFilterDisable, 
-    kPORT_LowDriveStrength, 
-    kPORT_MuxAsGpio
-  };
-  PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG);
-
-  /* PORTA1 (pin 23) is configured as LPUART0_RX */
-  PORT_SetPinMux(PORTA, 1U, kPORT_MuxAlt2);
-  /* PORTA2 (pin 24) is configured as LPUART0_TX */
-  PORT_SetPinMux(PORTA, 2U, kPORT_MuxAlt2);
-  
-  SIM->SOPT5 = ((SIM->SOPT5 &
-               /* Mask bits to zero which are setting */
-               (~(SIM_SOPT5_LPUART0TXSRC_MASK | SIM_SOPT5_LPUART0RXSRC_MASK)))
-               /* LPUART0 Transmit Data Source Select: LPUART0_TX pin. */
-               | SIM_SOPT5_LPUART0TXSRC(SOPT5_LPUART0TXSRC_LPUART_TX)
-               /* LPUART0 Receive Data Source Select: LPUART_RX pin. */
-               | SIM_SOPT5_LPUART0RXSRC(SOPT5_LPUART0RXSRC_LPUART_RX));
-
-  BOARD_BootClockRUN();
-  SystemCoreClockUpdate();
-  CLOCK_SetLpuart0Clock(1);
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  lpuart_config_t uart_config;
-  LPUART_GetDefaultConfig(&uart_config);
-  uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
-  uart_config.enableTx = true;
-  uart_config.enableRx = true;
-  LPUART_Init(UART_PORT, &uart_config, CLOCK_GetFreq(kCLOCK_McgIrc48MClk));
-
-  // USB
-  CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcIrc48M, 48000000U);
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  LPUART_ReadBlocking(UART_PORT, buf, len);
-  return len;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  LPUART_WriteBlocking(UART_PORT, (uint8_t*)buf, len);
-  return len;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/tinyusb/hw/bsp/frdm_kl25z/board.mk b/tinyusb/hw/bsp/frdm_kl25z/board.mk
deleted file mode 100755
index 451bc37c..00000000
--- a/tinyusb/hw/bsp/frdm_kl25z/board.mk
+++ /dev/null
@@ -1,46 +0,0 @@
-SDK_DIR = hw/mcu/nxp/nxp_sdk
-DEPS_SUBMODULES += $(SDK_DIR)
-
-CFLAGS += \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
-  -DCPU_MKL25Z128VLK4 \
-  -DCFG_TUSB_MCU=OPT_MCU_MKL25ZXX
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter
-
-MCU_DIR = $(SDK_DIR)/devices/MKL25Z4
-
-# All source paths should be relative to the top level.
-LD_FILE = $(MCU_DIR)/gcc/MKL25Z128xxx4_flash.ld
-
-SRC_C += \
-	src/portable/nxp/khci/dcd_khci.c \
-	$(MCU_DIR)/system_MKL25Z4.c \
-	$(MCU_DIR)/project_template/clock_config.c \
-	$(MCU_DIR)/drivers/fsl_clock.c \
-	$(MCU_DIR)/drivers/fsl_gpio.c \
-	$(MCU_DIR)/drivers/fsl_lpsci.c
-
-INC += \
-	$(TOP)/hw/bsp/$(BOARD) \
-	$(TOP)/$(SDK_DIR)/CMSIS/Include \
-	$(TOP)/$(MCU_DIR) \
-	$(TOP)/$(MCU_DIR)/drivers \
-	$(TOP)/$(MCU_DIR)/project_template \
-
-SRC_S += $(MCU_DIR)/gcc/startup_MKL25Z4.S
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
-
-# For flash-jlink target
-JLINK_DEVICE = MKL25Z128xxx4
-
-# For flash-pyocd target
-PYOCD_TARGET = mkl25zl128
-
-# flash using pyocd
-flash: flash-pyocd
diff --git a/tinyusb/hw/bsp/frdm_kl25z/frdm_kl25z.c b/tinyusb/hw/bsp/frdm_kl25z/frdm_kl25z.c
deleted file mode 100755
index 7d3a173e..00000000
--- a/tinyusb/hw/bsp/frdm_kl25z/frdm_kl25z.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2018, hathach (tinyusb.org)
- * Copyright (c) 2020, Koji Kitayama
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "../board.h"
-#include "fsl_device_registers.h"
-#include "fsl_gpio.h"
-#include "fsl_port.h"
-#include "fsl_clock.h"
-#include "fsl_lpsci.h"
-
-#include "clock_config.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-// LED
-#define LED_PINMUX            IOMUXC_GPIO_AD_B0_09_GPIO1_IO09
-#define LED_PORT              GPIOB
-#define LED_PIN_CLOCK         kCLOCK_PortB
-#define LED_PIN_PORT          PORTB
-#define LED_PIN               19U
-#define LED_PIN_FUNCTION      kPORT_MuxAsGpio
-#define LED_STATE_ON          0
-
-// UART
-#define UART_PORT             UART0
-#define UART_PIN_CLOCK        kCLOCK_PortA
-#define UART_PIN_PORT         PORTA
-#define UART_PIN_RX           1u
-#define UART_PIN_TX           2u
-#define UART_PIN_FUNCTION     kPORT_MuxAlt2
-#define SOPT5_UART0RXSRC_UART_RX      0x00u   /*!< UART0 receive data source select: UART0_RX pin */
-#define SOPT5_UART0TXSRC_UART_TX      0x00u   /*!< UART0 transmit data source select: UART0_TX pin */
-
-const uint8_t dcd_data[] = { 0x00 };
-
-void board_init(void)
-{
-  BOARD_BootClockRUN();
-  SystemCoreClockUpdate();
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  // LED
-  CLOCK_EnableClock(LED_PIN_CLOCK);
-  PORT_SetPinMux(LED_PIN_PORT, LED_PIN, LED_PIN_FUNCTION);
-  gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 };
-  GPIO_PinInit(LED_PORT, LED_PIN, &led_config);
-  board_led_write(true);
-
-  // UART
-  CLOCK_EnableClock(UART_PIN_CLOCK);
-  PORT_SetPinMux(UART_PIN_PORT, UART_PIN_RX, UART_PIN_FUNCTION);
-  PORT_SetPinMux(UART_PIN_PORT, UART_PIN_TX, UART_PIN_FUNCTION);
-  SIM->SOPT5 = ((SIM->SOPT5 &
-    (~(SIM_SOPT5_UART0TXSRC_MASK | SIM_SOPT5_UART0RXSRC_MASK)))
-      | SIM_SOPT5_UART0TXSRC(SOPT5_UART0TXSRC_UART_TX)
-      | SIM_SOPT5_UART0RXSRC(SOPT5_UART0RXSRC_UART_RX)
-    );
-
-  lpsci_config_t uart_config;
-  CLOCK_SetLpsci0Clock(1);
-  LPSCI_GetDefaultConfig(&uart_config);
-  uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
-  uart_config.enableTx = true;
-  uart_config.enableRx = true;
-  LPSCI_Init(UART_PORT, &uart_config, CLOCK_GetPllFllSelClkFreq());
-
-  // USB
-  CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0, CLOCK_GetFreq(kCLOCK_PllFllSelClk));
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  GPIO_WritePinOutput(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return 0;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  LPSCI_ReadBlocking(UART_PORT, buf, len);
-  return len;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  LPSCI_WriteBlocking(UART_PORT, (uint8_t*)buf, len);
-  return len;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/tinyusb/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.h b/tinyusb/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.h
deleted file mode 100755
index fae7c40b..00000000
--- a/tinyusb/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef _NUCLEI_SDK_HAL_H
-#define _NUCLEI_SDK_HAL_H
-
-#include "gd32vf103c_longan_nano.h"
-
-// 4 bits for interrupt level, 0 for priority.
-// level 0 = lowest priority, level 15 = highest priority.
-#define __ECLIC_INTCTLBITS  4
-
-#define __SYSTEM_CLOCK      72000000
-#define HXTAL_VALUE         ((uint32_t)8000000)
-
-#define SOC_DEBUG_UART      GD32_COM0
-
-#define DBG_KEY_UNLOCK      0x4B5A6978
-#define DBG_CMD_RESET       0x1
-#define DBG_KEY             REG32(DBG + 0x0C)
-#define DBG_CMD             REG32(DBG + 0x08)
-
-#endif
diff --git a/tinyusb/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.mk b/tinyusb/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.mk
deleted file mode 100755
index 3b894445..00000000
--- a/tinyusb/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-LONGAN_NANO_SDK_BSP = $(GD32VF103_SDK_SOC)/Board/gd32vf103c_longan_nano
-LINKER_SCRIPTS = $(LONGAN_NANO_SDK_BSP)/Source/GCC
-
-# All source paths should be relative to the top level.
-LD_FILE = $(LINKER_SCRIPTS)/gcc_gd32vf103xb_flashxip.ld # Longan Nano 128k ROM 32k RAM
-#LD_FILE = $(LINKER_SCRIPTS)/gcc_gd32vf103x8_flashxip.ld # Longan Nano Lite 64k ROM 20k RAM
-
-SRC_C += $(LONGAN_NANO_SDK_BSP)/Source/gd32vf103c_longan_nano.c
-INC += $(TOP)/$(LONGAN_NANO_SDK_BSP)/Include
-
-# Longan Nano 128k ROM 32k RAM
-JLINK_DEVICE = gd32vf103cbt6
-#JLINK_DEVICE = gd32vf103c8t6 # Longan Nano Lite 64k ROM 20k RAM
diff --git a/tinyusb/hw/bsp/gd32vf103/family.c b/tinyusb/hw/bsp/gd32vf103/family.c
deleted file mode 100755
index d76fb9a2..00000000
--- a/tinyusb/hw/bsp/gd32vf103/family.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "board.h"
-#include "drv_usb_hw.h"
-#include "drv_usb_dev.h"
-
-#include "../board.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-
-void USBFS_IRQHandler(void) { tud_int_handler(0); }
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-#define USB_NO_VBUS_PIN
-
-// According to GD32VF103 user manual clock tree:
-// Systick clock = AHB clock / 4.
-#define TIMER_TICKS         ((SystemCoreClock / 4) / 1000) 
-
-#define BUTTON_PORT         GPIOA
-#define BUTTON_PIN          GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE 1
-
-#define UART_DEV            SOC_DEBUG_UART
-
-#define LED_PIN             LED_R
-
-void board_init(void) {
-  /* Disable interrupts during init */
-  __disable_irq();
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  SysTick_Config(TIMER_TICKS);
-#endif
-
-  rcu_periph_clock_enable(RCU_GPIOA);
-  rcu_periph_clock_enable(RCU_GPIOB);
-  rcu_periph_clock_enable(RCU_GPIOC);
-  rcu_periph_clock_enable(RCU_GPIOD);
-  rcu_periph_clock_enable(RCU_AF);
-
-#ifdef BUTTON_PIN
-  gpio_init(BUTTON_PORT, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, BUTTON_PIN);
-#endif
-
-#ifdef LED_PIN
-  gd_led_init(LED_PIN);
-#endif
-
-#if defined(UART_DEV)
-  gd_com_init(UART_DEV);
-#endif
-
-  /* USB D+ and D- pins don't need to be configured. */
-  /* Configure VBUS Pin */
-#ifndef USB_NO_VBUS_PIN
-  gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_9);
-#endif
-
-  /* This for ID line debug */
-  // gpio_init(GPIOA, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_10);
-
-  /* Enable USB OTG clock */
-  usb_rcu_config();
-
-  /* Reset USB OTG peripheral */
-  rcu_periph_reset_enable(RCU_USBFSRST);
-  rcu_periph_reset_disable(RCU_USBFSRST);
-
-  /* Configure USBFS IRQ */
-  ECLIC_Register_IRQ(USBFS_IRQn, ECLIC_NON_VECTOR_INTERRUPT,
-                     ECLIC_POSTIVE_EDGE_TRIGGER, 3, 0, NULL);
-
-  /* Retrieve otg core registers */
-  usb_gr* otg_core_regs = (usb_gr*)(USBFS_REG_BASE + USB_REG_OFFSET_CORE);
-
-#ifdef USB_NO_VBUS_PIN
-  /* Disable VBUS sense*/
-  otg_core_regs->GCCFG |= GCCFG_VBUSIG | GCCFG_PWRON | GCCFG_VBUSBCEN;
-#else
-  /* Enable VBUS sense via pin PA9 */
-  otg_core_regs->GCCFG |= GCCFG_VBUSIG | GCCFG_PWRON | GCCFG_VBUSBCEN;
-  otg_core_regs->GCCFG &= ~GCCFG_VBUSIG;
-#endif
-
-  /* Enable interrupts globaly */
-  __enable_irq();
-}
-
-void gd32vf103_reset(void) {
-  /* The MTIMER unit of the GD32VF103 doesn't have the MSFRST
-   * register to generate a software reset request.
-   * BUT instead two undocumented registers in the debug peripheral
-   * that allow issueing a software reset.
-   * https://github.com/esmil/gd32vf103inator/blob/master/include/gd32vf103/dbg.h
-   */
-  DBG_KEY = DBG_KEY_UNLOCK;
-  DBG_CMD = DBG_CMD_RESET;
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state) {
-  state ? gd_led_on(LED_PIN) : gd_led_off(LED_PIN);
-}
-
-uint32_t board_button_read(void) {
-  return BUTTON_STATE_ACTIVE == gpio_input_bit_get(BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len) {
-#if defined(UART_DEV)
-  int rxsize = len;
-  while (rxsize--) {
-    *(uint8_t*)buf = usart_read(UART_DEV);
-    buf++;
-  }
-  return len;
-#else
-  (void)buf;
-  (void)len;
-  return 0;
-#endif
-}
-
-int board_uart_write(void const* buf, int len) {
-#if defined(UART_DEV)
-  int txsize = len;
-  while (txsize--) {
-    usart_write(UART_DEV, *(uint8_t*)buf);
-    buf++;
-  }
-  return len;
-#else
-  (void)buf;
-  (void)len;
-  return 0;
-#endif
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void eclic_mtip_handler(void) {
-  system_ticks++;
-  SysTick_Reload(TIMER_TICKS);
-}
-uint32_t board_millis(void) { return system_ticks; }
-#endif
-
-#ifdef USE_FULL_ASSERT
-/**
- * @brief  Reports the name of the source file and the source line number
- *         where the assert_param error has occurred.
- * @param  file: pointer to the source file name
- * @param  line: assert_param error line source number
- * @retval None
- */
-void assert_failed(char* file, uint32_t line) {
-  /* USER CODE BEGIN 6 */
-  /* User can add his own implementation to report the file name and line
-     number,
-     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line)
-   */
-  /* USER CODE END 6 */
-}
-#endif /* USE_FULL_ASSERT */
diff --git a/tinyusb/hw/bsp/gd32vf103/family.mk b/tinyusb/hw/bsp/gd32vf103/family.mk
deleted file mode 100755
index 9148e7f8..00000000
--- a/tinyusb/hw/bsp/gd32vf103/family.mk
+++ /dev/null
@@ -1,68 +0,0 @@
-# https://www.embecosm.com/resources/tool-chain-downloads/#riscv-stable
-#CROSS_COMPILE ?= riscv32-unknown-elf-
-
-# Toolchain from https://nucleisys.com/download.php
-#CROSS_COMPILE ?= riscv-nuclei-elf-
-
-# Toolchain from https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack
-CROSS_COMPILE ?= riscv-none-embed-
-
-# Submodules
-NUCLEI_SDK = hw/mcu/gd/nuclei-sdk
-DEPS_SUBMODULES += $(NUCLEI_SDK)
-
-# Nuclei-SDK paths
-GD32VF103_SDK_SOC = $(NUCLEI_SDK)/SoC/gd32vf103
-GD32VF103_SDK_DRIVER = $(GD32VF103_SDK_SOC)/Common/Source/Drivers
-LIBC_STUBS = $(GD32VF103_SDK_SOC)/Common/Source/Stubs
-STARTUP_ASM = $(GD32VF103_SDK_SOC)/Common/Source/GCC
-
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-SKIP_NANOLIB = 1
-
-CFLAGS += \
-	-march=rv32imac \
-	-mabi=ilp32 \
-	-mcmodel=medlow \
-	-mstrict-align \
-	-nostdlib -nostartfiles \
-	-DCFG_TUSB_MCU=OPT_MCU_GD32VF103 \
-	-DDOWNLOAD_MODE=DOWNLOAD_MODE_FLASHXIP \
-	-DGD32VF103 
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter
-
-SRC_C += \
-	src/portable/st/synopsys/dcd_synopsys.c \
-	$(GD32VF103_SDK_DRIVER)/gd32vf103_rcu.c \
-	$(GD32VF103_SDK_DRIVER)/gd32vf103_gpio.c \
-	$(GD32VF103_SDK_DRIVER)/Usb/gd32vf103_usb_hw.c \
-	$(GD32VF103_SDK_DRIVER)/gd32vf103_usart.c \
-	$(LIBC_STUBS)/sbrk.c \
-	$(LIBC_STUBS)/close.c \
-	$(LIBC_STUBS)/isatty.c \
-	$(LIBC_STUBS)/fstat.c \
-	$(LIBC_STUBS)/lseek.c \
-	$(LIBC_STUBS)/read.c 
-
-SRC_S += \
-	$(STARTUP_ASM)/startup_gd32vf103.S \
-	$(STARTUP_ASM)/intexc_gd32vf103.S
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(NUCLEI_SDK)/NMSIS/Core/Include \
-	$(TOP)/$(GD32VF103_SDK_SOC)/Common/Include \
-	$(TOP)/$(GD32VF103_SDK_SOC)/Common/Include/Usb
-
-# For freeRTOS port source
-FREERTOS_PORT = RISC-V
-
-# For flash-jlink target
-JLINK_IF = jtag
-
-# flash target ROM bootloader
-flash: $(BUILD)/$(PROJECT).bin
-	dfu-util -R -a 0 --dfuse-address 0x08000000 -D $<
diff --git a/tinyusb/hw/bsp/gd32vf103/system_gd32vf103.c b/tinyusb/hw/bsp/gd32vf103/system_gd32vf103.c
deleted file mode 100755
index 29518a54..00000000
--- a/tinyusb/hw/bsp/gd32vf103/system_gd32vf103.c
+++ /dev/null
@@ -1,668 +0,0 @@
-/*!
- \file    system_gd32vf103.h
-\brief   RISC-V Device Peripheral Access Layer Source File for
-          GD32VF103 Device Series
-
-*/
-
-/*
-    Copyright (c) 2020, GigaDevice Semiconductor Inc.
-
-    Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-    1. Redistributions of source code must retain the above copyright notice, this
-       list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright notice,
-       this list of conditions and the following disclaimer in the documentation
-       and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holder nor the names of its contributors
-       may be used to endorse or promote products derived from this software without
-       specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
-OF SUCH DAMAGE.
-*/
-
-/* This file refers the RISC-V standard, some adjustments are made according to GigaDevice chips */
-#include "board.h"
-
-/* system frequency define */
-#define __IRC8M           (IRC8M_VALUE)            /* internal 8 MHz RC oscillator frequency */
-#define __HXTAL           (HXTAL_VALUE)            /* high speed crystal oscillator frequency */
-#define __SYS_OSC_CLK     (__IRC8M)                /* main oscillator frequency */
-#define __SYSTEM_CLOCK_HXTAL                    (HXTAL_VALUE)
-
-#if !defined(__SYSTEM_CLOCK)
-#define __SYSTEM_CLOCK 72000000
-#endif
-
-#if __SYSTEM_CLOCK == 48000000
-  #define __SYSTEM_CLOCK_48M_PLL_HXTAL            (uint32_t)(48000000)
-  uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL;
-  static void system_clock_48m_hxtal(void);
-
-#elif __SYSTEM_CLOCK == 72000000
-  #define __SYSTEM_CLOCK_72M_PLL_HXTAL            (uint32_t)(72000000)
-  uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL;
-  static void system_clock_72m_hxtal(void);
-
-#elif __SYSTEM_CLOCK == 96000000
-  #define __SYSTEM_CLOCK_96M_PLL_HXTAL            (uint32_t)(96000000)
-  uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL;
-  static void system_clock_96m_hxtal(void);
-
-#else
-#error No valid system clock configuration set!
-#endif
-
-/* configure the system clock */
-static void system_clock_config(void);
-
-/*!
-    \brief      configure the system clock
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-static void system_clock_config(void)
-{
-#if defined (__SYSTEM_CLOCK_48M_PLL_HXTAL)
-    system_clock_48m_hxtal();
-#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
-    system_clock_72m_hxtal();
-#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL)
-    system_clock_96m_hxtal();
-#endif /* __SYSTEM_CLOCK_HXTAL */
-}
-
-/*!
-    \brief      setup the microcontroller system, initialize the system
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void SystemInit(void)
-{
-    /* reset the RCC clock configuration to the default reset state */
-    /* enable IRC8M */
-    RCU_CTL |= RCU_CTL_IRC8MEN;
-    
-    /* reset SCS, AHBPSC, APB1PSC, APB2PSC, ADCPSC, CKOUT0SEL bits */
-    RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |
-                  RCU_CFG0_ADCPSC | RCU_CFG0_ADCPSC_2 | RCU_CFG0_CKOUT0SEL);
-
-    /* reset HXTALEN, CKMEN, PLLEN bits */
-    RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN);
-
-    /* Reset HXTALBPS bit */
-    RCU_CTL &= ~(RCU_CTL_HXTALBPS);
-
-    /* reset PLLSEL, PREDV0_LSB, PLLMF, USBFSPSC bits */
-    
-    RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF |
-                  RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4);
-    RCU_CFG1 = 0x00000000U;
-
-    /* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */
-    RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN);
-    /* disable all interrupts */
-    RCU_INT = 0x00FF0000U;
-
-    /* Configure the System clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */
-    system_clock_config();
-}
-
-/*!
-    \brief      update the SystemCoreClock with current core clock retrieved from cpu registers
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-void SystemCoreClockUpdate(void)
-{
-    uint32_t scss;
-    uint32_t pllsel, predv0sel, pllmf, ck_src;
-    uint32_t predv0, predv1, pll1mf;
-
-    scss = GET_BITS(RCU_CFG0, 2, 3);
-
-    switch (scss)
-    {
-        /* IRC8M is selected as CK_SYS */
-        case SEL_IRC8M:
-            SystemCoreClock = IRC8M_VALUE;
-            break;
-            
-        /* HXTAL is selected as CK_SYS */
-        case SEL_HXTAL:
-            SystemCoreClock = HXTAL_VALUE;
-            break;
-            
-        /* PLL is selected as CK_SYS */
-        case SEL_PLL:
-            /* PLL clock source selection, HXTAL or IRC8M/2 */
-            pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL);
-
-
-            if(RCU_PLLSRC_IRC8M_DIV2 == pllsel){
-                /* PLL clock source is IRC8M/2 */
-                ck_src = IRC8M_VALUE / 2U;
-            }else{
-                /* PLL clock source is HXTAL */
-                ck_src = HXTAL_VALUE;
-
-                predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL);
-
-                /* source clock use PLL1 */
-                if(RCU_PREDV0SRC_CKPLL1 == predv0sel){
-                    predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U;
-                    pll1mf = ((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U;
-                    if(17U == pll1mf){
-                        pll1mf = 20U;
-                    }
-                    ck_src = (ck_src / predv1) * pll1mf;
-                }
-                predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U;
-                ck_src /= predv0;
-            }
-
-            /* PLL multiplication factor */
-            pllmf = GET_BITS(RCU_CFG0, 18, 21);
-
-            if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){
-                pllmf |= 0x10U;
-            }
-
-            if(pllmf >= 15U){
-                pllmf += 1U;
-            }else{
-                pllmf += 2U;
-            }
-
-            SystemCoreClock = ck_src * pllmf;
-
-            if(15U == pllmf){
-                /* PLL source clock multiply by 6.5 */
-                SystemCoreClock = ck_src * 6U + ck_src / 2U;
-            }
-
-            break;
-
-        /* IRC8M is selected as CK_SYS */
-        default:
-            SystemCoreClock = IRC8M_VALUE;
-            break;
-    }
-}
-
-#if defined (__SYSTEM_CLOCK_48M_PLL_HXTAL)
-/*!
-    \brief      configure the system clock to 48M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-static void system_clock_48m_hxtal(void)
-{
-    uint32_t timeout = 0U;
-    uint32_t stab_flag = 0U;
-
-    /* enable HXTAL */
-    RCU_CTL |= RCU_CTL_HXTALEN;
-
-    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
-    do{
-        timeout++;
-        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
-    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
-
-    /* if fail */
-    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
-        while(1){
-        }
-    }
-
-    /* HXTAL is stable */
-    /* AHB = SYSCLK */
-    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
-    /* APB2 = AHB/1 */
-    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
-    /* APB1 = AHB/2 */
-    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
-
-    /* CK_PLL = (CK_PREDIV0) * 12 = 48 MHz */
-    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
-    RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL12);
-
-    if(HXTAL_VALUE==25000000){
-
-        /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
-        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
-        RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
-
-        /* enable PLL1 */
-        RCU_CTL |= RCU_CTL_PLL1EN;
-        /* wait till PLL1 is ready */
-        while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
-        }
-
-    }else if(HXTAL_VALUE==8000000){
-        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
-        RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 );
-    }
-
-
-
-    /* enable PLL */
-    RCU_CTL |= RCU_CTL_PLLEN;
-
-    /* wait until PLL is stable */
-    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
-    }
-
-    /* select PLL as system clock */
-    RCU_CFG0 &= ~RCU_CFG0_SCS;
-    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
-
-    /* wait until PLL is selected as system clock */
-    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
-    }
-}
-
-#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
-/*!
-    \brief      configure the system clock to 72M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-static void system_clock_72m_hxtal(void)
-{
-    uint32_t timeout = 0U;
-    uint32_t stab_flag = 0U;
-
-    /* enable HXTAL */
-    RCU_CTL |= RCU_CTL_HXTALEN;
-
-    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
-    do{
-        timeout++;
-        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
-    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
-
-    /* if fail */
-    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
-        while(1){
-        }
-    }
-
-    /* HXTAL is stable */
-    /* AHB = SYSCLK */
-    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
-    /* APB2 = AHB/1 */
-    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
-    /* APB1 = AHB/2 */
-    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
-
-    /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */ 
-    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
-    RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL18);
-
-
-    if(HXTAL_VALUE==25000000){
-
-        /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
-        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
-        RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
-
-        /* enable PLL1 */
-        RCU_CTL |= RCU_CTL_PLL1EN;
-        /* wait till PLL1 is ready */
-        while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
-        }
-
-    }else if(HXTAL_VALUE==8000000){
-        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
-        RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 );
-    }
-
-    /* enable PLL */
-    RCU_CTL |= RCU_CTL_PLLEN;
-
-    /* wait until PLL is stable */
-    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
-    }
-
-    /* select PLL as system clock */
-    RCU_CFG0 &= ~RCU_CFG0_SCS;
-    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
-
-    /* wait until PLL is selected as system clock */
-    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
-    }
-}
-
-#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL)
-/*!
-    \brief      configure the system clock to 96M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-static void system_clock_96m_hxtal(void)
-{
-    uint32_t timeout = 0U;
-    uint32_t stab_flag = 0U;
-
-    /* enable HXTAL */
-    RCU_CTL |= RCU_CTL_HXTALEN;
-
-    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
-    do{
-        timeout++;
-        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
-    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
-
-    /* if fail */
-    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
-        while(1){
-        }
-    }
-
-    /* HXTAL is stable */
-    /* AHB = SYSCLK */
-    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
-    /* APB2 = AHB/1 */
-    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
-    /* APB1 = AHB/2 */
-    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
-
-    if(HXTAL_VALUE==25000000){
-
-        /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */
-        RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
-        RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24);
-
-        /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
-        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
-        RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
-        /* enable PLL1 */
-        RCU_CTL |= RCU_CTL_PLL1EN;
-        /* wait till PLL1 is ready */
-        while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
-        }
-
-    }else if(HXTAL_VALUE==8000000){
-        /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */
-        RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
-        RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24);
-
-        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
-        RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 );
-    }
-
-    /* enable PLL */
-    RCU_CTL |= RCU_CTL_PLLEN;
-
-    /* wait until PLL is stable */
-    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
-    }
-
-    /* select PLL as system clock */
-    RCU_CFG0 &= ~RCU_CFG0_SCS;
-    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
-
-    /* wait until PLL is selected as system clock */
-    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
-    }
-}
-
-#endif
-
-/**
- * \defgroup  NMSIS_Core_IntExcNMI_Handling   Interrupt and Exception and NMI Handling
- * \brief Functions for interrupt, exception and nmi handle available in system_<device>.c.
- * \details
- * Nuclei provide a template for interrupt, exception and NMI handling. Silicon Vendor could adapat according
- * to their requirement. Silicon vendor could implement interface for different exception code and
- * replace current implementation.
- *
- * @{
- */
-/** \brief Max exception handler number, don't include the NMI(0xFFF) one */
-#define MAX_SYSTEM_EXCEPTION_NUM        12
-/**
- * \brief      Store the exception handlers for each exception ID
- * \note
- * - This SystemExceptionHandlers are used to store all the handlers for all
- * the exception codes Nuclei N/NX core provided.
- * - Exception code 0 - 11, totally 12 exceptions are mapped to SystemExceptionHandlers[0:11]
- * - Exception for NMI is also re-routed to exception handling(exception code 0xFFF) in startup code configuration, the handler itself is mapped to SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM]
- */
-static unsigned long SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM + 1];
-
-/**
- * \brief      Exception Handler Function Typedef
- * \note
- * This typedef is only used internal in this system_gd32vf103.c file.
- * It is used to do type conversion for registered exception handler before calling it.
- */
-typedef void (*EXC_HANDLER)(unsigned long mcause, unsigned long sp);
-
-/**
- * \brief      System Default Exception Handler
- * \details
- * This function provided a default exception and NMI handling code for all exception ids.
- * By default, It will just print some information for debug, Vendor can customize it according to its requirements.
- */
-static void system_default_exception_handler(unsigned long mcause, unsigned long sp)
-{
-    /* TODO: Uncomment this if you have implement printf function */
-    /*printf("MCAUSE: 0x%lx\r\n", mcause);
-    printf("MEPC  : 0x%lx\r\n", __RV_CSR_READ(CSR_MEPC));
-    printf("MTVAL : 0x%lx\r\n", __RV_CSR_READ(CSR_MBADADDR));*/
-    while (1);
-}
-
-/**
- * \brief      Initialize all the default core exception handlers
- * \details
- * The core exception handler for each exception id will be initialized to \ref system_default_exception_handler.
- * \note
- * Called in \ref _init function, used to initialize default exception handlers for all exception IDs
- */
-static void Exception_Init(void)
-{
-    for (int i = 0; i < MAX_SYSTEM_EXCEPTION_NUM + 1; i++) {
-        SystemExceptionHandlers[i] = (unsigned long)system_default_exception_handler;
-    }
-}
-
-/**
- * \brief       Register an exception handler for exception code EXCn
- * \details
- * * For EXCn < \ref MAX_SYSTEM_EXCEPTION_NUM, it will be registered into SystemExceptionHandlers[EXCn-1].
- * * For EXCn == NMI_EXCn, it will be registered into SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM].
- * \param   EXCn    See \ref EXCn_Type
- * \param   exc_handler     The exception handler for this exception code EXCn
- */
-void Exception_Register_EXC(uint32_t EXCn, unsigned long exc_handler)
-{
-    if ((EXCn < MAX_SYSTEM_EXCEPTION_NUM) && (EXCn != 0)) {
-        SystemExceptionHandlers[EXCn] = exc_handler;
-    } else if (EXCn == NMI_EXCn) {
-        SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM] = exc_handler;
-    }
-}
-
-/**
- * \brief       Get current exception handler for exception code EXCn
- * \details
- * * For EXCn < \ref MAX_SYSTEM_EXCEPTION_NUM, it will return SystemExceptionHandlers[EXCn-1].
- * * For EXCn == NMI_EXCn, it will return SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM].
- * \param   EXCn    See \ref EXCn_Type
- * \return  Current exception handler for exception code EXCn, if not found, return 0.
- */
-unsigned long Exception_Get_EXC(uint32_t EXCn)
-{
-    if ((EXCn < MAX_SYSTEM_EXCEPTION_NUM) && (EXCn != 0)) {
-        return SystemExceptionHandlers[EXCn];
-    } else if (EXCn == NMI_EXCn) {
-        return SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM];
-    } else {
-        return 0;
-    }
-}
-
-/**
- * \brief      Common NMI and Exception handler entry
- * \details
- * This function provided a command entry for NMI and exception. Silicon Vendor could modify
- * this template implementation according to requirement.
- * \remarks
- * - RISCV provided common entry for all types of exception. This is proposed code template
- *   for exception entry function, Silicon Vendor could modify the implementation.
- * - For the core_exception_handler template, we provided exception register function \ref Exception_Register_EXC
- *   which can help developer to register your exception handler for specific exception number.
- */
-uint32_t core_exception_handler(unsigned long mcause, unsigned long sp)
-{
-    uint32_t EXCn = (uint32_t)(mcause & 0X00000fff);
-    EXC_HANDLER exc_handler;
-
-    if ((EXCn < MAX_SYSTEM_EXCEPTION_NUM) && (EXCn > 0)) {
-        exc_handler = (EXC_HANDLER)SystemExceptionHandlers[EXCn];
-    } else if (EXCn == NMI_EXCn) {
-        exc_handler = (EXC_HANDLER)SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM];
-    } else {
-        exc_handler = (EXC_HANDLER)system_default_exception_handler;
-    }
-    if (exc_handler != NULL) {
-        exc_handler(mcause, sp);
-    }
-    return 0;
-}
-/** @} */ /* End of Doxygen Group NMSIS_Core_ExceptionAndNMI */
-
-/**
- * \brief initialize eclic config
- * \details
- * Eclic need initialize after boot up, Vendor could also change the initialization
- * configuration.
- */
-void ECLIC_Init(void)
-{
-    /* TODO: Add your own initialization code here. This function will be called by main */
-    ECLIC_SetMth(0);
-    ECLIC_SetCfgNlbits(__ECLIC_INTCTLBITS);
-}
-
-/**
- * \brief  Initialize a specific IRQ and register the handler
- * \details
- * This function set vector mode, trigger mode and polarity, interrupt level and priority,
- * assign handler for specific IRQn.
- * \param [in]  IRQn        NMI interrupt handler address
- * \param [in]  shv         \ref ECLIC_NON_VECTOR_INTERRUPT means non-vector mode, and \ref ECLIC_VECTOR_INTERRUPT is vector mode
- * \param [in]  trig_mode   see \ref ECLIC_TRIGGER_Type
- * \param [in]  lvl         interupt level
- * \param [in]  priority    interrupt priority
- * \param [in]  handler     interrupt handler, if NULL, handler will not be installed
- * \return       -1 means invalid input parameter. 0 means successful.
- * \remarks
- * - This function use to configure specific eclic interrupt and register its interrupt handler and enable its interrupt.
- * - If the vector table is placed in read-only section(FLASHXIP mode), handler could not be installed
- */
-int32_t ECLIC_Register_IRQ(IRQn_Type IRQn, uint8_t shv, ECLIC_TRIGGER_Type trig_mode, uint8_t lvl, uint8_t priority, void* handler)
-{
-    if ((IRQn > SOC_INT_MAX) || (shv > ECLIC_VECTOR_INTERRUPT) \
-        || (trig_mode > ECLIC_NEGTIVE_EDGE_TRIGGER)) {
-        return -1;
-    }
-
-    /* set interrupt vector mode */
-    ECLIC_SetShvIRQ(IRQn, shv);
-    /* set interrupt trigger mode and polarity */
-    ECLIC_SetTrigIRQ(IRQn, trig_mode);
-    /* set interrupt level */
-    ECLIC_SetLevelIRQ(IRQn, lvl);
-    /* set interrupt priority */
-    ECLIC_SetPriorityIRQ(IRQn, priority);
-    if (handler != NULL) {
-        /* set interrupt handler entry to vector table */
-        ECLIC_SetVector(IRQn, (rv_csr_t)handler);
-    }
-    /* enable interrupt */
-    ECLIC_EnableIRQ(IRQn);
-    return 0;
-}
-/** @} */ /* End of Doxygen Group NMSIS_Core_ExceptionAndNMI */
-
-/**
- * \brief early init function before main
- * \details
- * This function is executed right before main function.
- * For RISC-V gnu toolchain, _init function might not be called
- * by __libc_init_array function, so we defined a new function
- * to do initialization
- */
-void _premain_init(void)
-{
-    /* Initialize exception default handlers */
-    Exception_Init();
-    /* ECLIC initialization, mainly MTH and NLBIT */
-    ECLIC_Init();
-}
-
-/**
- * \brief finish function after main
- * \param [in]  status     status code return from main
- * \details
- * This function is executed right after main function.
- * For RISC-V gnu toolchain, _fini function might not be called
- * by __libc_fini_array function, so we defined a new function
- * to do initialization
- */
-void _postmain_fini(int status)
-{
-    /* TODO: Add your own finishing code here, called after main */
-}
-
-/**
- * \brief _init function called in __libc_init_array()
- * \details
- * This `__libc_init_array()` function is called during startup code,
- * user need to implement this function, otherwise when link it will
- * error init.c:(.text.__libc_init_array+0x26): undefined reference to `_init'
- * \note
- * Please use \ref _premain_init function now
- */
-void _init(void)
-{
-    /* Don't put any code here, please use _premain_init now */
-}
-
-/**
- * \brief _fini function called in __libc_fini_array()
- * \details
- * This `__libc_fini_array()` function is called when exit main.
- * user need to implement this function, otherwise when link it will
- * error fini.c:(.text.__libc_fini_array+0x28): undefined reference to `_fini'
- * \note
- * Please use \ref _postmain_fini function now
- */
-void _fini(void)
-{
-    /* Don't put any code here, please use _postmain_fini now */
-}
-
-/** @} */ /* End of Doxygen Group NMSIS_Core_SystemAndClock */
diff --git a/tinyusb/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h b/tinyusb/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h
deleted file mode 100755
index 4f21b52f..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#include "fsl_device_registers.h"
-
-// required since iMX RT10xx SDK include this file for board size
-#define BOARD_FLASH_SIZE (0x1000000U)
-
-// LED
-#define LED_PINMUX            IOMUXC_GPIO_11_GPIOMUX_IO11
-#define LED_PORT              GPIO1
-#define LED_PIN               11
-#define LED_STATE_ON          0
-
-// SW8 button
-#define BUTTON_PINMUX         IOMUXC_GPIO_SD_05_GPIO2_IO05
-#define BUTTON_PORT           GPIO2
-#define BUTTON_PIN            5
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_PORT             LPUART1
-#define UART_RX_PINMUX        IOMUXC_GPIO_09_LPUART1_RXD
-#define UART_TX_PINMUX        IOMUXC_GPIO_10_LPUART1_TXD
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk b/tinyusb/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk
deleted file mode 100755
index 507db7f0..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-CFLAGS += -DCPU_MIMXRT1011DAE5A
-MCU_VARIANT = MIMXRT1011
-
-# For flash-jlink target
-JLINK_DEVICE = MIMXRT1011DAE5A
-
-# For flash-pyocd target
-PYOCD_TARGET = mimxrt1010
-
-# flash using pyocd
-flash: flash-pyocd
diff --git a/tinyusb/hw/bsp/imxrt/boards/mimxrt1010_evk/evkmimxrt1010_flexspi_nor_config.c b/tinyusb/hw/bsp/imxrt/boards/mimxrt1010_evk/evkmimxrt1010_flexspi_nor_config.c
deleted file mode 100755
index cd50a93d..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/mimxrt1010_evk/evkmimxrt1010_flexspi_nor_config.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright 2019 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include "evkmimxrt1010_flexspi_nor_config.h"
-
-/* Component ID definition, used by tools. */
-#ifndef FSL_COMPONENT_ID
-#define FSL_COMPONENT_ID "platform.drivers.xip_board"
-#endif
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
-#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
-__attribute__((section(".boot_hdr.conf")))
-#elif defined(__ICCARM__)
-#pragma location = ".boot_hdr.conf"
-#endif
-
-const flexspi_nor_config_t qspiflash_config = {
-    .memConfig =
-        {
-            .tag              = FLEXSPI_CFG_BLK_TAG,
-            .version          = FLEXSPI_CFG_BLK_VERSION,
-            .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
-            .csHoldTime       = 3u,
-            .csSetupTime      = 3u,
-            .sflashPadType    = kSerialFlash_4Pads,
-            .serialClkFreq    = kFlexSpiSerialClk_100MHz,
-            .sflashA1Size     = 16u * 1024u * 1024u,
-            .lookupTable =
-                {
-                    // Read LUTs
-                    FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
-                    FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
-                },
-        },
-    .pageSize           = 256u,
-    .sectorSize         = 4u * 1024u,
-    .blockSize          = 256u * 1024u,
-    .isUniformBlockSize = false,
-};
-#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/tinyusb/hw/bsp/imxrt/boards/mimxrt1010_evk/evkmimxrt1010_flexspi_nor_config.h b/tinyusb/hw/bsp/imxrt/boards/mimxrt1010_evk/evkmimxrt1010_flexspi_nor_config.h
deleted file mode 100755
index 4be2760b..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/mimxrt1010_evk/evkmimxrt1010_flexspi_nor_config.h
+++ /dev/null
@@ -1,267 +0,0 @@
-/*
- * Copyright 2019 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__
-#define __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "fsl_common.h"
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief XIP_BOARD driver version 2.0.0. */
-#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
-/* FLEXSPI memory config block related defintions */
-#define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
-#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
-#define FLEXSPI_CFG_BLK_SIZE (512)
-
-/* FLEXSPI Feature related definitions */
-#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
-
-/* Lookup table related defintions */
-#define CMD_INDEX_READ 0
-#define CMD_INDEX_READSTATUS 1
-#define CMD_INDEX_WRITEENABLE 2
-#define CMD_INDEX_WRITE 4
-
-#define CMD_LUT_SEQ_IDX_READ 0
-#define CMD_LUT_SEQ_IDX_READSTATUS 1
-#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
-#define CMD_LUT_SEQ_IDX_WRITE 9
-
-#define CMD_SDR 0x01
-#define CMD_DDR 0x21
-#define RADDR_SDR 0x02
-#define RADDR_DDR 0x22
-#define CADDR_SDR 0x03
-#define CADDR_DDR 0x23
-#define MODE1_SDR 0x04
-#define MODE1_DDR 0x24
-#define MODE2_SDR 0x05
-#define MODE2_DDR 0x25
-#define MODE4_SDR 0x06
-#define MODE4_DDR 0x26
-#define MODE8_SDR 0x07
-#define MODE8_DDR 0x27
-#define WRITE_SDR 0x08
-#define WRITE_DDR 0x28
-#define READ_SDR 0x09
-#define READ_DDR 0x29
-#define LEARN_SDR 0x0A
-#define LEARN_DDR 0x2A
-#define DATSZ_SDR 0x0B
-#define DATSZ_DDR 0x2B
-#define DUMMY_SDR 0x0C
-#define DUMMY_DDR 0x2C
-#define DUMMY_RWDS_SDR 0x0D
-#define DUMMY_RWDS_DDR 0x2D
-#define JMP_ON_CS 0x1F
-#define STOP 0
-
-#define FLEXSPI_1PAD 0
-#define FLEXSPI_2PAD 1
-#define FLEXSPI_4PAD 2
-#define FLEXSPI_8PAD 3
-
-#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)                                                              \
-    (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
-     FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
-
-//!@brief Definitions for FlexSPI Serial Clock Frequency
-typedef enum _FlexSpiSerialClockFreq
-{
-    kFlexSpiSerialClk_30MHz  = 1,
-    kFlexSpiSerialClk_50MHz  = 2,
-    kFlexSpiSerialClk_60MHz  = 3,
-    kFlexSpiSerialClk_75MHz  = 4,
-    kFlexSpiSerialClk_80MHz  = 5,
-    kFlexSpiSerialClk_100MHz = 6,
-    kFlexSpiSerialClk_120MHz = 7,
-    kFlexSpiSerialClk_133MHz = 8,
-} flexspi_serial_clk_freq_t;
-
-//!@brief FlexSPI clock configuration type
-enum
-{
-    kFlexSpiClk_SDR, //!< Clock configure for SDR mode
-    kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
-};
-
-//!@brief FlexSPI Read Sample Clock Source definition
-typedef enum _FlashReadSampleClkSource
-{
-    kFlexSPIReadSampleClk_LoopbackInternally      = 0,
-    kFlexSPIReadSampleClk_LoopbackFromDqsPad      = 1,
-    kFlexSPIReadSampleClk_LoopbackFromSckPad      = 2,
-    kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
-} flexspi_read_sample_clk_t;
-
-//!@brief Misc feature bit definitions
-enum
-{
-    kFlexSpiMiscOffset_DiffClkEnable            = 0, //!< Bit for Differential clock enable
-    kFlexSpiMiscOffset_Ck2Enable                = 1, //!< Bit for CK2 enable
-    kFlexSpiMiscOffset_ParallelEnable           = 2, //!< Bit for Parallel mode enable
-    kFlexSpiMiscOffset_WordAddressableEnable    = 3, //!< Bit for Word Addressable enable
-    kFlexSpiMiscOffset_SafeConfigFreqEnable     = 4, //!< Bit for Safe Configuration Frequency enable
-    kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
-    kFlexSpiMiscOffset_DdrModeEnable            = 6, //!< Bit for DDR clock confiuration indication.
-};
-
-//!@brief Flash Type Definition
-enum
-{
-    kFlexSpiDeviceType_SerialNOR    = 1,    //!< Flash devices are Serial NOR
-    kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
-    kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
-    kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
-    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
-};
-
-//!@brief Flash Pad Definitions
-enum
-{
-    kSerialFlash_1Pad  = 1,
-    kSerialFlash_2Pads = 2,
-    kSerialFlash_4Pads = 4,
-    kSerialFlash_8Pads = 8,
-};
-
-//!@brief FlexSPI LUT Sequence structure
-typedef struct _lut_sequence
-{
-    uint8_t seqNum; //!< Sequence Number, valid number: 1-16
-    uint8_t seqId;  //!< Sequence Index, valid number: 0-15
-    uint16_t reserved;
-} flexspi_lut_seq_t;
-
-//!@brief Flash Configuration Command Type
-enum
-{
-    kDeviceConfigCmdType_Generic,    //!< Generic command, for example: configure dummy cycles, drive strength, etc
-    kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
-    kDeviceConfigCmdType_Spi2Xpi,    //!< Switch from SPI to DPI/QPI/OPI mode
-    kDeviceConfigCmdType_Xpi2Spi,    //!< Switch from DPI/QPI/OPI to SPI mode
-    kDeviceConfigCmdType_Spi2NoCmd,  //!< Switch to 0-4-4/0-8-8 mode
-    kDeviceConfigCmdType_Reset,      //!< Reset device command
-};
-
-//!@brief FlexSPI Memory Configuration Block
-typedef struct _FlexSPIConfig
-{
-    uint32_t tag;               //!< [0x000-0x003] Tag, fixed value 0x42464346UL
-    uint32_t version;           //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
-    uint32_t reserved0;         //!< [0x008-0x00b] Reserved for future use
-    uint8_t readSampleClkSrc;   //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
-    uint8_t csHoldTime;         //!< [0x00d-0x00d] CS hold time, default value: 3
-    uint8_t csSetupTime;        //!< [0x00e-0x00e] CS setup time, default value: 3
-    uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
-    //! Serial NAND, need to refer to datasheet
-    uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
-    uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
-    //! Generic configuration, etc.
-    uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
-    //! DPI/QPI/OPI switch or reset command
-    flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
-    //! sequence number, [31:16] Reserved
-    uint32_t deviceModeArg;    //!< [0x018-0x01b] Argument/Parameter for device configuration
-    uint8_t configCmdEnable;   //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
-    uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
-    flexspi_lut_seq_t
-        configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
-    uint32_t reserved1;   //!< [0x02c-0x02f] Reserved for future use
-    uint32_t configCmdArgs[3];     //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
-    uint32_t reserved2;            //!< [0x03c-0x03f] Reserved for future use
-    uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
-    //! details
-    uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
-    uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
-    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
-    //! Chapter for more details
-    uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
-    //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
-    uint32_t reserved3[2];           //!< [0x048-0x04f] Reserved for future use
-    uint32_t sflashA1Size;           //!< [0x050-0x053] Size of Flash connected to A1
-    uint32_t sflashA2Size;           //!< [0x054-0x057] Size of Flash connected to A2
-    uint32_t sflashB1Size;           //!< [0x058-0x05b] Size of Flash connected to B1
-    uint32_t sflashB2Size;           //!< [0x05c-0x05f] Size of Flash connected to B2
-    uint32_t csPadSettingOverride;   //!< [0x060-0x063] CS pad setting override value
-    uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
-    uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
-    uint32_t dqsPadSettingOverride;  //!< [0x06c-0x06f] DQS pad setting override value
-    uint32_t timeoutInMs;            //!< [0x070-0x073] Timeout threshold for read status command
-    uint32_t commandInterval;        //!< [0x074-0x077] CS deselect interval between two commands
-    uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
-    uint16_t busyOffset;       //!< [0x07c-0x07d] Busy offset, valid value: 0-31
-    uint16_t busyBitPolarity;  //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
-    //! busy flag is 0 when flash device is busy
-    uint32_t lookupTable[64];           //!< [0x080-0x17f] Lookup table holds Flash command sequences
-    flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
-    uint32_t reserved4[4];              //!< [0x1b0-0x1bf] Reserved for future use
-} flexspi_mem_config_t;
-
-/*  */
-#define NOR_CMD_INDEX_READ CMD_INDEX_READ               //!< 0
-#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS   //!< 1
-#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
-#define NOR_CMD_INDEX_ERASESECTOR 3                     //!< 3
-#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE       //!< 4
-#define NOR_CMD_INDEX_CHIPERASE 5                       //!< 5
-#define NOR_CMD_INDEX_DUMMY 6                           //!< 6
-#define NOR_CMD_INDEX_ERASEBLOCK 7                      //!< 7
-
-#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0  READ LUT sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
-    CMD_LUT_SEQ_IDX_READSTATUS //!< 1  Read Status LUT sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
-    2 //!< 2  Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
-    CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3  Write Enable sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
-    4 //!< 4  Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5  Erase Sector sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8  //!< 8 Erase Block sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
-    CMD_LUT_SEQ_IDX_WRITE                //!< 9  Program sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
-    14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
-    15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
-
-/*
- *  Serial NOR configuration block
- */
-typedef struct _flexspi_nor_config
-{
-    flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
-    uint32_t pageSize;              //!< Page size of Serial NOR
-    uint32_t sectorSize;            //!< Sector size of Serial NOR
-    uint8_t ipcmdSerialClkFreq;     //!< Clock frequency for IP command
-    uint8_t isUniformBlockSize;     //!< Sector/Block size is the same
-    uint8_t reserved0[2];           //!< Reserved for future use
-    uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
-    uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
-    uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
-    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
-    uint32_t blockSize;             //!< Block size
-    uint32_t reserve2[11];          //!< Reserved for future use
-} flexspi_nor_config_t;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__ */
diff --git a/tinyusb/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h b/tinyusb/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h
deleted file mode 100755
index 932ce7fd..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-// required since iMX RT10xx SDK include this file for board size
-#define BOARD_FLASH_SIZE (0x1000000U)
-
-// LED
-#define LED_PINMUX            IOMUXC_GPIO_SD_B1_01_GPIO3_IO21
-#define LED_PORT              GPIO3
-#define LED_PIN               21
-#define LED_STATE_ON          0
-
-// SW8 button
-#define BUTTON_PINMUX         IOMUXC_GPIO_EMC_09_GPIO2_IO09
-#define BUTTON_PORT           GPIO2
-#define BUTTON_PIN            9
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_PORT             LPUART1
-#define UART_RX_PINMUX        IOMUXC_GPIO_AD_B0_07_LPUART1_RX
-#define UART_TX_PINMUX        IOMUXC_GPIO_AD_B0_06_LPUART1_TX
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/imxrt/boards/mimxrt1015_evk/board.mk b/tinyusb/hw/bsp/imxrt/boards/mimxrt1015_evk/board.mk
deleted file mode 100755
index 17fd25df..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/mimxrt1015_evk/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-CFLAGS += -DCPU_MIMXRT1015DAF5A
-MCU_VARIANT = MIMXRT1015
-
-# For flash-jlink target
-JLINK_DEVICE = MIMXRT1015DAF5A
-
-# For flash-pyocd target
-PYOCD_TARGET = mimxrt1015
-
-# flash using pyocd
-flash: flash-pyocd
diff --git a/tinyusb/hw/bsp/imxrt/boards/mimxrt1015_evk/evkmimxrt1015_flexspi_nor_config.c b/tinyusb/hw/bsp/imxrt/boards/mimxrt1015_evk/evkmimxrt1015_flexspi_nor_config.c
deleted file mode 100755
index a396fe60..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/mimxrt1015_evk/evkmimxrt1015_flexspi_nor_config.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright 2018-2019 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include "evkmimxrt1015_flexspi_nor_config.h"
-
-/* Component ID definition, used by tools. */
-#ifndef FSL_COMPONENT_ID
-#define FSL_COMPONENT_ID "platform.drivers.xip_board"
-#endif
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
-#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
-__attribute__((section(".boot_hdr.conf")))
-#elif defined(__ICCARM__)
-#pragma location = ".boot_hdr.conf"
-#endif
-
-const flexspi_nor_config_t qspiflash_config = {
-    .memConfig =
-        {
-            .tag              = FLEXSPI_CFG_BLK_TAG,
-            .version          = FLEXSPI_CFG_BLK_VERSION,
-            .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
-            .csHoldTime       = 3u,
-            .csSetupTime      = 3u,
-            .sflashPadType    = kSerialFlash_4Pads,
-            .serialClkFreq    = kFlexSpiSerialClk_100MHz,
-            .sflashA1Size     = 16u * 1024u * 1024u,
-            .lookupTable =
-                {
-                    // Read LUTs
-                    FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
-                    FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
-                },
-        },
-    .pageSize           = 256u,
-    .sectorSize         = 4u * 1024u,
-    .blockSize          = 256u * 1024u,
-    .isUniformBlockSize = false,
-};
-#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/tinyusb/hw/bsp/imxrt/boards/mimxrt1015_evk/evkmimxrt1015_flexspi_nor_config.h b/tinyusb/hw/bsp/imxrt/boards/mimxrt1015_evk/evkmimxrt1015_flexspi_nor_config.h
deleted file mode 100755
index 94af5a11..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/mimxrt1015_evk/evkmimxrt1015_flexspi_nor_config.h
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * Copyright 2018-2019 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __EVKMIMXRT1015_FLEXSPI_NOR_CONFIG__
-#define __EVKMIMXRT1015_FLEXSPI_NOR_CONFIG__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "fsl_common.h"
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief XIP_BOARD driver version 2.0.0. */
-#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
-/* FLEXSPI memory config block related defintions */
-#define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
-#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
-#define FLEXSPI_CFG_BLK_SIZE (512)
-
-/* FLEXSPI Feature related definitions */
-#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
-
-/* Lookup table related defintions */
-#define CMD_INDEX_READ 0
-#define CMD_INDEX_READSTATUS 1
-#define CMD_INDEX_WRITEENABLE 2
-#define CMD_INDEX_WRITE 4
-
-#define CMD_LUT_SEQ_IDX_READ 0
-#define CMD_LUT_SEQ_IDX_READSTATUS 1
-#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
-#define CMD_LUT_SEQ_IDX_WRITE 9
-
-#define CMD_SDR 0x01
-#define CMD_DDR 0x21
-#define RADDR_SDR 0x02
-#define RADDR_DDR 0x22
-#define CADDR_SDR 0x03
-#define CADDR_DDR 0x23
-#define MODE1_SDR 0x04
-#define MODE1_DDR 0x24
-#define MODE2_SDR 0x05
-#define MODE2_DDR 0x25
-#define MODE4_SDR 0x06
-#define MODE4_DDR 0x26
-#define MODE8_SDR 0x07
-#define MODE8_DDR 0x27
-#define WRITE_SDR 0x08
-#define WRITE_DDR 0x28
-#define READ_SDR 0x09
-#define READ_DDR 0x29
-#define LEARN_SDR 0x0A
-#define LEARN_DDR 0x2A
-#define DATSZ_SDR 0x0B
-#define DATSZ_DDR 0x2B
-#define DUMMY_SDR 0x0C
-#define DUMMY_DDR 0x2C
-#define DUMMY_RWDS_SDR 0x0D
-#define DUMMY_RWDS_DDR 0x2D
-#define JMP_ON_CS 0x1F
-#define STOP 0
-
-#define FLEXSPI_1PAD 0
-#define FLEXSPI_2PAD 1
-#define FLEXSPI_4PAD 2
-#define FLEXSPI_8PAD 3
-
-#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)                                                              \
-    (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
-     FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
-
-//!@brief Definitions for FlexSPI Serial Clock Frequency
-typedef enum _FlexSpiSerialClockFreq
-{
-    kFlexSpiSerialClk_30MHz  = 1,
-    kFlexSpiSerialClk_50MHz  = 2,
-    kFlexSpiSerialClk_60MHz  = 3,
-    kFlexSpiSerialClk_75MHz  = 4,
-    kFlexSpiSerialClk_80MHz  = 5,
-    kFlexSpiSerialClk_100MHz = 6,
-    kFlexSpiSerialClk_133MHz = 7,
-    kFlexSpiSerialClk_166MHz = 8,
-    kFlexSpiSerialClk_200MHz = 9,
-} flexspi_serial_clk_freq_t;
-
-//!@brief FlexSPI clock configuration type
-enum
-{
-    kFlexSpiClk_SDR, //!< Clock configure for SDR mode
-    kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
-};
-
-//!@brief FlexSPI Read Sample Clock Source definition
-typedef enum _FlashReadSampleClkSource
-{
-    kFlexSPIReadSampleClk_LoopbackInternally      = 0,
-    kFlexSPIReadSampleClk_LoopbackFromDqsPad      = 1,
-    kFlexSPIReadSampleClk_LoopbackFromSckPad      = 2,
-    kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
-} flexspi_read_sample_clk_t;
-
-//!@brief Misc feature bit definitions
-enum
-{
-    kFlexSpiMiscOffset_DiffClkEnable            = 0, //!< Bit for Differential clock enable
-    kFlexSpiMiscOffset_Ck2Enable                = 1, //!< Bit for CK2 enable
-    kFlexSpiMiscOffset_ParallelEnable           = 2, //!< Bit for Parallel mode enable
-    kFlexSpiMiscOffset_WordAddressableEnable    = 3, //!< Bit for Word Addressable enable
-    kFlexSpiMiscOffset_SafeConfigFreqEnable     = 4, //!< Bit for Safe Configuration Frequency enable
-    kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
-    kFlexSpiMiscOffset_DdrModeEnable            = 6, //!< Bit for DDR clock confiuration indication.
-};
-
-//!@brief Flash Type Definition
-enum
-{
-    kFlexSpiDeviceType_SerialNOR    = 1,    //!< Flash devices are Serial NOR
-    kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
-    kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
-    kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
-    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
-};
-
-//!@brief Flash Pad Definitions
-enum
-{
-    kSerialFlash_1Pad  = 1,
-    kSerialFlash_2Pads = 2,
-    kSerialFlash_4Pads = 4,
-    kSerialFlash_8Pads = 8,
-};
-
-//!@brief FlexSPI LUT Sequence structure
-typedef struct _lut_sequence
-{
-    uint8_t seqNum; //!< Sequence Number, valid number: 1-16
-    uint8_t seqId;  //!< Sequence Index, valid number: 0-15
-    uint16_t reserved;
-} flexspi_lut_seq_t;
-
-//!@brief Flash Configuration Command Type
-enum
-{
-    kDeviceConfigCmdType_Generic,    //!< Generic command, for example: configure dummy cycles, drive strength, etc
-    kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
-    kDeviceConfigCmdType_Spi2Xpi,    //!< Switch from SPI to DPI/QPI/OPI mode
-    kDeviceConfigCmdType_Xpi2Spi,    //!< Switch from DPI/QPI/OPI to SPI mode
-    kDeviceConfigCmdType_Spi2NoCmd,  //!< Switch to 0-4-4/0-8-8 mode
-    kDeviceConfigCmdType_Reset,      //!< Reset device command
-};
-
-//!@brief FlexSPI Memory Configuration Block
-typedef struct _FlexSPIConfig
-{
-    uint32_t tag;               //!< [0x000-0x003] Tag, fixed value 0x42464346UL
-    uint32_t version;           //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
-    uint32_t reserved0;         //!< [0x008-0x00b] Reserved for future use
-    uint8_t readSampleClkSrc;   //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
-    uint8_t csHoldTime;         //!< [0x00d-0x00d] CS hold time, default value: 3
-    uint8_t csSetupTime;        //!< [0x00e-0x00e] CS setup time, default value: 3
-    uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
-    //! Serial NAND, need to refer to datasheet
-    uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
-    uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
-    //! Generic configuration, etc.
-    uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
-    //! DPI/QPI/OPI switch or reset command
-    flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
-    //! sequence number, [31:16] Reserved
-    uint32_t deviceModeArg;    //!< [0x018-0x01b] Argument/Parameter for device configuration
-    uint8_t configCmdEnable;   //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
-    uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
-    flexspi_lut_seq_t
-        configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
-    uint32_t reserved1;   //!< [0x02c-0x02f] Reserved for future use
-    uint32_t configCmdArgs[3];     //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
-    uint32_t reserved2;            //!< [0x03c-0x03f] Reserved for future use
-    uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
-    //! details
-    uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
-    uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
-    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
-    //! Chapter for more details
-    uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
-    //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
-    uint32_t reserved3[2];           //!< [0x048-0x04f] Reserved for future use
-    uint32_t sflashA1Size;           //!< [0x050-0x053] Size of Flash connected to A1
-    uint32_t sflashA2Size;           //!< [0x054-0x057] Size of Flash connected to A2
-    uint32_t sflashB1Size;           //!< [0x058-0x05b] Size of Flash connected to B1
-    uint32_t sflashB2Size;           //!< [0x05c-0x05f] Size of Flash connected to B2
-    uint32_t csPadSettingOverride;   //!< [0x060-0x063] CS pad setting override value
-    uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
-    uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
-    uint32_t dqsPadSettingOverride;  //!< [0x06c-0x06f] DQS pad setting override value
-    uint32_t timeoutInMs;            //!< [0x070-0x073] Timeout threshold for read status command
-    uint32_t commandInterval;        //!< [0x074-0x077] CS deselect interval between two commands
-    uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
-    uint16_t busyOffset;       //!< [0x07c-0x07d] Busy offset, valid value: 0-31
-    uint16_t busyBitPolarity;  //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
-    //! busy flag is 0 when flash device is busy
-    uint32_t lookupTable[64];           //!< [0x080-0x17f] Lookup table holds Flash command sequences
-    flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
-    uint32_t reserved4[4];              //!< [0x1b0-0x1bf] Reserved for future use
-} flexspi_mem_config_t;
-
-/*  */
-#define NOR_CMD_INDEX_READ CMD_INDEX_READ               //!< 0
-#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS   //!< 1
-#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
-#define NOR_CMD_INDEX_ERASESECTOR 3                     //!< 3
-#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE       //!< 4
-#define NOR_CMD_INDEX_CHIPERASE 5                       //!< 5
-#define NOR_CMD_INDEX_DUMMY 6                           //!< 6
-#define NOR_CMD_INDEX_ERASEBLOCK 7                      //!< 7
-
-#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0  READ LUT sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
-    CMD_LUT_SEQ_IDX_READSTATUS //!< 1  Read Status LUT sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
-    2 //!< 2  Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
-    CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3  Write Enable sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
-    4 //!< 4  Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5  Erase Sector sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8  //!< 8 Erase Block sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
-    CMD_LUT_SEQ_IDX_WRITE                //!< 9  Program sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
-    14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
-    15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
-
-/*
- *  Serial NOR configuration block
- */
-typedef struct _flexspi_nor_config
-{
-    flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
-    uint32_t pageSize;              //!< Page size of Serial NOR
-    uint32_t sectorSize;            //!< Sector size of Serial NOR
-    uint8_t ipcmdSerialClkFreq;     //!< Clock frequency for IP command
-    uint8_t isUniformBlockSize;     //!< Sector/Block size is the same
-    uint8_t reserved0[2];           //!< Reserved for future use
-    uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
-    uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
-    uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
-    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
-    uint32_t blockSize;             //!< Block size
-    uint32_t reserve2[11];          //!< Reserved for future use
-} flexspi_nor_config_t;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* __EVKMIMXRT1015_FLEXSPI_NOR_CONFIG__ */
diff --git a/tinyusb/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h b/tinyusb/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h
deleted file mode 100755
index 56ed5855..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-// required since iMX RT10xx SDK include this file for board size
-#define BOARD_FLASH_SIZE (0x800000U)
-
-// LED
-#define LED_PINMUX            IOMUXC_GPIO_AD_B0_05_GPIO1_IO05
-#define LED_PORT              GPIO1
-#define LED_PIN               5
-#define LED_STATE_ON          0
-
-// SW8 button
-#define BUTTON_PINMUX         IOMUXC_SNVS_WAKEUP_GPIO5_IO00
-#define BUTTON_PORT           GPIO5
-#define BUTTON_PIN            0
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_PORT             LPUART1
-#define UART_RX_PINMUX        IOMUXC_GPIO_AD_B0_07_LPUART1_RX
-#define UART_TX_PINMUX        IOMUXC_GPIO_AD_B0_06_LPUART1_TX
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk b/tinyusb/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk
deleted file mode 100755
index b15da1b6..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-CFLAGS += -DCPU_MIMXRT1021DAG5A
-MCU_VARIANT = MIMXRT1021
-
-# For flash-jlink target
-JLINK_DEVICE = MIMXRT1021DAG5A
-
-# For flash-pyocd target
-PYOCD_TARGET = mimxrt1020
-
-# flash using pyocd
-flash: flash-pyocd
diff --git a/tinyusb/hw/bsp/imxrt/boards/mimxrt1020_evk/evkmimxrt1020_flexspi_nor_config.c b/tinyusb/hw/bsp/imxrt/boards/mimxrt1020_evk/evkmimxrt1020_flexspi_nor_config.c
deleted file mode 100755
index 6bafe195..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/mimxrt1020_evk/evkmimxrt1020_flexspi_nor_config.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright 2018 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include "evkmimxrt1020_flexspi_nor_config.h"
-
-/* Component ID definition, used by tools. */
-#ifndef FSL_COMPONENT_ID
-#define FSL_COMPONENT_ID "platform.drivers.xip_board"
-#endif
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
-#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
-__attribute__((section(".boot_hdr.conf")))
-#elif defined(__ICCARM__)
-#pragma location = ".boot_hdr.conf"
-#endif
-
-const flexspi_nor_config_t qspiflash_config = {
-    .memConfig =
-        {
-            .tag              = FLEXSPI_CFG_BLK_TAG,
-            .version          = FLEXSPI_CFG_BLK_VERSION,
-            .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
-            .csHoldTime       = 3u,
-            .csSetupTime      = 3u,
-            // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
-            .sflashPadType = kSerialFlash_4Pads,
-            .serialClkFreq = kFlexSpiSerialClk_100MHz,
-            .sflashA1Size  = 8u * 1024u * 1024u,
-            .lookupTable =
-                {
-                    // Read LUTs
-                    FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
-                    FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
-                },
-        },
-    .pageSize           = 256u,
-    .sectorSize         = 4u * 1024u,
-    .blockSize          = 256u * 1024u,
-    .isUniformBlockSize = false,
-};
-#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/tinyusb/hw/bsp/imxrt/boards/mimxrt1020_evk/evkmimxrt1020_flexspi_nor_config.h b/tinyusb/hw/bsp/imxrt/boards/mimxrt1020_evk/evkmimxrt1020_flexspi_nor_config.h
deleted file mode 100755
index f5e1aca5..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/mimxrt1020_evk/evkmimxrt1020_flexspi_nor_config.h
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * Copyright 2018 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __EVKMIMXRT1020_FLEXSPI_NOR_CONFIG__
-#define __EVKMIMXRT1020_FLEXSPI_NOR_CONFIG__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "fsl_common.h"
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief XIP_BOARD driver version 2.0.0. */
-#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
-/* FLEXSPI memory config block related defintions */
-#define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
-#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
-#define FLEXSPI_CFG_BLK_SIZE (512)
-
-/* FLEXSPI Feature related definitions */
-#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
-
-/* Lookup table related defintions */
-#define CMD_INDEX_READ 0
-#define CMD_INDEX_READSTATUS 1
-#define CMD_INDEX_WRITEENABLE 2
-#define CMD_INDEX_WRITE 4
-
-#define CMD_LUT_SEQ_IDX_READ 0
-#define CMD_LUT_SEQ_IDX_READSTATUS 1
-#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
-#define CMD_LUT_SEQ_IDX_WRITE 9
-
-#define CMD_SDR 0x01
-#define CMD_DDR 0x21
-#define RADDR_SDR 0x02
-#define RADDR_DDR 0x22
-#define CADDR_SDR 0x03
-#define CADDR_DDR 0x23
-#define MODE1_SDR 0x04
-#define MODE1_DDR 0x24
-#define MODE2_SDR 0x05
-#define MODE2_DDR 0x25
-#define MODE4_SDR 0x06
-#define MODE4_DDR 0x26
-#define MODE8_SDR 0x07
-#define MODE8_DDR 0x27
-#define WRITE_SDR 0x08
-#define WRITE_DDR 0x28
-#define READ_SDR 0x09
-#define READ_DDR 0x29
-#define LEARN_SDR 0x0A
-#define LEARN_DDR 0x2A
-#define DATSZ_SDR 0x0B
-#define DATSZ_DDR 0x2B
-#define DUMMY_SDR 0x0C
-#define DUMMY_DDR 0x2C
-#define DUMMY_RWDS_SDR 0x0D
-#define DUMMY_RWDS_DDR 0x2D
-#define JMP_ON_CS 0x1F
-#define STOP 0
-
-#define FLEXSPI_1PAD 0
-#define FLEXSPI_2PAD 1
-#define FLEXSPI_4PAD 2
-#define FLEXSPI_8PAD 3
-
-#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)                                                              \
-    (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
-     FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
-
-//!@brief Definitions for FlexSPI Serial Clock Frequency
-typedef enum _FlexSpiSerialClockFreq
-{
-    kFlexSpiSerialClk_30MHz  = 1,
-    kFlexSpiSerialClk_50MHz  = 2,
-    kFlexSpiSerialClk_60MHz  = 3,
-    kFlexSpiSerialClk_75MHz  = 4,
-    kFlexSpiSerialClk_80MHz  = 5,
-    kFlexSpiSerialClk_100MHz = 6,
-    kFlexSpiSerialClk_133MHz = 7,
-    kFlexSpiSerialClk_166MHz = 8,
-    kFlexSpiSerialClk_200MHz = 9,
-} flexspi_serial_clk_freq_t;
-
-//!@brief FlexSPI clock configuration type
-enum
-{
-    kFlexSpiClk_SDR, //!< Clock configure for SDR mode
-    kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
-};
-
-//!@brief FlexSPI Read Sample Clock Source definition
-typedef enum _FlashReadSampleClkSource
-{
-    kFlexSPIReadSampleClk_LoopbackInternally      = 0,
-    kFlexSPIReadSampleClk_LoopbackFromDqsPad      = 1,
-    kFlexSPIReadSampleClk_LoopbackFromSckPad      = 2,
-    kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
-} flexspi_read_sample_clk_t;
-
-//!@brief Misc feature bit definitions
-enum
-{
-    kFlexSpiMiscOffset_DiffClkEnable            = 0, //!< Bit for Differential clock enable
-    kFlexSpiMiscOffset_Ck2Enable                = 1, //!< Bit for CK2 enable
-    kFlexSpiMiscOffset_ParallelEnable           = 2, //!< Bit for Parallel mode enable
-    kFlexSpiMiscOffset_WordAddressableEnable    = 3, //!< Bit for Word Addressable enable
-    kFlexSpiMiscOffset_SafeConfigFreqEnable     = 4, //!< Bit for Safe Configuration Frequency enable
-    kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
-    kFlexSpiMiscOffset_DdrModeEnable            = 6, //!< Bit for DDR clock confiuration indication.
-};
-
-//!@brief Flash Type Definition
-enum
-{
-    kFlexSpiDeviceType_SerialNOR    = 1,    //!< Flash devices are Serial NOR
-    kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
-    kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
-    kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
-    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
-};
-
-//!@brief Flash Pad Definitions
-enum
-{
-    kSerialFlash_1Pad  = 1,
-    kSerialFlash_2Pads = 2,
-    kSerialFlash_4Pads = 4,
-    kSerialFlash_8Pads = 8,
-};
-
-//!@brief FlexSPI LUT Sequence structure
-typedef struct _lut_sequence
-{
-    uint8_t seqNum; //!< Sequence Number, valid number: 1-16
-    uint8_t seqId;  //!< Sequence Index, valid number: 0-15
-    uint16_t reserved;
-} flexspi_lut_seq_t;
-
-//!@brief Flash Configuration Command Type
-enum
-{
-    kDeviceConfigCmdType_Generic,    //!< Generic command, for example: configure dummy cycles, drive strength, etc
-    kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
-    kDeviceConfigCmdType_Spi2Xpi,    //!< Switch from SPI to DPI/QPI/OPI mode
-    kDeviceConfigCmdType_Xpi2Spi,    //!< Switch from DPI/QPI/OPI to SPI mode
-    kDeviceConfigCmdType_Spi2NoCmd,  //!< Switch to 0-4-4/0-8-8 mode
-    kDeviceConfigCmdType_Reset,      //!< Reset device command
-};
-
-//!@brief FlexSPI Memory Configuration Block
-typedef struct _FlexSPIConfig
-{
-    uint32_t tag;               //!< [0x000-0x003] Tag, fixed value 0x42464346UL
-    uint32_t version;           //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
-    uint32_t reserved0;         //!< [0x008-0x00b] Reserved for future use
-    uint8_t readSampleClkSrc;   //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
-    uint8_t csHoldTime;         //!< [0x00d-0x00d] CS hold time, default value: 3
-    uint8_t csSetupTime;        //!< [0x00e-0x00e] CS setup time, default value: 3
-    uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
-    //! Serial NAND, need to refer to datasheet
-    uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
-    uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
-    //! Generic configuration, etc.
-    uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
-    //! DPI/QPI/OPI switch or reset command
-    flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
-    //! sequence number, [31:16] Reserved
-    uint32_t deviceModeArg;    //!< [0x018-0x01b] Argument/Parameter for device configuration
-    uint8_t configCmdEnable;   //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
-    uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
-    flexspi_lut_seq_t
-        configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
-    uint32_t reserved1;   //!< [0x02c-0x02f] Reserved for future use
-    uint32_t configCmdArgs[3];     //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
-    uint32_t reserved2;            //!< [0x03c-0x03f] Reserved for future use
-    uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
-    //! details
-    uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
-    uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
-    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
-    //! Chapter for more details
-    uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
-    //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
-    uint32_t reserved3[2];           //!< [0x048-0x04f] Reserved for future use
-    uint32_t sflashA1Size;           //!< [0x050-0x053] Size of Flash connected to A1
-    uint32_t sflashA2Size;           //!< [0x054-0x057] Size of Flash connected to A2
-    uint32_t sflashB1Size;           //!< [0x058-0x05b] Size of Flash connected to B1
-    uint32_t sflashB2Size;           //!< [0x05c-0x05f] Size of Flash connected to B2
-    uint32_t csPadSettingOverride;   //!< [0x060-0x063] CS pad setting override value
-    uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
-    uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
-    uint32_t dqsPadSettingOverride;  //!< [0x06c-0x06f] DQS pad setting override value
-    uint32_t timeoutInMs;            //!< [0x070-0x073] Timeout threshold for read status command
-    uint32_t commandInterval;        //!< [0x074-0x077] CS deselect interval between two commands
-    uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
-    uint16_t busyOffset;       //!< [0x07c-0x07d] Busy offset, valid value: 0-31
-    uint16_t busyBitPolarity;  //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
-    //! busy flag is 0 when flash device is busy
-    uint32_t lookupTable[64];           //!< [0x080-0x17f] Lookup table holds Flash command sequences
-    flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
-    uint32_t reserved4[4];              //!< [0x1b0-0x1bf] Reserved for future use
-} flexspi_mem_config_t;
-
-/*  */
-#define NOR_CMD_INDEX_READ CMD_INDEX_READ               //!< 0
-#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS   //!< 1
-#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
-#define NOR_CMD_INDEX_ERASESECTOR 3                     //!< 3
-#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE       //!< 4
-#define NOR_CMD_INDEX_CHIPERASE 5                       //!< 5
-#define NOR_CMD_INDEX_DUMMY 6                           //!< 6
-#define NOR_CMD_INDEX_ERASEBLOCK 7                      //!< 7
-
-#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0  READ LUT sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
-    CMD_LUT_SEQ_IDX_READSTATUS //!< 1  Read Status LUT sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
-    2 //!< 2  Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
-    CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3  Write Enable sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
-    4 //!< 4  Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5  Erase Sector sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8  //!< 8 Erase Block sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
-    CMD_LUT_SEQ_IDX_WRITE                //!< 9  Program sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
-    14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
-    15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
-
-/*
- *  Serial NOR configuration block
- */
-typedef struct _flexspi_nor_config
-{
-    flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
-    uint32_t pageSize;              //!< Page size of Serial NOR
-    uint32_t sectorSize;            //!< Sector size of Serial NOR
-    uint8_t ipcmdSerialClkFreq;     //!< Clock frequency for IP command
-    uint8_t isUniformBlockSize;     //!< Sector/Block size is the same
-    uint8_t reserved0[2];           //!< Reserved for future use
-    uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
-    uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
-    uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
-    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
-    uint32_t blockSize;             //!< Block size
-    uint32_t reserve2[11];          //!< Reserved for future use
-} flexspi_nor_config_t;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* __EVKMIMXRT1020_FLEXSPI_NOR_CONFIG__ */
diff --git a/tinyusb/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h b/tinyusb/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h
deleted file mode 100755
index 928fbd72..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-// required since iMX RT10xx SDK include this file for board size
-#define BOARD_FLASH_SIZE (0x4000000U)
-
-// LED
-#define LED_PINMUX            IOMUXC_GPIO_AD_B0_09_GPIO1_IO09
-#define LED_PORT              GPIO1
-#define LED_PIN               9
-#define LED_STATE_ON          0
-
-// SW8 button
-#define BUTTON_PINMUX         IOMUXC_SNVS_WAKEUP_GPIO5_IO00
-#define BUTTON_PORT           GPIO5
-#define BUTTON_PIN            0
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_PORT             LPUART1
-#define UART_RX_PINMUX        IOMUXC_GPIO_AD_B0_13_LPUART1_RX
-#define UART_TX_PINMUX        IOMUXC_GPIO_AD_B0_12_LPUART1_TX
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk b/tinyusb/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk
deleted file mode 100755
index 9fd22910..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-CFLAGS += -DCPU_MIMXRT1052DVL6B
-MCU_VARIANT = MIMXRT1052
-
-# For flash-pyocd target
-PYOCD_TARGET = mimxrt1050
-
-# flash using pyocd
-flash: flash-pyocd
diff --git a/tinyusb/hw/bsp/imxrt/boards/mimxrt1050_evkb/evkbimxrt1050_flexspi_nor_config.c b/tinyusb/hw/bsp/imxrt/boards/mimxrt1050_evkb/evkbimxrt1050_flexspi_nor_config.c
deleted file mode 100755
index af6eabc8..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/mimxrt1050_evkb/evkbimxrt1050_flexspi_nor_config.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright 2017 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include "evkbimxrt1050_flexspi_nor_config.h"
-
-/* Component ID definition, used by tools. */
-#ifndef FSL_COMPONENT_ID
-#define FSL_COMPONENT_ID "platform.drivers.xip_board"
-#endif
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
-#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
-__attribute__((section(".boot_hdr.conf")))
-#elif defined(__ICCARM__)
-#pragma location = ".boot_hdr.conf"
-#endif
-
-const flexspi_nor_config_t hyperflash_config = {
-    .memConfig =
-        {
-            .tag                = FLEXSPI_CFG_BLK_TAG,
-            .version            = FLEXSPI_CFG_BLK_VERSION,
-            .readSampleClkSrc   = kFlexSPIReadSampleClk_ExternalInputFromDqsPad,
-            .csHoldTime         = 3u,
-            .csSetupTime        = 3u,
-            .columnAddressWidth = 3u,
-            // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
-            .controllerMiscOption =
-                (1u << kFlexSpiMiscOffset_DdrModeEnable) | (1u << kFlexSpiMiscOffset_WordAddressableEnable) |
-                (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable),
-            .sflashPadType = kSerialFlash_8Pads,
-            .serialClkFreq = kFlexSpiSerialClk_133MHz,
-            .sflashA1Size  = 64u * 1024u * 1024u,
-            .dataValidTime = {16u, 16u},
-            .lookupTable =
-                {
-                    // Read LUTs
-                    FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18),
-                    FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06),
-                    FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),
-                },
-        },
-    .pageSize           = 512u,
-    .sectorSize         = 256u * 1024u,
-    .blockSize          = 256u * 1024u,
-    .isUniformBlockSize = true,
-};
-#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/tinyusb/hw/bsp/imxrt/boards/mimxrt1050_evkb/evkbimxrt1050_flexspi_nor_config.h b/tinyusb/hw/bsp/imxrt/boards/mimxrt1050_evkb/evkbimxrt1050_flexspi_nor_config.h
deleted file mode 100755
index fe40e7ed..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/mimxrt1050_evkb/evkbimxrt1050_flexspi_nor_config.h
+++ /dev/null
@@ -1,269 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__
-#define __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "fsl_common.h"
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief XIP_BOARD driver version 2.0.0. */
-#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
-/* FLEXSPI memory config block related defintions */
-#define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
-#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
-#define FLEXSPI_CFG_BLK_SIZE (512)
-
-/* FLEXSPI Feature related definitions */
-#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
-
-/* Lookup table related defintions */
-#define CMD_INDEX_READ 0
-#define CMD_INDEX_READSTATUS 1
-#define CMD_INDEX_WRITEENABLE 2
-#define CMD_INDEX_WRITE 4
-
-#define CMD_LUT_SEQ_IDX_READ 0
-#define CMD_LUT_SEQ_IDX_READSTATUS 1
-#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
-#define CMD_LUT_SEQ_IDX_WRITE 9
-
-#define CMD_SDR 0x01
-#define CMD_DDR 0x21
-#define RADDR_SDR 0x02
-#define RADDR_DDR 0x22
-#define CADDR_SDR 0x03
-#define CADDR_DDR 0x23
-#define MODE1_SDR 0x04
-#define MODE1_DDR 0x24
-#define MODE2_SDR 0x05
-#define MODE2_DDR 0x25
-#define MODE4_SDR 0x06
-#define MODE4_DDR 0x26
-#define MODE8_SDR 0x07
-#define MODE8_DDR 0x27
-#define WRITE_SDR 0x08
-#define WRITE_DDR 0x28
-#define READ_SDR 0x09
-#define READ_DDR 0x29
-#define LEARN_SDR 0x0A
-#define LEARN_DDR 0x2A
-#define DATSZ_SDR 0x0B
-#define DATSZ_DDR 0x2B
-#define DUMMY_SDR 0x0C
-#define DUMMY_DDR 0x2C
-#define DUMMY_RWDS_SDR 0x0D
-#define DUMMY_RWDS_DDR 0x2D
-#define JMP_ON_CS 0x1F
-#define STOP 0
-
-#define FLEXSPI_1PAD 0
-#define FLEXSPI_2PAD 1
-#define FLEXSPI_4PAD 2
-#define FLEXSPI_8PAD 3
-
-#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)                                                              \
-    (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
-     FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
-
-//!@brief Definitions for FlexSPI Serial Clock Frequency
-typedef enum _FlexSpiSerialClockFreq
-{
-    kFlexSpiSerialClk_30MHz  = 1,
-    kFlexSpiSerialClk_50MHz  = 2,
-    kFlexSpiSerialClk_60MHz  = 3,
-    kFlexSpiSerialClk_75MHz  = 4,
-    kFlexSpiSerialClk_80MHz  = 5,
-    kFlexSpiSerialClk_100MHz = 6,
-    kFlexSpiSerialClk_133MHz = 7,
-    kFlexSpiSerialClk_166MHz = 8,
-    kFlexSpiSerialClk_200MHz = 9,
-} flexspi_serial_clk_freq_t;
-
-//!@brief FlexSPI clock configuration type
-enum
-{
-    kFlexSpiClk_SDR, //!< Clock configure for SDR mode
-    kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
-};
-
-//!@brief FlexSPI Read Sample Clock Source definition
-typedef enum _FlashReadSampleClkSource
-{
-    kFlexSPIReadSampleClk_LoopbackInternally      = 0,
-    kFlexSPIReadSampleClk_LoopbackFromDqsPad      = 1,
-    kFlexSPIReadSampleClk_LoopbackFromSckPad      = 2,
-    kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
-} flexspi_read_sample_clk_t;
-
-//!@brief Misc feature bit definitions
-enum
-{
-    kFlexSpiMiscOffset_DiffClkEnable            = 0, //!< Bit for Differential clock enable
-    kFlexSpiMiscOffset_Ck2Enable                = 1, //!< Bit for CK2 enable
-    kFlexSpiMiscOffset_ParallelEnable           = 2, //!< Bit for Parallel mode enable
-    kFlexSpiMiscOffset_WordAddressableEnable    = 3, //!< Bit for Word Addressable enable
-    kFlexSpiMiscOffset_SafeConfigFreqEnable     = 4, //!< Bit for Safe Configuration Frequency enable
-    kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
-    kFlexSpiMiscOffset_DdrModeEnable            = 6, //!< Bit for DDR clock confiuration indication.
-};
-
-//!@brief Flash Type Definition
-enum
-{
-    kFlexSpiDeviceType_SerialNOR    = 1,    //!< Flash devices are Serial NOR
-    kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
-    kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
-    kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
-    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
-};
-
-//!@brief Flash Pad Definitions
-enum
-{
-    kSerialFlash_1Pad  = 1,
-    kSerialFlash_2Pads = 2,
-    kSerialFlash_4Pads = 4,
-    kSerialFlash_8Pads = 8,
-};
-
-//!@brief FlexSPI LUT Sequence structure
-typedef struct _lut_sequence
-{
-    uint8_t seqNum; //!< Sequence Number, valid number: 1-16
-    uint8_t seqId;  //!< Sequence Index, valid number: 0-15
-    uint16_t reserved;
-} flexspi_lut_seq_t;
-
-//!@brief Flash Configuration Command Type
-enum
-{
-    kDeviceConfigCmdType_Generic,    //!< Generic command, for example: configure dummy cycles, drive strength, etc
-    kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
-    kDeviceConfigCmdType_Spi2Xpi,    //!< Switch from SPI to DPI/QPI/OPI mode
-    kDeviceConfigCmdType_Xpi2Spi,    //!< Switch from DPI/QPI/OPI to SPI mode
-    kDeviceConfigCmdType_Spi2NoCmd,  //!< Switch to 0-4-4/0-8-8 mode
-    kDeviceConfigCmdType_Reset,      //!< Reset device command
-};
-
-//!@brief FlexSPI Memory Configuration Block
-typedef struct _FlexSPIConfig
-{
-    uint32_t tag;               //!< [0x000-0x003] Tag, fixed value 0x42464346UL
-    uint32_t version;           //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
-    uint32_t reserved0;         //!< [0x008-0x00b] Reserved for future use
-    uint8_t readSampleClkSrc;   //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
-    uint8_t csHoldTime;         //!< [0x00d-0x00d] CS hold time, default value: 3
-    uint8_t csSetupTime;        //!< [0x00e-0x00e] CS setup time, default value: 3
-    uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
-    //! Serial NAND, need to refer to datasheet
-    uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
-    uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
-    //! Generic configuration, etc.
-    uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
-    //! DPI/QPI/OPI switch or reset command
-    flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
-    //! sequence number, [31:16] Reserved
-    uint32_t deviceModeArg;    //!< [0x018-0x01b] Argument/Parameter for device configuration
-    uint8_t configCmdEnable;   //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
-    uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
-    flexspi_lut_seq_t
-        configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
-    uint32_t reserved1;   //!< [0x02c-0x02f] Reserved for future use
-    uint32_t configCmdArgs[3];     //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
-    uint32_t reserved2;            //!< [0x03c-0x03f] Reserved for future use
-    uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
-    //! details
-    uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
-    uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
-    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
-    //! Chapter for more details
-    uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
-    //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
-    uint32_t reserved3[2];           //!< [0x048-0x04f] Reserved for future use
-    uint32_t sflashA1Size;           //!< [0x050-0x053] Size of Flash connected to A1
-    uint32_t sflashA2Size;           //!< [0x054-0x057] Size of Flash connected to A2
-    uint32_t sflashB1Size;           //!< [0x058-0x05b] Size of Flash connected to B1
-    uint32_t sflashB2Size;           //!< [0x05c-0x05f] Size of Flash connected to B2
-    uint32_t csPadSettingOverride;   //!< [0x060-0x063] CS pad setting override value
-    uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
-    uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
-    uint32_t dqsPadSettingOverride;  //!< [0x06c-0x06f] DQS pad setting override value
-    uint32_t timeoutInMs;            //!< [0x070-0x073] Timeout threshold for read status command
-    uint32_t commandInterval;        //!< [0x074-0x077] CS deselect interval between two commands
-    uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
-    uint16_t busyOffset;       //!< [0x07c-0x07d] Busy offset, valid value: 0-31
-    uint16_t busyBitPolarity;  //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
-    //! busy flag is 0 when flash device is busy
-    uint32_t lookupTable[64];           //!< [0x080-0x17f] Lookup table holds Flash command sequences
-    flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
-    uint32_t reserved4[4];              //!< [0x1b0-0x1bf] Reserved for future use
-} flexspi_mem_config_t;
-
-/*  */
-#define NOR_CMD_INDEX_READ CMD_INDEX_READ               //!< 0
-#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS   //!< 1
-#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
-#define NOR_CMD_INDEX_ERASESECTOR 3                     //!< 3
-#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE       //!< 4
-#define NOR_CMD_INDEX_CHIPERASE 5                       //!< 5
-#define NOR_CMD_INDEX_DUMMY 6                           //!< 6
-#define NOR_CMD_INDEX_ERASEBLOCK 7                      //!< 7
-
-#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0  READ LUT sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
-    CMD_LUT_SEQ_IDX_READSTATUS //!< 1  Read Status LUT sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
-    2 //!< 2  Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
-    CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3  Write Enable sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
-    4 //!< 4  Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5  Erase Sector sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8  //!< 8 Erase Block sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
-    CMD_LUT_SEQ_IDX_WRITE                //!< 9  Program sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
-    14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
-    15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
-
-/*
- *  Serial NOR configuration block
- */
-typedef struct _flexspi_nor_config
-{
-    flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
-    uint32_t pageSize;              //!< Page size of Serial NOR
-    uint32_t sectorSize;            //!< Sector size of Serial NOR
-    uint8_t ipcmdSerialClkFreq;     //!< Clock frequency for IP command
-    uint8_t isUniformBlockSize;     //!< Sector/Block size is the same
-    uint8_t reserved0[2];           //!< Reserved for future use
-    uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
-    uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
-    uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
-    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
-    uint32_t blockSize;             //!< Block size
-    uint32_t reserve2[11];          //!< Reserved for future use
-} flexspi_nor_config_t;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__ */
diff --git a/tinyusb/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h b/tinyusb/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h
deleted file mode 100755
index 7fa37e33..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-// required since iMX RT10xx SDK include this file for board size
-#define BOARD_FLASH_SIZE (0x800000U)
-
-// LED
-#define LED_PINMUX            IOMUXC_GPIO_AD_B0_09_GPIO1_IO09
-#define LED_PORT              GPIO1
-#define LED_PIN               9
-#define LED_STATE_ON          0
-
-// SW8 button
-#define BUTTON_PINMUX         IOMUXC_SNVS_WAKEUP_GPIO5_IO00
-#define BUTTON_PORT           GPIO5
-#define BUTTON_PIN            0
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_PORT             LPUART1
-#define UART_RX_PINMUX        IOMUXC_GPIO_AD_B0_13_LPUART1_RX
-#define UART_TX_PINMUX        IOMUXC_GPIO_AD_B0_12_LPUART1_TX
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk b/tinyusb/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk
deleted file mode 100755
index d0498dbb..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-CFLAGS += -DCPU_MIMXRT1062DVL6A
-MCU_VARIANT = MIMXRT1062
-
-# For flash-jlink target
-JLINK_DEVICE = MIMXRT1062xxx6A
-
-# For flash-pyocd target
-PYOCD_TARGET = mimxrt1060
-
-# flash using pyocd
-flash: flash-pyocd
diff --git a/tinyusb/hw/bsp/imxrt/boards/mimxrt1060_evk/evkmimxrt1060_flexspi_nor_config.c b/tinyusb/hw/bsp/imxrt/boards/mimxrt1060_evk/evkmimxrt1060_flexspi_nor_config.c
deleted file mode 100755
index 5df2b7c1..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/mimxrt1060_evk/evkmimxrt1060_flexspi_nor_config.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright 2018 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include "evkmimxrt1060_flexspi_nor_config.h"
-
-/* Component ID definition, used by tools. */
-#ifndef FSL_COMPONENT_ID
-#define FSL_COMPONENT_ID "platform.drivers.xip_board"
-#endif
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
-#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
-__attribute__((section(".boot_hdr.conf")))
-#elif defined(__ICCARM__)
-#pragma location = ".boot_hdr.conf"
-#endif
-
-const flexspi_nor_config_t qspiflash_config = {
-    .memConfig =
-        {
-            .tag              = FLEXSPI_CFG_BLK_TAG,
-            .version          = FLEXSPI_CFG_BLK_VERSION,
-            .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
-            .csHoldTime       = 3u,
-            .csSetupTime      = 3u,
-            // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
-            .sflashPadType = kSerialFlash_4Pads,
-            .serialClkFreq = kFlexSpiSerialClk_100MHz,
-            .sflashA1Size  = 8u * 1024u * 1024u,
-            .lookupTable =
-                {
-                    // Read LUTs
-                    FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
-                    FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
-                },
-        },
-    .pageSize           = 256u,
-    .sectorSize         = 4u * 1024u,
-    .blockSize          = 256u * 1024u,
-    .isUniformBlockSize = false,
-};
-#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/tinyusb/hw/bsp/imxrt/boards/mimxrt1060_evk/evkmimxrt1060_flexspi_nor_config.h b/tinyusb/hw/bsp/imxrt/boards/mimxrt1060_evk/evkmimxrt1060_flexspi_nor_config.h
deleted file mode 100755
index 28d7db57..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/mimxrt1060_evk/evkmimxrt1060_flexspi_nor_config.h
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * Copyright 2018 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__
-#define __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "fsl_common.h"
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief XIP_BOARD driver version 2.0.0. */
-#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
-/* FLEXSPI memory config block related defintions */
-#define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
-#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
-#define FLEXSPI_CFG_BLK_SIZE (512)
-
-/* FLEXSPI Feature related definitions */
-#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
-
-/* Lookup table related defintions */
-#define CMD_INDEX_READ 0
-#define CMD_INDEX_READSTATUS 1
-#define CMD_INDEX_WRITEENABLE 2
-#define CMD_INDEX_WRITE 4
-
-#define CMD_LUT_SEQ_IDX_READ 0
-#define CMD_LUT_SEQ_IDX_READSTATUS 1
-#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
-#define CMD_LUT_SEQ_IDX_WRITE 9
-
-#define CMD_SDR 0x01
-#define CMD_DDR 0x21
-#define RADDR_SDR 0x02
-#define RADDR_DDR 0x22
-#define CADDR_SDR 0x03
-#define CADDR_DDR 0x23
-#define MODE1_SDR 0x04
-#define MODE1_DDR 0x24
-#define MODE2_SDR 0x05
-#define MODE2_DDR 0x25
-#define MODE4_SDR 0x06
-#define MODE4_DDR 0x26
-#define MODE8_SDR 0x07
-#define MODE8_DDR 0x27
-#define WRITE_SDR 0x08
-#define WRITE_DDR 0x28
-#define READ_SDR 0x09
-#define READ_DDR 0x29
-#define LEARN_SDR 0x0A
-#define LEARN_DDR 0x2A
-#define DATSZ_SDR 0x0B
-#define DATSZ_DDR 0x2B
-#define DUMMY_SDR 0x0C
-#define DUMMY_DDR 0x2C
-#define DUMMY_RWDS_SDR 0x0D
-#define DUMMY_RWDS_DDR 0x2D
-#define JMP_ON_CS 0x1F
-#define STOP 0
-
-#define FLEXSPI_1PAD 0
-#define FLEXSPI_2PAD 1
-#define FLEXSPI_4PAD 2
-#define FLEXSPI_8PAD 3
-
-#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)                                                              \
-    (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
-     FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
-
-//!@brief Definitions for FlexSPI Serial Clock Frequency
-typedef enum _FlexSpiSerialClockFreq
-{
-    kFlexSpiSerialClk_30MHz  = 1,
-    kFlexSpiSerialClk_50MHz  = 2,
-    kFlexSpiSerialClk_60MHz  = 3,
-    kFlexSpiSerialClk_75MHz  = 4,
-    kFlexSpiSerialClk_80MHz  = 5,
-    kFlexSpiSerialClk_100MHz = 6,
-    kFlexSpiSerialClk_120MHz = 7,
-    kFlexSpiSerialClk_133MHz = 8,
-    kFlexSpiSerialClk_166MHz = 9,
-} flexspi_serial_clk_freq_t;
-
-//!@brief FlexSPI clock configuration type
-enum
-{
-    kFlexSpiClk_SDR, //!< Clock configure for SDR mode
-    kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
-};
-
-//!@brief FlexSPI Read Sample Clock Source definition
-typedef enum _FlashReadSampleClkSource
-{
-    kFlexSPIReadSampleClk_LoopbackInternally      = 0,
-    kFlexSPIReadSampleClk_LoopbackFromDqsPad      = 1,
-    kFlexSPIReadSampleClk_LoopbackFromSckPad      = 2,
-    kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
-} flexspi_read_sample_clk_t;
-
-//!@brief Misc feature bit definitions
-enum
-{
-    kFlexSpiMiscOffset_DiffClkEnable            = 0, //!< Bit for Differential clock enable
-    kFlexSpiMiscOffset_Ck2Enable                = 1, //!< Bit for CK2 enable
-    kFlexSpiMiscOffset_ParallelEnable           = 2, //!< Bit for Parallel mode enable
-    kFlexSpiMiscOffset_WordAddressableEnable    = 3, //!< Bit for Word Addressable enable
-    kFlexSpiMiscOffset_SafeConfigFreqEnable     = 4, //!< Bit for Safe Configuration Frequency enable
-    kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
-    kFlexSpiMiscOffset_DdrModeEnable            = 6, //!< Bit for DDR clock confiuration indication.
-};
-
-//!@brief Flash Type Definition
-enum
-{
-    kFlexSpiDeviceType_SerialNOR    = 1,    //!< Flash devices are Serial NOR
-    kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
-    kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
-    kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
-    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
-};
-
-//!@brief Flash Pad Definitions
-enum
-{
-    kSerialFlash_1Pad  = 1,
-    kSerialFlash_2Pads = 2,
-    kSerialFlash_4Pads = 4,
-    kSerialFlash_8Pads = 8,
-};
-
-//!@brief FlexSPI LUT Sequence structure
-typedef struct _lut_sequence
-{
-    uint8_t seqNum; //!< Sequence Number, valid number: 1-16
-    uint8_t seqId;  //!< Sequence Index, valid number: 0-15
-    uint16_t reserved;
-} flexspi_lut_seq_t;
-
-//!@brief Flash Configuration Command Type
-enum
-{
-    kDeviceConfigCmdType_Generic,    //!< Generic command, for example: configure dummy cycles, drive strength, etc
-    kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
-    kDeviceConfigCmdType_Spi2Xpi,    //!< Switch from SPI to DPI/QPI/OPI mode
-    kDeviceConfigCmdType_Xpi2Spi,    //!< Switch from DPI/QPI/OPI to SPI mode
-    kDeviceConfigCmdType_Spi2NoCmd,  //!< Switch to 0-4-4/0-8-8 mode
-    kDeviceConfigCmdType_Reset,      //!< Reset device command
-};
-
-//!@brief FlexSPI Memory Configuration Block
-typedef struct _FlexSPIConfig
-{
-    uint32_t tag;               //!< [0x000-0x003] Tag, fixed value 0x42464346UL
-    uint32_t version;           //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
-    uint32_t reserved0;         //!< [0x008-0x00b] Reserved for future use
-    uint8_t readSampleClkSrc;   //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
-    uint8_t csHoldTime;         //!< [0x00d-0x00d] CS hold time, default value: 3
-    uint8_t csSetupTime;        //!< [0x00e-0x00e] CS setup time, default value: 3
-    uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
-    //! Serial NAND, need to refer to datasheet
-    uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
-    uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
-    //! Generic configuration, etc.
-    uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
-    //! DPI/QPI/OPI switch or reset command
-    flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
-    //! sequence number, [31:16] Reserved
-    uint32_t deviceModeArg;    //!< [0x018-0x01b] Argument/Parameter for device configuration
-    uint8_t configCmdEnable;   //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
-    uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
-    flexspi_lut_seq_t
-        configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
-    uint32_t reserved1;   //!< [0x02c-0x02f] Reserved for future use
-    uint32_t configCmdArgs[3];     //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
-    uint32_t reserved2;            //!< [0x03c-0x03f] Reserved for future use
-    uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
-    //! details
-    uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
-    uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
-    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
-    //! Chapter for more details
-    uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
-    //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
-    uint32_t reserved3[2];           //!< [0x048-0x04f] Reserved for future use
-    uint32_t sflashA1Size;           //!< [0x050-0x053] Size of Flash connected to A1
-    uint32_t sflashA2Size;           //!< [0x054-0x057] Size of Flash connected to A2
-    uint32_t sflashB1Size;           //!< [0x058-0x05b] Size of Flash connected to B1
-    uint32_t sflashB2Size;           //!< [0x05c-0x05f] Size of Flash connected to B2
-    uint32_t csPadSettingOverride;   //!< [0x060-0x063] CS pad setting override value
-    uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
-    uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
-    uint32_t dqsPadSettingOverride;  //!< [0x06c-0x06f] DQS pad setting override value
-    uint32_t timeoutInMs;            //!< [0x070-0x073] Timeout threshold for read status command
-    uint32_t commandInterval;        //!< [0x074-0x077] CS deselect interval between two commands
-    uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
-    uint16_t busyOffset;       //!< [0x07c-0x07d] Busy offset, valid value: 0-31
-    uint16_t busyBitPolarity;  //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
-    //! busy flag is 0 when flash device is busy
-    uint32_t lookupTable[64];           //!< [0x080-0x17f] Lookup table holds Flash command sequences
-    flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
-    uint32_t reserved4[4];              //!< [0x1b0-0x1bf] Reserved for future use
-} flexspi_mem_config_t;
-
-/*  */
-#define NOR_CMD_INDEX_READ CMD_INDEX_READ               //!< 0
-#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS   //!< 1
-#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
-#define NOR_CMD_INDEX_ERASESECTOR 3                     //!< 3
-#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE       //!< 4
-#define NOR_CMD_INDEX_CHIPERASE 5                       //!< 5
-#define NOR_CMD_INDEX_DUMMY 6                           //!< 6
-#define NOR_CMD_INDEX_ERASEBLOCK 7                      //!< 7
-
-#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0  READ LUT sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
-    CMD_LUT_SEQ_IDX_READSTATUS //!< 1  Read Status LUT sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
-    2 //!< 2  Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
-    CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3  Write Enable sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
-    4 //!< 4  Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5  Erase Sector sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8  //!< 8 Erase Block sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
-    CMD_LUT_SEQ_IDX_WRITE                //!< 9  Program sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
-    14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
-    15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
-
-/*
- *  Serial NOR configuration block
- */
-typedef struct _flexspi_nor_config
-{
-    flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
-    uint32_t pageSize;              //!< Page size of Serial NOR
-    uint32_t sectorSize;            //!< Sector size of Serial NOR
-    uint8_t ipcmdSerialClkFreq;     //!< Clock frequency for IP command
-    uint8_t isUniformBlockSize;     //!< Sector/Block size is the same
-    uint8_t reserved0[2];           //!< Reserved for future use
-    uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
-    uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
-    uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
-    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
-    uint32_t blockSize;             //!< Block size
-    uint32_t reserve2[11];          //!< Reserved for future use
-} flexspi_nor_config_t;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ */
diff --git a/tinyusb/hw/bsp/imxrt/boards/mimxrt1064_evk/board.h b/tinyusb/hw/bsp/imxrt/boards/mimxrt1064_evk/board.h
deleted file mode 100755
index 5f51e91a..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/mimxrt1064_evk/board.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-// required since iMX RT10xx SDK include this file for board size
-#define BOARD_FLASH_SIZE (0x400000U)
-
-// LED
-#define LED_PINMUX            IOMUXC_GPIO_AD_B0_09_GPIO1_IO09
-#define LED_PORT              GPIO1
-#define LED_PIN               9
-#define LED_STATE_ON          0
-
-// SW8 button
-#define BUTTON_PINMUX         IOMUXC_SNVS_WAKEUP_GPIO5_IO00
-#define BUTTON_PORT           GPIO5
-#define BUTTON_PIN            0
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_PORT             LPUART1
-#define UART_RX_PINMUX        IOMUXC_GPIO_AD_B0_13_LPUART1_RX
-#define UART_TX_PINMUX        IOMUXC_GPIO_AD_B0_12_LPUART1_TX
-
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk b/tinyusb/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk
deleted file mode 100755
index 586d74fe..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-CFLAGS += -DCPU_MIMXRT1064DVL6A
-MCU_VARIANT = MIMXRT1064
-
-# For flash-jlink target
-JLINK_DEVICE = MIMXRT1064xxx6A
-
-# For flash-pyocd target
-PYOCD_TARGET = mimxrt1064
-
-# flash using pyocd
-flash: flash-pyocd
diff --git a/tinyusb/hw/bsp/imxrt/boards/mimxrt1064_evk/evkmimxrt1064_flexspi_nor_config.c b/tinyusb/hw/bsp/imxrt/boards/mimxrt1064_evk/evkmimxrt1064_flexspi_nor_config.c
deleted file mode 100755
index bfb1c2d5..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/mimxrt1064_evk/evkmimxrt1064_flexspi_nor_config.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright 2018 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include "evkmimxrt1064_flexspi_nor_config.h"
-
-/* Component ID definition, used by tools. */
-#ifndef FSL_COMPONENT_ID
-#define FSL_COMPONENT_ID "platform.drivers.xip_board"
-#endif
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
-#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
-__attribute__((section(".boot_hdr.conf")))
-#elif defined(__ICCARM__)
-#pragma location = ".boot_hdr.conf"
-#endif
-
-const flexspi_nor_config_t qspiflash_config = {
-    .memConfig =
-        {
-            .tag              = FLEXSPI_CFG_BLK_TAG,
-            .version          = FLEXSPI_CFG_BLK_VERSION,
-            .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
-            .csHoldTime       = 3u,
-            .csSetupTime      = 3u,
-            // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
-            .sflashPadType = kSerialFlash_4Pads,
-            .serialClkFreq = kFlexSpiSerialClk_100MHz,
-            .sflashA1Size  = 8u * 1024u * 1024u,
-            .lookupTable =
-                {
-                    // Read LUTs
-                    FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
-                    FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
-                },
-        },
-    .pageSize           = 256u,
-    .sectorSize         = 4u * 1024u,
-    .blockSize          = 256u * 1024u,
-    .isUniformBlockSize = false,
-};
-#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/tinyusb/hw/bsp/imxrt/boards/mimxrt1064_evk/evkmimxrt1064_flexspi_nor_config.h b/tinyusb/hw/bsp/imxrt/boards/mimxrt1064_evk/evkmimxrt1064_flexspi_nor_config.h
deleted file mode 100755
index efdfe583..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/mimxrt1064_evk/evkmimxrt1064_flexspi_nor_config.h
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * Copyright 2018 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __EVKMIMXRT1064_FLEXSPI_NOR_CONFIG__
-#define __EVKMIMXRT1064_FLEXSPI_NOR_CONFIG__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "fsl_common.h"
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief XIP_BOARD driver version 2.0.0. */
-#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
-/* FLEXSPI memory config block related defintions */
-#define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
-#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
-#define FLEXSPI_CFG_BLK_SIZE (512)
-
-/* FLEXSPI Feature related definitions */
-#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
-
-/* Lookup table related defintions */
-#define CMD_INDEX_READ 0
-#define CMD_INDEX_READSTATUS 1
-#define CMD_INDEX_WRITEENABLE 2
-#define CMD_INDEX_WRITE 4
-
-#define CMD_LUT_SEQ_IDX_READ 0
-#define CMD_LUT_SEQ_IDX_READSTATUS 1
-#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
-#define CMD_LUT_SEQ_IDX_WRITE 9
-
-#define CMD_SDR 0x01
-#define CMD_DDR 0x21
-#define RADDR_SDR 0x02
-#define RADDR_DDR 0x22
-#define CADDR_SDR 0x03
-#define CADDR_DDR 0x23
-#define MODE1_SDR 0x04
-#define MODE1_DDR 0x24
-#define MODE2_SDR 0x05
-#define MODE2_DDR 0x25
-#define MODE4_SDR 0x06
-#define MODE4_DDR 0x26
-#define MODE8_SDR 0x07
-#define MODE8_DDR 0x27
-#define WRITE_SDR 0x08
-#define WRITE_DDR 0x28
-#define READ_SDR 0x09
-#define READ_DDR 0x29
-#define LEARN_SDR 0x0A
-#define LEARN_DDR 0x2A
-#define DATSZ_SDR 0x0B
-#define DATSZ_DDR 0x2B
-#define DUMMY_SDR 0x0C
-#define DUMMY_DDR 0x2C
-#define DUMMY_RWDS_SDR 0x0D
-#define DUMMY_RWDS_DDR 0x2D
-#define JMP_ON_CS 0x1F
-#define STOP 0
-
-#define FLEXSPI_1PAD 0
-#define FLEXSPI_2PAD 1
-#define FLEXSPI_4PAD 2
-#define FLEXSPI_8PAD 3
-
-#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)                                                              \
-    (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
-     FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
-
-//!@brief Definitions for FlexSPI Serial Clock Frequency
-typedef enum _FlexSpiSerialClockFreq
-{
-    kFlexSpiSerialClk_30MHz  = 1,
-    kFlexSpiSerialClk_50MHz  = 2,
-    kFlexSpiSerialClk_60MHz  = 3,
-    kFlexSpiSerialClk_75MHz  = 4,
-    kFlexSpiSerialClk_80MHz  = 5,
-    kFlexSpiSerialClk_100MHz = 6,
-    kFlexSpiSerialClk_120MHz = 7,
-    kFlexSpiSerialClk_133MHz = 8,
-    kFlexSpiSerialClk_166MHz = 9,
-} flexspi_serial_clk_freq_t;
-
-//!@brief FlexSPI clock configuration type
-enum
-{
-    kFlexSpiClk_SDR, //!< Clock configure for SDR mode
-    kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
-};
-
-//!@brief FlexSPI Read Sample Clock Source definition
-typedef enum _FlashReadSampleClkSource
-{
-    kFlexSPIReadSampleClk_LoopbackInternally      = 0,
-    kFlexSPIReadSampleClk_LoopbackFromDqsPad      = 1,
-    kFlexSPIReadSampleClk_LoopbackFromSckPad      = 2,
-    kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
-} flexspi_read_sample_clk_t;
-
-//!@brief Misc feature bit definitions
-enum
-{
-    kFlexSpiMiscOffset_DiffClkEnable            = 0, //!< Bit for Differential clock enable
-    kFlexSpiMiscOffset_Ck2Enable                = 1, //!< Bit for CK2 enable
-    kFlexSpiMiscOffset_ParallelEnable           = 2, //!< Bit for Parallel mode enable
-    kFlexSpiMiscOffset_WordAddressableEnable    = 3, //!< Bit for Word Addressable enable
-    kFlexSpiMiscOffset_SafeConfigFreqEnable     = 4, //!< Bit for Safe Configuration Frequency enable
-    kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
-    kFlexSpiMiscOffset_DdrModeEnable            = 6, //!< Bit for DDR clock confiuration indication.
-};
-
-//!@brief Flash Type Definition
-enum
-{
-    kFlexSpiDeviceType_SerialNOR    = 1,    //!< Flash devices are Serial NOR
-    kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
-    kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
-    kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
-    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
-};
-
-//!@brief Flash Pad Definitions
-enum
-{
-    kSerialFlash_1Pad  = 1,
-    kSerialFlash_2Pads = 2,
-    kSerialFlash_4Pads = 4,
-    kSerialFlash_8Pads = 8,
-};
-
-//!@brief FlexSPI LUT Sequence structure
-typedef struct _lut_sequence
-{
-    uint8_t seqNum; //!< Sequence Number, valid number: 1-16
-    uint8_t seqId;  //!< Sequence Index, valid number: 0-15
-    uint16_t reserved;
-} flexspi_lut_seq_t;
-
-//!@brief Flash Configuration Command Type
-enum
-{
-    kDeviceConfigCmdType_Generic,    //!< Generic command, for example: configure dummy cycles, drive strength, etc
-    kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
-    kDeviceConfigCmdType_Spi2Xpi,    //!< Switch from SPI to DPI/QPI/OPI mode
-    kDeviceConfigCmdType_Xpi2Spi,    //!< Switch from DPI/QPI/OPI to SPI mode
-    kDeviceConfigCmdType_Spi2NoCmd,  //!< Switch to 0-4-4/0-8-8 mode
-    kDeviceConfigCmdType_Reset,      //!< Reset device command
-};
-
-//!@brief FlexSPI Memory Configuration Block
-typedef struct _FlexSPIConfig
-{
-    uint32_t tag;               //!< [0x000-0x003] Tag, fixed value 0x42464346UL
-    uint32_t version;           //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
-    uint32_t reserved0;         //!< [0x008-0x00b] Reserved for future use
-    uint8_t readSampleClkSrc;   //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
-    uint8_t csHoldTime;         //!< [0x00d-0x00d] CS hold time, default value: 3
-    uint8_t csSetupTime;        //!< [0x00e-0x00e] CS setup time, default value: 3
-    uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
-    //! Serial NAND, need to refer to datasheet
-    uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
-    uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
-    //! Generic configuration, etc.
-    uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
-    //! DPI/QPI/OPI switch or reset command
-    flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
-    //! sequence number, [31:16] Reserved
-    uint32_t deviceModeArg;    //!< [0x018-0x01b] Argument/Parameter for device configuration
-    uint8_t configCmdEnable;   //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
-    uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
-    flexspi_lut_seq_t
-        configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
-    uint32_t reserved1;   //!< [0x02c-0x02f] Reserved for future use
-    uint32_t configCmdArgs[3];     //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
-    uint32_t reserved2;            //!< [0x03c-0x03f] Reserved for future use
-    uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
-    //! details
-    uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
-    uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
-    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
-    //! Chapter for more details
-    uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
-    //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
-    uint32_t reserved3[2];           //!< [0x048-0x04f] Reserved for future use
-    uint32_t sflashA1Size;           //!< [0x050-0x053] Size of Flash connected to A1
-    uint32_t sflashA2Size;           //!< [0x054-0x057] Size of Flash connected to A2
-    uint32_t sflashB1Size;           //!< [0x058-0x05b] Size of Flash connected to B1
-    uint32_t sflashB2Size;           //!< [0x05c-0x05f] Size of Flash connected to B2
-    uint32_t csPadSettingOverride;   //!< [0x060-0x063] CS pad setting override value
-    uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
-    uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
-    uint32_t dqsPadSettingOverride;  //!< [0x06c-0x06f] DQS pad setting override value
-    uint32_t timeoutInMs;            //!< [0x070-0x073] Timeout threshold for read status command
-    uint32_t commandInterval;        //!< [0x074-0x077] CS deselect interval between two commands
-    uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
-    uint16_t busyOffset;       //!< [0x07c-0x07d] Busy offset, valid value: 0-31
-    uint16_t busyBitPolarity;  //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
-    //! busy flag is 0 when flash device is busy
-    uint32_t lookupTable[64];           //!< [0x080-0x17f] Lookup table holds Flash command sequences
-    flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
-    uint32_t reserved4[4];              //!< [0x1b0-0x1bf] Reserved for future use
-} flexspi_mem_config_t;
-
-/*  */
-#define NOR_CMD_INDEX_READ CMD_INDEX_READ               //!< 0
-#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS   //!< 1
-#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
-#define NOR_CMD_INDEX_ERASESECTOR 3                     //!< 3
-#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE       //!< 4
-#define NOR_CMD_INDEX_CHIPERASE 5                       //!< 5
-#define NOR_CMD_INDEX_DUMMY 6                           //!< 6
-#define NOR_CMD_INDEX_ERASEBLOCK 7                      //!< 7
-
-#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0  READ LUT sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
-    CMD_LUT_SEQ_IDX_READSTATUS //!< 1  Read Status LUT sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
-    2 //!< 2  Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
-    CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3  Write Enable sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
-    4 //!< 4  Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5  Erase Sector sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8  //!< 8 Erase Block sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
-    CMD_LUT_SEQ_IDX_WRITE                //!< 9  Program sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
-    14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
-    15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
-
-/*
- *  Serial NOR configuration block
- */
-typedef struct _flexspi_nor_config
-{
-    flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
-    uint32_t pageSize;              //!< Page size of Serial NOR
-    uint32_t sectorSize;            //!< Sector size of Serial NOR
-    uint8_t ipcmdSerialClkFreq;     //!< Clock frequency for IP command
-    uint8_t isUniformBlockSize;     //!< Sector/Block size is the same
-    uint8_t reserved0[2];           //!< Reserved for future use
-    uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
-    uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
-    uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
-    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
-    uint32_t blockSize;             //!< Block size
-    uint32_t reserve2[11];          //!< Reserved for future use
-} flexspi_nor_config_t;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* __EVKMIMXRT1064_FLEXSPI_NOR_CONFIG__ */
diff --git a/tinyusb/hw/bsp/imxrt/boards/teensy_40/board.h b/tinyusb/hw/bsp/imxrt/boards/teensy_40/board.h
deleted file mode 100755
index b3cc0a8c..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/teensy_40/board.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-
-// required since iMX RT10xx SDK include this file for board size
-#define BOARD_FLASH_SIZE (2 * 1024 * 1024)
-
-// LED
-#define LED_PINMUX            IOMUXC_GPIO_B0_03_GPIO2_IO03 // D13
-#define LED_PORT              GPIO2
-#define LED_PIN               3
-#define LED_STATE_ON          0
-
-// no button
-#define BUTTON_PINMUX         IOMUXC_GPIO_B0_01_GPIO2_IO01 // D12
-#define BUTTON_PORT           GPIO2
-#define BUTTON_PIN            1
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_PORT             LPUART6
-#define UART_RX_PINMUX        IOMUXC_GPIO_AD_B0_03_LPUART6_RX  // D0
-#define UART_TX_PINMUX        IOMUXC_GPIO_AD_B0_02_LPUART6_TX  // D1
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/imxrt/boards/teensy_40/board.mk b/tinyusb/hw/bsp/imxrt/boards/teensy_40/board.mk
deleted file mode 100755
index 0ad5ea5c..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/teensy_40/board.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-CFLAGS += -DCPU_MIMXRT1062DVL6A
-MCU_VARIANT = MIMXRT1062
-
-# For flash-jlink target
-JLINK_DEVICE = MIMXRT1062xxx6A
-
-# flash by using teensy_loader_cli https://github.com/PaulStoffregen/teensy_loader_cli
-# Make sure it is in your PATH 
-flash: $(BUILD)/$(PROJECT).hex
-	teensy_loader_cli --mcu=imxrt1062 -v -w $<
diff --git a/tinyusb/hw/bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.c b/tinyusb/hw/bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.c
deleted file mode 100755
index 7929906e..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright 2018 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.h>
-
-/* Component ID definition, used by tools. */
-#ifndef FSL_COMPONENT_ID
-#define FSL_COMPONENT_ID "platform.drivers.xip_board"
-#endif
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
-#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
-__attribute__((section(".boot_hdr.conf")))
-#elif defined(__ICCARM__)
-#pragma location = ".boot_hdr.conf"
-#endif
-
-const flexspi_nor_config_t qspiflash_config = {
-    .memConfig =
-        {
-            .tag              = FLEXSPI_CFG_BLK_TAG,
-            .version          = FLEXSPI_CFG_BLK_VERSION,
-            .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
-            .csHoldTime       = 3u,
-            .csSetupTime      = 3u,
-            // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
-            .sflashPadType = kSerialFlash_4Pads,
-            .serialClkFreq = kFlexSpiSerialClk_100MHz,
-            .sflashA1Size  = 2u * 1024u * 1024u,
-            .lookupTable =
-                {
-                    // Read LUTs
-                    FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
-                    FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
-                },
-        },
-    .pageSize           = 256u,
-    .sectorSize         = 4u * 1024u,
-    .blockSize          = 256u * 1024u,
-    .isUniformBlockSize = false,
-};
-#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/tinyusb/hw/bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.h b/tinyusb/hw/bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.h
deleted file mode 100755
index 56068ec6..00000000
--- a/tinyusb/hw/bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.h
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * Copyright 2018 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __TEENSY40_FLEXSPI_NOR_CONFIG__
-#define __TEENSY40_FLEXSPI_NOR_CONFIG__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "fsl_common.h"
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief XIP_BOARD driver version 2.0.0. */
-#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
-/* FLEXSPI memory config block related defintions */
-#define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
-#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
-#define FLEXSPI_CFG_BLK_SIZE (512)
-
-/* FLEXSPI Feature related definitions */
-#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
-
-/* Lookup table related defintions */
-#define CMD_INDEX_READ 0
-#define CMD_INDEX_READSTATUS 1
-#define CMD_INDEX_WRITEENABLE 2
-#define CMD_INDEX_WRITE 4
-
-#define CMD_LUT_SEQ_IDX_READ 0
-#define CMD_LUT_SEQ_IDX_READSTATUS 1
-#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
-#define CMD_LUT_SEQ_IDX_WRITE 9
-
-#define CMD_SDR 0x01
-#define CMD_DDR 0x21
-#define RADDR_SDR 0x02
-#define RADDR_DDR 0x22
-#define CADDR_SDR 0x03
-#define CADDR_DDR 0x23
-#define MODE1_SDR 0x04
-#define MODE1_DDR 0x24
-#define MODE2_SDR 0x05
-#define MODE2_DDR 0x25
-#define MODE4_SDR 0x06
-#define MODE4_DDR 0x26
-#define MODE8_SDR 0x07
-#define MODE8_DDR 0x27
-#define WRITE_SDR 0x08
-#define WRITE_DDR 0x28
-#define READ_SDR 0x09
-#define READ_DDR 0x29
-#define LEARN_SDR 0x0A
-#define LEARN_DDR 0x2A
-#define DATSZ_SDR 0x0B
-#define DATSZ_DDR 0x2B
-#define DUMMY_SDR 0x0C
-#define DUMMY_DDR 0x2C
-#define DUMMY_RWDS_SDR 0x0D
-#define DUMMY_RWDS_DDR 0x2D
-#define JMP_ON_CS 0x1F
-#define STOP 0
-
-#define FLEXSPI_1PAD 0
-#define FLEXSPI_2PAD 1
-#define FLEXSPI_4PAD 2
-#define FLEXSPI_8PAD 3
-
-#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)                                                              \
-    (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
-     FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
-
-//!@brief Definitions for FlexSPI Serial Clock Frequency
-typedef enum _FlexSpiSerialClockFreq
-{
-    kFlexSpiSerialClk_30MHz  = 1,
-    kFlexSpiSerialClk_50MHz  = 2,
-    kFlexSpiSerialClk_60MHz  = 3,
-    kFlexSpiSerialClk_75MHz  = 4,
-    kFlexSpiSerialClk_80MHz  = 5,
-    kFlexSpiSerialClk_100MHz = 6,
-    kFlexSpiSerialClk_120MHz = 7,
-    kFlexSpiSerialClk_133MHz = 8,
-    kFlexSpiSerialClk_166MHz = 9,
-} flexspi_serial_clk_freq_t;
-
-//!@brief FlexSPI clock configuration type
-enum
-{
-    kFlexSpiClk_SDR, //!< Clock configure for SDR mode
-    kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
-};
-
-//!@brief FlexSPI Read Sample Clock Source definition
-typedef enum _FlashReadSampleClkSource
-{
-    kFlexSPIReadSampleClk_LoopbackInternally      = 0,
-    kFlexSPIReadSampleClk_LoopbackFromDqsPad      = 1,
-    kFlexSPIReadSampleClk_LoopbackFromSckPad      = 2,
-    kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
-} flexspi_read_sample_clk_t;
-
-//!@brief Misc feature bit definitions
-enum
-{
-    kFlexSpiMiscOffset_DiffClkEnable            = 0, //!< Bit for Differential clock enable
-    kFlexSpiMiscOffset_Ck2Enable                = 1, //!< Bit for CK2 enable
-    kFlexSpiMiscOffset_ParallelEnable           = 2, //!< Bit for Parallel mode enable
-    kFlexSpiMiscOffset_WordAddressableEnable    = 3, //!< Bit for Word Addressable enable
-    kFlexSpiMiscOffset_SafeConfigFreqEnable     = 4, //!< Bit for Safe Configuration Frequency enable
-    kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
-    kFlexSpiMiscOffset_DdrModeEnable            = 6, //!< Bit for DDR clock confiuration indication.
-};
-
-//!@brief Flash Type Definition
-enum
-{
-    kFlexSpiDeviceType_SerialNOR    = 1,    //!< Flash devices are Serial NOR
-    kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
-    kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
-    kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
-    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
-};
-
-//!@brief Flash Pad Definitions
-enum
-{
-    kSerialFlash_1Pad  = 1,
-    kSerialFlash_2Pads = 2,
-    kSerialFlash_4Pads = 4,
-    kSerialFlash_8Pads = 8,
-};
-
-//!@brief FlexSPI LUT Sequence structure
-typedef struct _lut_sequence
-{
-    uint8_t seqNum; //!< Sequence Number, valid number: 1-16
-    uint8_t seqId;  //!< Sequence Index, valid number: 0-15
-    uint16_t reserved;
-} flexspi_lut_seq_t;
-
-//!@brief Flash Configuration Command Type
-enum
-{
-    kDeviceConfigCmdType_Generic,    //!< Generic command, for example: configure dummy cycles, drive strength, etc
-    kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
-    kDeviceConfigCmdType_Spi2Xpi,    //!< Switch from SPI to DPI/QPI/OPI mode
-    kDeviceConfigCmdType_Xpi2Spi,    //!< Switch from DPI/QPI/OPI to SPI mode
-    kDeviceConfigCmdType_Spi2NoCmd,  //!< Switch to 0-4-4/0-8-8 mode
-    kDeviceConfigCmdType_Reset,      //!< Reset device command
-};
-
-//!@brief FlexSPI Memory Configuration Block
-typedef struct _FlexSPIConfig
-{
-    uint32_t tag;               //!< [0x000-0x003] Tag, fixed value 0x42464346UL
-    uint32_t version;           //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
-    uint32_t reserved0;         //!< [0x008-0x00b] Reserved for future use
-    uint8_t readSampleClkSrc;   //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
-    uint8_t csHoldTime;         //!< [0x00d-0x00d] CS hold time, default value: 3
-    uint8_t csSetupTime;        //!< [0x00e-0x00e] CS setup time, default value: 3
-    uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
-    //! Serial NAND, need to refer to datasheet
-    uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
-    uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
-    //! Generic configuration, etc.
-    uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
-    //! DPI/QPI/OPI switch or reset command
-    flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
-    //! sequence number, [31:16] Reserved
-    uint32_t deviceModeArg;    //!< [0x018-0x01b] Argument/Parameter for device configuration
-    uint8_t configCmdEnable;   //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
-    uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
-    flexspi_lut_seq_t
-        configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
-    uint32_t reserved1;   //!< [0x02c-0x02f] Reserved for future use
-    uint32_t configCmdArgs[3];     //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
-    uint32_t reserved2;            //!< [0x03c-0x03f] Reserved for future use
-    uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
-    //! details
-    uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
-    uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
-    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
-    //! Chapter for more details
-    uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
-    //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
-    uint32_t reserved3[2];           //!< [0x048-0x04f] Reserved for future use
-    uint32_t sflashA1Size;           //!< [0x050-0x053] Size of Flash connected to A1
-    uint32_t sflashA2Size;           //!< [0x054-0x057] Size of Flash connected to A2
-    uint32_t sflashB1Size;           //!< [0x058-0x05b] Size of Flash connected to B1
-    uint32_t sflashB2Size;           //!< [0x05c-0x05f] Size of Flash connected to B2
-    uint32_t csPadSettingOverride;   //!< [0x060-0x063] CS pad setting override value
-    uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
-    uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
-    uint32_t dqsPadSettingOverride;  //!< [0x06c-0x06f] DQS pad setting override value
-    uint32_t timeoutInMs;            //!< [0x070-0x073] Timeout threshold for read status command
-    uint32_t commandInterval;        //!< [0x074-0x077] CS deselect interval between two commands
-    uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
-    uint16_t busyOffset;       //!< [0x07c-0x07d] Busy offset, valid value: 0-31
-    uint16_t busyBitPolarity;  //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
-    //! busy flag is 0 when flash device is busy
-    uint32_t lookupTable[64];           //!< [0x080-0x17f] Lookup table holds Flash command sequences
-    flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
-    uint32_t reserved4[4];              //!< [0x1b0-0x1bf] Reserved for future use
-} flexspi_mem_config_t;
-
-/*  */
-#define NOR_CMD_INDEX_READ CMD_INDEX_READ               //!< 0
-#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS   //!< 1
-#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
-#define NOR_CMD_INDEX_ERASESECTOR 3                     //!< 3
-#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE       //!< 4
-#define NOR_CMD_INDEX_CHIPERASE 5                       //!< 5
-#define NOR_CMD_INDEX_DUMMY 6                           //!< 6
-#define NOR_CMD_INDEX_ERASEBLOCK 7                      //!< 7
-
-#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0  READ LUT sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
-    CMD_LUT_SEQ_IDX_READSTATUS //!< 1  Read Status LUT sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
-    2 //!< 2  Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
-    CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3  Write Enable sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
-    4 //!< 4  Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5  Erase Sector sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8  //!< 8 Erase Block sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
-    CMD_LUT_SEQ_IDX_WRITE                //!< 9  Program sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
-    14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
-#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
-    15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
-
-/*
- *  Serial NOR configuration block
- */
-typedef struct _flexspi_nor_config
-{
-    flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
-    uint32_t pageSize;              //!< Page size of Serial NOR
-    uint32_t sectorSize;            //!< Sector size of Serial NOR
-    uint8_t ipcmdSerialClkFreq;     //!< Clock frequency for IP command
-    uint8_t isUniformBlockSize;     //!< Sector/Block size is the same
-    uint8_t reserved0[2];           //!< Reserved for future use
-    uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
-    uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
-    uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
-    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
-    uint32_t blockSize;             //!< Block size
-    uint32_t reserve2[11];          //!< Reserved for future use
-} flexspi_nor_config_t;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ */
diff --git a/tinyusb/hw/bsp/imxrt/family.c b/tinyusb/hw/bsp/imxrt/family.c
deleted file mode 100755
index 77a224a5..00000000
--- a/tinyusb/hw/bsp/imxrt/family.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2018, hathach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "bsp/board.h"
-#include "board.h"
-#include "fsl_device_registers.h"
-#include "fsl_gpio.h"
-#include "fsl_iomuxc.h"
-#include "fsl_clock.h"
-#include "fsl_lpuart.h"
-
-#include "clock_config.h"
-
-// needed by fsl_flexspi_nor_boot
-const uint8_t dcd_data[] = { 0x00 };
-
-void board_init(void)
-{
-  // Init clock
-  BOARD_BootClockRUN();
-  SystemCoreClockUpdate();
-
-  // Enable IOCON clock
-  CLOCK_EnableClock(kCLOCK_Iomuxc);
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-//  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  // LED
-  IOMUXC_SetPinMux( LED_PINMUX, 0U);
-  IOMUXC_SetPinConfig( LED_PINMUX, 0x10B0U);
-
-  gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0, kGPIO_NoIntmode };
-  GPIO_PinInit(LED_PORT, LED_PIN, &led_config);
-  board_led_write(true);
-
-  // Button
-  IOMUXC_SetPinMux( BUTTON_PINMUX, 0U);
-  IOMUXC_SetPinConfig(BUTTON_PINMUX, 0x01B0A0U);
-  gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0, kGPIO_IntRisingEdge, };
-  GPIO_PinInit(BUTTON_PORT, BUTTON_PIN, &button_config);
-
-  // UART
-  IOMUXC_SetPinMux( UART_TX_PINMUX, 0U);
-  IOMUXC_SetPinMux( UART_RX_PINMUX, 0U);
-  IOMUXC_SetPinConfig( UART_TX_PINMUX, 0x10B0u);
-  IOMUXC_SetPinConfig( UART_RX_PINMUX, 0x10B0u);
-
-  lpuart_config_t uart_config;
-  LPUART_GetDefaultConfig(&uart_config);
-  uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
-  uart_config.enableTx = true;
-  uart_config.enableRx = true;
-
-  uint32_t freq;
-  if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
-  {
-    freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
-  }
-  else
-  {
-    freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
-  }
-
-  LPUART_Init(UART_PORT, &uart_config, freq);
-
-  //------------- USB0 -------------//
-
-  // Clock
-  CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
-  CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U);
-
-  // USB1
-//  CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
-//  CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, 480000000U);
-
-  USBPHY_Type* usb_phy;
-
-  // RT105x RT106x have dual USB controller. TODO support USB2
-#ifdef USBPHY1
-  usb_phy = USBPHY1;
-#else
-  usb_phy = USBPHY;
-#endif
-
-  // Enable PHY support for Low speed device + LS via FS Hub
-  usb_phy->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
-
-  // Enable all power for normal operation
-  usb_phy->PWD = 0;
-
-  // TX Timing
-  uint32_t phytx = usb_phy->TX;
-  phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
-  phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
-  usb_phy->TX = phytx;
-}
-
-//--------------------------------------------------------------------+
-// USB Interrupt Handler
-//--------------------------------------------------------------------+
-void USB_OTG1_IRQHandler(void)
-{
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
-    tuh_int_handler(0);
-  #endif
-
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-    tud_int_handler(0);
-  #endif
-}
-
-void USB_OTG2_IRQHandler(void)
-{
-  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
-    tuh_int_handler(1);
-  #endif
-
-  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE
-    tud_int_handler(1);
-  #endif
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  GPIO_PinWrite(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  // active low
-  return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  LPUART_ReadBlocking(UART_PORT, buf, len);
-  return len;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  LPUART_WriteBlocking(UART_PORT, (uint8_t*)buf, len);
-  return len;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/tinyusb/hw/bsp/imxrt/family.mk b/tinyusb/hw/bsp/imxrt/family.mk
deleted file mode 100755
index a919d369..00000000
--- a/tinyusb/hw/bsp/imxrt/family.mk
+++ /dev/null
@@ -1,54 +0,0 @@
-UF2_FAMILY_ID = 0x4fb2d5bd
-SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += $(SDK_DIR)
-
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-CFLAGS += \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m7 \
-  -mfloat-abi=hard \
-  -mfpu=fpv5-d16 \
-  -D__ARMVFP__=0 -D__ARMFPV5__=0\
-  -DXIP_EXTERNAL_FLASH=1 \
-  -DXIP_BOOT_HEADER_ENABLE=1 \
-  -DCFG_TUSB_MCU=OPT_MCU_MIMXRT10XX
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=implicit-fallthrough=
-
-MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT)
-
-# All source paths should be relative to the top level.
-LD_FILE = $(MCU_DIR)/gcc/$(MCU_VARIANT)xxxxx_flexspi_nor.ld
-
-# TODO for net_lwip_webserver exmaple, but may not needed !! 
-LDFLAGS += \
-	-Wl,--defsym,__stack_size__=0x800 \
-
-SRC_C += \
-	src/portable/nxp/transdimension/dcd_transdimension.c \
-	$(MCU_DIR)/system_$(MCU_VARIANT).c \
-	$(MCU_DIR)/xip/fsl_flexspi_nor_boot.c \
-	$(MCU_DIR)/project_template/clock_config.c \
-	$(MCU_DIR)/drivers/fsl_clock.c \
-	$(SDK_DIR)/drivers/common/fsl_common.c \
-	$(SDK_DIR)/drivers/igpio/fsl_gpio.c \
-	$(SDK_DIR)/drivers/lpuart/fsl_lpuart.c
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(MCU_DIR)/../../CMSIS/Include \
-	$(TOP)/$(MCU_DIR) \
-	$(TOP)/$(MCU_DIR)/project_template \
-	$(TOP)/$(MCU_DIR)/drivers \
-	$(TOP)/$(SDK_DIR)/drivers/common \
-	$(TOP)/$(SDK_DIR)/drivers/igpio \
-	$(TOP)/$(SDK_DIR)/drivers/lpuart
-
-SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_VARIANT).S
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM7/r0p1
-
diff --git a/tinyusb/hw/bsp/lpc15/boards/lpcxpresso1549/board.h b/tinyusb/hw/bsp/lpc15/boards/lpcxpresso1549/board.h
deleted file mode 100755
index 5ed5b75b..00000000
--- a/tinyusb/hw/bsp/lpc15/boards/lpcxpresso1549/board.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// XTAL
-#define XTAL_OscRateIn      12000000
-#define XTAL_RTCOscRateIn   32768
-
-// LED
-#define LED_PORT            0
-#define LED_PIN             25
-
-// Wake Switch
-#define BUTTON_PORT         0
-#define BUTTON_PIN          17
-
-#define UART_PORT           LPC_USART0
-
-static inline void board_lpc15_pinmux_swm_init(void)
-{
-  // Pinmux
-  const PINMUX_GRP_T pinmuxing[] =
-  {
-    {0, 25, (IOCON_MODE_INACT    | IOCON_DIGMODE_EN)}, // PIO0_25-BREAK_CTRL-RED (low enable)
-    {0, 13, (IOCON_MODE_INACT    | IOCON_DIGMODE_EN)}, // PIO0_13-ISP_RX
-    {0, 18, (IOCON_MODE_INACT    | IOCON_DIGMODE_EN)}, // PIO0_18-ISP_TX
-    {1, 11, (IOCON_MODE_PULLDOWN | IOCON_DIGMODE_EN)}, // PIO1_11-ISP_1 (VBUS)
-  };
-
-  // Pin Mux
-  Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
-
-  // SWIM
-  Chip_SWM_MovablePortPinAssign(SWM_USB_VBUS_I , 1, 11);
-  Chip_SWM_MovablePortPinAssign(SWM_UART0_RXD_I, 0, 13);
-  Chip_SWM_MovablePortPinAssign(SWM_UART0_TXD_O, 0, 18);
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif
diff --git a/tinyusb/hw/bsp/lpc15/boards/lpcxpresso1549/board.mk b/tinyusb/hw/bsp/lpc15/boards/lpcxpresso1549/board.mk
deleted file mode 100755
index a3e04cfa..00000000
--- a/tinyusb/hw/bsp/lpc15/boards/lpcxpresso1549/board.mk
+++ /dev/null
@@ -1,6 +0,0 @@
-LD_FILE = $(BOARD_PATH)/lpc1549.ld
-
-JLINK_DEVICE = LPC1549
-
-# flash using pyocd
-flash: flash-jlink
diff --git a/tinyusb/hw/bsp/lpc15/boards/lpcxpresso1549/lpc1549.ld b/tinyusb/hw/bsp/lpc15/boards/lpcxpresso1549/lpc1549.ld
deleted file mode 100755
index 6dd12ade..00000000
--- a/tinyusb/hw/bsp/lpc15/boards/lpcxpresso1549/lpc1549.ld
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- * GENERATED FILE - DO NOT EDIT
- * Copyright (c) 2008-2013 Code Red Technologies Ltd,
- * Copyright 2015, 2018-2019 NXP
- * (c) NXP Semiconductors 2013-2019
- * Generated linker script file for LPC1549
- * Created from linkscript.ldt by FMCreateLinkLibraries
- * Using Freemarker v2.3.23
- * MCUXpresso IDE v11.0.0 [Build 2516] [2019-06-05] on Oct 3, 2019 2:55:18 PM
- */
-
-
-MEMORY
-{
-  /* Define each memory region */
-  MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes (alias Flash) */  
-  Ram0_16 (rwx) : ORIGIN = 0x2000000, LENGTH = 0x4000 /* 16K bytes (alias RAM) */  
-  Ram1_16 (rwx) : ORIGIN = 0x2004000, LENGTH = 0x4000 /* 16K bytes (alias RAM2) */  
-  Ram2_4 (rwx) : ORIGIN = 0x2008000, LENGTH = 0x1000 /* 4K bytes (alias RAM3) */  
-}
-
-  /* Define a symbol for the top of each memory region */
-  __base_MFlash256 = 0x0  ; /* MFlash256 */  
-  __base_Flash = 0x0 ; /* Flash */  
-  __top_MFlash256 = 0x0 + 0x40000 ; /* 256K bytes */  
-  __top_Flash = 0x0 + 0x40000 ; /* 256K bytes */  
-  __base_Ram0_16 = 0x2000000  ; /* Ram0_16 */  
-  __base_RAM = 0x2000000 ; /* RAM */  
-  __top_Ram0_16 = 0x2000000 + 0x4000 ; /* 16K bytes */  
-  __top_RAM = 0x2000000 + 0x4000 ; /* 16K bytes */  
-  __base_Ram1_16 = 0x2004000  ; /* Ram1_16 */  
-  __base_RAM2 = 0x2004000 ; /* RAM2 */  
-  __top_Ram1_16 = 0x2004000 + 0x4000 ; /* 16K bytes */  
-  __top_RAM2 = 0x2004000 + 0x4000 ; /* 16K bytes */  
-  __base_Ram2_4 = 0x2008000  ; /* Ram2_4 */  
-  __base_RAM3 = 0x2008000 ; /* RAM3 */  
-  __top_Ram2_4 = 0x2008000 + 0x1000 ; /* 4K bytes */  
-  __top_RAM3 = 0x2008000 + 0x1000 ; /* 4K bytes */  
-
-ENTRY(ResetISR)
-
-SECTIONS
-{
-     /* MAIN TEXT SECTION */
-    .text : ALIGN(4)
-    {
-        FILL(0xff)
-        __vectors_start__ = ABSOLUTE(.) ;
-        KEEP(*(.isr_vector))
-        /* Global Section Table */
-        . = ALIGN(4) ;
-        __section_table_start = .;
-        __data_section_table = .;
-        LONG(LOADADDR(.data));
-        LONG(    ADDR(.data));
-        LONG(  SIZEOF(.data));
-        LONG(LOADADDR(.data_RAM2));
-        LONG(    ADDR(.data_RAM2));
-        LONG(  SIZEOF(.data_RAM2));
-        LONG(LOADADDR(.data_RAM3));
-        LONG(    ADDR(.data_RAM3));
-        LONG(  SIZEOF(.data_RAM3));
-        __data_section_table_end = .;
-        __bss_section_table = .;
-        LONG(    ADDR(.bss));
-        LONG(  SIZEOF(.bss));
-        LONG(    ADDR(.bss_RAM2));
-        LONG(  SIZEOF(.bss_RAM2));
-        LONG(    ADDR(.bss_RAM3));
-        LONG(  SIZEOF(.bss_RAM3));
-        __bss_section_table_end = .;
-        __section_table_end = . ;
-        /* End of Global Section Table */
-
-        *(.after_vectors*)
-
-    } > MFlash256
-
-    .text : ALIGN(4)
-    {
-       *(.text*)
-       *(.rodata .rodata.* .constdata .constdata.*)
-       . = ALIGN(4);
-    } > MFlash256
-    /*
-     * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
-     */
-    .ARM.extab : ALIGN(4) 
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > MFlash256
-
-    __exidx_start = .;
-
-    .ARM.exidx : ALIGN(4)
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > MFlash256
-    __exidx_end = .;
- 
-    _etext = .;
-        
-    /* DATA section for Ram1_16 */
-
-    .data_RAM2 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM2 = .) ;
-        *(.ramfunc.$RAM2)
-        *(.ramfunc.$Ram1_16)
-        *(.data.$RAM2)
-        *(.data.$Ram1_16)
-        *(.data.$RAM2.*)
-        *(.data.$Ram1_16.*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM2 = .) ;
-     } > Ram1_16 AT>MFlash256
-    /* DATA section for Ram2_4 */
-
-    .data_RAM3 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM3 = .) ;
-        *(.ramfunc.$RAM3)
-        *(.ramfunc.$Ram2_4)
-        *(.data.$RAM3)
-        *(.data.$Ram2_4)
-        *(.data.$RAM3.*)
-        *(.data.$Ram2_4.*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM3 = .) ;
-     } > Ram2_4 AT>MFlash256
-    /* MAIN DATA SECTION */
-    .uninit_RESERVED (NOLOAD) :
-    {
-        . = ALIGN(4) ;
-        KEEP(*(.bss.$RESERVED*))
-       . = ALIGN(4) ;
-        _end_uninit_RESERVED = .;
-    } > Ram0_16
-
-    /* Main DATA section (Ram0_16) */
-    .data : ALIGN(4)
-    {
-       FILL(0xff)
-       _data = . ;
-       *(vtable)
-       *(.ramfunc*)
-       *(.data*)
-       . = ALIGN(4) ;
-       _edata = . ;
-    } > Ram0_16 AT>MFlash256
-
-    /* BSS section for Ram1_16 */
-    .bss_RAM2 :
-    {
-       . = ALIGN(4) ;
-       PROVIDE(__start_bss_RAM2 = .) ;
-       *(.bss.$RAM2)
-       *(.bss.$Ram1_16)
-       *(.bss.$RAM2.*)
-       *(.bss.$Ram1_16.*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM2 = .) ;
-    } > Ram1_16
-
-    /* BSS section for Ram2_4 */
-    .bss_RAM3 :
-    {
-       . = ALIGN(4) ;
-       PROVIDE(__start_bss_RAM3 = .) ;
-       *(.bss.$RAM3)
-       *(.bss.$Ram2_4)
-       *(.bss.$RAM3.*)
-       *(.bss.$Ram2_4.*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM3 = .) ;
-    } > Ram2_4
-
-    /* MAIN BSS SECTION */
-    .bss :
-    {
-        . = ALIGN(4) ;
-        _bss = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4) ;
-        _ebss = .;
-        PROVIDE(end = .);
-    } > Ram0_16
-
-    /* NOINIT section for Ram1_16 */
-    .noinit_RAM2 (NOLOAD) :
-    {
-       . = ALIGN(4) ;
-       *(.noinit.$RAM2)
-       *(.noinit.$Ram1_16)
-       *(.noinit.$RAM2.*)
-       *(.noinit.$Ram1_16.*)
-       . = ALIGN(4) ;
-    } > Ram1_16
-
-    /* NOINIT section for Ram2_4 */
-    .noinit_RAM3 (NOLOAD) :
-    {
-       . = ALIGN(4) ;
-       *(.noinit.$RAM3)
-       *(.noinit.$Ram2_4)
-       *(.noinit.$RAM3.*)
-       *(.noinit.$Ram2_4.*)
-       . = ALIGN(4) ;
-    } > Ram2_4
-
-    /* DEFAULT NOINIT SECTION */
-    .noinit (NOLOAD):
-    {
-         . = ALIGN(4) ;
-        _noinit = .;
-        *(.noinit*)
-         . = ALIGN(4) ;
-        _end_noinit = .;
-    } > Ram0_16
-    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
-    PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_Ram0_16 - 0);
-
-    /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (NMI_Handler + 1) 
-                                         + (HardFault_Handler + 1) 
-                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
-                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
-                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
-                                         ) );
-
-    /* Provide basic symbols giving location and size of main text
-     * block, including initial values of RW data sections. Note that
-     * these will need extending to give a complete picture with
-     * complex images (e.g multiple Flash banks).
-     */
-    _image_start = LOADADDR(.text);
-    _image_end = LOADADDR(.data) + SIZEOF(.data);
-    _image_size = _image_end - _image_start;
-}
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/lpc15/family.c b/tinyusb/hw/bsp/lpc15/family.c
deleted file mode 100755
index 7f5984a3..00000000
--- a/tinyusb/hw/bsp/lpc15/family.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "chip.h"
-#include "bsp/board.h"
-#include "board.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-/* System oscillator rate and RTC oscillator rate */
-const uint32_t OscRateIn = XTAL_OscRateIn;
-const uint32_t RTCOscRateIn = XTAL_RTCOscRateIn;
-
-// Invoked by startup code
-void SystemInit(void)
-{
-  Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SRAM1);
-  Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SRAM2);
-  Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
-  Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM);
-  Chip_SYSCTL_PeriphReset(RESET_IOCON);
-
-  board_lpc15_pinmux_swm_init();
-
-  Chip_SetupXtalClocking();
-}
-
-void board_init(void)
-{
-  SystemCoreClockUpdate();
-
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-
-#if CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  Chip_GPIO_Init(LPC_GPIO);
-
-  // LED
-  Chip_GPIO_SetPinDIROutput(LPC_GPIO, LED_PORT, LED_PIN);
-
-  // Button
-  Chip_GPIO_SetPinDIRInput(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
-
-	// UART
-	Chip_Clock_SetUARTBaseClockRate(Chip_Clock_GetMainClockRate(), false);
-	Chip_UART_Init(UART_PORT);
-	Chip_UART_ConfigData(UART_PORT, UART_CFG_DATALEN_8 | UART_CFG_PARITY_NONE | UART_CFG_STOPLEN_1);
-	Chip_UART_SetBaud(UART_PORT, CFG_BOARD_UART_BAUDRATE);
-	Chip_UART_Enable(UART_PORT);
-	Chip_UART_TXEnable(UART_PORT);
-
-  // USB: Setup PLL clock, and power
-  Chip_USB_Init();
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state);
-}
-
-uint32_t board_button_read(void)
-{
-  // active low
-  return Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN) ? 0 : 1;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  return Chip_UART_SendBlocking(UART_PORT, buf, len);
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/tinyusb/hw/bsp/lpc15/family.mk b/tinyusb/hw/bsp/lpc15/family.mk
deleted file mode 100755
index e80a3bc5..00000000
--- a/tinyusb/hw/bsp/lpc15/family.mk
+++ /dev/null
@@ -1,39 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m3 \
-  -nostdlib \
-  -DCORE_M3 \
-  -D__USE_LPCOPEN \
-  -DCFG_EXAMPLE_MSC_READONLY \
-  -DCFG_TUSB_MCU=OPT_MCU_LPC15XX \
-  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' 
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=unused-variable
-
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc15xx/lpc_chip_15xx
-
-SRC_C += \
-	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
-	$(MCU_DIR)/../gcc/cr_startup_lpc15xx.c \
-	$(MCU_DIR)/src/chip_15xx.c \
-	$(MCU_DIR)/src/clock_15xx.c \
-	$(MCU_DIR)/src/gpio_15xx.c \
-	$(MCU_DIR)/src/iocon_15xx.c \
-	$(MCU_DIR)/src/swm_15xx.c \
-	$(MCU_DIR)/src/sysctl_15xx.c \
-	$(MCU_DIR)/src/uart_15xx.c \
-	$(MCU_DIR)/src/sysinit_15xx.c
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
diff --git a/tinyusb/hw/bsp/lpc18/boards/lpcxpresso18s37/board.h b/tinyusb/hw/bsp/lpc18/boards/lpcxpresso18s37/board.h
deleted file mode 100755
index b3a7bc44..00000000
--- a/tinyusb/hw/bsp/lpc18/boards/lpcxpresso18s37/board.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-// Note: For USB Host demo, install JP4
-// WARNING: don't install JP4 when running as device
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED Red
-#define LED_PORT      3
-#define LED_PIN       7
-
-// ISP Button
-#define BUTTON_PORT   0
-#define BUTTON_PIN    7
-
-#define UART_DEV      LPC_USART0
-
-static inline void board_lpc18_pinmux(void)
-{
-  const PINMUX_GRP_T pinmuxing[] =
-  {
-    // LEDs
-    { 0x6, 9 , SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0 },
-    { 0x6, 11, SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0 },
-
-    // Button
-    { 0x2, 7, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0 },
-
-    // UART
-    { 0x06, 4, SCU_MODE_PULLDOWN | SCU_MODE_FUNC2 },
-    { 0x02, 1, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC1 },
-
-    // USB0
-    //{ 0x6, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC1 },		                // P6_3 USB0_PWR_EN, USB0 VBus function
-
-    //{ 0x9, 5, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC2 },			              // P9_5 USB1_VBUS_EN, USB1 VBus function
-    //{ 0x2, 5, SCU_MODE_INACT  | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2 }, // P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION
-    {0x2, 5, SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC4 },
-  };
-
-  Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif
diff --git a/tinyusb/hw/bsp/lpc18/boards/lpcxpresso18s37/board.mk b/tinyusb/hw/bsp/lpc18/boards/lpcxpresso18s37/board.mk
deleted file mode 100755
index 29b12913..00000000
--- a/tinyusb/hw/bsp/lpc18/boards/lpcxpresso18s37/board.mk
+++ /dev/null
@@ -1,6 +0,0 @@
-LD_FILE = $(BOARD_PATH)/lpc1837.ld
-
-# For flash-jlink target
-JLINK_DEVICE = LPC18S37
-
-flash: flash-jlink
diff --git a/tinyusb/hw/bsp/lpc18/boards/lpcxpresso18s37/lpc1837.ld b/tinyusb/hw/bsp/lpc18/boards/lpcxpresso18s37/lpc1837.ld
deleted file mode 100755
index 51fd1539..00000000
--- a/tinyusb/hw/bsp/lpc18/boards/lpcxpresso18s37/lpc1837.ld
+++ /dev/null
@@ -1,404 +0,0 @@
-/*
- * GENERATED FILE - DO NOT EDIT
- * Copyright (c) 2008-2013 Code Red Technologies Ltd,
- * Copyright 2015, 2018-2019 NXP
- * (c) NXP Semiconductors 2013-2021
- * Generated linker script file for LPC1837
- * Created from linkscript.ldt by FMCreateLinkLibraries
- * Using Freemarker v2.3.23
- * MCUXpresso IDE v11.2.0 [Build 4120] [2020-07-09] on Mar 3, 2021 4:22:49 PM
- */
-
-MEMORY
-{
-  /* Define each memory region */
-  MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */  
-  MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */  
-  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */  
-  RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */  
-  RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */  
-  RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */  
-  RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */  
-}
-
-/* Define a symbol for the top of each memory region */
-__base_MFlashA512 = 0x1a000000  ; /* MFlashA512 */  
-__base_Flash = 0x1a000000 ; /* Flash */  
-__top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */  
-__top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */  
-__base_MFlashB512 = 0x1b000000  ; /* MFlashB512 */  
-__base_Flash2 = 0x1b000000 ; /* Flash2 */  
-__top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */  
-__top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */  
-__base_RamLoc32 = 0x10000000  ; /* RamLoc32 */  
-__base_RAM = 0x10000000 ; /* RAM */  
-__top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */  
-__top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */  
-__base_RamLoc40 = 0x10080000  ; /* RamLoc40 */  
-__base_RAM2 = 0x10080000 ; /* RAM2 */  
-__top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */  
-__top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */  
-__base_RamAHB32 = 0x20000000  ; /* RamAHB32 */  
-__base_RAM3 = 0x20000000 ; /* RAM3 */  
-__top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-__top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-__base_RamAHB16 = 0x20008000  ; /* RamAHB16 */  
-__base_RAM4 = 0x20008000 ; /* RAM4 */  
-__top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */  
-__top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */  
-__base_RamAHB_ETB16 = 0x2000c000  ; /* RamAHB_ETB16 */  
-__base_RAM5 = 0x2000c000 ; /* RAM5 */  
-__top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */  
-__top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */
-
-ENTRY(ResetISR)
-
-SECTIONS
-{
-     .text_Flash2 : ALIGN(4)
-    {
-       FILL(0xff)
-        *(.text_Flash2) /* for compatibility with previous releases */
-        *(.text_MFlashB512) /* for compatibility with previous releases */
-        *(.text.$Flash2)
-        *(.text.$MFlashB512)
-        *(.text_Flash2.*) /* for compatibility with previous releases */
-        *(.text_MFlashB512.*) /* for compatibility with previous releases */
-        *(.text.$Flash2.*)
-        *(.text.$MFlashB512.*)
-        *(.rodata.$Flash2)
-        *(.rodata.$MFlashB512)
-        *(.rodata.$Flash2.*)
-        *(.rodata.$MFlashB512.*)            } > MFlashB512
-
-    /* MAIN TEXT SECTION */
-    .text : ALIGN(4)
-    {
-        FILL(0xff)
-        __vectors_start__ = ABSOLUTE(.) ;
-        KEEP(*(.isr_vector))
-        /* Global Section Table */
-        . = ALIGN(4) ;
-        __section_table_start = .;
-        __data_section_table = .;
-        LONG(LOADADDR(.data));
-        LONG(    ADDR(.data));
-        LONG(  SIZEOF(.data));
-        LONG(LOADADDR(.data_RAM2));
-        LONG(    ADDR(.data_RAM2));
-        LONG(  SIZEOF(.data_RAM2));
-        LONG(LOADADDR(.data_RAM3));
-        LONG(    ADDR(.data_RAM3));
-        LONG(  SIZEOF(.data_RAM3));
-        LONG(LOADADDR(.data_RAM4));
-        LONG(    ADDR(.data_RAM4));
-        LONG(  SIZEOF(.data_RAM4));
-        LONG(LOADADDR(.data_RAM5));
-        LONG(    ADDR(.data_RAM5));
-        LONG(  SIZEOF(.data_RAM5));
-        __data_section_table_end = .;
-        __bss_section_table = .;
-        LONG(    ADDR(.bss));
-        LONG(  SIZEOF(.bss));
-        LONG(    ADDR(.bss_RAM2));
-        LONG(  SIZEOF(.bss_RAM2));
-        LONG(    ADDR(.bss_RAM3));
-        LONG(  SIZEOF(.bss_RAM3));
-        LONG(    ADDR(.bss_RAM4));
-        LONG(  SIZEOF(.bss_RAM4));
-        LONG(    ADDR(.bss_RAM5));
-        LONG(  SIZEOF(.bss_RAM5));
-        __bss_section_table_end = .;
-        __section_table_end = . ;
-        /* End of Global Section Table */
-
-        *(.after_vectors*)
-
-    } > MFlashA512
-
-    .text : ALIGN(4)
-    {
-       *(.text*)
-       *(.rodata .rodata.* .constdata .constdata.*)
-       . = ALIGN(4);
-    } > MFlashA512
-    /*
-     * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this.
-     */
-    .ARM.extab : ALIGN(4)
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > MFlashA512
-
-    .ARM.exidx : ALIGN(4)
-    {
-        __exidx_start = .;
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        __exidx_end = .;
-    } > MFlashA512
- 
-    _etext = .;
-        
-    /* DATA section for RamLoc40 */
-
-    .data_RAM2 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM2 = .) ;
-        PROVIDE(__start_data_RamLoc40 = .) ;
-        *(.ramfunc.$RAM2)
-        *(.ramfunc.$RamLoc40)
-        *(.data.$RAM2)
-        *(.data.$RamLoc40)
-        *(.data.$RAM2.*)
-        *(.data.$RamLoc40.*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM2 = .) ;
-        PROVIDE(__end_data_RamLoc40 = .) ;
-     } > RamLoc40 AT>MFlashA512
-
-    /* DATA section for RamAHB32 */
-
-    .data_RAM3 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM3 = .) ;
-        PROVIDE(__start_data_RamAHB32 = .) ;
-        *(.ramfunc.$RAM3)
-        *(.ramfunc.$RamAHB32)
-        *(.data.$RAM3)
-        *(.data.$RamAHB32)
-        *(.data.$RAM3.*)
-        *(.data.$RamAHB32.*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM3 = .) ;
-        PROVIDE(__end_data_RamAHB32 = .) ;
-     } > RamAHB32 AT>MFlashA512
-
-    /* DATA section for RamAHB16 */
-
-    .data_RAM4 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM4 = .) ;
-        PROVIDE(__start_data_RamAHB16 = .) ;
-        *(.ramfunc.$RAM4)
-        *(.ramfunc.$RamAHB16)
-        *(.data.$RAM4)
-        *(.data.$RamAHB16)
-        *(.data.$RAM4.*)
-        *(.data.$RamAHB16.*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM4 = .) ;
-        PROVIDE(__end_data_RamAHB16 = .) ;
-     } > RamAHB16 AT>MFlashA512
-
-    /* DATA section for RamAHB_ETB16 */
-
-    .data_RAM5 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM5 = .) ;
-        PROVIDE(__start_data_RamAHB_ETB16 = .) ;
-        *(.ramfunc.$RAM5)
-        *(.ramfunc.$RamAHB_ETB16)
-        *(.data.$RAM5)
-        *(.data.$RamAHB_ETB16)
-        *(.data.$RAM5.*)
-        *(.data.$RamAHB_ETB16.*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM5 = .) ;
-        PROVIDE(__end_data_RamAHB_ETB16 = .) ;
-     } > RamAHB_ETB16 AT>MFlashA512
-
-    /* MAIN DATA SECTION */
-    .uninit_RESERVED (NOLOAD) : ALIGN(4)
-    {
-        _start_uninit_RESERVED = .;
-        KEEP(*(.bss.$RESERVED*))
-       . = ALIGN(4) ;
-        _end_uninit_RESERVED = .;
-    } > RamLoc32 AT> RamLoc32
-
-    /* Main DATA section (RamLoc32) */
-    .data : ALIGN(4)
-    {
-       FILL(0xff)
-       _data = . ;
-       PROVIDE(__start_data_RAM = .) ;
-       PROVIDE(__start_data_RamLoc32 = .) ;
-       *(vtable)
-       *(.ramfunc*)
-       KEEP(*(CodeQuickAccess))
-       KEEP(*(DataQuickAccess))
-       *(RamFunction)
-       *(.data*)
-       . = ALIGN(4) ;
-       _edata = . ;
-       PROVIDE(__end_data_RAM = .) ;
-       PROVIDE(__end_data_RamLoc32 = .) ;
-    } > RamLoc32 AT>MFlashA512
-
-    /* BSS section for RamLoc40 */
-    .bss_RAM2 : ALIGN(4)
-    {
-       PROVIDE(__start_bss_RAM2 = .) ;
-       PROVIDE(__start_bss_RamLoc40 = .) ;
-       *(.bss.$RAM2)
-       *(.bss.$RamLoc40)
-       *(.bss.$RAM2.*)
-       *(.bss.$RamLoc40.*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM2 = .) ;
-       PROVIDE(__end_bss_RamLoc40 = .) ;
-    } > RamLoc40 AT> RamLoc40
-
-    /* BSS section for RamAHB32 */
-    .bss_RAM3 : ALIGN(4)
-    {
-       PROVIDE(__start_bss_RAM3 = .) ;
-       PROVIDE(__start_bss_RamAHB32 = .) ;
-       *(.bss.$RAM3)
-       *(.bss.$RamAHB32)
-       *(.bss.$RAM3.*)
-       *(.bss.$RamAHB32.*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM3 = .) ;
-       PROVIDE(__end_bss_RamAHB32 = .) ;
-    } > RamAHB32 AT> RamAHB32
-
-    /* BSS section for RamAHB16 */
-    .bss_RAM4 : ALIGN(4)
-    {
-       PROVIDE(__start_bss_RAM4 = .) ;
-       PROVIDE(__start_bss_RamAHB16 = .) ;
-       *(.bss.$RAM4)
-       *(.bss.$RamAHB16)
-       *(.bss.$RAM4.*)
-       *(.bss.$RamAHB16.*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM4 = .) ;
-       PROVIDE(__end_bss_RamAHB16 = .) ;
-    } > RamAHB16 AT> RamAHB16
-
-    /* BSS section for RamAHB_ETB16 */
-    .bss_RAM5 : ALIGN(4)
-    {
-       PROVIDE(__start_bss_RAM5 = .) ;
-       PROVIDE(__start_bss_RamAHB_ETB16 = .) ;
-       *(.bss.$RAM5)
-       *(.bss.$RamAHB_ETB16)
-       *(.bss.$RAM5.*)
-       *(.bss.$RamAHB_ETB16.*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM5 = .) ;
-       PROVIDE(__end_bss_RamAHB_ETB16 = .) ;
-    } > RamAHB_ETB16 AT> RamAHB_ETB16
-
-    /* MAIN BSS SECTION */
-    .bss : ALIGN(4)
-    {
-        _bss = .;
-        PROVIDE(__start_bss_RAM = .) ;
-        PROVIDE(__start_bss_RamLoc32 = .) ;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4) ;
-        _ebss = .;
-        PROVIDE(__end_bss_RAM = .) ;
-        PROVIDE(__end_bss_RamLoc32 = .) ;
-        PROVIDE(end = .);
-    } > RamLoc32 AT> RamLoc32
-
-    /* NOINIT section for RamLoc40 */
-    .noinit_RAM2 (NOLOAD) : ALIGN(4)
-    {
-       PROVIDE(__start_noinit_RAM2 = .) ;
-       PROVIDE(__start_noinit_RamLoc40 = .) ;
-       *(.noinit.$RAM2)
-       *(.noinit.$RamLoc40)
-       *(.noinit.$RAM2.*)
-       *(.noinit.$RamLoc40.*)
-       . = ALIGN(4) ;
-       PROVIDE(__end_noinit_RAM2 = .) ;
-       PROVIDE(__end_noinit_RamLoc40 = .) ;
-    } > RamLoc40 AT> RamLoc40
-
-    /* NOINIT section for RamAHB32 */
-    .noinit_RAM3 (NOLOAD) : ALIGN(4)
-    {
-       PROVIDE(__start_noinit_RAM3 = .) ;
-       PROVIDE(__start_noinit_RamAHB32 = .) ;
-       *(.noinit.$RAM3)
-       *(.noinit.$RamAHB32)
-       *(.noinit.$RAM3.*)
-       *(.noinit.$RamAHB32.*)
-       . = ALIGN(4) ;
-       PROVIDE(__end_noinit_RAM3 = .) ;
-       PROVIDE(__end_noinit_RamAHB32 = .) ;
-    } > RamAHB32 AT> RamAHB32
-
-    /* NOINIT section for RamAHB16 */
-    .noinit_RAM4 (NOLOAD) : ALIGN(4)
-    {
-       PROVIDE(__start_noinit_RAM4 = .) ;
-       PROVIDE(__start_noinit_RamAHB16 = .) ;
-       *(.noinit.$RAM4)
-       *(.noinit.$RamAHB16)
-       *(.noinit.$RAM4.*)
-       *(.noinit.$RamAHB16.*)
-       . = ALIGN(4) ;
-       PROVIDE(__end_noinit_RAM4 = .) ;
-       PROVIDE(__end_noinit_RamAHB16 = .) ;
-    } > RamAHB16 AT> RamAHB16
-
-    /* NOINIT section for RamAHB_ETB16 */
-    .noinit_RAM5 (NOLOAD) : ALIGN(4)
-    {
-       PROVIDE(__start_noinit_RAM5 = .) ;
-       PROVIDE(__start_noinit_RamAHB_ETB16 = .) ;
-       *(.noinit.$RAM5)
-       *(.noinit.$RamAHB_ETB16)
-       *(.noinit.$RAM5.*)
-       *(.noinit.$RamAHB_ETB16.*)
-       . = ALIGN(4) ;
-       PROVIDE(__end_noinit_RAM5 = .) ;
-       PROVIDE(__end_noinit_RamAHB_ETB16 = .) ;
-    } > RamAHB_ETB16 AT> RamAHB_ETB16
-
-    /* DEFAULT NOINIT SECTION */
-    .noinit (NOLOAD): ALIGN(4)
-    {
-        _noinit = .;
-        PROVIDE(__start_noinit_RAM = .) ;
-        PROVIDE(__start_noinit_RamLoc32 = .) ;
-        *(.noinit*)
-         . = ALIGN(4) ;
-        _end_noinit = .;
-       PROVIDE(__end_noinit_RAM = .) ;
-       PROVIDE(__end_noinit_RamLoc32 = .) ;        
-    } > RamLoc32 AT> RamLoc32
-    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
-    PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
-
-    /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (NMI_Handler + 1) 
-                                         + (HardFault_Handler + 1) 
-                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
-                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
-                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
-                                         ) );
-
-    /* Provide basic symbols giving location and size of main text
-     * block, including initial values of RW data sections. Note that
-     * these will need extending to give a complete picture with
-     * complex images (e.g multiple Flash banks).
-     */
-    _image_start = LOADADDR(.text);
-    _image_end = LOADADDR(.data) + SIZEOF(.data);
-    _image_size = _image_end - _image_start;
-}
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/lpc18/boards/mcb1800/board.h b/tinyusb/hw/bsp/lpc18/boards/mcb1800/board.h
deleted file mode 100755
index 6111da97..00000000
--- a/tinyusb/hw/bsp/lpc18/boards/mcb1800/board.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// PD_10
-#define LED_PORT      6
-#define LED_PIN       24
-
-// P4_0
-#define BUTTON_PORT   2
-#define BUTTON_PIN    0
-
-#define UART_DEV      LPC_USART3
-
-static inline void board_lpc18_pinmux(void)
-{
-  const PINMUX_GRP_T pinmuxing[] =
-  {
-    // LEDs
-    { 0xD, 10, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4) },
-    { 0xD, 11, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4 | SCU_MODE_PULLDOWN) },
-    { 0xD, 12, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4 | SCU_MODE_PULLDOWN) },
-    { 0xD, 13, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4 | SCU_MODE_PULLDOWN) },
-    { 0xD, 14, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4 | SCU_MODE_PULLDOWN) },
-    { 0x9,  0, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0 | SCU_MODE_PULLDOWN) },
-    { 0x9,  1, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0 | SCU_MODE_PULLDOWN) },
-    { 0x9,  2, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0 | SCU_MODE_PULLDOWN) },
-
-    // Button
-    { 0x4, 0, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0 | SCU_MODE_PULLUP) },
-
-    // UART
-    { 2, 3, SCU_MODE_PULLDOWN | SCU_MODE_FUNC2 },
-    { 2, 4, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2 },
-
-    // USB0
-    { 0x6, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC1 },		                // P6_3 USB0_PWR_EN, USB0 VBus function
-
-    { 0x9, 5, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC2 },			              // P9_5 USB1_VBUS_EN, USB1 VBus function
-    { 0x2, 5, SCU_MODE_INACT  | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2 }, // P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION
-  };
-
-  Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
-
-  /* Pin clock mux values, re-used structure, value in first index is meaningless */
-  const PINMUX_GRP_T pinclockmuxing[] =
-  {
-    { 0, 0,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
-    { 0, 1,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
-    { 0, 2,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
-    { 0, 3,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
-  };
-
-  /* Clock pins only, group field not used */
-  for (uint32_t i = 0; i < (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++)
-  {
-    Chip_SCU_ClockPinMuxSet(pinclockmuxing[i].pinnum, pinclockmuxing[i].modefunc);
-  }
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif
diff --git a/tinyusb/hw/bsp/lpc18/boards/mcb1800/board.mk b/tinyusb/hw/bsp/lpc18/boards/mcb1800/board.mk
deleted file mode 100755
index 0307a21d..00000000
--- a/tinyusb/hw/bsp/lpc18/boards/mcb1800/board.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-LD_FILE = $(BOARD_PATH)/lpc1857.ld
-
-# For flash-jlink target
-JLINK_DEVICE = LPC1857
-
-# flash using jlink
-flash: flash-jlink
diff --git a/tinyusb/hw/bsp/lpc18/boards/mcb1800/lpc1857.ld b/tinyusb/hw/bsp/lpc18/boards/mcb1800/lpc1857.ld
deleted file mode 100755
index 9a308e34..00000000
--- a/tinyusb/hw/bsp/lpc18/boards/mcb1800/lpc1857.ld
+++ /dev/null
@@ -1,323 +0,0 @@
-/*
- * GENERATED FILE - DO NOT EDIT
- * (c) Code Red Technologies Ltd, 2008-2013
- * (c) NXP Semiconductors 2013-2019
- * Generated linker script file for LPC1857
- * Created from linkscript.ldt by FMCreateLinkLibraries
- * Using Freemarker v2.3.23
- * MCUXpresso IDE v10.2.1 [Build 795] [2018-07-25] on May 15, 2019 1:01:52 PM
- */
-
-MEMORY
-{
-  /* Define each memory region */
-  MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */  
-  MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */  
-  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */  
-  RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */  
-  RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */  
-  RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */  
-  RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */  
-}
-
-/* Define a symbol for the top of each memory region */
-__base_MFlashA512 = 0x1a000000  ; /* MFlashA512 */  
-__base_Flash = 0x1a000000 ; /* Flash */  
-__top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */  
-__top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */  
-__base_MFlashB512 = 0x1b000000  ; /* MFlashB512 */  
-__base_Flash2 = 0x1b000000 ; /* Flash2 */  
-__top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */  
-__top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */  
-__base_RamLoc32 = 0x10000000  ; /* RamLoc32 */  
-__base_RAM = 0x10000000 ; /* RAM */  
-__top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */  
-__top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */  
-__base_RamLoc40 = 0x10080000  ; /* RamLoc40 */  
-__base_RAM2 = 0x10080000 ; /* RAM2 */  
-__top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */  
-__top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */  
-__base_RamAHB32 = 0x20000000  ; /* RamAHB32 */  
-__base_RAM3 = 0x20000000 ; /* RAM3 */  
-__top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-__top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-__base_RamAHB16 = 0x20008000  ; /* RamAHB16 */  
-__base_RAM4 = 0x20008000 ; /* RAM4 */  
-__top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */  
-__top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */  
-__base_RamAHB_ETB16 = 0x2000c000  ; /* RamAHB_ETB16 */  
-__base_RAM5 = 0x2000c000 ; /* RAM5 */  
-__top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */  
-__top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */  
-
-ENTRY(ResetISR)
-
-SECTIONS
-{
-    .text_Flash2 : ALIGN(4)
-    {
-       FILL(0xff)
-        *(.text_Flash2*) /* for compatibility with previous releases */
-        *(.text_MFlashB512*) /* for compatibility with previous releases */
-        *(.text.$Flash2*)
-        *(.text.$MFlashB512*)
-        *(.rodata.$Flash2*)
-        *(.rodata.$MFlashB512*)
-    } > MFlashB512
-
-    /* MAIN TEXT SECTION */
-    .text : ALIGN(4)
-    {
-        FILL(0xff)
-        __vectors_start__ = ABSOLUTE(.) ;
-        KEEP(*(.isr_vector))
-        /* Global Section Table */
-        . = ALIGN(4) ;
-        __section_table_start = .;
-        __data_section_table = .;
-        LONG(LOADADDR(.data));
-        LONG(    ADDR(.data));
-        LONG(  SIZEOF(.data));
-        LONG(LOADADDR(.data_RAM2));
-        LONG(    ADDR(.data_RAM2));
-        LONG(  SIZEOF(.data_RAM2));
-        LONG(LOADADDR(.data_RAM3));
-        LONG(    ADDR(.data_RAM3));
-        LONG(  SIZEOF(.data_RAM3));
-        LONG(LOADADDR(.data_RAM4));
-        LONG(    ADDR(.data_RAM4));
-        LONG(  SIZEOF(.data_RAM4));
-        LONG(LOADADDR(.data_RAM5));
-        LONG(    ADDR(.data_RAM5));
-        LONG(  SIZEOF(.data_RAM5));
-        __data_section_table_end = .;
-        __bss_section_table = .;
-        LONG(    ADDR(.bss));
-        LONG(  SIZEOF(.bss));
-        LONG(    ADDR(.bss_RAM2));
-        LONG(  SIZEOF(.bss_RAM2));
-        LONG(    ADDR(.bss_RAM3));
-        LONG(  SIZEOF(.bss_RAM3));
-        LONG(    ADDR(.bss_RAM4));
-        LONG(  SIZEOF(.bss_RAM4));
-        LONG(    ADDR(.bss_RAM5));
-        LONG(  SIZEOF(.bss_RAM5));
-        __bss_section_table_end = .;
-        __section_table_end = . ;
-        /* End of Global Section Table */
-
-        *(.after_vectors*)
-
-    } > MFlashA512
-
-    .text : ALIGN(4)
-    {
-       *(.text*)
-       *(.rodata .rodata.* .constdata .constdata.*)
-       . = ALIGN(4);
-    } > MFlashA512
-    /*
-     * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
-     */
-    .ARM.extab : ALIGN(4) 
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > MFlashA512
-
-    __exidx_start = .;
-
-    .ARM.exidx : ALIGN(4)
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > MFlashA512
-    __exidx_end = .;
-
-    _etext = .;
-        
-    /* DATA section for RamLoc40 */
-
-    .data_RAM2 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM2 = .) ;
-        *(.ramfunc.$RAM2)
-        *(.ramfunc.$RamLoc40)
-        *(.data.$RAM2*)
-        *(.data.$RamLoc40*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM2 = .) ;
-     } > RamLoc40 AT>MFlashA512
-    /* DATA section for RamAHB32 */
-
-    .data_RAM3 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM3 = .) ;
-        *(.ramfunc.$RAM3)
-        *(.ramfunc.$RamAHB32)
-        *(.data.$RAM3*)
-        *(.data.$RamAHB32*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM3 = .) ;
-     } > RamAHB32 AT>MFlashA512
-    /* DATA section for RamAHB16 */
-
-    .data_RAM4 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM4 = .) ;
-        *(.ramfunc.$RAM4)
-        *(.ramfunc.$RamAHB16)
-        *(.data.$RAM4*)
-        *(.data.$RamAHB16*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM4 = .) ;
-     } > RamAHB16 AT>MFlashA512
-    /* DATA section for RamAHB_ETB16 */
-
-    .data_RAM5 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM5 = .) ;
-        *(.ramfunc.$RAM5)
-        *(.ramfunc.$RamAHB_ETB16)
-        *(.data.$RAM5*)
-        *(.data.$RamAHB_ETB16*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM5 = .) ;
-     } > RamAHB_ETB16 AT>MFlashA512
-    /* MAIN DATA SECTION */
-    .uninit_RESERVED : ALIGN(4)
-    {
-        KEEP(*(.bss.$RESERVED*))
-        . = ALIGN(4) ;
-        _end_uninit_RESERVED = .;
-    } > RamLoc32
-
-    /* Main DATA section (RamLoc32) */
-    .data : ALIGN(4)
-    {
-       FILL(0xff)
-       _data = . ;
-       *(vtable)
-       *(.ramfunc*)
-       *(.data*)
-       . = ALIGN(4) ;
-       _edata = . ;
-    } > RamLoc32 AT>MFlashA512
-
-    /* BSS section for RamLoc40 */
-    .bss_RAM2 : ALIGN(4)
-    {
-       PROVIDE(__start_bss_RAM2 = .) ;
-       *(.bss.$RAM2*)
-       *(.bss.$RamLoc40*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM2 = .) ;
-    } > RamLoc40 
-
-    /* BSS section for RamAHB32 */
-    .bss_RAM3 : ALIGN(4)
-    {
-       PROVIDE(__start_bss_RAM3 = .) ;
-       *(.bss.$RAM3*)
-       *(.bss.$RamAHB32*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM3 = .) ;
-    } > RamAHB32 
-
-    /* BSS section for RamAHB16 */
-    .bss_RAM4 : ALIGN(4)
-    {
-       PROVIDE(__start_bss_RAM4 = .) ;
-       *(.bss.$RAM4*)
-       *(.bss.$RamAHB16*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM4 = .) ;
-    } > RamAHB16 
-
-    /* BSS section for RamAHB_ETB16 */
-    .bss_RAM5 : ALIGN(4)
-    {
-       PROVIDE(__start_bss_RAM5 = .) ;
-       *(.bss.$RAM5*)
-       *(.bss.$RamAHB_ETB16*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM5 = .) ;
-    } > RamAHB_ETB16 
-
-    /* MAIN BSS SECTION */
-    .bss : ALIGN(4)
-    {
-        _bss = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4) ;
-        _ebss = .;
-        PROVIDE(end = .);
-    } > RamLoc32
-
-    /* NOINIT section for RamLoc40 */
-    .noinit_RAM2 (NOLOAD) : ALIGN(4)
-    {
-       *(.noinit.$RAM2*)
-       *(.noinit.$RamLoc40*)
-       . = ALIGN(4) ;
-    } > RamLoc40 
-
-    /* NOINIT section for RamAHB32 */
-    .noinit_RAM3 (NOLOAD) : ALIGN(4)
-    {
-       *(.noinit.$RAM3*)
-       *(.noinit.$RamAHB32*)
-       . = ALIGN(4) ;
-    } > RamAHB32 
-
-    /* NOINIT section for RamAHB16 */
-    .noinit_RAM4 (NOLOAD) : ALIGN(4)
-    {
-       *(.noinit.$RAM4*)
-       *(.noinit.$RamAHB16*)
-       . = ALIGN(4) ;
-    } > RamAHB16 
-
-    /* NOINIT section for RamAHB_ETB16 */
-    .noinit_RAM5 (NOLOAD) : ALIGN(4)
-    {
-       *(.noinit.$RAM5*)
-       *(.noinit.$RamAHB_ETB16*)
-       . = ALIGN(4) ;
-    } > RamAHB_ETB16 
-
-    /* DEFAULT NOINIT SECTION */
-    .noinit (NOLOAD): ALIGN(4)
-    {
-        _noinit = .;
-        *(.noinit*) 
-         . = ALIGN(4) ;
-        _end_noinit = .;
-    } > RamLoc32
-    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
-    PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
-
-    /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (NMI_Handler + 1) 
-                                         + (HardFault_Handler + 1) 
-                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
-                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
-                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
-                                         ) );
-
-    /* Provide basic symbols giving location and size of main text
-     * block, including initial values of RW data sections. Note that
-     * these will need extending to give a complete picture with
-     * complex images (e.g multiple Flash banks).
-     */
-    _image_start = LOADADDR(.text);
-    _image_end = LOADADDR(.data) + SIZEOF(.data);
-    _image_size = _image_end - _image_start;
-}
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/lpc18/family.c b/tinyusb/hw/bsp/lpc18/family.c
deleted file mode 100755
index d74ebcd3..00000000
--- a/tinyusb/hw/bsp/lpc18/family.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "chip.h"
-#include "bsp/board.h"
-#include "board.h"
-
-//--------------------------------------------------------------------+
-// USB Interrupt Handler
-//--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
-    tuh_int_handler(0);
-  #endif
-
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-    tud_int_handler(0);
-  #endif
-}
-
-void USB1_IRQHandler(void)
-{
-  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
-    tuh_int_handler(1);
-  #endif
-
-  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE
-    tud_int_handler(1);
-  #endif
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-
-
-/* System configuration variables used by chip driver */
-const uint32_t OscRateIn = 12000000;
-const uint32_t ExtRateIn = 0;
-
-// Invoked by startup code
-void SystemInit(void)
-{
-#ifdef __USE_LPCOPEN
-	extern void (* const g_pfnVectors[])(void);
-  unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
-	*pSCB_VTOR = (unsigned int) g_pfnVectors;
-#endif
-
-  board_lpc18_pinmux();
-  Chip_SetupXtalClocking();
-}
-
-void board_init(void)
-{
-  SystemCoreClockUpdate();
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  //NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  Chip_GPIO_Init(LPC_GPIO_PORT);
-
-  // LED
-  Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, LED_PORT, LED_PIN);
-
-  // Button
-  Chip_GPIO_SetPinDIRInput(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN);
-
-  //------------- UART -------------//
-  Chip_UART_Init(UART_DEV);
-  Chip_UART_SetBaud(UART_DEV, CFG_BOARD_UART_BAUDRATE);
-  Chip_UART_ConfigData(UART_DEV, UART_LCR_WLEN8 | UART_LCR_SBS_1BIT | UART_LCR_PARITY_DIS);
-  Chip_UART_TXEnable(UART_DEV);
-
-  //------------- USB -------------//
-#if CFG_TUSB_RHPORT0_MODE
-  Chip_USB0_Init();
-#endif
-
-#if CFG_TUSB_RHPORT1_MODE
-  Chip_USB1_Init();
-#endif
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  Chip_GPIO_SetPinState(LPC_GPIO_PORT, LED_PORT, LED_PIN, state);
-}
-
-uint32_t board_button_read(void)
-{
-  // active low
-  return Chip_GPIO_GetPinState(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN) ? 0 : 1;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  //return UART_ReceiveByte(BOARD_UART_PORT);
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  uint8_t const* buf8 = (uint8_t const*) buf;
-  for(int i=0; i<len; i++)
-  {
-    while ((Chip_UART_ReadLineStatus(UART_DEV) & UART_LSR_THRE) == 0) {}
-    Chip_UART_SendByte(UART_DEV, buf8[i]);
-  }
-
-  return len;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/tinyusb/hw/bsp/lpc18/family.mk b/tinyusb/hw/bsp/lpc18/family.mk
deleted file mode 100755
index 3fed0b45..00000000
--- a/tinyusb/hw/bsp/lpc18/family.mk
+++ /dev/null
@@ -1,35 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m3 \
-  -nostdlib \
-  -DCORE_M3 \
-  -D__USE_LPCOPEN \
-  -DCFG_TUSB_MCU=OPT_MCU_LPC18XX
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes
-
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx
-
-SRC_C += \
-	src/portable/nxp/transdimension/dcd_transdimension.c \
-	$(MCU_DIR)/../gcc/cr_startup_lpc18xx.c \
-	$(MCU_DIR)/src/chip_18xx_43xx.c \
-	$(MCU_DIR)/src/clock_18xx_43xx.c \
-	$(MCU_DIR)/src/gpio_18xx_43xx.c \
-	$(MCU_DIR)/src/sysinit_18xx_43xx.c \
-	$(MCU_DIR)/src/uart_18xx_43xx.c
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(MCU_DIR)/inc \
-	$(TOP)/$(MCU_DIR)/inc/config_18xx
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
diff --git a/tinyusb/hw/bsp/lpc54/boards/lpcxpresso54114/board.h b/tinyusb/hw/bsp/lpc54/boards/lpcxpresso54114/board.h
deleted file mode 100755
index b1ad4258..00000000
--- a/tinyusb/hw/bsp/lpc54/boards/lpcxpresso54114/board.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PORT              0
-#define LED_PIN               29
-#define LED_STATE_ON          0
-
-// WAKE button
-#define BUTTON_PORT           0
-#define BUTTON_PIN            24
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_DEV              USART0
-#define UART_RX_PINMUX        0, 0, IOCON_PIO_DIG_FUNC1_EN
-#define UART_TX_PINMUX        0, 1, IOCON_PIO_DIG_FUNC1_EN
-
-// USB0 VBUS
-#define USB0_VBUS_PINMUX      1, 6, IOCON_PIO_DIG_FUNC7_EN
-
-// XTAL
-//#define XTAL0_CLK_HZ          (16 * 1000 * 1000U)
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif
diff --git a/tinyusb/hw/bsp/lpc54/boards/lpcxpresso54114/board.mk b/tinyusb/hw/bsp/lpc54/boards/lpcxpresso54114/board.mk
deleted file mode 100755
index 6e33d8cb..00000000
--- a/tinyusb/hw/bsp/lpc54/boards/lpcxpresso54114/board.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-MCU_VARIANT = LPC54114
-MCU_CORE = LPC54114_cm4
-
-CFLAGS += -DCPU_LPC54114J256BD64_cm4
-LD_FILE = $(MCU_DIR)/gcc/LPC54114J256_cm4_flash.ld
-
-LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower_cm4_hardabi.a
-
-JLINK_DEVICE = LPC54114J256_M4
-PYOCD_TARGET = LPC54114
-
-# flash using pyocd
-flash: flash-pyocd
diff --git a/tinyusb/hw/bsp/lpc54/boards/lpcxpresso54628/board.h b/tinyusb/hw/bsp/lpc54/boards/lpcxpresso54628/board.h
deleted file mode 100755
index 67027751..00000000
--- a/tinyusb/hw/bsp/lpc54/boards/lpcxpresso54628/board.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PORT              2
-#define LED_PIN               2
-#define LED_STATE_ON          0
-
-// WAKE button
-#define BUTTON_PORT           1
-#define BUTTON_PIN            1
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_DEV              USART0
-#define UART_RX_PINMUX        0, 29, IOCON_PIO_DIG_FUNC1_EN
-#define UART_TX_PINMUX        0, 30, IOCON_PIO_DIG_FUNC1_EN
-
-// USB0 VBUS
-#define USB0_VBUS_PINMUX      0, 22, IOCON_PIO_DIG_FUNC7_EN
-
-// XTAL
-//#define XTAL0_CLK_HZ          (16 * 1000 * 1000U)
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif
diff --git a/tinyusb/hw/bsp/lpc54/boards/lpcxpresso54628/board.mk b/tinyusb/hw/bsp/lpc54/boards/lpcxpresso54628/board.mk
deleted file mode 100755
index 925374cc..00000000
--- a/tinyusb/hw/bsp/lpc54/boards/lpcxpresso54628/board.mk
+++ /dev/null
@@ -1,18 +0,0 @@
-MCU_VARIANT = LPC54628
-MCU_CORE = LPC54628
-
-PORT ?= 0
-
-CFLAGS += -DCPU_LPC54628J512ET180
-CFLAGS += -Wno-error=double-promotion
-
-LD_FILE = $(MCU_DIR)/gcc/LPC54628J512_flash.ld
-
-LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower_hardabi.a
-
-JLINK_DEVICE = LPC54628J512
-PYOCD_TARGET = LPC54628
-
-#flash: flash-pyocd
-
-flash: flash-jlink
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/lpc54/family.c b/tinyusb/hw/bsp/lpc54/family.c
deleted file mode 100755
index 4789425a..00000000
--- a/tinyusb/hw/bsp/lpc54/family.c
+++ /dev/null
@@ -1,228 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2018, hathach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "fsl_device_registers.h"
-#include "fsl_gpio.h"
-#include "fsl_power.h"
-#include "fsl_iocon.h"
-#include "fsl_usart.h"
-
-#include "bsp/board.h"
-#include "board.h"
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-// IOCON pin mux
-#define IOCON_PIO_DIGITAL_EN     0x80u   // Enables digital function
-#define IOCON_PIO_FUNC0          0x00u
-#define IOCON_PIO_FUNC1          0x01u   // Selects pin function 1
-#define IOCON_PIO_FUNC7          0x07u   // Selects pin function 7
-#define IOCON_PIO_INPFILT_OFF    0x0100u // Input filter disabled
-#define IOCON_PIO_INV_DI         0x00u   // Input function is not inverted
-#define IOCON_PIO_MODE_INACT     0x00u   // No addition pin function
-#define IOCON_PIO_MODE_PULLUP    0x10u
-#define IOCON_PIO_OPENDRAIN_DI   0x00u   // Open drain is disabled
-#define IOCON_PIO_SLEW_STANDARD  0x00u   // Standard mode, output slew rate control is enabled
-
-// Digital pin function n enabled
-#define IOCON_PIO_DIG_FUNC0_EN   (IOCON_PIO_DIGITAL_EN | IOCON_PIO_INPFILT_OFF | IOCON_PIO_FUNC0)
-#define IOCON_PIO_DIG_FUNC1_EN   (IOCON_PIO_DIGITAL_EN | IOCON_PIO_INPFILT_OFF | IOCON_PIO_FUNC1)
-#define IOCON_PIO_DIG_FUNC4_EN   (IOCON_PIO_DIGITAL_EN | IOCON_PIO_INPFILT_OFF | IOCON_PIO_FUNC4)
-#define IOCON_PIO_DIG_FUNC7_EN   (IOCON_PIO_DIGITAL_EN | IOCON_PIO_INPFILT_OFF | IOCON_PIO_FUNC7)
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-void USB1_IRQHandler(void)
-{
-  tud_int_handler(1);
-}
-
-/****************************************************************
-name: BOARD_BootClockFROHF96M
-outputs:
-- {id: SYSTICK_clock.outFreq, value: 96 MHz}
-- {id: System_clock.outFreq, value: 96 MHz}
-settings:
-- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
-sources:
-- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
-******************************************************************/
-void BootClockFROHF96M(void)
-{
-  /*!< Set up the clock sources */
-  /*!< Set up FRO */
-  POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
-  CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
-                                             accidentally being below the voltage for current speed */
-  POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
-  CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
-
-  CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
-
-  /*!< Set up dividers */
-  CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);     /*!< Set AHBCLKDIV divider to value 1 */
-
-  /*!< Set up clock selectors - Attach clocks to the peripheries */
-  CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
-
-  /*!< Set SystemCoreClock variable. */
-  SystemCoreClock = 96000000U;
-}
-
-void board_init(void)
-{
-  // Enable IOCON clock
-  CLOCK_EnableClock(kCLOCK_Iocon);
-
-  // Init 96 MHz clock
-  BootClockFROHF96M();
-
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-
-#if CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  // Init all GPIO ports 54114 only has 2 ports.
-  GPIO_PortInit(GPIO, LED_PORT);
-  GPIO_PortInit(GPIO, BUTTON_PORT);
-
-  // LED
-  IOCON_PinMuxSet(IOCON, LED_PORT, LED_PIN, IOCON_PIO_DIG_FUNC0_EN);
-  gpio_pin_config_t const led_config = { kGPIO_DigitalOutput, 0};
-  GPIO_PinInit(GPIO, LED_PORT, LED_PIN, &led_config);
-
-  board_led_write(0);
-
-  // Button
-  IOCON_PinMuxSet(IOCON, BUTTON_PORT, BUTTON_PIN, IOCON_PIO_DIG_FUNC0_EN | IOCON_PIO_MODE_PULLUP);
-  gpio_pin_config_t const button_config = { kGPIO_DigitalInput, 0};
-  GPIO_PinInit(GPIO, BUTTON_PORT, BUTTON_PIN, &button_config);
-
-#ifdef UART_DEV
-  // UART
-  IOCON_PinMuxSet(IOCON, UART_RX_PINMUX);
-  IOCON_PinMuxSet(IOCON, UART_TX_PINMUX);
-
-  // Enable UART when debug log is on
-  CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0);
-  usart_config_t uart_config;
-  USART_GetDefaultConfig(&uart_config);
-  uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
-  uart_config.enableTx     = true;
-  uart_config.enableRx     = true;
-  USART_Init(UART_DEV, &uart_config, 12000000);
-#endif
-
-  // USB
-  IOCON_PinMuxSet(IOCON, USB0_VBUS_PINMUX);
-
-#if defined(FSL_FEATURE_SOC_USBHSD_COUNT) && FSL_FEATURE_SOC_USBHSD_COUNT
-  // LPC546xx and LPC540xx has OTG 1 FS + 1 HS rhports
-
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-    // Port0 is Full Speed
-    POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); /*< Turn on USB Phy */
-    CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false);
-    CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
-
-    /*According to reference mannual, device mode setting has to be set by access usb host register */
-    CLOCK_EnableClock(kCLOCK_Usbhsl0); /* enable usb0 host clock */
-    USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK;
-    CLOCK_DisableClock(kCLOCK_Usbhsl0); /* disable usb0 host clock */
-
-    CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbSrcFro, CLOCK_GetFroHfFreq());
-  #endif
-
-  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE
-    // Port1 is High Speed
-    POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY);
-
-    /*According to reference mannual, device mode setting has to be set by access usb host register */
-    CLOCK_EnableClock(kCLOCK_Usbh1); /* enable usb1 host clock */
-    USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK;
-    CLOCK_DisableClock(kCLOCK_Usbh1); /* enable usb1 host clock */
-
-    CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUsbPll, 0U);
-  #endif
-
-#else
-  // LPC5411x series only has full speed device
-
-  POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); // Turn on USB Phy
-  CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcFro, CLOCK_GetFreq(kCLOCK_FroHf)); /* enable USB IP clock */
-#endif
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  GPIO_PinWrite(GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  // active low
-  return BUTTON_STATE_ACTIVE == GPIO_PinRead(GPIO, BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  USART_WriteBlocking(UART_DEV, (uint8_t *)buf, len);
-  return 0;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/tinyusb/hw/bsp/lpc54/family.mk b/tinyusb/hw/bsp/lpc54/family.mk
deleted file mode 100755
index 600df6fd..00000000
--- a/tinyusb/hw/bsp/lpc54/family.mk
+++ /dev/null
@@ -1,54 +0,0 @@
-SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += $(SDK_DIR)
-
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -DCFG_TUSB_MCU=OPT_MCU_LPC54XXX \
-  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' 
-
-ifeq ($(PORT), 1)
-  $(info "PORT1 High Speed")
-  CFLAGS += -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED
-
-  # LPC55 Highspeed Port1 can only write to USB_SRAM region
-  CFLAGS += -DCFG_TUSB_MEM_SECTION='__attribute__((section("m_usb_global")))'
-else
-  $(info "PORT0 Full Speed")
-endif
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter
-
-MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT)
-
-SRC_C += \
-	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
-	$(MCU_DIR)/system_$(MCU_CORE).c \
-	$(MCU_DIR)/drivers/fsl_clock.c \
-	$(MCU_DIR)/drivers/fsl_power.c \
-	$(MCU_DIR)/drivers/fsl_reset.c \
-	$(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \
-	$(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \
-	$(SDK_DIR)/drivers/flexcomm/fsl_usart.c
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(MCU_DIR)/../../CMSIS/Include \
-	$(TOP)/$(MCU_DIR) \
-	$(TOP)/$(MCU_DIR)/drivers \
-	$(TOP)/$(SDK_DIR)/drivers/common \
-	$(TOP)/$(SDK_DIR)/drivers/flexcomm \
-	$(TOP)/$(SDK_DIR)/drivers/lpc_iocon \
-	$(TOP)/$(SDK_DIR)/drivers/lpc_gpio
-
-SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_CORE).S
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
diff --git a/tinyusb/hw/bsp/lpc55/boards/double_m33_express/LPC55S69_cm33_core0_uf2.ld b/tinyusb/hw/bsp/lpc55/boards/double_m33_express/LPC55S69_cm33_core0_uf2.ld
deleted file mode 100755
index 6b5d852a..00000000
--- a/tinyusb/hw/bsp/lpc55/boards/double_m33_express/LPC55S69_cm33_core0_uf2.ld
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
-** ###################################################################
-**     Processors:          LPC55S69JBD100_cm33_core0
-**                          LPC55S69JBD64_cm33_core0
-**                          LPC55S69JEV98_cm33_core0
-**
-**     Compiler:            GNU C Compiler
-**     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019
-**     Version:             rev. 1.1, 2019-05-16
-**     Build:               b191008
-**
-**     Abstract:
-**         Linker file for the GNU C Compiler
-**
-**     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2019 NXP
-**     All rights reserved.
-**
-**     SPDX-License-Identifier: BSD-3-Clause
-**
-**     http:                 www.nxp.com
-**     mail:                 support@nxp.com
-**
-** ###################################################################
-*/
-
-
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
-STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800;
-RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0;
-
-/* Specify the memory areas */
-MEMORY
-{
-  m_interrupts          (RX)  : ORIGIN = 0x00010000, LENGTH = 0x00000200
-  m_text                (RX)  : ORIGIN = 0x00010200, LENGTH = 0x0007FE00
-  m_core1_image         (RX)  : ORIGIN = 0x00090000, LENGTH = 0x00008000
-  m_data                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00033000 - RPMSG_SHMEM_SIZE
-  rpmsg_sh_mem          (RW)  : ORIGIN = 0x20033000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE
-  m_usb_sram            (RW)  : ORIGIN = 0x40100000, LENGTH = 0x00004000
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* section for storing the secondary core image */
-  .m0code :
-  {
-     . = ALIGN(4) ;
-    KEEP (*(.m0code))
-     *(.m0code*)
-     . = ALIGN(4) ;
-  } > m_core1_image
-
-  /* NOINIT section for rpmsg_sh_mem */
-  .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4)
-  {
-     __RPMSG_SH_MEM_START__ = .;
-     *(.noinit.$rpmsg_sh_mem*)
-     . = ALIGN(4) ;
-     __RPMSG_SH_MEM_END__ = .;
-  } > rpmsg_sh_mem
-
-  /* The startup code goes first into internal flash */
-  .interrupts :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector))     /* Startup code */
-    . = ALIGN(4);
-  } > m_interrupts
-
-  /* The program code and other data goes into internal flash */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)                 /* .text sections (code) */
-    *(.text*)                /* .text* sections (code) */
-    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
-    *(.glue_7)               /* glue arm to thumb code */
-    *(.glue_7t)              /* glue thumb to arm code */
-    *(.eh_frame)
-    KEEP (*(.init))
-    KEEP (*(.fini))
-    . = ALIGN(4);
-  } > m_text
-
-  .ARM.extab :
-  {
-    *(.ARM.extab* .gnu.linkonce.armextab.*)
-  } > m_text
-
-  .ARM :
-  {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } > m_text
-
- .ctors :
-  {
-    __CTOR_LIST__ = .;
-    /* gcc uses crtbegin.o to find the start of
-       the constructors, so we make sure it is
-       first.  Because this is a wildcard, it
-       doesn't matter if the user does not
-       actually link against crtbegin.o; the
-       linker won't look for a file to match a
-       wildcard.  The wildcard also means that it
-       doesn't matter which directory crtbegin.o
-       is in.  */
-    KEEP (*crtbegin.o(.ctors))
-    KEEP (*crtbegin?.o(.ctors))
-    /* We don't want to include the .ctor section from
-       from the crtend.o file until after the sorted ctors.
-       The .ctor section from the crtend file contains the
-       end of ctors marker and it must be last */
-    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
-    KEEP (*(SORT(.ctors.*)))
-    KEEP (*(.ctors))
-    __CTOR_END__ = .;
-  } > m_text
-
-  .dtors :
-  {
-    __DTOR_LIST__ = .;
-    KEEP (*crtbegin.o(.dtors))
-    KEEP (*crtbegin?.o(.dtors))
-    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
-    KEEP (*(SORT(.dtors.*)))
-    KEEP (*(.dtors))
-    __DTOR_END__ = .;
-  } > m_text
-
-  .preinit_array :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } > m_text
-
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } > m_text
-
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } > m_text
-
-  __etext = .;    /* define a global symbol at end of code */
-  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
-
-  .data : AT(__DATA_ROM)
-  {
-    . = ALIGN(4);
-    __DATA_RAM = .;
-    __data_start__ = .;      /* create a global symbol at data start */
-    *(.ramfunc*)             /* for functions in ram */
-    *(.data)                 /* .data sections */
-    *(.data*)                /* .data* sections */
-    KEEP(*(.jcr*))
-    . = ALIGN(4);
-    __data_end__ = .;        /* define a global symbol at data end */
-  } > m_data
-
-  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
-  text_end = ORIGIN(m_text) + LENGTH(m_text);
-  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
-
-  /* Uninitialized data section */
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss section */
-    . = ALIGN(4);
-    __START_BSS = .;
-    __bss_start__ = .;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-    . = ALIGN(4);
-    __bss_end__ = .;
-    __END_BSS = .;
-  } > m_data
-
-  .heap :
-  {
-    . = ALIGN(8);
-    __end__ = .;
-    PROVIDE(end = .);
-    __HeapBase = .;
-    . += HEAP_SIZE;
-    __HeapLimit = .;
-    __heap_limit = .; /* Add for _sbrk */
-  } > m_data
-
-  .stack :
-  {
-    . = ALIGN(8);
-    . += STACK_SIZE;
-  } > m_data
-
-  m_usb_bdt (NOLOAD) :
-  {
-    . = ALIGN(512);
-    *(m_usb_bdt)
-  } > m_usb_sram
-
-  m_usb_global (NOLOAD) :
-  {
-    *(m_usb_global)
-  } > m_usb_sram
-
-  /* Initializes stack on the end of block */
-  __StackTop   = ORIGIN(m_data) + LENGTH(m_data);
-  __StackLimit = __StackTop - STACK_SIZE;
-  PROVIDE(__stack = __StackTop);
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-
-  ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
-}
-
diff --git a/tinyusb/hw/bsp/lpc55/boards/double_m33_express/board.h b/tinyusb/hw/bsp/lpc55/boards/double_m33_express/board.h
deleted file mode 100755
index 975e74e9..00000000
--- a/tinyusb/hw/bsp/lpc55/boards/double_m33_express/board.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PORT              0
-#define LED_PIN               1
-#define LED_STATE_ON          1
-
-// WAKE button
-#define BUTTON_PORT           0
-#define BUTTON_PIN            5
-#define BUTTON_STATE_ACTIVE   0
-
-// Number of neopixels
-#define NEOPIXEL_NUMBER       2
-#define NEOPIXEL_PORT         0
-#define NEOPIXEL_PIN          27
-#define NEOPIXEL_CH           6
-#define NEOPIXEL_TYPE         0
-
-// UART
-#define UART_DEV              USART0
-#define UART_RX_PINMUX        0U, 29U, IOCON_PIO_DIG_FUNC1_EN
-#define UART_TX_PINMUX        0U, 30U, IOCON_PIO_DIG_FUNC1_EN
-
-// XTAL
-#define XTAL0_CLK_HZ          (16 * 1000 * 1000U)
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif
diff --git a/tinyusb/hw/bsp/lpc55/boards/double_m33_express/board.mk b/tinyusb/hw/bsp/lpc55/boards/double_m33_express/board.mk
deleted file mode 100755
index d28700ca..00000000
--- a/tinyusb/hw/bsp/lpc55/boards/double_m33_express/board.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-MCU_VARIANT = LPC55S69
-MCU_CORE = LPC55S69_cm33_core0
-PORT ?= 1
-
-CFLAGS += -DCPU_LPC55S69JBD100_cm33_core0
-LD_FILE = $(BOARD_PATH)/LPC55S69_cm33_core0_uf2.ld
-
-JLINK_DEVICE = LPC55S69
-PYOCD_TARGET = LPC55S69
-
-# flash using pyocd
-flash: flash-pyocd
diff --git a/tinyusb/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h b/tinyusb/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h
deleted file mode 100755
index f85701b0..00000000
--- a/tinyusb/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PORT              1
-#define LED_PIN               6
-#define LED_STATE_ON          0
-
-// WAKE button
-#define BUTTON_PORT           1
-#define BUTTON_PIN            18
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_DEV              USART0
-#define UART_RX_PINMUX        0, 29, IOCON_PIO_DIG_FUNC1_EN
-#define UART_TX_PINMUX        0, 30, IOCON_PIO_DIG_FUNC1_EN
-
-// XTAL
-#define XTAL0_CLK_HZ          (16 * 1000 * 1000U)
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif
diff --git a/tinyusb/hw/bsp/lpc55/boards/lpcxpresso55s28/board.mk b/tinyusb/hw/bsp/lpc55/boards/lpcxpresso55s28/board.mk
deleted file mode 100755
index ec0828e4..00000000
--- a/tinyusb/hw/bsp/lpc55/boards/lpcxpresso55s28/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-MCU_VARIANT = LPC55S28
-MCU_CORE = LPC55S28
-PORT ?= 1
-
-CFLAGS += -DCPU_LPC55S28JBD100
-
-JLINK_DEVICE = LPC55S28
-PYOCD_TARGET = LPC55S28
-
-# flash using pyocd
-flash: flash-pyocd
diff --git a/tinyusb/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h b/tinyusb/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h
deleted file mode 100755
index f85701b0..00000000
--- a/tinyusb/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PORT              1
-#define LED_PIN               6
-#define LED_STATE_ON          0
-
-// WAKE button
-#define BUTTON_PORT           1
-#define BUTTON_PIN            18
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_DEV              USART0
-#define UART_RX_PINMUX        0, 29, IOCON_PIO_DIG_FUNC1_EN
-#define UART_TX_PINMUX        0, 30, IOCON_PIO_DIG_FUNC1_EN
-
-// XTAL
-#define XTAL0_CLK_HZ          (16 * 1000 * 1000U)
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif
diff --git a/tinyusb/hw/bsp/lpc55/boards/lpcxpresso55s69/board.mk b/tinyusb/hw/bsp/lpc55/boards/lpcxpresso55s69/board.mk
deleted file mode 100755
index 73edc88a..00000000
--- a/tinyusb/hw/bsp/lpc55/boards/lpcxpresso55s69/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-MCU_VARIANT = LPC55S69
-MCU_CORE = LPC55S69_cm33_core0
-PORT ?= 1
-
-CFLAGS += -DCPU_LPC55S69JBD100_cm33_core0
-
-JLINK_DEVICE = LPC55S69
-PYOCD_TARGET = LPC55S69
-
-# flash using pyocd
-flash: flash-pyocd
diff --git a/tinyusb/hw/bsp/lpc55/boards/mcu_link/board.h b/tinyusb/hw/bsp/lpc55/boards/mcu_link/board.h
deleted file mode 100755
index 5e17cf9f..00000000
--- a/tinyusb/hw/bsp/lpc55/boards/mcu_link/board.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PORT              0
-#define LED_PIN               5
-#define LED_STATE_ON          0
-
-// WAKE button (Dummy, use unused pin
-#define BUTTON_PORT           0
-#define BUTTON_PIN            30
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_DEV              USART0
-#define UART_RX_PINMUX        0, 24, IOCON_PIO_DIG_FUNC1_EN
-#define UART_TX_PINMUX        0, 25, IOCON_PIO_DIG_FUNC1_EN
-
-// XTAL
-#define XTAL0_CLK_HZ          (16 * 1000 * 1000U)
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif
diff --git a/tinyusb/hw/bsp/lpc55/boards/mcu_link/board.mk b/tinyusb/hw/bsp/lpc55/boards/mcu_link/board.mk
deleted file mode 100755
index ceb1d0eb..00000000
--- a/tinyusb/hw/bsp/lpc55/boards/mcu_link/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-MCU_VARIANT = LPC55S69
-MCU_CORE = LPC55S69_cm33_core0
-PORT ?= 1
-
-CFLAGS += -DCPU_LPC55S69JBD64_cm33_core0
-
-JLINK_DEVICE = LPC55S69
-PYOCD_TARGET = LPC55S69
-
-# flash using pyocd
-flash: flash-pyocd
diff --git a/tinyusb/hw/bsp/lpc55/family.c b/tinyusb/hw/bsp/lpc55/family.c
deleted file mode 100755
index 4fc1f622..00000000
--- a/tinyusb/hw/bsp/lpc55/family.c
+++ /dev/null
@@ -1,283 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2018, hathach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "bsp/board.h"
-#include "board.h"
-#include "fsl_device_registers.h"
-#include "fsl_gpio.h"
-#include "fsl_power.h"
-#include "fsl_iocon.h"
-#include "fsl_usart.h"
-#include "fsl_sctimer.h"
-#include "sct_neopixel.h"
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-// IOCON pin mux
-#define IOCON_PIO_DIGITAL_EN     0x0100u // Enables digital function
-#define IOCON_PIO_FUNC0          0x00u   // Selects pin function 0
-#define IOCON_PIO_FUNC1          0x01u   // Selects pin function 1
-#define IOCON_PIO_FUNC4          0x04u   // Selects pin function 4
-#define IOCON_PIO_FUNC7          0x07u   // Selects pin function 7
-#define IOCON_PIO_INV_DI         0x00u   // Input function is not inverted
-#define IOCON_PIO_MODE_INACT     0x00u   // No addition pin function
-#define IOCON_PIO_OPENDRAIN_DI   0x00u   // Open drain is disabled
-#define IOCON_PIO_SLEW_STANDARD  0x00u   // Standard mode, output slew rate control is enabled
-
-#define IOCON_PIO_DIG_FUNC0_EN   (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC0) // Digital pin function 0 enabled
-#define IOCON_PIO_DIG_FUNC1_EN   (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC1) // Digital pin function 1 enabled
-#define IOCON_PIO_DIG_FUNC4_EN   (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC4) // Digital pin function 2 enabled
-#define IOCON_PIO_DIG_FUNC7_EN   (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC7) // Digital pin function 2 enabled
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-void USB1_IRQHandler(void)
-{
-  tud_int_handler(1);
-}
-
-/****************************************************************
-name: BOARD_BootClockFROHF96M
-outputs:
-- {id: SYSTICK_clock.outFreq, value: 96 MHz}
-- {id: System_clock.outFreq, value: 96 MHz}
-settings:
-- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
-sources:
-- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
-******************************************************************/
-void BootClockFROHF96M(void)
-{
-  /*!< Set up the clock sources */
-  /*!< Set up FRO */
-  POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on  */
-  CLOCK_SetupFROClocking(12000000U);     /*!< Set up FRO to the 12 MHz, just for sure */
-  CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
-                                             accidentally being below the voltage for current speed */
-
-  CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
-
-  POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
-  CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
-
-  /*!< Set up dividers */
-  CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);     /*!< Set AHBCLKDIV divider to value 1 */
-
-  /*!< Set up clock selectors - Attach clocks to the peripheries */
-  CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
-
-  /*!< Set SystemCoreClock variable. */
-  SystemCoreClock = 96000000U;
-}
-
-void board_init(void)
-{
-  // Enable IOCON clock
-  CLOCK_EnableClock(kCLOCK_Iocon);
-
-  // Init 96 MHz clock
-  BootClockFROHF96M();
-
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-
-#if CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  // Init all GPIO ports
-  GPIO_PortInit(GPIO, 0);
-  GPIO_PortInit(GPIO, 1);
-
-  // LED
-  IOCON_PinMuxSet(IOCON, LED_PORT, LED_PIN, IOCON_PIO_DIG_FUNC0_EN);
-  gpio_pin_config_t const led_config = { kGPIO_DigitalOutput, 1};
-  GPIO_PinInit(GPIO, LED_PORT, LED_PIN, &led_config);
-
-  board_led_write(0);
-
-#ifdef NEOPIXEL_PIN
-  // Neopixel
-  static uint32_t pixelData[NEOPIXEL_NUMBER];
-  IOCON_PinMuxSet(IOCON, NEOPIXEL_PORT, NEOPIXEL_PIN, IOCON_PIO_DIG_FUNC4_EN);
-
-  sctpix_init(NEOPIXEL_TYPE);
-  sctpix_addCh(NEOPIXEL_CH, pixelData, NEOPIXEL_NUMBER);
-  sctpix_setPixel(NEOPIXEL_CH, 0, 0x100010);
-  sctpix_setPixel(NEOPIXEL_CH, 1, 0x100010);
-  sctpix_show();
-#endif
-
-  // Button
-  IOCON_PinMuxSet(IOCON, BUTTON_PORT, BUTTON_PIN, IOCON_PIO_DIG_FUNC0_EN);
-  gpio_pin_config_t const button_config = { kGPIO_DigitalInput, 0};
-  GPIO_PinInit(GPIO, BUTTON_PORT, BUTTON_PIN, &button_config);
-
-#ifdef UART_DEV
-  // UART
-  IOCON_PinMuxSet(IOCON, UART_RX_PINMUX);
-  IOCON_PinMuxSet(IOCON, UART_TX_PINMUX);
-
-  // Enable UART when debug log is on
-  CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0);
-  usart_config_t uart_config;
-  USART_GetDefaultConfig(&uart_config);
-  uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
-  uart_config.enableTx     = true;
-  uart_config.enableRx     = true;
-  USART_Init(UART_DEV, &uart_config, 12000000);
-#endif
-
-  // USB VBUS
-  /* PORT0 PIN22 configured as USB0_VBUS */
-  IOCON_PinMuxSet(IOCON, 0U, 22U, IOCON_PIO_DIG_FUNC7_EN);
-
-#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-  // Port0 is Full Speed
-
-  /* Turn on USB0 Phy */
-  POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY);
-
-  /* reset the IP to make sure it's in reset state. */
-  RESET_PeripheralReset(kUSB0D_RST_SHIFT_RSTn);
-  RESET_PeripheralReset(kUSB0HSL_RST_SHIFT_RSTn);
-  RESET_PeripheralReset(kUSB0HMR_RST_SHIFT_RSTn);
-
-  // Enable USB Clock Adjustments to trim the FRO for the full speed controller
-  ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK;
-  CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false);
-  CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
-
-  /*According to reference mannual, device mode setting has to be set by access usb host register */
-  CLOCK_EnableClock(kCLOCK_Usbhsl0);  // enable usb0 host clock
-  USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK;
-  CLOCK_DisableClock(kCLOCK_Usbhsl0); // disable usb0 host clock
-
-  /* enable USB Device clock */
-  CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbfsSrcFro, CLOCK_GetFreq(kCLOCK_FroHf));
-#endif
-
-#if CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE
-  // Port1 is High Speed
-
-  /* Turn on USB1 Phy */
-  POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY);
-
-  /* reset the IP to make sure it's in reset state. */
-  RESET_PeripheralReset(kUSB1H_RST_SHIFT_RSTn);
-  RESET_PeripheralReset(kUSB1D_RST_SHIFT_RSTn);
-  RESET_PeripheralReset(kUSB1_RST_SHIFT_RSTn);
-  RESET_PeripheralReset(kUSB1RAM_RST_SHIFT_RSTn);
-
-  /* According to reference mannual, device mode setting has to be set by access usb host register */
-  CLOCK_EnableClock(kCLOCK_Usbh1); // enable usb0 host clock
-
-  USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK; // Put PHY powerdown under software control
-  USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK;
-
-  CLOCK_DisableClock(kCLOCK_Usbh1); // disable usb0 host clock
-
-  /* enable USB Device clock */
-  CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_UsbPhySrcExt, XTAL0_CLK_HZ);
-  CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUnused, 0U);
-  CLOCK_EnableClock(kCLOCK_UsbRam1);
-
-  // Enable PHY support for Low speed device + LS via FS Hub
-  USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
-
-  // Enable all power for normal operation
-  USBPHY->PWD = 0;
-
-  USBPHY->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK;
-  USBPHY->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK;
-
-  // TX Timing
-//  uint32_t phytx = USBPHY->TX;
-//  phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
-//  phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
-//  USBPHY->TX = phytx;
-#endif
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  GPIO_PinWrite(GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-
-#ifdef NEOPIXEL_PIN
-  if (state) {
-    sctpix_setPixel(NEOPIXEL_CH, 0, 0x100000);
-    sctpix_setPixel(NEOPIXEL_CH, 1, 0x101010);
-  } else {
-    sctpix_setPixel(NEOPIXEL_CH, 0, 0x001000);
-    sctpix_setPixel(NEOPIXEL_CH, 1, 0x000010);
-  }
-  sctpix_show();
-#endif
-}
-
-uint32_t board_button_read(void)
-{
-  // active low
-  return BUTTON_STATE_ACTIVE == GPIO_PinRead(GPIO, BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  USART_WriteBlocking(UART_DEV, (uint8_t *)buf, len);
-  return len;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/tinyusb/hw/bsp/lpc55/family.mk b/tinyusb/hw/bsp/lpc55/family.mk
deleted file mode 100755
index 4e8d65ce..00000000
--- a/tinyusb/hw/bsp/lpc55/family.mk
+++ /dev/null
@@ -1,67 +0,0 @@
-UF2_FAMILY_ID = 0x2abc77ec
-SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += lib/sct_neopixel $(SDK_DIR)
-
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-# Default to Highspeed PORT1
-PORT ?= 1
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m33 \
-  -mfloat-abi=hard \
-  -mfpu=fpv5-sp-d16 \
-  -DCFG_TUSB_MCU=OPT_MCU_LPC55XX \
-  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' \
-  -DBOARD_DEVICE_RHPORT_NUM=$(PORT)
-
-ifeq ($(PORT), 1)
-  $(info "PORT1 High Speed")
-  CFLAGS += -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED
-
-  # LPC55 Highspeed Port1 can only write to USB_SRAM region
-  CFLAGS += -DCFG_TUSB_MEM_SECTION='__attribute__((section("m_usb_global")))'
-else
-  $(info "PORT0 Full Speed")
-endif
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=float-equal
-
-MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT)
-
-# All source paths should be relative to the top level.
-LD_FILE ?= $(MCU_DIR)/gcc/$(MCU_CORE)_flash.ld
-
-SRC_C += \
-	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
-	$(MCU_DIR)/system_$(MCU_CORE).c \
-	$(MCU_DIR)/drivers/fsl_clock.c \
-	$(MCU_DIR)/drivers/fsl_power.c \
-	$(MCU_DIR)/drivers/fsl_reset.c \
-	$(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \
-	$(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \
-	$(SDK_DIR)/drivers/flexcomm/fsl_usart.c \
-	lib/sct_neopixel/sct_neopixel.c
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/lib/sct_neopixel \
-	$(TOP)/$(MCU_DIR)/../../CMSIS/Include \
-	$(TOP)/$(MCU_DIR) \
-	$(TOP)/$(MCU_DIR)/drivers \
-	$(TOP)/$(SDK_DIR)/drivers/common \
-	$(TOP)/$(SDK_DIR)/drivers/flexcomm \
-	$(TOP)/$(SDK_DIR)/drivers/lpc_iocon \
-	$(TOP)/$(SDK_DIR)/drivers/lpc_gpio \
-	$(TOP)/$(SDK_DIR)/drivers/sctimer
-
-SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_CORE).S
-
-LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower_hardabi.a
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM33_NTZ/non_secure
diff --git a/tinyusb/hw/bsp/lpcxpresso11u37/board.mk b/tinyusb/hw/bsp/lpcxpresso11u37/board.mk
deleted file mode 100755
index 8fcda51e..00000000
--- a/tinyusb/hw/bsp/lpcxpresso11u37/board.mk
+++ /dev/null
@@ -1,45 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0 \
-  -nostdlib \
-  -DCORE_M0 \
-  -D__USE_LPCOPEN \
-  -DCFG_EXAMPLE_MSC_READONLY \
-  -DCFG_TUSB_MCU=OPT_MCU_LPC11UXX \
-  -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
-  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' 
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter
-
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc11uxx/lpc_chip_11uxx
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc11u37.ld
-
-SRC_C += \
-	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
-	$(MCU_DIR)/../gcc/cr_startup_lpc11xx.c \
-	$(MCU_DIR)/src/chip_11xx.c \
-	$(MCU_DIR)/src/clock_11xx.c \
-	$(MCU_DIR)/src/gpio_11xx_1.c \
-	$(MCU_DIR)/src/iocon_11xx.c \
-	$(MCU_DIR)/src/sysctl_11xx.c \
-	$(MCU_DIR)/src/sysinit_11xx.c
-
-INC += \
-	$(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
-
-# For flash-jlink target
-JLINK_DEVICE = LPC11U37/401
-
-# flash using pyocd 
-flash: $(BUILD)/$(PROJECT).hex
-	pyocd flash -t lpc11u37 $<
diff --git a/tinyusb/hw/bsp/lpcxpresso11u37/lpc11u37.ld b/tinyusb/hw/bsp/lpcxpresso11u37/lpc11u37.ld
deleted file mode 100755
index 6a2dfb7f..00000000
--- a/tinyusb/hw/bsp/lpcxpresso11u37/lpc11u37.ld
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * GENERATED FILE - DO NOT EDIT
- * Copyright (c) 2008-2013 Code Red Technologies Ltd,
- * Copyright 2015, 2018-2019 NXP
- * (c) NXP Semiconductors 2013-2019
- * Generated linker script file for LPC11U37/401
- * Created from linkscript.ldt by FMCreateLinkLibraries
- * Using Freemarker v2.3.23
- * MCUXpresso IDE v11.0.0 [Build 2516] [2019-06-05] on Sep 6, 2019 12:16:06 PM
- */
-
-MEMORY
-{
-  /* Define each memory region */
-  MFlash128 (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K bytes (alias Flash) */  
-  RamLoc8 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 8K bytes (alias RAM) */  
-  RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */  
-}
-
-  /* Define a symbol for the top of each memory region */
-  __base_MFlash128 = 0x0  ; /* MFlash128 */  
-  __base_Flash = 0x0 ; /* Flash */  
-  __top_MFlash128 = 0x0 + 0x20000 ; /* 128K bytes */  
-  __top_Flash = 0x0 + 0x20000 ; /* 128K bytes */  
-  __base_RamLoc8 = 0x10000000  ; /* RamLoc8 */  
-  __base_RAM = 0x10000000 ; /* RAM */  
-  __top_RamLoc8 = 0x10000000 + 0x2000 ; /* 8K bytes */  
-  __top_RAM = 0x10000000 + 0x2000 ; /* 8K bytes */  
-  __base_RamUsb2 = 0x20004000  ; /* RamUsb2 */  
-  __base_RAM2 = 0x20004000 ; /* RAM2 */  
-  __top_RamUsb2 = 0x20004000 + 0x800 ; /* 2K bytes */  
-  __top_RAM2 = 0x20004000 + 0x800 ; /* 2K bytes */  
-
-
-ENTRY(ResetISR)
-
-SECTIONS
-{
-     /* MAIN TEXT SECTION */
-    .text : ALIGN(4)
-    {
-        FILL(0xff)
-        __vectors_start__ = ABSOLUTE(.) ;
-        KEEP(*(.isr_vector))
-        /* Global Section Table */
-        . = ALIGN(4) ;
-        __section_table_start = .;
-        __data_section_table = .;
-        LONG(LOADADDR(.data));
-        LONG(    ADDR(.data));
-        LONG(  SIZEOF(.data));
-        LONG(LOADADDR(.data_RAM2));
-        LONG(    ADDR(.data_RAM2));
-        LONG(  SIZEOF(.data_RAM2));
-        __data_section_table_end = .;
-        __bss_section_table = .;
-        LONG(    ADDR(.bss));
-        LONG(  SIZEOF(.bss));
-        LONG(    ADDR(.bss_RAM2));
-        LONG(  SIZEOF(.bss_RAM2));
-        __bss_section_table_end = .;
-        __section_table_end = . ;
-        /* End of Global Section Table */
-
-        *(.after_vectors*)
-
-    } > MFlash128
-
-    .text : ALIGN(4)
-    {
-       *(.text*)
-       *(.rodata .rodata.* .constdata .constdata.*)
-       . = ALIGN(4);
-    } > MFlash128
-    /*
-     * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
-     */
-    .ARM.extab : ALIGN(4) 
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > MFlash128
-
-    __exidx_start = .;
-
-    .ARM.exidx : ALIGN(4)
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > MFlash128
-    __exidx_end = .;
- 
-    _etext = .;
-        
-    /* DATA section for RamUsb2 */
-
-    .data_RAM2 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM2 = .) ;
-        *(.ramfunc.$RAM2)
-        *(.ramfunc.$RamUsb2)
-        *(.data.$RAM2)
-        *(.data.$RamUsb2)
-        *(.data.$RAM2.*)
-        *(.data.$RamUsb2.*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM2 = .) ;
-     } > RamUsb2 AT>MFlash128
-    /* MAIN DATA SECTION */
-    .uninit_RESERVED (NOLOAD) :
-    {
-        . = ALIGN(4) ;
-        KEEP(*(.bss.$RESERVED*))
-       . = ALIGN(4) ;
-        _end_uninit_RESERVED = .;
-    } > RamLoc8
-
-    /* Main DATA section (RamLoc8) */
-    .data : ALIGN(4)
-    {
-       FILL(0xff)
-       _data = . ;
-       *(vtable)
-       *(.ramfunc*)
-       *(.data*)
-       . = ALIGN(4) ;
-       _edata = . ;
-    } > RamLoc8 AT>MFlash128
-
-    /* BSS section for RamUsb2 */
-    .bss_RAM2 :
-    {
-       . = ALIGN(4) ;
-       PROVIDE(__start_bss_RAM2 = .) ;
-       *(.bss.$RAM2)
-       *(.bss.$RamUsb2)
-       *(.bss.$RAM2.*)
-       *(.bss.$RamUsb2.*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM2 = .) ;
-    } > RamUsb2
-
-    /* MAIN BSS SECTION */
-    .bss :
-    {
-        . = ALIGN(4) ;
-        _bss = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4) ;
-        _ebss = .;
-        PROVIDE(end = .);
-    } > RamLoc8
-
-    /* NOINIT section for RamUsb2 */
-    .noinit_RAM2 (NOLOAD) :
-    {
-       . = ALIGN(4) ;
-       *(.noinit.$RAM2)
-       *(.noinit.$RamUsb2)
-       *(.noinit.$RAM2.*)
-       *(.noinit.$RamUsb2.*)
-       . = ALIGN(4) ;
-    } > RamUsb2
-
-    /* DEFAULT NOINIT SECTION */
-    .noinit (NOLOAD):
-    {
-         . = ALIGN(4) ;
-        _noinit = .;
-        *(.noinit*)
-         . = ALIGN(4) ;
-        _end_noinit = .;
-    } > RamLoc8
-    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
-    PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc8 - 0);
-
-    /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (( DEFINED(NMI_Handler) ? NMI_Handler : M0_NMI_Handler ) + 1) 
-                                         + (( DEFINED(HardFault_Handler) ? HardFault_Handler : M0_HardFault_Handler ) + 1) 
-                                         )
-           );
-
-    /* Provide basic symbols giving location and size of main text
-     * block, including initial values of RW data sections. Note that
-     * these will need extending to give a complete picture with
-     * complex images (e.g multiple Flash banks).
-     */
-    _image_start = LOADADDR(.text);
-    _image_end = LOADADDR(.data) + SIZEOF(.data);
-    _image_size = _image_end - _image_start;
-}
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c b/tinyusb/hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c
deleted file mode 100755
index 11f1797a..00000000
--- a/tinyusb/hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "chip.h"
-#include "../board.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//---------------------------------------------------------------- ----+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-#define LED_PORT              1
-#define LED_PIN               24
-#define LED_STATE_ON          0
-
-// Wake up Switch
-#define BUTTON_PORT           0
-#define BUTTON_PIN            16
-#define BUTTON_STATE_ACTIVE   0
-
-/* System oscillator rate and RTC oscillator rate */
-const uint32_t OscRateIn = 12000000;
-const uint32_t ExtRateIn = 0;
-
-/* Pin muxing table, only items that need changing from their default pin
-   state are in this table. Not every pin is mapped. */
-/* IOCON pin definitions for pin muxing */
-typedef struct {
-	uint32_t port : 8;			/* Pin port */
-	uint32_t pin : 8;			/* Pin number */
-	uint32_t modefunc : 16;		/* Function and mode */
-} PINMUX_GRP_T;
-
-static const PINMUX_GRP_T pinmuxing[] =
-{
-  {0,  3, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // USB VBUS
-  {0,  6, (IOCON_FUNC1 | IOCON_MODE_INACT)},		/* PIO0_6 used for USB_CONNECT */
-
-  {0, 18, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 RX
-  {0, 19, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 TX
-};
-
-/* Setup system clocking */
-static void SystemSetupClocking(void)
-{
-	volatile int i;
-
-	/* Powerup main oscillator */
-	Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSOSC_PD);
-
-	/* Wait 200us for OSC to be stablized, no status
-	   indication, dummy wait. */
-	for (i = 0; i < 0x100; i++) {}
-
-	/* Set system PLL input to main oscillator */
-	Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
-
-	/* Power down PLL to change the PLL divider ratio */
-	Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
-
-	/* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 4 = 48MHz
-	   MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
-	   FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
-	   FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
-	Chip_Clock_SetupSystemPLL(3, 1);
-
-	/* Powerup system PLL */
-	Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
-
-	/* Wait for PLL to lock */
-	while (!Chip_Clock_IsSystemPLLLocked()) {}
-
-	/* Set system clock divider to 1 */
-	Chip_Clock_SetSysClockDiv(1);
-
-	/* Setup FLASH access to 3 clocks */
-	Chip_FMC_SetFLASHAccess(FLASHTIM_50MHZ_CPU);
-
-	/* Set main clock source to the system PLL. This will drive 48MHz
-	   for the main clock and 48MHz for the system clock */
-	Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
-
-	/* Set USB PLL input to main oscillator */
-	Chip_Clock_SetUSBPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
-	/* Setup USB PLL  (FCLKIN = 12MHz) * 4 = 48MHz
-	   MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
-	   FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
-	   FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
-	Chip_Clock_SetupUSBPLL(3, 1);
-
-	/* Powerup USB PLL */
-	Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_USBPLL_PD);
-
-	/* Wait for PLL to lock */
-	while (!Chip_Clock_IsUSBPLLLocked()) {}
-}
-
-// Invoked by startup code
-void SystemInit(void)
-{
-  SystemSetupClocking();
-  Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_RAM1);
-
-  /* Enable IOCON clock */
-  Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
-  for (uint32_t i = 0; i < (sizeof(pinmuxing) / sizeof(PINMUX_GRP_T)); i++)
-  {
-		Chip_IOCON_PinMuxSet(LPC_IOCON, pinmuxing[i].port, pinmuxing[i].pin, pinmuxing[i].modefunc);
-	}
-}
-
-void board_init(void)
-{
-  SystemCoreClockUpdate();
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  Chip_GPIO_Init(LPC_GPIO);
-
-  // LED
-  Chip_GPIO_SetPinDIROutput(LPC_GPIO, LED_PORT, LED_PIN);
-
-  // Button
-  Chip_GPIO_SetPinDIRInput(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
-
-  // USB: Setup PLL clock, and power
-	/* enable USB main clock */
-	Chip_Clock_SetUSBClockSource(SYSCTL_USBCLKSRC_PLLOUT, 1);
-	/* Enable AHB clock to the USB block and USB RAM. */
-	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_USB);
-	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_USBRAM);
-	/* power UP USB Phy */
-	Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_USBPAD_PD);
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/tinyusb/hw/bsp/lpcxpresso11u68/board.mk b/tinyusb/hw/bsp/lpcxpresso11u68/board.mk
deleted file mode 100755
index 922414f8..00000000
--- a/tinyusb/hw/bsp/lpcxpresso11u68/board.mk
+++ /dev/null
@@ -1,42 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
-  -nostdlib \
-  -DCORE_M0PLUS \
-  -D__VTOR_PRESENT=0 \
-  -D__USE_LPCOPEN \
-  -DCFG_TUSB_MCU=OPT_MCU_LPC11UXX \
-  -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM3")))' \
-  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' 
-
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc11u6x/lpc_chip_11u6x
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc11u68.ld
-
-SRC_C += \
-	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
-	$(MCU_DIR)/../gcc/cr_startup_lpc11u6x.c \
-	$(MCU_DIR)/src/chip_11u6x.c \
-	$(MCU_DIR)/src/clock_11u6x.c \
-	$(MCU_DIR)/src/gpio_11u6x.c \
-	$(MCU_DIR)/src/iocon_11u6x.c \
-	$(MCU_DIR)/src/syscon_11u6x.c \
-	$(MCU_DIR)/src/sysinit_11u6x.c
-
-INC += \
-	$(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
-
-# For flash-jlink target
-JLINK_DEVICE = LPC11U68
-
-# flash using pyocd 
-flash: $(BUILD)/$(PROJECT).hex
-	pyocd flash -t lpc11u68 $<
diff --git a/tinyusb/hw/bsp/lpcxpresso11u68/lpc11u68.ld b/tinyusb/hw/bsp/lpcxpresso11u68/lpc11u68.ld
deleted file mode 100755
index 56d9e4b8..00000000
--- a/tinyusb/hw/bsp/lpcxpresso11u68/lpc11u68.ld
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * GENERATED FILE - DO NOT EDIT
- * (c) Code Red Technologies Ltd, 2008-2013
- * (c) NXP Semiconductors 2013-2019
- * Generated linker script file for LPC11U68
- * Created from linkscript.ldt by FMCreateLinkLibraries
- * Using Freemarker v2.3.23
- * MCUXpresso IDE v10.2.1 [Build 795] [2018-07-25] on May 14, 2019 4:55:54 PM
- */
-
-MEMORY
-{
-  /* Define each memory region */
-  MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes (alias Flash) */  
-  Ram0_32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */  
-  Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */  
-  Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM3) */  
-}
-
-  /* Define a symbol for the top of each memory region */
-  __base_MFlash256 = 0x0  ; /* MFlash256 */  
-  __base_Flash = 0x0 ; /* Flash */  
-  __top_MFlash256 = 0x0 + 0x40000 ; /* 256K bytes */  
-  __top_Flash = 0x0 + 0x40000 ; /* 256K bytes */  
-  __base_Ram0_32 = 0x10000000  ; /* Ram0_32 */  
-  __base_RAM = 0x10000000 ; /* RAM */  
-  __top_Ram0_32 = 0x10000000 + 0x8000 ; /* 32K bytes */  
-  __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */  
-  __base_Ram1_2 = 0x20000000  ; /* Ram1_2 */  
-  __base_RAM2 = 0x20000000 ; /* RAM2 */  
-  __top_Ram1_2 = 0x20000000 + 0x800 ; /* 2K bytes */  
-  __top_RAM2 = 0x20000000 + 0x800 ; /* 2K bytes */  
-  __base_Ram2USB_2 = 0x20004000  ; /* Ram2USB_2 */  
-  __base_RAM3 = 0x20004000 ; /* RAM3 */  
-  __top_Ram2USB_2 = 0x20004000 + 0x800 ; /* 2K bytes */  
-  __top_RAM3 = 0x20004000 + 0x800 ; /* 2K bytes */  
-
-ENTRY(ResetISR)
-
-SECTIONS
-{
-    /* MAIN TEXT SECTION */
-    .text : ALIGN(4)
-    {
-        FILL(0xff)
-        __vectors_start__ = ABSOLUTE(.) ;
-        KEEP(*(.isr_vector))
-        /* Global Section Table */
-        . = ALIGN(4) ;
-        __section_table_start = .;
-        __data_section_table = .;
-        LONG(LOADADDR(.data));
-        LONG(    ADDR(.data));
-        LONG(  SIZEOF(.data));
-        LONG(LOADADDR(.data_RAM2));
-        LONG(    ADDR(.data_RAM2));
-        LONG(  SIZEOF(.data_RAM2));
-        LONG(LOADADDR(.data_RAM3));
-        LONG(    ADDR(.data_RAM3));
-        LONG(  SIZEOF(.data_RAM3));
-        __data_section_table_end = .;
-        __bss_section_table = .;
-        LONG(    ADDR(.bss));
-        LONG(  SIZEOF(.bss));
-        LONG(    ADDR(.bss_RAM2));
-        LONG(  SIZEOF(.bss_RAM2));
-        LONG(    ADDR(.bss_RAM3));
-        LONG(  SIZEOF(.bss_RAM3));
-        __bss_section_table_end = .;
-        __section_table_end = . ;
-        /* End of Global Section Table */
-
-        *(.after_vectors*)
-
-    } > MFlash256
-
-    .text : ALIGN(4)
-    {
-       *(.text*)
-       *(.rodata .rodata.* .constdata .constdata.*)
-       . = ALIGN(4);
-    } > MFlash256
-    /*
-     * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
-     */
-    .ARM.extab : ALIGN(4) 
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > MFlash256
-
-    __exidx_start = .;
-
-    .ARM.exidx : ALIGN(4)
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > MFlash256
-    __exidx_end = .;
-
-    _etext = .;
-        
-    /* possible MTB section for Ram1_2 */
-    .mtb_buffer_RAM2 (NOLOAD) :
-    {
-        KEEP(*(.mtb.$RAM2*))
-        KEEP(*(.mtb.$Ram1_2*))
-    } > Ram1_2
-
-    /* DATA section for Ram1_2 */
-
-    .data_RAM2 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM2 = .) ;
-        *(.ramfunc.$RAM2)
-        *(.ramfunc.$Ram1_2)
-        *(.data.$RAM2*)
-        *(.data.$Ram1_2*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM2 = .) ;
-     } > Ram1_2 AT>MFlash256
-    /* possible MTB section for Ram2USB_2 */
-    .mtb_buffer_RAM3 (NOLOAD) :
-    {
-        KEEP(*(.mtb.$RAM3*))
-        KEEP(*(.mtb.$Ram2USB_2*))
-    } > Ram2USB_2
-
-    /* DATA section for Ram2USB_2 */
-
-    .data_RAM3 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM3 = .) ;
-        *(.ramfunc.$RAM3)
-        *(.ramfunc.$Ram2USB_2)
-        *(.data.$RAM3*)
-        *(.data.$Ram2USB_2*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM3 = .) ;
-     } > Ram2USB_2 AT>MFlash256
-    /* MAIN DATA SECTION */
-        /* Default MTB section */
-        .mtb_buffer_default (NOLOAD) :
-        {
-           KEEP(*(.mtb*))
-        } > Ram0_32
-    .uninit_RESERVED : ALIGN(4)
-    {
-        KEEP(*(.bss.$RESERVED*))
-        . = ALIGN(4) ;
-        _end_uninit_RESERVED = .;
-    } > Ram0_32
-
-    /* Main DATA section (Ram0_32) */
-    .data : ALIGN(4)
-    {
-       FILL(0xff)
-       _data = . ;
-       *(vtable)
-       *(.ramfunc*)
-       *(.data*)
-       . = ALIGN(4) ;
-       _edata = . ;
-    } > Ram0_32 AT>MFlash256
-
-    /* BSS section for Ram1_2 */
-    .bss_RAM2 : ALIGN(4)
-    {
-       PROVIDE(__start_bss_RAM2 = .) ;
-       *(.bss.$RAM2*)
-       *(.bss.$Ram1_2*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM2 = .) ;
-    } > Ram1_2 
-
-    /* BSS section for Ram2USB_2 */
-    .bss_RAM3 : ALIGN(4)
-    {
-       PROVIDE(__start_bss_RAM3 = .) ;
-       *(.bss.$RAM3*)
-       *(.bss.$Ram2USB_2*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM3 = .) ;
-    } > Ram2USB_2 
-
-    /* MAIN BSS SECTION */
-    .bss : ALIGN(4)
-    {
-        _bss = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4) ;
-        _ebss = .;
-        PROVIDE(end = .);
-    } > Ram0_32
-
-    /* NOINIT section for Ram1_2 */
-    .noinit_RAM2 (NOLOAD) : ALIGN(4)
-    {
-       *(.noinit.$RAM2*)
-       *(.noinit.$Ram1_2*)
-       . = ALIGN(4) ;
-    } > Ram1_2 
-
-    /* NOINIT section for Ram2USB_2 */
-    .noinit_RAM3 (NOLOAD) : ALIGN(4)
-    {
-       *(.noinit.$RAM3*)
-       *(.noinit.$Ram2USB_2*)
-       . = ALIGN(4) ;
-    } > Ram2USB_2 
-
-    /* DEFAULT NOINIT SECTION */
-    .noinit (NOLOAD): ALIGN(4)
-    {
-        _noinit = .;
-        *(.noinit*) 
-         . = ALIGN(4) ;
-        _end_noinit = .;
-    } > Ram0_32
-    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
-    PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_Ram0_32 - 0);
-
-    /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (( DEFINED(NMI_Handler) ? NMI_Handler : M0_NMI_Handler ) + 1) 
-                                         + (( DEFINED(HardFault_Handler) ? HardFault_Handler : M0_HardFault_Handler ) + 1) 
-                                         )
-           );
-
-    /* Provide basic symbols giving location and size of main text
-     * block, including initial values of RW data sections. Note that
-     * these will need extending to give a complete picture with
-     * complex images (e.g multiple Flash banks).
-     */
-    _image_start = LOADADDR(.text);
-    _image_end = LOADADDR(.data) + SIZEOF(.data);
-    _image_size = _image_end - _image_start;
-}
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/lpcxpresso11u68/lpcxpresso11u68.c b/tinyusb/hw/bsp/lpcxpresso11u68/lpcxpresso11u68.c
deleted file mode 100755
index e33a5c6e..00000000
--- a/tinyusb/hw/bsp/lpcxpresso11u68/lpcxpresso11u68.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "chip.h"
-#include "../board.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-#define LED_PORT              2
-#define LED_PIN               17
-#define LED_STATE_ON          0
-
-// Wake up Switch
-#define BUTTON_PORT           0
-#define BUTTON_PIN            16
-#define BUTTON_STATE_ACTIVE   0
-
-/* System oscillator rate and RTC oscillator rate */
-const uint32_t OscRateIn = 12000000;
-const uint32_t RTCOscRateIn = 32768;
-
-/* Pin muxing table, only items that need changing from their default pin
-   state are in this table. Not every pin is mapped. */
-static const PINMUX_GRP_T pinmuxing[] =
-{
-  {0, 3,  (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // USB VBUS
-  {0, 18, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 RX
-  {0, 19, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 TX
-  {2, 0,  (IOCON_FUNC1 | IOCON_MODE_INACT)}, // XTALIN
-  {2, 1,  (IOCON_FUNC1 | IOCON_MODE_INACT)}, // XTALOUT
-};
-
-// Invoked by startup code
-void SystemInit(void)
-{
-  /* Enable IOCON clock */
-  Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
-  Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
-  Chip_SetupXtalClocking();
-}
-
-void board_init(void)
-{
-  SystemCoreClockUpdate();
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  Chip_GPIO_Init(LPC_GPIO);
-
-  // LED
-  Chip_GPIO_SetPinDIROutput(LPC_GPIO, LED_PORT, LED_PIN);
-
-  // Button
-  Chip_GPIO_SetPinDIRInput(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
-
-  // USB: Setup PLL clock, and power
-  Chip_USB_Init();
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/tinyusb/hw/bsp/lpcxpresso1347/board.mk b/tinyusb/hw/bsp/lpcxpresso1347/board.mk
deleted file mode 100755
index 0d56a33a..00000000
--- a/tinyusb/hw/bsp/lpcxpresso1347/board.mk
+++ /dev/null
@@ -1,44 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m3 \
-  -nostdlib \
-  -DCORE_M3 \
-  -D__USE_LPCOPEN \
-  -DCFG_EXAMPLE_MSC_READONLY \
-  -DCFG_TUSB_MCU=OPT_MCU_LPC13XX \
-  -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
-  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' 
-
-# startup.c and lpc_types.h cause following errors
-CFLAGS += -Wno-error=strict-prototypes
-
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc13xx/lpc_chip_13xx
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc1347.ld
-
-SRC_C += \
-	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
-	$(MCU_DIR)/../gcc/cr_startup_lpc13xx.c \
-	$(MCU_DIR)/src/chip_13xx.c \
-	$(MCU_DIR)/src/clock_13xx.c \
-	$(MCU_DIR)/src/gpio_13xx_1.c \
-	$(MCU_DIR)/src/iocon_13xx.c \
-	$(MCU_DIR)/src/sysctl_13xx.c \
-	$(MCU_DIR)/src/sysinit_13xx.c
-
-INC += \
-	$(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
-
-# For flash-jlink target
-JLINK_DEVICE = LPC1347
-
-# flash using jlink
-flash: flash-jlink
diff --git a/tinyusb/hw/bsp/lpcxpresso1347/lpc1347.ld b/tinyusb/hw/bsp/lpcxpresso1347/lpc1347.ld
deleted file mode 100755
index 42a4bb25..00000000
--- a/tinyusb/hw/bsp/lpcxpresso1347/lpc1347.ld
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- * GENERATED FILE - DO NOT EDIT
- * (c) Code Red Technologies Ltd, 2008-2013
- * (c) NXP Semiconductors 2013-2019
- * Generated linker script file for LPC1347
- * Created from linkscript.ldt by FMCreateLinkLibraries
- * Using Freemarker v2.3.23
- * MCUXpresso IDE v10.2.1 [Build 795] [2018-07-25] on May 14, 2019 6:01:58 PM
- */
-
-MEMORY
-{
-  /* Define each memory region */
-  MFlash64 (rx) : ORIGIN = 0x0, LENGTH = 0x10000 /* 64K bytes (alias Flash) */  
-  RamLoc8 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 8K bytes (alias RAM) */  
-  RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */  
-  RamPeriph2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes (alias RAM3) */  
-}
-
-  /* Define a symbol for the top of each memory region */
-  __base_MFlash64 = 0x0  ; /* MFlash64 */  
-  __base_Flash = 0x0 ; /* Flash */  
-  __top_MFlash64 = 0x0 + 0x10000 ; /* 64K bytes */  
-  __top_Flash = 0x0 + 0x10000 ; /* 64K bytes */  
-  __base_RamLoc8 = 0x10000000  ; /* RamLoc8 */  
-  __base_RAM = 0x10000000 ; /* RAM */  
-  __top_RamLoc8 = 0x10000000 + 0x2000 ; /* 8K bytes */  
-  __top_RAM = 0x10000000 + 0x2000 ; /* 8K bytes */  
-  __base_RamUsb2 = 0x20004000  ; /* RamUsb2 */  
-  __base_RAM2 = 0x20004000 ; /* RAM2 */  
-  __top_RamUsb2 = 0x20004000 + 0x800 ; /* 2K bytes */  
-  __top_RAM2 = 0x20004000 + 0x800 ; /* 2K bytes */  
-  __base_RamPeriph2 = 0x20000000  ; /* RamPeriph2 */  
-  __base_RAM3 = 0x20000000 ; /* RAM3 */  
-  __top_RamPeriph2 = 0x20000000 + 0x800 ; /* 2K bytes */  
-  __top_RAM3 = 0x20000000 + 0x800 ; /* 2K bytes */  
-
-ENTRY(ResetISR)
-
-SECTIONS
-{
-    /* MAIN TEXT SECTION */
-    .text : ALIGN(4)
-    {
-        FILL(0xff)
-        __vectors_start__ = ABSOLUTE(.) ;
-        KEEP(*(.isr_vector))
-        /* Global Section Table */
-        . = ALIGN(4) ;
-        __section_table_start = .;
-        __data_section_table = .;
-        LONG(LOADADDR(.data));
-        LONG(    ADDR(.data));
-        LONG(  SIZEOF(.data));
-        LONG(LOADADDR(.data_RAM2));
-        LONG(    ADDR(.data_RAM2));
-        LONG(  SIZEOF(.data_RAM2));
-        LONG(LOADADDR(.data_RAM3));
-        LONG(    ADDR(.data_RAM3));
-        LONG(  SIZEOF(.data_RAM3));
-        __data_section_table_end = .;
-        __bss_section_table = .;
-        LONG(    ADDR(.bss));
-        LONG(  SIZEOF(.bss));
-        LONG(    ADDR(.bss_RAM2));
-        LONG(  SIZEOF(.bss_RAM2));
-        LONG(    ADDR(.bss_RAM3));
-        LONG(  SIZEOF(.bss_RAM3));
-        __bss_section_table_end = .;
-        __section_table_end = . ;
-        /* End of Global Section Table */
-
-        *(.after_vectors*)
-
-    } > MFlash64
-
-    .text : ALIGN(4)
-    {
-       *(.text*)
-       *(.rodata .rodata.* .constdata .constdata.*)
-       . = ALIGN(4);
-    } > MFlash64
-    /*
-     * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
-     */
-    .ARM.extab : ALIGN(4) 
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > MFlash64
-
-    __exidx_start = .;
-
-    .ARM.exidx : ALIGN(4)
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > MFlash64
-    __exidx_end = .;
-
-    _etext = .;
-        
-    /* DATA section for RamUsb2 */
-
-    .data_RAM2 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM2 = .) ;
-        *(.ramfunc.$RAM2)
-        *(.ramfunc.$RamUsb2)
-        *(.data.$RAM2*)
-        *(.data.$RamUsb2*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM2 = .) ;
-     } > RamUsb2 AT>MFlash64
-    /* DATA section for RamPeriph2 */
-
-    .data_RAM3 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM3 = .) ;
-        *(.ramfunc.$RAM3)
-        *(.ramfunc.$RamPeriph2)
-        *(.data.$RAM3*)
-        *(.data.$RamPeriph2*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM3 = .) ;
-     } > RamPeriph2 AT>MFlash64
-    /* MAIN DATA SECTION */
-    .uninit_RESERVED : ALIGN(4)
-    {
-        KEEP(*(.bss.$RESERVED*))
-        . = ALIGN(4) ;
-        _end_uninit_RESERVED = .;
-    } > RamLoc8
-
-    /* Main DATA section (RamLoc8) */
-    .data : ALIGN(4)
-    {
-       FILL(0xff)
-       _data = . ;
-       *(vtable)
-       *(.ramfunc*)
-       *(.data*)
-       . = ALIGN(4) ;
-       _edata = . ;
-    } > RamLoc8 AT>MFlash64
-
-    /* BSS section for RamUsb2 */
-    .bss_RAM2 : ALIGN(4)
-    {
-       PROVIDE(__start_bss_RAM2 = .) ;
-       *(.bss.$RAM2*)
-       *(.bss.$RamUsb2*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM2 = .) ;
-    } > RamUsb2 
-
-    /* BSS section for RamPeriph2 */
-    .bss_RAM3 : ALIGN(4)
-    {
-       PROVIDE(__start_bss_RAM3 = .) ;
-       *(.bss.$RAM3*)
-       *(.bss.$RamPeriph2*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM3 = .) ;
-    } > RamPeriph2 
-
-    /* MAIN BSS SECTION */
-    .bss : ALIGN(4)
-    {
-        _bss = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4) ;
-        _ebss = .;
-        PROVIDE(end = .);
-    } > RamLoc8
-
-    /* NOINIT section for RamUsb2 */
-    .noinit_RAM2 (NOLOAD) : ALIGN(4)
-    {
-       *(.noinit.$RAM2*)
-       *(.noinit.$RamUsb2*)
-       . = ALIGN(4) ;
-    } > RamUsb2 
-
-    /* NOINIT section for RamPeriph2 */
-    .noinit_RAM3 (NOLOAD) : ALIGN(4)
-    {
-       *(.noinit.$RAM3*)
-       *(.noinit.$RamPeriph2*)
-       . = ALIGN(4) ;
-    } > RamPeriph2 
-
-    /* DEFAULT NOINIT SECTION */
-    .noinit (NOLOAD): ALIGN(4)
-    {
-        _noinit = .;
-        *(.noinit*) 
-         . = ALIGN(4) ;
-        _end_noinit = .;
-    } > RamLoc8
-    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
-    PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc8 - 0);
-
-    /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (NMI_Handler + 1) 
-                                         + (HardFault_Handler + 1) 
-                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
-                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
-                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
-                                         ) );
-
-    /* Provide basic symbols giving location and size of main text
-     * block, including initial values of RW data sections. Note that
-     * these will need extending to give a complete picture with
-     * complex images (e.g multiple Flash banks).
-     */
-    _image_start = LOADADDR(.text);
-    _image_end = LOADADDR(.data) + SIZEOF(.data);
-    _image_size = _image_end - _image_start;
-}
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/lpcxpresso1347/lpcxpresso1347.c b/tinyusb/hw/bsp/lpcxpresso1347/lpcxpresso1347.c
deleted file mode 100755
index a9a67ae3..00000000
--- a/tinyusb/hw/bsp/lpcxpresso1347/lpcxpresso1347.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "chip.h"
-#include "../board.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-#define LED_PORT      0
-#define LED_PIN       7
-
-// Joytick Down if connected to LPCXpresso Base board
-#define BUTTON_PORT   1
-#define BUTTON_PIN    20
-
-//static const struct {
-//  uint8_t port;
-//  uint8_t pin;
-//} buttons[] =
-//{
-//    {1, 22 }, // Joystick up
-//    {1, 20 }, // Joystick down
-//    {1, 23 }, // Joystick left
-//    {1, 21 }, // Joystick right
-//    {1, 19 }, // Joystick press
-//    {0, 1  }, // SW3
-//};
-
-/* System oscillator rate and RTC oscillator rate */
-const uint32_t OscRateIn = 12000000;
-const uint32_t ExtRateIn = 0;
-
-/* Pin muxing table, only items that need changing from their default pin
-   state are in this table. */
-static const PINMUX_GRP_T pinmuxing[] = 
-{
-  {0,  1,  (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},	/* PIO0_1 used for CLKOUT */
-  {0,  2,  (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_PULLUP)},	/* PIO0_2 used for SSEL */
-  {0,  3,  (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},	/* PIO0_3 used for USB_VBUS */
-  {0,  6,  (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},	/* PIO0_6 used for USB_CONNECT */
-  {0,  8,  (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},	/* PIO0_8 used for MISO0 */
-  {0,  9,  (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},	/* PIO0_9 used for MOSI0 */
-  {0,  11, (IOCON_FUNC2 | IOCON_ADMODE_EN      | IOCON_FILT_DIS)},	/* PIO0_11 used for AD0 */
-  {0,  18, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},	/* PIO0_18 used for RXD */
-  {0,  19, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},	/* PIO0_19 used for TXD */
-  {1,  29, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},	/* PIO1_29 used for SCK0 */
-};
-
-// Invoked by startup code
-void SystemInit(void)
-{
-  /* Enable IOCON clock */
-  Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
-  Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
-  Chip_SetupXtalClocking();
-}
-
-void board_init(void)
-{
-  SystemCoreClockUpdate();
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  Chip_GPIO_Init(LPC_GPIO_PORT);
-
-  // LED
-  Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, LED_PORT, LED_PIN);
-
-  // Button
-  Chip_GPIO_SetPinDIRInput(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN);
-
-  // USB: Setup PLL clock, and power
-  Chip_USB_Init();
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-
-void board_led_write(bool state)
-{
-  Chip_GPIO_SetPinState(LPC_GPIO_PORT, LED_PORT, LED_PIN, state);
-}
-
-uint32_t board_button_read(void)
-{
-  // active low
-  return Chip_GPIO_GetPinState(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN) ? 0 : 1;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
diff --git a/tinyusb/hw/bsp/lpcxpresso1769/board.mk b/tinyusb/hw/bsp/lpcxpresso1769/board.mk
deleted file mode 100755
index b69be39b..00000000
--- a/tinyusb/hw/bsp/lpcxpresso1769/board.mk
+++ /dev/null
@@ -1,43 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m3 \
-  -nostdlib \
-  -DCORE_M3 \
-  -D__USE_LPCOPEN \
-  -DCFG_TUSB_MCU=OPT_MCU_LPC175X_6X \
-  -DRTC_EV_SUPPORT=0
-
-# lpc_types.h cause following errors
-CFLAGS += -Wno-error=strict-prototypes
-
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc1769.ld
-
-SRC_C += \
-	src/portable/nxp/lpc17_40/dcd_lpc17_40.c \
-	$(MCU_DIR)/../gcc/cr_startup_lpc175x_6x.c \
-	$(MCU_DIR)/src/chip_17xx_40xx.c \
-	$(MCU_DIR)/src/clock_17xx_40xx.c \
-	$(MCU_DIR)/src/gpio_17xx_40xx.c \
-	$(MCU_DIR)/src/iocon_17xx_40xx.c \
-	$(MCU_DIR)/src/sysctl_17xx_40xx.c \
-	$(MCU_DIR)/src/sysinit_17xx_40xx.c \
-	$(MCU_DIR)/src/uart_17xx_40xx.c
-
-INC += \
-	$(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
-
-# For flash-jlink target
-JLINK_DEVICE = LPC1769
-
-# flash using jlink
-flash: flash-jlink
diff --git a/tinyusb/hw/bsp/lpcxpresso1769/lpc1769.ld b/tinyusb/hw/bsp/lpcxpresso1769/lpc1769.ld
deleted file mode 100755
index d1c83d8e..00000000
--- a/tinyusb/hw/bsp/lpcxpresso1769/lpc1769.ld
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * GENERATED FILE - DO NOT EDIT
- * (c) Code Red Technologies Ltd, 2008-2013
- * (c) NXP Semiconductors 2013-2019
- * Generated linker script file for LPC1769
- * Created from linkscript.ldt by FMCreateLinkLibraries
- * Using Freemarker v2.3.23
- * MCUXpresso IDE v10.2.1 [Build 795] [2018-07-25] on May 14, 2019 6:39:29 PM
- */
-
-MEMORY
-{
-  /* Define each memory region */
-  MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */  
-  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */  
-  RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */  
-}
-
-  /* Define a symbol for the top of each memory region */
-  __base_MFlash512 = 0x0  ; /* MFlash512 */  
-  __base_Flash = 0x0 ; /* Flash */  
-  __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */  
-  __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */  
-  __base_RamLoc32 = 0x10000000  ; /* RamLoc32 */  
-  __base_RAM = 0x10000000 ; /* RAM */  
-  __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */  
-  __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */  
-  __base_RamAHB32 = 0x2007c000  ; /* RamAHB32 */  
-  __base_RAM2 = 0x2007c000 ; /* RAM2 */  
-  __top_RamAHB32 = 0x2007c000 + 0x8000 ; /* 32K bytes */  
-  __top_RAM2 = 0x2007c000 + 0x8000 ; /* 32K bytes */  
-
-ENTRY(ResetISR)
-
-SECTIONS
-{
-    /* MAIN TEXT SECTION */
-    .text : ALIGN(4)
-    {
-        FILL(0xff)
-        __vectors_start__ = ABSOLUTE(.) ;
-        KEEP(*(.isr_vector))
-        /* Global Section Table */
-        . = ALIGN(4) ;
-        __section_table_start = .;
-        __data_section_table = .;
-        LONG(LOADADDR(.data));
-        LONG(    ADDR(.data));
-        LONG(  SIZEOF(.data));
-        LONG(LOADADDR(.data_RAM2));
-        LONG(    ADDR(.data_RAM2));
-        LONG(  SIZEOF(.data_RAM2));
-        __data_section_table_end = .;
-        __bss_section_table = .;
-        LONG(    ADDR(.bss));
-        LONG(  SIZEOF(.bss));
-        LONG(    ADDR(.bss_RAM2));
-        LONG(  SIZEOF(.bss_RAM2));
-        __bss_section_table_end = .;
-        __section_table_end = . ;
-        /* End of Global Section Table */
-
-        *(.after_vectors*)
-
-    } > MFlash512
-
-    .text : ALIGN(4)
-    {
-       *(.text*)
-       *(.rodata .rodata.* .constdata .constdata.*)
-       . = ALIGN(4);
-    } > MFlash512
-    /*
-     * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
-     */
-    .ARM.extab : ALIGN(4) 
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > MFlash512
-
-    __exidx_start = .;
-
-    .ARM.exidx : ALIGN(4)
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > MFlash512
-    __exidx_end = .;
-
-    _etext = .;
-        
-    /* DATA section for RamAHB32 */
-
-    .data_RAM2 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM2 = .) ;
-        *(.ramfunc.$RAM2)
-        *(.ramfunc.$RamAHB32)
-        *(.data.$RAM2*)
-        *(.data.$RamAHB32*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM2 = .) ;
-     } > RamAHB32 AT>MFlash512
-    /* MAIN DATA SECTION */
-    .uninit_RESERVED : ALIGN(4)
-    {
-        KEEP(*(.bss.$RESERVED*))
-        . = ALIGN(4) ;
-        _end_uninit_RESERVED = .;
-    } > RamLoc32
-
-    /* Main DATA section (RamLoc32) */
-    .data : ALIGN(4)
-    {
-       FILL(0xff)
-       _data = . ;
-       *(vtable)
-       *(.ramfunc*)
-       *(.data*)
-       . = ALIGN(4) ;
-       _edata = . ;
-    } > RamLoc32 AT>MFlash512
-
-    /* BSS section for RamAHB32 */
-    .bss_RAM2 : ALIGN(4)
-    {
-       PROVIDE(__start_bss_RAM2 = .) ;
-       *(.bss.$RAM2*)
-       *(.bss.$RamAHB32*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM2 = .) ;
-    } > RamAHB32 
-
-    /* MAIN BSS SECTION */
-    .bss : ALIGN(4)
-    {
-        _bss = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4) ;
-        _ebss = .;
-        PROVIDE(end = .);
-    } > RamLoc32
-
-    /* NOINIT section for RamAHB32 */
-    .noinit_RAM2 (NOLOAD) : ALIGN(4)
-    {
-       *(.noinit.$RAM2*)
-       *(.noinit.$RamAHB32*)
-       . = ALIGN(4) ;
-    } > RamAHB32 
-
-    /* DEFAULT NOINIT SECTION */
-    .noinit (NOLOAD): ALIGN(4)
-    {
-        _noinit = .;
-        *(.noinit*) 
-         . = ALIGN(4) ;
-        _end_noinit = .;
-    } > RamLoc32
-    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
-    PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
-
-    /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (NMI_Handler + 1) 
-                                         + (HardFault_Handler + 1) 
-                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
-                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
-                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
-                                         ) );
-
-    /* Provide basic symbols giving location and size of main text
-     * block, including initial values of RW data sections. Note that
-     * these will need extending to give a complete picture with
-     * complex images (e.g multiple Flash banks).
-     */
-    _image_start = LOADADDR(.text);
-    _image_end = LOADADDR(.data) + SIZEOF(.data);
-    _image_size = _image_end - _image_start;
-}
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/lpcxpresso1769/lpcxpresso1769.c b/tinyusb/hw/bsp/lpcxpresso1769/lpcxpresso1769.c
deleted file mode 100755
index 101cc8a4..00000000
--- a/tinyusb/hw/bsp/lpcxpresso1769/lpcxpresso1769.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "chip.h"
-#include "../board.h"
-
-//--------------------------------------------------------------------+
-// USB Interrupt Handler
-//--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
-    tuh_int_handler(0);
-  #endif
-
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-    tud_int_handler(0);
-  #endif
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-#define LED_PORT              0
-#define LED_PIN               22
-#define LED_STATE_ON          1
-
-// JOYSTICK_DOWN if using LPCXpresso Base Board
-#define BUTTON_PORT           0
-#define BUTTON_PIN            15
-#define BUTTON_STATE_ACTIVE   0
-
-#define BOARD_UART_PORT   LPC_UART3
-
-/* System oscillator rate and RTC oscillator rate */
-const uint32_t OscRateIn = 12000000;
-const uint32_t RTCOscRateIn = 32768;
-
-/* Pin muxing configuration */
-static const PINMUX_GRP_T pinmuxing[] =
-{
-  {0,  0,   IOCON_MODE_INACT | IOCON_FUNC2},	/* TXD3 */
-  {0,  1,   IOCON_MODE_INACT | IOCON_FUNC2},	/* RXD3 */
-  {LED_PORT, LED_PIN,  IOCON_MODE_INACT | IOCON_FUNC0},	/* Led 0 */
-
-  /* Joystick buttons. */
-//  {2, 3,  IOCON_MODE_INACT | IOCON_FUNC0},	/* JOYSTICK_UP */
-  {BUTTON_PORT, BUTTON_PIN, IOCON_FUNC0 | IOCON_MODE_PULLUP},	/* JOYSTICK_DOWN */
-//  {2, 4,  IOCON_MODE_INACT | IOCON_FUNC0},	/* JOYSTICK_LEFT */
-//  {0, 16, IOCON_MODE_INACT | IOCON_FUNC0},	/* JOYSTICK_RIGHT */
-//  {0, 17, IOCON_MODE_INACT | IOCON_FUNC0},	/* JOYSTICK_PRESS */
-};
-
-static const PINMUX_GRP_T pin_usb_mux[] =
-{
-  {0, 29, IOCON_MODE_INACT | IOCON_FUNC1}, // D+
-  {0, 30, IOCON_MODE_INACT | IOCON_FUNC1}, // D-
-  {2,  9, IOCON_MODE_INACT | IOCON_FUNC1}, // Soft Connect
-
-  {1, 19, IOCON_MODE_INACT | IOCON_FUNC2}, // USB_PPWR (Host mode)
-
-  // VBUS is not connected on this board, so leave the pin at default setting.
-  /// Chip_IOCON_PinMux(LPC_IOCON, 1, 30, IOCON_MODE_INACT, IOCON_FUNC2);  // USB VBUS
-};
-
-// Invoked by startup code
-void SystemInit(void)
-{
-#ifdef __USE_LPCOPEN
-	extern void (* const g_pfnVectors[])(void);
-  unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
-	*pSCB_VTOR = (unsigned int) g_pfnVectors;
-#endif
-
-  Chip_IOCON_Init(LPC_IOCON);
-  Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
-  Chip_SetupXtalClocking();
-
-  Chip_SYSCTL_SetFLASHAccess(FLASHTIM_100MHZ_CPU);
-}
-
-void board_init(void)
-{
-  SystemCoreClockUpdate();
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  Chip_GPIO_Init(LPC_GPIO);
-
-  // LED
-  Chip_GPIO_SetPinDIROutput(LPC_GPIO, LED_PORT, LED_PIN);
-
-  // Button
-  Chip_GPIO_SetPinDIRInput(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
-
-#if 0
-  //------------- UART -------------//
-  PINSEL_CFG_Type PinCfg =
-  {
-      .Portnum   = 0,
-      .Pinnum    = 0, // TXD is P0.0
-      .Funcnum   = 2,
-      .OpenDrain = 0,
-      .Pinmode   = 0
-  };
-	PINSEL_ConfigPin(&PinCfg);
-
-	PinCfg.Portnum = 0;
-	PinCfg.Pinnum  = 1; // RXD is P0.1
-	PINSEL_ConfigPin(&PinCfg);
-
-	UART_CFG_Type UARTConfigStruct;
-  UART_ConfigStructInit(&UARTConfigStruct);
-	UARTConfigStruct.Baud_rate = CFG_BOARD_UART_BAUDRATE;
-
-	UART_Init(BOARD_UART_PORT, &UARTConfigStruct);
-	UART_TxCmd(BOARD_UART_PORT, ENABLE); // Enable UART Transmit
-#endif
-
-	//------------- USB -------------//
-  Chip_IOCON_SetPinMuxing(LPC_IOCON, pin_usb_mux, sizeof(pin_usb_mux) / sizeof(PINMUX_GRP_T));
-	Chip_USB_Init();
-
-  enum {
-    USBCLK_DEVCIE = 0x12,     // AHB + Device
-    USBCLK_HOST   = 0x19,     // AHB + Host + OTG
-//    0x1B // Host + Device + OTG + AHB
-  };
-
-  uint32_t const clk_en = TUSB_OPT_DEVICE_ENABLED ? USBCLK_DEVCIE : USBCLK_HOST;
-
-  LPC_USB->OTGClkCtrl = clk_en;
-  while ( (LPC_USB->OTGClkSt & clk_en) != clk_en );
-
-#if TUSB_OPT_HOST_ENABLED
-  // set portfunc to host !!!
-  LPC_USB->StCtrl = 0x3; // should be 1
-#endif
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-//  return UART_ReceiveByte(BOARD_UART_PORT);
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-//  UART_Send(BOARD_UART_PORT, &c, 1, BLOCKING);
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/tinyusb/hw/bsp/lpcxpresso51u68/board.mk b/tinyusb/hw/bsp/lpcxpresso51u68/board.mk
deleted file mode 100755
index 98bef675..00000000
--- a/tinyusb/hw/bsp/lpcxpresso51u68/board.mk
+++ /dev/null
@@ -1,52 +0,0 @@
-SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += $(SDK_DIR)
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
-  -DCPU_LPC51U68JBD64 \
-  -DCFG_TUSB_MCU=OPT_MCU_LPC51UXX \
-  -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data")))' \
-  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' 
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter
-
-MCU_DIR = $(SDK_DIR)/devices/LPC51U68
-
-# All source paths should be relative to the top level.
-LD_FILE = $(MCU_DIR)/gcc/LPC51U68_flash.ld
-
-SRC_C += \
-	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
-	$(MCU_DIR)/system_LPC51U68.c \
-	$(MCU_DIR)/drivers/fsl_clock.c \
-	$(MCU_DIR)/drivers/fsl_power.c \
-	$(MCU_DIR)/drivers/fsl_reset.c \
-	$(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \
-	$(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \
-	$(SDK_DIR)/drivers/flexcomm/fsl_usart.c
-
-INC += \
-	$(TOP)/$(MCU_DIR)/../../CMSIS/Include \
-	$(TOP)/$(MCU_DIR) \
-	$(TOP)/$(MCU_DIR)/drivers \
-	$(TOP)/$(SDK_DIR)/drivers/common \
-	$(TOP)/$(SDK_DIR)/drivers/flexcomm \
-	$(TOP)/$(SDK_DIR)/drivers/lpc_iocon \
-	$(TOP)/$(SDK_DIR)/drivers/lpc_gpio	
-
-SRC_S += $(MCU_DIR)/gcc/startup_LPC51U68.S
-
-LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower.a
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
-
-JLINK_DEVICE = LPC51U68
-PYOCD_TARGET = LPC51U68
-
-# flash using pyocd (51u68 is not supported yet)
-flash: flash-pyocd
diff --git a/tinyusb/hw/bsp/lpcxpresso51u68/lpcxpresso51u68.c b/tinyusb/hw/bsp/lpcxpresso51u68/lpcxpresso51u68.c
deleted file mode 100755
index 6bade774..00000000
--- a/tinyusb/hw/bsp/lpcxpresso51u68/lpcxpresso51u68.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2018, hathach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "../board.h"
-#include "fsl_device_registers.h"
-#include "fsl_gpio.h"
-#include "fsl_power.h"
-#include "fsl_iocon.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-#define LED_PORT      0
-#define LED_PIN       29
-#define LED_STATE_ON  0
-
-// WAKE button
-#define BUTTON_PORT   0
-#define BUTTON_PIN    24
-
-// IOCON pin mux
-#define IOCON_PIO_DIGITAL_EN          0x80u   /*!< Enables digital function */
-#define IOCON_PIO_FUNC1               0x01u   /*!< Selects pin function 1 */
-#define IOCON_PIO_FUNC7               0x07u   /*!< Selects pin function 7 */
-#define IOCON_PIO_INPFILT_OFF       0x0100u   /*!< Input filter disabled */
-#define IOCON_PIO_INV_DI              0x00u   /*!< Input function is not inverted */
-#define IOCON_PIO_MODE_INACT          0x00u   /*!< No addition pin function */
-#define IOCON_PIO_OPENDRAIN_DI        0x00u   /*!< Open drain is disabled */
-#define IOCON_PIO_SLEW_STANDARD       0x00u   /*!< Standard mode, output slew rate control is enabled */
-
-/****************************************************************
-name: BOARD_BootClockFROHF96M
-outputs:
-- {id: SYSTICK_clock.outFreq, value: 96 MHz}
-- {id: System_clock.outFreq, value: 96 MHz}
-settings:
-- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
-sources:
-- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
-******************************************************************/
-void BootClockFROHF96M(void)
-{
-  /*!< Set up the clock sources */
-  /*!< Set up FRO */
-  POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
-  CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
-                                             accidentally being below the voltage for current speed */
-  POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
-  CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
-
-  CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
-
-  /*!< Set up dividers */
-  CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);     /*!< Set AHBCLKDIV divider to value 1 */
-  CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 0U, true);  /*!< Reset SYSTICKCLKDIV divider counter and halt it */
-  CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U, false); /*!< Set SYSTICKCLKDIV divider to value 1 */
-
-  /*!< Set up clock selectors - Attach clocks to the peripheries */
-  CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
-  /*!< Set SystemCoreClock variable. */
-  SystemCoreClock = 96000000U;
-}
-
-void board_init(void)
-{
-  // Enable IOCON clock
-  CLOCK_EnableClock(kCLOCK_Iocon);
-
-  // Enable GPIO0 clock
-  CLOCK_EnableClock(kCLOCK_Gpio0);
-
-  // Init 96 MHz clock
-  BootClockFROHF96M();
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  GPIO_PortInit(GPIO, LED_PORT);
-  GPIO_PortInit(GPIO, BUTTON_PORT);
-
-  // LED
-  gpio_pin_config_t const led_config = { kGPIO_DigitalOutput, 0};
-  GPIO_PinInit(GPIO, LED_PORT, LED_PIN, &led_config);
-  board_led_write(true);
-
-  // Button
-  gpio_pin_config_t const button_config = { kGPIO_DigitalInput, 0};
-  GPIO_PinInit(GPIO, BUTTON_PORT, BUTTON_PIN, &button_config);
-
-  // USB
-  const uint32_t port1_pin6_config = (
-    IOCON_PIO_FUNC7       | /* Pin is configured as USB0_VBUS */
-    IOCON_PIO_MODE_INACT  | /* No addition pin function */
-    IOCON_PIO_INV_DI      | /* Input function is not inverted */
-    IOCON_PIO_DIGITAL_EN  | /* Enables digital function */
-    IOCON_PIO_INPFILT_OFF | /* Input filter disabled */
-    IOCON_PIO_OPENDRAIN_DI  /* Open drain is disabled */
-  );
-  IOCON_PinMuxSet(IOCON, 1, 6, port1_pin6_config); /* PORT1 PIN6 (coords: 26) is configured as USB0_VBUS */
-
-  POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); /*Turn on USB Phy */
-  CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcFro, CLOCK_GetFreq(kCLOCK_FroHf)); /* enable USB IP clock */
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  GPIO_PinWrite(GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  // active low
-  return 1-GPIO_PinRead(GPIO, BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/tinyusb/hw/bsp/mbed1768/board.mk b/tinyusb/hw/bsp/mbed1768/board.mk
deleted file mode 100755
index e99df9f0..00000000
--- a/tinyusb/hw/bsp/mbed1768/board.mk
+++ /dev/null
@@ -1,45 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m3 \
-  -nostdlib \
-  -DCORE_M3 \
-  -D__USE_LPCOPEN \
-  -DCFG_TUSB_MCU=OPT_MCU_LPC175X_6X \
-  -DRTC_EV_SUPPORT=0
-
-# startup.c and lpc_types.h cause following errors
-CFLAGS += -Wno-error=strict-prototypes
-
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc1768.ld
-
-SRC_C += \
-	src/portable/nxp/lpc17_40/dcd_lpc17_40.c \
-	$(MCU_DIR)/../gcc/cr_startup_lpc175x_6x.c \
-	$(MCU_DIR)/src/chip_17xx_40xx.c \
-	$(MCU_DIR)/src/clock_17xx_40xx.c \
-	$(MCU_DIR)/src/gpio_17xx_40xx.c \
-	$(MCU_DIR)/src/iocon_17xx_40xx.c \
-	$(MCU_DIR)/src/sysctl_17xx_40xx.c \
-	$(MCU_DIR)/src/sysinit_17xx_40xx.c \
-	$(MCU_DIR)/src/uart_17xx_40xx.c
-
-INC += \
-	$(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
-
-# For flash-jlink target
-JLINK_DEVICE = LPC1768
-
-# flash using pyocd 
-flash: $(BUILD)/$(PROJECT).hex
-	pyocd flash -t lpc1768 $<
-
diff --git a/tinyusb/hw/bsp/mbed1768/lpc1768.ld b/tinyusb/hw/bsp/mbed1768/lpc1768.ld
deleted file mode 100755
index d1c83d8e..00000000
--- a/tinyusb/hw/bsp/mbed1768/lpc1768.ld
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * GENERATED FILE - DO NOT EDIT
- * (c) Code Red Technologies Ltd, 2008-2013
- * (c) NXP Semiconductors 2013-2019
- * Generated linker script file for LPC1769
- * Created from linkscript.ldt by FMCreateLinkLibraries
- * Using Freemarker v2.3.23
- * MCUXpresso IDE v10.2.1 [Build 795] [2018-07-25] on May 14, 2019 6:39:29 PM
- */
-
-MEMORY
-{
-  /* Define each memory region */
-  MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */  
-  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */  
-  RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */  
-}
-
-  /* Define a symbol for the top of each memory region */
-  __base_MFlash512 = 0x0  ; /* MFlash512 */  
-  __base_Flash = 0x0 ; /* Flash */  
-  __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */  
-  __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */  
-  __base_RamLoc32 = 0x10000000  ; /* RamLoc32 */  
-  __base_RAM = 0x10000000 ; /* RAM */  
-  __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */  
-  __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */  
-  __base_RamAHB32 = 0x2007c000  ; /* RamAHB32 */  
-  __base_RAM2 = 0x2007c000 ; /* RAM2 */  
-  __top_RamAHB32 = 0x2007c000 + 0x8000 ; /* 32K bytes */  
-  __top_RAM2 = 0x2007c000 + 0x8000 ; /* 32K bytes */  
-
-ENTRY(ResetISR)
-
-SECTIONS
-{
-    /* MAIN TEXT SECTION */
-    .text : ALIGN(4)
-    {
-        FILL(0xff)
-        __vectors_start__ = ABSOLUTE(.) ;
-        KEEP(*(.isr_vector))
-        /* Global Section Table */
-        . = ALIGN(4) ;
-        __section_table_start = .;
-        __data_section_table = .;
-        LONG(LOADADDR(.data));
-        LONG(    ADDR(.data));
-        LONG(  SIZEOF(.data));
-        LONG(LOADADDR(.data_RAM2));
-        LONG(    ADDR(.data_RAM2));
-        LONG(  SIZEOF(.data_RAM2));
-        __data_section_table_end = .;
-        __bss_section_table = .;
-        LONG(    ADDR(.bss));
-        LONG(  SIZEOF(.bss));
-        LONG(    ADDR(.bss_RAM2));
-        LONG(  SIZEOF(.bss_RAM2));
-        __bss_section_table_end = .;
-        __section_table_end = . ;
-        /* End of Global Section Table */
-
-        *(.after_vectors*)
-
-    } > MFlash512
-
-    .text : ALIGN(4)
-    {
-       *(.text*)
-       *(.rodata .rodata.* .constdata .constdata.*)
-       . = ALIGN(4);
-    } > MFlash512
-    /*
-     * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
-     */
-    .ARM.extab : ALIGN(4) 
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > MFlash512
-
-    __exidx_start = .;
-
-    .ARM.exidx : ALIGN(4)
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > MFlash512
-    __exidx_end = .;
-
-    _etext = .;
-        
-    /* DATA section for RamAHB32 */
-
-    .data_RAM2 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM2 = .) ;
-        *(.ramfunc.$RAM2)
-        *(.ramfunc.$RamAHB32)
-        *(.data.$RAM2*)
-        *(.data.$RamAHB32*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM2 = .) ;
-     } > RamAHB32 AT>MFlash512
-    /* MAIN DATA SECTION */
-    .uninit_RESERVED : ALIGN(4)
-    {
-        KEEP(*(.bss.$RESERVED*))
-        . = ALIGN(4) ;
-        _end_uninit_RESERVED = .;
-    } > RamLoc32
-
-    /* Main DATA section (RamLoc32) */
-    .data : ALIGN(4)
-    {
-       FILL(0xff)
-       _data = . ;
-       *(vtable)
-       *(.ramfunc*)
-       *(.data*)
-       . = ALIGN(4) ;
-       _edata = . ;
-    } > RamLoc32 AT>MFlash512
-
-    /* BSS section for RamAHB32 */
-    .bss_RAM2 : ALIGN(4)
-    {
-       PROVIDE(__start_bss_RAM2 = .) ;
-       *(.bss.$RAM2*)
-       *(.bss.$RamAHB32*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM2 = .) ;
-    } > RamAHB32 
-
-    /* MAIN BSS SECTION */
-    .bss : ALIGN(4)
-    {
-        _bss = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4) ;
-        _ebss = .;
-        PROVIDE(end = .);
-    } > RamLoc32
-
-    /* NOINIT section for RamAHB32 */
-    .noinit_RAM2 (NOLOAD) : ALIGN(4)
-    {
-       *(.noinit.$RAM2*)
-       *(.noinit.$RamAHB32*)
-       . = ALIGN(4) ;
-    } > RamAHB32 
-
-    /* DEFAULT NOINIT SECTION */
-    .noinit (NOLOAD): ALIGN(4)
-    {
-        _noinit = .;
-        *(.noinit*) 
-         . = ALIGN(4) ;
-        _end_noinit = .;
-    } > RamLoc32
-    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
-    PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
-
-    /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (NMI_Handler + 1) 
-                                         + (HardFault_Handler + 1) 
-                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
-                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
-                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
-                                         ) );
-
-    /* Provide basic symbols giving location and size of main text
-     * block, including initial values of RW data sections. Note that
-     * these will need extending to give a complete picture with
-     * complex images (e.g multiple Flash banks).
-     */
-    _image_start = LOADADDR(.text);
-    _image_end = LOADADDR(.data) + SIZEOF(.data);
-    _image_size = _image_end - _image_start;
-}
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/mbed1768/mbed1768.c b/tinyusb/hw/bsp/mbed1768/mbed1768.c
deleted file mode 100755
index 5495ed16..00000000
--- a/tinyusb/hw/bsp/mbed1768/mbed1768.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "chip.h"
-#include "../board.h"
-
-#define LED_PORT              1
-#define LED_PIN               18
-#define LED_STATE_ON          1
-
-// JOYSTICK_DOWN if using LPCXpresso Base Board
-#define BUTTON_PORT           0
-#define BUTTON_PIN            15
-#define BUTTON_STATE_ACTIVE   0
-
-#define BOARD_UART_PORT   LPC_UART3
-
-/* System oscillator rate and RTC oscillator rate */
-const uint32_t OscRateIn = 10000000;
-const uint32_t RTCOscRateIn = 32768;
-
-/* Pin muxing configuration */
-static const PINMUX_GRP_T pinmuxing[] =
-{
-  {LED_PORT,  LED_PIN,  IOCON_MODE_INACT | IOCON_FUNC0},
-  {BUTTON_PORT, BUTTON_PIN, IOCON_FUNC0 | IOCON_MODE_PULLUP},
-};
-
-static const PINMUX_GRP_T pin_usb_mux[] =
-{
-  {0, 29, IOCON_MODE_INACT | IOCON_FUNC1}, // D+
-  {0, 30, IOCON_MODE_INACT | IOCON_FUNC1}, // D-
-  {2,  9, IOCON_MODE_INACT | IOCON_FUNC1}, // Connect
-
-  {1, 19, IOCON_MODE_INACT | IOCON_FUNC2}, // USB_PPWR
-  {1, 22, IOCON_MODE_INACT | IOCON_FUNC2}, // USB_PWRD
-
-  /* VBUS is not connected on this board, so leave the pin at default setting. */
-  /*Chip_IOCON_PinMux(LPC_IOCON, 1, 30, IOCON_MODE_INACT, IOCON_FUNC2);*/ /* USB VBUS */
-};
-
-// Invoked by startup code
-void SystemInit(void)
-{
-#ifdef __USE_LPCOPEN
-	extern void (* const g_pfnVectors[])(void);
-  unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
-	*pSCB_VTOR = (unsigned int) g_pfnVectors;
-#endif
-
-  Chip_IOCON_Init(LPC_IOCON);
-  Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
-  Chip_SetupXtalClocking();
-}
-
-void board_init(void)
-{
-  SystemCoreClockUpdate();
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  Chip_GPIO_Init(LPC_GPIO);
-
-  // LED
-  Chip_GPIO_SetPinDIROutput(LPC_GPIO, LED_PORT, LED_PIN);
-
-  // Button
-  Chip_GPIO_SetPinDIRInput(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
-
-#if 0
-  //------------- UART -------------//
-  PINSEL_CFG_Type PinCfg =
-  {
-      .Portnum   = 0,
-      .Pinnum    = 0, // TXD is P0.0
-      .Funcnum   = 2,
-      .OpenDrain = 0,
-      .Pinmode   = 0
-  };
-	PINSEL_ConfigPin(&PinCfg);
-
-	PinCfg.Portnum = 0;
-	PinCfg.Pinnum  = 1; // RXD is P0.1
-	PINSEL_ConfigPin(&PinCfg);
-
-	UART_CFG_Type UARTConfigStruct;
-  UART_ConfigStructInit(&UARTConfigStruct);
-	UARTConfigStruct.Baud_rate = CFG_BOARD_UART_BAUDRATE;
-
-	UART_Init(BOARD_UART_PORT, &UARTConfigStruct);
-	UART_TxCmd(BOARD_UART_PORT, ENABLE); // Enable UART Transmit
-#endif
-
-	//------------- USB -------------//
-  Chip_IOCON_SetPinMuxing(LPC_IOCON, pin_usb_mux, sizeof(pin_usb_mux) / sizeof(PINMUX_GRP_T));
-	Chip_USB_Init();
-
-  enum {
-    USBCLK_DEVCIE = 0x12,     // AHB + Device
-    USBCLK_HOST   = 0x19,     // AHB + Host + OTG
-//    0x1B // Host + Device + OTG + AHB
-  };
-
-  uint32_t const clk_en = TUSB_OPT_DEVICE_ENABLED ? USBCLK_DEVCIE : USBCLK_HOST;
-
-  LPC_USB->OTGClkCtrl = clk_en;
-  while ( (LPC_USB->OTGClkSt & clk_en) != clk_en );
-
-#if TUSB_OPT_HOST_ENABLED
-  // set portfunc to host !!!
-  LPC_USB->StCtrl = 0x3; // should be 1
-#endif
-}
-
-//--------------------------------------------------------------------+
-// USB Interrupt Handler
-//--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
-    tuh_int_handler(0);
-  #endif
-
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-    tud_int_handler(0);
-  #endif
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-//  return UART_ReceiveByte(BOARD_UART_PORT);
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-//  UART_Send(BOARD_UART_PORT, &c, 1, BLOCKING);
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/tinyusb/hw/bsp/msp430/boards/msp_exp430f5529lp/board.h b/tinyusb/hw/bsp/msp430/boards/msp_exp430f5529lp/board.h
deleted file mode 100755
index ccfe321c..00000000
--- a/tinyusb/hw/bsp/msp430/boards/msp_exp430f5529lp/board.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define LED_PORT              P1OUT
-#define LED_PIN               BIT0
-#define LED_STATE_ON          1
-
-#define BUTTON_PORT           P1IN
-#define BUTTON_PIN            BIT1
-#define BUTTON_STATE_ACTIVE   0
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif
diff --git a/tinyusb/hw/bsp/msp430/family.c b/tinyusb/hw/bsp/msp430/family.c
deleted file mode 100755
index 4b8ae393..00000000
--- a/tinyusb/hw/bsp/msp430/family.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "bsp/board.h"
-#include "board.h"
-#include "msp430.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void __attribute__ ((interrupt(USB_UBM_VECTOR))) USB_UBM_ISR(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-uint32_t cnt = 0;
-
-static void SystemClock_Config(void)
-{
-  WDTCTL = WDTPW + WDTHOLD; // Disable watchdog.
-
-  // Increase VCore to level 2- required for 16 MHz operation on this MCU.
-  PMMCTL0 = PMMPW + PMMCOREV_2;
-
-  UCSCTL3 = SELREF__XT2CLK; // FLL is fed by XT2.
-
-  // XT1 used for ACLK (default- not used in this demo)
-  P5SEL |= BIT4; // Required to enable XT1
-  // Loop until XT1 fault flag is cleared.
-  do
-  {
-    UCSCTL7 &= ~XT1LFOFFG;
-  }while(UCSCTL7 & XT1LFOFFG);
-
-  // XT2 is 4 MHz an external oscillator, use PLL to boost to 16 MHz.
-  P5SEL |= BIT2; // Required to enable XT2.
-  // Loop until XT2 fault flag is cleared
-  do
-  {
-    UCSCTL7 &= ~XT2OFFG;
-  }while(UCSCTL7 & XT2OFFG);
-
-  // Kickstart the DCO into the correct frequency range, otherwise a
-  // fault will occur.
-  // FIXME: DCORSEL_6 should work according to datasheet params, but generates
-  // a fault. I am not sure why it faults.
-  UCSCTL1 = DCORSEL_7;
-  UCSCTL2 = FLLD_2 + 3; // DCO freq = D * (N + 1) * (FLLREFCLK / n)
-                        // DCOCLKDIV freq = (N + 1) * (FLLREFCLK / n)
-                        // N = 3, D = 2, thus DCO freq = 32 MHz.
-
-  // MCLK configured for 16 MHz using XT2.
-  // SMCLK configured for 8 MHz using XT2.
-  UCSCTL4 |= SELM__DCOCLKDIV + SELS__DCOCLKDIV;
-  UCSCTL5 |= DIVM__16 + DIVS__2;
-
-  // Now wait till everything's stabilized.
-  do
-  {
-    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
-    SFRIFG1 &= ~OFIFG;
-  }while(SFRIFG1 & OFIFG);
-
-  // Configure Timer A to use SMCLK as a source. Count 1000 ticks at 1 MHz.
-  TA0CCTL0 |= CCIE;
-  TA0CCR0 = 999; // 1000 ticks.
-  TA0CTL |= TASSEL_2 + ID_3 + MC__UP; // Use SMCLK, divide by 8, start timer.
-
-  // Initialize USB power and PLL.
-  USBKEYPID = USBKEY;
-
-  // VUSB enabled automatically.
-  // Wait two milliseconds to stabilize, per manual recommendation.
-  uint32_t ms_elapsed = board_millis();
-  do
-  {
-    while((board_millis() - ms_elapsed) < 2);
-  }while(!(USBPWRCTL & USBBGVBV));
-
-  // USB uses XT2 (4 MHz) directly. Enable the PLL.
-  USBPLLDIVB |= USBPLL_SETCLK_4_0;
-  USBPLLCTL |= (UPFDEN | UPLLEN);
-
-  // Wait until PLL locks. Check every 2ms, per manual.
-  ms_elapsed = board_millis();
-  do
-  {
-    USBPLLIR &= ~USBOOLIFG;
-    while((board_millis() - ms_elapsed) < 2);
-  }while(USBPLLIR & USBOOLIFG);
-
-  USBKEYPID = 0;
-}
-
-uint32_t wait = 0;
-
-void board_init(void)
-{
-  __bis_SR_register(GIE); // Enable interrupts.
-  SystemClock_Config();
-
-  // Enable basic I/O.
-  P1DIR |= LED_PIN; // LED output.
-  P1REN |= BUTTON_PIN; // Internal resistor enable.
-  P1OUT |= BUTTON_PIN; // Pullup.
-
-  // Enable the backchannel UART (115200)
-  P4DIR |= BIT5;
-  P4SEL |= (BIT5 | BIT4);
-
-  UCA1CTL1 |= (UCSSEL__SMCLK | UCSWRST); // Hold in reset, use SMCLK.
-  UCA1BRW = 4;
-  UCA1MCTL |= (UCBRF_3 | UCBRS_5 | UCOS16); // Overampling mode, 115200 baud.
-                                            // Copied from manual.
-  UCA1CTL1 &= ~UCSWRST;
-
-  // Set up USB pins.
-  USBKEYPID = USBKEY;
-  USBPHYCTL |= PUSEL; // Convert USB D+/D- pins to USB functionality.
-  USBKEYPID = 0;
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  if(state)
-  {
-    LED_PORT |= LED_PIN;
-  }
-  else
-  {
-    LED_PORT &= ~LED_PIN;
-  }
-}
-
-uint32_t board_button_read(void)
-{
-  return ((P1IN & BIT1) >> 1) == BUTTON_STATE_ACTIVE;
-}
-
-int board_uart_read(uint8_t * buf, int len)
-{
-  for(int i = 0; i < len; i++)
-  {
-    // Wait until something to receive (cleared by reading buffer).
-    while(!(UCA1IFG & UCRXIFG));
-    buf[i] = UCA1RXBUF;
-  }
-
-  return len;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  const char * char_buf = (const char *) buf;
-
-  for(int i = 0; i < len; i++)
-  {
-    // Wait until TX buffer is empty (cleared by writing buffer).
-    while(!(UCA1IFG & UCTXIFG));
-    UCA1TXBUF = char_buf[i];
-  }
-
-  return len;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void __attribute__ ((interrupt(TIMER0_A0_VECTOR))) TIMER0_A0_ISR (void)
-{
-  system_ticks++;
-  // TAxCCR0 CCIFG resets itself as soon as interrupt is invoked.
-}
-
-uint32_t board_millis(void)
-{
-  uint32_t systick_mirror;
-
-  // 32-bit update is not atomic on MSP430. We can read the bottom 16-bits,
-  // an interrupt occurs, updates _all_ 32 bits, and then we return a
-  // garbage value. And I've seen it happen!
-  TA0CCTL0 &= ~CCIE;
-  systick_mirror = system_ticks;
-  TA0CCTL0 |= CCIE;
-
-  return systick_mirror;
-}
-#endif
diff --git a/tinyusb/hw/bsp/msp430/family.mk b/tinyusb/hw/bsp/msp430/family.mk
deleted file mode 100755
index ceafa6ec..00000000
--- a/tinyusb/hw/bsp/msp430/family.mk
+++ /dev/null
@@ -1,35 +0,0 @@
-CROSS_COMPILE = msp430-elf-
-DEPS_SUBMODULES += hw/mcu/ti
-SKIP_NANOLIB = 1
-
-CFLAGS += \
-  -D__MSP430F5529__ \
-  -DCFG_TUSB_MCU=OPT_MCU_MSP430x5xx \
-	-DCFG_EXAMPLE_MSC_READONLY \
-	-DCFG_TUD_ENDPOINT0_SIZE=8
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/mcu/ti/msp430/msp430-gcc-support-files/include/msp430f5529.ld
-LDINC += $(TOP)/hw/mcu/ti/msp430/msp430-gcc-support-files/include
-LDFLAGS += $(addprefix -L,$(LDINC))
-
-SRC_C += src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
-
-INC += \
-	$(TOP)/hw/mcu/ti/msp430/msp430-gcc-support-files/include \
-	$(TOP)/$(BOARD_PATH)
-
-# export for libmsp430.so to same installation
-ifneq ($(OS),Windows_NT)
-export LD_LIBRARY_PATH=$(dir $(shell which MSP430Flasher))
-endif
-
-# flash target using TI MSP430-Flasher
-# http://www.ti.com/tool/MSP430-FLASHER
-# Please add its installation dir to PATH
-flash: $(BUILD)/$(PROJECT).hex
-	MSP430Flasher -w $< -z [VCC]
-
-# flash target using mspdebug.
-flash-mspdebug: $(BUILD)/$(PROJECT).elf
-	$(MSPDEBUG) tilib "prog $<" --allow-fw-update
diff --git a/tinyusb/hw/bsp/ngx4330/board.mk b/tinyusb/hw/bsp/ngx4330/board.mk
deleted file mode 100755
index 04c37fee..00000000
--- a/tinyusb/hw/bsp/ngx4330/board.mk
+++ /dev/null
@@ -1,45 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib \
-  -DCORE_M4 \
-  -D__USE_LPCOPEN \
-  -DCFG_TUSB_MCU=OPT_MCU_LPC43XX
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter
-
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/ngx4330.ld
-
-SRC_C += \
-	src/portable/nxp/transdimension/dcd_transdimension.c \
-	$(MCU_DIR)/../gcc/cr_startup_lpc43xx.c \
-	$(MCU_DIR)/src/chip_18xx_43xx.c \
-	$(MCU_DIR)/src/clock_18xx_43xx.c \
-	$(MCU_DIR)/src/gpio_18xx_43xx.c \
-	$(MCU_DIR)/src/sysinit_18xx_43xx.c \
-	$(MCU_DIR)/src/uart_18xx_43xx.c \
-	$(MCU_DIR)/src/fpu_init.c
-
-INC += \
-	$(TOP)/$(MCU_DIR)/inc \
-	$(TOP)/$(MCU_DIR)/inc/config_43xx
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = LPC4330
-JLINK_IF = swd 
-
-# flash using jlink
-flash: flash-jlink
diff --git a/tinyusb/hw/bsp/ngx4330/ngx4330.c b/tinyusb/hw/bsp/ngx4330/ngx4330.c
deleted file mode 100755
index b63f9b89..00000000
--- a/tinyusb/hw/bsp/ngx4330/ngx4330.c
+++ /dev/null
@@ -1,264 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "chip.h"
-#include "../board.h"
-
-#define LED_PORT              1
-#define LED_PIN               12
-#define LED_STATE_ON          0
-
-#define BUTTON_PORT           0
-#define BUTTON_PIN            7
-#define BUTTON_STATE_ACTIVE   0
-
-#define BOARD_UART_PORT           LPC_USART0
-#define BOARD_UART_PIN_PORT       0x0f
-#define BOARD_UART_PIN_TX         10 // PF.10 : UART0_TXD
-#define BOARD_UART_PIN_RX         11 // PF.11 : UART0_RXD
-
-/*------------------------------------------------------------------*/
-/* BOARD API
- *------------------------------------------------------------------*/
-
-/* System configuration variables used by chip driver */
-const uint32_t OscRateIn = 12000000;
-const uint32_t ExtRateIn = 0;
-
-static const PINMUX_GRP_T pinmuxing[] =
-{
-  // LED P2.12 as GPIO 1.12
-  {2, 11, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLDOWN | SCU_MODE_FUNC0)},
-
-  // Button P2.7 as GPIO 0.7
-  {2, 7,  (SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0)},
-
-  // USB
-  {2, 6, (SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC4)}, // USB1_PWR_EN
-  {2, 5, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2)}, // USB1_VBUS
-  {1, 7, (SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC4)}, // USB0_PWRN_EN
-
-  // SPIFI
-	{3, 3,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},	/* SPIFI CLK */
-	{3, 4,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},	/* SPIFI D3 */
-	{3, 5,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},	/* SPIFI D2 */
-	{3, 6,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},	/* SPIFI D1 */
-	{3, 7,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},	/* SPIFI D0 */
-	{3, 8,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)}	/* SPIFI CS/SSEL */
-};
-
-// Invoked by startup code
-void SystemInit(void)
-{
-#ifdef __USE_LPCOPEN
-	extern void (* const g_pfnVectors[])(void);
-  unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
-	*pSCB_VTOR = (unsigned int) g_pfnVectors;
-
-#if __FPU_USED == 1
-	fpuInit();
-#endif
-#endif // __USE_LPCOPEN
-
-	// Set up pinmux
-	Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
-
-	//------------- Set up clock -------------//
-	Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IRC, true, false);	// change SPIFI to IRC during clock programming
-	LPC_SPIFI->CTRL |= SPIFI_CTRL_FBCLK(1);								            // and set FBCLK in SPIFI controller
-
-	Chip_SetupCoreClock(CLKIN_CRYSTAL, MAX_CLOCK_FREQ, true);
-
-	/* Reset and enable 32Khz oscillator */
-	LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
-	LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
-
-	/* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
-	   Divide rate is based on CPU speed and speed of SPI FLASH part. */
-#if (MAX_CLOCK_FREQ > 180000000)
-	Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
-#else
-	Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
-#endif
-	Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
-
-	/* Setup system base clocks and initial states. This won't enable and
-	   disable individual clocks, but sets up the base clock sources for
-	   each individual peripheral clock. */
-	Chip_Clock_SetBaseClock(CLK_BASE_USB1, CLKIN_IDIVD, true, true);
-}
-
-void board_init(void)
-{
-  SystemCoreClockUpdate();
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  //NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  Chip_GPIO_Init(LPC_GPIO_PORT);
-
-  // LED
-  Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, LED_PORT, LED_PIN);
-
-  // Button
-  Chip_GPIO_SetPinDIRInput(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN);
-
-#if 0
-  //------------- UART -------------//
-  scu_pinmux(BOARD_UART_PIN_PORT, BOARD_UART_PIN_TX, MD_PDN, FUNC1);
-  scu_pinmux(BOARD_UART_PIN_PORT, BOARD_UART_PIN_RX, MD_PLN | MD_EZI | MD_ZI, FUNC1);
-
-  UART_CFG_Type UARTConfigStruct;
-  UART_ConfigStructInit(&UARTConfigStruct);
-  UARTConfigStruct.Baud_rate   = CFG_BOARD_UART_BAUDRATE;
-  UARTConfigStruct.Clock_Speed = 0;
-
-  UART_Init(BOARD_UART_PORT, &UARTConfigStruct);
-  UART_TxCmd(BOARD_UART_PORT, ENABLE); // Enable UART Transmit
-#endif
-
-  //------------- USB -------------//
-  enum {
-    USBMODE_DEVICE = 2,
-    USBMODE_HOST   = 3
-  };
-
-  enum {
-    USBMODE_VBUS_LOW  = 0,
-    USBMODE_VBUS_HIGH = 1
-  };
-
-  /* USB0
-   * For USB Device operation; insert jumpers in position 1-2 in JP17/JP18/JP19. GPIO28 controls USB
-   * connect functionality and LED32 lights when the USB Device is connected. SJ4 has pads 1-2 shorted
-   * by default. LED33 is controlled by GPIO27 and signals USB-up state. GPIO54 is used for VBUS
-   * sensing.
-   * For USB Host operation; insert jumpers in position 2-3 in JP17/JP18/JP19. USB Host power is
-   * controlled via distribution switch U20 (found in schematic page 11). Signal GPIO26 is active low and
-   * enables +5V on VBUS2. LED35 light whenever +5V is present on VBUS2. GPIO55 is connected to
-   * status feedback from the distribution switch. GPIO54 is used for VBUS sensing. 15Kohm pull-down
-   * resistors are always active
-   */
-#if CFG_TUSB_RHPORT0_MODE
-  Chip_USB0_Init();
-#endif
-
-  /* USB1
-   * When USB channel #1 is used as USB Host, 15Kohm pull-down resistors are needed on the USB data
-   * signals. These are activated inside the USB OTG chip (U31), and this has to be done via the I2C
-   * interface of GPIO52/GPIO53.
-   * J20 is the connector to use when USB Host is used. In order to provide +5V to the external USB
-   * device connected to this connector (J20), channel A of U20 must be enabled. It is enabled by default
-   * since SJ5 is normally connected between pin 1-2. LED34 lights green when +5V is available on J20.
-   * JP15 shall not be inserted. JP16 has no effect
-   *
-   * When USB channel #1 is used as USB Device, a 1.5Kohm pull-up resistor is needed on the USB DP
-   * data signal. There are two methods to create this. JP15 is inserted and the pull-up resistor is always
-   * enabled. Alternatively, the pull-up resistor is activated inside the USB OTG chip (U31), and this has to
-   * be done via the I2C interface of GPIO52/GPIO53. In the latter case, JP15 shall not be inserted.
-   * J19 is the connector to use when USB Device is used. Normally it should be a USB-B connector for
-   * creating a USB Device interface, but the mini-AB connector can also be used in this case. The status
-   * of VBUS can be read via U31.
-   * JP16 shall not be inserted.
-   */
-#if CFG_TUSB_RHPORT1_MODE
-  Chip_USB1_Init();
-
-//	Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 5, 6);							/* GPIO5[6] = USB1_PWR_EN */
-//	Chip_GPIO_SetPinState(LPC_GPIO_PORT, 5, 6, true);							/* GPIO5[6] output high */
-#endif
-}
-
-//--------------------------------------------------------------------+
-// USB Interrupt Handler
-//--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
-    tuh_int_handler(0);
-  #endif
-
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-    tud_int_handler(0);
-  #endif
-}
-
-void USB1_IRQHandler(void)
-{
-  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
-    tuh_int_handler(1);
-  #endif
-
-  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE
-    tud_int_handler(1);
-  #endif
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  Chip_GPIO_SetPinState(LPC_GPIO_PORT, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == Chip_GPIO_GetPinState(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  //return UART_ReceiveByte(BOARD_UART_PORT);
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  //UART_Send(BOARD_UART_PORT, &c, 1, BLOCKING);
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/tinyusb/hw/bsp/ngx4330/ngx4330.ld b/tinyusb/hw/bsp/ngx4330/ngx4330.ld
deleted file mode 100755
index 7bd363f0..00000000
--- a/tinyusb/hw/bsp/ngx4330/ngx4330.ld
+++ /dev/null
@@ -1,343 +0,0 @@
-/*
- * GENERATED FILE - DO NOT EDIT
- * Copyright (c) 2008-2013 Code Red Technologies Ltd,
- * Copyright 2015, 2018-2019 NXP
- * (c) NXP Semiconductors 2013-2019
- * Generated linker script file for LPC4330
- * Created from linkscript.ldt by FMCreateLinkLibraries
- * Using Freemarker v2.3.23
- * MCUXpresso IDE v11.0.0 [Build 2516] [2019-06-05] on Sep 9, 2019 12:09:49 PM
- */
-
-MEMORY
-{
-  /* Define each memory region */
-  RamLoc128 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x20000 /* 128K bytes (alias RAM) */  
-  RamLoc72 (rwx) : ORIGIN = 0x10080000, LENGTH = 0x12000 /* 72K bytes (alias RAM2) */  
-  RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */  
-  RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */  
-  RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */  
-  SPIFI (rx) : ORIGIN = 0x14000000, LENGTH = 0x400000 /* 4M bytes (alias Flash) */  
-}
-
-  /* Define a symbol for the top of each memory region */
-  __base_RamLoc128 = 0x10000000  ; /* RamLoc128 */  
-  __base_RAM = 0x10000000 ; /* RAM */  
-  __top_RamLoc128 = 0x10000000 + 0x20000 ; /* 128K bytes */  
-  __top_RAM = 0x10000000 + 0x20000 ; /* 128K bytes */  
-  __base_RamLoc72 = 0x10080000  ; /* RamLoc72 */  
-  __base_RAM2 = 0x10080000 ; /* RAM2 */  
-  __top_RamLoc72 = 0x10080000 + 0x12000 ; /* 72K bytes */  
-  __top_RAM2 = 0x10080000 + 0x12000 ; /* 72K bytes */  
-  __base_RamAHB32 = 0x20000000  ; /* RamAHB32 */  
-  __base_RAM3 = 0x20000000 ; /* RAM3 */  
-  __top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-  __top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-  __base_RamAHB16 = 0x20008000  ; /* RamAHB16 */  
-  __base_RAM4 = 0x20008000 ; /* RAM4 */  
-  __top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */  
-  __top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */  
-  __base_RamAHB_ETB16 = 0x2000c000  ; /* RamAHB_ETB16 */  
-  __base_RAM5 = 0x2000c000 ; /* RAM5 */  
-  __top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */  
-  __top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */  
-  __base_SPIFI = 0x14000000  ; /* SPIFI */  
-  __base_Flash = 0x14000000 ; /* Flash */  
-  __top_SPIFI = 0x14000000 + 0x400000 ; /* 4M bytes */  
-  __top_Flash = 0x14000000 + 0x400000 ; /* 4M bytes */  
-
-ENTRY(ResetISR)
-
-SECTIONS
-{
-     /* MAIN TEXT SECTION */
-    .text : ALIGN(4)
-    {
-        FILL(0xff)
-        __vectors_start__ = ABSOLUTE(.) ;
-        KEEP(*(.isr_vector))
-        /* Global Section Table */
-        . = ALIGN(4) ;
-        __section_table_start = .;
-        __data_section_table = .;
-        LONG(LOADADDR(.data));
-        LONG(    ADDR(.data));
-        LONG(  SIZEOF(.data));
-        LONG(LOADADDR(.data_RAM2));
-        LONG(    ADDR(.data_RAM2));
-        LONG(  SIZEOF(.data_RAM2));
-        LONG(LOADADDR(.data_RAM3));
-        LONG(    ADDR(.data_RAM3));
-        LONG(  SIZEOF(.data_RAM3));
-        LONG(LOADADDR(.data_RAM4));
-        LONG(    ADDR(.data_RAM4));
-        LONG(  SIZEOF(.data_RAM4));
-        LONG(LOADADDR(.data_RAM5));
-        LONG(    ADDR(.data_RAM5));
-        LONG(  SIZEOF(.data_RAM5));
-        __data_section_table_end = .;
-        __bss_section_table = .;
-        LONG(    ADDR(.bss));
-        LONG(  SIZEOF(.bss));
-        LONG(    ADDR(.bss_RAM2));
-        LONG(  SIZEOF(.bss_RAM2));
-        LONG(    ADDR(.bss_RAM3));
-        LONG(  SIZEOF(.bss_RAM3));
-        LONG(    ADDR(.bss_RAM4));
-        LONG(  SIZEOF(.bss_RAM4));
-        LONG(    ADDR(.bss_RAM5));
-        LONG(  SIZEOF(.bss_RAM5));
-        __bss_section_table_end = .;
-        __section_table_end = . ;
-        /* End of Global Section Table */
-
-        *(.after_vectors*)
-
-    } > SPIFI
-
-    .text : ALIGN(4)
-    {
-       *(.text*)
-       *(.rodata .rodata.* .constdata .constdata.*)
-       . = ALIGN(4);
-    } > SPIFI
-    /*
-     * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
-     */
-    .ARM.extab : ALIGN(4) 
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > SPIFI
-
-    __exidx_start = .;
-
-    .ARM.exidx : ALIGN(4)
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > SPIFI
-    __exidx_end = .;
- 
-    _etext = .;
-        
-    /* DATA section for RamLoc72 */
-
-    .data_RAM2 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM2 = .) ;
-        *(.ramfunc.$RAM2)
-        *(.ramfunc.$RamLoc72)
-        *(.data.$RAM2)
-        *(.data.$RamLoc72)
-        *(.data.$RAM2.*)
-        *(.data.$RamLoc72.*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM2 = .) ;
-     } > RamLoc72 AT>SPIFI
-    /* DATA section for RamAHB32 */
-
-    .data_RAM3 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM3 = .) ;
-        *(.ramfunc.$RAM3)
-        *(.ramfunc.$RamAHB32)
-        *(.data.$RAM3)
-        *(.data.$RamAHB32)
-        *(.data.$RAM3.*)
-        *(.data.$RamAHB32.*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM3 = .) ;
-     } > RamAHB32 AT>SPIFI
-    /* DATA section for RamAHB16 */
-
-    .data_RAM4 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM4 = .) ;
-        *(.ramfunc.$RAM4)
-        *(.ramfunc.$RamAHB16)
-        *(.data.$RAM4)
-        *(.data.$RamAHB16)
-        *(.data.$RAM4.*)
-        *(.data.$RamAHB16.*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM4 = .) ;
-     } > RamAHB16 AT>SPIFI
-    /* DATA section for RamAHB_ETB16 */
-
-    .data_RAM5 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM5 = .) ;
-        *(.ramfunc.$RAM5)
-        *(.ramfunc.$RamAHB_ETB16)
-        *(.data.$RAM5)
-        *(.data.$RamAHB_ETB16)
-        *(.data.$RAM5.*)
-        *(.data.$RamAHB_ETB16.*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM5 = .) ;
-     } > RamAHB_ETB16 AT>SPIFI
-    /* MAIN DATA SECTION */
-    .uninit_RESERVED (NOLOAD) :
-    {
-        . = ALIGN(4) ;
-        KEEP(*(.bss.$RESERVED*))
-       . = ALIGN(4) ;
-        _end_uninit_RESERVED = .;
-    } > RamLoc128
-
-    /* Main DATA section (RamLoc128) */
-    .data : ALIGN(4)
-    {
-       FILL(0xff)
-       _data = . ;
-       *(vtable)
-       *(.ramfunc*)
-       *(.data*)
-       . = ALIGN(4) ;
-       _edata = . ;
-    } > RamLoc128 AT>SPIFI
-
-    /* BSS section for RamLoc72 */
-    .bss_RAM2 :
-    {
-       . = ALIGN(4) ;
-       PROVIDE(__start_bss_RAM2 = .) ;
-       *(.bss.$RAM2)
-       *(.bss.$RamLoc72)
-       *(.bss.$RAM2.*)
-       *(.bss.$RamLoc72.*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM2 = .) ;
-    } > RamLoc72
-
-    /* BSS section for RamAHB32 */
-    .bss_RAM3 :
-    {
-       . = ALIGN(4) ;
-       PROVIDE(__start_bss_RAM3 = .) ;
-       *(.bss.$RAM3)
-       *(.bss.$RamAHB32)
-       *(.bss.$RAM3.*)
-       *(.bss.$RamAHB32.*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM3 = .) ;
-    } > RamAHB32
-
-    /* BSS section for RamAHB16 */
-    .bss_RAM4 :
-    {
-       . = ALIGN(4) ;
-       PROVIDE(__start_bss_RAM4 = .) ;
-       *(.bss.$RAM4)
-       *(.bss.$RamAHB16)
-       *(.bss.$RAM4.*)
-       *(.bss.$RamAHB16.*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM4 = .) ;
-    } > RamAHB16
-
-    /* BSS section for RamAHB_ETB16 */
-    .bss_RAM5 :
-    {
-       . = ALIGN(4) ;
-       PROVIDE(__start_bss_RAM5 = .) ;
-       *(.bss.$RAM5)
-       *(.bss.$RamAHB_ETB16)
-       *(.bss.$RAM5.*)
-       *(.bss.$RamAHB_ETB16.*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM5 = .) ;
-    } > RamAHB_ETB16
-
-    /* MAIN BSS SECTION */
-    .bss :
-    {
-        . = ALIGN(4) ;
-        _bss = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4) ;
-        _ebss = .;
-        PROVIDE(end = .);
-    } > RamLoc128
-
-    /* NOINIT section for RamLoc72 */
-    .noinit_RAM2 (NOLOAD) :
-    {
-       . = ALIGN(4) ;
-       *(.noinit.$RAM2)
-       *(.noinit.$RamLoc72)
-       *(.noinit.$RAM2.*)
-       *(.noinit.$RamLoc72.*)
-       . = ALIGN(4) ;
-    } > RamLoc72
-
-    /* NOINIT section for RamAHB32 */
-    .noinit_RAM3 (NOLOAD) :
-    {
-       . = ALIGN(4) ;
-       *(.noinit.$RAM3)
-       *(.noinit.$RamAHB32)
-       *(.noinit.$RAM3.*)
-       *(.noinit.$RamAHB32.*)
-       . = ALIGN(4) ;
-    } > RamAHB32
-
-    /* NOINIT section for RamAHB16 */
-    .noinit_RAM4 (NOLOAD) :
-    {
-       . = ALIGN(4) ;
-       *(.noinit.$RAM4)
-       *(.noinit.$RamAHB16)
-       *(.noinit.$RAM4.*)
-       *(.noinit.$RamAHB16.*)
-       . = ALIGN(4) ;
-    } > RamAHB16
-
-    /* NOINIT section for RamAHB_ETB16 */
-    .noinit_RAM5 (NOLOAD) :
-    {
-       . = ALIGN(4) ;
-       *(.noinit.$RAM5)
-       *(.noinit.$RamAHB_ETB16)
-       *(.noinit.$RAM5.*)
-       *(.noinit.$RamAHB_ETB16.*)
-       . = ALIGN(4) ;
-    } > RamAHB_ETB16
-
-    /* DEFAULT NOINIT SECTION */
-    .noinit (NOLOAD):
-    {
-         . = ALIGN(4) ;
-        _noinit = .;
-        *(.noinit*)
-         . = ALIGN(4) ;
-        _end_noinit = .;
-    } > RamLoc128
-    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
-    PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc128 - 0);
-
-    /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (NMI_Handler + 1) 
-                                         + (HardFault_Handler + 1) 
-                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
-                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
-                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
-                                         ) );
-
-    /* Provide basic symbols giving location and size of main text
-     * block, including initial values of RW data sections. Note that
-     * these will need extending to give a complete picture with
-     * complex images (e.g multiple Flash banks).
-     */
-    _image_start = LOADADDR(.text);
-    _image_end = LOADADDR(.data) + SIZEOF(.data);
-    _image_size = _image_end - _image_start;
-}
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/nrf/boards/adafruit_clue/board.h b/tinyusb/hw/bsp/nrf/boards/adafruit_clue/board.h
deleted file mode 100755
index 2c58e8fe..00000000
--- a/tinyusb/hw/bsp/nrf/boards/adafruit_clue/board.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define _PINNUM(port, pin)    ((port)*32 + (pin))
-
-// LED
-#define LED_PIN               _PINNUM(1, 1)
-#define LED_STATE_ON          1
-
-// Button
-#define BUTTON_PIN            _PINNUM(1, 02)
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_RX_PIN           4
-#define UART_TX_PIN           5
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/nrf/boards/adafruit_clue/board.mk b/tinyusb/hw/bsp/nrf/boards/adafruit_clue/board.mk
deleted file mode 100755
index f31899eb..00000000
--- a/tinyusb/hw/bsp/nrf/boards/adafruit_clue/board.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-MCU_VARIANT = nrf52840
-CFLAGS += -DNRF52840_XXAA
-
-$(BUILD)/$(PROJECT).zip: $(BUILD)/$(PROJECT).hex
-	adafruit-nrfutil dfu genpkg --dev-type 0x0052 --sd-req 0xFFFE --application $^ $@
-
-# flash using adafruit-nrfutil dfu
-flash: $(BUILD)/$(PROJECT).zip
-	@:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyACM0)
-	adafruit-nrfutil --verbose dfu serial --package $^ -p $(SERIAL) -b 115200 --singlebank --touch 1200
diff --git a/tinyusb/hw/bsp/nrf/boards/adafruit_clue/nrf52840_s140_v6.ld b/tinyusb/hw/bsp/nrf/boards/adafruit_clue/nrf52840_s140_v6.ld
deleted file mode 100755
index 5314a4e9..00000000
--- a/tinyusb/hw/bsp/nrf/boards/adafruit_clue/nrf52840_s140_v6.ld
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Linker script to configure memory regions. */
-
-SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
-
-MEMORY
-{
-  FLASH (rx)     : ORIGIN = 0x26000, LENGTH = 0xED000 - 0x26000
-
-  /* SRAM required by S132 depend on
-   * - Attribute Table Size
-   * - Vendor UUID count
-   * - Max ATT MTU
-   * - Concurrent connection peripheral + central + secure links
-   * - Event Len, HVN queue, Write CMD queue
-   */ 
-  RAM (rwx) :  ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400
-}
-
-SECTIONS
-{
-  . = ALIGN(4);
-  .svc_data :
-  {
-    PROVIDE(__start_svc_data = .);
-    KEEP(*(.svc_data))
-    PROVIDE(__stop_svc_data = .);
-  } > RAM
-  
-  .fs_data :
-  {
-    PROVIDE(__start_fs_data = .);
-    KEEP(*(.fs_data))
-    PROVIDE(__stop_fs_data = .);
-  } > RAM
-} INSERT AFTER .data;
-
-INCLUDE "nrf52_common.ld"
diff --git a/tinyusb/hw/bsp/nrf/boards/arduino_nano33_ble/arduino_nano33_ble.ld b/tinyusb/hw/bsp/nrf/boards/arduino_nano33_ble/arduino_nano33_ble.ld
deleted file mode 100755
index f570740b..00000000
--- a/tinyusb/hw/bsp/nrf/boards/arduino_nano33_ble/arduino_nano33_ble.ld
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Linker script to configure memory regions. */
-
-SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
-
-MEMORY
-{
-  FLASH (rx) : ORIGIN = 0x10000, LENGTH = 0xf0000
-  RAM_NVIC (rwx) : ORIGIN = 0x20000000, LENGTH = 0x100
-  RAM_CRASH_DATA (rwx) : ORIGIN = (0x20000000 + 0x100), LENGTH = 0x100
-  RAM (rwx) : ORIGIN = ((0x20000000 + 0x100) + 0x100), LENGTH = (0x40000 - (0x100 + 0x100))
-}
-
-SECTIONS
-{
-  . = ALIGN(4);
-  .svc_data :
-  {
-    PROVIDE(__start_svc_data = .);
-    KEEP(*(.svc_data))
-    PROVIDE(__stop_svc_data = .);
-  } > RAM
-  
-  .fs_data :
-  {
-    PROVIDE(__start_fs_data = .);
-    KEEP(*(.fs_data))
-    PROVIDE(__stop_fs_data = .);
-  } > RAM
-} INSERT AFTER .data;
-
-INCLUDE "nrf52_common.ld"
diff --git a/tinyusb/hw/bsp/nrf/boards/arduino_nano33_ble/board.h b/tinyusb/hw/bsp/nrf/boards/arduino_nano33_ble/board.h
deleted file mode 100755
index d548e01c..00000000
--- a/tinyusb/hw/bsp/nrf/boards/arduino_nano33_ble/board.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define _PINNUM(port, pin)    ((port)*32 + (pin))
-
-// LED
-#define LED_PIN               _PINNUM(0, 24)
-#define LED_STATE_ON          0
-
-// Button
-#define BUTTON_PIN            _PINNUM(1, 11) // D2
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_RX_PIN           _PINNUM(1, 10)
-#define UART_TX_PIN           _PINNUM(1, 3)
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/nrf/boards/arduino_nano33_ble/board.mk b/tinyusb/hw/bsp/nrf/boards/arduino_nano33_ble/board.mk
deleted file mode 100755
index 94babd82..00000000
--- a/tinyusb/hw/bsp/nrf/boards/arduino_nano33_ble/board.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-MCU_VARIANT = nrf52840
-CFLAGS += -DNRF52840_XXAA
-
-LD_FILE = $(BOARD_PATH)/$(BOARD).ld
-
-# flash using bossac (as part of Nano33 BSP tools)
-# can be found in arduino15/packages/arduino/tools/bossac/
-# Add it to your PATH or change BOSSAC variable to match your installation
-BOSSAC = bossac
-
-flash: $(BUILD)/$(PROJECT).bin
-	@:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyACM0)
-	$(BOSSAC) --port=$(SERIAL) -U -i -e -w $^ -R
diff --git a/tinyusb/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.h b/tinyusb/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.h
deleted file mode 100755
index a86c9dc7..00000000
--- a/tinyusb/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define _PINNUM(port, pin)    ((port)*32 + (pin))
-
-// LED
-#define LED_PIN         _PINNUM(1, 14)
-#define LED_STATE_ON    1
-
-// Button
-#define BUTTON_PIN      _PINNUM(1, 15)
-#define BUTTON_STATE_ACTIVE   1
-
-// UART
-#define UART_RX_PIN     30
-#define UART_TX_PIN     14
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.mk b/tinyusb/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.mk
deleted file mode 100755
index f31899eb..00000000
--- a/tinyusb/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-MCU_VARIANT = nrf52840
-CFLAGS += -DNRF52840_XXAA
-
-$(BUILD)/$(PROJECT).zip: $(BUILD)/$(PROJECT).hex
-	adafruit-nrfutil dfu genpkg --dev-type 0x0052 --sd-req 0xFFFE --application $^ $@
-
-# flash using adafruit-nrfutil dfu
-flash: $(BUILD)/$(PROJECT).zip
-	@:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyACM0)
-	adafruit-nrfutil --verbose dfu serial --package $^ -p $(SERIAL) -b 115200 --singlebank --touch 1200
diff --git a/tinyusb/hw/bsp/nrf/boards/circuitplayground_bluefruit/nrf52840_s140_v6.ld b/tinyusb/hw/bsp/nrf/boards/circuitplayground_bluefruit/nrf52840_s140_v6.ld
deleted file mode 100755
index 5314a4e9..00000000
--- a/tinyusb/hw/bsp/nrf/boards/circuitplayground_bluefruit/nrf52840_s140_v6.ld
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Linker script to configure memory regions. */
-
-SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
-
-MEMORY
-{
-  FLASH (rx)     : ORIGIN = 0x26000, LENGTH = 0xED000 - 0x26000
-
-  /* SRAM required by S132 depend on
-   * - Attribute Table Size
-   * - Vendor UUID count
-   * - Max ATT MTU
-   * - Concurrent connection peripheral + central + secure links
-   * - Event Len, HVN queue, Write CMD queue
-   */ 
-  RAM (rwx) :  ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400
-}
-
-SECTIONS
-{
-  . = ALIGN(4);
-  .svc_data :
-  {
-    PROVIDE(__start_svc_data = .);
-    KEEP(*(.svc_data))
-    PROVIDE(__stop_svc_data = .);
-  } > RAM
-  
-  .fs_data :
-  {
-    PROVIDE(__start_fs_data = .);
-    KEEP(*(.fs_data))
-    PROVIDE(__stop_fs_data = .);
-  } > RAM
-} INSERT AFTER .data;
-
-INCLUDE "nrf52_common.ld"
diff --git a/tinyusb/hw/bsp/nrf/boards/feather_nrf52840_express/board.h b/tinyusb/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
deleted file mode 100755
index 3208a948..00000000
--- a/tinyusb/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define _PINNUM(port, pin)    ((port)*32 + (pin))
-
-// LED
-#define LED_PIN         _PINNUM(1, 15)
-#define LED_STATE_ON    1
-
-// Button
-#define BUTTON_PIN      _PINNUM(1, 02)
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_RX_PIN     24
-#define UART_TX_PIN     25
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/nrf/boards/feather_nrf52840_express/board.mk b/tinyusb/hw/bsp/nrf/boards/feather_nrf52840_express/board.mk
deleted file mode 100755
index f31899eb..00000000
--- a/tinyusb/hw/bsp/nrf/boards/feather_nrf52840_express/board.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-MCU_VARIANT = nrf52840
-CFLAGS += -DNRF52840_XXAA
-
-$(BUILD)/$(PROJECT).zip: $(BUILD)/$(PROJECT).hex
-	adafruit-nrfutil dfu genpkg --dev-type 0x0052 --sd-req 0xFFFE --application $^ $@
-
-# flash using adafruit-nrfutil dfu
-flash: $(BUILD)/$(PROJECT).zip
-	@:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyACM0)
-	adafruit-nrfutil --verbose dfu serial --package $^ -p $(SERIAL) -b 115200 --singlebank --touch 1200
diff --git a/tinyusb/hw/bsp/nrf/boards/feather_nrf52840_express/nrf52840_s140_v6.ld b/tinyusb/hw/bsp/nrf/boards/feather_nrf52840_express/nrf52840_s140_v6.ld
deleted file mode 100755
index 5314a4e9..00000000
--- a/tinyusb/hw/bsp/nrf/boards/feather_nrf52840_express/nrf52840_s140_v6.ld
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Linker script to configure memory regions. */
-
-SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
-
-MEMORY
-{
-  FLASH (rx)     : ORIGIN = 0x26000, LENGTH = 0xED000 - 0x26000
-
-  /* SRAM required by S132 depend on
-   * - Attribute Table Size
-   * - Vendor UUID count
-   * - Max ATT MTU
-   * - Concurrent connection peripheral + central + secure links
-   * - Event Len, HVN queue, Write CMD queue
-   */ 
-  RAM (rwx) :  ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400
-}
-
-SECTIONS
-{
-  . = ALIGN(4);
-  .svc_data :
-  {
-    PROVIDE(__start_svc_data = .);
-    KEEP(*(.svc_data))
-    PROVIDE(__stop_svc_data = .);
-  } > RAM
-  
-  .fs_data :
-  {
-    PROVIDE(__start_fs_data = .);
-    KEEP(*(.fs_data))
-    PROVIDE(__stop_fs_data = .);
-  } > RAM
-} INSERT AFTER .data;
-
-INCLUDE "nrf52_common.ld"
diff --git a/tinyusb/hw/bsp/nrf/boards/feather_nrf52840_sense/board.h b/tinyusb/hw/bsp/nrf/boards/feather_nrf52840_sense/board.h
deleted file mode 100755
index ece6e34c..00000000
--- a/tinyusb/hw/bsp/nrf/boards/feather_nrf52840_sense/board.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define _PINNUM(port, pin)    ((port)*32 + (pin))
-
-// LED
-#define LED_PIN         _PINNUM(1, 9)
-#define LED_STATE_ON    1
-
-// Button
-#define BUTTON_PIN      _PINNUM(1, 02)
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_RX_PIN     24
-#define UART_TX_PIN     25
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/nrf/boards/feather_nrf52840_sense/board.mk b/tinyusb/hw/bsp/nrf/boards/feather_nrf52840_sense/board.mk
deleted file mode 100755
index f31899eb..00000000
--- a/tinyusb/hw/bsp/nrf/boards/feather_nrf52840_sense/board.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-MCU_VARIANT = nrf52840
-CFLAGS += -DNRF52840_XXAA
-
-$(BUILD)/$(PROJECT).zip: $(BUILD)/$(PROJECT).hex
-	adafruit-nrfutil dfu genpkg --dev-type 0x0052 --sd-req 0xFFFE --application $^ $@
-
-# flash using adafruit-nrfutil dfu
-flash: $(BUILD)/$(PROJECT).zip
-	@:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyACM0)
-	adafruit-nrfutil --verbose dfu serial --package $^ -p $(SERIAL) -b 115200 --singlebank --touch 1200
diff --git a/tinyusb/hw/bsp/nrf/boards/feather_nrf52840_sense/nrf52840_s140_v6.ld b/tinyusb/hw/bsp/nrf/boards/feather_nrf52840_sense/nrf52840_s140_v6.ld
deleted file mode 100755
index 5314a4e9..00000000
--- a/tinyusb/hw/bsp/nrf/boards/feather_nrf52840_sense/nrf52840_s140_v6.ld
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Linker script to configure memory regions. */
-
-SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
-
-MEMORY
-{
-  FLASH (rx)     : ORIGIN = 0x26000, LENGTH = 0xED000 - 0x26000
-
-  /* SRAM required by S132 depend on
-   * - Attribute Table Size
-   * - Vendor UUID count
-   * - Max ATT MTU
-   * - Concurrent connection peripheral + central + secure links
-   * - Event Len, HVN queue, Write CMD queue
-   */ 
-  RAM (rwx) :  ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400
-}
-
-SECTIONS
-{
-  . = ALIGN(4);
-  .svc_data :
-  {
-    PROVIDE(__start_svc_data = .);
-    KEEP(*(.svc_data))
-    PROVIDE(__stop_svc_data = .);
-  } > RAM
-  
-  .fs_data :
-  {
-    PROVIDE(__start_fs_data = .);
-    KEEP(*(.fs_data))
-    PROVIDE(__stop_fs_data = .);
-  } > RAM
-} INSERT AFTER .data;
-
-INCLUDE "nrf52_common.ld"
diff --git a/tinyusb/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h b/tinyusb/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h
deleted file mode 100755
index 132173a8..00000000
--- a/tinyusb/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define _PINNUM(port, pin)    ((port)*32 + (pin))
-
-// LED
-#define LED_PIN         _PINNUM(0, 6)
-#define LED_STATE_ON    1
-
-// Button
-#define BUTTON_PIN      _PINNUM(0, 29)
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_RX_PIN     25
-#define UART_TX_PIN     24
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.mk b/tinyusb/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.mk
deleted file mode 100755
index f31899eb..00000000
--- a/tinyusb/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-MCU_VARIANT = nrf52840
-CFLAGS += -DNRF52840_XXAA
-
-$(BUILD)/$(PROJECT).zip: $(BUILD)/$(PROJECT).hex
-	adafruit-nrfutil dfu genpkg --dev-type 0x0052 --sd-req 0xFFFE --application $^ $@
-
-# flash using adafruit-nrfutil dfu
-flash: $(BUILD)/$(PROJECT).zip
-	@:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyACM0)
-	adafruit-nrfutil --verbose dfu serial --package $^ -p $(SERIAL) -b 115200 --singlebank --touch 1200
diff --git a/tinyusb/hw/bsp/nrf/boards/itsybitsy_nrf52840/nrf52840_s140_v6.ld b/tinyusb/hw/bsp/nrf/boards/itsybitsy_nrf52840/nrf52840_s140_v6.ld
deleted file mode 100755
index 5314a4e9..00000000
--- a/tinyusb/hw/bsp/nrf/boards/itsybitsy_nrf52840/nrf52840_s140_v6.ld
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Linker script to configure memory regions. */
-
-SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
-
-MEMORY
-{
-  FLASH (rx)     : ORIGIN = 0x26000, LENGTH = 0xED000 - 0x26000
-
-  /* SRAM required by S132 depend on
-   * - Attribute Table Size
-   * - Vendor UUID count
-   * - Max ATT MTU
-   * - Concurrent connection peripheral + central + secure links
-   * - Event Len, HVN queue, Write CMD queue
-   */ 
-  RAM (rwx) :  ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400
-}
-
-SECTIONS
-{
-  . = ALIGN(4);
-  .svc_data :
-  {
-    PROVIDE(__start_svc_data = .);
-    KEEP(*(.svc_data))
-    PROVIDE(__stop_svc_data = .);
-  } > RAM
-  
-  .fs_data :
-  {
-    PROVIDE(__start_fs_data = .);
-    KEEP(*(.fs_data))
-    PROVIDE(__stop_fs_data = .);
-  } > RAM
-} INSERT AFTER .data;
-
-INCLUDE "nrf52_common.ld"
diff --git a/tinyusb/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h b/tinyusb/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h
deleted file mode 100755
index 01dd1f24..00000000
--- a/tinyusb/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define _PINNUM(port, pin)    ((port)*32 + (pin))
-
-// LED
-#define LED_PIN               _PINNUM(0, 23)
-#define LED_STATE_ON          0
-
-// Button
-#define BUTTON_PIN            _PINNUM(0, 18)
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_RX_PIN           2
-#define UART_TX_PIN           3
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.mk b/tinyusb/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.mk
deleted file mode 100755
index 3afa234a..00000000
--- a/tinyusb/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-MCU_VARIANT = nrf52840
-CFLAGS += -DNRF52840_XXAA
-
-LD_FILE = $(BOARD_PATH)/$(BOARD).ld
-
-# flash using Nordic nrfutil (pip3 install nrfutil)
-# 	make BOARD=nrf52840_mdk_dongle SERIAL=/dev/ttyACM0 all flash
-NRFUTIL = nrfutil
-
-$(BUILD)/$(PROJECT).zip: $(BUILD)/$(PROJECT).hex
-	$(NRFUTIL) pkg generate --hw-version 52 --sd-req 0x0000 --debug-mode --application $^ $@
-
-flash: $(BUILD)/$(PROJECT).zip
-	@:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyACM0)
-	$(NRFUTIL) dfu usb-serial --package $^ -p $(SERIAL) -b 115200
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/nrf/boards/nrf52840_mdk_dongle/nrf52840_mdk_dongle.ld b/tinyusb/hw/bsp/nrf/boards/nrf52840_mdk_dongle/nrf52840_mdk_dongle.ld
deleted file mode 100755
index 78eddc9c..00000000
--- a/tinyusb/hw/bsp/nrf/boards/nrf52840_mdk_dongle/nrf52840_mdk_dongle.ld
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Linker script to configure memory regions. */
-
-SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
-
-MEMORY
-{
-  FLASH (rx) : ORIGIN = 0x1000, LENGTH = 0xE0000-0x1000
-  RAM (rwx) :  ORIGIN = 0x20000008, LENGTH = 0x3fff8
-}
-
-
-INCLUDE "nrf_common.ld"
diff --git a/tinyusb/hw/bsp/nrf/boards/pca10056/board.h b/tinyusb/hw/bsp/nrf/boards/pca10056/board.h
deleted file mode 100755
index ab12d21a..00000000
--- a/tinyusb/hw/bsp/nrf/boards/pca10056/board.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PIN               13
-#define LED_STATE_ON          0
-
-// Button
-#define BUTTON_PIN            11
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_RX_PIN           8
-#define UART_TX_PIN           6
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/nrf/boards/pca10056/board.mk b/tinyusb/hw/bsp/nrf/boards/pca10056/board.mk
deleted file mode 100755
index be2ed331..00000000
--- a/tinyusb/hw/bsp/nrf/boards/pca10056/board.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-MCU_VARIANT = nrf52840
-CFLAGS += -DNRF52840_XXAA
-
-LD_FILE = hw/mcu/nordic/nrfx/mdk/nrf52840_xxaa.ld
-
-# flash using jlink
-flash: flash-jlink
diff --git a/tinyusb/hw/bsp/nrf/boards/pca10059/board.h b/tinyusb/hw/bsp/nrf/boards/pca10059/board.h
deleted file mode 100755
index 0810be64..00000000
--- a/tinyusb/hw/bsp/nrf/boards/pca10059/board.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define _PINNUM(port, pin)    ((port)*32 + (pin))
-
-// LED
-#define LED_PIN               8
-#define LED_STATE_ON          0
-
-// Button
-#define BUTTON_PIN            _PINNUM(1, 6)
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_RX_PIN           8
-#define UART_TX_PIN           6
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/nrf/boards/pca10059/board.mk b/tinyusb/hw/bsp/nrf/boards/pca10059/board.mk
deleted file mode 100755
index 0b82ecdb..00000000
--- a/tinyusb/hw/bsp/nrf/boards/pca10059/board.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-MCU_VARIANT = nrf52840
-CFLAGS += -DNRF52840_XXAA
-
-LD_FILE = $(BOARD_PATH)/$(BOARD).ld
-
-# flash using Nordic nrfutil (pip2 install nrfutil)
-# 	make BOARD=pca10059 SERIAL=/dev/ttyACM0 all flash
-NRFUTIL = nrfutil
-
-$(BUILD)/$(PROJECT).zip: $(BUILD)/$(PROJECT).hex
-	$(NRFUTIL) pkg generate --hw-version 52 --sd-req 0x0000 --debug-mode --application $^ $@
-
-flash: $(BUILD)/$(PROJECT).zip
-	@:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyACM0)
-	$(NRFUTIL) dfu usb-serial --package $^ -p $(SERIAL) -b 115200
diff --git a/tinyusb/hw/bsp/nrf/boards/pca10059/pca10059.ld b/tinyusb/hw/bsp/nrf/boards/pca10059/pca10059.ld
deleted file mode 100755
index 510bfdd8..00000000
--- a/tinyusb/hw/bsp/nrf/boards/pca10059/pca10059.ld
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Linker script to configure memory regions. */
-
-SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
-
-MEMORY
-{
-  FLASH (rx) : ORIGIN = 0x1000, LENGTH = 0xff000
-  RAM (rwx) :  ORIGIN = 0x20000008, LENGTH = 0x3fff8
-}
-
-
-INCLUDE "nrf_common.ld"
diff --git a/tinyusb/hw/bsp/nrf/boards/pca10100/board.h b/tinyusb/hw/bsp/nrf/boards/pca10100/board.h
deleted file mode 100755
index 88113303..00000000
--- a/tinyusb/hw/bsp/nrf/boards/pca10100/board.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define _PINNUM(port, pin)    ((port)*32 + (pin))
-
-// LED
-#define LED_PIN               13
-#define LED_STATE_ON          0
-
-// Button
-#define BUTTON_PIN            11
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_RX_PIN           8
-#define UART_TX_PIN           6
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/nrf/boards/pca10100/board.mk b/tinyusb/hw/bsp/nrf/boards/pca10100/board.mk
deleted file mode 100755
index 5fba269b..00000000
--- a/tinyusb/hw/bsp/nrf/boards/pca10100/board.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-MCU_VARIANT = nrf52833
-CFLAGS += -DNRF52833_XXAA
-
-LD_FILE = hw/mcu/nordic/nrfx/mdk/nrf52833_xxaa.ld
-
-# flash using jlink
-flash: flash-jlink
diff --git a/tinyusb/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h b/tinyusb/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h
deleted file mode 100755
index dcf829d9..00000000
--- a/tinyusb/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define _PINNUM(port, pin)    ((port)*32 + (pin))
-
-// LED
-#define LED_PIN               _PINNUM(1, 13)
-#define LED_STATE_ON          0
-
-// Button
-#define BUTTON_PIN            _PINNUM(0, 15)
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_RX_PIN     25
-#define UART_TX_PIN     24
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.mk b/tinyusb/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.mk
deleted file mode 100755
index be2ed331..00000000
--- a/tinyusb/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-MCU_VARIANT = nrf52840
-CFLAGS += -DNRF52840_XXAA
-
-LD_FILE = hw/mcu/nordic/nrfx/mdk/nrf52840_xxaa.ld
-
-# flash using jlink
-flash: flash-jlink
diff --git a/tinyusb/hw/bsp/nrf/family.c b/tinyusb/hw/bsp/nrf/family.c
deleted file mode 100755
index ed742daa..00000000
--- a/tinyusb/hw/bsp/nrf/family.c
+++ /dev/null
@@ -1,224 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "bsp/board.h"
-#include "board.h"
-
-#include "nrfx.h"
-#include "nrfx/hal/nrf_gpio.h"
-#include "nrfx/drivers/include/nrfx_power.h"
-#include "nrfx/drivers/include/nrfx_uarte.h"
-
-#ifdef SOFTDEVICE_PRESENT
-#include "nrf_sdm.h"
-#include "nrf_soc.h"
-#endif
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USBD_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-/*------------------------------------------------------------------*/
-/* MACRO TYPEDEF CONSTANT ENUM
- *------------------------------------------------------------------*/
-
-static nrfx_uarte_t _uart_id = NRFX_UARTE_INSTANCE(0);
-
-// tinyusb function that handles power event (detected, ready, removed)
-// We must call it within SD's SOC event handler, or set it as power event handler if SD is not enabled.
-extern void tusb_hal_nrf_power_event(uint32_t event);
-
-
-// nrf power callback, could be unused if SD is enabled or usb is disabled (board_test example)
-TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event)
-{
-  tusb_hal_nrf_power_event((uint32_t) event);
-}
-
-void board_init(void)
-{
-  // stop LF clock just in case we jump from application without reset
-  NRF_CLOCK->TASKS_LFCLKSTOP = 1UL;
-
-  // Use Internal OSC to compatible with all boards
-  NRF_CLOCK->LFCLKSRC = CLOCK_LFCLKSRC_SRC_RC;
-  NRF_CLOCK->TASKS_LFCLKSTART = 1UL;
-
-  // LED
-  nrf_gpio_cfg_output(LED_PIN);
-  board_led_write(false);
-
-  // Button
-  nrf_gpio_cfg_input(BUTTON_PIN, NRF_GPIO_PIN_PULLUP);
-
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock/1000);
-
-  // UART
-  nrfx_uarte_config_t uart_cfg =
-  {
-    .pseltxd   = UART_TX_PIN,
-    .pselrxd   = UART_RX_PIN,
-    .pselcts   = NRF_UARTE_PSEL_DISCONNECTED,
-    .pselrts   = NRF_UARTE_PSEL_DISCONNECTED,
-    .p_context = NULL,
-    .baudrate  = NRF_UARTE_BAUDRATE_115200, // CFG_BOARD_UART_BAUDRATE
-    .interrupt_priority = 7,
-    .hal_cfg = {
-      .hwfc      = NRF_UARTE_HWFC_DISABLED,
-      .parity    = NRF_UARTE_PARITY_EXCLUDED,
-    }
-  };
-
-  nrfx_uarte_init(&_uart_id, &uart_cfg, NULL); //uart_handler);
-
-  //------------- USB -------------//
-#if TUSB_OPT_DEVICE_ENABLED
-  // Priorities 0, 1, 4 (nRF52) are reserved for SoftDevice
-  // 2 is highest for application
-  NVIC_SetPriority(USBD_IRQn, 2);
-
-  // USB power may already be ready at this time -> no event generated
-  // We need to invoke the handler based on the status initially
-  uint32_t usb_reg;
-
-#ifdef SOFTDEVICE_PRESENT
-  uint8_t sd_en = false;
-  sd_softdevice_is_enabled(&sd_en);
-
-  if ( sd_en ) {
-    sd_power_usbdetected_enable(true);
-    sd_power_usbpwrrdy_enable(true);
-    sd_power_usbremoved_enable(true);
-
-    sd_power_usbregstatus_get(&usb_reg);
-  }else
-#endif
-  {
-    // Power module init
-    const nrfx_power_config_t pwr_cfg = { 0 };
-    nrfx_power_init(&pwr_cfg);
-
-    // Register tusb function as USB power handler
-    // cause cast-function-type warning
-    const nrfx_power_usbevt_config_t config = { .handler = power_event_handler };
-    nrfx_power_usbevt_init(&config);
-
-    nrfx_power_usbevt_enable();
-
-    usb_reg = NRF_POWER->USBREGSTATUS;
-  }
-
-  if ( usb_reg & POWER_USBREGSTATUS_VBUSDETECT_Msk ) tusb_hal_nrf_power_event(NRFX_POWER_USB_EVT_DETECTED);
-  if ( usb_reg & POWER_USBREGSTATUS_OUTPUTRDY_Msk  ) tusb_hal_nrf_power_event(NRFX_POWER_USB_EVT_READY);
-#endif
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  nrf_gpio_pin_write(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == nrf_gpio_pin_read(BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-//  return NRFX_SUCCESS == nrfx_uart_rx(&_uart_id, buf, (size_t) len) ? len : 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  return (NRFX_SUCCESS == nrfx_uarte_tx(&_uart_id, (uint8_t const*) buf, (size_t) len)) ? len : 0;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-
-#ifdef SOFTDEVICE_PRESENT
-// process SOC event from SD
-uint32_t proc_soc(void)
-{
-  uint32_t soc_evt;
-  uint32_t err = sd_evt_get(&soc_evt);
-
-  if (NRF_SUCCESS == err)
-  {
-    /*------------- usb power event handler -------------*/
-    int32_t usbevt = (soc_evt == NRF_EVT_POWER_USB_DETECTED   ) ? NRFX_POWER_USB_EVT_DETECTED:
-                     (soc_evt == NRF_EVT_POWER_USB_POWER_READY) ? NRFX_POWER_USB_EVT_READY   :
-                     (soc_evt == NRF_EVT_POWER_USB_REMOVED    ) ? NRFX_POWER_USB_EVT_REMOVED : -1;
-
-    if ( usbevt >= 0) tusb_hal_nrf_power_event(usbevt);
-  }
-
-  return err;
-}
-
-uint32_t proc_ble(void)
-{
-  // do nothing with ble
-  return NRF_ERROR_NOT_FOUND;
-}
-
-void SD_EVT_IRQHandler(void)
-{
-  // process BLE and SOC until there is no more events
-  while( (NRF_ERROR_NOT_FOUND != proc_ble()) || (NRF_ERROR_NOT_FOUND != proc_soc()) )
-  {
-
-  }
-}
-
-void nrf_error_cb(uint32_t id, uint32_t pc, uint32_t info)
-{
-  (void) id;
-  (void) pc;
-  (void) info;
-}
-#endif
diff --git a/tinyusb/hw/bsp/nrf/family.mk b/tinyusb/hw/bsp/nrf/family.mk
deleted file mode 100755
index d1afd258..00000000
--- a/tinyusb/hw/bsp/nrf/family.mk
+++ /dev/null
@@ -1,60 +0,0 @@
-UF2_FAMILY_ID = 0xADA52840
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/nordic/nrfx
-
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -DCFG_TUSB_MCU=OPT_MCU_NRF5X \
-  -DCONFIG_GPIO_AS_PINRESET
-
-# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=undef -Wno-error=unused-parameter -Wno-error=cast-align
-
-# due to tusb_hal_nrf_power_event
-GCCVERSION = $(firstword $(subst ., ,$(shell arm-none-eabi-gcc -dumpversion)))
-ifeq ($(CMDEXE),1)
-  ifeq ($(shell if $(GCCVERSION) geq 8 echo 1), 1)
-  CFLAGS += -Wno-error=cast-function-type
-  endif
-else
-  ifeq ($(shell expr $(GCCVERSION) \>= 8), 1)
-  CFLAGS += -Wno-error=cast-function-type
-  endif
-endif
-
-# All source paths should be relative to the top level.
-LD_FILE ?= hw/bsp/nrf/boards/$(BOARD)/nrf52840_s140_v6.ld
-
-LDFLAGS += -L$(TOP)/hw/mcu/nordic/nrfx/mdk
-
-SRC_C += \
-  src/portable/nordic/nrf5x/dcd_nrf5x.c \
-  hw/mcu/nordic/nrfx/drivers/src/nrfx_power.c \
-  hw/mcu/nordic/nrfx/drivers/src/nrfx_uarte.c \
-  hw/mcu/nordic/nrfx/mdk/system_$(MCU_VARIANT).c
-
-INC += \
-  $(TOP)/$(BOARD_PATH) \
-  $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-  $(TOP)/hw/mcu/nordic \
-  $(TOP)/hw/mcu/nordic/nrfx \
-  $(TOP)/hw/mcu/nordic/nrfx/mdk \
-  $(TOP)/hw/mcu/nordic/nrfx/hal \
-  $(TOP)/hw/mcu/nordic/nrfx/drivers/include \
-  $(TOP)/hw/mcu/nordic/nrfx/drivers/src \
-
-SRC_S += hw/mcu/nordic/nrfx/mdk/gcc_startup_$(MCU_VARIANT).S
-
-ASFLAGS += -D__HEAP_SIZE=0
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = $(MCU_VARIANT)_xxaa
diff --git a/tinyusb/hw/bsp/nutiny_nuc121s/board.mk b/tinyusb/hw/bsp/nutiny_nuc121s/board.mk
deleted file mode 100755
index a0a208ca..00000000
--- a/tinyusb/hw/bsp/nutiny_nuc121s/board.mk
+++ /dev/null
@@ -1,55 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nuvoton
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs-linux \
-  -mcpu=cortex-m0 \
-  -D__ARM_FEATURE_DSP=0 \
-  -DUSE_ASSERT=0 \
-  -DCFG_EXAMPLE_MSC_READONLY \
-  -DCFG_TUSB_MCU=OPT_MCU_NUC121
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/nuc121_flash.ld
-
-SRC_C += \
-  src/portable/nuvoton/nuc121/dcd_nuc121.c \
-  hw/mcu/nuvoton/nuc121_125/Device/Nuvoton/NUC121/Source/system_NUC121.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/adc.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/bpwm.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/clk.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/fmc.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/gpio.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/i2c.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/pdma.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/pwm.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/spi_i2s.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/sys.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/timer.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/uart.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/usbd.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/usci_i2c.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/usci_spi.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/usci_uart.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/wdt.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/wwdt.c
-
-SRC_S += \
-  hw/mcu/nuvoton/nuc121_125/Device/Nuvoton/NUC121/Source/GCC/startup_NUC121.S
-
-INC += \
-  $(TOP)/hw/mcu/nuvoton/nuc121_125/Device/Nuvoton/NUC121/Include \
-  $(TOP)/hw/mcu/nuvoton/nuc121_125/StdDriver/inc \
-  $(TOP)/hw/mcu/nuvoton/nuc121_125/CMSIS/Include
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
-
-# For flash-jlink target
-JLINK_DEVICE = NUC121SC2AE
-
-# Flash using Nuvoton's openocd fork at https://github.com/OpenNuvoton/OpenOCD-Nuvoton
-# Please compile and install it from github source
-flash: $(BUILD)/$(PROJECT).elf
-	openocd -f interface/nulink.cfg -f target/numicroM0.cfg -c "program $< reset exit"
diff --git a/tinyusb/hw/bsp/nutiny_nuc121s/nuc121_flash.ld b/tinyusb/hw/bsp/nutiny_nuc121s/nuc121_flash.ld
deleted file mode 100755
index 3966b276..00000000
--- a/tinyusb/hw/bsp/nutiny_nuc121s/nuc121_flash.ld
+++ /dev/null
@@ -1,195 +0,0 @@
-/* Linker script to configure memory regions. */
-MEMORY
-{
-  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x8000    /* 32k */
-  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 0x2000    /* 8k  */
-}
-
-/* Library configurations */
-GROUP(libgcc.a libc.a libm.a libnosys.a)
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __copy_table_start__
- *   __copy_table_end__
- *   __zero_table_start__
- *   __zero_table_end__
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __end__
- *   end
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   __Vectors_End
- *   __Vectors_Size
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
-	.text :
-	{
-		KEEP(*(.vectors))
-		__Vectors_End = .;
-		__Vectors_Size = __Vectors_End - __Vectors;
-		__end__ = .;
-
-		*(.text*)
-
-		KEEP(*(.init))
-		KEEP(*(.fini))
-
-		/* .ctors */
-		*crtbegin.o(.ctors)
-		*crtbegin?.o(.ctors)
-		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-		*(SORT(.ctors.*))
-		*(.ctors)
-
-		/* .dtors */
- 		*crtbegin.o(.dtors)
- 		*crtbegin?.o(.dtors)
- 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
- 		*(SORT(.dtors.*))
- 		*(.dtors)
-        
-		*(.rodata*)
-
-		KEEP(*(.eh_frame*))
-	} > FLASH
-
-	.ARM.extab :
-	{
-		*(.ARM.extab* .gnu.linkonce.armextab.*)
-	} > FLASH
-
-	__exidx_start = .;
-	.ARM.exidx :
-	{
-		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
-	} > FLASH
-	__exidx_end = .;
-
-	/* To copy multiple ROM to RAM sections,
-	 * uncomment .copy.table section and,
-	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
-	/*
-	.copy.table :
-	{
-		. = ALIGN(4);
-		__copy_table_start__ = .;
-		LONG (__etext)
-		LONG (__data_start__)
-		LONG (__data_end__ - __data_start__)
-		LONG (__etext2)
-		LONG (__data2_start__)
-		LONG (__data2_end__ - __data2_start__)
-		__copy_table_end__ = .;
-	} > FLASH
-	*/
-
-	/* To clear multiple BSS sections,
-	 * uncomment .zero.table section and,
-	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
-	/*
-	.zero.table :
-	{
-		. = ALIGN(4);
-		__zero_table_start__ = .;
-		LONG (__bss_start__)
-		LONG (__bss_end__ - __bss_start__)
-		LONG (__bss2_start__)
-		LONG (__bss2_end__ - __bss2_start__)
-		__zero_table_end__ = .;
-	} > FLASH
-	*/
-
-	__etext = .;
-
-	.data : AT (__etext)
-	{
-		__data_start__ = .;
-		*(vtable)
-		*(.data*)
-
-		. = ALIGN(4);
-		/* preinit data */
-		PROVIDE_HIDDEN (__preinit_array_start = .);
-		KEEP(*(.preinit_array))
-		PROVIDE_HIDDEN (__preinit_array_end = .);
-
-		. = ALIGN(4);
-		/* init data */
-		PROVIDE_HIDDEN (__init_array_start = .);
-		KEEP(*(SORT(.init_array.*)))
-		KEEP(*(.init_array))
-		PROVIDE_HIDDEN (__init_array_end = .);
-
-
-		. = ALIGN(4);
-		/* finit data */
-		PROVIDE_HIDDEN (__fini_array_start = .);
-		KEEP(*(SORT(.fini_array.*)))
-		KEEP(*(.fini_array))
-		PROVIDE_HIDDEN (__fini_array_end = .);
-
-		KEEP(*(.jcr*))
-		. = ALIGN(4);
-		/* All data end */
-		__data_end__ = .;
-
-	} > RAM
-
-	.bss :
-	{
-		. = ALIGN(4);
-		__bss_start__ = .;
-		*(.bss*)
-		*(COMMON)
-		. = ALIGN(4);
-		__bss_end__ = .;
-	} > RAM
-
-	.heap (COPY):
-	{
-		__HeapBase = .;
-		__end__ = .;
-		end = __end__;
-		KEEP(*(.heap*))
-		__HeapLimit = .;
-	} > RAM
-
-	/* .stack_dummy section doesn't contains any symbols. It is only
-	 * used for linker to calculate size of stack sections, and assign
-	 * values to stack symbols later */
-	.stack_dummy (COPY):
-	{
-		KEEP(*(.stack*))
-	} > RAM
-
-	/* Set stack top to end of RAM, and stack limit move down by
-	 * size of stack_dummy section */
-	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
-	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
-	PROVIDE(__stack = __StackTop);
-
-	/* Check if data + heap + stack exceeds RAM limit */
-	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}
diff --git a/tinyusb/hw/bsp/nutiny_nuc121s/nutiny_nuc121.c b/tinyusb/hw/bsp/nutiny_nuc121s/nutiny_nuc121.c
deleted file mode 100755
index 7117a342..00000000
--- a/tinyusb/hw/bsp/nutiny_nuc121s/nutiny_nuc121.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "bsp/board.h"
-#include "NuMicro.h"
-#include "clk.h"
-#include "sys.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USBD_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-#define LED_PORT              PB
-#define LED_PIN               4
-#define LED_PIN_IO            PB4
-#define LED_STATE_ON          0
-
-void board_init(void)
-{
-  /* Unlock protected registers */
-  SYS_UnlockReg();
-
-  /*---------------------------------------------------------------------------------------------------------*/
-  /* Init System Clock                                                                                       */
-  /*---------------------------------------------------------------------------------------------------------*/
-
-  /* Enable Internal HIRC 48 MHz clock */
-  CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN);
-
-  /* Waiting for Internal RC clock ready */
-  CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
-
-  /* Switch HCLK clock source to Internal HIRC and HCLK source divide 1 */
-  CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
-
-  /* Enable module clock */
-  CLK_EnableModuleClock(USBD_MODULE);
-
-  /* Select module clock source */
-  CLK_SetModuleClock(USBD_MODULE, CLK_CLKSEL3_USBDSEL_HIRC, CLK_CLKDIV0_USB(1));
-
-  /* Enable module clock */
-  CLK_EnableModuleClock(USBD_MODULE);
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(48000000 / 1000);
-#endif
-
-  // LED
-  GPIO_SetMode(LED_PORT, 1 << LED_PIN, GPIO_MODE_OUTPUT);
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  LED_PIN_IO = (state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return 0;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
diff --git a/tinyusb/hw/bsp/nutiny_nuc125s/board.mk b/tinyusb/hw/bsp/nutiny_nuc125s/board.mk
deleted file mode 100755
index bb56e42a..00000000
--- a/tinyusb/hw/bsp/nutiny_nuc125s/board.mk
+++ /dev/null
@@ -1,39 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nuvoton
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs-linux \
-  -mcpu=cortex-m0 \
-  -D__ARM_FEATURE_DSP=0 \
-  -DUSE_ASSERT=0 \
-  -DCFG_EXAMPLE_MSC_READONLY \
-  -DCFG_TUSB_MCU=OPT_MCU_NUC121
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/nuc125_flash.ld
-
-SRC_C += \
-  src/portable/nuvoton/nuc121/dcd_nuc121.c \
-  hw/mcu/nuvoton/nuc121_125/Device/Nuvoton/NUC121/Source/system_NUC121.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/clk.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/gpio.c
-
-SRC_S += \
-  hw/mcu/nuvoton/nuc121_125/Device/Nuvoton/NUC121/Source/GCC/startup_NUC121.S
-
-INC += \
-  $(TOP)/hw/mcu/nuvoton/nuc121_125/Device/Nuvoton/NUC121/Include \
-  $(TOP)/hw/mcu/nuvoton/nuc121_125/StdDriver/inc \
-  $(TOP)/hw/mcu/nuvoton/nuc121_125/CMSIS/Include
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
-
-# For flash-jlink target
-JLINK_DEVICE = NUC125SC2AE
-
-# Flash using Nuvoton's openocd fork at https://github.com/OpenNuvoton/OpenOCD-Nuvoton
-# Please compile and install it from github source
-flash: $(BUILD)/$(PROJECT).elf
-	openocd -f interface/nulink.cfg -f target/numicroM0.cfg -c "program $< reset exit"
diff --git a/tinyusb/hw/bsp/nutiny_nuc125s/nuc125_flash.ld b/tinyusb/hw/bsp/nutiny_nuc125s/nuc125_flash.ld
deleted file mode 100755
index 3966b276..00000000
--- a/tinyusb/hw/bsp/nutiny_nuc125s/nuc125_flash.ld
+++ /dev/null
@@ -1,195 +0,0 @@
-/* Linker script to configure memory regions. */
-MEMORY
-{
-  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x8000    /* 32k */
-  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 0x2000    /* 8k  */
-}
-
-/* Library configurations */
-GROUP(libgcc.a libc.a libm.a libnosys.a)
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __copy_table_start__
- *   __copy_table_end__
- *   __zero_table_start__
- *   __zero_table_end__
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __end__
- *   end
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   __Vectors_End
- *   __Vectors_Size
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
-	.text :
-	{
-		KEEP(*(.vectors))
-		__Vectors_End = .;
-		__Vectors_Size = __Vectors_End - __Vectors;
-		__end__ = .;
-
-		*(.text*)
-
-		KEEP(*(.init))
-		KEEP(*(.fini))
-
-		/* .ctors */
-		*crtbegin.o(.ctors)
-		*crtbegin?.o(.ctors)
-		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-		*(SORT(.ctors.*))
-		*(.ctors)
-
-		/* .dtors */
- 		*crtbegin.o(.dtors)
- 		*crtbegin?.o(.dtors)
- 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
- 		*(SORT(.dtors.*))
- 		*(.dtors)
-        
-		*(.rodata*)
-
-		KEEP(*(.eh_frame*))
-	} > FLASH
-
-	.ARM.extab :
-	{
-		*(.ARM.extab* .gnu.linkonce.armextab.*)
-	} > FLASH
-
-	__exidx_start = .;
-	.ARM.exidx :
-	{
-		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
-	} > FLASH
-	__exidx_end = .;
-
-	/* To copy multiple ROM to RAM sections,
-	 * uncomment .copy.table section and,
-	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
-	/*
-	.copy.table :
-	{
-		. = ALIGN(4);
-		__copy_table_start__ = .;
-		LONG (__etext)
-		LONG (__data_start__)
-		LONG (__data_end__ - __data_start__)
-		LONG (__etext2)
-		LONG (__data2_start__)
-		LONG (__data2_end__ - __data2_start__)
-		__copy_table_end__ = .;
-	} > FLASH
-	*/
-
-	/* To clear multiple BSS sections,
-	 * uncomment .zero.table section and,
-	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
-	/*
-	.zero.table :
-	{
-		. = ALIGN(4);
-		__zero_table_start__ = .;
-		LONG (__bss_start__)
-		LONG (__bss_end__ - __bss_start__)
-		LONG (__bss2_start__)
-		LONG (__bss2_end__ - __bss2_start__)
-		__zero_table_end__ = .;
-	} > FLASH
-	*/
-
-	__etext = .;
-
-	.data : AT (__etext)
-	{
-		__data_start__ = .;
-		*(vtable)
-		*(.data*)
-
-		. = ALIGN(4);
-		/* preinit data */
-		PROVIDE_HIDDEN (__preinit_array_start = .);
-		KEEP(*(.preinit_array))
-		PROVIDE_HIDDEN (__preinit_array_end = .);
-
-		. = ALIGN(4);
-		/* init data */
-		PROVIDE_HIDDEN (__init_array_start = .);
-		KEEP(*(SORT(.init_array.*)))
-		KEEP(*(.init_array))
-		PROVIDE_HIDDEN (__init_array_end = .);
-
-
-		. = ALIGN(4);
-		/* finit data */
-		PROVIDE_HIDDEN (__fini_array_start = .);
-		KEEP(*(SORT(.fini_array.*)))
-		KEEP(*(.fini_array))
-		PROVIDE_HIDDEN (__fini_array_end = .);
-
-		KEEP(*(.jcr*))
-		. = ALIGN(4);
-		/* All data end */
-		__data_end__ = .;
-
-	} > RAM
-
-	.bss :
-	{
-		. = ALIGN(4);
-		__bss_start__ = .;
-		*(.bss*)
-		*(COMMON)
-		. = ALIGN(4);
-		__bss_end__ = .;
-	} > RAM
-
-	.heap (COPY):
-	{
-		__HeapBase = .;
-		__end__ = .;
-		end = __end__;
-		KEEP(*(.heap*))
-		__HeapLimit = .;
-	} > RAM
-
-	/* .stack_dummy section doesn't contains any symbols. It is only
-	 * used for linker to calculate size of stack sections, and assign
-	 * values to stack symbols later */
-	.stack_dummy (COPY):
-	{
-		KEEP(*(.stack*))
-	} > RAM
-
-	/* Set stack top to end of RAM, and stack limit move down by
-	 * size of stack_dummy section */
-	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
-	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
-	PROVIDE(__stack = __StackTop);
-
-	/* Check if data + heap + stack exceeds RAM limit */
-	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}
diff --git a/tinyusb/hw/bsp/nutiny_nuc125s/nutiny_nuc125.c b/tinyusb/hw/bsp/nutiny_nuc125s/nutiny_nuc125.c
deleted file mode 100755
index 7117a342..00000000
--- a/tinyusb/hw/bsp/nutiny_nuc125s/nutiny_nuc125.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "bsp/board.h"
-#include "NuMicro.h"
-#include "clk.h"
-#include "sys.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USBD_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-#define LED_PORT              PB
-#define LED_PIN               4
-#define LED_PIN_IO            PB4
-#define LED_STATE_ON          0
-
-void board_init(void)
-{
-  /* Unlock protected registers */
-  SYS_UnlockReg();
-
-  /*---------------------------------------------------------------------------------------------------------*/
-  /* Init System Clock                                                                                       */
-  /*---------------------------------------------------------------------------------------------------------*/
-
-  /* Enable Internal HIRC 48 MHz clock */
-  CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN);
-
-  /* Waiting for Internal RC clock ready */
-  CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
-
-  /* Switch HCLK clock source to Internal HIRC and HCLK source divide 1 */
-  CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
-
-  /* Enable module clock */
-  CLK_EnableModuleClock(USBD_MODULE);
-
-  /* Select module clock source */
-  CLK_SetModuleClock(USBD_MODULE, CLK_CLKSEL3_USBDSEL_HIRC, CLK_CLKDIV0_USB(1));
-
-  /* Enable module clock */
-  CLK_EnableModuleClock(USBD_MODULE);
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(48000000 / 1000);
-#endif
-
-  // LED
-  GPIO_SetMode(LED_PORT, 1 << LED_PIN, GPIO_MODE_OUTPUT);
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  LED_PIN_IO = (state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return 0;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
diff --git a/tinyusb/hw/bsp/nutiny_nuc126v/board.mk b/tinyusb/hw/bsp/nutiny_nuc126v/board.mk
deleted file mode 100755
index 848b19f9..00000000
--- a/tinyusb/hw/bsp/nutiny_nuc126v/board.mk
+++ /dev/null
@@ -1,59 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nuvoton
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs-linux \
-  -mcpu=cortex-m0 \
-  -D__ARM_FEATURE_DSP=0 \
-  -DUSE_ASSERT=0 \
-  -D__CORTEX_SC=0 \
-  -DCFG_TUSB_MCU=OPT_MCU_NUC126
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/nuc126_flash.ld
-
-SRC_C += \
-  src/portable/nuvoton/nuc121/dcd_nuc121.c \
-  hw/mcu/nuvoton/nuc126/Device/Nuvoton/NUC126/Source/system_NUC126.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/acmp.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/adc.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/clk.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/crc.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/ebi.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/fmc.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/gpio.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/pdma.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/pwm.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/rtc.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/sc.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/scuart.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/spi.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/sys.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/timer.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/timer_pwm.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/uart.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/usbd.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/usci_spi.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/usci_uart.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/wdt.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/wwdt.c
-
-SRC_S += \
-  hw/mcu/nuvoton/nuc126/Device/Nuvoton/NUC126/Source/GCC/startup_NUC126.S
-
-INC += \
-  $(TOP)/hw/mcu/nuvoton/nuc126/Device/Nuvoton/NUC126/Include \
-  $(TOP)/hw/mcu/nuvoton/nuc126/StdDriver/inc \
-  $(TOP)/hw/mcu/nuvoton/nuc126/CMSIS/Include
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
-
-# For flash-jlink target
-JLINK_DEVICE = NUC126VG4AE
-
-# Flash using Nuvoton's openocd fork at https://github.com/OpenNuvoton/OpenOCD-Nuvoton
-# Please compile and install it from github source
-flash: $(BUILD)/$(PROJECT).elf
-	openocd -f interface/nulink.cfg -f target/numicroM0.cfg -c "program $< reset exit"
diff --git a/tinyusb/hw/bsp/nutiny_nuc126v/nuc126_flash.ld b/tinyusb/hw/bsp/nutiny_nuc126v/nuc126_flash.ld
deleted file mode 100755
index b23890b4..00000000
--- a/tinyusb/hw/bsp/nutiny_nuc126v/nuc126_flash.ld
+++ /dev/null
@@ -1,195 +0,0 @@
-/* Linker script to configure memory regions. */
-MEMORY
-{
-  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000   /* 256k */
-  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 0x5000    /*  20k */
-}
-
-/* Library configurations */
-GROUP(libgcc.a libc.a libm.a libnosys.a)
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __copy_table_start__
- *   __copy_table_end__
- *   __zero_table_start__
- *   __zero_table_end__
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __end__
- *   end
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   __Vectors_End
- *   __Vectors_Size
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
-	.text :
-	{
-		KEEP(*(.vectors))
-		__Vectors_End = .;
-		__Vectors_Size = __Vectors_End - __Vectors;
-		__end__ = .;
-
-		*(.text*)
-
-		KEEP(*(.init))
-		KEEP(*(.fini))
-
-		/* .ctors */
-		*crtbegin.o(.ctors)
-		*crtbegin?.o(.ctors)
-		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-		*(SORT(.ctors.*))
-		*(.ctors)
-
-		/* .dtors */
- 		*crtbegin.o(.dtors)
- 		*crtbegin?.o(.dtors)
- 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
- 		*(SORT(.dtors.*))
- 		*(.dtors)
-
-		*(.rodata*)
-
-		KEEP(*(.eh_frame*))
-	} > FLASH
-
-	.ARM.extab :
-	{
-		*(.ARM.extab* .gnu.linkonce.armextab.*)
-	} > FLASH
-
-	__exidx_start = .;
-	.ARM.exidx :
-	{
-		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
-	} > FLASH
-	__exidx_end = .;
-
-	/* To copy multiple ROM to RAM sections,
-	 * uncomment .copy.table section and,
-	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
-	/*
-	.copy.table :
-	{
-		. = ALIGN(4);
-		__copy_table_start__ = .;
-		LONG (__etext)
-		LONG (__data_start__)
-		LONG (__data_end__ - __data_start__)
-		LONG (__etext2)
-		LONG (__data2_start__)
-		LONG (__data2_end__ - __data2_start__)
-		__copy_table_end__ = .;
-	} > FLASH
-	*/
-
-	/* To clear multiple BSS sections,
-	 * uncomment .zero.table section and,
-	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
-	/*
-	.zero.table :
-	{
-		. = ALIGN(4);
-		__zero_table_start__ = .;
-		LONG (__bss_start__)
-		LONG (__bss_end__ - __bss_start__)
-		LONG (__bss2_start__)
-		LONG (__bss2_end__ - __bss2_start__)
-		__zero_table_end__ = .;
-	} > FLASH
-	*/
-
-	__etext = .;
-
-	.data : AT (__etext)
-	{
-		__data_start__ = .;
-		*(vtable)
-		*(.data*)
-
-		. = ALIGN(4);
-		/* preinit data */
-		PROVIDE_HIDDEN (__preinit_array_start = .);
-		KEEP(*(.preinit_array))
-		PROVIDE_HIDDEN (__preinit_array_end = .);
-
-		. = ALIGN(4);
-		/* init data */
-		PROVIDE_HIDDEN (__init_array_start = .);
-		KEEP(*(SORT(.init_array.*)))
-		KEEP(*(.init_array))
-		PROVIDE_HIDDEN (__init_array_end = .);
-
-
-		. = ALIGN(4);
-		/* finit data */
-		PROVIDE_HIDDEN (__fini_array_start = .);
-		KEEP(*(SORT(.fini_array.*)))
-		KEEP(*(.fini_array))
-		PROVIDE_HIDDEN (__fini_array_end = .);
-
-		KEEP(*(.jcr*))
-		. = ALIGN(4);
-		/* All data end */
-		__data_end__ = .;
-
-	} > RAM
-
-	.bss :
-	{
-		. = ALIGN(4);
-		__bss_start__ = .;
-		*(.bss*)
-		*(COMMON)
-		. = ALIGN(4);
-		__bss_end__ = .;
-	} > RAM
-
-	.heap (COPY):
-	{
-		__HeapBase = .;
-		__end__ = .;
-		end = __end__;
-		KEEP(*(.heap*))
-		__HeapLimit = .;
-	} > RAM
-
-	/* .stack_dummy section doesn't contains any symbols. It is only
-	 * used for linker to calculate size of stack sections, and assign
-	 * values to stack symbols later */
-	.stack_dummy (COPY):
-	{
-		KEEP(*(.stack*))
-	} > RAM
-
-	/* Set stack top to end of RAM, and stack limit move down by
-	 * size of stack_dummy section */
-	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
-	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
-	PROVIDE(__stack = __StackTop);
-
-	/* Check if data + heap + stack exceeds RAM limit */
-	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}
diff --git a/tinyusb/hw/bsp/nutiny_nuc126v/nutiny_nuc126.c b/tinyusb/hw/bsp/nutiny_nuc126v/nutiny_nuc126.c
deleted file mode 100755
index da62e7bd..00000000
--- a/tinyusb/hw/bsp/nutiny_nuc126v/nutiny_nuc126.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "bsp/board.h"
-#include "NuMicro.h"
-#include "clk.h"
-#include "sys.h"
-
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USBD_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-#define LED_PORT              PC
-#define LED_PIN               9
-#define LED_PIN_IO            PC9
-#define LED_STATE_ON          0
-
-#define CRYSTAL_LESS /* system will be 48MHz when defined, otherwise, system is 72MHz */
-#define HIRC48_AUTO_TRIM    SYS_IRCTCTL1_REFCKSEL_Msk | (1UL << SYS_IRCTCTL1_LOOPSEL_Pos) | (2UL << SYS_IRCTCTL1_FREQSEL_Pos)
-#define TRIM_INIT           (SYS_BASE+0x118)
-
-void board_init(void)
-{
-  /* Unlock protected registers */
-  SYS_UnlockReg();
-
-  /*---------------------------------------------------------------------------------------------------------*/
-  /* Init System Clock                                                                                       */
-  /*---------------------------------------------------------------------------------------------------------*/
-
-  /* Enable Internal RC 22.1184 MHz clock */
-  CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
-
-  /* Waiting for Internal RC clock ready */
-  CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
-
-  /* Switch HCLK clock source to Internal RC and HCLK source divide 1 */
-  CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
-
-#ifndef CRYSTAL_LESS
-  /* Enable external XTAL 12 MHz clock */
-  CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
-
-  /* Waiting for external XTAL clock ready */
-  CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
-
-  /* Set core clock */
-  CLK_SetCoreClock(72000000);
-
-  /* Use HIRC as UART clock source */
-  CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1));
-
-  /* Use PLL as USB clock source */
-  CLK_SetModuleClock(USBD_MODULE, CLK_CLKSEL3_USBDSEL_PLL, CLK_CLKDIV0_USB(3));
-
-#else
-  /* Enable Internal RC 48MHz clock */
-  CLK_EnableXtalRC(CLK_PWRCTL_HIRC48EN_Msk);
-
-  /* Waiting for Internal RC clock ready */
-  CLK_WaitClockReady(CLK_STATUS_HIRC48STB_Msk);
-
-  /* Switch HCLK clock source to Internal RC and HCLK source divide 1 */
-  CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC48, CLK_CLKDIV0_HCLK(1));
-
-  /* Use HIRC as UART clock source */
-  CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1));
-
-  /* Use HIRC48 as USB clock source */
-  CLK_SetModuleClock(USBD_MODULE, CLK_CLKSEL3_USBDSEL_HIRC48, CLK_CLKDIV0_USB(1));
-#endif
-
-  /* Enable module clock */
-  CLK_EnableModuleClock(USBD_MODULE);
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(48000000 / 1000);
-#endif
-
-  // LED
-  GPIO_SetMode(LED_PORT, 1 << LED_PIN, GPIO_MODE_OUTPUT);
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  LED_PIN_IO = (state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return 0;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
diff --git a/tinyusb/hw/bsp/nutiny_sdk_nuc120/board.mk b/tinyusb/hw/bsp/nutiny_sdk_nuc120/board.mk
deleted file mode 100755
index 90b3e91f..00000000
--- a/tinyusb/hw/bsp/nutiny_sdk_nuc120/board.mk
+++ /dev/null
@@ -1,55 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nuvoton
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs-linux \
-  -mcpu=cortex-m0 \
-  -DCFG_EXAMPLE_MSC_READONLY \
-  -DCFG_TUSB_MCU=OPT_MCU_NUC120
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/nutiny_sdk_nuc120/nuc120_flash.ld
-
-SRC_C += \
-  src/portable/nuvoton/nuc120/dcd_nuc120.c \
-  hw/mcu/nuvoton/nuc100_120/Device/Nuvoton/NUC100Series/Source/system_NUC100Series.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/acmp.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/adc.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/clk.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/crc.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/fmc.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/gpio.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/i2c.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/i2s.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/pdma.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/ps2.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/pwm.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/rtc.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/sc.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/spi.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/sys.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/timer.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/uart.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/usbd.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/wdt.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/wwdt.c
-
-SRC_S += \
-  hw/mcu/nuvoton/nuc100_120/Device/Nuvoton/NUC100Series/Source/GCC/startup_NUC100Series.S
-
-INC += \
-  $(TOP)/hw/mcu/nuvoton/nuc100_120/Device/Nuvoton/NUC100Series/Include \
-  $(TOP)/hw/mcu/nuvoton/nuc100_120/StdDriver/inc \
-  $(TOP)/hw/mcu/nuvoton/nuc100_120/CMSIS/Include
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
-
-# For flash-jlink target
-JLINK_DEVICE = NUC120LE3
-
-# Flash using Nuvoton's openocd fork at https://github.com/OpenNuvoton/OpenOCD-Nuvoton
-# Please compile and install it from github source
-flash: $(BUILD)/$(PROJECT).elf
-	openocd -f interface/nulink.cfg -f target/numicroM0.cfg -c "program $< reset exit"
diff --git a/tinyusb/hw/bsp/nutiny_sdk_nuc120/nuc120_flash.ld b/tinyusb/hw/bsp/nutiny_sdk_nuc120/nuc120_flash.ld
deleted file mode 100755
index cab12c8b..00000000
--- a/tinyusb/hw/bsp/nutiny_sdk_nuc120/nuc120_flash.ld
+++ /dev/null
@@ -1,195 +0,0 @@
-/* Linker script to configure memory regions. */
-MEMORY
-{
-  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x20000   /* 128k */
-  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 0x4000    /*  16k */
-}
-
-/* Library configurations */
-GROUP(libgcc.a libc.a libm.a libnosys.a)
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __copy_table_start__
- *   __copy_table_end__
- *   __zero_table_start__
- *   __zero_table_end__
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __end__
- *   end
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   __Vectors_End
- *   __Vectors_Size
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
-	.text :
-	{
-		KEEP(*(.vectors))
-		__Vectors_End = .;
-		__Vectors_Size = __Vectors_End - __Vectors;
-		__end__ = .;
-
-		*(.text*)
-
-		KEEP(*(.init))
-		KEEP(*(.fini))
-
-		/* .ctors */
-		*crtbegin.o(.ctors)
-		*crtbegin?.o(.ctors)
-		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-		*(SORT(.ctors.*))
-		*(.ctors)
-
-		/* .dtors */
- 		*crtbegin.o(.dtors)
- 		*crtbegin?.o(.dtors)
- 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
- 		*(SORT(.dtors.*))
- 		*(.dtors)
-
-		*(.rodata*)
-
-		KEEP(*(.eh_frame*))
-	} > FLASH
-
-	.ARM.extab :
-	{
-		*(.ARM.extab* .gnu.linkonce.armextab.*)
-	} > FLASH
-
-	__exidx_start = .;
-	.ARM.exidx :
-	{
-		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
-	} > FLASH
-	__exidx_end = .;
-
-	/* To copy multiple ROM to RAM sections,
-	 * uncomment .copy.table section and,
-	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
-	/*
-	.copy.table :
-	{
-		. = ALIGN(4);
-		__copy_table_start__ = .;
-		LONG (__etext)
-		LONG (__data_start__)
-		LONG (__data_end__ - __data_start__)
-		LONG (__etext2)
-		LONG (__data2_start__)
-		LONG (__data2_end__ - __data2_start__)
-		__copy_table_end__ = .;
-	} > FLASH
-	*/
-
-	/* To clear multiple BSS sections,
-	 * uncomment .zero.table section and,
-	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
-	/*
-	.zero.table :
-	{
-		. = ALIGN(4);
-		__zero_table_start__ = .;
-		LONG (__bss_start__)
-		LONG (__bss_end__ - __bss_start__)
-		LONG (__bss2_start__)
-		LONG (__bss2_end__ - __bss2_start__)
-		__zero_table_end__ = .;
-	} > FLASH
-	*/
-
-	__etext = .;
-
-	.data : AT (__etext)
-	{
-		__data_start__ = .;
-		*(vtable)
-		*(.data*)
-
-		. = ALIGN(4);
-		/* preinit data */
-		PROVIDE_HIDDEN (__preinit_array_start = .);
-		KEEP(*(.preinit_array))
-		PROVIDE_HIDDEN (__preinit_array_end = .);
-
-		. = ALIGN(4);
-		/* init data */
-		PROVIDE_HIDDEN (__init_array_start = .);
-		KEEP(*(SORT(.init_array.*)))
-		KEEP(*(.init_array))
-		PROVIDE_HIDDEN (__init_array_end = .);
-
-
-		. = ALIGN(4);
-		/* finit data */
-		PROVIDE_HIDDEN (__fini_array_start = .);
-		KEEP(*(SORT(.fini_array.*)))
-		KEEP(*(.fini_array))
-		PROVIDE_HIDDEN (__fini_array_end = .);
-
-		KEEP(*(.jcr*))
-		. = ALIGN(4);
-		/* All data end */
-		__data_end__ = .;
-
-	} > RAM
-
-	.bss :
-	{
-		. = ALIGN(4);
-		__bss_start__ = .;
-		*(.bss*)
-		*(COMMON)
-		. = ALIGN(4);
-		__bss_end__ = .;
-	} > RAM
-
-	.heap (COPY):
-	{
-		__HeapBase = .;
-		__end__ = .;
-		end = __end__;
-		KEEP(*(.heap*))
-		__HeapLimit = .;
-	} > RAM
-
-	/* .stack_dummy section doesn't contains any symbols. It is only
-	 * used for linker to calculate size of stack sections, and assign
-	 * values to stack symbols later */
-	.stack_dummy (COPY):
-	{
-		KEEP(*(.stack*))
-	} > RAM
-
-	/* Set stack top to end of RAM, and stack limit move down by
-	 * size of stack_dummy section */
-	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
-	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
-	PROVIDE(__stack = __StackTop);
-
-	/* Check if data + heap + stack exceeds RAM limit */
-	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}
diff --git a/tinyusb/hw/bsp/nutiny_sdk_nuc120/nutiny_sdk_nuc120.c b/tinyusb/hw/bsp/nutiny_sdk_nuc120/nutiny_sdk_nuc120.c
deleted file mode 100755
index 0d78116b..00000000
--- a/tinyusb/hw/bsp/nutiny_sdk_nuc120/nutiny_sdk_nuc120.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "bsp/board.h"
-#include "NUC100Series.h"
-#include "clk.h"
-#include "sys.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USBD_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-#define LED_PORT     PB
-#define LED_PIN      0
-#define LED_PIN_IO   PB0
-#define LED_STATE_ON 0
-
-void board_init(void)
-{
-  SYS_UnlockReg();
-
-  /* Enable Internal RC 22.1184 MHz clock */
-  CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk);
-
-  /* Waiting for Internal RC clock ready */
-  CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);
-
-  /* Switch HCLK clock source to Internal RC and HCLK source divide 1 */
-  CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));
-
-  /* Enable external XTAL 12 MHz clock */
-  CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk);
-
-  /* Waiting for external XTAL clock ready */
-  CLK_WaitClockReady(CLK_CLKSTATUS_XTL12M_STB_Msk);
-
-  /* Set core clock */
-  CLK_SetCoreClock(48000000);
-
-  /* Enable module clock */
-  CLK_EnableModuleClock(USBD_MODULE);
-
-  /* Select module clock source */
-  CLK_SetModuleClock(USBD_MODULE, 0, CLK_CLKDIV_USB(1));
-
-  SYS_LockReg();
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(48000000 / 1000);
-#endif
-
-  GPIO_SetMode(LED_PORT, 1UL << LED_PIN, GPIO_PMD_OUTPUT);
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-#if 0
-  /* this would be the simplest solution... *IF* the part supported the pin data interface */
-  LED_PIN_IO = (state) ? LED_STATE_ON : (1-LED_STATE_ON);
-#else
-  /* if the part's *PDIO pin data registers don't work, a more elaborate approach is needed */
-  uint32_t irq_state = __get_PRIMASK();
-  __disable_irq();
-  uint32_t current = LED_PORT->DOUT & ~(1UL << LED_PIN);
-  LED_PORT->DOUT = current | (((state) ? LED_STATE_ON : (1UL-LED_STATE_ON)) << LED_PIN);
-  __set_PRIMASK(irq_state);
-#endif
-}
-
-uint32_t board_button_read(void)
-{
-  return 0;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
diff --git a/tinyusb/hw/bsp/nutiny_sdk_nuc505/board.mk b/tinyusb/hw/bsp/nutiny_sdk_nuc505/board.mk
deleted file mode 100755
index e8514347..00000000
--- a/tinyusb/hw/bsp/nutiny_sdk_nuc505/board.mk
+++ /dev/null
@@ -1,60 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nuvoton
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs-linux \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -DCFG_TUSB_MCU=OPT_MCU_NUC505
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/nuc505_flashtoram.ld
-
-SRC_C += \
-  src/portable/nuvoton/nuc505/dcd_nuc505.c \
-  hw/mcu/nuvoton/nuc505/Device/Nuvoton/NUC505Series/Source/system_NUC505Series.c \
-  hw/mcu/nuvoton/nuc505/StdDriver/src/adc.c \
-  hw/mcu/nuvoton/nuc505/StdDriver/src/clk.c \
-  hw/mcu/nuvoton/nuc505/StdDriver/src/gpio.c \
-  hw/mcu/nuvoton/nuc505/StdDriver/src/i2c.c \
-  hw/mcu/nuvoton/nuc505/StdDriver/src/i2s.c \
-  hw/mcu/nuvoton/nuc505/StdDriver/src/pwm.c \
-  hw/mcu/nuvoton/nuc505/StdDriver/src/rtc.c \
-  hw/mcu/nuvoton/nuc505/StdDriver/src/spi.c \
-  hw/mcu/nuvoton/nuc505/StdDriver/src/spim.c \
-  hw/mcu/nuvoton/nuc505/StdDriver/src/sys.c \
-  hw/mcu/nuvoton/nuc505/StdDriver/src/timer.c \
-  hw/mcu/nuvoton/nuc505/StdDriver/src/uart.c \
-  hw/mcu/nuvoton/nuc505/StdDriver/src/wdt.c \
-  hw/mcu/nuvoton/nuc505/StdDriver/src/wwdt.c
-
-SRC_S += \
-  hw/mcu/nuvoton/nuc505/Device/Nuvoton/NUC505Series/Source/GCC/startup_NUC505Series.S
-
-INC += \
-  $(TOP)/hw/mcu/nuvoton/nuc505/Device/Nuvoton/NUC505Series/Include \
-  $(TOP)/hw/mcu/nuvoton/nuc505/StdDriver/inc \
-  $(TOP)/hw/mcu/nuvoton/nuc505/CMSIS/Include
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = NUC505YO13Y
-
-# Note
-# To be able to program the SPI flash, it need to boot with ICP mode "1011". 
-# However, in ICP mode, opencod cannot establish connection to the mcu. 
-# Therefore, there is no easy command line flash for NUC505
-# It is probably better to just use Nuvoton NuMicro ICP programming on windows to program the board
-# - 1111 "SPI" (run from internal flash)
-# - 1110 "USB" (mass storage emulator that accepts a .bin file)
-# - 0111 "ICE-SPI" (allow external debugger access, but may not be programmable)
-# - 1011 ICP mode (programmable via NuMicro ICP programming tool)
-
-# Flash using Nuvoton's openocd fork at https://github.com/OpenNuvoton/OpenOCD-Nuvoton
-# Please compile and install it from github source
-flash: $(BUILD)/$(PROJECT).elf
-	openocd -f interface/nulink.cfg -f target/numicroM4.cfg -c "program $< reset exit"
diff --git a/tinyusb/hw/bsp/nutiny_sdk_nuc505/nuc505_flashtoram.ld b/tinyusb/hw/bsp/nutiny_sdk_nuc505/nuc505_flashtoram.ld
deleted file mode 100755
index 53d385cd..00000000
--- a/tinyusb/hw/bsp/nutiny_sdk_nuc505/nuc505_flashtoram.ld
+++ /dev/null
@@ -1,199 +0,0 @@
-/* Linker script to configure memory regions. */
-MEMORY
-{
-  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000   /* 512k */
-  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 0x20000   /* 128k */
-}
-
-/* Library configurations */
-GROUP(libgcc.a libc.a libm.a libnosys.a)
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __copy_table_start__
- *   __copy_table_end__
- *   __zero_table_start__
- *   __zero_table_end__
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __end__
- *   end
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   __Vectors_End
- *   __Vectors_Size
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
-	.startup :
-	{
-		KEEP(*(.vectors))
-		__Vectors_End = .;
-		__Vectors_Size = __Vectors_End - __Vectors;
-		__end__ = .;
-
-		KEEP(*(.preinit))
-
-		KEEP(*(.init))
-		KEEP(*(.fini))
-
-	} > FLASH
-
-	.ARM.extab :
-	{
-		*(.ARM.extab* .gnu.linkonce.armextab.*)
-	} > FLASH
-
-	__exidx_start = .;
-	.ARM.exidx :
-	{
-		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
-	} > FLASH
-	__exidx_end = .;
-
-	/* To copy multiple ROM to RAM sections,
-	 * uncomment .copy.table section and,
-	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
-	/*
-	.copy.table :
-	{
-		. = ALIGN(4);
-		__copy_table_start__ = .;
-		LONG (__etext)
-		LONG (__data_start__)
-		LONG (__data_end__ - __data_start__)
-		LONG (__etext2)
-		LONG (__data2_start__)
-		LONG (__data2_end__ - __data2_start__)
-		__copy_table_end__ = .;
-	} > FLASH
-	*/
-
-	/* To clear multiple BSS sections,
-	 * uncomment .zero.table section and,
-	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
-	/*
-	.zero.table :
-	{
-		. = ALIGN(4);
-		__zero_table_start__ = .;
-		LONG (__bss_start__)
-		LONG (__bss_end__ - __bss_start__)
-		LONG (__bss2_start__)
-		LONG (__bss2_end__ - __bss2_start__)
-		__zero_table_end__ = .;
-	} > FLASH
-	*/
-
-	__etext = .;
-
-	.data : AT (__etext)
-	{
-		__data_start__ = .;
-
-		*(.text*)
-
-		/* .ctors */
-		*crtbegin.o(.ctors)
-		*crtbegin?.o(.ctors)
-		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-		*(SORT(.ctors.*))
-		*(.ctors)
-
-		/* .dtors */
- 		*crtbegin.o(.dtors)
- 		*crtbegin?.o(.dtors)
- 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
- 		*(SORT(.dtors.*))
- 		*(.dtors)
-
-		*(.rodata*)
-
-		KEEP(*(.eh_frame*))
-
-		*(vtable)
-		*(.data*)
-
-		. = ALIGN(4);
-		/* preinit data */
-		PROVIDE_HIDDEN (__preinit_array_start = .);
-		KEEP(*(.preinit_array))
-		PROVIDE_HIDDEN (__preinit_array_end = .);
-
-		. = ALIGN(4);
-		/* init data */
-		PROVIDE_HIDDEN (__init_array_start = .);
-		KEEP(*(SORT(.init_array.*)))
-		KEEP(*(.init_array))
-		PROVIDE_HIDDEN (__init_array_end = .);
-
-
-		. = ALIGN(4);
-		/* finit data */
-		PROVIDE_HIDDEN (__fini_array_start = .);
-		KEEP(*(SORT(.fini_array.*)))
-		KEEP(*(.fini_array))
-		PROVIDE_HIDDEN (__fini_array_end = .);
-
-		KEEP(*(.jcr*))
-		. = ALIGN(4);
-		/* All data end */
-		__data_end__ = .;
-
-	} > RAM
-
-	.bss :
-	{
-		. = ALIGN(4);
-		__bss_start__ = .;
-		*(.bss*)
-		*(COMMON)
-		. = ALIGN(4);
-		__bss_end__ = .;
-	} > RAM
-
-	.heap (COPY):
-	{
-		__HeapBase = .;
-		__end__ = .;
-		end = __end__;
-		KEEP(*(.heap*))
-		__HeapLimit = .;
-	} > RAM
-
-	/* .stack_dummy section doesn't contains any symbols. It is only
-	 * used for linker to calculate size of stack sections, and assign
-	 * values to stack symbols later */
-	.stack_dummy (COPY):
-	{
-		KEEP(*(.stack*))
-	} > RAM
-
-	/* Set stack top to end of RAM, and stack limit move down by
-	 * size of stack_dummy section */
-	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
-	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
-	PROVIDE(__stack = __StackTop);
-
-	/* Check if data + heap + stack exceeds RAM limit */
-	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}
diff --git a/tinyusb/hw/bsp/nutiny_sdk_nuc505/nutiny_sdk_nuc505.c b/tinyusb/hw/bsp/nutiny_sdk_nuc505/nutiny_sdk_nuc505.c
deleted file mode 100755
index 49e66d2d..00000000
--- a/tinyusb/hw/bsp/nutiny_sdk_nuc505/nutiny_sdk_nuc505.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "bsp/board.h"
-#include "NUC505Series.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USBD_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-#define LED_PORT     PC
-#define LED_PIN      3
-#define LED_STATE_ON 0
-
-void board_init(void)
-{
-  /* Enable XTAL */
-  CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk;
-
-  CLK_SetCoreClock(96000000);
-
-  /* Set PCLK divider */
-  CLK_SetModuleClock(PCLK_MODULE, 0, 1);
-
-  /* Update System Core Clock */
-  SystemCoreClockUpdate();
-
-  /* Enable USB IP clock */
-  CLK_EnableModuleClock(USBD_MODULE);
-
-  /* Select USB IP clock source */
-  CLK_SetModuleClock(USBD_MODULE, CLK_USBD_SRC_EXT, 0);
-
-  CLK_SetModuleClock(PCLK_MODULE, 0, 1);
-
-  /* Enable PHY */
-  USBD_ENABLE_PHY();
-  /* wait PHY clock ready */
-  while (1) {
-      USBD->EP[EPA].EPMPS = 0x20;
-      if (USBD->EP[EPA].EPMPS == 0x20)
-          break;
-  }
-
-  /* Force SE0, and then clear it to connect*/
-  USBD_SET_SE0();
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(96000000 / 1000);
-#endif
-
-  GPIO_SetMode(LED_PORT, 1UL << LED_PIN, GPIO_MODE_OUTPUT);
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  uint32_t current = (state) ? LED_STATE_ON : (1-LED_STATE_ON);
-  current <<= LED_PIN;
-  uint32_t irq_state = __get_PRIMASK();
-  __disable_irq();
-  current |= LED_PORT->DOUT & ~(1UL << LED_PIN);
-  LED_PORT->DOUT = current;
-  __set_PRIMASK(irq_state);
-}
-
-uint32_t board_button_read(void)
-{
-  return 0;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
diff --git a/tinyusb/hw/bsp/rp2040/board.h b/tinyusb/hw/bsp/rp2040/board.h
deleted file mode 100755
index 237f29dc..00000000
--- a/tinyusb/hw/bsp/rp2040/board.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifdef PICO_DEFAULT_LED_PIN
-#define LED_PIN               PICO_DEFAULT_LED_PIN
-#define LED_STATE_ON          (!(PICO_DEFAULT_LED_PIN_INVERTED))
-#endif
-
-// Button pin is BOOTSEL which is flash CS pin
-#define BUTTON_BOOTSEL
-#define BUTTON_STATE_ACTIVE   0
-
-#if defined(PICO_DEFAULT_UART_TX_PIN) && defined(PICO_DEFAULT_UART_RX_PIN) && defined(PICO_DEFAULT_UART)
-#define UART_DEV              PICO_DEFAULT_UART
-#define UART_TX_PIN           PICO_DEFAULT_UART_TX_PIN
-#define UART_RX_PIN           PICO_DEFAULT_UART_RX_PIN
-#endif
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/rp2040/boards/adafruit_feather_rp2040/board.cmake b/tinyusb/hw/bsp/rp2040/boards/adafruit_feather_rp2040/board.cmake
deleted file mode 100755
index e527a8ce..00000000
--- a/tinyusb/hw/bsp/rp2040/boards/adafruit_feather_rp2040/board.cmake
+++ /dev/null
@@ -1 +0,0 @@
-set(PICO_BOARD adafruit_feather_rp2040)
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/rp2040/boards/adafruit_itsybitsy_rp2040/board.cmake b/tinyusb/hw/bsp/rp2040/boards/adafruit_itsybitsy_rp2040/board.cmake
deleted file mode 100755
index 3fd2dd06..00000000
--- a/tinyusb/hw/bsp/rp2040/boards/adafruit_itsybitsy_rp2040/board.cmake
+++ /dev/null
@@ -1 +0,0 @@
-set(PICO_BOARD adafruit_itsybitsy_rp2040)
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/rp2040/boards/adafruit_qtpy_rp2040/board.cmake b/tinyusb/hw/bsp/rp2040/boards/adafruit_qtpy_rp2040/board.cmake
deleted file mode 100755
index 469929c5..00000000
--- a/tinyusb/hw/bsp/rp2040/boards/adafruit_qtpy_rp2040/board.cmake
+++ /dev/null
@@ -1 +0,0 @@
-set(PICO_BOARD adafruit_qtpy_rp2040)
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/rp2040/boards/pico_sdk/board.cmake b/tinyusb/hw/bsp/rp2040/boards/pico_sdk/board.cmake
deleted file mode 100755
index d57cbe52..00000000
--- a/tinyusb/hw/bsp/rp2040/boards/pico_sdk/board.cmake
+++ /dev/null
@@ -1 +0,0 @@
-# This builds with settings based purely on the current PICO_BOARD set via the SDK
diff --git a/tinyusb/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake b/tinyusb/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake
deleted file mode 100755
index 8280c835..00000000
--- a/tinyusb/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake
+++ /dev/null
@@ -1 +0,0 @@
-set(PICO_BOARD pico)
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/rp2040/family.c b/tinyusb/hw/bsp/rp2040/family.c
deleted file mode 100755
index 10ead277..00000000
--- a/tinyusb/hw/bsp/rp2040/family.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "pico/stdlib.h"
-#include "pico/binary_info.h"
-#include "hardware/gpio.h"
-#include "hardware/sync.h"
-#include "hardware/structs/ioqspi.h"
-#include "hardware/structs/sio.h"
-
-#include "bsp/board.h"
-#include "board.h"
-
-#ifdef BUTTON_BOOTSEL
-// This example blinks the Picoboard LED when the BOOTSEL button is pressed.
-//
-// Picoboard has a button attached to the flash CS pin, which the bootrom
-// checks, and jumps straight to the USB bootcode if the button is pressed
-// (pulling flash CS low). We can check this pin in by jumping to some code in
-// SRAM (so that the XIP interface is not required), floating the flash CS
-// pin, and observing whether it is pulled low.
-//
-// This doesn't work if others are trying to access flash at the same time,
-// e.g. XIP streamer, or the other core.
-bool __no_inline_not_in_flash_func(get_bootsel_button)() {
-    const uint CS_PIN_INDEX = 1;
-
-    // Must disable interrupts, as interrupt handlers may be in flash, and we
-    // are about to temporarily disable flash access!
-    uint32_t flags = save_and_disable_interrupts();
-
-    // Set chip select to Hi-Z
-    hw_write_masked(&ioqspi_hw->io[CS_PIN_INDEX].ctrl,
-                    GPIO_OVERRIDE_LOW << IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB,
-                    IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS);
-
-    // Note we can't call into any sleep functions in flash right now
-    for (volatile int i = 0; i < 1000; ++i);
-
-    // The HI GPIO registers in SIO can observe and control the 6 QSPI pins.
-    // Note the button pulls the pin *low* when pressed.
-    bool button_state = (sio_hw->gpio_hi_in & (1u << CS_PIN_INDEX));
-
-    // Need to restore the state of chip select, else we are going to have a
-    // bad time when we return to code in flash!
-    hw_write_masked(&ioqspi_hw->io[CS_PIN_INDEX].ctrl,
-                    GPIO_OVERRIDE_NORMAL << IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB,
-                    IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS);
-
-    restore_interrupts(flags);
-
-    return button_state;
-}
-#endif
-
-//------------- Segger RTT retarget -------------//
-#if defined(LOGGER_RTT)
-
-// Logging with RTT
-// - If RTT Control Block is not found by 'Auto Detection` try to use 'Search Range` with '0x20000000 0x10000'
-// - SWD speed is rather slow around 1000Khz
-
-#include "pico/stdio/driver.h"
-#include "SEGGER_RTT.h"
-
-static void stdio_rtt_write (const char *buf, int length)
-{
-  SEGGER_RTT_Write(0, buf, length);
-}
-
-static int stdio_rtt_read (char *buf, int len)
-{
-  return SEGGER_RTT_Read(0, buf, len);
-}
-
-static stdio_driver_t stdio_rtt =
-{
-  .out_chars = stdio_rtt_write,
-  .out_flush = NULL,
-  .in_chars = stdio_rtt_read
-};
-
-void stdio_rtt_init(void)
-{
-  stdio_set_driver_enabled(&stdio_rtt, true);
-}
-
-#endif
-
-#ifdef UART_DEV
-static uart_inst_t *uart_inst;
-#endif
-
-void board_init(void)
-{
-#ifdef LED_PIN
-  bi_decl(bi_1pin_with_name(LED_PIN, "LED"));
-  gpio_init(LED_PIN);
-  gpio_set_dir(LED_PIN, GPIO_OUT);
-#endif
-
-  // Button
-#ifndef BUTTON_BOOTSEL
-#endif
-
-#if defined(UART_DEV) && defined(LIB_PICO_STDIO_UART)
-  bi_decl(bi_2pins_with_func(UART_TX_PIN, UART_TX_PIN, GPIO_FUNC_UART));
-  uart_inst = uart_get_instance(UART_DEV);
-  stdio_uart_init_full(uart_inst, CFG_BOARD_UART_BAUDRATE, UART_TX_PIN, UART_RX_PIN);
-#endif
-
-#if defined(LOGGER_RTT)
-  stdio_rtt_init();
-#endif
-
-  // todo probably set up device mode?
-#if TUSB_OPT_DEVICE_ENABLED
-
-#endif
-
-#if TUSB_OPT_HOST_ENABLED
-  // set portfunc to host !!!
-#endif
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-#ifdef LED_PIN
-  gpio_put(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-#endif
-}
-
-uint32_t board_button_read(void)
-{
-#ifdef BUTTON_BOOTSEL
-  return BUTTON_STATE_ACTIVE == get_bootsel_button();
-#else
-  return 0;
-#endif
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-#ifdef UART_DEV
-  for(int i=0;i<len;i++) {
-    buf[i] = uart_getc(uart_inst);
-  }
-  return len;
-#else
-  return 0;
-#endif
-}
-
-int board_uart_write(void const * buf, int len)
-{
-#ifdef UART_DEV
-  char const* bufch = (char const*) buf;
-  for(int i=0;i<len;i++) {
-    uart_putc(uart_inst, bufch[i]);
-  }
-  return len;
-#else
-  return 0;
-#endif
-}
-
-//--------------------------------------------------------------------+
-// USB Interrupt Handler
-// rp2040 implementation will install approriate handler when initializing
-// tinyusb. There is no need to forward IRQ from application
-//--------------------------------------------------------------------+
diff --git a/tinyusb/hw/bsp/rp2040/family.cmake b/tinyusb/hw/bsp/rp2040/family.cmake
deleted file mode 100755
index 41960b6c..00000000
--- a/tinyusb/hw/bsp/rp2040/family.cmake
+++ /dev/null
@@ -1,154 +0,0 @@
-cmake_minimum_required(VERSION 3.13)
-if (NOT TARGET _rp2040_family_inclusion_marker)
-	add_library(_rp2040_family_inclusion_marker INTERFACE)
-
-	if (NOT BOARD)
-		message("BOARD not specified, defaulting to pico_sdk")
-		set(BOARD pico_sdk)
-	endif()
-
-	# add the SDK in case we are standalone tinyusb example (noop if already present)
-	include(${CMAKE_CURRENT_LIST_DIR}/pico_sdk_import.cmake)
-
-	# include basic family CMake functionality
-	set(FAMILY_MCUS RP2040)
-
-	include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
-
-	# TOP is absolute path to root directory of TinyUSB git repo
-	set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..")
-	get_filename_component(TOP "${TOP}" REALPATH)
-
-	if (NOT PICO_TINYUSB_PATH)
-		set(PICO_TINYUSB_PATH ${TOP})
-	endif()
-
-	# Base config for both device and host; wrapped by SDK's tinyusb_common
-	add_library(tinyusb_common_base INTERFACE)
-	
-	target_sources(tinyusb_common_base INTERFACE
-			${TOP}/src/tusb.c
-			${TOP}/src/common/tusb_fifo.c
-			)
-
-	target_include_directories(tinyusb_common_base INTERFACE
-			${TOP}/src
-			${TOP}/src/common
-			${TOP}/hw
-			)
-
-	target_link_libraries(tinyusb_common_base INTERFACE
-			hardware_structs
-			hardware_irq
-			hardware_resets
-			pico_sync
-			)
-
-	set(TINYUSB_DEBUG_LEVEL 0)
-	if (CMAKE_BUILD_TYPE STREQUAL "Debug")
-		message("Compiling TinyUSB with CFG_TUSB_DEBUG=1")
-		set(TINYUSB_DEBUG_LEVEL 1)
-	endif ()
-	
-	target_compile_definitions(tinyusb_common_base INTERFACE
-			CFG_TUSB_MCU=OPT_MCU_RP2040
-			CFG_TUSB_OS=OPT_OS_PICO
-			CFG_TUSB_DEBUG=${TINYUSB_DEBUG_LEVEL}
-	)
-
-	# Base config for device mode; wrapped by SDK's tinyusb_device
-	add_library(tinyusb_device_base INTERFACE)
-	target_sources(tinyusb_device_base INTERFACE
-			${TOP}/src/portable/raspberrypi/rp2040/dcd_rp2040.c
-			${TOP}/src/portable/raspberrypi/rp2040/rp2040_usb.c
-			${TOP}/src/device/usbd.c
-			${TOP}/src/device/usbd_control.c
-			${TOP}/src/class/audio/audio_device.c
-			${TOP}/src/class/cdc/cdc_device.c
-			${TOP}/src/class/dfu/dfu_device.c
-			${TOP}/src/class/dfu/dfu_rt_device.c
-			${TOP}/src/class/hid/hid_device.c
-			${TOP}/src/class/midi/midi_device.c
-			${TOP}/src/class/msc/msc_device.c
-			${TOP}/src/class/net/net_device.c
-			${TOP}/src/class/usbtmc/usbtmc_device.c
-			${TOP}/src/class/vendor/vendor_device.c
-			)
-
-
-	# Base config for host mode; wrapped by SDK's tinyusb_host
-	add_library(tinyusb_host_base INTERFACE)
-	target_sources(tinyusb_host_base INTERFACE
-			${TOP}/src/portable/raspberrypi/rp2040/hcd_rp2040.c
-			${TOP}/src/portable/raspberrypi/rp2040/rp2040_usb.c
-			${TOP}/src/host/usbh.c
-			${TOP}/src/host/usbh_control.c
-			${TOP}/src/host/hub.c
-			${TOP}/src/class/cdc/cdc_host.c
-			${TOP}/src/class/hid/hid_host.c
-			${TOP}/src/class/msc/msc_host.c
-			${TOP}/src/class/vendor/vendor_host.c
-			)
-
-	# Sometimes have to do host specific actions in mostly
-	# common functions
-	target_compile_definitions(tinyusb_host_base INTERFACE
-			RP2040_USB_HOST_MODE=1
-	)
-
-	add_library(tinyusb_bsp INTERFACE)
-	target_sources(tinyusb_bsp INTERFACE
-			${TOP}/hw/bsp/rp2040/family.c
-			)
-#	target_include_directories(tinyusb_bsp INTERFACE
-#			${TOP}/hw/bsp/rp2040)
-
-	# tinyusb_additions will hold our extra settings for examples
-	add_library(tinyusb_additions INTERFACE)
-
-	target_compile_definitions(tinyusb_additions INTERFACE
-		PICO_RP2040_USB_DEVICE_ENUMERATION_FIX=1
-	)
-
-	if(DEFINED LOG)
-	  target_compile_definitions(tinyusb_additions INTERFACE CFG_TUSB_DEBUG=${LOG} )
-	endif()
-
-	if(LOGGER STREQUAL "rtt")
-	  target_compile_definitions(tinyusb_additions INTERFACE
-		LOGGER_RTT
-		SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL
-	  )
-
-	  target_sources(tinyusb_additions INTERFACE
-		${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
-	  )
-
-	  target_include_directories(tinyusb_additions INTERFACE
-		${TOP}/lib/SEGGER_RTT/RTT
-	  )
-	endif()
-
-	function(family_configure_target TARGET)
-		pico_add_extra_outputs(${TARGET})
-		pico_enable_stdio_uart(${TARGET} 1)
-		target_link_libraries(${TARGET} PUBLIC pico_stdlib pico_bootsel_via_double_reset tinyusb_board tinyusb_additions)
-	endfunction()
-
-	function(family_configure_device_example TARGET)
-		family_configure_target(${TARGET})
-		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device)
-	endfunction()
-
-	function(family_configure_host_example TARGET)
-		family_configure_target(${TARGET})
-		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_host)
-	endfunction()
-
-	function(family_initialize_project PROJECT DIR)
-		# call the original version of this function from family_common.cmake
-		_family_initialize_project(${PROJECT} ${DIR})
-		enable_language(C CXX ASM)
-		pico_sdk_init()
-	endfunction()
-endif()
diff --git a/tinyusb/hw/bsp/rp2040/family.mk b/tinyusb/hw/bsp/rp2040/family.mk
deleted file mode 100755
index 5db784b1..00000000
--- a/tinyusb/hw/bsp/rp2040/family.mk
+++ /dev/null
@@ -1,19 +0,0 @@
-JLINK_DEVICE = rp2040_m0_0
-PYOCD_TARGET = rp2040
-
-ifeq ($(DEBUG), 1)
-CMAKE_DEFSYM += -DCMAKE_BUILD_TYPE=Debug
-endif
-
-$(BUILD):
-	cmake -S . -B $(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) -DPICO_BUILD_DOCS=0 $(CMAKE_DEFSYM)
-
-all: $(BUILD)
-	$(MAKE) -C $(BUILD)
-
-clean:
-	$(RM) -rf $(BUILD)
-
-flash: flash-pyocd
-flash-uf2:
-	@$(CP) $(BUILD)/$(PROJECT).uf2 /media/$(USER)/RPI-RP2
diff --git a/tinyusb/hw/bsp/rp2040/pico_sdk_import.cmake b/tinyusb/hw/bsp/rp2040/pico_sdk_import.cmake
deleted file mode 100755
index 28efe9ea..00000000
--- a/tinyusb/hw/bsp/rp2040/pico_sdk_import.cmake
+++ /dev/null
@@ -1,62 +0,0 @@
-# This is a copy of <PICO_SDK_PATH>/external/pico_sdk_import.cmake
-
-# This can be dropped into an external project to help locate this SDK
-# It should be include()ed prior to project()
-
-if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH))
-    set(PICO_SDK_PATH $ENV{PICO_SDK_PATH})
-    message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')")
-endif ()
-
-if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT))
-    set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT})
-    message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')")
-endif ()
-
-if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH))
-    set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH})
-    message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')")
-endif ()
-
-set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK")
-set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable")
-set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK")
-
-if (NOT PICO_SDK_PATH)
-    if (PICO_SDK_FETCH_FROM_GIT)
-        include(FetchContent)
-        set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR})
-        if (PICO_SDK_FETCH_FROM_GIT_PATH)
-            get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}")
-        endif ()
-        FetchContent_Declare(
-                pico_sdk
-                GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk
-                GIT_TAG master
-        )
-        if (NOT pico_sdk)
-            message("Downloading Raspberry Pi Pico SDK")
-            FetchContent_Populate(pico_sdk)
-            set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR})
-        endif ()
-        set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE})
-    else ()
-        message(FATAL_ERROR
-                "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git."
-                )
-    endif ()
-endif ()
-
-get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}")
-if (NOT EXISTS ${PICO_SDK_PATH})
-    message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found")
-endif ()
-
-set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake)
-if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE})
-    message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK")
-endif ()
-
-set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE)
-
-include(${PICO_SDK_INIT_CMAKE_FILE})
diff --git a/tinyusb/hw/bsp/rx/boards/gr_citrus/board.mk b/tinyusb/hw/bsp/rx/boards/gr_citrus/board.mk
deleted file mode 100755
index 0eba9461..00000000
--- a/tinyusb/hw/bsp/rx/boards/gr_citrus/board.mk
+++ /dev/null
@@ -1,24 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/renesas/rx
-
-CFLAGS += \
-  -mcpu=rx610 \
-  -misa=v1 \
-  -DCFG_TUSB_MCU=OPT_MCU_RX63X
-
-MCU_DIR = hw/mcu/renesas/rx/rx63n
-
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/r5f5631fd.ld
-
-# For freeRTOS port source
-FREERTOS_PORT = RX600
-
-# For flash-jlink target
-JLINK_DEVICE = R5F5631F
-JLINK_IF     = JTAG
-
-# For flash-pyocd target
-PYOCD_TARGET =
-
-# flash using jlink
-flash: flash-jlink
diff --git a/tinyusb/hw/bsp/rx/boards/gr_citrus/gr_citrus.c b/tinyusb/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
deleted file mode 100755
index caf5fd6f..00000000
--- a/tinyusb/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
+++ /dev/null
@@ -1,275 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Koji Kitayama
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-/* How to connect JLink and GR-CITRUS
- *
- * GR-CITRUS needs to solder some pads to enable JTAG interface.
- * - Short the following pads individually with solder.
- *   - J4
- *   - J5
- * - Short EMLE pad and 3.3V(GR-CITRUS pin name) with a wire.
- *
- * The pads are [the back side of GR-CITRUS](https://www.slideshare.net/MinaoYamamoto/grcitrusrx631/2).
- * 
- * Connect the pins between GR-CITRUS and JLink as follows.
- * 
- * | Function  | GR-CITRUS pin | JLink pin No.| note     |
- * |:---------:|:-------------:|:------------:|:--------:|
- * | VTref     |   3.3V        |   1          |          |
- * | TRST      |   5           |   3          |          |
- * | GND       |   GND         |   4          |          |
- * | TDI       |   3           |   5          |          |
- * | TMS       |   2           |   7          |          |
- * | TCK/FINEC |   14          |   9          | short J4 |
- * | TDO       |   9           |  13          | short J5 |
- * | nRES      |   RST         |  15          |          |
- *
- * JLink firmware needs to update to V6.96 or newer version to avoid
- * [a bug](https://forum.segger.com/index.php/Thread/7758-SOLVED-Bug-in-JLink-from-V6-88b-regarding-RX65N)
- * regarding downloading.
- */
-
-#include "../board.h"
-#include "iodefine.h"
-#include "interrupt_handlers.h"
-
-#define IRQ_PRIORITY_CMT0     5
-#define IRQ_PRIORITY_USBI0    6
-#define IRQ_PRIORITY_SCI0     5
-
-#define SYSTEM_PRCR_PRC1      (1<<1)
-#define SYSTEM_PRCR_PRKEY     (0xA5u<<8)
-
-#define CMT_PCLK              48000000
-#define CMT_CMCR_CKS_DIV_128  2
-#define CMT_CMCR_CMIE         (1<<6)
-#define MPC_PFS_ISEL          (1<<6)
-
-#define SCI_PCLK              48000000
-#define SCI_SSR_FER           (1<<4)
-#define SCI_SSR_ORER          (1<<5)
-
-#define SCI_SCR_TEIE          (1u<<2)
-#define SCI_SCR_RE            (1u<<4)
-#define SCI_SCR_TE            (1u<<5)
-#define SCI_SCR_RIE           (1u<<6)
-#define SCI_SCR_TIE           (1u<<7)
-
-//--------------------------------------------------------------------+
-// SCI0 handling
-//--------------------------------------------------------------------+
-typedef struct {
-  uint8_t *buf;
-  uint32_t cnt;
-} sci_buf_t;
-static volatile sci_buf_t sci0_buf[2];
-
-void INT_Excep_SCI0_TXI0(void)
-{
-  uint8_t *buf = sci0_buf[0].buf;
-  uint32_t cnt = sci0_buf[0].cnt;
-  
-  if (!buf || !cnt) {
-    SCI0.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
-    return;
-  }
-  SCI0.TDR = *buf;
-  if (--cnt) {
-    ++buf;
-  } else {
-    buf = NULL;
-    SCI0.SCR.BIT.TIE  = 0;
-    SCI0.SCR.BIT.TEIE = 1;
-  }
-  sci0_buf[0].buf = buf;
-  sci0_buf[0].cnt = cnt;
-}
-
-void INT_Excep_SCI0_TEI0(void)
-{
-  SCI0.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
-}
-
-void INT_Excep_SCI0_RXI0(void)
-{
-  uint8_t *buf = sci0_buf[1].buf;
-  uint32_t cnt = sci0_buf[1].cnt;
-
-  if (!buf || !cnt ||
-      (SCI0.SSR.BYTE & (SCI_SSR_FER | SCI_SSR_ORER))) {
-    sci0_buf[1].buf = NULL;
-    SCI0.SSR.BYTE   = 0;
-    SCI0.SCR.BYTE  &= ~(SCI_SCR_RE | SCI_SCR_RIE);
-    return;
-  }
-  *buf = SCI0.RDR;
-  if (--cnt) {
-    ++buf;
-  } else {
-    buf = NULL;
-    SCI0.SCR.BYTE &= ~(SCI_SCR_RE | SCI_SCR_RIE);
-  }
-  sci0_buf[1].buf = buf;
-  sci0_buf[1].cnt = cnt;
-}
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void INT_Excep_USB0_USBI0(void)
-{
-  tud_int_handler(0);
-}
-
-void board_init(void)
-{
-#if CFG_TUSB_OS == OPT_OS_NONE
-  /* Enable CMT0 */
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
-  MSTP(CMT0)       = 0;
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
-  /* Setup 1ms tick timer */
-  CMT0.CMCNT      = 0;
-  CMT0.CMCOR      = CMT_PCLK / 1000 / 128;
-  CMT0.CMCR.WORD  = CMT_CMCR_CMIE | CMT_CMCR_CKS_DIV_128;
-  IR(CMT0, CMI0)  = 0;
-  IPR(CMT0, CMI0) = IRQ_PRIORITY_CMT0;
-  IEN(CMT0, CMI0) = 1;
-  CMT.CMSTR0.BIT.STR0 = 1;
-#endif
-
-  /* Unlock MPC registers */
-  MPC.PWPR.BIT.B0WI  = 0;
-  MPC.PWPR.BIT.PFSWE = 1;
-  /* LED PA0 */
-  PORTA.PMR.BIT.B0  = 0U;
-  PORTA.PODR.BIT.B0 = 0U;
-  PORTA.PDR.BIT.B0  = 1U;
-  /* UART TXD0 => P20, RXD0 => P21 */
-  PORT2.PMR.BIT.B0 = 1U;
-  PORT2.PCR.BIT.B0 = 1U;
-  MPC.P20PFS.BYTE  = 0b01010;
-  PORT2.PMR.BIT.B1 = 1U;
-  MPC.P21PFS.BYTE  = 0b01010;
-  /* USB VBUS -> P16 DPUPE -> P14 */
-  PORT1.PMR.BIT.B4 = 1U;
-  PORT1.PMR.BIT.B6 = 1U;
-  MPC.P14PFS.BYTE  = 0b10001;
-  MPC.P16PFS.BYTE  = MPC_PFS_ISEL | 0b10001;
-  MPC.PFUSB0.BIT.PUPHZS = 1;
-  /* Lock MPC registers */
-  MPC.PWPR.BIT.PFSWE = 0;
-  MPC.PWPR.BIT.B0WI  = 1;
-
-  IR(USB0, USBI0)  = 0;
-  IPR(USB0, USBI0) = IRQ_PRIORITY_USBI0;
-
-  /* Enable SCI0 */
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
-  MSTP(SCI0) = 0;
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
-  SCI0.BRR = (SCI_PCLK / (32 * 115200)) - 1;
-  IR(SCI0,  RXI0)  = 0;
-  IR(SCI0,  TXI0)  = 0;
-  IR(SCI0,  TEI0)  = 0;
-  IPR(SCI0, RXI0) = IRQ_PRIORITY_SCI0;
-  IPR(SCI0, TXI0) = IRQ_PRIORITY_SCI0;
-  IPR(SCI0, TEI0) = IRQ_PRIORITY_SCI0;
-  IEN(SCI0, RXI0) = 1;
-  IEN(SCI0, TXI0) = 1;
-  IEN(SCI0, TEI0) = 1;
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  PORTA.PODR.BIT.B0 = state ? 1 : 0;
-}
-
-uint32_t board_button_read(void)
-{
-  return 0;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  sci0_buf[1].buf = buf;
-  sci0_buf[1].cnt = len;
-  SCI0.SCR.BYTE |= SCI_SCR_RE | SCI_SCR_RIE;
-  while (SCI0.SCR.BIT.RE) ;
-  return len - sci0_buf[1].cnt;
-}
-
-int board_uart_write(void const *buf, int len)
-{
-  sci0_buf[0].buf = (uint8_t*)buf;
-  sci0_buf[0].cnt = len;
-  SCI0.SCR.BYTE |= SCI_SCR_TE | SCI_SCR_TIE;
-  while (SCI0.SCR.BIT.TE) ;
-  return len;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void INT_Excep_CMT0_CMI0(void)
-{
-  ++system_ticks;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#else
-uint32_t SystemCoreClock = 96000000;
-#endif
-
-int close(int fd)
-{
-    (void)fd;
-    return -1;
-}
-int fstat(int fd, void *pstat)
-{
-    (void)fd;
-    (void)pstat;
-    return 0;
-}
-off_t lseek(int fd, off_t pos, int whence)
-{
-    (void)fd;
-    (void)pos;
-    (void)whence;
-    return 0;
-}
-int isatty(int fd)
-{
-    (void)fd;
-    return 1;
-}
diff --git a/tinyusb/hw/bsp/rx/boards/gr_citrus/hwinit.c b/tinyusb/hw/bsp/rx/boards/gr_citrus/hwinit.c
deleted file mode 100755
index 8245d774..00000000
--- a/tinyusb/hw/bsp/rx/boards/gr_citrus/hwinit.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/************************************************************************/
-/*    File Version: V1.00                                               */
-/*    Date Generated: 08/07/2013                                        */
-/************************************************************************/
-
-#include "iodefine.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-extern void HardwareSetup(void);
-#ifdef __cplusplus
-}
-#endif
-
-void HardwareSetup(void)
-{
-    SYSTEM.PRCR.WORD     = 0xA503u;
-    SYSTEM.SOSCCR.BYTE   = 0x01u;
-    SYSTEM.MOSCWTCR.BYTE = 0x0Du;
-    SYSTEM.PLLWTCR.BYTE  = 0x0Eu;
-    SYSTEM.PLLCR.WORD    = 0x0F00u;
-    SYSTEM.MOSCCR.BYTE   = 0x00u;
-    SYSTEM.PLLCR2.BYTE   = 0x00u;
-    for (unsigned i = 0; i < 2075u; ++i) __asm("nop");
-    SYSTEM.SCKCR.LONG    = 0x21021211u;
-    SYSTEM.SCKCR2.WORD   = 0x0033u;
-    SYSTEM.SCKCR3.WORD   = 0x0400u;
-    SYSTEM.SYSCR0.WORD   = 0x5A01;
-    SYSTEM.MSTPCRB.BIT.MSTPB15 = 0;
-    SYSTEM.PRCR.WORD     = 0xA500u;
-}
diff --git a/tinyusb/hw/bsp/rx/boards/gr_citrus/r5f5631fd.ld b/tinyusb/hw/bsp/rx/boards/gr_citrus/r5f5631fd.ld
deleted file mode 100755
index bb9c297c..00000000
--- a/tinyusb/hw/bsp/rx/boards/gr_citrus/r5f5631fd.ld
+++ /dev/null
@@ -1,127 +0,0 @@
-__USTACK_SIZE = 0x00000400;
-__ISTACK_SIZE = 0x00000400;
-
-MEMORY
-{
-	RAM : ORIGIN = 0x4,        LENGTH = 0x3fffc
-	ROM : ORIGIN = 0xFFE00000, LENGTH = 0x200000
-}
-SECTIONS
-{
-	.fvectors 0xFFFFFF80: AT(0xFFFFFF80)
-	{
-		KEEP(*(.fvectors))
-	} > ROM
-	.text 0xFFE00000: AT(0xFFE00000)
-	{
-		*(.text)
-		*(.text.*)
-		*(P)
-		etext = .;
-	} > ROM
-	.rvectors ALIGN(4):
-	{
-		_rvectors_start = .;
-		KEEP(*(.rvectors))
-		_rvectors_end = .;
-	} > ROM
-	.init :
-	{
-		KEEP(*(.init))
-		__preinit_array_start = .;
-		KEEP(*(.preinit_array))
-		__preinit_array_end = .;
-		__init_array_start = (. + 3) & ~ 3;
-		KEEP(*(.init_array))
-		KEEP(*(SORT(.init_array.*)))
-		__init_array_end = .;
-		__fini_array_start = .;
-		KEEP(*(.fini_array))
-		KEEP(*(SORT(.fini_array.*)))
-		__fini_array_end = .;
-	} > ROM
-	.fini :
-	{
-		KEEP(*(.fini))
-	} > ROM
-	.got :
-	{
-		*(.got)
-		*(.got.plt)
-	} > ROM
-	.rodata :
-	{
-		*(.rodata)
-		*(.rodata.*)
-		*(C_1)
-		*(C_2)
-		*(C)
-		_erodata = .;
-	} > ROM
-	.eh_frame_hdr :
-	{
-		*(.eh_frame_hdr)
-	} > ROM
-	.eh_frame :
-	{
-		*(.eh_frame)
-	} > ROM
-	.jcr :
-	{
-		*(.jcr)
-	} > ROM
-	.tors :
-	{
-		__CTOR_LIST__ = .;
-		. = ALIGN(2);
-		___ctors = .;
-		*(.ctors)
-		___ctors_end = .;
-		__CTOR_END__ = .;
-		__DTOR_LIST__ = .;
-		___dtors = .;
-		*(.dtors)
-		___dtors_end = .;
-		__DTOR_END__ = .;
-		. = ALIGN(2);
-		_mdata = .;
-	} > ROM
-	.data : AT(_mdata)
-	{
-		_data = .;
-		*(.data)
-		*(.data.*)
-		*(D)
-		*(D_1)
-		*(D_2)
-		_edata = .;
-	} > RAM
-	.gcc_exc :
-	{
-		*(.gcc_exc)
-	} > RAM
-	.bss :
-	{
-		_bss = .;
-		*(.bss)
-		*(.bss.**)
-		*(COMMON)
-		*(B)
-		*(B_1)
-		*(B_2)
-		_ebss = .;
-		_end = .;
-	} > RAM
-	.ustack :
-	{
-		. = ALIGN(8);
-		. = . + __USTACK_SIZE;
-		PROVIDE(_ustack = .);
-	} > RAM
-	.istack :
-	{
-		. = ALIGN(8);
-		. = . + __ISTACK_SIZE;
-		PROVIDE(_istack = .);
-	} > RAM
-}
diff --git a/tinyusb/hw/bsp/rx/boards/rx65n_target/board.mk b/tinyusb/hw/bsp/rx/boards/rx65n_target/board.mk
deleted file mode 100755
index fc76d79f..00000000
--- a/tinyusb/hw/bsp/rx/boards/rx65n_target/board.mk
+++ /dev/null
@@ -1,25 +0,0 @@
-CFLAGS += \
-  -mcpu=rx64m \
-  -misa=v2 \
-  -DCFG_TUSB_MCU=OPT_MCU_RX65X \
-  -DIR_USB0_USBI0=IR_PERIB_INTB185 \
-  -DIER_USB0_USBI0=IER_PERIB_INTB185 \
-  -DIEN_USB0_USBI0=IEN_PERIB_INTB185
-
-MCU_DIR = hw/mcu/renesas/rx/rx65n
-
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/r5f565ne.ld
-
-# For freeRTOS port source
-FREERTOS_PORT = RX600
-
-# For flash-jlink target
-JLINK_DEVICE = R5F565NE
-JLINK_IF     = JTAG
-
-# For flash-pyocd target
-PYOCD_TARGET =
-
-# flash using rfp-cli
-flash: flash-rfp
diff --git a/tinyusb/hw/bsp/rx/boards/rx65n_target/r5f565ne.ld b/tinyusb/hw/bsp/rx/boards/rx65n_target/r5f565ne.ld
deleted file mode 100755
index 8e5617f2..00000000
--- a/tinyusb/hw/bsp/rx/boards/rx65n_target/r5f565ne.ld
+++ /dev/null
@@ -1,168 +0,0 @@
-__USTACK_SIZE = 0x00000400;
-__ISTACK_SIZE = 0x00000400;
-
-MEMORY
-{
-	RAM  : ORIGIN = 0x4,        LENGTH = 0x3fffc
-	RAM2 : ORIGIN = 0x00800000, LENGTH = 0x60000
-	OFS  : ORIGIN = 0xFE7F5D00, LENGTH = 128
-	ROM  : ORIGIN = 0xFFE00000, LENGTH = 0x200000
-}
-SECTIONS
-{
-	.exvectors 0xFFFFFF80: AT(0xFFFFFF80)
-	{
-		"_exvectors_start" = .;
-		KEEP(*(.exvectors))
-		"_exvectors_end" = .;
-	} >ROM
-	.fvectors 0xFFFFFFFC: AT(0xFFFFFFFC)
-	{
-		KEEP(*(.fvectors))
-	} > ROM
-	.text 0xFFE00000: AT(0xFFE00000)
-	{
-		*(.text)
-		*(.text.*)
-		*(P)
-		KEEP(*(.text.*_isr))
-		etext = .;
-	} > ROM
-	.rvectors ALIGN(4):
-	{
-		_rvectors_start = .;
-		KEEP(*(.rvectors))
-		_rvectors_end = .;
-	} > ROM
-	.init :
-	{
-		KEEP(*(.init))
-		__preinit_array_start = .;
-		KEEP(*(.preinit_array))
-		__preinit_array_end = .;
-		__init_array_start = (. + 3) & ~ 3;
-		KEEP(*(.init_array))
-		KEEP(*(SORT(.init_array.*)))
-		__init_array_end = .;
-		__fini_array_start = .;
-		KEEP(*(.fini_array))
-		KEEP(*(SORT(.fini_array.*)))
-		__fini_array_end = .;
-	} > ROM
-	.fini :
-	{
-		KEEP(*(.fini))
-	} > ROM
-	.got :
-	{
-		*(.got)
-		*(.got.plt)
-	} > ROM
-	.rodata :
-	{
-		*(.rodata)
-		*(.rodata.*)
-		*(C_1)
-		*(C_2)
-		*(C)
-		_erodata = .;
-	} > ROM
-	.eh_frame_hdr :
-	{
-		*(.eh_frame_hdr)
-	} > ROM
-	.eh_frame :
-	{
-		*(.eh_frame)
-	} > ROM
-	.jcr :
-	{
-		*(.jcr)
-	} > ROM
-	.tors :
-	{
-		__CTOR_LIST__ = .;
-		. = ALIGN(2);
-		___ctors = .;
-		*(.ctors)
-		___ctors_end = .;
-		__CTOR_END__ = .;
-		__DTOR_LIST__ = .;
-		___dtors = .;
-		*(.dtors)
-		___dtors_end = .;
-		__DTOR_END__ = .;
-		. = ALIGN(2);
-		_mdata = .;
-	} > ROM
-	.data : AT(_mdata)
-	{
-		_data = .;
-		*(.data)
-		*(.data.*)
-		*(D)
-		*(D_1)
-		*(D_2)
-		_edata = .;
-	} > RAM
-	.gcc_exc :
-	{
-		*(.gcc_exc)
-	} > RAM
-	.bss :
-	{
-		_bss = .;
-		*(.bss)
-		*(.bss.**)
-		*(COMMON)
-		*(B)
-		*(B_1)
-		*(B_2)
-		_ebss = .;
-		_end = .;
-	} > RAM
-	.ustack :
-	{
-		. = ALIGN(8);
-		. = . + __USTACK_SIZE;
-		PROVIDE(_ustack = .);
-	} > RAM
-	.istack :
-	{
-		. = ALIGN(8);
-		. = . + __ISTACK_SIZE;
-		PROVIDE(_istack = .);
-	} > RAM
-	.ofs1 0xFE7F5D00: AT(0xFE7F5D00)
-	{
-		KEEP(*(.ofs1))
-	} > OFS
-	.ofs2 0xFE7F5D10: AT(0xFE7F5D10)
-	{
-		KEEP(*(.ofs2))
-	} > OFS
-	.ofs3 0xFE7F5D20: AT(0xFE7F5D20)
-	{
-		KEEP(*(.ofs3))
-	} > OFS
-	.ofs4 0xFE7F5D40: AT(0xFE7F5D40)
-	{
-		KEEP(*(.ofs4))
-	} > OFS
-	.ofs5 0xFE7F5D48: AT(0xFE7F5D48)
-	{
-		KEEP(*(.ofs5))
-	} > OFS
-	.ofs6 0xFE7F5D50: AT(0xFE7F5D50)
-	{
-		KEEP(*(.ofs6))
-	} > OFS
-	.ofs7 0xFE7F5D64: AT(0xFE7F5D64)
-	{
-		KEEP(*(.ofs7))
-	} > OFS
-	.ofs8 0xFE7F5D70: AT(0xFE7F5D70)
-	{
-		KEEP(*(.ofs8))
-	} > OFS
-}
diff --git a/tinyusb/hw/bsp/rx/boards/rx65n_target/rx65n_target.c b/tinyusb/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
deleted file mode 100755
index 20867455..00000000
--- a/tinyusb/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
+++ /dev/null
@@ -1,320 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Koji Kitayama
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-/* How to connect JLink and RX65n Target and option board
- * (For original comment https://github.com/hathach/tinyusb/pull/922#issuecomment-869786131)
- *
- * To enable JTAG, RX65N requires following connections on main board.
- * - short EJ2 jumper header, to disable onboard E2L.
- * - short EMLE(J1-2) and 3V3(J1-14 or J2-10), to enable In-Circuit Emulator.
- *
- * Note: For RX65N-Cloud-Kit, the option board's JTAG pins to some switches or floating.
- * To use JLink with the option board, I think some further modifications will be necessary.
- *
- * | Function  | RX65N pin  | main board | option board | JLink connector |
- * |:---------:|:----------:|:----------:|:------------:|:---------------:|
- * | 3V3       | VCC        |   J1-14    | CN5-6        |    1            |
- * | TRST      | P34        |   J1-16    | CN5-7        |    3            |
- * | GND       | VSS        |   J1-12    | CN5-5        |    4            |
- * | TDI       | P30        |   J1-20    | CN5-10       |    5            |
- * | TMS       | P31        |   J1-19    | USER_SW      |    7            |
- * | TCK/FINEC | P27        |   J1-21    | N/A          |    9            |
- * | TDO       | P26        |   J1-22    | CN5-9        |   13            |
- * | nRES      | RES#       |   J1-10    | RESET_SW     |   15            |
- *
- * JLink firmware needs to update to V6.96 or newer version to avoid
- * [a bug](https://forum.segger.com/index.php/Thread/7758-SOLVED-Bug-in-JLink-from-V6-88b-regarding-RX65N)
- * regarding downloading.
- */
-
-#include "bsp/board.h"
-#include "iodefine.h"
-#include "interrupt_handlers.h"
-
-#define IRQ_PRIORITY_CMT0     5
-#define IRQ_PRIORITY_USBI0    6
-#define IRQ_PRIORITY_SCI5     5
-
-#define SYSTEM_PRCR_PRC1      (1<<1)
-#define SYSTEM_PRCR_PRKEY     (0xA5u<<8)
-
-#define CMT_PCLK              60000000
-#define CMT_CMCR_CKS_DIV_128  2
-#define CMT_CMCR_CMIE         (1<<6)
-#define MPC_PFS_ISEL          (1<<6)
-
-#define SCI_PCLK              60000000
-#define SCI_SSR_FER           (1<<4)
-#define SCI_SSR_ORER          (1<<5)
-
-#define SCI_SCR_TEIE          (1u<<2)
-#define SCI_SCR_RE            (1u<<4)
-#define SCI_SCR_TE            (1u<<5)
-#define SCI_SCR_RIE           (1u<<6)
-#define SCI_SCR_TIE           (1u<<7)
-#define INT_Excep_SCI5_TEI5   INT_Excep_ICU_GROUPBL0
-
-#define IRQ_USB0_USBI0        62
-#define SLIBR_USBI0           SLIBR185
-#define IPR_USB0_USBI0        IPR_PERIB_INTB185
-#define INT_Excep_USB0_USBI0  INT_Excep_PERIB_INTB185
-
-void HardwareSetup(void)
-{
-  FLASH.ROMCIV.WORD = 1;
-  while (FLASH.ROMCIV.WORD) ;
-  FLASH.ROMCE.WORD = 1;
-  while (!FLASH.ROMCE.WORD) ;
-
-  SYSTEM.PRCR.WORD = 0xA503u;
-  if (!SYSTEM.RSTSR1.BYTE) {
-    RTC.RCR4.BYTE = 0;
-    RTC.RCR3.BYTE = 12;
-    while (12 != RTC.RCR3.BYTE) ;
-  }
-  SYSTEM.SOSCCR.BYTE = 1;
-
-  if (SYSTEM.HOCOCR.BYTE) {
-    SYSTEM.HOCOCR.BYTE = 0;
-    while (!SYSTEM.OSCOVFSR.BIT.HCOVF) ;
-  }
-  SYSTEM.PLLCR.WORD  = 0x1D10u; /* HOCO x 15 */
-  SYSTEM.PLLCR2.BYTE = 0;
-  while (!SYSTEM.OSCOVFSR.BIT.PLOVF) ;
-
-  SYSTEM.SCKCR.LONG  = 0x21C11222u;
-  SYSTEM.SCKCR2.WORD = 0x0041u;
-  SYSTEM.ROMWT.BYTE  = 0x02u;
-  while (0x02u != SYSTEM.ROMWT.BYTE) ;
-  SYSTEM.SCKCR3.WORD = 0x400u;
-  SYSTEM.PRCR.WORD   = 0xA500u;
-}
-
-//--------------------------------------------------------------------+
-// SCI handling
-//--------------------------------------------------------------------+
-typedef struct {
-  uint8_t *buf;
-  uint32_t cnt;
-} sci_buf_t;
-static volatile sci_buf_t sci_buf[2];
-
-void INT_Excep_SCI5_TXI5(void)
-{
-  uint8_t *buf = sci_buf[0].buf;
-  uint32_t cnt = sci_buf[0].cnt;
-  
-  if (!buf || !cnt) {
-    SCI5.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
-    return;
-  }
-  SCI5.TDR = *buf;
-  if (--cnt) {
-    ++buf;
-  } else {
-    buf = NULL;
-    SCI5.SCR.BIT.TIE  = 0;
-    SCI5.SCR.BIT.TEIE = 1;
-  }
-  sci_buf[0].buf = buf;
-  sci_buf[0].cnt = cnt;
-}
-
-void INT_Excep_SCI5_TEI5(void)
-{
-  SCI5.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
-}
-
-void INT_Excep_SCI5_RXI5(void)
-{
-  uint8_t *buf = sci_buf[1].buf;
-  uint32_t cnt = sci_buf[1].cnt;
-
-  if (!buf || !cnt ||
-      (SCI5.SSR.BYTE & (SCI_SSR_FER | SCI_SSR_ORER))) {
-    sci_buf[1].buf = NULL;
-    SCI5.SSR.BYTE   = 0;
-    SCI5.SCR.BYTE  &= ~(SCI_SCR_RE | SCI_SCR_RIE);
-    return;
-  }
-  *buf = SCI5.RDR;
-  if (--cnt) {
-    ++buf;
-  } else {
-    buf = NULL;
-    SCI5.SCR.BYTE &= ~(SCI_SCR_RE | SCI_SCR_RIE);
-  }
-  sci_buf[1].buf = buf;
-  sci_buf[1].cnt = cnt;
-}
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void INT_Excep_USB0_USBI0(void)
-{
-  tud_int_handler(0);
-}
-
-void board_init(void)
-{
-  /* setup software configurable interrupts */
-  ICU.SLIBR_USBI0.BYTE = IRQ_USB0_USBI0;
-  ICU.SLIPRCR.BYTE     = 1;
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  /* Enable CMT0 */
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
-  MSTP(CMT0)       = 0;
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
-  /* Setup 1ms tick timer */
-  CMT0.CMCNT      = 0;
-  CMT0.CMCOR      = CMT_PCLK / 1000 / 128;
-  CMT0.CMCR.WORD  = CMT_CMCR_CMIE | CMT_CMCR_CKS_DIV_128;
-  IR(CMT0, CMI0)  = 0;
-  IPR(CMT0, CMI0) = IRQ_PRIORITY_CMT0;
-  IEN(CMT0, CMI0) = 1;
-  CMT.CMSTR0.BIT.STR0 = 1;
-#endif
-
-  /* Unlock MPC registers */
-  MPC.PWPR.BIT.B0WI  = 0;
-  MPC.PWPR.BIT.PFSWE = 1;
-  // SW PB1
-  PORTB.PMR.BIT.B1 = 0U;
-  PORTB.PDR.BIT.B1 = 0U;
-  // LED PD6
-  PORTD.PODR.BIT.B6 = 1U;
-  PORTD.ODR1.BIT.B4 = 1U;
-  PORTD.PMR.BIT.B6  = 0U;
-  PORTD.PDR.BIT.B6  = 1U;
-  /* UART TXD5 => PA4, RXD5 => PA3 */
-  PORTA.PMR.BIT.B4 = 1U;
-  PORTA.PCR.BIT.B4 = 1U;
-  MPC.PA4PFS.BYTE  = 0b01010;
-  PORTA.PMR.BIT.B3 = 1U;
-  MPC.PA5PFS.BYTE  = 0b01010;
-  /* USB VBUS -> P16 */
-  PORT1.PMR.BIT.B6 = 1U;
-  MPC.P16PFS.BYTE  = MPC_PFS_ISEL | 0b10001;
-  /* Lock MPC registers */
-  MPC.PWPR.BIT.PFSWE = 0;
-  MPC.PWPR.BIT.B0WI  = 1;
-
-  /* Enable SCI5 */
-  SYSTEM.PRCR.WORD   = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
-  MSTP(SCI5)         = 0;
-  SYSTEM.PRCR.WORD   = SYSTEM_PRCR_PRKEY;
-  SCI5.SEMR.BIT.ABCS = 1;
-  SCI5.SEMR.BIT.BGDM = 1;
-  SCI5.BRR           = (SCI_PCLK / (8 * 115200)) - 1;
-  IR(SCI5,  RXI5)    = 0;
-  IR(SCI5,  TXI5)    = 0;
-  IS(SCI5,  TEI5)    = 0;
-  IR(ICU, GROUPBL0)  = 0;
-  IPR(SCI5, RXI5)    = IRQ_PRIORITY_SCI5;
-  IPR(SCI5, TXI5)    = IRQ_PRIORITY_SCI5;
-  IPR(ICU,GROUPBL0)  = IRQ_PRIORITY_SCI5;
-  IEN(SCI5, RXI5)    = 1;
-  IEN(SCI5, TXI5)    = 1;
-  IEN(ICU,GROUPBL0)  = 1;
-  EN(SCI5, TEI5)     = 1;
-
-  /* setup USBI0 interrupt. */
-  IR(USB0, USBI0)  = 0;
-  IPR(USB0, USBI0) = IRQ_PRIORITY_USBI0;
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  PORTD.PODR.BIT.B6 = state ? 0 : 1;
-}
-
-uint32_t board_button_read(void)
-{
-  return PORTB.PIDR.BIT.B1 ? 0 : 1;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  sci_buf[1].buf = buf;
-  sci_buf[1].cnt = len;
-  SCI5.SCR.BYTE |= SCI_SCR_RE | SCI_SCR_RIE;
-  while (SCI5.SCR.BIT.RE) ;
-  return len - sci_buf[1].cnt;
-}
-
-int board_uart_write(void const *buf, int len)
-{
-  sci_buf[0].buf = (uint8_t*)buf;
-  sci_buf[0].cnt = len;
-  SCI5.SCR.BYTE |= SCI_SCR_TE | SCI_SCR_TIE;
-  while (SCI5.SCR.BIT.TE) ;
-  return len;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void INT_Excep_CMT0_CMI0(void)
-{
-  ++system_ticks;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#else
-uint32_t SystemCoreClock = 120000000;
-#endif
-
-int close(int fd)
-{
-    (void)fd;
-    return -1;
-}
-int fstat(int fd, void *pstat)
-{
-    (void)fd;
-    (void)pstat;
-    return 0;
-}
-off_t lseek(int fd, off_t pos, int whence)
-{
-    (void)fd;
-    (void)pos;
-    (void)whence;
-    return 0;
-}
-int isatty(int fd)
-{
-    (void)fd;
-    return 1;
-}
diff --git a/tinyusb/hw/bsp/rx/family.mk b/tinyusb/hw/bsp/rx/family.mk
deleted file mode 100755
index 5a828171..00000000
--- a/tinyusb/hw/bsp/rx/family.mk
+++ /dev/null
@@ -1,32 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/renesas/rx
-
-# Cross Compiler for RX
-CROSS_COMPILE = rx-elf-
-
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-CFLAGS += \
-  -nostartfiles \
-  -ffunction-sections \
-  -fdata-sections \
-  -fshort-enums \
-  -mlittle-endian-data \
-  -DSSIZE_MAX=__INT_MAX__
-
-SRC_C += \
-	src/portable/renesas/usba/dcd_usba.c \
-	$(MCU_DIR)/vects.c
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(MCU_DIR)
-
-SRC_S += $(MCU_DIR)/start.S
-
-$(BUILD)/$(PROJECT).mot: $(BUILD)/$(PROJECT).elf
-	@echo CREATE $@
-	$(OBJCOPY) -O srec -I elf32-rx-be-ns $^ $@
-
-# flash using rfp-cli
-flash-rfp: $(BUILD)/$(PROJECT).mot
-	rfp-cli -device rx65x -tool e2l -if fine -fo id FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF -auth id FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF -auto $^
diff --git a/tinyusb/hw/bsp/samd11/boards/luna_d11/board.h b/tinyusb/hw/bsp/samd11/boards/luna_d11/board.h
deleted file mode 100755
index 1bda9293..00000000
--- a/tinyusb/hw/bsp/samd11/boards/luna_d11/board.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PIN               PIN_PA27 // pin PA22
-#define LED_STATE_ON          0
-
-// Button
-#define BUTTON_PIN            PIN_PA16 // pin PB22
-#define BUTTON_STATE_ACTIVE   0
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/samd11/boards/luna_d11/board.mk b/tinyusb/hw/bsp/samd11/boards/luna_d11/board.mk
deleted file mode 100755
index ad9cfb25..00000000
--- a/tinyusb/hw/bsp/samd11/boards/luna_d11/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-CFLAGS += -D__SAMD11D14AM__
-
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/samd11d14am_flash.ld
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAMD11D14
-
-# flash using dfu-util
-flash: $(BUILD)/$(PROJECT).bin
-	dfu-util -a 0 -d 1d50:615c -D $< || dfu-util -a 0 -d 16d0:05a5 -D $<
diff --git a/tinyusb/hw/bsp/samd11/boards/luna_d11/samd11d14am_flash.ld b/tinyusb/hw/bsp/samd11/boards/luna_d11/samd11d14am_flash.ld
deleted file mode 100755
index cb633c19..00000000
--- a/tinyusb/hw/bsp/samd11/boards/luna_d11/samd11d14am_flash.ld
+++ /dev/null
@@ -1,144 +0,0 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD11D14AM
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-SEARCH_DIR(.)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-  rom      (rx)  : ORIGIN = 0x00000000 + 4K, LENGTH = 0x00004000 - 4K
-  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
-}
-
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
-
-/* Section Definitions */
-SECTIONS
-{
-    .text :
-    {
-        . = ALIGN(4);
-        _sfixed = .;
-        KEEP(*(.vectors .vectors.*))
-        *(.text .text.* .gnu.linkonce.t.*)
-        *(.glue_7t) *(.glue_7)
-        *(.rodata .rodata* .gnu.linkonce.r.*)
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-
-        /* Support C constructors, and C destructors in both user code
-           and the C library. This also provides support for C++ code. */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-
-        . = ALIGN(4);
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-
-        . = ALIGN(4);
-        KEEP(*(.fini))
-
-        . = ALIGN(4);
-        __fini_array_start = .;
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        __fini_array_end = .;
-
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-
-        . = ALIGN(4);
-        _efixed = .;            /* End of text section */
-    } > rom
-
-    /* .ARM.exidx is sorted, so has to go in its own output section.  */
-    PROVIDE_HIDDEN (__exidx_start = .);
-    .ARM.exidx :
-    {
-      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > rom
-    PROVIDE_HIDDEN (__exidx_end = .);
-
-    . = ALIGN(4);
-    _etext = .;
-
-    .relocate : AT (_etext)
-    {
-        . = ALIGN(4);
-        _srelocate = .;
-        *(.ramfunc .ramfunc.*);
-        *(.data .data.*);
-        . = ALIGN(4);
-        _erelocate = .;
-    } > ram
-
-    /* .bss section which is used for uninitialized data */
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        _sbss = . ;
-        _szero = .;
-        *(.bss .bss.*)
-        *(COMMON)
-        . = ALIGN(4);
-        _ebss = . ;
-        _ezero = .;
-        end = .;
-    } > ram
-
-    /* stack section */
-    .stack (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sstack = .;
-        . = . + STACK_SIZE;
-        . = ALIGN(8);
-        _estack = .;
-    } > ram
-
-    . = ALIGN(4);
-    _end = . ;
-}
diff --git a/tinyusb/hw/bsp/samd11/boards/samd11_xplained/board.h b/tinyusb/hw/bsp/samd11/boards/samd11_xplained/board.h
deleted file mode 100755
index cfeac673..00000000
--- a/tinyusb/hw/bsp/samd11/boards/samd11_xplained/board.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PIN               PIN_PA16 // pin PA22
-#define LED_STATE_ON          0
-
-// Button
-#define BUTTON_PIN            PIN_PA14 // pin PB22
-#define BUTTON_STATE_ACTIVE   0
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/samd11/boards/samd11_xplained/board.mk b/tinyusb/hw/bsp/samd11/boards/samd11_xplained/board.mk
deleted file mode 100755
index e351cf0b..00000000
--- a/tinyusb/hw/bsp/samd11/boards/samd11_xplained/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-CFLAGS += -D__SAMD11D14AM__
-
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/samd11d14am_flash.ld
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAMD11D14
-
-# flash using edbg
-flash: $(BUILD)/$(PROJECT).bin
-	edbg -b -t samd11 -e -pv -f $<
diff --git a/tinyusb/hw/bsp/samd11/boards/samd11_xplained/samd11d14am_flash.ld b/tinyusb/hw/bsp/samd11/boards/samd11_xplained/samd11d14am_flash.ld
deleted file mode 100755
index 8b3124c0..00000000
--- a/tinyusb/hw/bsp/samd11/boards/samd11_xplained/samd11d14am_flash.ld
+++ /dev/null
@@ -1,144 +0,0 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD11D14AM
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-SEARCH_DIR(.)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00004000
-  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
-}
-
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
-
-/* Section Definitions */
-SECTIONS
-{
-    .text :
-    {
-        . = ALIGN(4);
-        _sfixed = .;
-        KEEP(*(.vectors .vectors.*))
-        *(.text .text.* .gnu.linkonce.t.*)
-        *(.glue_7t) *(.glue_7)
-        *(.rodata .rodata* .gnu.linkonce.r.*)
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-
-        /* Support C constructors, and C destructors in both user code
-           and the C library. This also provides support for C++ code. */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-
-        . = ALIGN(4);
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-
-        . = ALIGN(4);
-        KEEP(*(.fini))
-
-        . = ALIGN(4);
-        __fini_array_start = .;
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        __fini_array_end = .;
-
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-
-        . = ALIGN(4);
-        _efixed = .;            /* End of text section */
-    } > rom
-
-    /* .ARM.exidx is sorted, so has to go in its own output section.  */
-    PROVIDE_HIDDEN (__exidx_start = .);
-    .ARM.exidx :
-    {
-      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > rom
-    PROVIDE_HIDDEN (__exidx_end = .);
-
-    . = ALIGN(4);
-    _etext = .;
-
-    .relocate : AT (_etext)
-    {
-        . = ALIGN(4);
-        _srelocate = .;
-        *(.ramfunc .ramfunc.*);
-        *(.data .data.*);
-        . = ALIGN(4);
-        _erelocate = .;
-    } > ram
-
-    /* .bss section which is used for uninitialized data */
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        _sbss = . ;
-        _szero = .;
-        *(.bss .bss.*)
-        *(COMMON)
-        . = ALIGN(4);
-        _ebss = . ;
-        _ezero = .;
-        end = .;
-    } > ram
-
-    /* stack section */
-    .stack (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sstack = .;
-        . = . + STACK_SIZE;
-        . = ALIGN(8);
-        _estack = .;
-    } > ram
-
-    . = ALIGN(4);
-    _end = . ;
-}
diff --git a/tinyusb/hw/bsp/samd11/family.c b/tinyusb/hw/bsp/samd11/family.c
deleted file mode 100755
index 8d963397..00000000
--- a/tinyusb/hw/bsp/samd11/family.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2020 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "sam.h"
-#include "bsp/board.h"
-#include "board.h"
-
-#include "hal/include/hal_gpio.h"
-#include "hal/include/hal_init.h"
-#include "hri/hri_nvmctrl_d11.h"
-
-#include "hpl/gclk/hpl_gclk_base.h"
-#include "hpl_pm_config.h"
-#include "hpl/pm/hpl_pm_base.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_Handler(void)
-{
-  tud_int_handler(0);
-}
-
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-
-/* Referenced GCLKs, should be initialized firstly */
-#define _GCLK_INIT_1ST (1 << 0 | 1 << 1)
-
-/* Not referenced GCLKs, initialized last */
-#define _GCLK_INIT_LAST (~_GCLK_INIT_1ST)
-
-void board_init(void)
-{
-  // Clock init ( follow hpl_init.c )
-  hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, 2);
-
-  _pm_init();
-  _sysctrl_init_sources();
-#if _GCLK_INIT_1ST
-  _gclk_init_generators_by_fref(_GCLK_INIT_1ST);
-#endif
-  _sysctrl_init_referenced_generators();
-  _gclk_init_generators_by_fref(_GCLK_INIT_LAST);
-
-  // 1ms tick timer (samd SystemCoreClock may not correct)
-  SystemCoreClock = CONF_CPU_FREQUENCY;
-  SysTick_Config(CONF_CPU_FREQUENCY / 1000);
-
-  // Led init
-  gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
-  gpio_set_pin_level(LED_PIN, 0);
-
-  // Button init
-  gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
-  gpio_set_pin_pull_mode(BUTTON_PIN, GPIO_PULL_UP);
-
-  /* USB Clock init
-   * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock
-   * for low speed and full speed operation. */
-  _pm_enable_bus_clock(PM_BUS_APBB, USB);
-  _pm_enable_bus_clock(PM_BUS_AHB, USB);
-  _gclk_enable_channel(USB_GCLK_ID, GCLK_CLKCTRL_GEN_GCLK0_Val);
-
-  // USB Pin Init
-  gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT);
-  gpio_set_pin_level(PIN_PA24, false);
-  gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF);
-  gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT);
-  gpio_set_pin_level(PIN_PA25, false);
-  gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF);
-
-  gpio_set_pin_function(PIN_PA24, PINMUX_PA24G_USB_DM);
-  gpio_set_pin_function(PIN_PA25, PINMUX_PA25G_USB_DP);
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  gpio_set_pin_level(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == gpio_get_pin_level(BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-
-volatile uint32_t system_ticks = 0;
-
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-
-void _init(void)
-{
-  // This _init() standin makes certain GCC environments happier.
-  // They expect the main binary to have a constructor called _init; but don't provide a weak default.
-  // Providing an empty constructor satisfies this odd case, and doesn't harm anything.
-}
-
-
-#endif
diff --git a/tinyusb/hw/bsp/samd11/family.mk b/tinyusb/hw/bsp/samd11/family.mk
deleted file mode 100755
index 032d11b9..00000000
--- a/tinyusb/hw/bsp/samd11/family.mk
+++ /dev/null
@@ -1,37 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/microchip
-
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-CFLAGS += \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
-  -nostdlib -nostartfiles \
-  -DCONF_DFLL_OVERWRITE_CALIBRATION=0 \
-  -DOSC32K_OVERWRITE_CALIBRATION=0 \
-  -DCFG_TUSB_MCU=OPT_MCU_SAMD11
-
-SRC_C += \
-	src/portable/microchip/samd/dcd_samd.c \
-	hw/mcu/microchip/samd11/gcc/gcc/startup_samd11.c \
-	hw/mcu/microchip/samd11/gcc/system_samd11.c \
-	hw/mcu/microchip/samd11/hpl/gclk/hpl_gclk.c \
-	hw/mcu/microchip/samd11/hpl/pm/hpl_pm.c \
-	hw/mcu/microchip/samd11/hpl/sysctrl/hpl_sysctrl.c \
-	hw/mcu/microchip/samd11/hal/src/hal_atomic.c
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/hw/mcu/microchip/samd11/ \
-	$(TOP)/hw/mcu/microchip/samd11/config \
-	$(TOP)/hw/mcu/microchip/samd11/include \
-	$(TOP)/hw/mcu/microchip/samd11/hal/include \
-	$(TOP)/hw/mcu/microchip/samd11/hal/utils/include \
-	$(TOP)/hw/mcu/microchip/samd11/hpl/pm/ \
-	$(TOP)/hw/mcu/microchip/samd11/hpl/port \
-	$(TOP)/hw/mcu/microchip/samd11/hri \
-	$(TOP)/hw/mcu/microchip/samd11/CMSIS/Include \
-	$(TOP)/hw/mcu/microchip/samd11/CMSIS/Core/Include
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
diff --git a/tinyusb/hw/bsp/samd21/boards/atsamd21_xpro/board.h b/tinyusb/hw/bsp/samd21/boards/atsamd21_xpro/board.h
deleted file mode 100755
index a3e03997..00000000
--- a/tinyusb/hw/bsp/samd21/boards/atsamd21_xpro/board.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PIN               (32 + 30) // PB30
-#define LED_STATE_ON          0
-
-// Button
-#define BUTTON_PIN            (0  + 15) // PA15
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_RX_PIN           4
-#define UART_TX_PIN           5
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/samd21/boards/atsamd21_xpro/board.mk b/tinyusb/hw/bsp/samd21/boards/atsamd21_xpro/board.mk
deleted file mode 100755
index 5cd82735..00000000
--- a/tinyusb/hw/bsp/samd21/boards/atsamd21_xpro/board.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-CFLAGS += -D__SAMD21J18A__
-
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/samd21j18a_flash.ld
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAMD21J18
-
-# flash using jlink
-flash: flash-jlink
diff --git a/tinyusb/hw/bsp/samd21/boards/atsamd21_xpro/samd21j18a_flash.ld b/tinyusb/hw/bsp/samd21/boards/atsamd21_xpro/samd21j18a_flash.ld
deleted file mode 100755
index e2f93416..00000000
--- a/tinyusb/hw/bsp/samd21/boards/atsamd21_xpro/samd21j18a_flash.ld
+++ /dev/null
@@ -1,144 +0,0 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD21J18A
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-SEARCH_DIR(.)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00040000
-  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
-}
-
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
-
-/* Section Definitions */
-SECTIONS
-{
-    .text :
-    {
-        . = ALIGN(4);
-        _sfixed = .;
-        KEEP(*(.vectors .vectors.*))
-        *(.text .text.* .gnu.linkonce.t.*)
-        *(.glue_7t) *(.glue_7)
-        *(.rodata .rodata* .gnu.linkonce.r.*)
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-
-        /* Support C constructors, and C destructors in both user code
-           and the C library. This also provides support for C++ code. */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-
-        . = ALIGN(4);
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-
-        . = ALIGN(4);
-        KEEP(*(.fini))
-
-        . = ALIGN(4);
-        __fini_array_start = .;
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        __fini_array_end = .;
-
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-
-        . = ALIGN(4);
-        _efixed = .;            /* End of text section */
-    } > rom
-
-    /* .ARM.exidx is sorted, so has to go in its own output section.  */
-    PROVIDE_HIDDEN (__exidx_start = .);
-    .ARM.exidx :
-    {
-      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > rom
-    PROVIDE_HIDDEN (__exidx_end = .);
-
-    . = ALIGN(4);
-    _etext = .;
-
-    .relocate : AT (_etext)
-    {
-        . = ALIGN(4);
-        _srelocate = .;
-        *(.ramfunc .ramfunc.*);
-        *(.data .data.*);
-        . = ALIGN(4);
-        _erelocate = .;
-    } > ram
-
-    /* .bss section which is used for uninitialized data */
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        _sbss = . ;
-        _szero = .;
-        *(.bss .bss.*)
-        *(COMMON)
-        . = ALIGN(4);
-        _ebss = . ;
-        _ezero = .;
-        end = .;
-    } > ram
-
-    /* stack section */
-    .stack (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sstack = .;
-        . = . + STACK_SIZE;
-        . = ALIGN(8);
-        _estack = .;
-    } > ram
-
-    . = ALIGN(4);
-    _end = . ;
-}
diff --git a/tinyusb/hw/bsp/samd21/boards/circuitplayground_express/board.h b/tinyusb/hw/bsp/samd21/boards/circuitplayground_express/board.h
deleted file mode 100755
index 2d7da1c0..00000000
--- a/tinyusb/hw/bsp/samd21/boards/circuitplayground_express/board.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PIN               17
-#define LED_STATE_ON          1
-
-// Button
-#define BUTTON_PIN            28
-#define BUTTON_STATE_ACTIVE   1
-
-// UART
-#define UART_RX_PIN           4
-#define UART_TX_PIN           5
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/samd21/boards/circuitplayground_express/board.mk b/tinyusb/hw/bsp/samd21/boards/circuitplayground_express/board.mk
deleted file mode 100755
index bb426cda..00000000
--- a/tinyusb/hw/bsp/samd21/boards/circuitplayground_express/board.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-CFLAGS += -D__SAMD21G18A__
-
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/$(BOARD).ld
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAMD21G18
-
-flash: flash-bossac
diff --git a/tinyusb/hw/bsp/samd21/boards/circuitplayground_express/circuitplayground_express.ld b/tinyusb/hw/bsp/samd21/boards/circuitplayground_express/circuitplayground_express.ld
deleted file mode 100755
index f0c93340..00000000
--- a/tinyusb/hw/bsp/samd21/boards/circuitplayground_express/circuitplayground_express.ld
+++ /dev/null
@@ -1,146 +0,0 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD21G18A
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-SEARCH_DIR(.)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-  rom      (rx)  : ORIGIN = 0x00000000 + 8K, LENGTH = 0x00040000 - 8K
-  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
-}
-
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
-
-ENTRY(Reset_Handler)
-
-/* Section Definitions */
-SECTIONS
-{
-    .text :
-    {
-        . = ALIGN(4);
-        _sfixed = .;
-        KEEP(*(.vectors .vectors.*))
-        *(.text .text.* .gnu.linkonce.t.*)
-        *(.glue_7t) *(.glue_7)
-        *(.rodata .rodata* .gnu.linkonce.r.*)
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-
-        /* Support C constructors, and C destructors in both user code
-           and the C library. This also provides support for C++ code. */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-
-        . = ALIGN(4);
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-
-        . = ALIGN(4);
-        KEEP(*(.fini))
-
-        . = ALIGN(4);
-        __fini_array_start = .;
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        __fini_array_end = .;
-
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-
-        . = ALIGN(4);
-        _efixed = .;            /* End of text section */
-    } > rom
-
-    /* .ARM.exidx is sorted, so has to go in its own output section.  */
-    PROVIDE_HIDDEN (__exidx_start = .);
-    .ARM.exidx :
-    {
-      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > rom
-    PROVIDE_HIDDEN (__exidx_end = .);
-
-    . = ALIGN(4);
-    _etext = .;
-
-    .relocate : AT (_etext)
-    {
-        . = ALIGN(4);
-        _srelocate = .;
-        *(.ramfunc .ramfunc.*);
-        *(.data .data.*);
-        . = ALIGN(4);
-        _erelocate = .;
-    } > ram
-
-    /* .bss section which is used for uninitialized data */
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        _sbss = . ;
-        _szero = .;
-        *(.bss .bss.*)
-        *(COMMON)
-        . = ALIGN(4);
-        _ebss = . ;
-        _ezero = .;
-        end = .;
-    } > ram
-
-    /* stack section */
-    .stack (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sstack = .;
-        . = . + STACK_SIZE;
-        . = ALIGN(8);
-        _estack = .;
-    } > ram
-
-    . = ALIGN(4);
-    _end = . ;
-}
diff --git a/tinyusb/hw/bsp/samd21/boards/feather_m0_express/board.h b/tinyusb/hw/bsp/samd21/boards/feather_m0_express/board.h
deleted file mode 100755
index b9292b9a..00000000
--- a/tinyusb/hw/bsp/samd21/boards/feather_m0_express/board.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PIN               17
-#define LED_STATE_ON          1
-
-// Button
-#define BUTTON_PIN            15
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_RX_PIN           4
-#define UART_TX_PIN           5
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/samd21/boards/feather_m0_express/board.mk b/tinyusb/hw/bsp/samd21/boards/feather_m0_express/board.mk
deleted file mode 100755
index bb426cda..00000000
--- a/tinyusb/hw/bsp/samd21/boards/feather_m0_express/board.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-CFLAGS += -D__SAMD21G18A__
-
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/$(BOARD).ld
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAMD21G18
-
-flash: flash-bossac
diff --git a/tinyusb/hw/bsp/samd21/boards/feather_m0_express/feather_m0_express.ld b/tinyusb/hw/bsp/samd21/boards/feather_m0_express/feather_m0_express.ld
deleted file mode 100755
index f0c93340..00000000
--- a/tinyusb/hw/bsp/samd21/boards/feather_m0_express/feather_m0_express.ld
+++ /dev/null
@@ -1,146 +0,0 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD21G18A
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-SEARCH_DIR(.)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-  rom      (rx)  : ORIGIN = 0x00000000 + 8K, LENGTH = 0x00040000 - 8K
-  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
-}
-
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
-
-ENTRY(Reset_Handler)
-
-/* Section Definitions */
-SECTIONS
-{
-    .text :
-    {
-        . = ALIGN(4);
-        _sfixed = .;
-        KEEP(*(.vectors .vectors.*))
-        *(.text .text.* .gnu.linkonce.t.*)
-        *(.glue_7t) *(.glue_7)
-        *(.rodata .rodata* .gnu.linkonce.r.*)
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-
-        /* Support C constructors, and C destructors in both user code
-           and the C library. This also provides support for C++ code. */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-
-        . = ALIGN(4);
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-
-        . = ALIGN(4);
-        KEEP(*(.fini))
-
-        . = ALIGN(4);
-        __fini_array_start = .;
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        __fini_array_end = .;
-
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-
-        . = ALIGN(4);
-        _efixed = .;            /* End of text section */
-    } > rom
-
-    /* .ARM.exidx is sorted, so has to go in its own output section.  */
-    PROVIDE_HIDDEN (__exidx_start = .);
-    .ARM.exidx :
-    {
-      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > rom
-    PROVIDE_HIDDEN (__exidx_end = .);
-
-    . = ALIGN(4);
-    _etext = .;
-
-    .relocate : AT (_etext)
-    {
-        . = ALIGN(4);
-        _srelocate = .;
-        *(.ramfunc .ramfunc.*);
-        *(.data .data.*);
-        . = ALIGN(4);
-        _erelocate = .;
-    } > ram
-
-    /* .bss section which is used for uninitialized data */
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        _sbss = . ;
-        _szero = .;
-        *(.bss .bss.*)
-        *(COMMON)
-        . = ALIGN(4);
-        _ebss = . ;
-        _ezero = .;
-        end = .;
-    } > ram
-
-    /* stack section */
-    .stack (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sstack = .;
-        . = . + STACK_SIZE;
-        . = ALIGN(8);
-        _estack = .;
-    } > ram
-
-    . = ALIGN(4);
-    _end = . ;
-}
diff --git a/tinyusb/hw/bsp/samd21/boards/itsybitsy_m0/board.h b/tinyusb/hw/bsp/samd21/boards/itsybitsy_m0/board.h
deleted file mode 100755
index 177fb695..00000000
--- a/tinyusb/hw/bsp/samd21/boards/itsybitsy_m0/board.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PIN               17
-#define LED_STATE_ON          1
-
-// Button
-#define BUTTON_PIN            21
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_RX_PIN           4
-#define UART_TX_PIN           5
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/samd21/boards/itsybitsy_m0/board.mk b/tinyusb/hw/bsp/samd21/boards/itsybitsy_m0/board.mk
deleted file mode 100755
index bb426cda..00000000
--- a/tinyusb/hw/bsp/samd21/boards/itsybitsy_m0/board.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-CFLAGS += -D__SAMD21G18A__
-
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/$(BOARD).ld
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAMD21G18
-
-flash: flash-bossac
diff --git a/tinyusb/hw/bsp/samd21/boards/itsybitsy_m0/itsybitsy_m0.ld b/tinyusb/hw/bsp/samd21/boards/itsybitsy_m0/itsybitsy_m0.ld
deleted file mode 100755
index f0c93340..00000000
--- a/tinyusb/hw/bsp/samd21/boards/itsybitsy_m0/itsybitsy_m0.ld
+++ /dev/null
@@ -1,146 +0,0 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD21G18A
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-SEARCH_DIR(.)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-  rom      (rx)  : ORIGIN = 0x00000000 + 8K, LENGTH = 0x00040000 - 8K
-  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
-}
-
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
-
-ENTRY(Reset_Handler)
-
-/* Section Definitions */
-SECTIONS
-{
-    .text :
-    {
-        . = ALIGN(4);
-        _sfixed = .;
-        KEEP(*(.vectors .vectors.*))
-        *(.text .text.* .gnu.linkonce.t.*)
-        *(.glue_7t) *(.glue_7)
-        *(.rodata .rodata* .gnu.linkonce.r.*)
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-
-        /* Support C constructors, and C destructors in both user code
-           and the C library. This also provides support for C++ code. */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-
-        . = ALIGN(4);
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-
-        . = ALIGN(4);
-        KEEP(*(.fini))
-
-        . = ALIGN(4);
-        __fini_array_start = .;
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        __fini_array_end = .;
-
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-
-        . = ALIGN(4);
-        _efixed = .;            /* End of text section */
-    } > rom
-
-    /* .ARM.exidx is sorted, so has to go in its own output section.  */
-    PROVIDE_HIDDEN (__exidx_start = .);
-    .ARM.exidx :
-    {
-      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > rom
-    PROVIDE_HIDDEN (__exidx_end = .);
-
-    . = ALIGN(4);
-    _etext = .;
-
-    .relocate : AT (_etext)
-    {
-        . = ALIGN(4);
-        _srelocate = .;
-        *(.ramfunc .ramfunc.*);
-        *(.data .data.*);
-        . = ALIGN(4);
-        _erelocate = .;
-    } > ram
-
-    /* .bss section which is used for uninitialized data */
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        _sbss = . ;
-        _szero = .;
-        *(.bss .bss.*)
-        *(COMMON)
-        . = ALIGN(4);
-        _ebss = . ;
-        _ezero = .;
-        end = .;
-    } > ram
-
-    /* stack section */
-    .stack (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sstack = .;
-        . = . + STACK_SIZE;
-        . = ALIGN(8);
-        _estack = .;
-    } > ram
-
-    . = ALIGN(4);
-    _end = . ;
-}
diff --git a/tinyusb/hw/bsp/samd21/boards/luna_d21/board.h b/tinyusb/hw/bsp/samd21/boards/luna_d21/board.h
deleted file mode 100755
index 2e0a2a60..00000000
--- a/tinyusb/hw/bsp/samd21/boards/luna_d21/board.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PIN               PIN_PA22
-#define LED_STATE_ON          1
-
-// Button
-#define BUTTON_PIN            PIN_PB22
-#define BUTTON_STATE_ACTIVE   0
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/samd21/boards/luna_d21/board.mk b/tinyusb/hw/bsp/samd21/boards/luna_d21/board.mk
deleted file mode 100755
index 5beb5e02..00000000
--- a/tinyusb/hw/bsp/samd21/boards/luna_d21/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-CFLAGS += -D__SAMD21G18A__
-
-LD_FILE = $(BOARD_PATH)/samd21g18a_flash.ld
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAMD21G18
-
-# flash using dfu-util
-flash: $(BUILD)/$(PROJECT).bin
-	dfu-util -a 0 -d 1d50:615c -D $< || dfu-util -a 0 -d 16d0:05a5 -D $<
-
diff --git a/tinyusb/hw/bsp/samd21/boards/luna_d21/samd21g18a_flash.ld b/tinyusb/hw/bsp/samd21/boards/luna_d21/samd21g18a_flash.ld
deleted file mode 100755
index 15859303..00000000
--- a/tinyusb/hw/bsp/samd21/boards/luna_d21/samd21g18a_flash.ld
+++ /dev/null
@@ -1,144 +0,0 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD21G18A
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-SEARCH_DIR(.)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-  rom      (rx)  : ORIGIN = 0x00000000 + 4K, LENGTH = 0x00040000 - 4K
-  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
-}
-
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
-
-/* Section Definitions */
-SECTIONS
-{
-    .text :
-    {
-        . = ALIGN(4);
-        _sfixed = .;
-        KEEP(*(.vectors .vectors.*))
-        *(.text .text.* .gnu.linkonce.t.*)
-        *(.glue_7t) *(.glue_7)
-        *(.rodata .rodata* .gnu.linkonce.r.*)
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-
-        /* Support C constructors, and C destructors in both user code
-           and the C library. This also provides support for C++ code. */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-
-        . = ALIGN(4);
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-
-        . = ALIGN(4);
-        KEEP(*(.fini))
-
-        . = ALIGN(4);
-        __fini_array_start = .;
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        __fini_array_end = .;
-
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-
-        . = ALIGN(4);
-        _efixed = .;            /* End of text section */
-    } > rom
-
-    /* .ARM.exidx is sorted, so has to go in its own output section.  */
-    PROVIDE_HIDDEN (__exidx_start = .);
-    .ARM.exidx :
-    {
-      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > rom
-    PROVIDE_HIDDEN (__exidx_end = .);
-
-    . = ALIGN(4);
-    _etext = .;
-
-    .relocate : AT (_etext)
-    {
-        . = ALIGN(4);
-        _srelocate = .;
-        *(.ramfunc .ramfunc.*);
-        *(.data .data.*);
-        . = ALIGN(4);
-        _erelocate = .;
-    } > ram
-
-    /* .bss section which is used for uninitialized data */
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        _sbss = . ;
-        _szero = .;
-        *(.bss .bss.*)
-        *(COMMON)
-        . = ALIGN(4);
-        _ebss = . ;
-        _ezero = .;
-        end = .;
-    } > ram
-
-    /* stack section */
-    .stack (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sstack = .;
-        . = . + STACK_SIZE;
-        . = ALIGN(8);
-        _estack = .;
-    } > ram
-
-    . = ALIGN(4);
-    _end = . ;
-}
diff --git a/tinyusb/hw/bsp/samd21/boards/metro_m0_express/board.h b/tinyusb/hw/bsp/samd21/boards/metro_m0_express/board.h
deleted file mode 100755
index b9292b9a..00000000
--- a/tinyusb/hw/bsp/samd21/boards/metro_m0_express/board.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PIN               17
-#define LED_STATE_ON          1
-
-// Button
-#define BUTTON_PIN            15
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_RX_PIN           4
-#define UART_TX_PIN           5
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/samd21/boards/metro_m0_express/board.mk b/tinyusb/hw/bsp/samd21/boards/metro_m0_express/board.mk
deleted file mode 100755
index bb426cda..00000000
--- a/tinyusb/hw/bsp/samd21/boards/metro_m0_express/board.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-CFLAGS += -D__SAMD21G18A__
-
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/$(BOARD).ld
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAMD21G18
-
-flash: flash-bossac
diff --git a/tinyusb/hw/bsp/samd21/boards/metro_m0_express/metro_m0_express.ld b/tinyusb/hw/bsp/samd21/boards/metro_m0_express/metro_m0_express.ld
deleted file mode 100755
index f0c93340..00000000
--- a/tinyusb/hw/bsp/samd21/boards/metro_m0_express/metro_m0_express.ld
+++ /dev/null
@@ -1,146 +0,0 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD21G18A
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-SEARCH_DIR(.)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-  rom      (rx)  : ORIGIN = 0x00000000 + 8K, LENGTH = 0x00040000 - 8K
-  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
-}
-
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
-
-ENTRY(Reset_Handler)
-
-/* Section Definitions */
-SECTIONS
-{
-    .text :
-    {
-        . = ALIGN(4);
-        _sfixed = .;
-        KEEP(*(.vectors .vectors.*))
-        *(.text .text.* .gnu.linkonce.t.*)
-        *(.glue_7t) *(.glue_7)
-        *(.rodata .rodata* .gnu.linkonce.r.*)
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-
-        /* Support C constructors, and C destructors in both user code
-           and the C library. This also provides support for C++ code. */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-
-        . = ALIGN(4);
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-
-        . = ALIGN(4);
-        KEEP(*(.fini))
-
-        . = ALIGN(4);
-        __fini_array_start = .;
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        __fini_array_end = .;
-
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-
-        . = ALIGN(4);
-        _efixed = .;            /* End of text section */
-    } > rom
-
-    /* .ARM.exidx is sorted, so has to go in its own output section.  */
-    PROVIDE_HIDDEN (__exidx_start = .);
-    .ARM.exidx :
-    {
-      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > rom
-    PROVIDE_HIDDEN (__exidx_end = .);
-
-    . = ALIGN(4);
-    _etext = .;
-
-    .relocate : AT (_etext)
-    {
-        . = ALIGN(4);
-        _srelocate = .;
-        *(.ramfunc .ramfunc.*);
-        *(.data .data.*);
-        . = ALIGN(4);
-        _erelocate = .;
-    } > ram
-
-    /* .bss section which is used for uninitialized data */
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        _sbss = . ;
-        _szero = .;
-        *(.bss .bss.*)
-        *(COMMON)
-        . = ALIGN(4);
-        _ebss = . ;
-        _ezero = .;
-        end = .;
-    } > ram
-
-    /* stack section */
-    .stack (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sstack = .;
-        . = . + STACK_SIZE;
-        . = ALIGN(8);
-        _estack = .;
-    } > ram
-
-    . = ALIGN(4);
-    _end = . ;
-}
diff --git a/tinyusb/hw/bsp/samd21/boards/seeeduino_xiao/board.h b/tinyusb/hw/bsp/samd21/boards/seeeduino_xiao/board.h
deleted file mode 100755
index 0d1e9cef..00000000
--- a/tinyusb/hw/bsp/samd21/boards/seeeduino_xiao/board.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PIN               17
-#define LED_STATE_ON          0
-
-// Button
-#define BUTTON_PIN            9 // PA4 pin D1 on seed input
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_RX_PIN           4
-#define UART_TX_PIN           5
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/samd21/boards/seeeduino_xiao/board.mk b/tinyusb/hw/bsp/samd21/boards/seeeduino_xiao/board.mk
deleted file mode 100755
index 54591b3a..00000000
--- a/tinyusb/hw/bsp/samd21/boards/seeeduino_xiao/board.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-CFLAGS += -D__SAMD21G18A__
-
-LD_FILE = $(BOARD_PATH)/$(BOARD).ld
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAMD21G18
-
-# flash using jlink
-flash: flash-jlink
diff --git a/tinyusb/hw/bsp/samd21/boards/seeeduino_xiao/seeeduino_xiao.ld b/tinyusb/hw/bsp/samd21/boards/seeeduino_xiao/seeeduino_xiao.ld
deleted file mode 100755
index cf11c4c3..00000000
--- a/tinyusb/hw/bsp/samd21/boards/seeeduino_xiao/seeeduino_xiao.ld
+++ /dev/null
@@ -1,146 +0,0 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD21G18A
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-SEARCH_DIR(.)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-  rom      (rx)  : ORIGIN = 0x00000000 + 8K, LENGTH = 0x00040000 - 8K  /* 8K offset to preserve bootloader */
-  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
-}
-
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
-
-ENTRY(Reset_Handler)
-
-/* Section Definitions */
-SECTIONS
-{
-    .text :
-    {
-        . = ALIGN(4);
-        _sfixed = .;
-        KEEP(*(.vectors .vectors.*))
-        *(.text .text.* .gnu.linkonce.t.*)
-        *(.glue_7t) *(.glue_7)
-        *(.rodata .rodata* .gnu.linkonce.r.*)
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-
-        /* Support C constructors, and C destructors in both user code
-           and the C library. This also provides support for C++ code. */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-
-        . = ALIGN(4);
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-
-        . = ALIGN(4);
-        KEEP(*(.fini))
-
-        . = ALIGN(4);
-        __fini_array_start = .;
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        __fini_array_end = .;
-
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-
-        . = ALIGN(4);
-        _efixed = .;            /* End of text section */
-    } > rom
-
-    /* .ARM.exidx is sorted, so has to go in its own output section.  */
-    PROVIDE_HIDDEN (__exidx_start = .);
-    .ARM.exidx :
-    {
-      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > rom
-    PROVIDE_HIDDEN (__exidx_end = .);
-
-    . = ALIGN(4);
-    _etext = .;
-
-    .relocate : AT (_etext)
-    {
-        . = ALIGN(4);
-        _srelocate = .;
-        *(.ramfunc .ramfunc.*);
-        *(.data .data.*);
-        . = ALIGN(4);
-        _erelocate = .;
-    } > ram
-
-    /* .bss section which is used for uninitialized data */
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        _sbss = . ;
-        _szero = .;
-        *(.bss .bss.*)
-        *(COMMON)
-        . = ALIGN(4);
-        _ebss = . ;
-        _ezero = .;
-        end = .;
-    } > ram
-
-    /* stack section */
-    .stack (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sstack = .;
-        . = . + STACK_SIZE;
-        . = ALIGN(8);
-        _estack = .;
-    } > ram
-
-    . = ALIGN(4);
-    _end = . ;
-}
diff --git a/tinyusb/hw/bsp/samd21/family.c b/tinyusb/hw/bsp/samd21/family.c
deleted file mode 100755
index eb5b5586..00000000
--- a/tinyusb/hw/bsp/samd21/family.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "sam.h"
-#include "bsp/board.h"
-#include "board.h"
-
-#include "hal/include/hal_gpio.h"
-#include "hal/include/hal_init.h"
-#include "hri/hri_nvmctrl_d21.h"
-
-#include "hpl/gclk/hpl_gclk_base.h"
-#include "hpl_pm_config.h"
-#include "hpl/pm/hpl_pm_base.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_Handler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-
-/* Referenced GCLKs, should be initialized firstly */
-#define _GCLK_INIT_1ST (1 << 0 | 1 << 1)
-
-/* Not referenced GCLKs, initialized last */
-#define _GCLK_INIT_LAST (~_GCLK_INIT_1ST)
-
-void board_init(void)
-{
-  // Clock init ( follow hpl_init.c )
-  hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, 2);
-
-  _pm_init();
-  _sysctrl_init_sources();
-#if _GCLK_INIT_1ST
-  _gclk_init_generators_by_fref(_GCLK_INIT_1ST);
-#endif
-  _sysctrl_init_referenced_generators();
-  _gclk_init_generators_by_fref(_GCLK_INIT_LAST);
-
-  // Update SystemCoreClock since it is hard coded with asf4 and not correct
-  // Init 1ms tick timer (samd SystemCoreClock may not correct)
-  SystemCoreClock = CONF_CPU_FREQUENCY;
-  SysTick_Config(CONF_CPU_FREQUENCY / 1000);
-
-  // Led init
-  gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
-  board_led_write(false);
-
-  // Button init
-  gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
-  gpio_set_pin_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULL_DOWN : GPIO_PULL_UP);
-
-#if CFG_TUSB_OS  == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-#endif
-
-  /* USB Clock init
-   * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock
-   * for low speed and full speed operation. */
-  _pm_enable_bus_clock(PM_BUS_APBB, USB);
-  _pm_enable_bus_clock(PM_BUS_AHB, USB);
-  _gclk_enable_channel(USB_GCLK_ID, GCLK_CLKCTRL_GEN_GCLK0_Val);
-
-  // USB Pin Init
-  gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT);
-  gpio_set_pin_level(PIN_PA24, false);
-  gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF);
-  gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT);
-  gpio_set_pin_level(PIN_PA25, false);
-  gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF);
-
-  gpio_set_pin_function(PIN_PA24, PINMUX_PA24G_USB_DM);
-  gpio_set_pin_function(PIN_PA25, PINMUX_PA25G_USB_DP);
-
-  // Output 500hz PWM on D12 (PA19 - TCC0 WO[3]) so we can validate the GCLK0 clock speed with a Saleae.
-  _pm_enable_bus_clock(PM_BUS_APBC, TCC0);
-  TCC0->PER.bit.PER = 48000000 / 1000;
-  TCC0->CC[3].bit.CC = 48000000 / 2000;
-  TCC0->CTRLA.bit.ENABLE = true;
-
-  gpio_set_pin_function(PIN_PA19, PINMUX_PA19F_TCC0_WO3);
-  _gclk_enable_channel(TCC0_GCLK_ID, GCLK_CLKCTRL_GEN_GCLK0_Val);
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  gpio_set_pin_level(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == gpio_get_pin_level(BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/tinyusb/hw/bsp/samd21/family.mk b/tinyusb/hw/bsp/samd21/family.mk
deleted file mode 100755
index f1b063f2..00000000
--- a/tinyusb/hw/bsp/samd21/family.mk
+++ /dev/null
@@ -1,46 +0,0 @@
-UF2_FAMILY_ID = 0x68ed2b88
-DEPS_SUBMODULES += hw/mcu/microchip
-
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
-  -nostdlib -nostartfiles \
-  -DCONF_DFLL_OVERWRITE_CALIBRATION=0 \
-  -DCFG_TUSB_MCU=OPT_MCU_SAMD21
-
-SRC_C += \
-	src/portable/microchip/samd/dcd_samd.c \
-	hw/mcu/microchip/samd21/gcc/gcc/startup_samd21.c \
-	hw/mcu/microchip/samd21/gcc/system_samd21.c \
-	hw/mcu/microchip/samd21/hpl/gclk/hpl_gclk.c \
-	hw/mcu/microchip/samd21/hpl/pm/hpl_pm.c \
-	hw/mcu/microchip/samd21/hpl/sysctrl/hpl_sysctrl.c \
-	hw/mcu/microchip/samd21/hal/src/hal_atomic.c
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/hw/mcu/microchip/samd21/ \
-	$(TOP)/hw/mcu/microchip/samd21/config \
-	$(TOP)/hw/mcu/microchip/samd21/include \
-	$(TOP)/hw/mcu/microchip/samd21/hal/include \
-	$(TOP)/hw/mcu/microchip/samd21/hal/utils/include \
-	$(TOP)/hw/mcu/microchip/samd21/hpl/pm/ \
-	$(TOP)/hw/mcu/microchip/samd21/hpl/port \
-	$(TOP)/hw/mcu/microchip/samd21/hri \
-	$(TOP)/hw/mcu/microchip/samd21/CMSIS/Include
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
-
-# flash using bossac at least version 1.8
-# can be found in arduino15/packages/arduino/tools/bossac/
-# Add it to your PATH or change BOSSAC variable to match your installation
-BOSSAC = bossac
-
-flash-bossac: $(BUILD)/$(PROJECT).bin
-	@:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyACM0)
-	$(BOSSAC) --port=$(SERIAL) -U -i --offset=0x2000 -e -w $^ -R
diff --git a/tinyusb/hw/bsp/samd51/boards/feather_m4_express/board.h b/tinyusb/hw/bsp/samd51/boards/feather_m4_express/board.h
deleted file mode 100755
index 1d5ed804..00000000
--- a/tinyusb/hw/bsp/samd51/boards/feather_m4_express/board.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PIN               23
-#define LED_STATE_ON          1
-
-// Button
-#define BUTTON_PIN            16 // D5
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_TX_PIN           (32 + 17)
-#define UART_RX_PIN           (32 + 16)
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/samd51/boards/feather_m4_express/board.mk b/tinyusb/hw/bsp/samd51/boards/feather_m4_express/board.mk
deleted file mode 100755
index a8a98a98..00000000
--- a/tinyusb/hw/bsp/samd51/boards/feather_m4_express/board.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-CFLAGS += -D__SAMD51J19A__
-
-LD_FILE = $(BOARD_PATH)/$(BOARD).ld
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAMD51J19
-
-flash: flash-bossac
diff --git a/tinyusb/hw/bsp/samd51/boards/feather_m4_express/feather_m4_express.ld b/tinyusb/hw/bsp/samd51/boards/feather_m4_express/feather_m4_express.ld
deleted file mode 100755
index f1a021d7..00000000
--- a/tinyusb/hw/bsp/samd51/boards/feather_m4_express/feather_m4_express.ld
+++ /dev/null
@@ -1,166 +0,0 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD51G19A
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-SEARCH_DIR(.)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-  rom      (rx)  : ORIGIN = 0x00000000 + 16K, LENGTH = 0x00080000 - 16K
-  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
-  bkupram  (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
-  qspi     (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
-}
-
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
-
-ENTRY(Reset_Handler)
-
-/* Section Definitions */
-SECTIONS
-{
-    .text :
-    {
-        . = ALIGN(4);
-        _sfixed = .;
-        KEEP(*(.vectors .vectors.*))
-        *(.text .text.* .gnu.linkonce.t.*)
-        *(.glue_7t) *(.glue_7)
-        *(.rodata .rodata* .gnu.linkonce.r.*)
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-
-        /* Support C constructors, and C destructors in both user code
-           and the C library. This also provides support for C++ code. */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-
-        . = ALIGN(4);
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-
-        . = ALIGN(4);
-        KEEP(*(.fini))
-
-        . = ALIGN(4);
-        __fini_array_start = .;
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        __fini_array_end = .;
-
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-
-        . = ALIGN(4);
-        _efixed = .;            /* End of text section */
-    } > rom
-
-    /* .ARM.exidx is sorted, so has to go in its own output section.  */
-    PROVIDE_HIDDEN (__exidx_start = .);
-    .ARM.exidx :
-    {
-      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > rom
-    PROVIDE_HIDDEN (__exidx_end = .);
-
-    . = ALIGN(4);
-    _etext = .;
-
-    .relocate : AT (_etext)
-    {
-        . = ALIGN(4);
-        _srelocate = .;
-        *(.ramfunc .ramfunc.*);
-        *(.data .data.*);
-        . = ALIGN(4);
-        _erelocate = .;
-    } > ram
-
-    .bkupram (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sbkupram = .;
-        *(.bkupram .bkupram.*);
-        . = ALIGN(8);
-        _ebkupram = .;
-    } > bkupram
-
-    .qspi (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sqspi = .;
-        *(.qspi .qspi.*);
-        . = ALIGN(8);
-        _eqspi = .;
-    } > qspi
-
-    /* .bss section which is used for uninitialized data */
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        _sbss = . ;
-        _szero = .;
-        *(.bss .bss.*)
-        *(COMMON)
-        . = ALIGN(4);
-        _ebss = . ;
-        _ezero = .;
-        end = .;
-    } > ram
-
-    /* stack section */
-    .stack (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sstack = .;
-        . = . + STACK_SIZE;
-        . = ALIGN(8);
-        _estack = .;
-    } > ram
-
-    . = ALIGN(4);
-    _end = . ;
-}
diff --git a/tinyusb/hw/bsp/samd51/boards/itsybitsy_m4/board.h b/tinyusb/hw/bsp/samd51/boards/itsybitsy_m4/board.h
deleted file mode 100755
index 0760d428..00000000
--- a/tinyusb/hw/bsp/samd51/boards/itsybitsy_m4/board.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PIN               22
-#define LED_STATE_ON          1
-
-// Button
-#define BUTTON_PIN            18 // D5
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_TX_PIN           16
-#define UART_RX_PIN           17
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/samd51/boards/itsybitsy_m4/board.mk b/tinyusb/hw/bsp/samd51/boards/itsybitsy_m4/board.mk
deleted file mode 100755
index 57a680e9..00000000
--- a/tinyusb/hw/bsp/samd51/boards/itsybitsy_m4/board.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-CFLAGS += -D__SAMD51J19A__
-
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/$(BOARD).ld
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAMD51J19
-
-flash: flash-bossac
diff --git a/tinyusb/hw/bsp/samd51/boards/itsybitsy_m4/itsybitsy_m4.ld b/tinyusb/hw/bsp/samd51/boards/itsybitsy_m4/itsybitsy_m4.ld
deleted file mode 100755
index f1a021d7..00000000
--- a/tinyusb/hw/bsp/samd51/boards/itsybitsy_m4/itsybitsy_m4.ld
+++ /dev/null
@@ -1,166 +0,0 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD51G19A
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-SEARCH_DIR(.)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-  rom      (rx)  : ORIGIN = 0x00000000 + 16K, LENGTH = 0x00080000 - 16K
-  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
-  bkupram  (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
-  qspi     (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
-}
-
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
-
-ENTRY(Reset_Handler)
-
-/* Section Definitions */
-SECTIONS
-{
-    .text :
-    {
-        . = ALIGN(4);
-        _sfixed = .;
-        KEEP(*(.vectors .vectors.*))
-        *(.text .text.* .gnu.linkonce.t.*)
-        *(.glue_7t) *(.glue_7)
-        *(.rodata .rodata* .gnu.linkonce.r.*)
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-
-        /* Support C constructors, and C destructors in both user code
-           and the C library. This also provides support for C++ code. */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-
-        . = ALIGN(4);
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-
-        . = ALIGN(4);
-        KEEP(*(.fini))
-
-        . = ALIGN(4);
-        __fini_array_start = .;
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        __fini_array_end = .;
-
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-
-        . = ALIGN(4);
-        _efixed = .;            /* End of text section */
-    } > rom
-
-    /* .ARM.exidx is sorted, so has to go in its own output section.  */
-    PROVIDE_HIDDEN (__exidx_start = .);
-    .ARM.exidx :
-    {
-      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > rom
-    PROVIDE_HIDDEN (__exidx_end = .);
-
-    . = ALIGN(4);
-    _etext = .;
-
-    .relocate : AT (_etext)
-    {
-        . = ALIGN(4);
-        _srelocate = .;
-        *(.ramfunc .ramfunc.*);
-        *(.data .data.*);
-        . = ALIGN(4);
-        _erelocate = .;
-    } > ram
-
-    .bkupram (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sbkupram = .;
-        *(.bkupram .bkupram.*);
-        . = ALIGN(8);
-        _ebkupram = .;
-    } > bkupram
-
-    .qspi (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sqspi = .;
-        *(.qspi .qspi.*);
-        . = ALIGN(8);
-        _eqspi = .;
-    } > qspi
-
-    /* .bss section which is used for uninitialized data */
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        _sbss = . ;
-        _szero = .;
-        *(.bss .bss.*)
-        *(COMMON)
-        . = ALIGN(4);
-        _ebss = . ;
-        _ezero = .;
-        end = .;
-    } > ram
-
-    /* stack section */
-    .stack (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sstack = .;
-        . = . + STACK_SIZE;
-        . = ALIGN(8);
-        _estack = .;
-    } > ram
-
-    . = ALIGN(4);
-    _end = . ;
-}
diff --git a/tinyusb/hw/bsp/samd51/boards/metro_m4_express/board.h b/tinyusb/hw/bsp/samd51/boards/metro_m4_express/board.h
deleted file mode 100755
index 9bb5f815..00000000
--- a/tinyusb/hw/bsp/samd51/boards/metro_m4_express/board.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PIN               16
-#define LED_STATE_ON          1
-
-// Button
-#define BUTTON_PIN            (32+14) // D5
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_TX_PIN           23
-#define UART_RX_PIN           22
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/samd51/boards/metro_m4_express/board.mk b/tinyusb/hw/bsp/samd51/boards/metro_m4_express/board.mk
deleted file mode 100755
index d7953cc2..00000000
--- a/tinyusb/hw/bsp/samd51/boards/metro_m4_express/board.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-CFLAGS += -D__SAMD51J19A__
-
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/$(BOARD).ld
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAMD51J19
-
-flash: flash-bossac
-
diff --git a/tinyusb/hw/bsp/samd51/boards/metro_m4_express/metro_m4_express.ld b/tinyusb/hw/bsp/samd51/boards/metro_m4_express/metro_m4_express.ld
deleted file mode 100755
index f1a021d7..00000000
--- a/tinyusb/hw/bsp/samd51/boards/metro_m4_express/metro_m4_express.ld
+++ /dev/null
@@ -1,166 +0,0 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD51G19A
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-SEARCH_DIR(.)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-  rom      (rx)  : ORIGIN = 0x00000000 + 16K, LENGTH = 0x00080000 - 16K
-  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
-  bkupram  (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
-  qspi     (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
-}
-
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
-
-ENTRY(Reset_Handler)
-
-/* Section Definitions */
-SECTIONS
-{
-    .text :
-    {
-        . = ALIGN(4);
-        _sfixed = .;
-        KEEP(*(.vectors .vectors.*))
-        *(.text .text.* .gnu.linkonce.t.*)
-        *(.glue_7t) *(.glue_7)
-        *(.rodata .rodata* .gnu.linkonce.r.*)
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-
-        /* Support C constructors, and C destructors in both user code
-           and the C library. This also provides support for C++ code. */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-
-        . = ALIGN(4);
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-
-        . = ALIGN(4);
-        KEEP(*(.fini))
-
-        . = ALIGN(4);
-        __fini_array_start = .;
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        __fini_array_end = .;
-
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-
-        . = ALIGN(4);
-        _efixed = .;            /* End of text section */
-    } > rom
-
-    /* .ARM.exidx is sorted, so has to go in its own output section.  */
-    PROVIDE_HIDDEN (__exidx_start = .);
-    .ARM.exidx :
-    {
-      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > rom
-    PROVIDE_HIDDEN (__exidx_end = .);
-
-    . = ALIGN(4);
-    _etext = .;
-
-    .relocate : AT (_etext)
-    {
-        . = ALIGN(4);
-        _srelocate = .;
-        *(.ramfunc .ramfunc.*);
-        *(.data .data.*);
-        . = ALIGN(4);
-        _erelocate = .;
-    } > ram
-
-    .bkupram (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sbkupram = .;
-        *(.bkupram .bkupram.*);
-        . = ALIGN(8);
-        _ebkupram = .;
-    } > bkupram
-
-    .qspi (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sqspi = .;
-        *(.qspi .qspi.*);
-        . = ALIGN(8);
-        _eqspi = .;
-    } > qspi
-
-    /* .bss section which is used for uninitialized data */
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        _sbss = . ;
-        _szero = .;
-        *(.bss .bss.*)
-        *(COMMON)
-        . = ALIGN(4);
-        _ebss = . ;
-        _ezero = .;
-        end = .;
-    } > ram
-
-    /* stack section */
-    .stack (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sstack = .;
-        . = . + STACK_SIZE;
-        . = ALIGN(8);
-        _estack = .;
-    } > ram
-
-    . = ALIGN(4);
-    _end = . ;
-}
diff --git a/tinyusb/hw/bsp/samd51/boards/pybadge/board.h b/tinyusb/hw/bsp/samd51/boards/pybadge/board.h
deleted file mode 100755
index 1d5ed804..00000000
--- a/tinyusb/hw/bsp/samd51/boards/pybadge/board.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PIN               23
-#define LED_STATE_ON          1
-
-// Button
-#define BUTTON_PIN            16 // D5
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_TX_PIN           (32 + 17)
-#define UART_RX_PIN           (32 + 16)
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/samd51/boards/pybadge/board.mk b/tinyusb/hw/bsp/samd51/boards/pybadge/board.mk
deleted file mode 100755
index a8a98a98..00000000
--- a/tinyusb/hw/bsp/samd51/boards/pybadge/board.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-CFLAGS += -D__SAMD51J19A__
-
-LD_FILE = $(BOARD_PATH)/$(BOARD).ld
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAMD51J19
-
-flash: flash-bossac
diff --git a/tinyusb/hw/bsp/samd51/boards/pybadge/pybadge.ld b/tinyusb/hw/bsp/samd51/boards/pybadge/pybadge.ld
deleted file mode 100755
index f1a021d7..00000000
--- a/tinyusb/hw/bsp/samd51/boards/pybadge/pybadge.ld
+++ /dev/null
@@ -1,166 +0,0 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD51G19A
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-SEARCH_DIR(.)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-  rom      (rx)  : ORIGIN = 0x00000000 + 16K, LENGTH = 0x00080000 - 16K
-  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
-  bkupram  (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
-  qspi     (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
-}
-
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
-
-ENTRY(Reset_Handler)
-
-/* Section Definitions */
-SECTIONS
-{
-    .text :
-    {
-        . = ALIGN(4);
-        _sfixed = .;
-        KEEP(*(.vectors .vectors.*))
-        *(.text .text.* .gnu.linkonce.t.*)
-        *(.glue_7t) *(.glue_7)
-        *(.rodata .rodata* .gnu.linkonce.r.*)
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-
-        /* Support C constructors, and C destructors in both user code
-           and the C library. This also provides support for C++ code. */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-
-        . = ALIGN(4);
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-
-        . = ALIGN(4);
-        KEEP(*(.fini))
-
-        . = ALIGN(4);
-        __fini_array_start = .;
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        __fini_array_end = .;
-
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-
-        . = ALIGN(4);
-        _efixed = .;            /* End of text section */
-    } > rom
-
-    /* .ARM.exidx is sorted, so has to go in its own output section.  */
-    PROVIDE_HIDDEN (__exidx_start = .);
-    .ARM.exidx :
-    {
-      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > rom
-    PROVIDE_HIDDEN (__exidx_end = .);
-
-    . = ALIGN(4);
-    _etext = .;
-
-    .relocate : AT (_etext)
-    {
-        . = ALIGN(4);
-        _srelocate = .;
-        *(.ramfunc .ramfunc.*);
-        *(.data .data.*);
-        . = ALIGN(4);
-        _erelocate = .;
-    } > ram
-
-    .bkupram (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sbkupram = .;
-        *(.bkupram .bkupram.*);
-        . = ALIGN(8);
-        _ebkupram = .;
-    } > bkupram
-
-    .qspi (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sqspi = .;
-        *(.qspi .qspi.*);
-        . = ALIGN(8);
-        _eqspi = .;
-    } > qspi
-
-    /* .bss section which is used for uninitialized data */
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        _sbss = . ;
-        _szero = .;
-        *(.bss .bss.*)
-        *(COMMON)
-        . = ALIGN(4);
-        _ebss = . ;
-        _ezero = .;
-        end = .;
-    } > ram
-
-    /* stack section */
-    .stack (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sstack = .;
-        . = . + STACK_SIZE;
-        . = ALIGN(8);
-        _estack = .;
-    } > ram
-
-    . = ALIGN(4);
-    _end = . ;
-}
diff --git a/tinyusb/hw/bsp/samd51/boards/pyportal/board.h b/tinyusb/hw/bsp/samd51/boards/pyportal/board.h
deleted file mode 100755
index 9e51ded3..00000000
--- a/tinyusb/hw/bsp/samd51/boards/pyportal/board.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PIN               (32+23)
-#define LED_STATE_ON          1
-
-// Button
-#define BUTTON_PIN            (32+22) // D2
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_TX_PIN           (32 + 13)
-#define UART_RX_PIN           (32 + 12)
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/samd51/boards/pyportal/board.mk b/tinyusb/hw/bsp/samd51/boards/pyportal/board.mk
deleted file mode 100755
index a8a98a98..00000000
--- a/tinyusb/hw/bsp/samd51/boards/pyportal/board.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-CFLAGS += -D__SAMD51J19A__
-
-LD_FILE = $(BOARD_PATH)/$(BOARD).ld
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAMD51J19
-
-flash: flash-bossac
diff --git a/tinyusb/hw/bsp/samd51/boards/pyportal/pyportal.ld b/tinyusb/hw/bsp/samd51/boards/pyportal/pyportal.ld
deleted file mode 100755
index f1a021d7..00000000
--- a/tinyusb/hw/bsp/samd51/boards/pyportal/pyportal.ld
+++ /dev/null
@@ -1,166 +0,0 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD51G19A
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-SEARCH_DIR(.)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-  rom      (rx)  : ORIGIN = 0x00000000 + 16K, LENGTH = 0x00080000 - 16K
-  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
-  bkupram  (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
-  qspi     (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
-}
-
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
-
-ENTRY(Reset_Handler)
-
-/* Section Definitions */
-SECTIONS
-{
-    .text :
-    {
-        . = ALIGN(4);
-        _sfixed = .;
-        KEEP(*(.vectors .vectors.*))
-        *(.text .text.* .gnu.linkonce.t.*)
-        *(.glue_7t) *(.glue_7)
-        *(.rodata .rodata* .gnu.linkonce.r.*)
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-
-        /* Support C constructors, and C destructors in both user code
-           and the C library. This also provides support for C++ code. */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-
-        . = ALIGN(4);
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-
-        . = ALIGN(4);
-        KEEP(*(.fini))
-
-        . = ALIGN(4);
-        __fini_array_start = .;
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        __fini_array_end = .;
-
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-
-        . = ALIGN(4);
-        _efixed = .;            /* End of text section */
-    } > rom
-
-    /* .ARM.exidx is sorted, so has to go in its own output section.  */
-    PROVIDE_HIDDEN (__exidx_start = .);
-    .ARM.exidx :
-    {
-      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > rom
-    PROVIDE_HIDDEN (__exidx_end = .);
-
-    . = ALIGN(4);
-    _etext = .;
-
-    .relocate : AT (_etext)
-    {
-        . = ALIGN(4);
-        _srelocate = .;
-        *(.ramfunc .ramfunc.*);
-        *(.data .data.*);
-        . = ALIGN(4);
-        _erelocate = .;
-    } > ram
-
-    .bkupram (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sbkupram = .;
-        *(.bkupram .bkupram.*);
-        . = ALIGN(8);
-        _ebkupram = .;
-    } > bkupram
-
-    .qspi (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sqspi = .;
-        *(.qspi .qspi.*);
-        . = ALIGN(8);
-        _eqspi = .;
-    } > qspi
-
-    /* .bss section which is used for uninitialized data */
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        _sbss = . ;
-        _szero = .;
-        *(.bss .bss.*)
-        *(COMMON)
-        . = ALIGN(4);
-        _ebss = . ;
-        _ezero = .;
-        end = .;
-    } > ram
-
-    /* stack section */
-    .stack (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sstack = .;
-        . = . + STACK_SIZE;
-        . = ALIGN(8);
-        _estack = .;
-    } > ram
-
-    . = ALIGN(4);
-    _end = . ;
-}
diff --git a/tinyusb/hw/bsp/samd51/family.c b/tinyusb/hw/bsp/samd51/family.c
deleted file mode 100755
index 020e638c..00000000
--- a/tinyusb/hw/bsp/samd51/family.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "sam.h"
-#include "bsp/board.h"
-#include "board.h"
-
-#include "hal/include/hal_gpio.h"
-#include "hal/include/hal_init.h"
-#include "hpl/gclk/hpl_gclk_base.h"
-#include "hpl_mclk_config.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_0_Handler (void)
-{
-  tud_int_handler(0);
-}
-
-void USB_1_Handler (void)
-{
-  tud_int_handler(0);
-}
-
-void USB_2_Handler (void)
-{
-  tud_int_handler(0);
-}
-
-void USB_3_Handler (void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-
-/* Referenced GCLKs, should be initialized firstly */
-#define _GCLK_INIT_1ST 0xFFFFFFFF
-
-/* Not referenced GCLKs, initialized last */
-#define _GCLK_INIT_LAST (~_GCLK_INIT_1ST)
-
-void board_init(void)
-{
-  // Clock init ( follow hpl_init.c )
-  hri_nvmctrl_set_CTRLA_RWS_bf(NVMCTRL, 0);
-
-  _osc32kctrl_init_sources();
-  _oscctrl_init_sources();
-  _mclk_init();
-#if _GCLK_INIT_1ST
-  _gclk_init_generators_by_fref(_GCLK_INIT_1ST);
-#endif
-  _oscctrl_init_referenced_generators();
-  _gclk_init_generators_by_fref(_GCLK_INIT_LAST);
-
-  // Update SystemCoreClock since it is hard coded with asf4 and not correct
-  // Init 1ms tick timer (samd SystemCoreClock may not correct)
-  SystemCoreClock = CONF_CPU_FREQUENCY;
-  SysTick_Config(CONF_CPU_FREQUENCY / 1000);
-
-  // Led init
-  gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
-  gpio_set_pin_level(LED_PIN, 0);
-
-  // Button init
-  gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
-  gpio_set_pin_pull_mode(BUTTON_PIN, GPIO_PULL_UP);
-
-#if CFG_TUSB_OS  == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-  NVIC_SetPriority(USB_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-  NVIC_SetPriority(USB_2_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-  NVIC_SetPriority(USB_3_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-#endif
-
-  /* USB Clock init
-   * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock
-   * for low speed and full speed operation. */
-  hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN);
-  hri_mclk_set_AHBMASK_USB_bit(MCLK);
-  hri_mclk_set_APBBMASK_USB_bit(MCLK);
-
-  // USB Pin Init
-  gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT);
-  gpio_set_pin_level(PIN_PA24, false);
-  gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF);
-  gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT);
-  gpio_set_pin_level(PIN_PA25, false);
-  gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF);
-
-  gpio_set_pin_function(PIN_PA24, PINMUX_PA24H_USB_DM);
-  gpio_set_pin_function(PIN_PA25, PINMUX_PA25H_USB_DP);
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  gpio_set_pin_level(LED_PIN, state);
-}
-
-uint32_t board_button_read(void)
-{
-  // button is active low
-  return gpio_get_pin_level(BUTTON_PIN) ? 0 : 1;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/tinyusb/hw/bsp/samd51/family.mk b/tinyusb/hw/bsp/samd51/family.mk
deleted file mode 100755
index f4e260fb..00000000
--- a/tinyusb/hw/bsp/samd51/family.mk
+++ /dev/null
@@ -1,49 +0,0 @@
-UF2_FAMILY_ID = 0x55114460
-DEPS_SUBMODULES += hw/mcu/microchip
-
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib -nostartfiles \
-  -DCFG_TUSB_MCU=OPT_MCU_SAMD51
-
-CFLAGS += -Wno-error=undef
-
-SRC_C += \
-	src/portable/microchip/samd/dcd_samd.c \
-	hw/mcu/microchip/samd51/gcc/gcc/startup_samd51.c \
-	hw/mcu/microchip/samd51/gcc/system_samd51.c \
-	hw/mcu/microchip/samd51/hpl/gclk/hpl_gclk.c \
-	hw/mcu/microchip/samd51/hpl/mclk/hpl_mclk.c \
-	hw/mcu/microchip/samd51/hpl/osc32kctrl/hpl_osc32kctrl.c \
-	hw/mcu/microchip/samd51/hpl/oscctrl/hpl_oscctrl.c \
-	hw/mcu/microchip/samd51/hal/src/hal_atomic.c
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/hw/mcu/microchip/samd51/ \
-	$(TOP)/hw/mcu/microchip/samd51/config \
-	$(TOP)/hw/mcu/microchip/samd51/include \
-	$(TOP)/hw/mcu/microchip/samd51/hal/include \
-	$(TOP)/hw/mcu/microchip/samd51/hal/utils/include \
-	$(TOP)/hw/mcu/microchip/samd51/hpl/port \
-	$(TOP)/hw/mcu/microchip/samd51/hri \
-	$(TOP)/hw/mcu/microchip/samd51/CMSIS/Include
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
-# flash using bossac at least version 1.8
-# can be found in arduino15/packages/arduino/tools/bossac/
-# Add it to your PATH or change BOSSAC variable to match your installation
-BOSSAC = bossac
-
-flash-bossac: $(BUILD)/$(PROJECT).bin
-	@:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyACM0)
-	$(BOSSAC) --port=$(SERIAL) -U -i --offset=0x4000 -e -w $^ -R
diff --git a/tinyusb/hw/bsp/same54xplainedpro/board.mk b/tinyusb/hw/bsp/same54xplainedpro/board.mk
deleted file mode 100755
index 16ac786d..00000000
--- a/tinyusb/hw/bsp/same54xplainedpro/board.mk
+++ /dev/null
@@ -1,46 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/microchip
-
-CONF_CPU_FREQUENCY ?= 48000000
-
-CFLAGS += \
-  -mthumb \
-  -mabi=aapcs \
-  -mlong-calls \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib -nostartfiles \
-  -D__SAME54P20A__ \
-  -DCONF_CPU_FREQUENCY=$(CONF_CPU_FREQUENCY) \
-  -DCFG_TUSB_MCU=OPT_MCU_SAME5X \
-  -DBOARD_NAME="\"Microchip SAM E54 Xplained Pro\""
-
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/same54p20a_flash.ld
-
-SRC_C += \
-  src/portable/microchip/samd/dcd_samd.c \
-  hw/mcu/microchip/same54/gcc/gcc/startup_same54.c \
-  hw/mcu/microchip/same54/gcc/system_same54.c \
-  hw/mcu/microchip/same54/hal/utils/src/utils_syscalls.c
-
-INC += \
-	$(TOP)/hw/mcu/microchip/same54/ \
-	$(TOP)/hw/mcu/microchip/same54/config \
-	$(TOP)/hw/mcu/microchip/same54/include \
-	$(TOP)/hw/mcu/microchip/same54/hal/include \
-	$(TOP)/hw/mcu/microchip/same54/hal/utils/include \
-	$(TOP)/hw/mcu/microchip/same54/hpl/port \
-	$(TOP)/hw/mcu/microchip/same54/hri \
-	$(TOP)/hw/mcu/microchip/same54/CMSIS/Include
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAME54P20
-
-# flash using edbg from https://github.com/ataradov/edbg
-flash: $(BUILD)/$(PROJECT).bin
-	edbg --verbose -t same54 -pv -f $<
diff --git a/tinyusb/hw/bsp/same54xplainedpro/same54p20a_flash.ld b/tinyusb/hw/bsp/same54xplainedpro/same54p20a_flash.ld
deleted file mode 100755
index 97072bfe..00000000
--- a/tinyusb/hw/bsp/same54xplainedpro/same54p20a_flash.ld
+++ /dev/null
@@ -1,163 +0,0 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAME54P20A
- *
- * Copyright (c) 2019 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-SEARCH_DIR(.)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00100000
-  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
-  bkupram  (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
-  qspi     (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
-}
-
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
-
-/* Section Definitions */
-SECTIONS
-{
-    .text :
-    {
-        . = ALIGN(4);
-        _sfixed = .;
-        KEEP(*(.vectors .vectors.*))
-        *(.text .text.* .gnu.linkonce.t.*)
-        *(.glue_7t) *(.glue_7)
-        *(.rodata .rodata* .gnu.linkonce.r.*)
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-
-        /* Support C constructors, and C destructors in both user code
-           and the C library. This also provides support for C++ code. */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-
-        . = ALIGN(4);
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-
-        . = ALIGN(4);
-        KEEP(*(.fini))
-
-        . = ALIGN(4);
-        __fini_array_start = .;
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        __fini_array_end = .;
-
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-
-        . = ALIGN(4);
-        _efixed = .;            /* End of text section */
-    } > rom
-
-    /* .ARM.exidx is sorted, so has to go in its own output section.  */
-    PROVIDE_HIDDEN (__exidx_start = .);
-    .ARM.exidx :
-    {
-      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > rom
-    PROVIDE_HIDDEN (__exidx_end = .);
-
-    . = ALIGN(4);
-    _etext = .;
-
-    .relocate : AT (_etext)
-    {
-        . = ALIGN(4);
-        _srelocate = .;
-        *(.ramfunc .ramfunc.*);
-        *(.data .data.*);
-        . = ALIGN(4);
-        _erelocate = .;
-    } > ram
-
-    .bkupram (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sbkupram = .;
-        *(.bkupram .bkupram.*);
-        . = ALIGN(8);
-        _ebkupram = .;
-    } > bkupram
-
-    .qspi (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sqspi = .;
-        *(.qspi .qspi.*);
-        . = ALIGN(8);
-        _eqspi = .;
-    } > qspi
-
-    /* .bss section which is used for uninitialized data */
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        _sbss = . ;
-        _szero = .;
-        *(.bss .bss.*)
-        *(COMMON)
-        . = ALIGN(4);
-        _ebss = . ;
-        _ezero = .;
-    } > ram
-
-    /* stack section */
-    .stack (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sstack = .;
-        . = . + STACK_SIZE;
-        . = ALIGN(8);
-        _estack = .;
-    } > ram
-
-    . = ALIGN(4);
-    _end = . ;
-}
diff --git a/tinyusb/hw/bsp/same54xplainedpro/same54p20a_sram.ld b/tinyusb/hw/bsp/same54xplainedpro/same54p20a_sram.ld
deleted file mode 100755
index 6219f4af..00000000
--- a/tinyusb/hw/bsp/same54xplainedpro/same54p20a_sram.ld
+++ /dev/null
@@ -1,162 +0,0 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal SRAM on the SAME54P20A
- *
- * Copyright (c) 2019 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-SEARCH_DIR(.)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
-  bkupram  (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
-  qspi     (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
-}
-
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
-
-/* Section Definitions */
-SECTIONS
-{
-    .text :
-    {
-        . = ALIGN(4);
-        _sfixed = .;
-        KEEP(*(.vectors .vectors.*))
-        *(.text .text.* .gnu.linkonce.t.*)
-        *(.glue_7t) *(.glue_7)
-        *(.rodata .rodata* .gnu.linkonce.r.*)
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-
-        /* Support C constructors, and C destructors in both user code
-           and the C library. This also provides support for C++ code. */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-
-        . = ALIGN(4);
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-
-        . = ALIGN(4);
-        KEEP(*(.fini))
-
-        . = ALIGN(4);
-        __fini_array_start = .;
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        __fini_array_end = .;
-
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-
-        . = ALIGN(4);
-        _efixed = .;            /* End of text section */
-    } > ram
-
-    /* .ARM.exidx is sorted, so has to go in its own output section.  */
-    PROVIDE_HIDDEN (__exidx_start = .);
-    .ARM.exidx :
-    {
-      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > ram
-    PROVIDE_HIDDEN (__exidx_end = .);
-
-    . = ALIGN(4);
-    _etext = .;
-
-    .relocate : AT (_etext)
-    {
-        . = ALIGN(4);
-        _srelocate = .;
-        *(.ramfunc .ramfunc.*);
-        *(.data .data.*);
-        . = ALIGN(4);
-        _erelocate = .;
-    } > ram
-
-    .bkupram (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sbkupram = .;
-        *(.bkupram .bkupram.*);
-        . = ALIGN(8);
-        _ebkupram = .;
-    } > bkupram
-
-    .qspi (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sqspi = .;
-        *(.qspi .qspi.*);
-        . = ALIGN(8);
-        _eqspi = .;
-    } > qspi
-
-    /* .bss section which is used for uninitialized data */
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        _sbss = . ;
-        _szero = .;
-        *(.bss .bss.*)
-        *(COMMON)
-        . = ALIGN(4);
-        _ebss = . ;
-        _ezero = .;
-    } > ram
-
-    /* stack section */
-    .stack (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sstack = .;
-        . = . + STACK_SIZE;
-        . = ALIGN(8);
-        _estack = .;
-    } > ram
-
-    . = ALIGN(4);
-    _end = . ;
-}
diff --git a/tinyusb/hw/bsp/same54xplainedpro/same54xplainedpro.c b/tinyusb/hw/bsp/same54xplainedpro/same54xplainedpro.c
deleted file mode 100755
index 4c38fc6e..00000000
--- a/tinyusb/hw/bsp/same54xplainedpro/same54xplainedpro.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021 Jean Gressmann <jean@0x42.de>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- */
-
-#include <sam.h>
-#include "bsp/board.h"
-
-#include <hal/include/hal_gpio.h>
-
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_0_Handler(void)
-{
-	tud_int_handler(0);
-}
-
-void USB_1_Handler(void)
-{
-	tud_int_handler(0);
-}
-
-void USB_2_Handler(void)
-{
-	tud_int_handler(0);
-}
-
-void USB_3_Handler(void)
-{
-	tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-#define LED_PIN PIN_PC18
-#define BUTTON_PIN PIN_PB31
-#define BOARD_SERCOM SERCOM2
-
-/** Initializes the clocks from the external 12 MHz crystal
- *
- * The goal of this setup is to preserve the second PLL
- * for the application code while still having a reasonable
- * 48 MHz clock for USB / UART.
- *
- * GCLK0:   CONF_CPU_FREQUENCY (default 120 MHz) from PLL0
- * GCLK1:   unused
- * GCLK2:   12 MHz from XOSC1
- * DFLL48M: closed loop from GLCK2
- * GCLK3:   48 MHz
- */
-static inline void init_clock_xtal(void)
-{
-	/* configure for a 12MHz crystal connected to XIN1/XOUT1 */
-	OSCCTRL->XOSCCTRL[1].reg =
-		OSCCTRL_XOSCCTRL_STARTUP(6) | // 1.953 ms
-		OSCCTRL_XOSCCTRL_RUNSTDBY |
-		OSCCTRL_XOSCCTRL_ENALC |
-		OSCCTRL_XOSCCTRL_IMULT(4) | OSCCTRL_XOSCCTRL_IPTAT(3) | // 8MHz to 16MHz
-		OSCCTRL_XOSCCTRL_XTALEN |
-		OSCCTRL_XOSCCTRL_ENABLE;
-	while(0 == OSCCTRL->STATUS.bit.XOSCRDY1);
-
-	OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(2) | OSCCTRL_DPLLCTRLB_REFCLK_XOSC1; /* 12MHz / 6 = 2Mhz, input = XOSC1 */
-	OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR((CONF_CPU_FREQUENCY / 1000000 / 2) - 1); /* multiply to get CONF_CPU_FREQUENCY (default = 120MHz) */
-	OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
-	while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL0 to be ready */
-
-	/* configure clock-generator 0 to use DPLL0 as source -> GCLK0 is used for the core */
-	GCLK->GENCTRL[0].reg =
-		GCLK_GENCTRL_DIV(0) |
-		GCLK_GENCTRL_RUNSTDBY |
-		GCLK_GENCTRL_GENEN |
-		GCLK_GENCTRL_SRC_DPLL0 |
-		GCLK_GENCTRL_IDC;
-	while(1 == GCLK->SYNCBUSY.bit.GENCTRL0); /* wait for the synchronization between clock domains to be complete */
-
-	// configure GCLK2 for 12MHz from XOSC1
-	GCLK->GENCTRL[2].reg =
-		GCLK_GENCTRL_DIV(0) |
-		GCLK_GENCTRL_RUNSTDBY |
-		GCLK_GENCTRL_GENEN |
-		GCLK_GENCTRL_SRC_XOSC1 |
-		GCLK_GENCTRL_IDC;
-	while(1 == GCLK->SYNCBUSY.bit.GENCTRL2); /* wait for the synchronization between clock domains to be complete */
-
-	 /* setup DFLL48M to use GLCK2 */
-	GCLK->PCHCTRL[OSCCTRL_GCLK_ID_DFLL48].reg = GCLK_PCHCTRL_GEN_GCLK2 | GCLK_PCHCTRL_CHEN;
-
-	OSCCTRL->DFLLCTRLA.reg = 0;
-	while(1 == OSCCTRL->DFLLSYNC.bit.ENABLE);
-
-	OSCCTRL->DFLLCTRLB.reg = OSCCTRL_DFLLCTRLB_MODE | OSCCTRL_DFLLCTRLB_WAITLOCK;
-	OSCCTRL->DFLLMUL.bit.MUL = 4; // 4 * 12MHz -> 48MHz
-
-	OSCCTRL->DFLLCTRLA.reg =
-		OSCCTRL_DFLLCTRLA_ENABLE |
-		OSCCTRL_DFLLCTRLA_RUNSTDBY;
-	while(1 == OSCCTRL->DFLLSYNC.bit.ENABLE);
-
-	// setup 48 MHz GCLK3 from DFLL48M
-	GCLK->GENCTRL[3].reg =
-		GCLK_GENCTRL_DIV(0) |
-		GCLK_GENCTRL_RUNSTDBY |
-		GCLK_GENCTRL_GENEN |
-		GCLK_GENCTRL_SRC_DFLL |
-		GCLK_GENCTRL_IDC;
-	while(1 == GCLK->SYNCBUSY.bit.GENCTRL3);
-}
-
-/* Initialize SERCOM2 for 115200 bps 8N1 using a 48 MHz clock */
-static inline void uart_init(void)
-{
-	gpio_set_pin_function(PIN_PB24, PINMUX_PB24D_SERCOM2_PAD1);
-	gpio_set_pin_function(PIN_PB25, PINMUX_PB25D_SERCOM2_PAD0);
-
-	MCLK->APBBMASK.bit.SERCOM2_ = 1;
-	GCLK->PCHCTRL[SERCOM2_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK0 | GCLK_PCHCTRL_CHEN;
-
-	BOARD_SERCOM->USART.CTRLA.bit.SWRST = 1; /* reset and disable SERCOM -> enable configuration */
-	while (BOARD_SERCOM->USART.SYNCBUSY.bit.SWRST);
-
-	BOARD_SERCOM->USART.CTRLA.reg  =
-		SERCOM_USART_CTRLA_SAMPR(0) | /* 0 = 16x / arithmetic baud rate, 1 = 16x / fractional baud rate */
-		SERCOM_USART_CTRLA_SAMPA(0) | /* 16x over sampling */
-		SERCOM_USART_CTRLA_FORM(0) | /* 0x0 USART frame, 0x1 USART frame with parity, ... */
-		SERCOM_USART_CTRLA_DORD | /* LSB first */
-		SERCOM_USART_CTRLA_MODE(1) | /* 0x0 USART with external clock, 0x1 USART with internal clock */
-		SERCOM_USART_CTRLA_RXPO(1) | /* SERCOM PAD[1] is used for data reception */
-		SERCOM_USART_CTRLA_TXPO(0); /* SERCOM PAD[0] is used for data transmission */
-
-	BOARD_SERCOM->USART.CTRLB.reg = /* RXEM = 0 -> receiver disabled, LINCMD = 0 -> normal USART transmission, SFDE = 0 -> start-of-frame detection disabled, SBMODE = 0 -> one stop bit, CHSIZE = 0 -> 8 bits */
-		SERCOM_USART_CTRLB_TXEN | /* transmitter enabled */
-		SERCOM_USART_CTRLB_RXEN; /* receiver enabled */
-	// BOARD_SERCOM->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(0) | SERCOM_USART_BAUD_FRAC_BAUD(26); /* 48000000/(16*115200) = 26.041666667 */
-	BOARD_SERCOM->USART.BAUD.reg = SERCOM_USART_BAUD_BAUD(63019); /* 65536*(1−16*115200/48000000) */
-
-	BOARD_SERCOM->USART.CTRLA.bit.ENABLE = 1; /* activate SERCOM */
-	while (BOARD_SERCOM->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */
-}
-
-static inline void uart_send_buffer(uint8_t const *text, size_t len)
-{
-	for (size_t i = 0; i < len; ++i) {
-		BOARD_SERCOM->USART.DATA.reg = text[i];
-		while((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) == 0);
-	}
-}
-
-static inline void uart_send_str(const char* text)
-{
-	while (*text) {
-		BOARD_SERCOM->USART.DATA.reg = *text++;
-		while((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) == 0);
-	}
-}
-
-
-void board_init(void)
-{
-	// Uncomment this line and change the GCLK for UART/USB to run off the XTAL.
-	// init_clock_xtal();
-
-	SystemCoreClock = CONF_CPU_FREQUENCY;
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-	SysTick_Config(CONF_CPU_FREQUENCY / 1000);
-#endif
-
-	uart_init();
-
-#if CFG_TUSB_DEBUG >= 2
-	uart_send_str(BOARD_NAME " UART initialized\n");
-	tu_printf(BOARD_NAME " reset cause %#02x\n", RSTC->RCAUSE.reg);
-#endif
-
-	// LED0 init
-	gpio_set_pin_function(LED_PIN, GPIO_PIN_FUNCTION_OFF);
-	gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
-	board_led_write(0);
-
-#if CFG_TUSB_DEBUG >= 2
-	uart_send_str(BOARD_NAME " LED pin configured\n");
-#endif
-
-	// BTN0 init
-	gpio_set_pin_function(BUTTON_PIN, GPIO_PIN_FUNCTION_OFF);
-	gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
-	gpio_set_pin_pull_mode(BUTTON_PIN, GPIO_PULL_UP);
-
-#if CFG_TUSB_DEBUG >= 2
-	uart_send_str(BOARD_NAME " Button pin configured\n");
-#endif
-
-#if CFG_TUSB_OS == OPT_OS_FREERTOS
-	// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-	NVIC_SetPriority(USB_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-	NVIC_SetPriority(USB_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-	NVIC_SetPriority(USB_2_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-	NVIC_SetPriority(USB_3_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-#endif
-
-
-#if TUSB_OPT_DEVICE_ENABLED
-#if CFG_TUSB_DEBUG >= 2
-	uart_send_str(BOARD_NAME " USB device enabled\n");
-#endif
-
-	/* USB clock init
-	 * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock
-	 * for low speed and full speed operation.
-	 */
-	hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK0_Val | GCLK_PCHCTRL_CHEN);
-	hri_mclk_set_AHBMASK_USB_bit(MCLK);
-	hri_mclk_set_APBBMASK_USB_bit(MCLK);
-
-	// USB pin init
-	gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT);
-	gpio_set_pin_level(PIN_PA24, false);
-	gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF);
-	gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT);
-	gpio_set_pin_level(PIN_PA25, false);
-	gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF);
-
-	gpio_set_pin_function(PIN_PA24, PINMUX_PA24H_USB_DM);
-	gpio_set_pin_function(PIN_PA25, PINMUX_PA25H_USB_DP);
-
-
-#if CFG_TUSB_DEBUG >= 2
-	uart_send_str(BOARD_NAME " USB device configured\n");
-#endif
-#endif
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-	gpio_set_pin_level(LED_PIN, !state);
-}
-
-uint32_t board_button_read(void)
-{
-	return (PORT->Group[1].IN.reg & 0x80000000) != 0x80000000;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-	if (len < 0) {
-		uart_send_str(buf);
-	} else {
-		uart_send_buffer(buf, len);
-	}
-	return len;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-
-void SysTick_Handler(void)
-{
-	system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-	return system_ticks;
-}
-#endif
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
-}
diff --git a/tinyusb/hw/bsp/same70_xplained/board.mk b/tinyusb/hw/bsp/same70_xplained/board.mk
deleted file mode 100755
index c9bc0cea..00000000
--- a/tinyusb/hw/bsp/same70_xplained/board.mk
+++ /dev/null
@@ -1,56 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/microchip
-
-CFLAGS += \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m7 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib -nostartfiles \
-  -D__SAME70Q21B__ \
-  -DCFG_TUSB_MCU=OPT_MCU_SAMX7X
-
-# suppress following warnings from mcu driver
-CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align
-
-ASF_DIR = hw/mcu/microchip/same70
-
-# All source paths should be relative to the top level.
-LD_FILE = $(ASF_DIR)/same70b/gcc/gcc/same70q21b_flash.ld
-
-SRC_C += \
-	src/portable/microchip/samx7x/dcd_samx7x.c \
-	$(ASF_DIR)/same70b/gcc/gcc/startup_same70q21b.c \
-	$(ASF_DIR)/same70b/gcc/system_same70q21b.c \
-	$(ASF_DIR)/hpl/core/hpl_init.c \
-	$(ASF_DIR)/hpl/usart/hpl_usart.c \
-	$(ASF_DIR)/hpl/pmc/hpl_pmc.c \
-	$(ASF_DIR)/hal/src/hal_usart_async.c \
-	$(ASF_DIR)/hal/src/hal_io.c \
-	$(ASF_DIR)/hal/src/hal_atomic.c \
-	$(ASF_DIR)/hal/utils/src/utils_ringbuffer.c
-
-INC += \
-  $(TOP)/hw/bsp/$(BOARD) \
-	$(TOP)/$(ASF_DIR) \
-	$(TOP)/$(ASF_DIR)/config \
-	$(TOP)/$(ASF_DIR)/same70b/include \
-	$(TOP)/$(ASF_DIR)/hal/include \
-	$(TOP)/$(ASF_DIR)/hal/utils/include \
-	$(TOP)/$(ASF_DIR)/hpl/core \
-	$(TOP)/$(ASF_DIR)/hpl/pio \
-	$(TOP)/$(ASF_DIR)/hpl/pmc \
-	$(TOP)/$(ASF_DIR)/hri \
-	$(TOP)/$(ASF_DIR)/CMSIS/Core/Include
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM7
-
-# For flash-jlink target
-JLINK_DEVICE = SAME70Q21B
-
-# flash using edbg from https://github.com/ataradov/edbg
-# Note: SAME70's GPNVM1 must be set to 1 to boot from flash with
-# 	edbg -t same70 -F w0,1,1
-flash: $(BUILD)/$(PROJECT).bin
-	edbg --verbose -t same70 -pv -f $< 
diff --git a/tinyusb/hw/bsp/same70_xplained/hpl_pmc_config.h b/tinyusb/hw/bsp/same70_xplained/hpl_pmc_config.h
deleted file mode 100755
index 387aaa5d..00000000
--- a/tinyusb/hw/bsp/same70_xplained/hpl_pmc_config.h
+++ /dev/null
@@ -1,1053 +0,0 @@
-/* Auto-generated config file hpl_pmc_config.h */
-#ifndef HPL_PMC_CONFIG_H
-#define HPL_PMC_CONFIG_H
-
-// <<< Use Configuration Wizard in Context Menu >>>
-
-#include <peripheral_clk_config.h>
-
-#define CLK_SRC_OPTION_OSC32K 0
-#define CLK_SRC_OPTION_XOSC32K 1
-#define CLK_SRC_OPTION_OSC12M 2
-#define CLK_SRC_OPTION_XOSC20M 3
-
-#define CLK_SRC_OPTION_SLCK 0
-#define CLK_SRC_OPTION_MAINCK 1
-#define CLK_SRC_OPTION_PLLACK 2
-#define CLK_SRC_OPTION_UPLLCKDIV 3
-#define CLK_SRC_OPTION_MCK 4
-
-#define CLK_SRC_OPTION_UPLLCK 3
-
-#define CONF_RC_4M 0
-#define CONF_RC_8M 1
-#define CONF_RC_12M 2
-
-#define CONF_XOSC32K_NO_BYPASS 0
-#define CONF_XOSC32K_BYPASS 1
-
-#define CONF_XOSC20M_NO_BYPASS 0
-#define CONF_XOSC20M_BYPASS 1
-
-// <e> Clock_SLCK configuration
-// <i> Indicates whether SLCK configuration is enabled or not
-// <id> enable_clk_gen_slck
-#ifndef CONF_CLK_SLCK_CONFIG
-#define CONF_CLK_SLCK_CONFIG 1
-#endif
-
-//<h> Clock Generator
-// <y> clock generator SLCK source
-
-// <CLK_SRC_OPTION_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K)
-
-// <CLK_SRC_OPTION_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
-
-// <i> This defines the clock source for SLCK
-// <id> clk_gen_slck_oscillator
-#ifndef CONF_CLK_GEN_SLCK_SRC
-#define CONF_CLK_GEN_SLCK_SRC CLK_SRC_OPTION_OSC32K
-#endif
-
-// <q> Enable Clock_SLCK
-// <i> Indicates whether SLCK is enabled or disable
-// <id> clk_gen_slck_arch_enable
-#ifndef CONF_CLK_SLCK_ENABLE
-#define CONF_CLK_SLCK_ENABLE 1
-#endif
-
-// </h>
-
-// <h>
-
-// </h>
-// </e>// <e> Clock_MAINCK configuration
-// <i> Indicates whether MAINCK configuration is enabled or not
-// <id> enable_clk_gen_mainck
-#ifndef CONF_CLK_MAINCK_CONFIG
-#define CONF_CLK_MAINCK_CONFIG 1
-#endif
-
-//<h> Clock Generator
-// <y> clock generator MAINCK source
-
-// <CLK_SRC_OPTION_OSC12M"> Embedded 4/8/12MHz RC Oscillator (OSC12M)
-
-// <CLK_SRC_OPTION_XOSC20M"> External 3-20MHz Oscillator (XOSC20M)
-
-// <i> This defines the clock source for MAINCK
-// <id> clk_gen_mainck_oscillator
-#ifndef CONF_CLK_GEN_MAINCK_SRC
-#define CONF_CLK_GEN_MAINCK_SRC CLK_SRC_OPTION_XOSC20M
-#endif
-
-// <q> Enable Clock_MAINCK
-// <i> Indicates whether MAINCK is enabled or disable
-// <id> clk_gen_mainck_arch_enable
-#ifndef CONF_CLK_MAINCK_ENABLE
-#define CONF_CLK_MAINCK_ENABLE 1
-#endif
-
-// <q> Enable Main Clock Failure Detection
-// <i> Indicates whether Main Clock Failure Detection is enabled or disable.
-// <i> The 4/8/12 MHz RC oscillator must be selected as the source of MAINCK.
-// <id> clk_gen_cfden_enable
-#ifndef CONF_CLK_CFDEN_ENABLE
-#define CONF_CLK_CFDEN_ENABLE 0
-#endif
-
-// </h>
-
-// <h>
-
-// </h>
-// </e>// <e> Clock_MCKR configuration
-// <i> Indicates whether MCKR configuration is enabled or not
-// <id> enable_clk_gen_mckr
-#ifndef CONF_CLK_MCKR_CONFIG
-#define CONF_CLK_MCKR_CONFIG 1
-#endif
-
-//<h> Clock Generator
-// <y> clock generator MCKR source
-
-// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
-
-// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
-
-// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
-
-// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2)
-
-// <i> This defines the clock source for MCKR
-// <id> clk_gen_mckr_oscillator
-#ifndef CONF_CLK_GEN_MCKR_SRC
-#define CONF_CLK_GEN_MCKR_SRC CLK_SRC_OPTION_PLLACK
-#endif
-
-// <q> Enable Clock_MCKR
-// <i> Indicates whether MCKR is enabled or disable
-// <id> clk_gen_mckr_arch_enable
-#ifndef CONF_CLK_MCKR_ENABLE
-#define CONF_CLK_MCKR_ENABLE 1
-#endif
-
-// </h>
-
-// <h>
-
-// <o> Master Clock Prescaler
-// <0=> 1
-// <1=> 2
-// <2=> 4
-// <3=> 8
-// <4=> 16
-// <5=> 32
-// <6=> 64
-// <7=> 3
-// <i> Select the clock prescaler.
-// <id> mckr_presc
-#ifndef CONF_MCKR_PRESC
-#define CONF_MCKR_PRESC 0
-#endif
-
-// </h>
-// </e>// <e> Clock_MCK configuration
-// <i> Indicates whether MCK configuration is enabled or not
-// <id> enable_clk_gen_mck
-#ifndef CONF_CLK_MCK_CONFIG
-#define CONF_CLK_MCK_CONFIG 1
-#endif
-
-//<h> Clock Generator
-// <y> clock generator MCK source
-
-// <CLK_SRC_OPTION_MCKR"> Master Clock Controller (PMC_MCKR)
-
-// <i> This defines the clock source for MCK
-// <id> clk_gen_mck_oscillator
-#ifndef CONF_CLK_GEN_MCK_SRC
-#define CONF_CLK_GEN_MCK_SRC CLK_SRC_OPTION_MCKR
-#endif
-
-// </h>
-
-// <h>
-
-//<o> Master Clock Controller Divider MCK divider
-// <0=> 1
-// <1=> 2
-// <3=> 3
-// <2=> 4
-// <i> Select the master clock divider.
-// <id> mck_div
-#ifndef CONF_MCK_DIV
-#define CONF_MCK_DIV 1
-#endif
-
-// </h>
-// </e>// <e> Clock_SYSTICK configuration
-// <i> Indicates whether SYSTICK configuration is enabled or not
-// <id> enable_clk_gen_systick
-#ifndef CONF_CLK_SYSTICK_CONFIG
-#define CONF_CLK_SYSTICK_CONFIG 1
-#endif
-
-//<h> Clock Generator
-// <y> clock generator SYSTICK source
-
-// <CLK_SRC_OPTION_MCKR"> Master Clock Controller (PMC_MCKR)
-
-// <i> This defines the clock source for SYSTICK
-// <id> clk_gen_systick_oscillator
-#ifndef CONF_CLK_GEN_SYSTICK_SRC
-#define CONF_CLK_GEN_SYSTICK_SRC CLK_SRC_OPTION_MCKR
-#endif
-
-// </h>
-
-// <h>
-
-// <o> Systick clock divider
-// <8=> 8
-// <i> Select systick clock divider
-// <id> systick_clock_div
-#ifndef CONF_SYSTICK_DIV
-#define CONF_SYSTICK_DIV 8
-#endif
-
-// </h>
-// </e>// <e> Clock_FCLK configuration
-// <i> Indicates whether FCLK configuration is enabled or not
-// <id> enable_clk_gen_fclk
-#ifndef CONF_CLK_FCLK_CONFIG
-#define CONF_CLK_FCLK_CONFIG 1
-#endif
-
-//<h> Clock Generator
-// <y> clock generator FCLK source
-
-// <CLK_SRC_OPTION_MCKR"> Master Clock Controller (PMC_MCKR)
-
-// <i> This defines the clock source for FCLK
-// <id> clk_gen_fclk_oscillator
-#ifndef CONF_CLK_GEN_FCLK_SRC
-#define CONF_CLK_GEN_FCLK_SRC CLK_SRC_OPTION_MCKR
-#endif
-
-// </h>
-
-// <h>
-
-// </h>
-// </e>// <e> Clock_GCLK0 configuration
-// <i> Indicates whether GCLK0 configuration is enabled or not
-// <id> enable_clk_gen_gclk0
-#ifndef CONF_CLK_GCLK0_CONFIG
-#define CONF_CLK_GCLK0_CONFIG 1
-#endif
-
-//<h> Clock Generator
-// <y> clock generator GCLK0 source
-
-// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
-
-// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
-
-// <CLK_SRC_OPTION_UPLLCK"> USB 480M Clock (UPLLCK)
-
-// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
-
-// <CLK_SRC_OPTION_MCK"> Master Clock (MCK)
-
-// <i> This defines the clock source for GCLK0
-// <id> clk_gen_gclk0_oscillator
-#ifndef CONF_CLK_GEN_GCLK0_SRC
-#define CONF_CLK_GEN_GCLK0_SRC CLK_SRC_OPTION_MCK
-#endif
-
-// <q> Enable Clock_GCLK0
-// <i> Indicates whether GCLK0 is enabled or disable
-// <id> clk_gen_gclk0_arch_enable
-#ifndef CONF_CLK_GCLK0_ENABLE
-#define CONF_CLK_GCLK0_ENABLE 1
-#endif
-
-// </h>
-
-// <h>
-// <q> Enable GCLK0 GCLKEN
-// <i> Indicates whether GCLK0 GCLKEN is enabled or disable
-// <id> gclk0_gclken_enable
-#ifndef CONF_GCLK0_GCLKEN_ENABLE
-#define CONF_GCLK0_GCLKEN_ENABLE 0
-#endif
-
-// <o> Generic Clock GCLK0 divider <1-256>
-// <i> Select the clock divider (divider = GCLKDIV + 1).
-// <id> gclk0_div
-#ifndef CONF_GCLK0_DIV
-#define CONF_GCLK0_DIV 2
-#endif
-
-// </h>
-// </e>// <e> Clock_GCLK1 configuration
-// <i> Indicates whether GCLK1 configuration is enabled or not
-// <id> enable_clk_gen_gclk1
-#ifndef CONF_CLK_GCLK1_CONFIG
-#define CONF_CLK_GCLK1_CONFIG 1
-#endif
-
-//<h> Clock Generator
-// <y> clock generator GCLK1 source
-
-// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
-
-// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
-
-// <CLK_SRC_OPTION_UPLLCK"> USB 480M Clock (UPLLCK)
-
-// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
-
-// <CLK_SRC_OPTION_MCK"> Master Clock (MCK)
-
-// <i> This defines the clock source for GCLK1
-// <id> clk_gen_gclk1_oscillator
-#ifndef CONF_CLK_GEN_GCLK1_SRC
-#define CONF_CLK_GEN_GCLK1_SRC CLK_SRC_OPTION_PLLACK
-#endif
-
-// <q> Enable Clock_GCLK1
-// <i> Indicates whether GCLK1 is enabled or disable
-// <id> clk_gen_gclk1_arch_enable
-#ifndef CONF_CLK_GCLK1_ENABLE
-#define CONF_CLK_GCLK1_ENABLE 1
-#endif
-
-// </h>
-
-// <h>
-// <q> Enable GCLK1 GCLKEN
-// <i> Indicates whether GCLK1 GCLKEN is enabled or disable
-// <id> gclk1_gclken_enable
-#ifndef CONF_GCLK1_GCLKEN_ENABLE
-#define CONF_GCLK1_GCLKEN_ENABLE 0
-#endif
-
-// <o> Generic Clock GCLK1 divider <1-256>
-// <i> Select the clock divider (divider = GCLKDIV + 1).
-// <id> gclk1_div
-#ifndef CONF_GCLK1_DIV
-#define CONF_GCLK1_DIV 3
-#endif
-
-// </h>
-// </e>// <e> Clock_PCK0 configuration
-// <i> Indicates whether PCK0 configuration is enabled or not
-// <id> enable_clk_gen_pck0
-#ifndef CONF_CLK_PCK0_CONFIG
-#define CONF_CLK_PCK0_CONFIG 1
-#endif
-
-//<h> Clock Generator
-// <y> clock generator PCK0 source
-
-// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
-
-// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
-
-// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2)
-
-// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
-
-// <CLK_SRC_OPTION_MCK"> Master Clock (MCK)
-
-// <i> This defines the clock source for PCK0
-// <id> clk_gen_pck0_oscillator
-#ifndef CONF_CLK_GEN_PCK0_SRC
-#define CONF_CLK_GEN_PCK0_SRC CLK_SRC_OPTION_MAINCK
-#endif
-
-// <q> Enable Clock_PCK0
-// <i> Indicates whether PCK0 is enabled or disable
-// <id> clk_gen_pck0_arch_enable
-#ifndef CONF_CLK_PCK0_ENABLE
-#define CONF_CLK_PCK0_ENABLE 0
-#endif
-
-// </h>
-
-// <h>
-
-// <o> Programmable Clock Controller Prescaler <1-256>
-// <i> Select the clock prescaler (prescaler = PRESC + 1).
-// <id> pck0_presc
-#ifndef CONF_PCK0_PRESC
-#define CONF_PCK0_PRESC 1
-#endif
-
-// </h>
-// </e>// <e> Clock_PCK1 configuration
-// <i> Indicates whether PCK1 configuration is enabled or not
-// <id> enable_clk_gen_pck1
-#ifndef CONF_CLK_PCK1_CONFIG
-#define CONF_CLK_PCK1_CONFIG 1
-#endif
-
-//<h> Clock Generator
-// <y> clock generator PCK1 source
-
-// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
-
-// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
-
-// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2)
-
-// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
-
-// <CLK_SRC_OPTION_MCK"> Master Clock (MCK)
-
-// <i> This defines the clock source for PCK1
-// <id> clk_gen_pck1_oscillator
-#ifndef CONF_CLK_GEN_PCK1_SRC
-#define CONF_CLK_GEN_PCK1_SRC CLK_SRC_OPTION_MAINCK
-#endif
-
-// <q> Enable Clock_PCK1
-// <i> Indicates whether PCK1 is enabled or disable
-// <id> clk_gen_pck1_arch_enable
-#ifndef CONF_CLK_PCK1_ENABLE
-#define CONF_CLK_PCK1_ENABLE 0
-#endif
-
-// </h>
-
-// <h>
-
-// <o> Programmable Clock Controller Prescaler <1-256>
-// <i> Select the clock prescaler (prescaler = PRESC + 1).
-// <id> pck1_presc
-#ifndef CONF_PCK1_PRESC
-#define CONF_PCK1_PRESC 2
-#endif
-
-// </h>
-// </e>// <e> Clock_PCK2 configuration
-// <i> Indicates whether PCK2 configuration is enabled or not
-// <id> enable_clk_gen_pck2
-#ifndef CONF_CLK_PCK2_CONFIG
-#define CONF_CLK_PCK2_CONFIG 1
-#endif
-
-//<h> Clock Generator
-// <y> clock generator PCK2 source
-
-// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
-
-// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
-
-// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2)
-
-// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
-
-// <CLK_SRC_OPTION_MCK"> Master Clock (MCK)
-
-// <i> This defines the clock source for PCK2
-// <id> clk_gen_pck2_oscillator
-#ifndef CONF_CLK_GEN_PCK2_SRC
-#define CONF_CLK_GEN_PCK2_SRC CLK_SRC_OPTION_MAINCK
-#endif
-
-// <q> Enable Clock_PCK2
-// <i> Indicates whether PCK2 is enabled or disable
-// <id> clk_gen_pck2_arch_enable
-#ifndef CONF_CLK_PCK2_ENABLE
-#define CONF_CLK_PCK2_ENABLE 0
-#endif
-
-// </h>
-
-// <h>
-
-// <o> Programmable Clock Controller Prescaler <1-256>
-// <i> Select the clock prescaler (prescaler = PRESC + 1).
-// <id> pck2_presc
-#ifndef CONF_PCK2_PRESC
-#define CONF_PCK2_PRESC 3
-#endif
-
-// </h>
-// </e>// <e> Clock_PCK3 configuration
-// <i> Indicates whether PCK3 configuration is enabled or not
-// <id> enable_clk_gen_pck3
-#ifndef CONF_CLK_PCK3_CONFIG
-#define CONF_CLK_PCK3_CONFIG 1
-#endif
-
-//<h> Clock Generator
-// <y> clock generator PCK3 source
-
-// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
-
-// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
-
-// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2)
-
-// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
-
-// <CLK_SRC_OPTION_MCK"> Master Clock (MCK)
-
-// <i> This defines the clock source for PCK3
-// <id> clk_gen_pck3_oscillator
-#ifndef CONF_CLK_GEN_PCK3_SRC
-#define CONF_CLK_GEN_PCK3_SRC CLK_SRC_OPTION_MAINCK
-#endif
-
-// <q> Enable Clock_PCK3
-// <i> Indicates whether PCK3 is enabled or disable
-// <id> clk_gen_pck3_arch_enable
-#ifndef CONF_CLK_PCK3_ENABLE
-#define CONF_CLK_PCK3_ENABLE 0
-#endif
-
-// </h>
-
-// <h>
-
-// <o> Programmable Clock Controller Prescaler <1-256>
-// <i> Select the clock prescaler (prescaler = PRESC + 1).
-// <id> pck3_presc
-#ifndef CONF_PCK3_PRESC
-#define CONF_PCK3_PRESC 4
-#endif
-
-// </h>
-// </e>// <e> Clock_PCK4 configuration
-// <i> Indicates whether PCK4 configuration is enabled or not
-// <id> enable_clk_gen_pck4
-#ifndef CONF_CLK_PCK4_CONFIG
-#define CONF_CLK_PCK4_CONFIG 1
-#endif
-
-//<h> Clock Generator
-// <y> clock generator PCK4 source
-
-// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
-
-// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
-
-// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2)
-
-// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
-
-// <CLK_SRC_OPTION_MCK"> Master Clock (MCK)
-
-// <i> This defines the clock source for PCK4
-// <id> clk_gen_pck4_oscillator
-#ifndef CONF_CLK_GEN_PCK4_SRC
-#define CONF_CLK_GEN_PCK4_SRC CLK_SRC_OPTION_MAINCK
-#endif
-
-// <q> Enable Clock_PCK4
-// <i> Indicates whether PCK4 is enabled or disable
-// <id> clk_gen_pck4_arch_enable
-#ifndef CONF_CLK_PCK4_ENABLE
-#define CONF_CLK_PCK4_ENABLE 0
-#endif
-
-// </h>
-
-// <h>
-
-// <o> Programmable Clock Controller Prescaler <1-256>
-// <i> Select the clock prescaler (prescaler = PRESC + 1).
-// <id> pck4_presc
-#ifndef CONF_PCK4_PRESC
-#define CONF_PCK4_PRESC 5
-#endif
-
-// </h>
-// </e>// <e> Clock_PCK5 configuration
-// <i> Indicates whether PCK5 configuration is enabled or not
-// <id> enable_clk_gen_pck5
-#ifndef CONF_CLK_PCK5_CONFIG
-#define CONF_CLK_PCK5_CONFIG 1
-#endif
-
-//<h> Clock Generator
-// <y> clock generator PCK5 source
-
-// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
-
-// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
-
-// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2)
-
-// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
-
-// <CLK_SRC_OPTION_MCK"> Master Clock (MCK)
-
-// <i> This defines the clock source for PCK5
-// <id> clk_gen_pck5_oscillator
-#ifndef CONF_CLK_GEN_PCK5_SRC
-#define CONF_CLK_GEN_PCK5_SRC CLK_SRC_OPTION_MAINCK
-#endif
-
-// <q> Enable Clock_PCK5
-// <i> Indicates whether PCK5 is enabled or disable
-// <id> clk_gen_pck5_arch_enable
-#ifndef CONF_CLK_PCK5_ENABLE
-#define CONF_CLK_PCK5_ENABLE 0
-#endif
-
-// </h>
-
-// <h>
-
-// <o> Programmable Clock Controller Prescaler <1-256>
-// <i> Select the clock prescaler (prescaler = PRESC + 1).
-// <id> pck5_presc
-#ifndef CONF_PCK5_PRESC
-#define CONF_PCK5_PRESC 6
-#endif
-
-// </h>
-// </e>// <e> Clock_PCK6 configuration
-// <i> Indicates whether PCK6 configuration is enabled or not
-// <id> enable_clk_gen_pck6
-#ifndef CONF_CLK_PCK6_CONFIG
-#define CONF_CLK_PCK6_CONFIG 1
-#endif
-
-//<h> Clock Generator
-// <y> clock generator PCK6 source
-
-// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
-
-// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
-
-// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2)
-
-// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
-
-// <CLK_SRC_OPTION_MCK"> Master Clock (MCK)
-
-// <i> This defines the clock source for PCK6
-// <id> clk_gen_pck6_oscillator
-#ifndef CONF_CLK_GEN_PCK6_SRC
-#define CONF_CLK_GEN_PCK6_SRC CLK_SRC_OPTION_MAINCK
-#endif
-
-// <q> Enable Clock_PCK6
-// <i> Indicates whether PCK6 is enabled or disable
-// <id> clk_gen_pck6_arch_enable
-#ifndef CONF_CLK_PCK6_ENABLE
-#define CONF_CLK_PCK6_ENABLE 0
-#endif
-
-// </h>
-
-// <h>
-
-// <o> Programmable Clock Controller Prescaler <1-256>
-// <i> Select the clock prescaler (prescaler = PRESC + 1).
-// <id> pck6_presc
-#ifndef CONF_PCK6_PRESC
-#define CONF_PCK6_PRESC 7
-#endif
-
-// </h>
-// </e>// <e> Clock_USB_480M configuration
-// <i> Indicates whether USB_480M configuration is enabled or not
-// <id> enable_clk_gen_usb_480m
-#ifndef CONF_CLK_USB_480M_CONFIG
-#define CONF_CLK_USB_480M_CONFIG 1
-#endif
-
-//<h> Clock Generator
-// <y> clock generator USB_480M source
-
-// <CLK_SRC_OPTION_UPLLCK"> USB 480M Clock (UPLLCK)
-
-// <i> This defines the clock source for USB_480M
-// <id> clk_gen_usb_480m_oscillator
-#ifndef CONF_CLK_GEN_USB_480M_SRC
-#define CONF_CLK_GEN_USB_480M_SRC CLK_SRC_OPTION_UPLLCK
-#endif
-
-// </h>
-
-// <h>
-
-// </h>
-// </e>// <e> Clock_USB_48M configuration
-// <i> Indicates whether USB_48M configuration is enabled or not
-// <id> enable_clk_gen_usb_48m
-#ifndef CONF_CLK_USB_48M_CONFIG
-#define CONF_CLK_USB_48M_CONFIG 1
-#endif
-
-//<h> Clock Generator
-// <y> clock generator USB_48M source
-
-// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
-
-// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2)
-
-// <i> This defines the clock source for USB_48M
-// <id> clk_gen_usb_48m_oscillator
-#ifndef CONF_CLK_GEN_USB_48M_SRC
-#define CONF_CLK_GEN_USB_48M_SRC CLK_SRC_OPTION_UPLLCKDIV
-#endif
-
-// <q> Enable Clock_USB_48M
-// <i> Indicates whether USB_48M is enabled or disable
-// <id> clk_gen_usb_48m_arch_enable
-#ifndef CONF_CLK_USB_48M_ENABLE
-#define CONF_CLK_USB_48M_ENABLE 1
-#endif
-
-// </h>
-
-// <h>
-
-// <o> USB Clock Controller Divider <1-16>
-// <i> Select the USB clock divider (divider = USBDIV + 1).
-// <id> usb_48m_div
-#ifndef CONF_USB_48M_DIV
-#define CONF_USB_48M_DIV 5
-#endif
-
-// </h>
-// </e>// <e> Clock_SLCK2 configuration
-// <i> Indicates whether SLCK2 configuration is enabled or not
-// <id> enable_clk_gen_slck2
-#ifndef CONF_CLK_SLCK2_CONFIG
-#define CONF_CLK_SLCK2_CONFIG 1
-#endif
-
-//<h> Clock Generator
-// <y> clock generator SLCK2 source
-
-// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
-
-// <i> This defines the clock source for SLCK2
-// <id> clk_gen_slck2_oscillator
-#ifndef CONF_CLK_GEN_SLCK2_SRC
-#define CONF_CLK_GEN_SLCK2_SRC CLK_SRC_OPTION_SLCK
-#endif
-
-// </h>
-
-// <h>
-
-// </h>
-// </e>
-
-// <e> System Configuration
-// <i> Indicates whether configuration for system is enabled or not
-// <id> enable_hclk_clock
-#ifndef CONF_SYSTEM_CONFIG
-#define CONF_SYSTEM_CONFIG 1
-#endif
-
-// <h> Processor Clock Settings
-// <y> Processor Clock source
-// <MCKR"> Master Clock Controller (PMC_MCKR)
-// <i> This defines the clock source for the HCLK (Processor clock)
-// <id> hclk_clock_source
-#ifndef CONF_HCLK_SRC
-#define CONF_HCLK_SRC MCKR
-#endif
-
-// <o> Flash Wait State
-// <0=> 1 cycle
-// <1=> 2 cycles
-// <2=> 3 cycles
-// <3=> 4 cycles
-// <4=> 5 cycles
-// <5=> 6 cycles
-// <6=> 7 cycles
-// <i> This field defines the number of wait states for read and write operations.
-// <id> efc_fws
-#ifndef CONF_EFC_WAIT_STATE
-#define CONF_EFC_WAIT_STATE 5
-#endif
-
-// </h>
-// </e>
-
-// <e> SysTick Clock
-// <id> enable_systick_clk_clock
-#ifndef CONF_SYSTICK_CLK_CONFIG
-#define CONF_SYSTICK_CLK_CONFIG 1
-#endif
-
-// <y> SysTick Clock source
-// <MCKR"> Master Clock Controller (PMC_MCKR)
-// <i> This defines the clock source for the SysTick Clock
-// <id> systick_clk_clock_source
-#ifndef CONF_SYSTICK_CLK_SRC
-#define CONF_SYSTICK_CLK_SRC MCKR
-#endif
-
-// <o> SysTick Clock Divider
-// <8=> 8
-// <i> Fixed to 8 if Systick is not using Processor clock
-// <id> systick_clk_clock_div
-#ifndef CONF_SYSTICK_CLK_DIV
-#define CONF_SYSTICK_CLK_DIV 8
-#endif
-
-// </e>
-
-// <e> OSC32K Oscillator Configuration
-// <i> Indicates whether configuration for OSC32K is enabled or not
-// <id> enable_osc32k
-#ifndef CONF_OSC32K_CONFIG
-#define CONF_OSC32K_CONFIG 1
-#endif
-
-// <h> OSC32K Oscillator Control
-// <q> OSC32K Oscillator Enable
-// <i> Indicates whether OSC32K Oscillator is enabled or not
-// <id> osc32k_arch_enable
-#ifndef CONF_OSC32K_ENABLE
-#define CONF_OSC32K_ENABLE 0
-#endif
-// </h>
-// </e>
-
-// <e> XOSC32K Oscillator Configuration
-// <i> Indicates whether configuration for XOSC32K is enabled or not
-// <id> enable_xosc32k
-#ifndef CONF_XOSC32K_CONFIG
-#define CONF_XOSC32K_CONFIG 0
-#endif
-
-// <h> XOSC32K Oscillator Control
-// <y> Oscillator Bypass Select
-// <CONF_XOSC32K_NO_BYPASS"> The 32kHz crystal oscillator is not bypassed.
-// <CONF_XOSC32K_BYPASS"> The 32kHz crystal oscillator is bypassed.
-// <i> Indicates whether XOSC32K is bypassed.
-// <id> xosc32k_bypass
-#ifndef CONF_XOSC32K
-#define CONF_XOSC32K CONF_XOSC32K_NO_BYPASS
-#endif
-
-// <q> XOSC32K Oscillator Enable
-// <i> Indicates whether XOSC32K Oscillator is enabled or not
-// <id> xosc32k_arch_enable
-#ifndef CONF_XOSC32K_ENABLE
-#define CONF_XOSC32K_ENABLE 0
-#endif
-// </h>
-// </e>
-
-// <e> OSC12M Oscillator Configuration
-// <i> Indicates whether configuration for OSC12M is enabled or not
-// <id> enable_osc12m
-#ifndef CONF_OSC12M_CONFIG
-#define CONF_OSC12M_CONFIG 0
-#endif
-
-// <h> OSC12M Oscillator Control
-// <q> OSC12M Oscillator Enable
-// <i> Indicates whether OSC12M Oscillator is enabled or not.
-// <id> osc12m_arch_enable
-#ifndef CONF_OSC12M_ENABLE
-#define CONF_OSC12M_ENABLE 0
-#endif
-
-// <o> OSC12M selector
-//  <0=> 4000000
-//  <1=> 8000000
-//  <2=> 12000000
-// <i> Select the frequency of embedded fast RC oscillator.
-// <id> osc12m_selector
-#ifndef CONF_OSC12M_SELECTOR
-#define CONF_OSC12M_SELECTOR 2
-#endif
-// </h>
-// </e>
-
-// <e> XOSC20M Oscillator Configuration
-// <i> Indicates whether configuration for XOSC20M is enabled or not.
-// <id> enable_xosc20m
-#ifndef CONF_XOSC20M_CONFIG
-#define CONF_XOSC20M_CONFIG 1
-#endif
-
-// <h> XOSC20M Oscillator Control
-// <o> XOSC20M selector <3000000-20000000>
-// <i> Select the frequency of crystal or ceramic resonator oscillator.
-// <id> xosc20m_selector
-#ifndef CONF_XOSC20M_SELECTOR
-#define CONF_XOSC20M_SELECTOR 12000000
-#endif
-
-// <o> Start up time for the external oscillator (ms): <0-256>
-// <i> Select start-up time.
-// <id> xosc20m_startup_time
-#ifndef CONF_XOSC20M_STARTUP_TIME
-#define CONF_XOSC20M_STARTUP_TIME 62
-#endif
-
-// <y> Oscillator Bypass Select
-// <CONF_XOSC20M_NO_BYPASS"> The external crystal oscillator is not bypassed.
-// <CONF_XOSC20M_BYPASS"> The external crystal oscillator is bypassed.
-// <i> Indicates whether XOSC20M is bypassed.
-// <id> xosc20m_bypass
-#ifndef CONF_XOSC20M
-#define CONF_XOSC20M CONF_XOSC20M_NO_BYPASS
-#endif
-
-// <q> XOSC20M Oscillator Enable
-// <i> Indicates whether XOSC20M Oscillator is enabled or not
-// <id> xosc20m_arch_enable
-#ifndef CONF_XOSC20M_ENABLE
-#define CONF_XOSC20M_ENABLE 1
-#endif
-// </h>
-// </e>
-
-// <e> PLLACK Oscillator Configuration
-// <i> Indicates whether configuration for PLLACK is enabled or not
-// <id> enable_pllack
-#ifndef CONF_PLLACK_CONFIG
-#define CONF_PLLACK_CONFIG 1
-#endif
-
-// <y> PLLACK Reference Clock Source
-// <MAINCK"> Main Clock (MAINCK)
-// <i> Select the clock source.
-// <id> pllack_ref_clock
-#ifndef CONF_PLLACK_CLK
-#define CONF_PLLACK_CLK MAINCK
-#endif
-
-// <h> PLLACK Oscillator Control
-// <q> PLLACK Oscillator Enable
-// <i> Indicates whether PLLACK Oscillator is enabled or not
-// <id> pllack_arch_enable
-#ifndef CONF_PLLACK_ENABLE
-#define CONF_PLLACK_ENABLE 1
-#endif
-
-// <o> PLLA Frontend Divider (DIVA)  <1-255>
-// <i> Select the clock divider
-// <id> pllack_div
-#ifndef CONF_PLLACK_DIV
-#define CONF_PLLACK_DIV 1
-#endif
-
-// <o> PLLACK Muliplier <1-62>
-// <i> Indicates PLLA multiplier (multiplier = MULA + 1).
-// <id> pllack_mul
-#ifndef CONF_PLLACK_MUL
-#define CONF_PLLACK_MUL 25
-#endif
-// </h>
-// </e>
-
-// <e> UPLLCK Oscillator Configuration
-// <i> Indicates whether configuration for UPLLCK is enabled or not
-// <id> enable_upllck
-#ifndef CONF_UPLLCK_CONFIG
-#define CONF_UPLLCK_CONFIG 1
-#endif
-
-// <y> UPLLCK Reference Clock Source
-// <XOSC20M"> External 3-20MHz Oscillator (XOSC20M)
-// <i> Select the clock source,only when the input frequency is 12M or 16M, the upllck output is 480M.
-// <id> upllck_ref_clock
-#ifndef CONF_UPLLCK_CLK
-#define CONF_UPLLCK_CLK XOSC20M
-#endif
-
-// <h> UPLLCK Oscillator Control
-// <q> UPLLCK Oscillator Enable
-// <i> Indicates whether UPLLCK Oscillator is enabled or not
-// <id> upllck_arch_enable
-#ifndef CONF_UPLLCK_ENABLE
-#define CONF_UPLLCK_ENABLE 1
-#endif
-// </h>
-// </e>
-
-// <e> UPLLCKDIV Oscillator Configuration
-// <i> Indicates whether configuration for UPLLCKDIV is enabled or not
-// <id> enable_upllckdiv
-#ifndef CONF_UPLLCKDIV_CONFIG
-#define CONF_UPLLCKDIV_CONFIG 1
-#endif
-
-// <y> UPLLCKDIV Reference Clock Source
-// <UPLLCK"> USB 480M Clock (UPLLCK)
-// <i> Select the clock source.
-// <id> upllckdiv_ref_clock
-#ifndef CONF_UPLLCKDIV_CLK
-#define CONF_UPLLCKDIV_CLK UPLLCK
-#endif
-
-// <h> UPLLCKDIV Oscillator Control
-// <o> UPLLCKDIV Clock Divider
-// <0=> 1
-// <1=> 2
-// <i> Select the clock divider.
-// <id> upllckdiv_div
-#ifndef CONF_UPLLCKDIV_DIV
-#define CONF_UPLLCKDIV_DIV 1
-#endif
-// </h>
-// </e>
-
-// <e> MCK/8
-// <id> enable_mck_div_8
-#ifndef CONF_MCK_DIV_8_CONFIG
-#define CONF_MCK_DIV_8_CONFIG 0
-#endif
-
-// <o> MCK/8 Source
-// <0=> Master Clock (MCK)
-// <id> mck_div_8_src
-#ifndef CONF_MCK_DIV_8_SRC
-#define CONF_MCK_DIV_8_SRC 0
-#endif
-// </e>
-
-// <e> External Clock Input Configuration
-// <id> enable_dummy_ext
-#ifndef CONF_DUMMY_EXT_CONFIG
-#define CONF_DUMMY_EXT_CONFIG 1
-#endif
-
-// <o> External Clock Input Source
-// <i> All here are dummy values
-// <i> Refer to the peripherals settings for actual input information
-// <0=> Specific clock input from specific pin
-// <id> dummy_ext_src
-#ifndef CONF_DUMMY_EXT_SRC
-#define CONF_DUMMY_EXT_SRC 0
-#endif
-// </e>
-
-// <e> External Clock Configuration
-// <id> enable_dummy_ext_clk
-#ifndef CONF_DUMMY_EXT_CLK_CONFIG
-#define CONF_DUMMY_EXT_CLK_CONFIG 1
-#endif
-
-// <o> External Clock Source
-// <i> All here are dummy values
-// <i> Refer to the peripherals settings for actual input information
-// <0=> External Clock Input
-// <id> dummy_ext_clk_src
-#ifndef CONF_DUMMY_EXT_CLK_SRC
-#define CONF_DUMMY_EXT_CLK_SRC 0
-#endif
-// </e>
-
-// <<< end of configuration section >>>
-
-#endif // HPL_PMC_CONFIG_H
diff --git a/tinyusb/hw/bsp/same70_xplained/hpl_usart_config.h b/tinyusb/hw/bsp/same70_xplained/hpl_usart_config.h
deleted file mode 100755
index 50ca3f15..00000000
--- a/tinyusb/hw/bsp/same70_xplained/hpl_usart_config.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/* Auto-generated config file hpl_usart_config.h */
-#ifndef HPL_USART_CONFIG_H
-#define HPL_USART_CONFIG_H
-
-// <<< Use Configuration Wizard in Context Menu >>>
-
-#include <peripheral_clk_config.h>
-
-#ifndef CONF_USART_1_ENABLE
-#define CONF_USART_1_ENABLE 1
-#endif
-
-// <h> Basic Configuration
-
-// <o> Frame parity
-// <0x0=>Even parity
-// <0x1=>Odd parity
-// <0x2=>Parity forced to 0
-// <0x3=>Parity forced to 1
-// <0x4=>No parity
-// <i> Parity bit mode for USART frame
-// <id> usart_parity
-#ifndef CONF_USART_1_PARITY
-#define CONF_USART_1_PARITY 0x4
-#endif
-
-// <o> Character Size
-// <0x0=>5 bits
-// <0x1=>6 bits
-// <0x2=>7 bits
-// <0x3=>8 bits
-// <i> Data character size in USART frame
-// <id> usart_character_size
-#ifndef CONF_USART_1_CHSIZE
-#define CONF_USART_1_CHSIZE 0x3
-#endif
-
-// <o> Stop Bit
-// <0=>1 stop bit
-// <1=>1.5 stop bits
-// <2=>2 stop bits
-// <i> Number of stop bits in USART frame
-// <id> usart_stop_bit
-#ifndef CONF_USART_1_SBMODE
-#define CONF_USART_1_SBMODE 0
-#endif
-
-// <o> Clock Output Select
-// <0=>The USART does not drive the SCK pin
-// <1=>The USART drives the SCK pin if USCLKS does not select the external clock SCK
-// <i> Clock Output Select in USART sck, if in usrt master mode, please drive SCK.
-// <id> usart_clock_output_select
-#ifndef CONF_USART_1_CLKO
-#define CONF_USART_1_CLKO 0
-#endif
-
-// <o> Baud rate <1-3000000>
-// <i> USART baud rate setting
-// <id> usart_baud_rate
-#ifndef CONF_USART_1_BAUD
-#define CONF_USART_1_BAUD 9600
-#endif
-
-// </h>
-
-// <e> Advanced configuration
-// <id> usart_advanced
-#ifndef CONF_USART_1_ADVANCED_CONFIG
-#define CONF_USART_1_ADVANCED_CONFIG 0
-#endif
-
-// <o> Channel Mode
-// <0=>Normal Mode
-// <1=>Automatic Echo
-// <2=>Local Loopback
-// <3=>Remote Loopback
-// <i> Channel mode in USART frame
-// <id> usart_channel_mode
-#ifndef CONF_USART_1_CHMODE
-#define CONF_USART_1_CHMODE 0
-#endif
-
-// <q> 9 bits character enable
-// <i> Enable 9 bits character, this has high priority than 5/6/7/8 bits.
-// <id> usart_9bits_enable
-#ifndef CONF_USART_1_MODE9
-#define CONF_USART_1_MODE9 0
-#endif
-
-// <o> Variable Sync
-// <0=>User defined configuration
-// <1=>sync field is updated when a character is written into US_THR
-// <i> Variable Synchronization of Command/Data Sync Start Frarm Delimiter
-// <id> variable_sync
-#ifndef CONF_USART_1_VAR_SYNC
-#define CONF_USART_1_VAR_SYNC 0
-#endif
-
-// <o> Oversampling Mode
-// <0=>16 Oversampling
-// <1=>8 Oversampling
-// <i> Oversampling Mode in UART mode
-// <id> usart__oversampling_mode
-#ifndef CONF_USART_1_OVER
-#define CONF_USART_1_OVER 0
-#endif
-
-// <o> Inhibit Non Ack
-// <0=>The NACK is generated
-// <1=>The NACK is not generated
-// <i> Inhibit Non Acknowledge
-// <id> usart__inack
-#ifndef CONF_USART_1_INACK
-#define CONF_USART_1_INACK 1
-#endif
-
-// <o> Disable Successive NACK
-// <0=>NACK is sent on the ISO line as soon as a parity error occurs
-// <1=>Many parity errors generate a NACK on the ISO line
-// <i> Disable Successive NACK
-// <id> usart_dsnack
-#ifndef CONF_USART_1_DSNACK
-#define CONF_USART_1_DSNACK 0
-#endif
-
-// <o> Inverted Data
-// <0=>Data isn't inverted, nomal mode
-// <1=>Data is inverted
-// <i> Inverted Data
-// <id> usart_invdata
-#ifndef CONF_USART_1_INVDATA
-#define CONF_USART_1_INVDATA 0
-#endif
-
-// <o> Maximum Number of Automatic Iteration <0-7>
-// <i> Defines the maximum number of iterations in mode ISO7816, protocol T = 0.
-// <id> usart_max_iteration
-#ifndef CONF_USART_1_MAX_ITERATION
-#define CONF_USART_1_MAX_ITERATION 0
-#endif
-
-// <q> Receive Line Filter enable
-// <i> whether the USART filters the receive line using a three-sample filter
-// <id> usart_receive_filter_enable
-#ifndef CONF_USART_1_FILTER
-#define CONF_USART_1_FILTER 0
-#endif
-
-// <q> Manchester Encoder/Decoder Enable
-// <i> whether the USART Manchester Encoder/Decoder
-// <id> usart_manchester_filter_enable
-#ifndef CONF_USART_1_MAN
-#define CONF_USART_1_MAN 0
-#endif
-
-// <o> Manchester Synchronization Mode
-// <0=>The Manchester start bit is a 0 to 1 transition
-// <1=>The Manchester start bit is a 1 to 0 transition
-// <i> Manchester Synchronization Mode
-// <id> usart_manchester_synchronization_mode
-#ifndef CONF_USART_1_MODSYNC
-#define CONF_USART_1_MODSYNC 0
-#endif
-
-// <o> Start Frame Delimiter Selector
-// <0=>Start frame delimiter is COMMAND or DATA SYNC
-// <1=>Start frame delimiter is one bit
-// <i> Start Frame Delimiter Selector
-// <id> usart_start_frame_delimiter
-#ifndef CONF_USART_1_ONEBIT
-#define CONF_USART_1_ONEBIT 0
-#endif
-
-// <o> Fractional Part <0-7>
-// <i> Fractional part of the baud rate if baud rate generator is in fractional mode
-// <id> usart_arch_fractional
-#ifndef CONF_USART_1_FRACTIONAL
-#define CONF_USART_1_FRACTIONAL 0x0
-#endif
-
-// <o> Data Order
-// <0=>LSB is transmitted first
-// <1=>MSB is transmitted first
-// <i> Data order of the data bits in the frame
-// <id> usart_arch_msbf
-#ifndef CONF_USART_1_MSBF
-#define CONF_USART_1_MSBF 0
-#endif
-
-// </e>
-
-#define CONF_USART_1_MODE 0x0
-
-// Calculate BAUD register value in UART mode
-#if CONF_USART1_CK_SRC < 3
-#ifndef CONF_USART_1_BAUD_CD
-#define CONF_USART_1_BAUD_CD ((CONF_USART1_FREQUENCY) / CONF_USART_1_BAUD / 8 / (2 - CONF_USART_1_OVER))
-#endif
-#ifndef CONF_USART_1_BAUD_FP
-#define CONF_USART_1_BAUD_FP                                                                                           \
-	((CONF_USART1_FREQUENCY) / CONF_USART_1_BAUD / (2 - CONF_USART_1_OVER) - 8 * CONF_USART_1_BAUD_CD)
-#endif
-#elif CONF_USART1_CK_SRC == 3
-// No division is active. The value written in US_BRGR has no effect.
-#ifndef CONF_USART_1_BAUD_CD
-#define CONF_USART_1_BAUD_CD 1
-#endif
-#ifndef CONF_USART_1_BAUD_FP
-#define CONF_USART_1_BAUD_FP 1
-#endif
-#endif
-
-// <<< end of configuration section >>>
-
-#endif // HPL_USART_CONFIG_H
diff --git a/tinyusb/hw/bsp/same70_xplained/hpl_xdmac_config.h b/tinyusb/hw/bsp/same70_xplained/hpl_xdmac_config.h
deleted file mode 100755
index a3d62c6f..00000000
--- a/tinyusb/hw/bsp/same70_xplained/hpl_xdmac_config.h
+++ /dev/null
@@ -1,4400 +0,0 @@
-/* Auto-generated config file hpl_xdmac_config.h */
-#ifndef HPL_XDMAC_CONFIG_H
-#define HPL_XDMAC_CONFIG_H
-
-// <<< Use Configuration Wizard in Context Menu >>>
-
-// <e> XDMAC enable
-// <i> Indicates whether xdmac is enabled or not
-// <id> xdmac_enable
-#ifndef CONF_DMA_ENABLE
-#define CONF_DMA_ENABLE 0
-#endif
-
-// <e> Channel 0 settings
-// <id> dmac_channel_0_settings
-#ifndef CONF_DMAC_CHANNEL_0_SETTINGS
-#define CONF_DMAC_CHANNEL_0_SETTINGS 0
-#endif
-
-// <o> Burst Size
-// <0x0=> 1 burst size
-// <0x1=> 4 burst size
-// <0x2=> 8 burst size
-// <0x3=> 16 burst size
-// <i> Define the memory burst size
-// <id> dmac_burstsize_0
-#ifndef CONF_DMAC_BURSTSIZE_0
-#define CONF_DMAC_BURSTSIZE_0 0x0
-#endif
-
-// <o> Chunk Size
-// <0x0=> 1 data transferred
-// <0x1=> 2 data transferred
-// <0x2=> 4 data transferred
-// <0x3=> 8 data transferred
-// <0x4=> 16 data transferred
-// <i> Define the peripheral chunk size
-// <id> dmac_chunksize_0
-#ifndef CONF_DMAC_CHUNKSIZE_0
-#define CONF_DMAC_CHUNKSIZE_0 0x0
-#endif
-
-// <o> Beat Size
-// <0=> 8-bit bus transfer
-// <1=> 16-bit bus transfer
-// <2=> 32-bit bus transfer
-// <i> Defines the size of one beat
-// <id> dmac_beatsize_0
-#ifndef CONF_DMAC_BEATSIZE_0
-#define CONF_DMAC_BEATSIZE_0 0x0
-#endif
-
-// <o> Source Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is read through the system bus interface 0 or 1
-// <id> dma_src_interface_0
-#ifndef CONF_DMAC_SRC_INTERFACE_0
-#define CONF_DMAC_SRC_INTERFACE_0 0x0
-#endif
-
-// <o> Destination Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is written through the system bus interface 0 or 1
-// <id> dma_des_interface_0
-#ifndef CONF_DMAC_DES_INTERFACE_0
-#define CONF_DMAC_DES_INTERFACE_0 0x0
-#endif
-
-// <q> Source Address Increment
-// <i> Indicates whether the source address incremented as beat size or not
-// <id> dmac_srcinc_0
-#ifndef CONF_DMAC_SRCINC_0
-#define CONF_DMAC_SRCINC_0 0
-#endif
-
-// <q> Destination Address Increment
-// <i> Indicates whether the destination address incremented as beat size or not
-// <id> dmac_dstinc_0
-#ifndef CONF_DMAC_DSTINC_0
-#define CONF_DMAC_DSTINC_0 0
-#endif
-
-// <o> Transfer Type
-// <0x0=> Memory to Memory Transfer
-// <0x1=> Peripheral to Memory Transfer
-// <0x2=> Memory to Peripheral Transfer
-// <i> Define the data transfer type
-// <id> dma_trans_type_0
-#ifndef CONF_DMAC_TRANS_TYPE_0
-#define CONF_DMAC_TRANS_TYPE_0 0x0
-#endif
-
-// <o> Trigger source
-// <0xFF=> Software Trigger
-// <0x00=> HSMCI TX/RX Trigger
-// <0x01=> SPI0 TX Trigger
-// <0x02=> SPI0 RX Trigger
-// <0x03=> SPI1 TX Trigger
-// <0x04=> SPI1 RX Trigger
-// <0x05=> QSPI TX Trigger
-// <0x06=> QSPI RX Trigger
-// <0x07=> USART0 TX Trigger
-// <0x08=> USART0 RX Trigger
-// <0x09=> USART1 TX Trigger
-// <0x0A=> USART1 RX Trigger
-// <0x0B=> USART2 TX Trigger
-// <0x0C=> USART2 RX Trigger
-// <0x0D=> PWM0 TX Trigger
-// <0x0E=> TWIHS0 TX Trigger
-// <0x0F=> TWIHS0 RX Trigger
-// <0x10=> TWIHS1 TX Trigger
-// <0x11=> TWIHS1 RX Trigger
-// <0x12=> TWIHS2 TX Trigger
-// <0x13=> TWIHS2 RX Trigger
-// <0x14=> UART0 TX Trigger
-// <0x15=> UART0 RX Trigger
-// <0x16=> UART1 TX Trigger
-// <0x17=> UART1 RX Trigger
-// <0x18=> UART2 TX Trigger
-// <0x19=> UART2 RX Trigger
-// <0x1A=> UART3 TX Trigger
-// <0x1B=> UART3 RX Trigger
-// <0x1C=> UART4 TX Trigger
-// <0x1D=> UART4 RX Trigger
-// <0x1E=> DACC TX Trigger
-// <0x20=> SSC TX Trigger
-// <0x21=> SSC RX Trigger
-// <0x22=> PIOA RX Trigger
-// <0x23=> AFEC0 RX Trigger
-// <0x24=> AFEC1 RX Trigger
-// <0x25=> AES TX Trigger
-// <0x26=> AES RX Trigger
-// <0x27=> PWM1 TX Trigger
-// <0x28=> TC0 RX Trigger
-// <0x29=> TC3 RX Trigger
-// <0x2A=> TC6 RX Trigger
-// <0x2B=> TC9 RX Trigger
-// <0x2C=> I2SC0 TX Left Trigger
-// <0x2D=> I2SC0 RX Left Trigger
-// <0x2E=> I2SC1 TX Left Trigger
-// <0x2F=> I2SC1 RX Left Trigger
-// <0x30=> I2SC0 TX Right Trigger
-// <0x31=> I2SC0 RX Right Trigger
-// <0x32=> I2SC1 TX Right Trigger
-// <0x33=> I2SC1 RX Right Trigger
-// <i> Define the DMA trigger source
-// <id> dmac_trifsrc_0
-#ifndef CONF_DMAC_TRIGSRC_0
-#define CONF_DMAC_TRIGSRC_0 0xff
-#endif
-
-// </e>
-
-#if CONF_DMAC_TRANS_TYPE_0 == 0
-#define CONF_DMAC_TYPE_0 0
-#define CONF_DMAC_DSYNC_0 0
-#elif CONF_DMAC_TRANS_TYPE_0 == 1
-#define CONF_DMAC_TYPE_0 1
-#define CONF_DMAC_DSYNC_0 0
-#elif CONF_DMAC_TRANS_TYPE_0 == 2
-#define CONF_DMAC_TYPE_0 1
-#define CONF_DMAC_DSYNC_0 1
-#endif
-
-#if CONF_DMAC_TRIGSRC_0 == 0xFF
-#define CONF_DMAC_SWREQ_0 1
-#else
-#define CONF_DMAC_SWREQ_0 0
-#endif
-
-/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
- * or fixed destination address mode, source and destination addresses are incremented
- * by 8-bit or 16-bit.
- * Workaround: The user can fix the problem by setting the source addressing mode to
- * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
- */
-#if (CONF_DMAC_CHANNEL_0_SETTINGS == 1 && CONF_DMAC_BEATSIZE_0 != 2 && ((!CONF_DMAC_SRCINC_0) || (!CONF_DMAC_DSTINC_0)))
-#if (!CONF_DMAC_SRCINC_0)
-#define CONF_DMAC_SRC_STRIDE_0 ((int16_t)(-1))
-#endif
-#if (!CONF_DMAC_DSTINC_0)
-#define CONF_DMAC_DES_STRIDE_0 ((int16_t)(-1))
-#endif
-#endif
-
-#ifndef CONF_DMAC_SRC_STRIDE_0
-#define CONF_DMAC_SRC_STRIDE_0 0
-#endif
-
-#ifndef CONF_DMAC_DES_STRIDE_0
-#define CONF_DMAC_DES_STRIDE_0 0
-#endif
-
-// <e> Channel 1 settings
-// <id> dmac_channel_1_settings
-#ifndef CONF_DMAC_CHANNEL_1_SETTINGS
-#define CONF_DMAC_CHANNEL_1_SETTINGS 0
-#endif
-
-// <o> Burst Size
-// <0x0=> 1 burst size
-// <0x1=> 4 burst size
-// <0x2=> 8 burst size
-// <0x3=> 16 burst size
-// <i> Define the memory burst size
-// <id> dmac_burstsize_1
-#ifndef CONF_DMAC_BURSTSIZE_1
-#define CONF_DMAC_BURSTSIZE_1 0x0
-#endif
-
-// <o> Chunk Size
-// <0x0=> 1 data transferred
-// <0x1=> 2 data transferred
-// <0x2=> 4 data transferred
-// <0x3=> 8 data transferred
-// <0x4=> 16 data transferred
-// <i> Define the peripheral chunk size
-// <id> dmac_chunksize_1
-#ifndef CONF_DMAC_CHUNKSIZE_1
-#define CONF_DMAC_CHUNKSIZE_1 0x0
-#endif
-
-// <o> Beat Size
-// <0=> 8-bit bus transfer
-// <1=> 16-bit bus transfer
-// <2=> 32-bit bus transfer
-// <i> Defines the size of one beat
-// <id> dmac_beatsize_1
-#ifndef CONF_DMAC_BEATSIZE_1
-#define CONF_DMAC_BEATSIZE_1 0x0
-#endif
-
-// <o> Source Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is read through the system bus interface 0 or 1
-// <id> dma_src_interface_1
-#ifndef CONF_DMAC_SRC_INTERFACE_1
-#define CONF_DMAC_SRC_INTERFACE_1 0x0
-#endif
-
-// <o> Destination Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is written through the system bus interface 0 or 1
-// <id> dma_des_interface_1
-#ifndef CONF_DMAC_DES_INTERFACE_1
-#define CONF_DMAC_DES_INTERFACE_1 0x0
-#endif
-
-// <q> Source Address Increment
-// <i> Indicates whether the source address incremented as beat size or not
-// <id> dmac_srcinc_1
-#ifndef CONF_DMAC_SRCINC_1
-#define CONF_DMAC_SRCINC_1 0
-#endif
-
-// <q> Destination Address Increment
-// <i> Indicates whether the destination address incremented as beat size or not
-// <id> dmac_dstinc_1
-#ifndef CONF_DMAC_DSTINC_1
-#define CONF_DMAC_DSTINC_1 0
-#endif
-
-// <o> Transfer Type
-// <0x0=> Memory to Memory Transfer
-// <0x1=> Peripheral to Memory Transfer
-// <0x2=> Memory to Peripheral Transfer
-// <i> Define the data transfer type
-// <id> dma_trans_type_1
-#ifndef CONF_DMAC_TRANS_TYPE_1
-#define CONF_DMAC_TRANS_TYPE_1 0x0
-#endif
-
-// <o> Trigger source
-// <0xFF=> Software Trigger
-// <0x00=> HSMCI TX/RX Trigger
-// <0x01=> SPI0 TX Trigger
-// <0x02=> SPI0 RX Trigger
-// <0x03=> SPI1 TX Trigger
-// <0x04=> SPI1 RX Trigger
-// <0x05=> QSPI TX Trigger
-// <0x06=> QSPI RX Trigger
-// <0x07=> USART0 TX Trigger
-// <0x08=> USART0 RX Trigger
-// <0x09=> USART1 TX Trigger
-// <0x0A=> USART1 RX Trigger
-// <0x0B=> USART2 TX Trigger
-// <0x0C=> USART2 RX Trigger
-// <0x0D=> PWM0 TX Trigger
-// <0x0E=> TWIHS0 TX Trigger
-// <0x0F=> TWIHS0 RX Trigger
-// <0x10=> TWIHS1 TX Trigger
-// <0x11=> TWIHS1 RX Trigger
-// <0x12=> TWIHS2 TX Trigger
-// <0x13=> TWIHS2 RX Trigger
-// <0x14=> UART0 TX Trigger
-// <0x15=> UART0 RX Trigger
-// <0x16=> UART1 TX Trigger
-// <0x17=> UART1 RX Trigger
-// <0x18=> UART2 TX Trigger
-// <0x19=> UART2 RX Trigger
-// <0x1A=> UART3 TX Trigger
-// <0x1B=> UART3 RX Trigger
-// <0x1C=> UART4 TX Trigger
-// <0x1D=> UART4 RX Trigger
-// <0x1E=> DACC TX Trigger
-// <0x20=> SSC TX Trigger
-// <0x21=> SSC RX Trigger
-// <0x22=> PIOA RX Trigger
-// <0x23=> AFEC0 RX Trigger
-// <0x24=> AFEC1 RX Trigger
-// <0x25=> AES TX Trigger
-// <0x26=> AES RX Trigger
-// <0x27=> PWM1 TX Trigger
-// <0x28=> TC0 RX Trigger
-// <0x29=> TC3 RX Trigger
-// <0x2A=> TC6 RX Trigger
-// <0x2B=> TC9 RX Trigger
-// <0x2C=> I2SC0 TX Left Trigger
-// <0x2D=> I2SC0 RX Left Trigger
-// <0x2E=> I2SC1 TX Left Trigger
-// <0x2F=> I2SC1 RX Left Trigger
-// <0x30=> I2SC0 TX Right Trigger
-// <0x31=> I2SC0 RX Right Trigger
-// <0x32=> I2SC1 TX Right Trigger
-// <0x33=> I2SC1 RX Right Trigger
-// <i> Define the DMA trigger source
-// <id> dmac_trifsrc_1
-#ifndef CONF_DMAC_TRIGSRC_1
-#define CONF_DMAC_TRIGSRC_1 0xff
-#endif
-
-// </e>
-
-#if CONF_DMAC_TRANS_TYPE_1 == 0
-#define CONF_DMAC_TYPE_1 0
-#define CONF_DMAC_DSYNC_1 0
-#elif CONF_DMAC_TRANS_TYPE_1 == 1
-#define CONF_DMAC_TYPE_1 1
-#define CONF_DMAC_DSYNC_1 0
-#elif CONF_DMAC_TRANS_TYPE_1 == 2
-#define CONF_DMAC_TYPE_1 1
-#define CONF_DMAC_DSYNC_1 1
-#endif
-
-#if CONF_DMAC_TRIGSRC_1 == 0xFF
-#define CONF_DMAC_SWREQ_1 1
-#else
-#define CONF_DMAC_SWREQ_1 0
-#endif
-
-/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
- * or fixed destination address mode, source and destination addresses are incremented
- * by 8-bit or 16-bit.
- * Workaround: The user can fix the problem by setting the source addressing mode to
- * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
- */
-#if (CONF_DMAC_CHANNEL_1_SETTINGS == 1 && CONF_DMAC_BEATSIZE_1 != 2 && ((!CONF_DMAC_SRCINC_1) || (!CONF_DMAC_DSTINC_1)))
-#if (!CONF_DMAC_SRCINC_1)
-#define CONF_DMAC_SRC_STRIDE_1 ((int16_t)(-1))
-#endif
-#if (!CONF_DMAC_DSTINC_1)
-#define CONF_DMAC_DES_STRIDE_1 ((int16_t)(-1))
-#endif
-#endif
-
-#ifndef CONF_DMAC_SRC_STRIDE_1
-#define CONF_DMAC_SRC_STRIDE_1 0
-#endif
-
-#ifndef CONF_DMAC_DES_STRIDE_1
-#define CONF_DMAC_DES_STRIDE_1 0
-#endif
-
-// <e> Channel 2 settings
-// <id> dmac_channel_2_settings
-#ifndef CONF_DMAC_CHANNEL_2_SETTINGS
-#define CONF_DMAC_CHANNEL_2_SETTINGS 0
-#endif
-
-// <o> Burst Size
-// <0x0=> 1 burst size
-// <0x1=> 4 burst size
-// <0x2=> 8 burst size
-// <0x3=> 16 burst size
-// <i> Define the memory burst size
-// <id> dmac_burstsize_2
-#ifndef CONF_DMAC_BURSTSIZE_2
-#define CONF_DMAC_BURSTSIZE_2 0x0
-#endif
-
-// <o> Chunk Size
-// <0x0=> 1 data transferred
-// <0x1=> 2 data transferred
-// <0x2=> 4 data transferred
-// <0x3=> 8 data transferred
-// <0x4=> 16 data transferred
-// <i> Define the peripheral chunk size
-// <id> dmac_chunksize_2
-#ifndef CONF_DMAC_CHUNKSIZE_2
-#define CONF_DMAC_CHUNKSIZE_2 0x0
-#endif
-
-// <o> Beat Size
-// <0=> 8-bit bus transfer
-// <1=> 16-bit bus transfer
-// <2=> 32-bit bus transfer
-// <i> Defines the size of one beat
-// <id> dmac_beatsize_2
-#ifndef CONF_DMAC_BEATSIZE_2
-#define CONF_DMAC_BEATSIZE_2 0x0
-#endif
-
-// <o> Source Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is read through the system bus interface 0 or 1
-// <id> dma_src_interface_2
-#ifndef CONF_DMAC_SRC_INTERFACE_2
-#define CONF_DMAC_SRC_INTERFACE_2 0x0
-#endif
-
-// <o> Destination Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is written through the system bus interface 0 or 1
-// <id> dma_des_interface_2
-#ifndef CONF_DMAC_DES_INTERFACE_2
-#define CONF_DMAC_DES_INTERFACE_2 0x0
-#endif
-
-// <q> Source Address Increment
-// <i> Indicates whether the source address incremented as beat size or not
-// <id> dmac_srcinc_2
-#ifndef CONF_DMAC_SRCINC_2
-#define CONF_DMAC_SRCINC_2 0
-#endif
-
-// <q> Destination Address Increment
-// <i> Indicates whether the destination address incremented as beat size or not
-// <id> dmac_dstinc_2
-#ifndef CONF_DMAC_DSTINC_2
-#define CONF_DMAC_DSTINC_2 0
-#endif
-
-// <o> Transfer Type
-// <0x0=> Memory to Memory Transfer
-// <0x1=> Peripheral to Memory Transfer
-// <0x2=> Memory to Peripheral Transfer
-// <i> Define the data transfer type
-// <id> dma_trans_type_2
-#ifndef CONF_DMAC_TRANS_TYPE_2
-#define CONF_DMAC_TRANS_TYPE_2 0x0
-#endif
-
-// <o> Trigger source
-// <0xFF=> Software Trigger
-// <0x00=> HSMCI TX/RX Trigger
-// <0x01=> SPI0 TX Trigger
-// <0x02=> SPI0 RX Trigger
-// <0x03=> SPI1 TX Trigger
-// <0x04=> SPI1 RX Trigger
-// <0x05=> QSPI TX Trigger
-// <0x06=> QSPI RX Trigger
-// <0x07=> USART0 TX Trigger
-// <0x08=> USART0 RX Trigger
-// <0x09=> USART1 TX Trigger
-// <0x0A=> USART1 RX Trigger
-// <0x0B=> USART2 TX Trigger
-// <0x0C=> USART2 RX Trigger
-// <0x0D=> PWM0 TX Trigger
-// <0x0E=> TWIHS0 TX Trigger
-// <0x0F=> TWIHS0 RX Trigger
-// <0x10=> TWIHS1 TX Trigger
-// <0x11=> TWIHS1 RX Trigger
-// <0x12=> TWIHS2 TX Trigger
-// <0x13=> TWIHS2 RX Trigger
-// <0x14=> UART0 TX Trigger
-// <0x15=> UART0 RX Trigger
-// <0x16=> UART1 TX Trigger
-// <0x17=> UART1 RX Trigger
-// <0x18=> UART2 TX Trigger
-// <0x19=> UART2 RX Trigger
-// <0x1A=> UART3 TX Trigger
-// <0x1B=> UART3 RX Trigger
-// <0x1C=> UART4 TX Trigger
-// <0x1D=> UART4 RX Trigger
-// <0x1E=> DACC TX Trigger
-// <0x20=> SSC TX Trigger
-// <0x21=> SSC RX Trigger
-// <0x22=> PIOA RX Trigger
-// <0x23=> AFEC0 RX Trigger
-// <0x24=> AFEC1 RX Trigger
-// <0x25=> AES TX Trigger
-// <0x26=> AES RX Trigger
-// <0x27=> PWM1 TX Trigger
-// <0x28=> TC0 RX Trigger
-// <0x29=> TC3 RX Trigger
-// <0x2A=> TC6 RX Trigger
-// <0x2B=> TC9 RX Trigger
-// <0x2C=> I2SC0 TX Left Trigger
-// <0x2D=> I2SC0 RX Left Trigger
-// <0x2E=> I2SC1 TX Left Trigger
-// <0x2F=> I2SC1 RX Left Trigger
-// <0x30=> I2SC0 TX Right Trigger
-// <0x31=> I2SC0 RX Right Trigger
-// <0x32=> I2SC1 TX Right Trigger
-// <0x33=> I2SC1 RX Right Trigger
-// <i> Define the DMA trigger source
-// <id> dmac_trifsrc_2
-#ifndef CONF_DMAC_TRIGSRC_2
-#define CONF_DMAC_TRIGSRC_2 0xff
-#endif
-
-// </e>
-
-#if CONF_DMAC_TRANS_TYPE_2 == 0
-#define CONF_DMAC_TYPE_2 0
-#define CONF_DMAC_DSYNC_2 0
-#elif CONF_DMAC_TRANS_TYPE_2 == 1
-#define CONF_DMAC_TYPE_2 1
-#define CONF_DMAC_DSYNC_2 0
-#elif CONF_DMAC_TRANS_TYPE_2 == 2
-#define CONF_DMAC_TYPE_2 1
-#define CONF_DMAC_DSYNC_2 1
-#endif
-
-#if CONF_DMAC_TRIGSRC_2 == 0xFF
-#define CONF_DMAC_SWREQ_2 1
-#else
-#define CONF_DMAC_SWREQ_2 0
-#endif
-
-/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
- * or fixed destination address mode, source and destination addresses are incremented
- * by 8-bit or 16-bit.
- * Workaround: The user can fix the problem by setting the source addressing mode to
- * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
- */
-#if (CONF_DMAC_CHANNEL_2_SETTINGS == 1 && CONF_DMAC_BEATSIZE_2 != 2 && ((!CONF_DMAC_SRCINC_2) || (!CONF_DMAC_DSTINC_2)))
-#if (!CONF_DMAC_SRCINC_2)
-#define CONF_DMAC_SRC_STRIDE_2 ((int16_t)(-1))
-#endif
-#if (!CONF_DMAC_DSTINC_2)
-#define CONF_DMAC_DES_STRIDE_2 ((int16_t)(-1))
-#endif
-#endif
-
-#ifndef CONF_DMAC_SRC_STRIDE_2
-#define CONF_DMAC_SRC_STRIDE_2 0
-#endif
-
-#ifndef CONF_DMAC_DES_STRIDE_2
-#define CONF_DMAC_DES_STRIDE_2 0
-#endif
-
-// <e> Channel 3 settings
-// <id> dmac_channel_3_settings
-#ifndef CONF_DMAC_CHANNEL_3_SETTINGS
-#define CONF_DMAC_CHANNEL_3_SETTINGS 0
-#endif
-
-// <o> Burst Size
-// <0x0=> 1 burst size
-// <0x1=> 4 burst size
-// <0x2=> 8 burst size
-// <0x3=> 16 burst size
-// <i> Define the memory burst size
-// <id> dmac_burstsize_3
-#ifndef CONF_DMAC_BURSTSIZE_3
-#define CONF_DMAC_BURSTSIZE_3 0x0
-#endif
-
-// <o> Chunk Size
-// <0x0=> 1 data transferred
-// <0x1=> 2 data transferred
-// <0x2=> 4 data transferred
-// <0x3=> 8 data transferred
-// <0x4=> 16 data transferred
-// <i> Define the peripheral chunk size
-// <id> dmac_chunksize_3
-#ifndef CONF_DMAC_CHUNKSIZE_3
-#define CONF_DMAC_CHUNKSIZE_3 0x0
-#endif
-
-// <o> Beat Size
-// <0=> 8-bit bus transfer
-// <1=> 16-bit bus transfer
-// <2=> 32-bit bus transfer
-// <i> Defines the size of one beat
-// <id> dmac_beatsize_3
-#ifndef CONF_DMAC_BEATSIZE_3
-#define CONF_DMAC_BEATSIZE_3 0x0
-#endif
-
-// <o> Source Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is read through the system bus interface 0 or 1
-// <id> dma_src_interface_3
-#ifndef CONF_DMAC_SRC_INTERFACE_3
-#define CONF_DMAC_SRC_INTERFACE_3 0x0
-#endif
-
-// <o> Destination Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is written through the system bus interface 0 or 1
-// <id> dma_des_interface_3
-#ifndef CONF_DMAC_DES_INTERFACE_3
-#define CONF_DMAC_DES_INTERFACE_3 0x0
-#endif
-
-// <q> Source Address Increment
-// <i> Indicates whether the source address incremented as beat size or not
-// <id> dmac_srcinc_3
-#ifndef CONF_DMAC_SRCINC_3
-#define CONF_DMAC_SRCINC_3 0
-#endif
-
-// <q> Destination Address Increment
-// <i> Indicates whether the destination address incremented as beat size or not
-// <id> dmac_dstinc_3
-#ifndef CONF_DMAC_DSTINC_3
-#define CONF_DMAC_DSTINC_3 0
-#endif
-
-// <o> Transfer Type
-// <0x0=> Memory to Memory Transfer
-// <0x1=> Peripheral to Memory Transfer
-// <0x2=> Memory to Peripheral Transfer
-// <i> Define the data transfer type
-// <id> dma_trans_type_3
-#ifndef CONF_DMAC_TRANS_TYPE_3
-#define CONF_DMAC_TRANS_TYPE_3 0x0
-#endif
-
-// <o> Trigger source
-// <0xFF=> Software Trigger
-// <0x00=> HSMCI TX/RX Trigger
-// <0x01=> SPI0 TX Trigger
-// <0x02=> SPI0 RX Trigger
-// <0x03=> SPI1 TX Trigger
-// <0x04=> SPI1 RX Trigger
-// <0x05=> QSPI TX Trigger
-// <0x06=> QSPI RX Trigger
-// <0x07=> USART0 TX Trigger
-// <0x08=> USART0 RX Trigger
-// <0x09=> USART1 TX Trigger
-// <0x0A=> USART1 RX Trigger
-// <0x0B=> USART2 TX Trigger
-// <0x0C=> USART2 RX Trigger
-// <0x0D=> PWM0 TX Trigger
-// <0x0E=> TWIHS0 TX Trigger
-// <0x0F=> TWIHS0 RX Trigger
-// <0x10=> TWIHS1 TX Trigger
-// <0x11=> TWIHS1 RX Trigger
-// <0x12=> TWIHS2 TX Trigger
-// <0x13=> TWIHS2 RX Trigger
-// <0x14=> UART0 TX Trigger
-// <0x15=> UART0 RX Trigger
-// <0x16=> UART1 TX Trigger
-// <0x17=> UART1 RX Trigger
-// <0x18=> UART2 TX Trigger
-// <0x19=> UART2 RX Trigger
-// <0x1A=> UART3 TX Trigger
-// <0x1B=> UART3 RX Trigger
-// <0x1C=> UART4 TX Trigger
-// <0x1D=> UART4 RX Trigger
-// <0x1E=> DACC TX Trigger
-// <0x20=> SSC TX Trigger
-// <0x21=> SSC RX Trigger
-// <0x22=> PIOA RX Trigger
-// <0x23=> AFEC0 RX Trigger
-// <0x24=> AFEC1 RX Trigger
-// <0x25=> AES TX Trigger
-// <0x26=> AES RX Trigger
-// <0x27=> PWM1 TX Trigger
-// <0x28=> TC0 RX Trigger
-// <0x29=> TC3 RX Trigger
-// <0x2A=> TC6 RX Trigger
-// <0x2B=> TC9 RX Trigger
-// <0x2C=> I2SC0 TX Left Trigger
-// <0x2D=> I2SC0 RX Left Trigger
-// <0x2E=> I2SC1 TX Left Trigger
-// <0x2F=> I2SC1 RX Left Trigger
-// <0x30=> I2SC0 TX Right Trigger
-// <0x31=> I2SC0 RX Right Trigger
-// <0x32=> I2SC1 TX Right Trigger
-// <0x33=> I2SC1 RX Right Trigger
-// <i> Define the DMA trigger source
-// <id> dmac_trifsrc_3
-#ifndef CONF_DMAC_TRIGSRC_3
-#define CONF_DMAC_TRIGSRC_3 0xff
-#endif
-
-// </e>
-
-#if CONF_DMAC_TRANS_TYPE_3 == 0
-#define CONF_DMAC_TYPE_3 0
-#define CONF_DMAC_DSYNC_3 0
-#elif CONF_DMAC_TRANS_TYPE_3 == 1
-#define CONF_DMAC_TYPE_3 1
-#define CONF_DMAC_DSYNC_3 0
-#elif CONF_DMAC_TRANS_TYPE_3 == 2
-#define CONF_DMAC_TYPE_3 1
-#define CONF_DMAC_DSYNC_3 1
-#endif
-
-#if CONF_DMAC_TRIGSRC_3 == 0xFF
-#define CONF_DMAC_SWREQ_3 1
-#else
-#define CONF_DMAC_SWREQ_3 0
-#endif
-
-/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
- * or fixed destination address mode, source and destination addresses are incremented
- * by 8-bit or 16-bit.
- * Workaround: The user can fix the problem by setting the source addressing mode to
- * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
- */
-#if (CONF_DMAC_CHANNEL_3_SETTINGS == 1 && CONF_DMAC_BEATSIZE_3 != 2 && ((!CONF_DMAC_SRCINC_3) || (!CONF_DMAC_DSTINC_3)))
-#if (!CONF_DMAC_SRCINC_3)
-#define CONF_DMAC_SRC_STRIDE_3 ((int16_t)(-1))
-#endif
-#if (!CONF_DMAC_DSTINC_3)
-#define CONF_DMAC_DES_STRIDE_3 ((int16_t)(-1))
-#endif
-#endif
-
-#ifndef CONF_DMAC_SRC_STRIDE_3
-#define CONF_DMAC_SRC_STRIDE_3 0
-#endif
-
-#ifndef CONF_DMAC_DES_STRIDE_3
-#define CONF_DMAC_DES_STRIDE_3 0
-#endif
-
-// <e> Channel 4 settings
-// <id> dmac_channel_4_settings
-#ifndef CONF_DMAC_CHANNEL_4_SETTINGS
-#define CONF_DMAC_CHANNEL_4_SETTINGS 0
-#endif
-
-// <o> Burst Size
-// <0x0=> 1 burst size
-// <0x1=> 4 burst size
-// <0x2=> 8 burst size
-// <0x3=> 16 burst size
-// <i> Define the memory burst size
-// <id> dmac_burstsize_4
-#ifndef CONF_DMAC_BURSTSIZE_4
-#define CONF_DMAC_BURSTSIZE_4 0x0
-#endif
-
-// <o> Chunk Size
-// <0x0=> 1 data transferred
-// <0x1=> 2 data transferred
-// <0x2=> 4 data transferred
-// <0x3=> 8 data transferred
-// <0x4=> 16 data transferred
-// <i> Define the peripheral chunk size
-// <id> dmac_chunksize_4
-#ifndef CONF_DMAC_CHUNKSIZE_4
-#define CONF_DMAC_CHUNKSIZE_4 0x0
-#endif
-
-// <o> Beat Size
-// <0=> 8-bit bus transfer
-// <1=> 16-bit bus transfer
-// <2=> 32-bit bus transfer
-// <i> Defines the size of one beat
-// <id> dmac_beatsize_4
-#ifndef CONF_DMAC_BEATSIZE_4
-#define CONF_DMAC_BEATSIZE_4 0x0
-#endif
-
-// <o> Source Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is read through the system bus interface 0 or 1
-// <id> dma_src_interface_4
-#ifndef CONF_DMAC_SRC_INTERFACE_4
-#define CONF_DMAC_SRC_INTERFACE_4 0x0
-#endif
-
-// <o> Destination Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is written through the system bus interface 0 or 1
-// <id> dma_des_interface_4
-#ifndef CONF_DMAC_DES_INTERFACE_4
-#define CONF_DMAC_DES_INTERFACE_4 0x0
-#endif
-
-// <q> Source Address Increment
-// <i> Indicates whether the source address incremented as beat size or not
-// <id> dmac_srcinc_4
-#ifndef CONF_DMAC_SRCINC_4
-#define CONF_DMAC_SRCINC_4 0
-#endif
-
-// <q> Destination Address Increment
-// <i> Indicates whether the destination address incremented as beat size or not
-// <id> dmac_dstinc_4
-#ifndef CONF_DMAC_DSTINC_4
-#define CONF_DMAC_DSTINC_4 0
-#endif
-
-// <o> Transfer Type
-// <0x0=> Memory to Memory Transfer
-// <0x1=> Peripheral to Memory Transfer
-// <0x2=> Memory to Peripheral Transfer
-// <i> Define the data transfer type
-// <id> dma_trans_type_4
-#ifndef CONF_DMAC_TRANS_TYPE_4
-#define CONF_DMAC_TRANS_TYPE_4 0x0
-#endif
-
-// <o> Trigger source
-// <0xFF=> Software Trigger
-// <0x00=> HSMCI TX/RX Trigger
-// <0x01=> SPI0 TX Trigger
-// <0x02=> SPI0 RX Trigger
-// <0x03=> SPI1 TX Trigger
-// <0x04=> SPI1 RX Trigger
-// <0x05=> QSPI TX Trigger
-// <0x06=> QSPI RX Trigger
-// <0x07=> USART0 TX Trigger
-// <0x08=> USART0 RX Trigger
-// <0x09=> USART1 TX Trigger
-// <0x0A=> USART1 RX Trigger
-// <0x0B=> USART2 TX Trigger
-// <0x0C=> USART2 RX Trigger
-// <0x0D=> PWM0 TX Trigger
-// <0x0E=> TWIHS0 TX Trigger
-// <0x0F=> TWIHS0 RX Trigger
-// <0x10=> TWIHS1 TX Trigger
-// <0x11=> TWIHS1 RX Trigger
-// <0x12=> TWIHS2 TX Trigger
-// <0x13=> TWIHS2 RX Trigger
-// <0x14=> UART0 TX Trigger
-// <0x15=> UART0 RX Trigger
-// <0x16=> UART1 TX Trigger
-// <0x17=> UART1 RX Trigger
-// <0x18=> UART2 TX Trigger
-// <0x19=> UART2 RX Trigger
-// <0x1A=> UART3 TX Trigger
-// <0x1B=> UART3 RX Trigger
-// <0x1C=> UART4 TX Trigger
-// <0x1D=> UART4 RX Trigger
-// <0x1E=> DACC TX Trigger
-// <0x20=> SSC TX Trigger
-// <0x21=> SSC RX Trigger
-// <0x22=> PIOA RX Trigger
-// <0x23=> AFEC0 RX Trigger
-// <0x24=> AFEC1 RX Trigger
-// <0x25=> AES TX Trigger
-// <0x26=> AES RX Trigger
-// <0x27=> PWM1 TX Trigger
-// <0x28=> TC0 RX Trigger
-// <0x29=> TC3 RX Trigger
-// <0x2A=> TC6 RX Trigger
-// <0x2B=> TC9 RX Trigger
-// <0x2C=> I2SC0 TX Left Trigger
-// <0x2D=> I2SC0 RX Left Trigger
-// <0x2E=> I2SC1 TX Left Trigger
-// <0x2F=> I2SC1 RX Left Trigger
-// <0x30=> I2SC0 TX Right Trigger
-// <0x31=> I2SC0 RX Right Trigger
-// <0x32=> I2SC1 TX Right Trigger
-// <0x33=> I2SC1 RX Right Trigger
-// <i> Define the DMA trigger source
-// <id> dmac_trifsrc_4
-#ifndef CONF_DMAC_TRIGSRC_4
-#define CONF_DMAC_TRIGSRC_4 0xff
-#endif
-
-// </e>
-
-#if CONF_DMAC_TRANS_TYPE_4 == 0
-#define CONF_DMAC_TYPE_4 0
-#define CONF_DMAC_DSYNC_4 0
-#elif CONF_DMAC_TRANS_TYPE_4 == 1
-#define CONF_DMAC_TYPE_4 1
-#define CONF_DMAC_DSYNC_4 0
-#elif CONF_DMAC_TRANS_TYPE_4 == 2
-#define CONF_DMAC_TYPE_4 1
-#define CONF_DMAC_DSYNC_4 1
-#endif
-
-#if CONF_DMAC_TRIGSRC_4 == 0xFF
-#define CONF_DMAC_SWREQ_4 1
-#else
-#define CONF_DMAC_SWREQ_4 0
-#endif
-
-/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
- * or fixed destination address mode, source and destination addresses are incremented
- * by 8-bit or 16-bit.
- * Workaround: The user can fix the problem by setting the source addressing mode to
- * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
- */
-#if (CONF_DMAC_CHANNEL_4_SETTINGS == 1 && CONF_DMAC_BEATSIZE_4 != 2 && ((!CONF_DMAC_SRCINC_4) || (!CONF_DMAC_DSTINC_4)))
-#if (!CONF_DMAC_SRCINC_4)
-#define CONF_DMAC_SRC_STRIDE_4 ((int16_t)(-1))
-#endif
-#if (!CONF_DMAC_DSTINC_4)
-#define CONF_DMAC_DES_STRIDE_4 ((int16_t)(-1))
-#endif
-#endif
-
-#ifndef CONF_DMAC_SRC_STRIDE_4
-#define CONF_DMAC_SRC_STRIDE_4 0
-#endif
-
-#ifndef CONF_DMAC_DES_STRIDE_4
-#define CONF_DMAC_DES_STRIDE_4 0
-#endif
-
-// <e> Channel 5 settings
-// <id> dmac_channel_5_settings
-#ifndef CONF_DMAC_CHANNEL_5_SETTINGS
-#define CONF_DMAC_CHANNEL_5_SETTINGS 0
-#endif
-
-// <o> Burst Size
-// <0x0=> 1 burst size
-// <0x1=> 4 burst size
-// <0x2=> 8 burst size
-// <0x3=> 16 burst size
-// <i> Define the memory burst size
-// <id> dmac_burstsize_5
-#ifndef CONF_DMAC_BURSTSIZE_5
-#define CONF_DMAC_BURSTSIZE_5 0x0
-#endif
-
-// <o> Chunk Size
-// <0x0=> 1 data transferred
-// <0x1=> 2 data transferred
-// <0x2=> 4 data transferred
-// <0x3=> 8 data transferred
-// <0x4=> 16 data transferred
-// <i> Define the peripheral chunk size
-// <id> dmac_chunksize_5
-#ifndef CONF_DMAC_CHUNKSIZE_5
-#define CONF_DMAC_CHUNKSIZE_5 0x0
-#endif
-
-// <o> Beat Size
-// <0=> 8-bit bus transfer
-// <1=> 16-bit bus transfer
-// <2=> 32-bit bus transfer
-// <i> Defines the size of one beat
-// <id> dmac_beatsize_5
-#ifndef CONF_DMAC_BEATSIZE_5
-#define CONF_DMAC_BEATSIZE_5 0x0
-#endif
-
-// <o> Source Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is read through the system bus interface 0 or 1
-// <id> dma_src_interface_5
-#ifndef CONF_DMAC_SRC_INTERFACE_5
-#define CONF_DMAC_SRC_INTERFACE_5 0x0
-#endif
-
-// <o> Destination Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is written through the system bus interface 0 or 1
-// <id> dma_des_interface_5
-#ifndef CONF_DMAC_DES_INTERFACE_5
-#define CONF_DMAC_DES_INTERFACE_5 0x0
-#endif
-
-// <q> Source Address Increment
-// <i> Indicates whether the source address incremented as beat size or not
-// <id> dmac_srcinc_5
-#ifndef CONF_DMAC_SRCINC_5
-#define CONF_DMAC_SRCINC_5 0
-#endif
-
-// <q> Destination Address Increment
-// <i> Indicates whether the destination address incremented as beat size or not
-// <id> dmac_dstinc_5
-#ifndef CONF_DMAC_DSTINC_5
-#define CONF_DMAC_DSTINC_5 0
-#endif
-
-// <o> Transfer Type
-// <0x0=> Memory to Memory Transfer
-// <0x1=> Peripheral to Memory Transfer
-// <0x2=> Memory to Peripheral Transfer
-// <i> Define the data transfer type
-// <id> dma_trans_type_5
-#ifndef CONF_DMAC_TRANS_TYPE_5
-#define CONF_DMAC_TRANS_TYPE_5 0x0
-#endif
-
-// <o> Trigger source
-// <0xFF=> Software Trigger
-// <0x00=> HSMCI TX/RX Trigger
-// <0x01=> SPI0 TX Trigger
-// <0x02=> SPI0 RX Trigger
-// <0x03=> SPI1 TX Trigger
-// <0x04=> SPI1 RX Trigger
-// <0x05=> QSPI TX Trigger
-// <0x06=> QSPI RX Trigger
-// <0x07=> USART0 TX Trigger
-// <0x08=> USART0 RX Trigger
-// <0x09=> USART1 TX Trigger
-// <0x0A=> USART1 RX Trigger
-// <0x0B=> USART2 TX Trigger
-// <0x0C=> USART2 RX Trigger
-// <0x0D=> PWM0 TX Trigger
-// <0x0E=> TWIHS0 TX Trigger
-// <0x0F=> TWIHS0 RX Trigger
-// <0x10=> TWIHS1 TX Trigger
-// <0x11=> TWIHS1 RX Trigger
-// <0x12=> TWIHS2 TX Trigger
-// <0x13=> TWIHS2 RX Trigger
-// <0x14=> UART0 TX Trigger
-// <0x15=> UART0 RX Trigger
-// <0x16=> UART1 TX Trigger
-// <0x17=> UART1 RX Trigger
-// <0x18=> UART2 TX Trigger
-// <0x19=> UART2 RX Trigger
-// <0x1A=> UART3 TX Trigger
-// <0x1B=> UART3 RX Trigger
-// <0x1C=> UART4 TX Trigger
-// <0x1D=> UART4 RX Trigger
-// <0x1E=> DACC TX Trigger
-// <0x20=> SSC TX Trigger
-// <0x21=> SSC RX Trigger
-// <0x22=> PIOA RX Trigger
-// <0x23=> AFEC0 RX Trigger
-// <0x24=> AFEC1 RX Trigger
-// <0x25=> AES TX Trigger
-// <0x26=> AES RX Trigger
-// <0x27=> PWM1 TX Trigger
-// <0x28=> TC0 RX Trigger
-// <0x29=> TC3 RX Trigger
-// <0x2A=> TC6 RX Trigger
-// <0x2B=> TC9 RX Trigger
-// <0x2C=> I2SC0 TX Left Trigger
-// <0x2D=> I2SC0 RX Left Trigger
-// <0x2E=> I2SC1 TX Left Trigger
-// <0x2F=> I2SC1 RX Left Trigger
-// <0x30=> I2SC0 TX Right Trigger
-// <0x31=> I2SC0 RX Right Trigger
-// <0x32=> I2SC1 TX Right Trigger
-// <0x33=> I2SC1 RX Right Trigger
-// <i> Define the DMA trigger source
-// <id> dmac_trifsrc_5
-#ifndef CONF_DMAC_TRIGSRC_5
-#define CONF_DMAC_TRIGSRC_5 0xff
-#endif
-
-// </e>
-
-#if CONF_DMAC_TRANS_TYPE_5 == 0
-#define CONF_DMAC_TYPE_5 0
-#define CONF_DMAC_DSYNC_5 0
-#elif CONF_DMAC_TRANS_TYPE_5 == 1
-#define CONF_DMAC_TYPE_5 1
-#define CONF_DMAC_DSYNC_5 0
-#elif CONF_DMAC_TRANS_TYPE_5 == 2
-#define CONF_DMAC_TYPE_5 1
-#define CONF_DMAC_DSYNC_5 1
-#endif
-
-#if CONF_DMAC_TRIGSRC_5 == 0xFF
-#define CONF_DMAC_SWREQ_5 1
-#else
-#define CONF_DMAC_SWREQ_5 0
-#endif
-
-/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
- * or fixed destination address mode, source and destination addresses are incremented
- * by 8-bit or 16-bit.
- * Workaround: The user can fix the problem by setting the source addressing mode to
- * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
- */
-#if (CONF_DMAC_CHANNEL_5_SETTINGS == 1 && CONF_DMAC_BEATSIZE_5 != 2 && ((!CONF_DMAC_SRCINC_5) || (!CONF_DMAC_DSTINC_5)))
-#if (!CONF_DMAC_SRCINC_5)
-#define CONF_DMAC_SRC_STRIDE_5 ((int16_t)(-1))
-#endif
-#if (!CONF_DMAC_DSTINC_5)
-#define CONF_DMAC_DES_STRIDE_5 ((int16_t)(-1))
-#endif
-#endif
-
-#ifndef CONF_DMAC_SRC_STRIDE_5
-#define CONF_DMAC_SRC_STRIDE_5 0
-#endif
-
-#ifndef CONF_DMAC_DES_STRIDE_5
-#define CONF_DMAC_DES_STRIDE_5 0
-#endif
-
-// <e> Channel 6 settings
-// <id> dmac_channel_6_settings
-#ifndef CONF_DMAC_CHANNEL_6_SETTINGS
-#define CONF_DMAC_CHANNEL_6_SETTINGS 0
-#endif
-
-// <o> Burst Size
-// <0x0=> 1 burst size
-// <0x1=> 4 burst size
-// <0x2=> 8 burst size
-// <0x3=> 16 burst size
-// <i> Define the memory burst size
-// <id> dmac_burstsize_6
-#ifndef CONF_DMAC_BURSTSIZE_6
-#define CONF_DMAC_BURSTSIZE_6 0x0
-#endif
-
-// <o> Chunk Size
-// <0x0=> 1 data transferred
-// <0x1=> 2 data transferred
-// <0x2=> 4 data transferred
-// <0x3=> 8 data transferred
-// <0x4=> 16 data transferred
-// <i> Define the peripheral chunk size
-// <id> dmac_chunksize_6
-#ifndef CONF_DMAC_CHUNKSIZE_6
-#define CONF_DMAC_CHUNKSIZE_6 0x0
-#endif
-
-// <o> Beat Size
-// <0=> 8-bit bus transfer
-// <1=> 16-bit bus transfer
-// <2=> 32-bit bus transfer
-// <i> Defines the size of one beat
-// <id> dmac_beatsize_6
-#ifndef CONF_DMAC_BEATSIZE_6
-#define CONF_DMAC_BEATSIZE_6 0x0
-#endif
-
-// <o> Source Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is read through the system bus interface 0 or 1
-// <id> dma_src_interface_6
-#ifndef CONF_DMAC_SRC_INTERFACE_6
-#define CONF_DMAC_SRC_INTERFACE_6 0x0
-#endif
-
-// <o> Destination Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is written through the system bus interface 0 or 1
-// <id> dma_des_interface_6
-#ifndef CONF_DMAC_DES_INTERFACE_6
-#define CONF_DMAC_DES_INTERFACE_6 0x0
-#endif
-
-// <q> Source Address Increment
-// <i> Indicates whether the source address incremented as beat size or not
-// <id> dmac_srcinc_6
-#ifndef CONF_DMAC_SRCINC_6
-#define CONF_DMAC_SRCINC_6 0
-#endif
-
-// <q> Destination Address Increment
-// <i> Indicates whether the destination address incremented as beat size or not
-// <id> dmac_dstinc_6
-#ifndef CONF_DMAC_DSTINC_6
-#define CONF_DMAC_DSTINC_6 0
-#endif
-
-// <o> Transfer Type
-// <0x0=> Memory to Memory Transfer
-// <0x1=> Peripheral to Memory Transfer
-// <0x2=> Memory to Peripheral Transfer
-// <i> Define the data transfer type
-// <id> dma_trans_type_6
-#ifndef CONF_DMAC_TRANS_TYPE_6
-#define CONF_DMAC_TRANS_TYPE_6 0x0
-#endif
-
-// <o> Trigger source
-// <0xFF=> Software Trigger
-// <0x00=> HSMCI TX/RX Trigger
-// <0x01=> SPI0 TX Trigger
-// <0x02=> SPI0 RX Trigger
-// <0x03=> SPI1 TX Trigger
-// <0x04=> SPI1 RX Trigger
-// <0x05=> QSPI TX Trigger
-// <0x06=> QSPI RX Trigger
-// <0x07=> USART0 TX Trigger
-// <0x08=> USART0 RX Trigger
-// <0x09=> USART1 TX Trigger
-// <0x0A=> USART1 RX Trigger
-// <0x0B=> USART2 TX Trigger
-// <0x0C=> USART2 RX Trigger
-// <0x0D=> PWM0 TX Trigger
-// <0x0E=> TWIHS0 TX Trigger
-// <0x0F=> TWIHS0 RX Trigger
-// <0x10=> TWIHS1 TX Trigger
-// <0x11=> TWIHS1 RX Trigger
-// <0x12=> TWIHS2 TX Trigger
-// <0x13=> TWIHS2 RX Trigger
-// <0x14=> UART0 TX Trigger
-// <0x15=> UART0 RX Trigger
-// <0x16=> UART1 TX Trigger
-// <0x17=> UART1 RX Trigger
-// <0x18=> UART2 TX Trigger
-// <0x19=> UART2 RX Trigger
-// <0x1A=> UART3 TX Trigger
-// <0x1B=> UART3 RX Trigger
-// <0x1C=> UART4 TX Trigger
-// <0x1D=> UART4 RX Trigger
-// <0x1E=> DACC TX Trigger
-// <0x20=> SSC TX Trigger
-// <0x21=> SSC RX Trigger
-// <0x22=> PIOA RX Trigger
-// <0x23=> AFEC0 RX Trigger
-// <0x24=> AFEC1 RX Trigger
-// <0x25=> AES TX Trigger
-// <0x26=> AES RX Trigger
-// <0x27=> PWM1 TX Trigger
-// <0x28=> TC0 RX Trigger
-// <0x29=> TC3 RX Trigger
-// <0x2A=> TC6 RX Trigger
-// <0x2B=> TC9 RX Trigger
-// <0x2C=> I2SC0 TX Left Trigger
-// <0x2D=> I2SC0 RX Left Trigger
-// <0x2E=> I2SC1 TX Left Trigger
-// <0x2F=> I2SC1 RX Left Trigger
-// <0x30=> I2SC0 TX Right Trigger
-// <0x31=> I2SC0 RX Right Trigger
-// <0x32=> I2SC1 TX Right Trigger
-// <0x33=> I2SC1 RX Right Trigger
-// <i> Define the DMA trigger source
-// <id> dmac_trifsrc_6
-#ifndef CONF_DMAC_TRIGSRC_6
-#define CONF_DMAC_TRIGSRC_6 0xff
-#endif
-
-// </e>
-
-#if CONF_DMAC_TRANS_TYPE_6 == 0
-#define CONF_DMAC_TYPE_6 0
-#define CONF_DMAC_DSYNC_6 0
-#elif CONF_DMAC_TRANS_TYPE_6 == 1
-#define CONF_DMAC_TYPE_6 1
-#define CONF_DMAC_DSYNC_6 0
-#elif CONF_DMAC_TRANS_TYPE_6 == 2
-#define CONF_DMAC_TYPE_6 1
-#define CONF_DMAC_DSYNC_6 1
-#endif
-
-#if CONF_DMAC_TRIGSRC_6 == 0xFF
-#define CONF_DMAC_SWREQ_6 1
-#else
-#define CONF_DMAC_SWREQ_6 0
-#endif
-
-/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
- * or fixed destination address mode, source and destination addresses are incremented
- * by 8-bit or 16-bit.
- * Workaround: The user can fix the problem by setting the source addressing mode to
- * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
- */
-#if (CONF_DMAC_CHANNEL_6_SETTINGS == 1 && CONF_DMAC_BEATSIZE_6 != 2 && ((!CONF_DMAC_SRCINC_6) || (!CONF_DMAC_DSTINC_6)))
-#if (!CONF_DMAC_SRCINC_6)
-#define CONF_DMAC_SRC_STRIDE_6 ((int16_t)(-1))
-#endif
-#if (!CONF_DMAC_DSTINC_6)
-#define CONF_DMAC_DES_STRIDE_6 ((int16_t)(-1))
-#endif
-#endif
-
-#ifndef CONF_DMAC_SRC_STRIDE_6
-#define CONF_DMAC_SRC_STRIDE_6 0
-#endif
-
-#ifndef CONF_DMAC_DES_STRIDE_6
-#define CONF_DMAC_DES_STRIDE_6 0
-#endif
-
-// <e> Channel 7 settings
-// <id> dmac_channel_7_settings
-#ifndef CONF_DMAC_CHANNEL_7_SETTINGS
-#define CONF_DMAC_CHANNEL_7_SETTINGS 0
-#endif
-
-// <o> Burst Size
-// <0x0=> 1 burst size
-// <0x1=> 4 burst size
-// <0x2=> 8 burst size
-// <0x3=> 16 burst size
-// <i> Define the memory burst size
-// <id> dmac_burstsize_7
-#ifndef CONF_DMAC_BURSTSIZE_7
-#define CONF_DMAC_BURSTSIZE_7 0x0
-#endif
-
-// <o> Chunk Size
-// <0x0=> 1 data transferred
-// <0x1=> 2 data transferred
-// <0x2=> 4 data transferred
-// <0x3=> 8 data transferred
-// <0x4=> 16 data transferred
-// <i> Define the peripheral chunk size
-// <id> dmac_chunksize_7
-#ifndef CONF_DMAC_CHUNKSIZE_7
-#define CONF_DMAC_CHUNKSIZE_7 0x0
-#endif
-
-// <o> Beat Size
-// <0=> 8-bit bus transfer
-// <1=> 16-bit bus transfer
-// <2=> 32-bit bus transfer
-// <i> Defines the size of one beat
-// <id> dmac_beatsize_7
-#ifndef CONF_DMAC_BEATSIZE_7
-#define CONF_DMAC_BEATSIZE_7 0x0
-#endif
-
-// <o> Source Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is read through the system bus interface 0 or 1
-// <id> dma_src_interface_7
-#ifndef CONF_DMAC_SRC_INTERFACE_7
-#define CONF_DMAC_SRC_INTERFACE_7 0x0
-#endif
-
-// <o> Destination Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is written through the system bus interface 0 or 1
-// <id> dma_des_interface_7
-#ifndef CONF_DMAC_DES_INTERFACE_7
-#define CONF_DMAC_DES_INTERFACE_7 0x0
-#endif
-
-// <q> Source Address Increment
-// <i> Indicates whether the source address incremented as beat size or not
-// <id> dmac_srcinc_7
-#ifndef CONF_DMAC_SRCINC_7
-#define CONF_DMAC_SRCINC_7 0
-#endif
-
-// <q> Destination Address Increment
-// <i> Indicates whether the destination address incremented as beat size or not
-// <id> dmac_dstinc_7
-#ifndef CONF_DMAC_DSTINC_7
-#define CONF_DMAC_DSTINC_7 0
-#endif
-
-// <o> Transfer Type
-// <0x0=> Memory to Memory Transfer
-// <0x1=> Peripheral to Memory Transfer
-// <0x2=> Memory to Peripheral Transfer
-// <i> Define the data transfer type
-// <id> dma_trans_type_7
-#ifndef CONF_DMAC_TRANS_TYPE_7
-#define CONF_DMAC_TRANS_TYPE_7 0x0
-#endif
-
-// <o> Trigger source
-// <0xFF=> Software Trigger
-// <0x00=> HSMCI TX/RX Trigger
-// <0x01=> SPI0 TX Trigger
-// <0x02=> SPI0 RX Trigger
-// <0x03=> SPI1 TX Trigger
-// <0x04=> SPI1 RX Trigger
-// <0x05=> QSPI TX Trigger
-// <0x06=> QSPI RX Trigger
-// <0x07=> USART0 TX Trigger
-// <0x08=> USART0 RX Trigger
-// <0x09=> USART1 TX Trigger
-// <0x0A=> USART1 RX Trigger
-// <0x0B=> USART2 TX Trigger
-// <0x0C=> USART2 RX Trigger
-// <0x0D=> PWM0 TX Trigger
-// <0x0E=> TWIHS0 TX Trigger
-// <0x0F=> TWIHS0 RX Trigger
-// <0x10=> TWIHS1 TX Trigger
-// <0x11=> TWIHS1 RX Trigger
-// <0x12=> TWIHS2 TX Trigger
-// <0x13=> TWIHS2 RX Trigger
-// <0x14=> UART0 TX Trigger
-// <0x15=> UART0 RX Trigger
-// <0x16=> UART1 TX Trigger
-// <0x17=> UART1 RX Trigger
-// <0x18=> UART2 TX Trigger
-// <0x19=> UART2 RX Trigger
-// <0x1A=> UART3 TX Trigger
-// <0x1B=> UART3 RX Trigger
-// <0x1C=> UART4 TX Trigger
-// <0x1D=> UART4 RX Trigger
-// <0x1E=> DACC TX Trigger
-// <0x20=> SSC TX Trigger
-// <0x21=> SSC RX Trigger
-// <0x22=> PIOA RX Trigger
-// <0x23=> AFEC0 RX Trigger
-// <0x24=> AFEC1 RX Trigger
-// <0x25=> AES TX Trigger
-// <0x26=> AES RX Trigger
-// <0x27=> PWM1 TX Trigger
-// <0x28=> TC0 RX Trigger
-// <0x29=> TC3 RX Trigger
-// <0x2A=> TC6 RX Trigger
-// <0x2B=> TC9 RX Trigger
-// <0x2C=> I2SC0 TX Left Trigger
-// <0x2D=> I2SC0 RX Left Trigger
-// <0x2E=> I2SC1 TX Left Trigger
-// <0x2F=> I2SC1 RX Left Trigger
-// <0x30=> I2SC0 TX Right Trigger
-// <0x31=> I2SC0 RX Right Trigger
-// <0x32=> I2SC1 TX Right Trigger
-// <0x33=> I2SC1 RX Right Trigger
-// <i> Define the DMA trigger source
-// <id> dmac_trifsrc_7
-#ifndef CONF_DMAC_TRIGSRC_7
-#define CONF_DMAC_TRIGSRC_7 0xff
-#endif
-
-// </e>
-
-#if CONF_DMAC_TRANS_TYPE_7 == 0
-#define CONF_DMAC_TYPE_7 0
-#define CONF_DMAC_DSYNC_7 0
-#elif CONF_DMAC_TRANS_TYPE_7 == 1
-#define CONF_DMAC_TYPE_7 1
-#define CONF_DMAC_DSYNC_7 0
-#elif CONF_DMAC_TRANS_TYPE_7 == 2
-#define CONF_DMAC_TYPE_7 1
-#define CONF_DMAC_DSYNC_7 1
-#endif
-
-#if CONF_DMAC_TRIGSRC_7 == 0xFF
-#define CONF_DMAC_SWREQ_7 1
-#else
-#define CONF_DMAC_SWREQ_7 0
-#endif
-
-/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
- * or fixed destination address mode, source and destination addresses are incremented
- * by 8-bit or 16-bit.
- * Workaround: The user can fix the problem by setting the source addressing mode to
- * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
- */
-#if (CONF_DMAC_CHANNEL_7_SETTINGS == 1 && CONF_DMAC_BEATSIZE_7 != 2 && ((!CONF_DMAC_SRCINC_7) || (!CONF_DMAC_DSTINC_7)))
-#if (!CONF_DMAC_SRCINC_7)
-#define CONF_DMAC_SRC_STRIDE_7 ((int16_t)(-1))
-#endif
-#if (!CONF_DMAC_DSTINC_7)
-#define CONF_DMAC_DES_STRIDE_7 ((int16_t)(-1))
-#endif
-#endif
-
-#ifndef CONF_DMAC_SRC_STRIDE_7
-#define CONF_DMAC_SRC_STRIDE_7 0
-#endif
-
-#ifndef CONF_DMAC_DES_STRIDE_7
-#define CONF_DMAC_DES_STRIDE_7 0
-#endif
-
-// <e> Channel 8 settings
-// <id> dmac_channel_8_settings
-#ifndef CONF_DMAC_CHANNEL_8_SETTINGS
-#define CONF_DMAC_CHANNEL_8_SETTINGS 0
-#endif
-
-// <o> Burst Size
-// <0x0=> 1 burst size
-// <0x1=> 4 burst size
-// <0x2=> 8 burst size
-// <0x3=> 16 burst size
-// <i> Define the memory burst size
-// <id> dmac_burstsize_8
-#ifndef CONF_DMAC_BURSTSIZE_8
-#define CONF_DMAC_BURSTSIZE_8 0x0
-#endif
-
-// <o> Chunk Size
-// <0x0=> 1 data transferred
-// <0x1=> 2 data transferred
-// <0x2=> 4 data transferred
-// <0x3=> 8 data transferred
-// <0x4=> 16 data transferred
-// <i> Define the peripheral chunk size
-// <id> dmac_chunksize_8
-#ifndef CONF_DMAC_CHUNKSIZE_8
-#define CONF_DMAC_CHUNKSIZE_8 0x0
-#endif
-
-// <o> Beat Size
-// <0=> 8-bit bus transfer
-// <1=> 16-bit bus transfer
-// <2=> 32-bit bus transfer
-// <i> Defines the size of one beat
-// <id> dmac_beatsize_8
-#ifndef CONF_DMAC_BEATSIZE_8
-#define CONF_DMAC_BEATSIZE_8 0x0
-#endif
-
-// <o> Source Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is read through the system bus interface 0 or 1
-// <id> dma_src_interface_8
-#ifndef CONF_DMAC_SRC_INTERFACE_8
-#define CONF_DMAC_SRC_INTERFACE_8 0x0
-#endif
-
-// <o> Destination Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is written through the system bus interface 0 or 1
-// <id> dma_des_interface_8
-#ifndef CONF_DMAC_DES_INTERFACE_8
-#define CONF_DMAC_DES_INTERFACE_8 0x0
-#endif
-
-// <q> Source Address Increment
-// <i> Indicates whether the source address incremented as beat size or not
-// <id> dmac_srcinc_8
-#ifndef CONF_DMAC_SRCINC_8
-#define CONF_DMAC_SRCINC_8 0
-#endif
-
-// <q> Destination Address Increment
-// <i> Indicates whether the destination address incremented as beat size or not
-// <id> dmac_dstinc_8
-#ifndef CONF_DMAC_DSTINC_8
-#define CONF_DMAC_DSTINC_8 0
-#endif
-
-// <o> Transfer Type
-// <0x0=> Memory to Memory Transfer
-// <0x1=> Peripheral to Memory Transfer
-// <0x2=> Memory to Peripheral Transfer
-// <i> Define the data transfer type
-// <id> dma_trans_type_8
-#ifndef CONF_DMAC_TRANS_TYPE_8
-#define CONF_DMAC_TRANS_TYPE_8 0x0
-#endif
-
-// <o> Trigger source
-// <0xFF=> Software Trigger
-// <0x00=> HSMCI TX/RX Trigger
-// <0x01=> SPI0 TX Trigger
-// <0x02=> SPI0 RX Trigger
-// <0x03=> SPI1 TX Trigger
-// <0x04=> SPI1 RX Trigger
-// <0x05=> QSPI TX Trigger
-// <0x06=> QSPI RX Trigger
-// <0x07=> USART0 TX Trigger
-// <0x08=> USART0 RX Trigger
-// <0x09=> USART1 TX Trigger
-// <0x0A=> USART1 RX Trigger
-// <0x0B=> USART2 TX Trigger
-// <0x0C=> USART2 RX Trigger
-// <0x0D=> PWM0 TX Trigger
-// <0x0E=> TWIHS0 TX Trigger
-// <0x0F=> TWIHS0 RX Trigger
-// <0x10=> TWIHS1 TX Trigger
-// <0x11=> TWIHS1 RX Trigger
-// <0x12=> TWIHS2 TX Trigger
-// <0x13=> TWIHS2 RX Trigger
-// <0x14=> UART0 TX Trigger
-// <0x15=> UART0 RX Trigger
-// <0x16=> UART1 TX Trigger
-// <0x17=> UART1 RX Trigger
-// <0x18=> UART2 TX Trigger
-// <0x19=> UART2 RX Trigger
-// <0x1A=> UART3 TX Trigger
-// <0x1B=> UART3 RX Trigger
-// <0x1C=> UART4 TX Trigger
-// <0x1D=> UART4 RX Trigger
-// <0x1E=> DACC TX Trigger
-// <0x20=> SSC TX Trigger
-// <0x21=> SSC RX Trigger
-// <0x22=> PIOA RX Trigger
-// <0x23=> AFEC0 RX Trigger
-// <0x24=> AFEC1 RX Trigger
-// <0x25=> AES TX Trigger
-// <0x26=> AES RX Trigger
-// <0x27=> PWM1 TX Trigger
-// <0x28=> TC0 RX Trigger
-// <0x29=> TC3 RX Trigger
-// <0x2A=> TC6 RX Trigger
-// <0x2B=> TC9 RX Trigger
-// <0x2C=> I2SC0 TX Left Trigger
-// <0x2D=> I2SC0 RX Left Trigger
-// <0x2E=> I2SC1 TX Left Trigger
-// <0x2F=> I2SC1 RX Left Trigger
-// <0x30=> I2SC0 TX Right Trigger
-// <0x31=> I2SC0 RX Right Trigger
-// <0x32=> I2SC1 TX Right Trigger
-// <0x33=> I2SC1 RX Right Trigger
-// <i> Define the DMA trigger source
-// <id> dmac_trifsrc_8
-#ifndef CONF_DMAC_TRIGSRC_8
-#define CONF_DMAC_TRIGSRC_8 0xff
-#endif
-
-// </e>
-
-#if CONF_DMAC_TRANS_TYPE_8 == 0
-#define CONF_DMAC_TYPE_8 0
-#define CONF_DMAC_DSYNC_8 0
-#elif CONF_DMAC_TRANS_TYPE_8 == 1
-#define CONF_DMAC_TYPE_8 1
-#define CONF_DMAC_DSYNC_8 0
-#elif CONF_DMAC_TRANS_TYPE_8 == 2
-#define CONF_DMAC_TYPE_8 1
-#define CONF_DMAC_DSYNC_8 1
-#endif
-
-#if CONF_DMAC_TRIGSRC_8 == 0xFF
-#define CONF_DMAC_SWREQ_8 1
-#else
-#define CONF_DMAC_SWREQ_8 0
-#endif
-
-/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
- * or fixed destination address mode, source and destination addresses are incremented
- * by 8-bit or 16-bit.
- * Workaround: The user can fix the problem by setting the source addressing mode to
- * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
- */
-#if (CONF_DMAC_CHANNEL_8_SETTINGS == 1 && CONF_DMAC_BEATSIZE_8 != 2 && ((!CONF_DMAC_SRCINC_8) || (!CONF_DMAC_DSTINC_8)))
-#if (!CONF_DMAC_SRCINC_8)
-#define CONF_DMAC_SRC_STRIDE_8 ((int16_t)(-1))
-#endif
-#if (!CONF_DMAC_DSTINC_8)
-#define CONF_DMAC_DES_STRIDE_8 ((int16_t)(-1))
-#endif
-#endif
-
-#ifndef CONF_DMAC_SRC_STRIDE_8
-#define CONF_DMAC_SRC_STRIDE_8 0
-#endif
-
-#ifndef CONF_DMAC_DES_STRIDE_8
-#define CONF_DMAC_DES_STRIDE_8 0
-#endif
-
-// <e> Channel 9 settings
-// <id> dmac_channel_9_settings
-#ifndef CONF_DMAC_CHANNEL_9_SETTINGS
-#define CONF_DMAC_CHANNEL_9_SETTINGS 0
-#endif
-
-// <o> Burst Size
-// <0x0=> 1 burst size
-// <0x1=> 4 burst size
-// <0x2=> 8 burst size
-// <0x3=> 16 burst size
-// <i> Define the memory burst size
-// <id> dmac_burstsize_9
-#ifndef CONF_DMAC_BURSTSIZE_9
-#define CONF_DMAC_BURSTSIZE_9 0x0
-#endif
-
-// <o> Chunk Size
-// <0x0=> 1 data transferred
-// <0x1=> 2 data transferred
-// <0x2=> 4 data transferred
-// <0x3=> 8 data transferred
-// <0x4=> 16 data transferred
-// <i> Define the peripheral chunk size
-// <id> dmac_chunksize_9
-#ifndef CONF_DMAC_CHUNKSIZE_9
-#define CONF_DMAC_CHUNKSIZE_9 0x0
-#endif
-
-// <o> Beat Size
-// <0=> 8-bit bus transfer
-// <1=> 16-bit bus transfer
-// <2=> 32-bit bus transfer
-// <i> Defines the size of one beat
-// <id> dmac_beatsize_9
-#ifndef CONF_DMAC_BEATSIZE_9
-#define CONF_DMAC_BEATSIZE_9 0x0
-#endif
-
-// <o> Source Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is read through the system bus interface 0 or 1
-// <id> dma_src_interface_9
-#ifndef CONF_DMAC_SRC_INTERFACE_9
-#define CONF_DMAC_SRC_INTERFACE_9 0x0
-#endif
-
-// <o> Destination Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is written through the system bus interface 0 or 1
-// <id> dma_des_interface_9
-#ifndef CONF_DMAC_DES_INTERFACE_9
-#define CONF_DMAC_DES_INTERFACE_9 0x0
-#endif
-
-// <q> Source Address Increment
-// <i> Indicates whether the source address incremented as beat size or not
-// <id> dmac_srcinc_9
-#ifndef CONF_DMAC_SRCINC_9
-#define CONF_DMAC_SRCINC_9 0
-#endif
-
-// <q> Destination Address Increment
-// <i> Indicates whether the destination address incremented as beat size or not
-// <id> dmac_dstinc_9
-#ifndef CONF_DMAC_DSTINC_9
-#define CONF_DMAC_DSTINC_9 0
-#endif
-
-// <o> Transfer Type
-// <0x0=> Memory to Memory Transfer
-// <0x1=> Peripheral to Memory Transfer
-// <0x2=> Memory to Peripheral Transfer
-// <i> Define the data transfer type
-// <id> dma_trans_type_9
-#ifndef CONF_DMAC_TRANS_TYPE_9
-#define CONF_DMAC_TRANS_TYPE_9 0x0
-#endif
-
-// <o> Trigger source
-// <0xFF=> Software Trigger
-// <0x00=> HSMCI TX/RX Trigger
-// <0x01=> SPI0 TX Trigger
-// <0x02=> SPI0 RX Trigger
-// <0x03=> SPI1 TX Trigger
-// <0x04=> SPI1 RX Trigger
-// <0x05=> QSPI TX Trigger
-// <0x06=> QSPI RX Trigger
-// <0x07=> USART0 TX Trigger
-// <0x08=> USART0 RX Trigger
-// <0x09=> USART1 TX Trigger
-// <0x0A=> USART1 RX Trigger
-// <0x0B=> USART2 TX Trigger
-// <0x0C=> USART2 RX Trigger
-// <0x0D=> PWM0 TX Trigger
-// <0x0E=> TWIHS0 TX Trigger
-// <0x0F=> TWIHS0 RX Trigger
-// <0x10=> TWIHS1 TX Trigger
-// <0x11=> TWIHS1 RX Trigger
-// <0x12=> TWIHS2 TX Trigger
-// <0x13=> TWIHS2 RX Trigger
-// <0x14=> UART0 TX Trigger
-// <0x15=> UART0 RX Trigger
-// <0x16=> UART1 TX Trigger
-// <0x17=> UART1 RX Trigger
-// <0x18=> UART2 TX Trigger
-// <0x19=> UART2 RX Trigger
-// <0x1A=> UART3 TX Trigger
-// <0x1B=> UART3 RX Trigger
-// <0x1C=> UART4 TX Trigger
-// <0x1D=> UART4 RX Trigger
-// <0x1E=> DACC TX Trigger
-// <0x20=> SSC TX Trigger
-// <0x21=> SSC RX Trigger
-// <0x22=> PIOA RX Trigger
-// <0x23=> AFEC0 RX Trigger
-// <0x24=> AFEC1 RX Trigger
-// <0x25=> AES TX Trigger
-// <0x26=> AES RX Trigger
-// <0x27=> PWM1 TX Trigger
-// <0x28=> TC0 RX Trigger
-// <0x29=> TC3 RX Trigger
-// <0x2A=> TC6 RX Trigger
-// <0x2B=> TC9 RX Trigger
-// <0x2C=> I2SC0 TX Left Trigger
-// <0x2D=> I2SC0 RX Left Trigger
-// <0x2E=> I2SC1 TX Left Trigger
-// <0x2F=> I2SC1 RX Left Trigger
-// <0x30=> I2SC0 TX Right Trigger
-// <0x31=> I2SC0 RX Right Trigger
-// <0x32=> I2SC1 TX Right Trigger
-// <0x33=> I2SC1 RX Right Trigger
-// <i> Define the DMA trigger source
-// <id> dmac_trifsrc_9
-#ifndef CONF_DMAC_TRIGSRC_9
-#define CONF_DMAC_TRIGSRC_9 0xff
-#endif
-
-// </e>
-
-#if CONF_DMAC_TRANS_TYPE_9 == 0
-#define CONF_DMAC_TYPE_9 0
-#define CONF_DMAC_DSYNC_9 0
-#elif CONF_DMAC_TRANS_TYPE_9 == 1
-#define CONF_DMAC_TYPE_9 1
-#define CONF_DMAC_DSYNC_9 0
-#elif CONF_DMAC_TRANS_TYPE_9 == 2
-#define CONF_DMAC_TYPE_9 1
-#define CONF_DMAC_DSYNC_9 1
-#endif
-
-#if CONF_DMAC_TRIGSRC_9 == 0xFF
-#define CONF_DMAC_SWREQ_9 1
-#else
-#define CONF_DMAC_SWREQ_9 0
-#endif
-
-/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
- * or fixed destination address mode, source and destination addresses are incremented
- * by 8-bit or 16-bit.
- * Workaround: The user can fix the problem by setting the source addressing mode to
- * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
- */
-#if (CONF_DMAC_CHANNEL_9_SETTINGS == 1 && CONF_DMAC_BEATSIZE_9 != 2 && ((!CONF_DMAC_SRCINC_9) || (!CONF_DMAC_DSTINC_9)))
-#if (!CONF_DMAC_SRCINC_9)
-#define CONF_DMAC_SRC_STRIDE_9 ((int16_t)(-1))
-#endif
-#if (!CONF_DMAC_DSTINC_9)
-#define CONF_DMAC_DES_STRIDE_9 ((int16_t)(-1))
-#endif
-#endif
-
-#ifndef CONF_DMAC_SRC_STRIDE_9
-#define CONF_DMAC_SRC_STRIDE_9 0
-#endif
-
-#ifndef CONF_DMAC_DES_STRIDE_9
-#define CONF_DMAC_DES_STRIDE_9 0
-#endif
-
-// <e> Channel 10 settings
-// <id> dmac_channel_10_settings
-#ifndef CONF_DMAC_CHANNEL_10_SETTINGS
-#define CONF_DMAC_CHANNEL_10_SETTINGS 0
-#endif
-
-// <o> Burst Size
-// <0x0=> 1 burst size
-// <0x1=> 4 burst size
-// <0x2=> 8 burst size
-// <0x3=> 16 burst size
-// <i> Define the memory burst size
-// <id> dmac_burstsize_10
-#ifndef CONF_DMAC_BURSTSIZE_10
-#define CONF_DMAC_BURSTSIZE_10 0x0
-#endif
-
-// <o> Chunk Size
-// <0x0=> 1 data transferred
-// <0x1=> 2 data transferred
-// <0x2=> 4 data transferred
-// <0x3=> 8 data transferred
-// <0x4=> 16 data transferred
-// <i> Define the peripheral chunk size
-// <id> dmac_chunksize_10
-#ifndef CONF_DMAC_CHUNKSIZE_10
-#define CONF_DMAC_CHUNKSIZE_10 0x0
-#endif
-
-// <o> Beat Size
-// <0=> 8-bit bus transfer
-// <1=> 16-bit bus transfer
-// <2=> 32-bit bus transfer
-// <i> Defines the size of one beat
-// <id> dmac_beatsize_10
-#ifndef CONF_DMAC_BEATSIZE_10
-#define CONF_DMAC_BEATSIZE_10 0x0
-#endif
-
-// <o> Source Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is read through the system bus interface 0 or 1
-// <id> dma_src_interface_10
-#ifndef CONF_DMAC_SRC_INTERFACE_10
-#define CONF_DMAC_SRC_INTERFACE_10 0x0
-#endif
-
-// <o> Destination Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is written through the system bus interface 0 or 1
-// <id> dma_des_interface_10
-#ifndef CONF_DMAC_DES_INTERFACE_10
-#define CONF_DMAC_DES_INTERFACE_10 0x0
-#endif
-
-// <q> Source Address Increment
-// <i> Indicates whether the source address incremented as beat size or not
-// <id> dmac_srcinc_10
-#ifndef CONF_DMAC_SRCINC_10
-#define CONF_DMAC_SRCINC_10 0
-#endif
-
-// <q> Destination Address Increment
-// <i> Indicates whether the destination address incremented as beat size or not
-// <id> dmac_dstinc_10
-#ifndef CONF_DMAC_DSTINC_10
-#define CONF_DMAC_DSTINC_10 0
-#endif
-
-// <o> Transfer Type
-// <0x0=> Memory to Memory Transfer
-// <0x1=> Peripheral to Memory Transfer
-// <0x2=> Memory to Peripheral Transfer
-// <i> Define the data transfer type
-// <id> dma_trans_type_10
-#ifndef CONF_DMAC_TRANS_TYPE_10
-#define CONF_DMAC_TRANS_TYPE_10 0x0
-#endif
-
-// <o> Trigger source
-// <0xFF=> Software Trigger
-// <0x00=> HSMCI TX/RX Trigger
-// <0x01=> SPI0 TX Trigger
-// <0x02=> SPI0 RX Trigger
-// <0x03=> SPI1 TX Trigger
-// <0x04=> SPI1 RX Trigger
-// <0x05=> QSPI TX Trigger
-// <0x06=> QSPI RX Trigger
-// <0x07=> USART0 TX Trigger
-// <0x08=> USART0 RX Trigger
-// <0x09=> USART1 TX Trigger
-// <0x0A=> USART1 RX Trigger
-// <0x0B=> USART2 TX Trigger
-// <0x0C=> USART2 RX Trigger
-// <0x0D=> PWM0 TX Trigger
-// <0x0E=> TWIHS0 TX Trigger
-// <0x0F=> TWIHS0 RX Trigger
-// <0x10=> TWIHS1 TX Trigger
-// <0x11=> TWIHS1 RX Trigger
-// <0x12=> TWIHS2 TX Trigger
-// <0x13=> TWIHS2 RX Trigger
-// <0x14=> UART0 TX Trigger
-// <0x15=> UART0 RX Trigger
-// <0x16=> UART1 TX Trigger
-// <0x17=> UART1 RX Trigger
-// <0x18=> UART2 TX Trigger
-// <0x19=> UART2 RX Trigger
-// <0x1A=> UART3 TX Trigger
-// <0x1B=> UART3 RX Trigger
-// <0x1C=> UART4 TX Trigger
-// <0x1D=> UART4 RX Trigger
-// <0x1E=> DACC TX Trigger
-// <0x20=> SSC TX Trigger
-// <0x21=> SSC RX Trigger
-// <0x22=> PIOA RX Trigger
-// <0x23=> AFEC0 RX Trigger
-// <0x24=> AFEC1 RX Trigger
-// <0x25=> AES TX Trigger
-// <0x26=> AES RX Trigger
-// <0x27=> PWM1 TX Trigger
-// <0x28=> TC0 RX Trigger
-// <0x29=> TC3 RX Trigger
-// <0x2A=> TC6 RX Trigger
-// <0x2B=> TC9 RX Trigger
-// <0x2C=> I2SC0 TX Left Trigger
-// <0x2D=> I2SC0 RX Left Trigger
-// <0x2E=> I2SC1 TX Left Trigger
-// <0x2F=> I2SC1 RX Left Trigger
-// <0x30=> I2SC0 TX Right Trigger
-// <0x31=> I2SC0 RX Right Trigger
-// <0x32=> I2SC1 TX Right Trigger
-// <0x33=> I2SC1 RX Right Trigger
-// <i> Define the DMA trigger source
-// <id> dmac_trifsrc_10
-#ifndef CONF_DMAC_TRIGSRC_10
-#define CONF_DMAC_TRIGSRC_10 0xff
-#endif
-
-// </e>
-
-#if CONF_DMAC_TRANS_TYPE_10 == 0
-#define CONF_DMAC_TYPE_10 0
-#define CONF_DMAC_DSYNC_10 0
-#elif CONF_DMAC_TRANS_TYPE_10 == 1
-#define CONF_DMAC_TYPE_10 1
-#define CONF_DMAC_DSYNC_10 0
-#elif CONF_DMAC_TRANS_TYPE_10 == 2
-#define CONF_DMAC_TYPE_10 1
-#define CONF_DMAC_DSYNC_10 1
-#endif
-
-#if CONF_DMAC_TRIGSRC_10 == 0xFF
-#define CONF_DMAC_SWREQ_10 1
-#else
-#define CONF_DMAC_SWREQ_10 0
-#endif
-
-/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
- * or fixed destination address mode, source and destination addresses are incremented
- * by 8-bit or 16-bit.
- * Workaround: The user can fix the problem by setting the source addressing mode to
- * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
- */
-#if (CONF_DMAC_CHANNEL_10_SETTINGS == 1 && CONF_DMAC_BEATSIZE_10 != 2                                                  \
-     && ((!CONF_DMAC_SRCINC_10) || (!CONF_DMAC_DSTINC_10)))
-#if (!CONF_DMAC_SRCINC_10)
-#define CONF_DMAC_SRC_STRIDE_10 ((int16_t)(-1))
-#endif
-#if (!CONF_DMAC_DSTINC_10)
-#define CONF_DMAC_DES_STRIDE_10 ((int16_t)(-1))
-#endif
-#endif
-
-#ifndef CONF_DMAC_SRC_STRIDE_10
-#define CONF_DMAC_SRC_STRIDE_10 0
-#endif
-
-#ifndef CONF_DMAC_DES_STRIDE_10
-#define CONF_DMAC_DES_STRIDE_10 0
-#endif
-
-// <e> Channel 11 settings
-// <id> dmac_channel_11_settings
-#ifndef CONF_DMAC_CHANNEL_11_SETTINGS
-#define CONF_DMAC_CHANNEL_11_SETTINGS 0
-#endif
-
-// <o> Burst Size
-// <0x0=> 1 burst size
-// <0x1=> 4 burst size
-// <0x2=> 8 burst size
-// <0x3=> 16 burst size
-// <i> Define the memory burst size
-// <id> dmac_burstsize_11
-#ifndef CONF_DMAC_BURSTSIZE_11
-#define CONF_DMAC_BURSTSIZE_11 0x0
-#endif
-
-// <o> Chunk Size
-// <0x0=> 1 data transferred
-// <0x1=> 2 data transferred
-// <0x2=> 4 data transferred
-// <0x3=> 8 data transferred
-// <0x4=> 16 data transferred
-// <i> Define the peripheral chunk size
-// <id> dmac_chunksize_11
-#ifndef CONF_DMAC_CHUNKSIZE_11
-#define CONF_DMAC_CHUNKSIZE_11 0x0
-#endif
-
-// <o> Beat Size
-// <0=> 8-bit bus transfer
-// <1=> 16-bit bus transfer
-// <2=> 32-bit bus transfer
-// <i> Defines the size of one beat
-// <id> dmac_beatsize_11
-#ifndef CONF_DMAC_BEATSIZE_11
-#define CONF_DMAC_BEATSIZE_11 0x0
-#endif
-
-// <o> Source Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is read through the system bus interface 0 or 1
-// <id> dma_src_interface_11
-#ifndef CONF_DMAC_SRC_INTERFACE_11
-#define CONF_DMAC_SRC_INTERFACE_11 0x0
-#endif
-
-// <o> Destination Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is written through the system bus interface 0 or 1
-// <id> dma_des_interface_11
-#ifndef CONF_DMAC_DES_INTERFACE_11
-#define CONF_DMAC_DES_INTERFACE_11 0x0
-#endif
-
-// <q> Source Address Increment
-// <i> Indicates whether the source address incremented as beat size or not
-// <id> dmac_srcinc_11
-#ifndef CONF_DMAC_SRCINC_11
-#define CONF_DMAC_SRCINC_11 0
-#endif
-
-// <q> Destination Address Increment
-// <i> Indicates whether the destination address incremented as beat size or not
-// <id> dmac_dstinc_11
-#ifndef CONF_DMAC_DSTINC_11
-#define CONF_DMAC_DSTINC_11 0
-#endif
-
-// <o> Transfer Type
-// <0x0=> Memory to Memory Transfer
-// <0x1=> Peripheral to Memory Transfer
-// <0x2=> Memory to Peripheral Transfer
-// <i> Define the data transfer type
-// <id> dma_trans_type_11
-#ifndef CONF_DMAC_TRANS_TYPE_11
-#define CONF_DMAC_TRANS_TYPE_11 0x0
-#endif
-
-// <o> Trigger source
-// <0xFF=> Software Trigger
-// <0x00=> HSMCI TX/RX Trigger
-// <0x01=> SPI0 TX Trigger
-// <0x02=> SPI0 RX Trigger
-// <0x03=> SPI1 TX Trigger
-// <0x04=> SPI1 RX Trigger
-// <0x05=> QSPI TX Trigger
-// <0x06=> QSPI RX Trigger
-// <0x07=> USART0 TX Trigger
-// <0x08=> USART0 RX Trigger
-// <0x09=> USART1 TX Trigger
-// <0x0A=> USART1 RX Trigger
-// <0x0B=> USART2 TX Trigger
-// <0x0C=> USART2 RX Trigger
-// <0x0D=> PWM0 TX Trigger
-// <0x0E=> TWIHS0 TX Trigger
-// <0x0F=> TWIHS0 RX Trigger
-// <0x10=> TWIHS1 TX Trigger
-// <0x11=> TWIHS1 RX Trigger
-// <0x12=> TWIHS2 TX Trigger
-// <0x13=> TWIHS2 RX Trigger
-// <0x14=> UART0 TX Trigger
-// <0x15=> UART0 RX Trigger
-// <0x16=> UART1 TX Trigger
-// <0x17=> UART1 RX Trigger
-// <0x18=> UART2 TX Trigger
-// <0x19=> UART2 RX Trigger
-// <0x1A=> UART3 TX Trigger
-// <0x1B=> UART3 RX Trigger
-// <0x1C=> UART4 TX Trigger
-// <0x1D=> UART4 RX Trigger
-// <0x1E=> DACC TX Trigger
-// <0x20=> SSC TX Trigger
-// <0x21=> SSC RX Trigger
-// <0x22=> PIOA RX Trigger
-// <0x23=> AFEC0 RX Trigger
-// <0x24=> AFEC1 RX Trigger
-// <0x25=> AES TX Trigger
-// <0x26=> AES RX Trigger
-// <0x27=> PWM1 TX Trigger
-// <0x28=> TC0 RX Trigger
-// <0x29=> TC3 RX Trigger
-// <0x2A=> TC6 RX Trigger
-// <0x2B=> TC9 RX Trigger
-// <0x2C=> I2SC0 TX Left Trigger
-// <0x2D=> I2SC0 RX Left Trigger
-// <0x2E=> I2SC1 TX Left Trigger
-// <0x2F=> I2SC1 RX Left Trigger
-// <0x30=> I2SC0 TX Right Trigger
-// <0x31=> I2SC0 RX Right Trigger
-// <0x32=> I2SC1 TX Right Trigger
-// <0x33=> I2SC1 RX Right Trigger
-// <i> Define the DMA trigger source
-// <id> dmac_trifsrc_11
-#ifndef CONF_DMAC_TRIGSRC_11
-#define CONF_DMAC_TRIGSRC_11 0xff
-#endif
-
-// </e>
-
-#if CONF_DMAC_TRANS_TYPE_11 == 0
-#define CONF_DMAC_TYPE_11 0
-#define CONF_DMAC_DSYNC_11 0
-#elif CONF_DMAC_TRANS_TYPE_11 == 1
-#define CONF_DMAC_TYPE_11 1
-#define CONF_DMAC_DSYNC_11 0
-#elif CONF_DMAC_TRANS_TYPE_11 == 2
-#define CONF_DMAC_TYPE_11 1
-#define CONF_DMAC_DSYNC_11 1
-#endif
-
-#if CONF_DMAC_TRIGSRC_11 == 0xFF
-#define CONF_DMAC_SWREQ_11 1
-#else
-#define CONF_DMAC_SWREQ_11 0
-#endif
-
-/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
- * or fixed destination address mode, source and destination addresses are incremented
- * by 8-bit or 16-bit.
- * Workaround: The user can fix the problem by setting the source addressing mode to
- * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
- */
-#if (CONF_DMAC_CHANNEL_11_SETTINGS == 1 && CONF_DMAC_BEATSIZE_11 != 2                                                  \
-     && ((!CONF_DMAC_SRCINC_11) || (!CONF_DMAC_DSTINC_11)))
-#if (!CONF_DMAC_SRCINC_11)
-#define CONF_DMAC_SRC_STRIDE_11 ((int16_t)(-1))
-#endif
-#if (!CONF_DMAC_DSTINC_11)
-#define CONF_DMAC_DES_STRIDE_11 ((int16_t)(-1))
-#endif
-#endif
-
-#ifndef CONF_DMAC_SRC_STRIDE_11
-#define CONF_DMAC_SRC_STRIDE_11 0
-#endif
-
-#ifndef CONF_DMAC_DES_STRIDE_11
-#define CONF_DMAC_DES_STRIDE_11 0
-#endif
-
-// <e> Channel 12 settings
-// <id> dmac_channel_12_settings
-#ifndef CONF_DMAC_CHANNEL_12_SETTINGS
-#define CONF_DMAC_CHANNEL_12_SETTINGS 0
-#endif
-
-// <o> Burst Size
-// <0x0=> 1 burst size
-// <0x1=> 4 burst size
-// <0x2=> 8 burst size
-// <0x3=> 16 burst size
-// <i> Define the memory burst size
-// <id> dmac_burstsize_12
-#ifndef CONF_DMAC_BURSTSIZE_12
-#define CONF_DMAC_BURSTSIZE_12 0x0
-#endif
-
-// <o> Chunk Size
-// <0x0=> 1 data transferred
-// <0x1=> 2 data transferred
-// <0x2=> 4 data transferred
-// <0x3=> 8 data transferred
-// <0x4=> 16 data transferred
-// <i> Define the peripheral chunk size
-// <id> dmac_chunksize_12
-#ifndef CONF_DMAC_CHUNKSIZE_12
-#define CONF_DMAC_CHUNKSIZE_12 0x0
-#endif
-
-// <o> Beat Size
-// <0=> 8-bit bus transfer
-// <1=> 16-bit bus transfer
-// <2=> 32-bit bus transfer
-// <i> Defines the size of one beat
-// <id> dmac_beatsize_12
-#ifndef CONF_DMAC_BEATSIZE_12
-#define CONF_DMAC_BEATSIZE_12 0x0
-#endif
-
-// <o> Source Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is read through the system bus interface 0 or 1
-// <id> dma_src_interface_12
-#ifndef CONF_DMAC_SRC_INTERFACE_12
-#define CONF_DMAC_SRC_INTERFACE_12 0x0
-#endif
-
-// <o> Destination Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is written through the system bus interface 0 or 1
-// <id> dma_des_interface_12
-#ifndef CONF_DMAC_DES_INTERFACE_12
-#define CONF_DMAC_DES_INTERFACE_12 0x0
-#endif
-
-// <q> Source Address Increment
-// <i> Indicates whether the source address incremented as beat size or not
-// <id> dmac_srcinc_12
-#ifndef CONF_DMAC_SRCINC_12
-#define CONF_DMAC_SRCINC_12 0
-#endif
-
-// <q> Destination Address Increment
-// <i> Indicates whether the destination address incremented as beat size or not
-// <id> dmac_dstinc_12
-#ifndef CONF_DMAC_DSTINC_12
-#define CONF_DMAC_DSTINC_12 0
-#endif
-
-// <o> Transfer Type
-// <0x0=> Memory to Memory Transfer
-// <0x1=> Peripheral to Memory Transfer
-// <0x2=> Memory to Peripheral Transfer
-// <i> Define the data transfer type
-// <id> dma_trans_type_12
-#ifndef CONF_DMAC_TRANS_TYPE_12
-#define CONF_DMAC_TRANS_TYPE_12 0x0
-#endif
-
-// <o> Trigger source
-// <0xFF=> Software Trigger
-// <0x00=> HSMCI TX/RX Trigger
-// <0x01=> SPI0 TX Trigger
-// <0x02=> SPI0 RX Trigger
-// <0x03=> SPI1 TX Trigger
-// <0x04=> SPI1 RX Trigger
-// <0x05=> QSPI TX Trigger
-// <0x06=> QSPI RX Trigger
-// <0x07=> USART0 TX Trigger
-// <0x08=> USART0 RX Trigger
-// <0x09=> USART1 TX Trigger
-// <0x0A=> USART1 RX Trigger
-// <0x0B=> USART2 TX Trigger
-// <0x0C=> USART2 RX Trigger
-// <0x0D=> PWM0 TX Trigger
-// <0x0E=> TWIHS0 TX Trigger
-// <0x0F=> TWIHS0 RX Trigger
-// <0x10=> TWIHS1 TX Trigger
-// <0x11=> TWIHS1 RX Trigger
-// <0x12=> TWIHS2 TX Trigger
-// <0x13=> TWIHS2 RX Trigger
-// <0x14=> UART0 TX Trigger
-// <0x15=> UART0 RX Trigger
-// <0x16=> UART1 TX Trigger
-// <0x17=> UART1 RX Trigger
-// <0x18=> UART2 TX Trigger
-// <0x19=> UART2 RX Trigger
-// <0x1A=> UART3 TX Trigger
-// <0x1B=> UART3 RX Trigger
-// <0x1C=> UART4 TX Trigger
-// <0x1D=> UART4 RX Trigger
-// <0x1E=> DACC TX Trigger
-// <0x20=> SSC TX Trigger
-// <0x21=> SSC RX Trigger
-// <0x22=> PIOA RX Trigger
-// <0x23=> AFEC0 RX Trigger
-// <0x24=> AFEC1 RX Trigger
-// <0x25=> AES TX Trigger
-// <0x26=> AES RX Trigger
-// <0x27=> PWM1 TX Trigger
-// <0x28=> TC0 RX Trigger
-// <0x29=> TC3 RX Trigger
-// <0x2A=> TC6 RX Trigger
-// <0x2B=> TC9 RX Trigger
-// <0x2C=> I2SC0 TX Left Trigger
-// <0x2D=> I2SC0 RX Left Trigger
-// <0x2E=> I2SC1 TX Left Trigger
-// <0x2F=> I2SC1 RX Left Trigger
-// <0x30=> I2SC0 TX Right Trigger
-// <0x31=> I2SC0 RX Right Trigger
-// <0x32=> I2SC1 TX Right Trigger
-// <0x33=> I2SC1 RX Right Trigger
-// <i> Define the DMA trigger source
-// <id> dmac_trifsrc_12
-#ifndef CONF_DMAC_TRIGSRC_12
-#define CONF_DMAC_TRIGSRC_12 0xff
-#endif
-
-// </e>
-
-#if CONF_DMAC_TRANS_TYPE_12 == 0
-#define CONF_DMAC_TYPE_12 0
-#define CONF_DMAC_DSYNC_12 0
-#elif CONF_DMAC_TRANS_TYPE_12 == 1
-#define CONF_DMAC_TYPE_12 1
-#define CONF_DMAC_DSYNC_12 0
-#elif CONF_DMAC_TRANS_TYPE_12 == 2
-#define CONF_DMAC_TYPE_12 1
-#define CONF_DMAC_DSYNC_12 1
-#endif
-
-#if CONF_DMAC_TRIGSRC_12 == 0xFF
-#define CONF_DMAC_SWREQ_12 1
-#else
-#define CONF_DMAC_SWREQ_12 0
-#endif
-
-/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
- * or fixed destination address mode, source and destination addresses are incremented
- * by 8-bit or 16-bit.
- * Workaround: The user can fix the problem by setting the source addressing mode to
- * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
- */
-#if (CONF_DMAC_CHANNEL_12_SETTINGS == 1 && CONF_DMAC_BEATSIZE_12 != 2                                                  \
-     && ((!CONF_DMAC_SRCINC_12) || (!CONF_DMAC_DSTINC_12)))
-#if (!CONF_DMAC_SRCINC_12)
-#define CONF_DMAC_SRC_STRIDE_12 ((int16_t)(-1))
-#endif
-#if (!CONF_DMAC_DSTINC_12)
-#define CONF_DMAC_DES_STRIDE_12 ((int16_t)(-1))
-#endif
-#endif
-
-#ifndef CONF_DMAC_SRC_STRIDE_12
-#define CONF_DMAC_SRC_STRIDE_12 0
-#endif
-
-#ifndef CONF_DMAC_DES_STRIDE_12
-#define CONF_DMAC_DES_STRIDE_12 0
-#endif
-
-// <e> Channel 13 settings
-// <id> dmac_channel_13_settings
-#ifndef CONF_DMAC_CHANNEL_13_SETTINGS
-#define CONF_DMAC_CHANNEL_13_SETTINGS 0
-#endif
-
-// <o> Burst Size
-// <0x0=> 1 burst size
-// <0x1=> 4 burst size
-// <0x2=> 8 burst size
-// <0x3=> 16 burst size
-// <i> Define the memory burst size
-// <id> dmac_burstsize_13
-#ifndef CONF_DMAC_BURSTSIZE_13
-#define CONF_DMAC_BURSTSIZE_13 0x0
-#endif
-
-// <o> Chunk Size
-// <0x0=> 1 data transferred
-// <0x1=> 2 data transferred
-// <0x2=> 4 data transferred
-// <0x3=> 8 data transferred
-// <0x4=> 16 data transferred
-// <i> Define the peripheral chunk size
-// <id> dmac_chunksize_13
-#ifndef CONF_DMAC_CHUNKSIZE_13
-#define CONF_DMAC_CHUNKSIZE_13 0x0
-#endif
-
-// <o> Beat Size
-// <0=> 8-bit bus transfer
-// <1=> 16-bit bus transfer
-// <2=> 32-bit bus transfer
-// <i> Defines the size of one beat
-// <id> dmac_beatsize_13
-#ifndef CONF_DMAC_BEATSIZE_13
-#define CONF_DMAC_BEATSIZE_13 0x0
-#endif
-
-// <o> Source Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is read through the system bus interface 0 or 1
-// <id> dma_src_interface_13
-#ifndef CONF_DMAC_SRC_INTERFACE_13
-#define CONF_DMAC_SRC_INTERFACE_13 0x0
-#endif
-
-// <o> Destination Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is written through the system bus interface 0 or 1
-// <id> dma_des_interface_13
-#ifndef CONF_DMAC_DES_INTERFACE_13
-#define CONF_DMAC_DES_INTERFACE_13 0x0
-#endif
-
-// <q> Source Address Increment
-// <i> Indicates whether the source address incremented as beat size or not
-// <id> dmac_srcinc_13
-#ifndef CONF_DMAC_SRCINC_13
-#define CONF_DMAC_SRCINC_13 0
-#endif
-
-// <q> Destination Address Increment
-// <i> Indicates whether the destination address incremented as beat size or not
-// <id> dmac_dstinc_13
-#ifndef CONF_DMAC_DSTINC_13
-#define CONF_DMAC_DSTINC_13 0
-#endif
-
-// <o> Transfer Type
-// <0x0=> Memory to Memory Transfer
-// <0x1=> Peripheral to Memory Transfer
-// <0x2=> Memory to Peripheral Transfer
-// <i> Define the data transfer type
-// <id> dma_trans_type_13
-#ifndef CONF_DMAC_TRANS_TYPE_13
-#define CONF_DMAC_TRANS_TYPE_13 0x0
-#endif
-
-// <o> Trigger source
-// <0xFF=> Software Trigger
-// <0x00=> HSMCI TX/RX Trigger
-// <0x01=> SPI0 TX Trigger
-// <0x02=> SPI0 RX Trigger
-// <0x03=> SPI1 TX Trigger
-// <0x04=> SPI1 RX Trigger
-// <0x05=> QSPI TX Trigger
-// <0x06=> QSPI RX Trigger
-// <0x07=> USART0 TX Trigger
-// <0x08=> USART0 RX Trigger
-// <0x09=> USART1 TX Trigger
-// <0x0A=> USART1 RX Trigger
-// <0x0B=> USART2 TX Trigger
-// <0x0C=> USART2 RX Trigger
-// <0x0D=> PWM0 TX Trigger
-// <0x0E=> TWIHS0 TX Trigger
-// <0x0F=> TWIHS0 RX Trigger
-// <0x10=> TWIHS1 TX Trigger
-// <0x11=> TWIHS1 RX Trigger
-// <0x12=> TWIHS2 TX Trigger
-// <0x13=> TWIHS2 RX Trigger
-// <0x14=> UART0 TX Trigger
-// <0x15=> UART0 RX Trigger
-// <0x16=> UART1 TX Trigger
-// <0x17=> UART1 RX Trigger
-// <0x18=> UART2 TX Trigger
-// <0x19=> UART2 RX Trigger
-// <0x1A=> UART3 TX Trigger
-// <0x1B=> UART3 RX Trigger
-// <0x1C=> UART4 TX Trigger
-// <0x1D=> UART4 RX Trigger
-// <0x1E=> DACC TX Trigger
-// <0x20=> SSC TX Trigger
-// <0x21=> SSC RX Trigger
-// <0x22=> PIOA RX Trigger
-// <0x23=> AFEC0 RX Trigger
-// <0x24=> AFEC1 RX Trigger
-// <0x25=> AES TX Trigger
-// <0x26=> AES RX Trigger
-// <0x27=> PWM1 TX Trigger
-// <0x28=> TC0 RX Trigger
-// <0x29=> TC3 RX Trigger
-// <0x2A=> TC6 RX Trigger
-// <0x2B=> TC9 RX Trigger
-// <0x2C=> I2SC0 TX Left Trigger
-// <0x2D=> I2SC0 RX Left Trigger
-// <0x2E=> I2SC1 TX Left Trigger
-// <0x2F=> I2SC1 RX Left Trigger
-// <0x30=> I2SC0 TX Right Trigger
-// <0x31=> I2SC0 RX Right Trigger
-// <0x32=> I2SC1 TX Right Trigger
-// <0x33=> I2SC1 RX Right Trigger
-// <i> Define the DMA trigger source
-// <id> dmac_trifsrc_13
-#ifndef CONF_DMAC_TRIGSRC_13
-#define CONF_DMAC_TRIGSRC_13 0xff
-#endif
-
-// </e>
-
-#if CONF_DMAC_TRANS_TYPE_13 == 0
-#define CONF_DMAC_TYPE_13 0
-#define CONF_DMAC_DSYNC_13 0
-#elif CONF_DMAC_TRANS_TYPE_13 == 1
-#define CONF_DMAC_TYPE_13 1
-#define CONF_DMAC_DSYNC_13 0
-#elif CONF_DMAC_TRANS_TYPE_13 == 2
-#define CONF_DMAC_TYPE_13 1
-#define CONF_DMAC_DSYNC_13 1
-#endif
-
-#if CONF_DMAC_TRIGSRC_13 == 0xFF
-#define CONF_DMAC_SWREQ_13 1
-#else
-#define CONF_DMAC_SWREQ_13 0
-#endif
-
-/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
- * or fixed destination address mode, source and destination addresses are incremented
- * by 8-bit or 16-bit.
- * Workaround: The user can fix the problem by setting the source addressing mode to
- * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
- */
-#if (CONF_DMAC_CHANNEL_13_SETTINGS == 1 && CONF_DMAC_BEATSIZE_13 != 2                                                  \
-     && ((!CONF_DMAC_SRCINC_13) || (!CONF_DMAC_DSTINC_13)))
-#if (!CONF_DMAC_SRCINC_13)
-#define CONF_DMAC_SRC_STRIDE_13 ((int16_t)(-1))
-#endif
-#if (!CONF_DMAC_DSTINC_13)
-#define CONF_DMAC_DES_STRIDE_13 ((int16_t)(-1))
-#endif
-#endif
-
-#ifndef CONF_DMAC_SRC_STRIDE_13
-#define CONF_DMAC_SRC_STRIDE_13 0
-#endif
-
-#ifndef CONF_DMAC_DES_STRIDE_13
-#define CONF_DMAC_DES_STRIDE_13 0
-#endif
-
-// <e> Channel 14 settings
-// <id> dmac_channel_14_settings
-#ifndef CONF_DMAC_CHANNEL_14_SETTINGS
-#define CONF_DMAC_CHANNEL_14_SETTINGS 0
-#endif
-
-// <o> Burst Size
-// <0x0=> 1 burst size
-// <0x1=> 4 burst size
-// <0x2=> 8 burst size
-// <0x3=> 16 burst size
-// <i> Define the memory burst size
-// <id> dmac_burstsize_14
-#ifndef CONF_DMAC_BURSTSIZE_14
-#define CONF_DMAC_BURSTSIZE_14 0x0
-#endif
-
-// <o> Chunk Size
-// <0x0=> 1 data transferred
-// <0x1=> 2 data transferred
-// <0x2=> 4 data transferred
-// <0x3=> 8 data transferred
-// <0x4=> 16 data transferred
-// <i> Define the peripheral chunk size
-// <id> dmac_chunksize_14
-#ifndef CONF_DMAC_CHUNKSIZE_14
-#define CONF_DMAC_CHUNKSIZE_14 0x0
-#endif
-
-// <o> Beat Size
-// <0=> 8-bit bus transfer
-// <1=> 16-bit bus transfer
-// <2=> 32-bit bus transfer
-// <i> Defines the size of one beat
-// <id> dmac_beatsize_14
-#ifndef CONF_DMAC_BEATSIZE_14
-#define CONF_DMAC_BEATSIZE_14 0x0
-#endif
-
-// <o> Source Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is read through the system bus interface 0 or 1
-// <id> dma_src_interface_14
-#ifndef CONF_DMAC_SRC_INTERFACE_14
-#define CONF_DMAC_SRC_INTERFACE_14 0x0
-#endif
-
-// <o> Destination Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is written through the system bus interface 0 or 1
-// <id> dma_des_interface_14
-#ifndef CONF_DMAC_DES_INTERFACE_14
-#define CONF_DMAC_DES_INTERFACE_14 0x0
-#endif
-
-// <q> Source Address Increment
-// <i> Indicates whether the source address incremented as beat size or not
-// <id> dmac_srcinc_14
-#ifndef CONF_DMAC_SRCINC_14
-#define CONF_DMAC_SRCINC_14 0
-#endif
-
-// <q> Destination Address Increment
-// <i> Indicates whether the destination address incremented as beat size or not
-// <id> dmac_dstinc_14
-#ifndef CONF_DMAC_DSTINC_14
-#define CONF_DMAC_DSTINC_14 0
-#endif
-
-// <o> Transfer Type
-// <0x0=> Memory to Memory Transfer
-// <0x1=> Peripheral to Memory Transfer
-// <0x2=> Memory to Peripheral Transfer
-// <i> Define the data transfer type
-// <id> dma_trans_type_14
-#ifndef CONF_DMAC_TRANS_TYPE_14
-#define CONF_DMAC_TRANS_TYPE_14 0x0
-#endif
-
-// <o> Trigger source
-// <0xFF=> Software Trigger
-// <0x00=> HSMCI TX/RX Trigger
-// <0x01=> SPI0 TX Trigger
-// <0x02=> SPI0 RX Trigger
-// <0x03=> SPI1 TX Trigger
-// <0x04=> SPI1 RX Trigger
-// <0x05=> QSPI TX Trigger
-// <0x06=> QSPI RX Trigger
-// <0x07=> USART0 TX Trigger
-// <0x08=> USART0 RX Trigger
-// <0x09=> USART1 TX Trigger
-// <0x0A=> USART1 RX Trigger
-// <0x0B=> USART2 TX Trigger
-// <0x0C=> USART2 RX Trigger
-// <0x0D=> PWM0 TX Trigger
-// <0x0E=> TWIHS0 TX Trigger
-// <0x0F=> TWIHS0 RX Trigger
-// <0x10=> TWIHS1 TX Trigger
-// <0x11=> TWIHS1 RX Trigger
-// <0x12=> TWIHS2 TX Trigger
-// <0x13=> TWIHS2 RX Trigger
-// <0x14=> UART0 TX Trigger
-// <0x15=> UART0 RX Trigger
-// <0x16=> UART1 TX Trigger
-// <0x17=> UART1 RX Trigger
-// <0x18=> UART2 TX Trigger
-// <0x19=> UART2 RX Trigger
-// <0x1A=> UART3 TX Trigger
-// <0x1B=> UART3 RX Trigger
-// <0x1C=> UART4 TX Trigger
-// <0x1D=> UART4 RX Trigger
-// <0x1E=> DACC TX Trigger
-// <0x20=> SSC TX Trigger
-// <0x21=> SSC RX Trigger
-// <0x22=> PIOA RX Trigger
-// <0x23=> AFEC0 RX Trigger
-// <0x24=> AFEC1 RX Trigger
-// <0x25=> AES TX Trigger
-// <0x26=> AES RX Trigger
-// <0x27=> PWM1 TX Trigger
-// <0x28=> TC0 RX Trigger
-// <0x29=> TC3 RX Trigger
-// <0x2A=> TC6 RX Trigger
-// <0x2B=> TC9 RX Trigger
-// <0x2C=> I2SC0 TX Left Trigger
-// <0x2D=> I2SC0 RX Left Trigger
-// <0x2E=> I2SC1 TX Left Trigger
-// <0x2F=> I2SC1 RX Left Trigger
-// <0x30=> I2SC0 TX Right Trigger
-// <0x31=> I2SC0 RX Right Trigger
-// <0x32=> I2SC1 TX Right Trigger
-// <0x33=> I2SC1 RX Right Trigger
-// <i> Define the DMA trigger source
-// <id> dmac_trifsrc_14
-#ifndef CONF_DMAC_TRIGSRC_14
-#define CONF_DMAC_TRIGSRC_14 0xff
-#endif
-
-// </e>
-
-#if CONF_DMAC_TRANS_TYPE_14 == 0
-#define CONF_DMAC_TYPE_14 0
-#define CONF_DMAC_DSYNC_14 0
-#elif CONF_DMAC_TRANS_TYPE_14 == 1
-#define CONF_DMAC_TYPE_14 1
-#define CONF_DMAC_DSYNC_14 0
-#elif CONF_DMAC_TRANS_TYPE_14 == 2
-#define CONF_DMAC_TYPE_14 1
-#define CONF_DMAC_DSYNC_14 1
-#endif
-
-#if CONF_DMAC_TRIGSRC_14 == 0xFF
-#define CONF_DMAC_SWREQ_14 1
-#else
-#define CONF_DMAC_SWREQ_14 0
-#endif
-
-/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
- * or fixed destination address mode, source and destination addresses are incremented
- * by 8-bit or 16-bit.
- * Workaround: The user can fix the problem by setting the source addressing mode to
- * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
- */
-#if (CONF_DMAC_CHANNEL_14_SETTINGS == 1 && CONF_DMAC_BEATSIZE_14 != 2                                                  \
-     && ((!CONF_DMAC_SRCINC_14) || (!CONF_DMAC_DSTINC_14)))
-#if (!CONF_DMAC_SRCINC_14)
-#define CONF_DMAC_SRC_STRIDE_14 ((int16_t)(-1))
-#endif
-#if (!CONF_DMAC_DSTINC_14)
-#define CONF_DMAC_DES_STRIDE_14 ((int16_t)(-1))
-#endif
-#endif
-
-#ifndef CONF_DMAC_SRC_STRIDE_14
-#define CONF_DMAC_SRC_STRIDE_14 0
-#endif
-
-#ifndef CONF_DMAC_DES_STRIDE_14
-#define CONF_DMAC_DES_STRIDE_14 0
-#endif
-
-// <e> Channel 15 settings
-// <id> dmac_channel_15_settings
-#ifndef CONF_DMAC_CHANNEL_15_SETTINGS
-#define CONF_DMAC_CHANNEL_15_SETTINGS 0
-#endif
-
-// <o> Burst Size
-// <0x0=> 1 burst size
-// <0x1=> 4 burst size
-// <0x2=> 8 burst size
-// <0x3=> 16 burst size
-// <i> Define the memory burst size
-// <id> dmac_burstsize_15
-#ifndef CONF_DMAC_BURSTSIZE_15
-#define CONF_DMAC_BURSTSIZE_15 0x0
-#endif
-
-// <o> Chunk Size
-// <0x0=> 1 data transferred
-// <0x1=> 2 data transferred
-// <0x2=> 4 data transferred
-// <0x3=> 8 data transferred
-// <0x4=> 16 data transferred
-// <i> Define the peripheral chunk size
-// <id> dmac_chunksize_15
-#ifndef CONF_DMAC_CHUNKSIZE_15
-#define CONF_DMAC_CHUNKSIZE_15 0x0
-#endif
-
-// <o> Beat Size
-// <0=> 8-bit bus transfer
-// <1=> 16-bit bus transfer
-// <2=> 32-bit bus transfer
-// <i> Defines the size of one beat
-// <id> dmac_beatsize_15
-#ifndef CONF_DMAC_BEATSIZE_15
-#define CONF_DMAC_BEATSIZE_15 0x0
-#endif
-
-// <o> Source Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is read through the system bus interface 0 or 1
-// <id> dma_src_interface_15
-#ifndef CONF_DMAC_SRC_INTERFACE_15
-#define CONF_DMAC_SRC_INTERFACE_15 0x0
-#endif
-
-// <o> Destination Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is written through the system bus interface 0 or 1
-// <id> dma_des_interface_15
-#ifndef CONF_DMAC_DES_INTERFACE_15
-#define CONF_DMAC_DES_INTERFACE_15 0x0
-#endif
-
-// <q> Source Address Increment
-// <i> Indicates whether the source address incremented as beat size or not
-// <id> dmac_srcinc_15
-#ifndef CONF_DMAC_SRCINC_15
-#define CONF_DMAC_SRCINC_15 0
-#endif
-
-// <q> Destination Address Increment
-// <i> Indicates whether the destination address incremented as beat size or not
-// <id> dmac_dstinc_15
-#ifndef CONF_DMAC_DSTINC_15
-#define CONF_DMAC_DSTINC_15 0
-#endif
-
-// <o> Transfer Type
-// <0x0=> Memory to Memory Transfer
-// <0x1=> Peripheral to Memory Transfer
-// <0x2=> Memory to Peripheral Transfer
-// <i> Define the data transfer type
-// <id> dma_trans_type_15
-#ifndef CONF_DMAC_TRANS_TYPE_15
-#define CONF_DMAC_TRANS_TYPE_15 0x0
-#endif
-
-// <o> Trigger source
-// <0xFF=> Software Trigger
-// <0x00=> HSMCI TX/RX Trigger
-// <0x01=> SPI0 TX Trigger
-// <0x02=> SPI0 RX Trigger
-// <0x03=> SPI1 TX Trigger
-// <0x04=> SPI1 RX Trigger
-// <0x05=> QSPI TX Trigger
-// <0x06=> QSPI RX Trigger
-// <0x07=> USART0 TX Trigger
-// <0x08=> USART0 RX Trigger
-// <0x09=> USART1 TX Trigger
-// <0x0A=> USART1 RX Trigger
-// <0x0B=> USART2 TX Trigger
-// <0x0C=> USART2 RX Trigger
-// <0x0D=> PWM0 TX Trigger
-// <0x0E=> TWIHS0 TX Trigger
-// <0x0F=> TWIHS0 RX Trigger
-// <0x10=> TWIHS1 TX Trigger
-// <0x11=> TWIHS1 RX Trigger
-// <0x12=> TWIHS2 TX Trigger
-// <0x13=> TWIHS2 RX Trigger
-// <0x14=> UART0 TX Trigger
-// <0x15=> UART0 RX Trigger
-// <0x16=> UART1 TX Trigger
-// <0x17=> UART1 RX Trigger
-// <0x18=> UART2 TX Trigger
-// <0x19=> UART2 RX Trigger
-// <0x1A=> UART3 TX Trigger
-// <0x1B=> UART3 RX Trigger
-// <0x1C=> UART4 TX Trigger
-// <0x1D=> UART4 RX Trigger
-// <0x1E=> DACC TX Trigger
-// <0x20=> SSC TX Trigger
-// <0x21=> SSC RX Trigger
-// <0x22=> PIOA RX Trigger
-// <0x23=> AFEC0 RX Trigger
-// <0x24=> AFEC1 RX Trigger
-// <0x25=> AES TX Trigger
-// <0x26=> AES RX Trigger
-// <0x27=> PWM1 TX Trigger
-// <0x28=> TC0 RX Trigger
-// <0x29=> TC3 RX Trigger
-// <0x2A=> TC6 RX Trigger
-// <0x2B=> TC9 RX Trigger
-// <0x2C=> I2SC0 TX Left Trigger
-// <0x2D=> I2SC0 RX Left Trigger
-// <0x2E=> I2SC1 TX Left Trigger
-// <0x2F=> I2SC1 RX Left Trigger
-// <0x30=> I2SC0 TX Right Trigger
-// <0x31=> I2SC0 RX Right Trigger
-// <0x32=> I2SC1 TX Right Trigger
-// <0x33=> I2SC1 RX Right Trigger
-// <i> Define the DMA trigger source
-// <id> dmac_trifsrc_15
-#ifndef CONF_DMAC_TRIGSRC_15
-#define CONF_DMAC_TRIGSRC_15 0xff
-#endif
-
-// </e>
-
-#if CONF_DMAC_TRANS_TYPE_15 == 0
-#define CONF_DMAC_TYPE_15 0
-#define CONF_DMAC_DSYNC_15 0
-#elif CONF_DMAC_TRANS_TYPE_15 == 1
-#define CONF_DMAC_TYPE_15 1
-#define CONF_DMAC_DSYNC_15 0
-#elif CONF_DMAC_TRANS_TYPE_15 == 2
-#define CONF_DMAC_TYPE_15 1
-#define CONF_DMAC_DSYNC_15 1
-#endif
-
-#if CONF_DMAC_TRIGSRC_15 == 0xFF
-#define CONF_DMAC_SWREQ_15 1
-#else
-#define CONF_DMAC_SWREQ_15 0
-#endif
-
-/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
- * or fixed destination address mode, source and destination addresses are incremented
- * by 8-bit or 16-bit.
- * Workaround: The user can fix the problem by setting the source addressing mode to
- * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
- */
-#if (CONF_DMAC_CHANNEL_15_SETTINGS == 1 && CONF_DMAC_BEATSIZE_15 != 2                                                  \
-     && ((!CONF_DMAC_SRCINC_15) || (!CONF_DMAC_DSTINC_15)))
-#if (!CONF_DMAC_SRCINC_15)
-#define CONF_DMAC_SRC_STRIDE_15 ((int16_t)(-1))
-#endif
-#if (!CONF_DMAC_DSTINC_15)
-#define CONF_DMAC_DES_STRIDE_15 ((int16_t)(-1))
-#endif
-#endif
-
-#ifndef CONF_DMAC_SRC_STRIDE_15
-#define CONF_DMAC_SRC_STRIDE_15 0
-#endif
-
-#ifndef CONF_DMAC_DES_STRIDE_15
-#define CONF_DMAC_DES_STRIDE_15 0
-#endif
-
-// <e> Channel 16 settings
-// <id> dmac_channel_16_settings
-#ifndef CONF_DMAC_CHANNEL_16_SETTINGS
-#define CONF_DMAC_CHANNEL_16_SETTINGS 0
-#endif
-
-// <o> Burst Size
-// <0x0=> 1 burst size
-// <0x1=> 4 burst size
-// <0x2=> 8 burst size
-// <0x3=> 16 burst size
-// <i> Define the memory burst size
-// <id> dmac_burstsize_16
-#ifndef CONF_DMAC_BURSTSIZE_16
-#define CONF_DMAC_BURSTSIZE_16 0x0
-#endif
-
-// <o> Chunk Size
-// <0x0=> 1 data transferred
-// <0x1=> 2 data transferred
-// <0x2=> 4 data transferred
-// <0x3=> 8 data transferred
-// <0x4=> 16 data transferred
-// <i> Define the peripheral chunk size
-// <id> dmac_chunksize_16
-#ifndef CONF_DMAC_CHUNKSIZE_16
-#define CONF_DMAC_CHUNKSIZE_16 0x0
-#endif
-
-// <o> Beat Size
-// <0=> 8-bit bus transfer
-// <1=> 16-bit bus transfer
-// <2=> 32-bit bus transfer
-// <i> Defines the size of one beat
-// <id> dmac_beatsize_16
-#ifndef CONF_DMAC_BEATSIZE_16
-#define CONF_DMAC_BEATSIZE_16 0x0
-#endif
-
-// <o> Source Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is read through the system bus interface 0 or 1
-// <id> dma_src_interface_16
-#ifndef CONF_DMAC_SRC_INTERFACE_16
-#define CONF_DMAC_SRC_INTERFACE_16 0x0
-#endif
-
-// <o> Destination Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is written through the system bus interface 0 or 1
-// <id> dma_des_interface_16
-#ifndef CONF_DMAC_DES_INTERFACE_16
-#define CONF_DMAC_DES_INTERFACE_16 0x0
-#endif
-
-// <q> Source Address Increment
-// <i> Indicates whether the source address incremented as beat size or not
-// <id> dmac_srcinc_16
-#ifndef CONF_DMAC_SRCINC_16
-#define CONF_DMAC_SRCINC_16 0
-#endif
-
-// <q> Destination Address Increment
-// <i> Indicates whether the destination address incremented as beat size or not
-// <id> dmac_dstinc_16
-#ifndef CONF_DMAC_DSTINC_16
-#define CONF_DMAC_DSTINC_16 0
-#endif
-
-// <o> Transfer Type
-// <0x0=> Memory to Memory Transfer
-// <0x1=> Peripheral to Memory Transfer
-// <0x2=> Memory to Peripheral Transfer
-// <i> Define the data transfer type
-// <id> dma_trans_type_16
-#ifndef CONF_DMAC_TRANS_TYPE_16
-#define CONF_DMAC_TRANS_TYPE_16 0x0
-#endif
-
-// <o> Trigger source
-// <0xFF=> Software Trigger
-// <0x00=> HSMCI TX/RX Trigger
-// <0x01=> SPI0 TX Trigger
-// <0x02=> SPI0 RX Trigger
-// <0x03=> SPI1 TX Trigger
-// <0x04=> SPI1 RX Trigger
-// <0x05=> QSPI TX Trigger
-// <0x06=> QSPI RX Trigger
-// <0x07=> USART0 TX Trigger
-// <0x08=> USART0 RX Trigger
-// <0x09=> USART1 TX Trigger
-// <0x0A=> USART1 RX Trigger
-// <0x0B=> USART2 TX Trigger
-// <0x0C=> USART2 RX Trigger
-// <0x0D=> PWM0 TX Trigger
-// <0x0E=> TWIHS0 TX Trigger
-// <0x0F=> TWIHS0 RX Trigger
-// <0x10=> TWIHS1 TX Trigger
-// <0x11=> TWIHS1 RX Trigger
-// <0x12=> TWIHS2 TX Trigger
-// <0x13=> TWIHS2 RX Trigger
-// <0x14=> UART0 TX Trigger
-// <0x15=> UART0 RX Trigger
-// <0x16=> UART1 TX Trigger
-// <0x17=> UART1 RX Trigger
-// <0x18=> UART2 TX Trigger
-// <0x19=> UART2 RX Trigger
-// <0x1A=> UART3 TX Trigger
-// <0x1B=> UART3 RX Trigger
-// <0x1C=> UART4 TX Trigger
-// <0x1D=> UART4 RX Trigger
-// <0x1E=> DACC TX Trigger
-// <0x20=> SSC TX Trigger
-// <0x21=> SSC RX Trigger
-// <0x22=> PIOA RX Trigger
-// <0x23=> AFEC0 RX Trigger
-// <0x24=> AFEC1 RX Trigger
-// <0x25=> AES TX Trigger
-// <0x26=> AES RX Trigger
-// <0x27=> PWM1 TX Trigger
-// <0x28=> TC0 RX Trigger
-// <0x29=> TC3 RX Trigger
-// <0x2A=> TC6 RX Trigger
-// <0x2B=> TC9 RX Trigger
-// <0x2C=> I2SC0 TX Left Trigger
-// <0x2D=> I2SC0 RX Left Trigger
-// <0x2E=> I2SC1 TX Left Trigger
-// <0x2F=> I2SC1 RX Left Trigger
-// <0x30=> I2SC0 TX Right Trigger
-// <0x31=> I2SC0 RX Right Trigger
-// <0x32=> I2SC1 TX Right Trigger
-// <0x33=> I2SC1 RX Right Trigger
-// <i> Define the DMA trigger source
-// <id> dmac_trifsrc_16
-#ifndef CONF_DMAC_TRIGSRC_16
-#define CONF_DMAC_TRIGSRC_16 0xff
-#endif
-
-// </e>
-
-#if CONF_DMAC_TRANS_TYPE_16 == 0
-#define CONF_DMAC_TYPE_16 0
-#define CONF_DMAC_DSYNC_16 0
-#elif CONF_DMAC_TRANS_TYPE_16 == 1
-#define CONF_DMAC_TYPE_16 1
-#define CONF_DMAC_DSYNC_16 0
-#elif CONF_DMAC_TRANS_TYPE_16 == 2
-#define CONF_DMAC_TYPE_16 1
-#define CONF_DMAC_DSYNC_16 1
-#endif
-
-#if CONF_DMAC_TRIGSRC_16 == 0xFF
-#define CONF_DMAC_SWREQ_16 1
-#else
-#define CONF_DMAC_SWREQ_16 0
-#endif
-
-/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
- * or fixed destination address mode, source and destination addresses are incremented
- * by 8-bit or 16-bit.
- * Workaround: The user can fix the problem by setting the source addressing mode to
- * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
- */
-#if (CONF_DMAC_CHANNEL_16_SETTINGS == 1 && CONF_DMAC_BEATSIZE_16 != 2                                                  \
-     && ((!CONF_DMAC_SRCINC_16) || (!CONF_DMAC_DSTINC_16)))
-#if (!CONF_DMAC_SRCINC_16)
-#define CONF_DMAC_SRC_STRIDE_16 ((int16_t)(-1))
-#endif
-#if (!CONF_DMAC_DSTINC_16)
-#define CONF_DMAC_DES_STRIDE_16 ((int16_t)(-1))
-#endif
-#endif
-
-#ifndef CONF_DMAC_SRC_STRIDE_16
-#define CONF_DMAC_SRC_STRIDE_16 0
-#endif
-
-#ifndef CONF_DMAC_DES_STRIDE_16
-#define CONF_DMAC_DES_STRIDE_16 0
-#endif
-
-// <e> Channel 17 settings
-// <id> dmac_channel_17_settings
-#ifndef CONF_DMAC_CHANNEL_17_SETTINGS
-#define CONF_DMAC_CHANNEL_17_SETTINGS 0
-#endif
-
-// <o> Burst Size
-// <0x0=> 1 burst size
-// <0x1=> 4 burst size
-// <0x2=> 8 burst size
-// <0x3=> 16 burst size
-// <i> Define the memory burst size
-// <id> dmac_burstsize_17
-#ifndef CONF_DMAC_BURSTSIZE_17
-#define CONF_DMAC_BURSTSIZE_17 0x0
-#endif
-
-// <o> Chunk Size
-// <0x0=> 1 data transferred
-// <0x1=> 2 data transferred
-// <0x2=> 4 data transferred
-// <0x3=> 8 data transferred
-// <0x4=> 16 data transferred
-// <i> Define the peripheral chunk size
-// <id> dmac_chunksize_17
-#ifndef CONF_DMAC_CHUNKSIZE_17
-#define CONF_DMAC_CHUNKSIZE_17 0x0
-#endif
-
-// <o> Beat Size
-// <0=> 8-bit bus transfer
-// <1=> 16-bit bus transfer
-// <2=> 32-bit bus transfer
-// <i> Defines the size of one beat
-// <id> dmac_beatsize_17
-#ifndef CONF_DMAC_BEATSIZE_17
-#define CONF_DMAC_BEATSIZE_17 0x0
-#endif
-
-// <o> Source Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is read through the system bus interface 0 or 1
-// <id> dma_src_interface_17
-#ifndef CONF_DMAC_SRC_INTERFACE_17
-#define CONF_DMAC_SRC_INTERFACE_17 0x0
-#endif
-
-// <o> Destination Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is written through the system bus interface 0 or 1
-// <id> dma_des_interface_17
-#ifndef CONF_DMAC_DES_INTERFACE_17
-#define CONF_DMAC_DES_INTERFACE_17 0x0
-#endif
-
-// <q> Source Address Increment
-// <i> Indicates whether the source address incremented as beat size or not
-// <id> dmac_srcinc_17
-#ifndef CONF_DMAC_SRCINC_17
-#define CONF_DMAC_SRCINC_17 0
-#endif
-
-// <q> Destination Address Increment
-// <i> Indicates whether the destination address incremented as beat size or not
-// <id> dmac_dstinc_17
-#ifndef CONF_DMAC_DSTINC_17
-#define CONF_DMAC_DSTINC_17 0
-#endif
-
-// <o> Transfer Type
-// <0x0=> Memory to Memory Transfer
-// <0x1=> Peripheral to Memory Transfer
-// <0x2=> Memory to Peripheral Transfer
-// <i> Define the data transfer type
-// <id> dma_trans_type_17
-#ifndef CONF_DMAC_TRANS_TYPE_17
-#define CONF_DMAC_TRANS_TYPE_17 0x0
-#endif
-
-// <o> Trigger source
-// <0xFF=> Software Trigger
-// <0x00=> HSMCI TX/RX Trigger
-// <0x01=> SPI0 TX Trigger
-// <0x02=> SPI0 RX Trigger
-// <0x03=> SPI1 TX Trigger
-// <0x04=> SPI1 RX Trigger
-// <0x05=> QSPI TX Trigger
-// <0x06=> QSPI RX Trigger
-// <0x07=> USART0 TX Trigger
-// <0x08=> USART0 RX Trigger
-// <0x09=> USART1 TX Trigger
-// <0x0A=> USART1 RX Trigger
-// <0x0B=> USART2 TX Trigger
-// <0x0C=> USART2 RX Trigger
-// <0x0D=> PWM0 TX Trigger
-// <0x0E=> TWIHS0 TX Trigger
-// <0x0F=> TWIHS0 RX Trigger
-// <0x10=> TWIHS1 TX Trigger
-// <0x11=> TWIHS1 RX Trigger
-// <0x12=> TWIHS2 TX Trigger
-// <0x13=> TWIHS2 RX Trigger
-// <0x14=> UART0 TX Trigger
-// <0x15=> UART0 RX Trigger
-// <0x16=> UART1 TX Trigger
-// <0x17=> UART1 RX Trigger
-// <0x18=> UART2 TX Trigger
-// <0x19=> UART2 RX Trigger
-// <0x1A=> UART3 TX Trigger
-// <0x1B=> UART3 RX Trigger
-// <0x1C=> UART4 TX Trigger
-// <0x1D=> UART4 RX Trigger
-// <0x1E=> DACC TX Trigger
-// <0x20=> SSC TX Trigger
-// <0x21=> SSC RX Trigger
-// <0x22=> PIOA RX Trigger
-// <0x23=> AFEC0 RX Trigger
-// <0x24=> AFEC1 RX Trigger
-// <0x25=> AES TX Trigger
-// <0x26=> AES RX Trigger
-// <0x27=> PWM1 TX Trigger
-// <0x28=> TC0 RX Trigger
-// <0x29=> TC3 RX Trigger
-// <0x2A=> TC6 RX Trigger
-// <0x2B=> TC9 RX Trigger
-// <0x2C=> I2SC0 TX Left Trigger
-// <0x2D=> I2SC0 RX Left Trigger
-// <0x2E=> I2SC1 TX Left Trigger
-// <0x2F=> I2SC1 RX Left Trigger
-// <0x30=> I2SC0 TX Right Trigger
-// <0x31=> I2SC0 RX Right Trigger
-// <0x32=> I2SC1 TX Right Trigger
-// <0x33=> I2SC1 RX Right Trigger
-// <i> Define the DMA trigger source
-// <id> dmac_trifsrc_17
-#ifndef CONF_DMAC_TRIGSRC_17
-#define CONF_DMAC_TRIGSRC_17 0xff
-#endif
-
-// </e>
-
-#if CONF_DMAC_TRANS_TYPE_17 == 0
-#define CONF_DMAC_TYPE_17 0
-#define CONF_DMAC_DSYNC_17 0
-#elif CONF_DMAC_TRANS_TYPE_17 == 1
-#define CONF_DMAC_TYPE_17 1
-#define CONF_DMAC_DSYNC_17 0
-#elif CONF_DMAC_TRANS_TYPE_17 == 2
-#define CONF_DMAC_TYPE_17 1
-#define CONF_DMAC_DSYNC_17 1
-#endif
-
-#if CONF_DMAC_TRIGSRC_17 == 0xFF
-#define CONF_DMAC_SWREQ_17 1
-#else
-#define CONF_DMAC_SWREQ_17 0
-#endif
-
-/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
- * or fixed destination address mode, source and destination addresses are incremented
- * by 8-bit or 16-bit.
- * Workaround: The user can fix the problem by setting the source addressing mode to
- * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
- */
-#if (CONF_DMAC_CHANNEL_17_SETTINGS == 1 && CONF_DMAC_BEATSIZE_17 != 2                                                  \
-     && ((!CONF_DMAC_SRCINC_17) || (!CONF_DMAC_DSTINC_17)))
-#if (!CONF_DMAC_SRCINC_17)
-#define CONF_DMAC_SRC_STRIDE_17 ((int16_t)(-1))
-#endif
-#if (!CONF_DMAC_DSTINC_17)
-#define CONF_DMAC_DES_STRIDE_17 ((int16_t)(-1))
-#endif
-#endif
-
-#ifndef CONF_DMAC_SRC_STRIDE_17
-#define CONF_DMAC_SRC_STRIDE_17 0
-#endif
-
-#ifndef CONF_DMAC_DES_STRIDE_17
-#define CONF_DMAC_DES_STRIDE_17 0
-#endif
-
-// <e> Channel 18 settings
-// <id> dmac_channel_18_settings
-#ifndef CONF_DMAC_CHANNEL_18_SETTINGS
-#define CONF_DMAC_CHANNEL_18_SETTINGS 0
-#endif
-
-// <o> Burst Size
-// <0x0=> 1 burst size
-// <0x1=> 4 burst size
-// <0x2=> 8 burst size
-// <0x3=> 16 burst size
-// <i> Define the memory burst size
-// <id> dmac_burstsize_18
-#ifndef CONF_DMAC_BURSTSIZE_18
-#define CONF_DMAC_BURSTSIZE_18 0x0
-#endif
-
-// <o> Chunk Size
-// <0x0=> 1 data transferred
-// <0x1=> 2 data transferred
-// <0x2=> 4 data transferred
-// <0x3=> 8 data transferred
-// <0x4=> 16 data transferred
-// <i> Define the peripheral chunk size
-// <id> dmac_chunksize_18
-#ifndef CONF_DMAC_CHUNKSIZE_18
-#define CONF_DMAC_CHUNKSIZE_18 0x0
-#endif
-
-// <o> Beat Size
-// <0=> 8-bit bus transfer
-// <1=> 16-bit bus transfer
-// <2=> 32-bit bus transfer
-// <i> Defines the size of one beat
-// <id> dmac_beatsize_18
-#ifndef CONF_DMAC_BEATSIZE_18
-#define CONF_DMAC_BEATSIZE_18 0x0
-#endif
-
-// <o> Source Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is read through the system bus interface 0 or 1
-// <id> dma_src_interface_18
-#ifndef CONF_DMAC_SRC_INTERFACE_18
-#define CONF_DMAC_SRC_INTERFACE_18 0x0
-#endif
-
-// <o> Destination Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is written through the system bus interface 0 or 1
-// <id> dma_des_interface_18
-#ifndef CONF_DMAC_DES_INTERFACE_18
-#define CONF_DMAC_DES_INTERFACE_18 0x0
-#endif
-
-// <q> Source Address Increment
-// <i> Indicates whether the source address incremented as beat size or not
-// <id> dmac_srcinc_18
-#ifndef CONF_DMAC_SRCINC_18
-#define CONF_DMAC_SRCINC_18 0
-#endif
-
-// <q> Destination Address Increment
-// <i> Indicates whether the destination address incremented as beat size or not
-// <id> dmac_dstinc_18
-#ifndef CONF_DMAC_DSTINC_18
-#define CONF_DMAC_DSTINC_18 0
-#endif
-
-// <o> Transfer Type
-// <0x0=> Memory to Memory Transfer
-// <0x1=> Peripheral to Memory Transfer
-// <0x2=> Memory to Peripheral Transfer
-// <i> Define the data transfer type
-// <id> dma_trans_type_18
-#ifndef CONF_DMAC_TRANS_TYPE_18
-#define CONF_DMAC_TRANS_TYPE_18 0x0
-#endif
-
-// <o> Trigger source
-// <0xFF=> Software Trigger
-// <0x00=> HSMCI TX/RX Trigger
-// <0x01=> SPI0 TX Trigger
-// <0x02=> SPI0 RX Trigger
-// <0x03=> SPI1 TX Trigger
-// <0x04=> SPI1 RX Trigger
-// <0x05=> QSPI TX Trigger
-// <0x06=> QSPI RX Trigger
-// <0x07=> USART0 TX Trigger
-// <0x08=> USART0 RX Trigger
-// <0x09=> USART1 TX Trigger
-// <0x0A=> USART1 RX Trigger
-// <0x0B=> USART2 TX Trigger
-// <0x0C=> USART2 RX Trigger
-// <0x0D=> PWM0 TX Trigger
-// <0x0E=> TWIHS0 TX Trigger
-// <0x0F=> TWIHS0 RX Trigger
-// <0x10=> TWIHS1 TX Trigger
-// <0x11=> TWIHS1 RX Trigger
-// <0x12=> TWIHS2 TX Trigger
-// <0x13=> TWIHS2 RX Trigger
-// <0x14=> UART0 TX Trigger
-// <0x15=> UART0 RX Trigger
-// <0x16=> UART1 TX Trigger
-// <0x17=> UART1 RX Trigger
-// <0x18=> UART2 TX Trigger
-// <0x19=> UART2 RX Trigger
-// <0x1A=> UART3 TX Trigger
-// <0x1B=> UART3 RX Trigger
-// <0x1C=> UART4 TX Trigger
-// <0x1D=> UART4 RX Trigger
-// <0x1E=> DACC TX Trigger
-// <0x20=> SSC TX Trigger
-// <0x21=> SSC RX Trigger
-// <0x22=> PIOA RX Trigger
-// <0x23=> AFEC0 RX Trigger
-// <0x24=> AFEC1 RX Trigger
-// <0x25=> AES TX Trigger
-// <0x26=> AES RX Trigger
-// <0x27=> PWM1 TX Trigger
-// <0x28=> TC0 RX Trigger
-// <0x29=> TC3 RX Trigger
-// <0x2A=> TC6 RX Trigger
-// <0x2B=> TC9 RX Trigger
-// <0x2C=> I2SC0 TX Left Trigger
-// <0x2D=> I2SC0 RX Left Trigger
-// <0x2E=> I2SC1 TX Left Trigger
-// <0x2F=> I2SC1 RX Left Trigger
-// <0x30=> I2SC0 TX Right Trigger
-// <0x31=> I2SC0 RX Right Trigger
-// <0x32=> I2SC1 TX Right Trigger
-// <0x33=> I2SC1 RX Right Trigger
-// <i> Define the DMA trigger source
-// <id> dmac_trifsrc_18
-#ifndef CONF_DMAC_TRIGSRC_18
-#define CONF_DMAC_TRIGSRC_18 0xff
-#endif
-
-// </e>
-
-#if CONF_DMAC_TRANS_TYPE_18 == 0
-#define CONF_DMAC_TYPE_18 0
-#define CONF_DMAC_DSYNC_18 0
-#elif CONF_DMAC_TRANS_TYPE_18 == 1
-#define CONF_DMAC_TYPE_18 1
-#define CONF_DMAC_DSYNC_18 0
-#elif CONF_DMAC_TRANS_TYPE_18 == 2
-#define CONF_DMAC_TYPE_18 1
-#define CONF_DMAC_DSYNC_18 1
-#endif
-
-#if CONF_DMAC_TRIGSRC_18 == 0xFF
-#define CONF_DMAC_SWREQ_18 1
-#else
-#define CONF_DMAC_SWREQ_18 0
-#endif
-
-/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
- * or fixed destination address mode, source and destination addresses are incremented
- * by 8-bit or 16-bit.
- * Workaround: The user can fix the problem by setting the source addressing mode to
- * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
- */
-#if (CONF_DMAC_CHANNEL_18_SETTINGS == 1 && CONF_DMAC_BEATSIZE_18 != 2                                                  \
-     && ((!CONF_DMAC_SRCINC_18) || (!CONF_DMAC_DSTINC_18)))
-#if (!CONF_DMAC_SRCINC_18)
-#define CONF_DMAC_SRC_STRIDE_18 ((int16_t)(-1))
-#endif
-#if (!CONF_DMAC_DSTINC_18)
-#define CONF_DMAC_DES_STRIDE_18 ((int16_t)(-1))
-#endif
-#endif
-
-#ifndef CONF_DMAC_SRC_STRIDE_18
-#define CONF_DMAC_SRC_STRIDE_18 0
-#endif
-
-#ifndef CONF_DMAC_DES_STRIDE_18
-#define CONF_DMAC_DES_STRIDE_18 0
-#endif
-
-// <e> Channel 19 settings
-// <id> dmac_channel_19_settings
-#ifndef CONF_DMAC_CHANNEL_19_SETTINGS
-#define CONF_DMAC_CHANNEL_19_SETTINGS 0
-#endif
-
-// <o> Burst Size
-// <0x0=> 1 burst size
-// <0x1=> 4 burst size
-// <0x2=> 8 burst size
-// <0x3=> 16 burst size
-// <i> Define the memory burst size
-// <id> dmac_burstsize_19
-#ifndef CONF_DMAC_BURSTSIZE_19
-#define CONF_DMAC_BURSTSIZE_19 0x0
-#endif
-
-// <o> Chunk Size
-// <0x0=> 1 data transferred
-// <0x1=> 2 data transferred
-// <0x2=> 4 data transferred
-// <0x3=> 8 data transferred
-// <0x4=> 16 data transferred
-// <i> Define the peripheral chunk size
-// <id> dmac_chunksize_19
-#ifndef CONF_DMAC_CHUNKSIZE_19
-#define CONF_DMAC_CHUNKSIZE_19 0x0
-#endif
-
-// <o> Beat Size
-// <0=> 8-bit bus transfer
-// <1=> 16-bit bus transfer
-// <2=> 32-bit bus transfer
-// <i> Defines the size of one beat
-// <id> dmac_beatsize_19
-#ifndef CONF_DMAC_BEATSIZE_19
-#define CONF_DMAC_BEATSIZE_19 0x0
-#endif
-
-// <o> Source Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is read through the system bus interface 0 or 1
-// <id> dma_src_interface_19
-#ifndef CONF_DMAC_SRC_INTERFACE_19
-#define CONF_DMAC_SRC_INTERFACE_19 0x0
-#endif
-
-// <o> Destination Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is written through the system bus interface 0 or 1
-// <id> dma_des_interface_19
-#ifndef CONF_DMAC_DES_INTERFACE_19
-#define CONF_DMAC_DES_INTERFACE_19 0x0
-#endif
-
-// <q> Source Address Increment
-// <i> Indicates whether the source address incremented as beat size or not
-// <id> dmac_srcinc_19
-#ifndef CONF_DMAC_SRCINC_19
-#define CONF_DMAC_SRCINC_19 0
-#endif
-
-// <q> Destination Address Increment
-// <i> Indicates whether the destination address incremented as beat size or not
-// <id> dmac_dstinc_19
-#ifndef CONF_DMAC_DSTINC_19
-#define CONF_DMAC_DSTINC_19 0
-#endif
-
-// <o> Transfer Type
-// <0x0=> Memory to Memory Transfer
-// <0x1=> Peripheral to Memory Transfer
-// <0x2=> Memory to Peripheral Transfer
-// <i> Define the data transfer type
-// <id> dma_trans_type_19
-#ifndef CONF_DMAC_TRANS_TYPE_19
-#define CONF_DMAC_TRANS_TYPE_19 0x0
-#endif
-
-// <o> Trigger source
-// <0xFF=> Software Trigger
-// <0x00=> HSMCI TX/RX Trigger
-// <0x01=> SPI0 TX Trigger
-// <0x02=> SPI0 RX Trigger
-// <0x03=> SPI1 TX Trigger
-// <0x04=> SPI1 RX Trigger
-// <0x05=> QSPI TX Trigger
-// <0x06=> QSPI RX Trigger
-// <0x07=> USART0 TX Trigger
-// <0x08=> USART0 RX Trigger
-// <0x09=> USART1 TX Trigger
-// <0x0A=> USART1 RX Trigger
-// <0x0B=> USART2 TX Trigger
-// <0x0C=> USART2 RX Trigger
-// <0x0D=> PWM0 TX Trigger
-// <0x0E=> TWIHS0 TX Trigger
-// <0x0F=> TWIHS0 RX Trigger
-// <0x10=> TWIHS1 TX Trigger
-// <0x11=> TWIHS1 RX Trigger
-// <0x12=> TWIHS2 TX Trigger
-// <0x13=> TWIHS2 RX Trigger
-// <0x14=> UART0 TX Trigger
-// <0x15=> UART0 RX Trigger
-// <0x16=> UART1 TX Trigger
-// <0x17=> UART1 RX Trigger
-// <0x18=> UART2 TX Trigger
-// <0x19=> UART2 RX Trigger
-// <0x1A=> UART3 TX Trigger
-// <0x1B=> UART3 RX Trigger
-// <0x1C=> UART4 TX Trigger
-// <0x1D=> UART4 RX Trigger
-// <0x1E=> DACC TX Trigger
-// <0x20=> SSC TX Trigger
-// <0x21=> SSC RX Trigger
-// <0x22=> PIOA RX Trigger
-// <0x23=> AFEC0 RX Trigger
-// <0x24=> AFEC1 RX Trigger
-// <0x25=> AES TX Trigger
-// <0x26=> AES RX Trigger
-// <0x27=> PWM1 TX Trigger
-// <0x28=> TC0 RX Trigger
-// <0x29=> TC3 RX Trigger
-// <0x2A=> TC6 RX Trigger
-// <0x2B=> TC9 RX Trigger
-// <0x2C=> I2SC0 TX Left Trigger
-// <0x2D=> I2SC0 RX Left Trigger
-// <0x2E=> I2SC1 TX Left Trigger
-// <0x2F=> I2SC1 RX Left Trigger
-// <0x30=> I2SC0 TX Right Trigger
-// <0x31=> I2SC0 RX Right Trigger
-// <0x32=> I2SC1 TX Right Trigger
-// <0x33=> I2SC1 RX Right Trigger
-// <i> Define the DMA trigger source
-// <id> dmac_trifsrc_19
-#ifndef CONF_DMAC_TRIGSRC_19
-#define CONF_DMAC_TRIGSRC_19 0xff
-#endif
-
-// </e>
-
-#if CONF_DMAC_TRANS_TYPE_19 == 0
-#define CONF_DMAC_TYPE_19 0
-#define CONF_DMAC_DSYNC_19 0
-#elif CONF_DMAC_TRANS_TYPE_19 == 1
-#define CONF_DMAC_TYPE_19 1
-#define CONF_DMAC_DSYNC_19 0
-#elif CONF_DMAC_TRANS_TYPE_19 == 2
-#define CONF_DMAC_TYPE_19 1
-#define CONF_DMAC_DSYNC_19 1
-#endif
-
-#if CONF_DMAC_TRIGSRC_19 == 0xFF
-#define CONF_DMAC_SWREQ_19 1
-#else
-#define CONF_DMAC_SWREQ_19 0
-#endif
-
-/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
- * or fixed destination address mode, source and destination addresses are incremented
- * by 8-bit or 16-bit.
- * Workaround: The user can fix the problem by setting the source addressing mode to
- * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
- */
-#if (CONF_DMAC_CHANNEL_19_SETTINGS == 1 && CONF_DMAC_BEATSIZE_19 != 2                                                  \
-     && ((!CONF_DMAC_SRCINC_19) || (!CONF_DMAC_DSTINC_19)))
-#if (!CONF_DMAC_SRCINC_19)
-#define CONF_DMAC_SRC_STRIDE_19 ((int16_t)(-1))
-#endif
-#if (!CONF_DMAC_DSTINC_19)
-#define CONF_DMAC_DES_STRIDE_19 ((int16_t)(-1))
-#endif
-#endif
-
-#ifndef CONF_DMAC_SRC_STRIDE_19
-#define CONF_DMAC_SRC_STRIDE_19 0
-#endif
-
-#ifndef CONF_DMAC_DES_STRIDE_19
-#define CONF_DMAC_DES_STRIDE_19 0
-#endif
-
-// <e> Channel 20 settings
-// <id> dmac_channel_20_settings
-#ifndef CONF_DMAC_CHANNEL_20_SETTINGS
-#define CONF_DMAC_CHANNEL_20_SETTINGS 0
-#endif
-
-// <o> Burst Size
-// <0x0=> 1 burst size
-// <0x1=> 4 burst size
-// <0x2=> 8 burst size
-// <0x3=> 16 burst size
-// <i> Define the memory burst size
-// <id> dmac_burstsize_20
-#ifndef CONF_DMAC_BURSTSIZE_20
-#define CONF_DMAC_BURSTSIZE_20 0x0
-#endif
-
-// <o> Chunk Size
-// <0x0=> 1 data transferred
-// <0x1=> 2 data transferred
-// <0x2=> 4 data transferred
-// <0x3=> 8 data transferred
-// <0x4=> 16 data transferred
-// <i> Define the peripheral chunk size
-// <id> dmac_chunksize_20
-#ifndef CONF_DMAC_CHUNKSIZE_20
-#define CONF_DMAC_CHUNKSIZE_20 0x0
-#endif
-
-// <o> Beat Size
-// <0=> 8-bit bus transfer
-// <1=> 16-bit bus transfer
-// <2=> 32-bit bus transfer
-// <i> Defines the size of one beat
-// <id> dmac_beatsize_20
-#ifndef CONF_DMAC_BEATSIZE_20
-#define CONF_DMAC_BEATSIZE_20 0x0
-#endif
-
-// <o> Source Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is read through the system bus interface 0 or 1
-// <id> dma_src_interface_20
-#ifndef CONF_DMAC_SRC_INTERFACE_20
-#define CONF_DMAC_SRC_INTERFACE_20 0x0
-#endif
-
-// <o> Destination Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is written through the system bus interface 0 or 1
-// <id> dma_des_interface_20
-#ifndef CONF_DMAC_DES_INTERFACE_20
-#define CONF_DMAC_DES_INTERFACE_20 0x0
-#endif
-
-// <q> Source Address Increment
-// <i> Indicates whether the source address incremented as beat size or not
-// <id> dmac_srcinc_20
-#ifndef CONF_DMAC_SRCINC_20
-#define CONF_DMAC_SRCINC_20 0
-#endif
-
-// <q> Destination Address Increment
-// <i> Indicates whether the destination address incremented as beat size or not
-// <id> dmac_dstinc_20
-#ifndef CONF_DMAC_DSTINC_20
-#define CONF_DMAC_DSTINC_20 0
-#endif
-
-// <o> Transfer Type
-// <0x0=> Memory to Memory Transfer
-// <0x1=> Peripheral to Memory Transfer
-// <0x2=> Memory to Peripheral Transfer
-// <i> Define the data transfer type
-// <id> dma_trans_type_20
-#ifndef CONF_DMAC_TRANS_TYPE_20
-#define CONF_DMAC_TRANS_TYPE_20 0x0
-#endif
-
-// <o> Trigger source
-// <0xFF=> Software Trigger
-// <0x00=> HSMCI TX/RX Trigger
-// <0x01=> SPI0 TX Trigger
-// <0x02=> SPI0 RX Trigger
-// <0x03=> SPI1 TX Trigger
-// <0x04=> SPI1 RX Trigger
-// <0x05=> QSPI TX Trigger
-// <0x06=> QSPI RX Trigger
-// <0x07=> USART0 TX Trigger
-// <0x08=> USART0 RX Trigger
-// <0x09=> USART1 TX Trigger
-// <0x0A=> USART1 RX Trigger
-// <0x0B=> USART2 TX Trigger
-// <0x0C=> USART2 RX Trigger
-// <0x0D=> PWM0 TX Trigger
-// <0x0E=> TWIHS0 TX Trigger
-// <0x0F=> TWIHS0 RX Trigger
-// <0x10=> TWIHS1 TX Trigger
-// <0x11=> TWIHS1 RX Trigger
-// <0x12=> TWIHS2 TX Trigger
-// <0x13=> TWIHS2 RX Trigger
-// <0x14=> UART0 TX Trigger
-// <0x15=> UART0 RX Trigger
-// <0x16=> UART1 TX Trigger
-// <0x17=> UART1 RX Trigger
-// <0x18=> UART2 TX Trigger
-// <0x19=> UART2 RX Trigger
-// <0x1A=> UART3 TX Trigger
-// <0x1B=> UART3 RX Trigger
-// <0x1C=> UART4 TX Trigger
-// <0x1D=> UART4 RX Trigger
-// <0x1E=> DACC TX Trigger
-// <0x20=> SSC TX Trigger
-// <0x21=> SSC RX Trigger
-// <0x22=> PIOA RX Trigger
-// <0x23=> AFEC0 RX Trigger
-// <0x24=> AFEC1 RX Trigger
-// <0x25=> AES TX Trigger
-// <0x26=> AES RX Trigger
-// <0x27=> PWM1 TX Trigger
-// <0x28=> TC0 RX Trigger
-// <0x29=> TC3 RX Trigger
-// <0x2A=> TC6 RX Trigger
-// <0x2B=> TC9 RX Trigger
-// <0x2C=> I2SC0 TX Left Trigger
-// <0x2D=> I2SC0 RX Left Trigger
-// <0x2E=> I2SC1 TX Left Trigger
-// <0x2F=> I2SC1 RX Left Trigger
-// <0x30=> I2SC0 TX Right Trigger
-// <0x31=> I2SC0 RX Right Trigger
-// <0x32=> I2SC1 TX Right Trigger
-// <0x33=> I2SC1 RX Right Trigger
-// <i> Define the DMA trigger source
-// <id> dmac_trifsrc_20
-#ifndef CONF_DMAC_TRIGSRC_20
-#define CONF_DMAC_TRIGSRC_20 0xff
-#endif
-
-// </e>
-
-#if CONF_DMAC_TRANS_TYPE_20 == 0
-#define CONF_DMAC_TYPE_20 0
-#define CONF_DMAC_DSYNC_20 0
-#elif CONF_DMAC_TRANS_TYPE_20 == 1
-#define CONF_DMAC_TYPE_20 1
-#define CONF_DMAC_DSYNC_20 0
-#elif CONF_DMAC_TRANS_TYPE_20 == 2
-#define CONF_DMAC_TYPE_20 1
-#define CONF_DMAC_DSYNC_20 1
-#endif
-
-#if CONF_DMAC_TRIGSRC_20 == 0xFF
-#define CONF_DMAC_SWREQ_20 1
-#else
-#define CONF_DMAC_SWREQ_20 0
-#endif
-
-/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
- * or fixed destination address mode, source and destination addresses are incremented
- * by 8-bit or 16-bit.
- * Workaround: The user can fix the problem by setting the source addressing mode to
- * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
- */
-#if (CONF_DMAC_CHANNEL_20_SETTINGS == 1 && CONF_DMAC_BEATSIZE_20 != 2                                                  \
-     && ((!CONF_DMAC_SRCINC_20) || (!CONF_DMAC_DSTINC_20)))
-#if (!CONF_DMAC_SRCINC_20)
-#define CONF_DMAC_SRC_STRIDE_20 ((int16_t)(-1))
-#endif
-#if (!CONF_DMAC_DSTINC_20)
-#define CONF_DMAC_DES_STRIDE_20 ((int16_t)(-1))
-#endif
-#endif
-
-#ifndef CONF_DMAC_SRC_STRIDE_20
-#define CONF_DMAC_SRC_STRIDE_20 0
-#endif
-
-#ifndef CONF_DMAC_DES_STRIDE_20
-#define CONF_DMAC_DES_STRIDE_20 0
-#endif
-
-// <e> Channel 21 settings
-// <id> dmac_channel_21_settings
-#ifndef CONF_DMAC_CHANNEL_21_SETTINGS
-#define CONF_DMAC_CHANNEL_21_SETTINGS 0
-#endif
-
-// <o> Burst Size
-// <0x0=> 1 burst size
-// <0x1=> 4 burst size
-// <0x2=> 8 burst size
-// <0x3=> 16 burst size
-// <i> Define the memory burst size
-// <id> dmac_burstsize_21
-#ifndef CONF_DMAC_BURSTSIZE_21
-#define CONF_DMAC_BURSTSIZE_21 0x0
-#endif
-
-// <o> Chunk Size
-// <0x0=> 1 data transferred
-// <0x1=> 2 data transferred
-// <0x2=> 4 data transferred
-// <0x3=> 8 data transferred
-// <0x4=> 16 data transferred
-// <i> Define the peripheral chunk size
-// <id> dmac_chunksize_21
-#ifndef CONF_DMAC_CHUNKSIZE_21
-#define CONF_DMAC_CHUNKSIZE_21 0x0
-#endif
-
-// <o> Beat Size
-// <0=> 8-bit bus transfer
-// <1=> 16-bit bus transfer
-// <2=> 32-bit bus transfer
-// <i> Defines the size of one beat
-// <id> dmac_beatsize_21
-#ifndef CONF_DMAC_BEATSIZE_21
-#define CONF_DMAC_BEATSIZE_21 0x0
-#endif
-
-// <o> Source Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is read through the system bus interface 0 or 1
-// <id> dma_src_interface_21
-#ifndef CONF_DMAC_SRC_INTERFACE_21
-#define CONF_DMAC_SRC_INTERFACE_21 0x0
-#endif
-
-// <o> Destination Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is written through the system bus interface 0 or 1
-// <id> dma_des_interface_21
-#ifndef CONF_DMAC_DES_INTERFACE_21
-#define CONF_DMAC_DES_INTERFACE_21 0x0
-#endif
-
-// <q> Source Address Increment
-// <i> Indicates whether the source address incremented as beat size or not
-// <id> dmac_srcinc_21
-#ifndef CONF_DMAC_SRCINC_21
-#define CONF_DMAC_SRCINC_21 0
-#endif
-
-// <q> Destination Address Increment
-// <i> Indicates whether the destination address incremented as beat size or not
-// <id> dmac_dstinc_21
-#ifndef CONF_DMAC_DSTINC_21
-#define CONF_DMAC_DSTINC_21 0
-#endif
-
-// <o> Transfer Type
-// <0x0=> Memory to Memory Transfer
-// <0x1=> Peripheral to Memory Transfer
-// <0x2=> Memory to Peripheral Transfer
-// <i> Define the data transfer type
-// <id> dma_trans_type_21
-#ifndef CONF_DMAC_TRANS_TYPE_21
-#define CONF_DMAC_TRANS_TYPE_21 0x0
-#endif
-
-// <o> Trigger source
-// <0xFF=> Software Trigger
-// <0x00=> HSMCI TX/RX Trigger
-// <0x01=> SPI0 TX Trigger
-// <0x02=> SPI0 RX Trigger
-// <0x03=> SPI1 TX Trigger
-// <0x04=> SPI1 RX Trigger
-// <0x05=> QSPI TX Trigger
-// <0x06=> QSPI RX Trigger
-// <0x07=> USART0 TX Trigger
-// <0x08=> USART0 RX Trigger
-// <0x09=> USART1 TX Trigger
-// <0x0A=> USART1 RX Trigger
-// <0x0B=> USART2 TX Trigger
-// <0x0C=> USART2 RX Trigger
-// <0x0D=> PWM0 TX Trigger
-// <0x0E=> TWIHS0 TX Trigger
-// <0x0F=> TWIHS0 RX Trigger
-// <0x10=> TWIHS1 TX Trigger
-// <0x11=> TWIHS1 RX Trigger
-// <0x12=> TWIHS2 TX Trigger
-// <0x13=> TWIHS2 RX Trigger
-// <0x14=> UART0 TX Trigger
-// <0x15=> UART0 RX Trigger
-// <0x16=> UART1 TX Trigger
-// <0x17=> UART1 RX Trigger
-// <0x18=> UART2 TX Trigger
-// <0x19=> UART2 RX Trigger
-// <0x1A=> UART3 TX Trigger
-// <0x1B=> UART3 RX Trigger
-// <0x1C=> UART4 TX Trigger
-// <0x1D=> UART4 RX Trigger
-// <0x1E=> DACC TX Trigger
-// <0x20=> SSC TX Trigger
-// <0x21=> SSC RX Trigger
-// <0x22=> PIOA RX Trigger
-// <0x23=> AFEC0 RX Trigger
-// <0x24=> AFEC1 RX Trigger
-// <0x25=> AES TX Trigger
-// <0x26=> AES RX Trigger
-// <0x27=> PWM1 TX Trigger
-// <0x28=> TC0 RX Trigger
-// <0x29=> TC3 RX Trigger
-// <0x2A=> TC6 RX Trigger
-// <0x2B=> TC9 RX Trigger
-// <0x2C=> I2SC0 TX Left Trigger
-// <0x2D=> I2SC0 RX Left Trigger
-// <0x2E=> I2SC1 TX Left Trigger
-// <0x2F=> I2SC1 RX Left Trigger
-// <0x30=> I2SC0 TX Right Trigger
-// <0x31=> I2SC0 RX Right Trigger
-// <0x32=> I2SC1 TX Right Trigger
-// <0x33=> I2SC1 RX Right Trigger
-// <i> Define the DMA trigger source
-// <id> dmac_trifsrc_21
-#ifndef CONF_DMAC_TRIGSRC_21
-#define CONF_DMAC_TRIGSRC_21 0xff
-#endif
-
-// </e>
-
-#if CONF_DMAC_TRANS_TYPE_21 == 0
-#define CONF_DMAC_TYPE_21 0
-#define CONF_DMAC_DSYNC_21 0
-#elif CONF_DMAC_TRANS_TYPE_21 == 1
-#define CONF_DMAC_TYPE_21 1
-#define CONF_DMAC_DSYNC_21 0
-#elif CONF_DMAC_TRANS_TYPE_21 == 2
-#define CONF_DMAC_TYPE_21 1
-#define CONF_DMAC_DSYNC_21 1
-#endif
-
-#if CONF_DMAC_TRIGSRC_21 == 0xFF
-#define CONF_DMAC_SWREQ_21 1
-#else
-#define CONF_DMAC_SWREQ_21 0
-#endif
-
-/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
- * or fixed destination address mode, source and destination addresses are incremented
- * by 8-bit or 16-bit.
- * Workaround: The user can fix the problem by setting the source addressing mode to
- * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
- */
-#if (CONF_DMAC_CHANNEL_21_SETTINGS == 1 && CONF_DMAC_BEATSIZE_21 != 2                                                  \
-     && ((!CONF_DMAC_SRCINC_21) || (!CONF_DMAC_DSTINC_21)))
-#if (!CONF_DMAC_SRCINC_21)
-#define CONF_DMAC_SRC_STRIDE_21 ((int16_t)(-1))
-#endif
-#if (!CONF_DMAC_DSTINC_21)
-#define CONF_DMAC_DES_STRIDE_21 ((int16_t)(-1))
-#endif
-#endif
-
-#ifndef CONF_DMAC_SRC_STRIDE_21
-#define CONF_DMAC_SRC_STRIDE_21 0
-#endif
-
-#ifndef CONF_DMAC_DES_STRIDE_21
-#define CONF_DMAC_DES_STRIDE_21 0
-#endif
-
-// <e> Channel 22 settings
-// <id> dmac_channel_22_settings
-#ifndef CONF_DMAC_CHANNEL_22_SETTINGS
-#define CONF_DMAC_CHANNEL_22_SETTINGS 0
-#endif
-
-// <o> Burst Size
-// <0x0=> 1 burst size
-// <0x1=> 4 burst size
-// <0x2=> 8 burst size
-// <0x3=> 16 burst size
-// <i> Define the memory burst size
-// <id> dmac_burstsize_22
-#ifndef CONF_DMAC_BURSTSIZE_22
-#define CONF_DMAC_BURSTSIZE_22 0x0
-#endif
-
-// <o> Chunk Size
-// <0x0=> 1 data transferred
-// <0x1=> 2 data transferred
-// <0x2=> 4 data transferred
-// <0x3=> 8 data transferred
-// <0x4=> 16 data transferred
-// <i> Define the peripheral chunk size
-// <id> dmac_chunksize_22
-#ifndef CONF_DMAC_CHUNKSIZE_22
-#define CONF_DMAC_CHUNKSIZE_22 0x0
-#endif
-
-// <o> Beat Size
-// <0=> 8-bit bus transfer
-// <1=> 16-bit bus transfer
-// <2=> 32-bit bus transfer
-// <i> Defines the size of one beat
-// <id> dmac_beatsize_22
-#ifndef CONF_DMAC_BEATSIZE_22
-#define CONF_DMAC_BEATSIZE_22 0x0
-#endif
-
-// <o> Source Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is read through the system bus interface 0 or 1
-// <id> dma_src_interface_22
-#ifndef CONF_DMAC_SRC_INTERFACE_22
-#define CONF_DMAC_SRC_INTERFACE_22 0x0
-#endif
-
-// <o> Destination Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is written through the system bus interface 0 or 1
-// <id> dma_des_interface_22
-#ifndef CONF_DMAC_DES_INTERFACE_22
-#define CONF_DMAC_DES_INTERFACE_22 0x0
-#endif
-
-// <q> Source Address Increment
-// <i> Indicates whether the source address incremented as beat size or not
-// <id> dmac_srcinc_22
-#ifndef CONF_DMAC_SRCINC_22
-#define CONF_DMAC_SRCINC_22 0
-#endif
-
-// <q> Destination Address Increment
-// <i> Indicates whether the destination address incremented as beat size or not
-// <id> dmac_dstinc_22
-#ifndef CONF_DMAC_DSTINC_22
-#define CONF_DMAC_DSTINC_22 0
-#endif
-
-// <o> Transfer Type
-// <0x0=> Memory to Memory Transfer
-// <0x1=> Peripheral to Memory Transfer
-// <0x2=> Memory to Peripheral Transfer
-// <i> Define the data transfer type
-// <id> dma_trans_type_22
-#ifndef CONF_DMAC_TRANS_TYPE_22
-#define CONF_DMAC_TRANS_TYPE_22 0x0
-#endif
-
-// <o> Trigger source
-// <0xFF=> Software Trigger
-// <0x00=> HSMCI TX/RX Trigger
-// <0x01=> SPI0 TX Trigger
-// <0x02=> SPI0 RX Trigger
-// <0x03=> SPI1 TX Trigger
-// <0x04=> SPI1 RX Trigger
-// <0x05=> QSPI TX Trigger
-// <0x06=> QSPI RX Trigger
-// <0x07=> USART0 TX Trigger
-// <0x08=> USART0 RX Trigger
-// <0x09=> USART1 TX Trigger
-// <0x0A=> USART1 RX Trigger
-// <0x0B=> USART2 TX Trigger
-// <0x0C=> USART2 RX Trigger
-// <0x0D=> PWM0 TX Trigger
-// <0x0E=> TWIHS0 TX Trigger
-// <0x0F=> TWIHS0 RX Trigger
-// <0x10=> TWIHS1 TX Trigger
-// <0x11=> TWIHS1 RX Trigger
-// <0x12=> TWIHS2 TX Trigger
-// <0x13=> TWIHS2 RX Trigger
-// <0x14=> UART0 TX Trigger
-// <0x15=> UART0 RX Trigger
-// <0x16=> UART1 TX Trigger
-// <0x17=> UART1 RX Trigger
-// <0x18=> UART2 TX Trigger
-// <0x19=> UART2 RX Trigger
-// <0x1A=> UART3 TX Trigger
-// <0x1B=> UART3 RX Trigger
-// <0x1C=> UART4 TX Trigger
-// <0x1D=> UART4 RX Trigger
-// <0x1E=> DACC TX Trigger
-// <0x20=> SSC TX Trigger
-// <0x21=> SSC RX Trigger
-// <0x22=> PIOA RX Trigger
-// <0x23=> AFEC0 RX Trigger
-// <0x24=> AFEC1 RX Trigger
-// <0x25=> AES TX Trigger
-// <0x26=> AES RX Trigger
-// <0x27=> PWM1 TX Trigger
-// <0x28=> TC0 RX Trigger
-// <0x29=> TC3 RX Trigger
-// <0x2A=> TC6 RX Trigger
-// <0x2B=> TC9 RX Trigger
-// <0x2C=> I2SC0 TX Left Trigger
-// <0x2D=> I2SC0 RX Left Trigger
-// <0x2E=> I2SC1 TX Left Trigger
-// <0x2F=> I2SC1 RX Left Trigger
-// <0x30=> I2SC0 TX Right Trigger
-// <0x31=> I2SC0 RX Right Trigger
-// <0x32=> I2SC1 TX Right Trigger
-// <0x33=> I2SC1 RX Right Trigger
-// <i> Define the DMA trigger source
-// <id> dmac_trifsrc_22
-#ifndef CONF_DMAC_TRIGSRC_22
-#define CONF_DMAC_TRIGSRC_22 0xff
-#endif
-
-// </e>
-
-#if CONF_DMAC_TRANS_TYPE_22 == 0
-#define CONF_DMAC_TYPE_22 0
-#define CONF_DMAC_DSYNC_22 0
-#elif CONF_DMAC_TRANS_TYPE_22 == 1
-#define CONF_DMAC_TYPE_22 1
-#define CONF_DMAC_DSYNC_22 0
-#elif CONF_DMAC_TRANS_TYPE_22 == 2
-#define CONF_DMAC_TYPE_22 1
-#define CONF_DMAC_DSYNC_22 1
-#endif
-
-#if CONF_DMAC_TRIGSRC_22 == 0xFF
-#define CONF_DMAC_SWREQ_22 1
-#else
-#define CONF_DMAC_SWREQ_22 0
-#endif
-
-/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
- * or fixed destination address mode, source and destination addresses are incremented
- * by 8-bit or 16-bit.
- * Workaround: The user can fix the problem by setting the source addressing mode to
- * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
- */
-#if (CONF_DMAC_CHANNEL_22_SETTINGS == 1 && CONF_DMAC_BEATSIZE_22 != 2                                                  \
-     && ((!CONF_DMAC_SRCINC_22) || (!CONF_DMAC_DSTINC_22)))
-#if (!CONF_DMAC_SRCINC_22)
-#define CONF_DMAC_SRC_STRIDE_22 ((int16_t)(-1))
-#endif
-#if (!CONF_DMAC_DSTINC_22)
-#define CONF_DMAC_DES_STRIDE_22 ((int16_t)(-1))
-#endif
-#endif
-
-#ifndef CONF_DMAC_SRC_STRIDE_22
-#define CONF_DMAC_SRC_STRIDE_22 0
-#endif
-
-#ifndef CONF_DMAC_DES_STRIDE_22
-#define CONF_DMAC_DES_STRIDE_22 0
-#endif
-
-// <e> Channel 23 settings
-// <id> dmac_channel_23_settings
-#ifndef CONF_DMAC_CHANNEL_23_SETTINGS
-#define CONF_DMAC_CHANNEL_23_SETTINGS 0
-#endif
-
-// <o> Burst Size
-// <0x0=> 1 burst size
-// <0x1=> 4 burst size
-// <0x2=> 8 burst size
-// <0x3=> 16 burst size
-// <i> Define the memory burst size
-// <id> dmac_burstsize_23
-#ifndef CONF_DMAC_BURSTSIZE_23
-#define CONF_DMAC_BURSTSIZE_23 0x0
-#endif
-
-// <o> Chunk Size
-// <0x0=> 1 data transferred
-// <0x1=> 2 data transferred
-// <0x2=> 4 data transferred
-// <0x3=> 8 data transferred
-// <0x4=> 16 data transferred
-// <i> Define the peripheral chunk size
-// <id> dmac_chunksize_23
-#ifndef CONF_DMAC_CHUNKSIZE_23
-#define CONF_DMAC_CHUNKSIZE_23 0x0
-#endif
-
-// <o> Beat Size
-// <0=> 8-bit bus transfer
-// <1=> 16-bit bus transfer
-// <2=> 32-bit bus transfer
-// <i> Defines the size of one beat
-// <id> dmac_beatsize_23
-#ifndef CONF_DMAC_BEATSIZE_23
-#define CONF_DMAC_BEATSIZE_23 0x0
-#endif
-
-// <o> Source Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is read through the system bus interface 0 or 1
-// <id> dma_src_interface_23
-#ifndef CONF_DMAC_SRC_INTERFACE_23
-#define CONF_DMAC_SRC_INTERFACE_23 0x0
-#endif
-
-// <o> Destination Interface Identifier
-// <0x0=> AHB_IF0
-// <0x1=> AHB_IF1
-// <i> Define the data is written through the system bus interface 0 or 1
-// <id> dma_des_interface_23
-#ifndef CONF_DMAC_DES_INTERFACE_23
-#define CONF_DMAC_DES_INTERFACE_23 0x0
-#endif
-
-// <q> Source Address Increment
-// <i> Indicates whether the source address incremented as beat size or not
-// <id> dmac_srcinc_23
-#ifndef CONF_DMAC_SRCINC_23
-#define CONF_DMAC_SRCINC_23 0
-#endif
-
-// <q> Destination Address Increment
-// <i> Indicates whether the destination address incremented as beat size or not
-// <id> dmac_dstinc_23
-#ifndef CONF_DMAC_DSTINC_23
-#define CONF_DMAC_DSTINC_23 0
-#endif
-
-// <o> Transfer Type
-// <0x0=> Memory to Memory Transfer
-// <0x1=> Peripheral to Memory Transfer
-// <0x2=> Memory to Peripheral Transfer
-// <i> Define the data transfer type
-// <id> dma_trans_type_23
-#ifndef CONF_DMAC_TRANS_TYPE_23
-#define CONF_DMAC_TRANS_TYPE_23 0x0
-#endif
-
-// <o> Trigger source
-// <0xFF=> Software Trigger
-// <0x00=> HSMCI TX/RX Trigger
-// <0x01=> SPI0 TX Trigger
-// <0x02=> SPI0 RX Trigger
-// <0x03=> SPI1 TX Trigger
-// <0x04=> SPI1 RX Trigger
-// <0x05=> QSPI TX Trigger
-// <0x06=> QSPI RX Trigger
-// <0x07=> USART0 TX Trigger
-// <0x08=> USART0 RX Trigger
-// <0x09=> USART1 TX Trigger
-// <0x0A=> USART1 RX Trigger
-// <0x0B=> USART2 TX Trigger
-// <0x0C=> USART2 RX Trigger
-// <0x0D=> PWM0 TX Trigger
-// <0x0E=> TWIHS0 TX Trigger
-// <0x0F=> TWIHS0 RX Trigger
-// <0x10=> TWIHS1 TX Trigger
-// <0x11=> TWIHS1 RX Trigger
-// <0x12=> TWIHS2 TX Trigger
-// <0x13=> TWIHS2 RX Trigger
-// <0x14=> UART0 TX Trigger
-// <0x15=> UART0 RX Trigger
-// <0x16=> UART1 TX Trigger
-// <0x17=> UART1 RX Trigger
-// <0x18=> UART2 TX Trigger
-// <0x19=> UART2 RX Trigger
-// <0x1A=> UART3 TX Trigger
-// <0x1B=> UART3 RX Trigger
-// <0x1C=> UART4 TX Trigger
-// <0x1D=> UART4 RX Trigger
-// <0x1E=> DACC TX Trigger
-// <0x20=> SSC TX Trigger
-// <0x21=> SSC RX Trigger
-// <0x22=> PIOA RX Trigger
-// <0x23=> AFEC0 RX Trigger
-// <0x24=> AFEC1 RX Trigger
-// <0x25=> AES TX Trigger
-// <0x26=> AES RX Trigger
-// <0x27=> PWM1 TX Trigger
-// <0x28=> TC0 RX Trigger
-// <0x29=> TC3 RX Trigger
-// <0x2A=> TC6 RX Trigger
-// <0x2B=> TC9 RX Trigger
-// <0x2C=> I2SC0 TX Left Trigger
-// <0x2D=> I2SC0 RX Left Trigger
-// <0x2E=> I2SC1 TX Left Trigger
-// <0x2F=> I2SC1 RX Left Trigger
-// <0x30=> I2SC0 TX Right Trigger
-// <0x31=> I2SC0 RX Right Trigger
-// <0x32=> I2SC1 TX Right Trigger
-// <0x33=> I2SC1 RX Right Trigger
-// <i> Define the DMA trigger source
-// <id> dmac_trifsrc_23
-#ifndef CONF_DMAC_TRIGSRC_23
-#define CONF_DMAC_TRIGSRC_23 0xff
-#endif
-
-// </e>
-
-#if CONF_DMAC_TRANS_TYPE_23 == 0
-#define CONF_DMAC_TYPE_23 0
-#define CONF_DMAC_DSYNC_23 0
-#elif CONF_DMAC_TRANS_TYPE_23 == 1
-#define CONF_DMAC_TYPE_23 1
-#define CONF_DMAC_DSYNC_23 0
-#elif CONF_DMAC_TRANS_TYPE_23 == 2
-#define CONF_DMAC_TYPE_23 1
-#define CONF_DMAC_DSYNC_23 1
-#endif
-
-#if CONF_DMAC_TRIGSRC_23 == 0xFF
-#define CONF_DMAC_SWREQ_23 1
-#else
-#define CONF_DMAC_SWREQ_23 0
-#endif
-
-/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
- * or fixed destination address mode, source and destination addresses are incremented
- * by 8-bit or 16-bit.
- * Workaround: The user can fix the problem by setting the source addressing mode to
- * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
- */
-#if (CONF_DMAC_CHANNEL_23_SETTINGS == 1 && CONF_DMAC_BEATSIZE_23 != 2                                                  \
-     && ((!CONF_DMAC_SRCINC_23) || (!CONF_DMAC_DSTINC_23)))
-#if (!CONF_DMAC_SRCINC_23)
-#define CONF_DMAC_SRC_STRIDE_23 ((int16_t)(-1))
-#endif
-#if (!CONF_DMAC_DSTINC_23)
-#define CONF_DMAC_DES_STRIDE_23 ((int16_t)(-1))
-#endif
-#endif
-
-#ifndef CONF_DMAC_SRC_STRIDE_23
-#define CONF_DMAC_SRC_STRIDE_23 0
-#endif
-
-#ifndef CONF_DMAC_DES_STRIDE_23
-#define CONF_DMAC_DES_STRIDE_23 0
-#endif
-
-// </e>
-
-// <<< end of configuration section >>>
-
-#endif // HPL_XDMAC_CONFIG_H
diff --git a/tinyusb/hw/bsp/same70_xplained/peripheral_clk_config.h b/tinyusb/hw/bsp/same70_xplained/peripheral_clk_config.h
deleted file mode 100755
index 84756f5a..00000000
--- a/tinyusb/hw/bsp/same70_xplained/peripheral_clk_config.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/* Auto-generated config file peripheral_clk_config.h */
-#ifndef PERIPHERAL_CLK_CONFIG_H
-#define PERIPHERAL_CLK_CONFIG_H
-
-// <<< Use Configuration Wizard in Context Menu >>>
-
-/**
- * \def CONF_HCLK_FREQUENCY
- * \brief HCLK's Clock frequency
- */
-#ifndef CONF_HCLK_FREQUENCY
-#define CONF_HCLK_FREQUENCY 300000000
-#endif
-
-/**
- * \def CONF_FCLK_FREQUENCY
- * \brief FCLK's Clock frequency
- */
-#ifndef CONF_FCLK_FREQUENCY
-#define CONF_FCLK_FREQUENCY 300000000
-#endif
-
-/**
- * \def CONF_CPU_FREQUENCY
- * \brief CPU's Clock frequency
- */
-#ifndef CONF_CPU_FREQUENCY
-#define CONF_CPU_FREQUENCY 300000000
-#endif
-
-/**
- * \def CONF_SLCK_FREQUENCY
- * \brief Slow Clock frequency
- */
-#define CONF_SLCK_FREQUENCY 0
-
-/**
- * \def CONF_MCK_FREQUENCY
- * \brief Master Clock frequency
- */
-#define CONF_MCK_FREQUENCY 150000000
-
-/**
- * \def CONF_PCK6_FREQUENCY
- * \brief Programmable Clock Controller 6 frequency
- */
-#define CONF_PCK6_FREQUENCY 1714285
-
-// <h> USART Clock Settings
-// <o> USART Clock source
-
-// <0=> Master Clock (MCK)
-// <1=> MCK / 8 for USART
-// <2=> Programmable Clock Controller 4 (PMC_PCK4)
-// <3=> External Clock
-// <i> This defines the clock source for the USART
-// <id> usart_clock_source
-#ifndef CONF_USART1_CK_SRC
-#define CONF_USART1_CK_SRC 0
-#endif
-
-// <o> USART External Clock Input on SCK <1-4294967295>
-// <i> Inputs the external clock frequency on SCK
-// <id> usart_clock_freq
-#ifndef CONF_USART1_SCK_FREQ
-#define CONF_USART1_SCK_FREQ 10000000
-#endif
-
-// </h>
-
-/**
- * \def USART FREQUENCY
- * \brief USART's Clock frequency
- */
-#ifndef CONF_USART1_FREQUENCY
-#define CONF_USART1_FREQUENCY 150000000
-#endif
-
-#ifndef CONF_SRC_USB_480M
-#define CONF_SRC_USB_480M 0
-#endif
-
-#ifndef CONF_SRC_USB_48M
-#define CONF_SRC_USB_48M 1
-#endif
-
-// <y> USB Full/Low Speed Clock
-// <CONF_SRC_USB_48M"> USB Clock Controller (USB_48M)
-// <id> usb_fsls_clock_source
-// <i> 48MHz clock source for low speed and full speed.
-// <i> It must be available when low speed is supported by host driver.
-// <i> It must be available when low power mode is selected.
-#ifndef CONF_USBHS_FSLS_SRC
-#define CONF_USBHS_FSLS_SRC CONF_SRC_USB_48M
-#endif
-
-// <y> USB Clock Source(Normal/Low-power Mode Selection)
-// <CONF_SRC_USB_480M"> USB High Speed Clock (USB_480M)
-// <CONF_SRC_USB_48M"> USB Clock Controller (USB_48M)
-// <id> usb_clock_source
-// <i> Select the clock source for USB.
-// <i> In normal mode, use "USB High Speed Clock (USB_480M)".
-// <i> In low-power mode, use "USB Clock Controller (USB_48M)".
-#ifndef CONF_USBHS_SRC
-#define CONF_USBHS_SRC CONF_SRC_USB_480M
-#endif
-
-/**
- * \def CONF_USBHS_FSLS_FREQUENCY
- * \brief USBHS's Full/Low Speed Clock Source frequency
- */
-#ifndef CONF_USBHS_FSLS_FREQUENCY
-#define CONF_USBHS_FSLS_FREQUENCY 48000000
-#endif
-
-/**
- * \def CONF_USBHS_FREQUENCY
- * \brief USBHS's Selected Clock Source frequency
- */
-#ifndef CONF_USBHS_FREQUENCY
-#define CONF_USBHS_FREQUENCY 480000000
-#endif
-
-// <<< end of configuration section >>>
-
-#endif // PERIPHERAL_CLK_CONFIG_H
diff --git a/tinyusb/hw/bsp/same70_xplained/same70_xplained.c b/tinyusb/hw/bsp/same70_xplained/same70_xplained.c
deleted file mode 100755
index e6e7db0f..00000000
--- a/tinyusb/hw/bsp/same70_xplained/same70_xplained.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2019, hathach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- */
-
-#include "sam.h"
-#include "bsp/board.h"
-
-#include "peripheral_clk_config.h"
-#include "hpl/usart/hpl_usart_base.h"
-#include "hpl/pmc/hpl_pmc.h"
-#include "hal/include/hal_init.h"
-#include "hal/include/hal_usart_async.h"
-#include "hal/include/hal_gpio.h"
-
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-
-#define LED_PIN               GPIO(GPIO_PORTC, 8)
-
-#define BUTTON_PIN            GPIO(GPIO_PORTA, 11)
-#define BUTTON_STATE_ACTIVE   0
-
-#define UART_TX_PIN           GPIO(GPIO_PORTB, 4)
-#define UART_RX_PIN           GPIO(GPIO_PORTA, 21)
-
-static struct usart_async_descriptor edbg_com;
-static uint8_t edbg_com_buffer[64];
-static volatile bool uart_busy = false;
-
-static void tx_cb_EDBG_COM(const struct usart_async_descriptor *const io_descr)
-{
-  (void) io_descr;
-  uart_busy = false;
-}
-
-//------------- IMPLEMENTATION -------------//
-void board_init(void)
-{
-  init_mcu();
-
-  /* Disable Watchdog */
-  hri_wdt_set_MR_WDDIS_bit(WDT);
-
-  // LED
-  _pmc_enable_periph_clock(ID_PIOC);
-  gpio_set_pin_level(LED_PIN, false);
-  gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
-  gpio_set_pin_function(LED_PIN, GPIO_PIN_FUNCTION_OFF);
-
-  // Button
-  _pmc_enable_periph_clock(ID_PIOA);
-  gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
-  gpio_set_pin_pull_mode(BUTTON_PIN, GPIO_PULL_UP);
-  gpio_set_pin_function(BUTTON_PIN, GPIO_PIN_FUNCTION_OFF);
-
-  // Uart via EDBG Com
-  _pmc_enable_periph_clock(ID_USART1);
-  gpio_set_pin_function(UART_RX_PIN, MUX_PA21A_USART1_RXD1);
-  gpio_set_pin_function(UART_TX_PIN, MUX_PB4D_USART1_TXD1);
-
-  usart_async_init(&edbg_com, USART1, edbg_com_buffer, sizeof(edbg_com_buffer), _usart_get_usart_async());
-  usart_async_set_baud_rate(&edbg_com, CFG_BOARD_UART_BAUDRATE);
-  usart_async_register_callback(&edbg_com, USART_ASYNC_TXC_CB, tx_cb_EDBG_COM);
-  usart_async_enable(&edbg_com);
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-  // 1ms tick timer (samd SystemCoreClock may not correct)
-  SysTick_Config(CONF_CPU_FREQUENCY / 1000);
-#endif
-
-  // Enable USB clock
-  _pmc_enable_periph_clock(ID_USBHS);
-
-}
-
-//--------------------------------------------------------------------+
-// USB Interrupt Handler
-//--------------------------------------------------------------------+
-void USBHS_Handler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  gpio_set_pin_level(LED_PIN, state);
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == gpio_get_pin_level(BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  // while until previous transfer is complete
-  while(uart_busy) {}
-  uart_busy = true;
-
-  io_write(&edbg_com.io, buf, len);
-  return len;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
-}
diff --git a/tinyusb/hw/bsp/samg55xplained/board.mk b/tinyusb/hw/bsp/samg55xplained/board.mk
deleted file mode 100755
index aed4de68..00000000
--- a/tinyusb/hw/bsp/samg55xplained/board.mk
+++ /dev/null
@@ -1,52 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/microchip
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib -nostartfiles \
-  -D__SAMG55J19__ \
-  -DCFG_TUSB_MCU=OPT_MCU_SAMG
-
-# suppress following warnings from mcu driver
-CFLAGS += -Wno-error=undef
-
-ASF_DIR = hw/mcu/microchip/samg55
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/samg55j19_flash.ld
-
-SRC_C += \
-	src/portable/microchip/samg/dcd_samg.c \
-	$(ASF_DIR)/samg55/gcc/gcc/startup_samg55.c \
-	$(ASF_DIR)/samg55/gcc/system_samg55.c \
-	$(ASF_DIR)/hpl/core/hpl_init.c \
-	$(ASF_DIR)/hpl/usart/hpl_usart.c \
-	$(ASF_DIR)/hpl/pmc/hpl_pmc.c \
-	$(ASF_DIR)/hal/src/hal_atomic.c
-
-INC += \
-  $(TOP)/hw/bsp/$(BOARD) \
-	$(TOP)/$(ASF_DIR) \
-	$(TOP)/$(ASF_DIR)/config \
-	$(TOP)/$(ASF_DIR)/samg55/include \
-	$(TOP)/$(ASF_DIR)/hal/include \
-	$(TOP)/$(ASF_DIR)/hal/utils/include \
-	$(TOP)/$(ASF_DIR)/hpl/core \
-	$(TOP)/$(ASF_DIR)/hpl/pio \
-	$(TOP)/$(ASF_DIR)/hpl/pmc \
-	$(TOP)/$(ASF_DIR)/hri \
-	$(TOP)/$(ASF_DIR)/CMSIS/Core/Include
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAMG55J19
-
-# flash using edbg from https://github.com/ataradov/edbg
-flash: $(BUILD)/$(PROJECT).bin
-	edbg --verbose -t samg55 -pv -f $< 
diff --git a/tinyusb/hw/bsp/samg55xplained/hpl_usart_config.h b/tinyusb/hw/bsp/samg55xplained/hpl_usart_config.h
deleted file mode 100755
index 4f2837d2..00000000
--- a/tinyusb/hw/bsp/samg55xplained/hpl_usart_config.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/* Auto-generated config file hpl_usart_config.h */
-#ifndef HPL_USART_CONFIG_H
-#define HPL_USART_CONFIG_H
-
-// <<< Use Configuration Wizard in Context Menu >>>
-
-#include <peripheral_clk_config.h>
-
-#ifndef CONF_USART_7_ENABLE
-#define CONF_USART_7_ENABLE 1
-#endif
-
-// <h> Basic Configuration
-
-// <o> Frame parity
-// <0x0=>Even parity
-// <0x1=>Odd parity
-// <0x2=>Parity forced to 0
-// <0x3=>Parity forced to 1
-// <0x4=>No parity
-// <i> Parity bit mode for USART frame
-// <id> usart_parity
-#ifndef CONF_USART_7_PARITY
-#define CONF_USART_7_PARITY 0x4
-#endif
-
-// <o> Character Size
-// <0x0=>5 bits
-// <0x1=>6 bits
-// <0x2=>7 bits
-// <0x3=>8 bits
-// <i> Data character size in USART frame
-// <id> usart_character_size
-#ifndef CONF_USART_7_CHSIZE
-#define CONF_USART_7_CHSIZE 0x3
-#endif
-
-// <o> Stop Bit
-// <0=>1 stop bit
-// <1=>1.5 stop bits
-// <2=>2 stop bits
-// <i> Number of stop bits in USART frame
-// <id> usart_stop_bit
-#ifndef CONF_USART_7_SBMODE
-#define CONF_USART_7_SBMODE 0
-#endif
-
-// <o> Clock Output Select
-// <0=>The USART does not drive the SCK pin
-// <1=>The USART drives the SCK pin if USCLKS does not select the external clock SCK
-// <i> Clock Output Select in USART sck, if in usrt master mode, please drive SCK.
-// <id> usart_clock_output_select
-#ifndef CONF_USART_7_CLKO
-#define CONF_USART_7_CLKO 0
-#endif
-
-// <o> Baud rate <1-3000000>
-// <i> USART baud rate setting
-// <id> usart_baud_rate
-#ifndef CONF_USART_7_BAUD
-#define CONF_USART_7_BAUD 9600
-#endif
-
-// </h>
-
-// <e> Advanced configuration
-// <id> usart_advanced
-#ifndef CONF_USART_7_ADVANCED_CONFIG
-#define CONF_USART_7_ADVANCED_CONFIG 0
-#endif
-
-// <o> Channel Mode
-// <0=>Normal Mode
-// <1=>Automatic Echo
-// <2=>Local Loopback
-// <3=>Remote Loopback
-// <i> Channel mode in USART frame
-// <id> usart_channel_mode
-#ifndef CONF_USART_7_CHMODE
-#define CONF_USART_7_CHMODE 0
-#endif
-
-// <q> 9 bits character enable
-// <i> Enable 9 bits character, this has high priority than 5/6/7/8 bits.
-// <id> usart_9bits_enable
-#ifndef CONF_USART_7_MODE9
-#define CONF_USART_7_MODE9 0
-#endif
-
-// <o> Variable Sync
-// <0=>User defined configuration
-// <1=>sync field is updated when a character is written into US_THR
-// <i> Variable Synchronization of Command/Data Sync Start Frarm Delimiter
-// <id> variable_sync
-#ifndef CONF_USART_7_VAR_SYNC
-#define CONF_USART_7_VAR_SYNC 0
-#endif
-
-// <o> Oversampling Mode
-// <0=>16 Oversampling
-// <1=>8 Oversampling
-// <i> Oversampling Mode in UART mode
-// <id> usart__oversampling_mode
-#ifndef CONF_USART_7_OVER
-#define CONF_USART_7_OVER 0
-#endif
-
-// <o> Inhibit Non Ack
-// <0=>The NACK is generated
-// <1=>The NACK is not generated
-// <i> Inhibit Non Acknowledge
-// <id> usart__inack
-#ifndef CONF_USART_7_INACK
-#define CONF_USART_7_INACK 1
-#endif
-
-// <o> Disable Successive NACK
-// <0=>NACK is sent on the ISO line as soon as a parity error occurs
-// <1=>Many parity errors generate a NACK on the ISO line
-// <i> Disable Successive NACK
-// <id> usart_dsnack
-#ifndef CONF_USART_7_DSNACK
-#define CONF_USART_7_DSNACK 0
-#endif
-
-// <o> Inverted Data
-// <0=>Data isn't inverted, nomal mode
-// <1=>Data is inverted
-// <i> Inverted Data
-// <id> usart_invdata
-#ifndef CONF_USART_7_INVDATA
-#define CONF_USART_7_INVDATA 0
-#endif
-
-// <o> Maximum Number of Automatic Iteration <0-7>
-// <i> Defines the maximum number of iterations in mode ISO7816, protocol T = 0.
-// <id> usart_max_iteration
-#ifndef CONF_USART_7_MAX_ITERATION
-#define CONF_USART_7_MAX_ITERATION 0
-#endif
-
-// <q> Receive Line Filter enable
-// <i> whether the USART filters the receive line using a three-sample filter
-// <id> usart_receive_filter_enable
-#ifndef CONF_USART_7_FILTER
-#define CONF_USART_7_FILTER 0
-#endif
-
-// <q> Manchester Encoder/Decoder Enable
-// <i> whether the USART Manchester Encoder/Decoder
-// <id> usart_manchester_filter_enable
-#ifndef CONF_USART_7_MAN
-#define CONF_USART_7_MAN 0
-#endif
-
-// <o> Manchester Synchronization Mode
-// <0=>The Manchester start bit is a 0 to 1 transition
-// <1=>The Manchester start bit is a 1 to 0 transition
-// <i> Manchester Synchronization Mode
-// <id> usart_manchester_synchronization_mode
-#ifndef CONF_USART_7_MODSYNC
-#define CONF_USART_7_MODSYNC 0
-#endif
-
-// <o> Start Frame Delimiter Selector
-// <0=>Start frame delimiter is COMMAND or DATA SYNC
-// <1=>Start frame delimiter is one bit
-// <i> Start Frame Delimiter Selector
-// <id> usart_start_frame_delimiter
-#ifndef CONF_USART_7_ONEBIT
-#define CONF_USART_7_ONEBIT 0
-#endif
-
-// <o> Fractional Part <0-7>
-// <i> Fractional part of the baud rate if baud rate generator is in fractional mode
-// <id> usart_arch_fractional
-#ifndef CONF_USART_7_FRACTIONAL
-#define CONF_USART_7_FRACTIONAL 0x0
-#endif
-
-// <o> Data Order
-// <0=>LSB is transmitted first
-// <1=>MSB is transmitted first
-// <i> Data order of the data bits in the frame
-// <id> usart_arch_msbf
-#ifndef CONF_USART_7_MSBF
-#define CONF_USART_7_MSBF 0
-#endif
-
-// </e>
-
-#define CONF_USART_7_MODE 0x0
-
-// Calculate BAUD register value in UART mode
-#if CONF_FLEXCOM7_CK_SRC < 3
-#ifndef CONF_USART_7_BAUD_CD
-#define CONF_USART_7_BAUD_CD ((CONF_FLEXCOM7_FREQUENCY) / CONF_USART_7_BAUD / 8 / (2 - CONF_USART_7_OVER))
-#endif
-#ifndef CONF_USART_7_BAUD_FP
-#define CONF_USART_7_BAUD_FP                                                                                           \
-	((CONF_FLEXCOM7_FREQUENCY) / CONF_USART_7_BAUD / (2 - CONF_USART_7_OVER) - 8 * CONF_USART_7_BAUD_CD)
-#endif
-#elif CONF_FLEXCOM7_CK_SRC == 3
-// No division is active. The value written in US_BRGR has no effect.
-#ifndef CONF_USART_7_BAUD_CD
-#define CONF_USART_7_BAUD_CD 1
-#endif
-#ifndef CONF_USART_7_BAUD_FP
-#define CONF_USART_7_BAUD_FP 1
-#endif
-#endif
-
-// <<< end of configuration section >>>
-
-#endif // HPL_USART_CONFIG_H
diff --git a/tinyusb/hw/bsp/samg55xplained/peripheral_clk_config.h b/tinyusb/hw/bsp/samg55xplained/peripheral_clk_config.h
deleted file mode 100755
index 6d390f38..00000000
--- a/tinyusb/hw/bsp/samg55xplained/peripheral_clk_config.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Auto-generated config file peripheral_clk_config.h */
-#ifndef PERIPHERAL_CLK_CONFIG_H
-#define PERIPHERAL_CLK_CONFIG_H
-
-// <<< Use Configuration Wizard in Context Menu >>>
-
-/**
- * \def CONF_HCLK_FREQUENCY
- * \brief HCLK's Clock frequency
- */
-#ifndef CONF_HCLK_FREQUENCY
-#define CONF_HCLK_FREQUENCY 8000000
-#endif
-
-/**
- * \def CONF_FCLK_FREQUENCY
- * \brief FCLK's Clock frequency
- */
-#ifndef CONF_FCLK_FREQUENCY
-#define CONF_FCLK_FREQUENCY 8000000
-#endif
-
-/**
- * \def CONF_CPU_FREQUENCY
- * \brief CPU's Clock frequency
- */
-#ifndef CONF_CPU_FREQUENCY
-#define CONF_CPU_FREQUENCY 8000000
-#endif
-
-/**
- * \def CONF_SLCK_FREQUENCY
- * \brief Slow Clock frequency
- */
-#define CONF_SLCK_FREQUENCY 32768
-
-/**
- * \def CONF_MCK_FREQUENCY
- * \brief Master Clock frequency
- */
-#define CONF_MCK_FREQUENCY 8000000
-
-// <o> USB Clock Source
-// <0=> USB Clock Controller (USB_48M)
-// <id> usb_clock_source
-// <i> Select the clock source for USB.
-#ifndef CONF_UDP_SRC
-#define CONF_UDP_SRC 0
-#endif
-
-/**
- * \def CONF_UDP_FREQUENCY
- * \brief UDP's Clock frequency
- */
-#ifndef CONF_UDP_FREQUENCY
-#define CONF_UDP_FREQUENCY 48005120
-#endif
-
-// <h> FLEXCOM Clock Settings
-// <o> FLEXCOM Clock source
-// <0=> Master Clock (MCK)
-// <1=> MCK / 8
-// <2=> Programmable Clock Controller 6 (PMC_PCK6)
-// <2=> Programmable Clock Controller 7 (PMC_PCK7)
-// <3=> External Clock
-// <i> This defines the clock source for the FLEXCOM, PCK6 is used for FLEXCOM0/1/2/3 and PCK7 is used for FLEXCOM4/5/6/7
-// <id> flexcom_clock_source
-#ifndef CONF_FLEXCOM7_CK_SRC
-#define CONF_FLEXCOM7_CK_SRC 0
-#endif
-
-// <o> FLEXCOM External Clock Input on SCK <1-4294967295>
-// <i> Inputs the external clock frequency on SCK
-// <id> flexcom_clock_freq
-#ifndef CONF_FLEXCOM7_SCK_FREQ
-#define CONF_FLEXCOM7_SCK_FREQ 10000000
-#endif
-
-#ifndef CONF_FLEXCOM7_FREQUENCY
-#define CONF_FLEXCOM7_FREQUENCY 8000000
-#endif
-
-// <<< end of configuration section >>>
-
-#endif // PERIPHERAL_CLK_CONFIG_H
diff --git a/tinyusb/hw/bsp/samg55xplained/samg55j19_flash.ld b/tinyusb/hw/bsp/samg55xplained/samg55j19_flash.ld
deleted file mode 100755
index 21c0b5bc..00000000
--- a/tinyusb/hw/bsp/samg55xplained/samg55j19_flash.ld
+++ /dev/null
@@ -1,158 +0,0 @@
-/**
- * \file
- *
- * \brief GCC linker script (flash) for ATSAMG55J19
- *
- * Copyright (c) 2017 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
- *
- * \license_start
- *
- * \page License
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *   http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \license_stop
- *
- */
-
-/*------------------------------------------------------------------------------
- *      Linker script for running in internal FLASH on the ATSAMG55J19
- *----------------------------------------------------------------------------*/
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-    rom (rx)    : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* rom, 524288K */
-    ram (rwx)   : ORIGIN = 0x20000000, LENGTH = 0x00028000 /* ram, 163840K */
-}
-
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
-
-/* The heapsize used by the application. NOTE: you need to adjust according to your application. */
-HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200;
-
-/* Section Definitions */
-SECTIONS
-{
-    .text :
-    {
-        . = ALIGN(4);
-        _sfixed = .;
-        KEEP(*(.vectors .vectors.*))
-        *(.text .text.* .gnu.linkonce.t.*)
-        *(.glue_7t) *(.glue_7)
-        *(.rodata .rodata* .gnu.linkonce.r.*)
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-
-        /* Support C constructors, and C destructors in both user code
-           and the C library. This also provides support for C++ code. */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-
-        . = ALIGN(0x4);
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-
-        . = ALIGN(4);
-        KEEP(*(.fini))
-
-        . = ALIGN(4);
-        __fini_array_start = .;
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        __fini_array_end = .;
-
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-
-        . = ALIGN(4);
-        _efixed = .;            /* End of text section */
-    } > rom
-
-    /* .ARM.exidx is sorted, so has to go in its own output section.  */
-    PROVIDE_HIDDEN (__exidx_start = .);
-    .ARM.exidx :
-    {
-      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > rom
-    PROVIDE_HIDDEN (__exidx_end = .);
-
-    . = ALIGN(4);
-    _etext = .;
-
-    .relocate : AT (_etext)
-    {
-        . = ALIGN(4);
-        _srelocate = .;
-        *(.ramfunc .ramfunc.*);
-        *(.data .data.*);
-        . = ALIGN(4);
-        _erelocate = .;
-    } > ram
-
-    /* .bss section which is used for uninitialized data */
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        _sbss = . ;
-        _szero = .;
-        *(.bss .bss.*)
-        *(COMMON)
-        . = ALIGN(4);
-        _ebss = . ;
-        _ezero = .;
-        end = .;
-    } > ram
-
-    /* heap section */
-    .heap (NOLOAD):
-    {
-        . = ALIGN(8);
-         _sheap = .;
-        . = . + HEAP_SIZE;
-        . = ALIGN(8);
-        _eheap = .;
-    } > ram
-
-    /* stack section */
-    .stack (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sstack = .;
-        . = . + STACK_SIZE;
-        . = ALIGN(8);
-        _estack = .;
-    } > ram
-
-    . = ALIGN(4);
-    _end = . ;
-    _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ;
-}
diff --git a/tinyusb/hw/bsp/samg55xplained/samg55xplained.c b/tinyusb/hw/bsp/samg55xplained/samg55xplained.c
deleted file mode 100755
index ed106b06..00000000
--- a/tinyusb/hw/bsp/samg55xplained/samg55xplained.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019, hathach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- */
-
-#include "sam.h"
-#include "bsp/board.h"
-
-#include "peripheral_clk_config.h"
-#include "hal/include/hal_init.h"
-#include "hal/include/hpl_usart_sync.h"
-#include "hpl/pmc/hpl_pmc.h"
-#include "hal/include/hal_gpio.h"
-
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-
-#define LED_PIN               GPIO(GPIO_PORTA, 6)
-
-#define BUTTON_PIN            GPIO(GPIO_PORTA, 2)
-#define BUTTON_STATE_ACTIVE   0
-
-#define UART_TX_PIN           GPIO(GPIO_PORTA, 28)
-#define UART_RX_PIN           GPIO(GPIO_PORTA, 27)
-
-struct _usart_sync_device edbg_com;
-
-//------------- IMPLEMENTATION -------------//
-void board_init(void)
-{
-	init_mcu();
-
-	_pmc_enable_periph_clock(ID_PIOA);
-
-	/* Disable Watchdog */
-	hri_wdt_set_MR_WDDIS_bit(WDT);
-
-	// LED
-	gpio_set_pin_level(LED_PIN, false);
-	gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
-	gpio_set_pin_function(LED_PIN, GPIO_PIN_FUNCTION_OFF);
-
-	// Button
-	gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
-	gpio_set_pin_pull_mode(BUTTON_PIN, GPIO_PULL_UP);
-	gpio_set_pin_function(BUTTON_PIN, GPIO_PIN_FUNCTION_OFF);
-
-	// Uart via EDBG Com
-	_pmc_enable_periph_clock(ID_FLEXCOM7);
-	gpio_set_pin_function(UART_RX_PIN, MUX_PA27B_FLEXCOM7_RXD);
-	gpio_set_pin_function(UART_TX_PIN, MUX_PA28B_FLEXCOM7_TXD);
-
-	_usart_sync_init(&edbg_com, FLEXCOM7);
-	_usart_sync_set_baud_rate(&edbg_com, CFG_BOARD_UART_BAUDRATE);
-	_usart_sync_set_mode(&edbg_com, USART_MODE_ASYNCHRONOUS);
-	_usart_sync_enable(&edbg_com);
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-  // 1ms tick timer (samd SystemCoreClock may not correct)
-  SysTick_Config(CONF_CPU_FREQUENCY / 1000);
-#endif
-
-  // USB Pin, Clock init
-
-  /* Clear SYSIO 10 & 11 for USB DM & DP */
-  hri_matrix_clear_CCFG_SYSIO_reg(MATRIX, CCFG_SYSIO_SYSIO10 | CCFG_SYSIO_SYSIO11);
-
-  // Enable clock
-  _pmc_enable_periph_clock(ID_UDP);
-
-	/* USB Device mode & Transceiver active */
-	hri_matrix_write_CCFG_USBMR_reg(MATRIX, CCFG_USBMR_USBMODE);
-}
-
-//--------------------------------------------------------------------+
-// USB Interrupt Handler
-//--------------------------------------------------------------------+
-void UDP_Handler(void)
-{
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-    tud_int_handler(0);
-  #endif
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  gpio_set_pin_level(LED_PIN, state);
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == gpio_get_pin_level(BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  uint8_t const * buf8 = (uint8_t const *) buf;
-  for(int i=0; i<len; i++)
-  {
-    while ( !_usart_sync_is_ready_to_send(&edbg_com) ) {}
-    _usart_sync_write_byte(&edbg_com, buf8[i]);
-  }
-  return len;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
-}
diff --git a/tinyusb/hw/bsp/saml2x/boards/atsaml21_xpro/board.h b/tinyusb/hw/bsp/saml2x/boards/atsaml21_xpro/board.h
deleted file mode 100755
index a3e03997..00000000
--- a/tinyusb/hw/bsp/saml2x/boards/atsaml21_xpro/board.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PIN               (32 + 30) // PB30
-#define LED_STATE_ON          0
-
-// Button
-#define BUTTON_PIN            (0  + 15) // PA15
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_RX_PIN           4
-#define UART_TX_PIN           5
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/saml2x/boards/atsaml21_xpro/board.mk b/tinyusb/hw/bsp/saml2x/boards/atsaml21_xpro/board.mk
deleted file mode 100755
index 81b4ecdc..00000000
--- a/tinyusb/hw/bsp/saml2x/boards/atsaml21_xpro/board.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-CFLAGS += -D__SAML21J18B__
-
-SAML_VARIANT = saml21
-
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/saml21j18b_flash.ld
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAML21J18
-
-# flash using jlink
-flash: flash-jlink
diff --git a/tinyusb/hw/bsp/saml2x/boards/atsaml21_xpro/saml21j18b_flash.ld b/tinyusb/hw/bsp/saml2x/boards/atsaml21_xpro/saml21j18b_flash.ld
deleted file mode 100755
index 7f6b7fa9..00000000
--- a/tinyusb/hw/bsp/saml2x/boards/atsaml21_xpro/saml21j18b_flash.ld
+++ /dev/null
@@ -1,153 +0,0 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAML21J18B
- *
- * Copyright (c) 2016 Atmel Corporation,
- *                    a wholly owned subsidiary of Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-SEARCH_DIR(.)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00040000
-  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
-  lpram    (rwx) : ORIGIN = 0x30000000, LENGTH = 0x00002000
-}
-
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
-
-/* Section Definitions */
-SECTIONS
-{
-    .text :
-    {
-        . = ALIGN(4);
-        _sfixed = .;
-        KEEP(*(.vectors .vectors.*))
-        *(.text .text.* .gnu.linkonce.t.*)
-        *(.glue_7t) *(.glue_7)
-        *(.rodata .rodata* .gnu.linkonce.r.*)
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-
-        /* Support C constructors, and C destructors in both user code
-           and the C library. This also provides support for C++ code. */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-
-        . = ALIGN(4);
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-
-        . = ALIGN(4);
-        KEEP(*(.fini))
-
-        . = ALIGN(4);
-        __fini_array_start = .;
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        __fini_array_end = .;
-
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-
-        . = ALIGN(4);
-        _efixed = .;            /* End of text section */
-    } > rom
-
-    /* .ARM.exidx is sorted, so has to go in its own output section.  */
-    PROVIDE_HIDDEN (__exidx_start = .);
-    .ARM.exidx :
-    {
-      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > rom
-    PROVIDE_HIDDEN (__exidx_end = .);
-
-    . = ALIGN(4);
-    _etext = .;
-
-    .relocate : AT (_etext)
-    {
-        . = ALIGN(4);
-        _srelocate = .;
-        *(.ramfunc .ramfunc.*);
-        *(.data .data.*);
-        . = ALIGN(4);
-        _erelocate = .;
-    } > ram
-
-    .lpram (NOLOAD):
-    {
-        . = ALIGN(8);
-        _slpram = .;
-        *(.lpram .lpram.*);
-        . = ALIGN(8);
-        _elpram = .;
-    } > lpram
-
-    /* .bss section which is used for uninitialized data */
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        _sbss = . ;
-        _szero = .;
-        *(.bss .bss.*)
-        *(COMMON)
-        . = ALIGN(4);
-        _ebss = . ;
-        _ezero = .;
-        end = .;
-    } > ram
-
-    /* stack section */
-    .stack (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sstack = .;
-        . = . + STACK_SIZE;
-        . = ALIGN(8);
-        _estack = .;
-    } > ram
-
-    . = ALIGN(4);
-    _end = . ;
-}
diff --git a/tinyusb/hw/bsp/saml2x/boards/saml22_feather/board.h b/tinyusb/hw/bsp/saml2x/boards/saml22_feather/board.h
deleted file mode 100755
index 13a32600..00000000
--- a/tinyusb/hw/bsp/saml2x/boards/saml22_feather/board.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PIN               PIN_PA08
-#define LED_STATE_ON          1
-
-// Button
-#define BUTTON_PIN            PIN_PA06
-#define BUTTON_STATE_ACTIVE   0
-
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/saml2x/boards/saml22_feather/board.mk b/tinyusb/hw/bsp/saml2x/boards/saml22_feather/board.mk
deleted file mode 100755
index 0605dca1..00000000
--- a/tinyusb/hw/bsp/saml2x/boards/saml22_feather/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-CFLAGS += -D__SAML22J18A__
-
-SAML_VARIANT = saml22
-
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/$(BOARD).ld
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAML22J18
-
-flash: flash-bossac
diff --git a/tinyusb/hw/bsp/saml2x/boards/saml22_feather/saml22_feather.ld b/tinyusb/hw/bsp/saml2x/boards/saml22_feather/saml22_feather.ld
deleted file mode 100755
index d1aaa44f..00000000
--- a/tinyusb/hw/bsp/saml2x/boards/saml22_feather/saml22_feather.ld
+++ /dev/null
@@ -1,146 +0,0 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAML22J18A
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-SEARCH_DIR(.)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00040000
-  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
-}
-
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
-
-ENTRY(Reset_Handler)
-
-/* Section Definitions */
-SECTIONS
-{
-    .text :
-    {
-        . = ALIGN(4);
-        _sfixed = .;
-        KEEP(*(.vectors .vectors.*))
-        *(.text .text.* .gnu.linkonce.t.*)
-        *(.glue_7t) *(.glue_7)
-        *(.rodata .rodata* .gnu.linkonce.r.*)
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-
-        /* Support C constructors, and C destructors in both user code
-           and the C library. This also provides support for C++ code. */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-
-        . = ALIGN(4);
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-
-        . = ALIGN(4);
-        KEEP(*(.fini))
-
-        . = ALIGN(4);
-        __fini_array_start = .;
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        __fini_array_end = .;
-
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-
-        . = ALIGN(4);
-        _efixed = .;            /* End of text section */
-    } > rom
-
-    /* .ARM.exidx is sorted, so has to go in its own output section.  */
-    PROVIDE_HIDDEN (__exidx_start = .);
-    .ARM.exidx :
-    {
-      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > rom
-    PROVIDE_HIDDEN (__exidx_end = .);
-
-    . = ALIGN(4);
-    _etext = .;
-
-    .relocate : AT (_etext)
-    {
-        . = ALIGN(4);
-        _srelocate = .;
-        *(.ramfunc .ramfunc.*);
-        *(.data .data.*);
-        . = ALIGN(4);
-        _erelocate = .;
-    } > ram
-
-    /* .bss section which is used for uninitialized data */
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        _sbss = . ;
-        _szero = .;
-        *(.bss .bss.*)
-        *(COMMON)
-        . = ALIGN(4);
-        _ebss = . ;
-        _ezero = .;
-        end = .;
-    } > ram
-
-    /* stack section */
-    .stack (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sstack = .;
-        . = . + STACK_SIZE;
-        . = ALIGN(8);
-        _estack = .;
-    } > ram
-
-    . = ALIGN(4);
-    _end = . ;
-}
diff --git a/tinyusb/hw/bsp/saml2x/boards/sensorwatch_m0/board.h b/tinyusb/hw/bsp/saml2x/boards/sensorwatch_m0/board.h
deleted file mode 100755
index 7fc690ab..00000000
--- a/tinyusb/hw/bsp/saml2x/boards/sensorwatch_m0/board.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PIN               PIN_PA21
-#define LED_STATE_ON          1
-
-// Button
-#define BUTTON_PIN            PIN_PA22
-#define BUTTON_STATE_ACTIVE   1
-
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/saml2x/boards/sensorwatch_m0/board.mk b/tinyusb/hw/bsp/saml2x/boards/sensorwatch_m0/board.mk
deleted file mode 100755
index 0605dca1..00000000
--- a/tinyusb/hw/bsp/saml2x/boards/sensorwatch_m0/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-CFLAGS += -D__SAML22J18A__
-
-SAML_VARIANT = saml22
-
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/$(BOARD).ld
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAML22J18
-
-flash: flash-bossac
diff --git a/tinyusb/hw/bsp/saml2x/boards/sensorwatch_m0/sensorwatch_m0.ld b/tinyusb/hw/bsp/saml2x/boards/sensorwatch_m0/sensorwatch_m0.ld
deleted file mode 100755
index d1aaa44f..00000000
--- a/tinyusb/hw/bsp/saml2x/boards/sensorwatch_m0/sensorwatch_m0.ld
+++ /dev/null
@@ -1,146 +0,0 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAML22J18A
- *
- * Copyright (c) 2018 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-SEARCH_DIR(.)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00040000
-  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
-}
-
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
-
-ENTRY(Reset_Handler)
-
-/* Section Definitions */
-SECTIONS
-{
-    .text :
-    {
-        . = ALIGN(4);
-        _sfixed = .;
-        KEEP(*(.vectors .vectors.*))
-        *(.text .text.* .gnu.linkonce.t.*)
-        *(.glue_7t) *(.glue_7)
-        *(.rodata .rodata* .gnu.linkonce.r.*)
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-
-        /* Support C constructors, and C destructors in both user code
-           and the C library. This also provides support for C++ code. */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-
-        . = ALIGN(4);
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-
-        . = ALIGN(4);
-        KEEP(*(.fini))
-
-        . = ALIGN(4);
-        __fini_array_start = .;
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        __fini_array_end = .;
-
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-
-        . = ALIGN(4);
-        _efixed = .;            /* End of text section */
-    } > rom
-
-    /* .ARM.exidx is sorted, so has to go in its own output section.  */
-    PROVIDE_HIDDEN (__exidx_start = .);
-    .ARM.exidx :
-    {
-      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > rom
-    PROVIDE_HIDDEN (__exidx_end = .);
-
-    . = ALIGN(4);
-    _etext = .;
-
-    .relocate : AT (_etext)
-    {
-        . = ALIGN(4);
-        _srelocate = .;
-        *(.ramfunc .ramfunc.*);
-        *(.data .data.*);
-        . = ALIGN(4);
-        _erelocate = .;
-    } > ram
-
-    /* .bss section which is used for uninitialized data */
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        _sbss = . ;
-        _szero = .;
-        *(.bss .bss.*)
-        *(COMMON)
-        . = ALIGN(4);
-        _ebss = . ;
-        _ezero = .;
-        end = .;
-    } > ram
-
-    /* stack section */
-    .stack (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sstack = .;
-        . = . + STACK_SIZE;
-        . = ALIGN(8);
-        _estack = .;
-    } > ram
-
-    . = ALIGN(4);
-    _end = . ;
-}
diff --git a/tinyusb/hw/bsp/saml2x/family.c b/tinyusb/hw/bsp/saml2x/family.c
deleted file mode 100755
index 470fde75..00000000
--- a/tinyusb/hw/bsp/saml2x/family.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "sam.h"
-#include "bsp/board.h"
-#include "board.h"
-
-#include "hal/include/hal_gpio.h"
-#include "hal/include/hal_init.h"
-#include "hpl/gclk/hpl_gclk_base.h"
-#include "hpl_mclk_config.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_Handler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-
-/* Referenced GCLKs (out of 0~4), should be initialized firstly */
-#define _GCLK_INIT_1ST 0x00000000
-/* Not referenced GCLKs, initialized last */
-#define _GCLK_INIT_LAST 0x0000001F
-
-void board_init(void)
-{
-  // Clock init ( follow hpl_init.c )
-  hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE);
-
-  _set_performance_level(2);
-
-  _osc32kctrl_init_sources();
-  _oscctrl_init_sources();
-  _mclk_init();
-#if _GCLK_INIT_1ST
-  _gclk_init_generators_by_fref(_GCLK_INIT_1ST);
-#endif
-  _oscctrl_init_referenced_generators();
-  _gclk_init_generators_by_fref(_GCLK_INIT_LAST);
-
-#if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3)
-  hri_port_set_EVCTRL_reg(PORT, 0, CONF_PORTA_EVCTRL);
-  hri_port_set_EVCTRL_reg(PORT, 1, CONF_PORTB_EVCTRL);
-#endif
-
-  // Update SystemCoreClock since it is hard coded with asf4 and not correct
-  // Init 1ms tick timer (samd SystemCoreClock may not correct)
-  SystemCoreClock = CONF_CPU_FREQUENCY;
-  SysTick_Config(CONF_CPU_FREQUENCY / 1000);
-
-  // Led init
-  gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
-  gpio_set_pin_level(LED_PIN, !LED_STATE_ON);
-
-  // Button init
-  gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
-  gpio_set_pin_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULL_DOWN : GPIO_PULL_UP);
-
-#if CFG_TUSB_OS  == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-#endif
-
-  /* USB Clock init
-   * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock
-   * for low speed and full speed operation. */
-  hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN);
-  hri_mclk_set_AHBMASK_USB_bit(MCLK);
-  hri_mclk_set_APBBMASK_USB_bit(MCLK);
-
-  // USB Pin Init
-  gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT);
-  gpio_set_pin_level(PIN_PA24, false);
-  gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF);
-  gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT);
-  gpio_set_pin_level(PIN_PA25, false);
-  gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF);
-
-  gpio_set_pin_function(PIN_PA24, PINMUX_PA24G_USB_DM);
-  gpio_set_pin_function(PIN_PA25, PINMUX_PA25G_USB_DP);
-
-  // Output 500hz PWM on PB23 (TCC0 WO[3]) so we can validate the GCLK1 clock speed
-//  hri_mclk_set_APBCMASK_TCC0_bit(MCLK);
-//  TCC0->PER.bit.PER = 48000000 / 1000;
-//  TCC0->CC[3].bit.CC = 48000000 / 2000;
-//  TCC0->CTRLA.bit.ENABLE = true;
-//
-//  gpio_set_pin_function(PIN_PB23, PINMUX_PB23F_TCC0_WO3);
-//  hri_gclk_write_PCHCTRL_reg(GCLK, TCC0_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN);
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  gpio_set_pin_level(LED_PIN, state);
-}
-
-uint32_t board_button_read(void)
-{
-  // button is active low
-  return gpio_get_pin_level(BUTTON_PIN) ? 0 : 1;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-void _init(void)
-{
-
-}
diff --git a/tinyusb/hw/bsp/saml2x/family.mk b/tinyusb/hw/bsp/saml2x/family.mk
deleted file mode 100755
index e0f6b2f7..00000000
--- a/tinyusb/hw/bsp/saml2x/family.mk
+++ /dev/null
@@ -1,48 +0,0 @@
-UF2_FAMILY_ID = 0x68ed2b88
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/microchip
-
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-MCU_DIR = hw/mcu/microchip/$(SAML_VARIANT)
-
-CFLAGS += \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
-  -nostdlib -nostartfiles \
-  -DCONF_OSC32K_CALIB_ENABLE=0 \
-  -DCFG_TUSB_MCU=OPT_MCU_SAML22
-
-SRC_C += \
-	src/portable/microchip/samd/dcd_samd.c \
-	$(MCU_DIR)/gcc/gcc/startup_$(SAML_VARIANT).c \
-	$(MCU_DIR)/gcc/system_$(SAML_VARIANT).c \
-	$(MCU_DIR)/hpl/gclk/hpl_gclk.c \
-	$(MCU_DIR)/hpl/mclk/hpl_mclk.c \
-	$(MCU_DIR)/hpl/pm/hpl_pm.c \
-	$(MCU_DIR)/hpl/osc32kctrl/hpl_osc32kctrl.c \
-	$(MCU_DIR)/hpl/oscctrl/hpl_oscctrl.c \
-	$(MCU_DIR)/hal/src/hal_atomic.c
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(MCU_DIR)/ \
-	$(TOP)/$(MCU_DIR)/config \
-	$(TOP)/$(MCU_DIR)/include \
-	$(TOP)/$(MCU_DIR)/hal/include \
-	$(TOP)/$(MCU_DIR)/hal/utils/include \
-	$(TOP)/$(MCU_DIR)/hpl/port \
-	$(TOP)/$(MCU_DIR)/hri \
-	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
-
-# flash using bossac at least version 1.8
-# can be found in arduino15/packages/arduino/tools/bossac/
-# Add it to your PATH or change BOSSAC variable to match your installation
-BOSSAC = bossac
-
-flash-bossac: $(BUILD)/$(PROJECT).bin
-	@:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyACM0)
-	$(BOSSAC) --port=$(SERIAL) -U -i --offset=0x2000 -e -w $^ -R
diff --git a/tinyusb/hw/bsp/sltb009a/board.mk b/tinyusb/hw/bsp/sltb009a/board.mk
deleted file mode 100755
index e8a24d1b..00000000
--- a/tinyusb/hw/bsp/sltb009a/board.mk
+++ /dev/null
@@ -1,47 +0,0 @@
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib -nostartfiles \
-  -D__STARTUP_CLEAR_BSS \
-  -D__START=main \
-  -DEFM32GG12B810F1024GM64 \
-  -DCFG_TUSB_MCU=OPT_MCU_EFM32GG12 
-
-# mcu driver cause following warnings
-#CFLAGS += -Wno-error=unused-parameter
-
-SILABS_FAMILY = efm32gg12b
-SILABS_CMSIS = hw/mcu/silabs/cmsis-dfp-$(SILABS_FAMILY)/Device/SiliconLabs/$(shell echo $(SILABS_FAMILY) | tr a-z A-Z)
-
-DEPS_SUBMODULES += hw/mcu/silabs/cmsis-dfp-$(SILABS_FAMILY)
-DEPS_SUBMODULES += lib/CMSIS_5
-
-# All source paths should be relative to the top level.
-LD_FILE = $(SILABS_CMSIS)/Source/GCC/$(SILABS_FAMILY).ld
-
-SRC_C += \
-  $(SILABS_CMSIS)/Source/system_$(SILABS_FAMILY).c \
-  src/portable/silabs/efm32/dcd_efm32.c
-
-SRC_S += \
-  $(SILABS_CMSIS)/Source/GCC/startup_$(SILABS_FAMILY).S
-
-INC += \
-  $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-  $(TOP)/$(SILABS_CMSIS)/Include \
-  $(TOP)/hw/bsp/$(BOARD)
-
-# For TinyUSB port source
-VENDOR = silabs
-CHIP_FAMILY = efm32
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4
-
-# For flash-jlink target
-JLINK_DEVICE = EFM32GG12B810F1024
-
-flash: flash-jlink
diff --git a/tinyusb/hw/bsp/sltb009a/sltb009a.c b/tinyusb/hw/bsp/sltb009a/sltb009a.c
deleted file mode 100755
index b929adb1..00000000
--- a/tinyusb/hw/bsp/sltb009a/sltb009a.c
+++ /dev/null
@@ -1,721 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2021 Rafael Silva (@perigoso)
- * Copyright (c) 2021 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "../board.h"
-
-#include "em_device.h"
-
-/*--------------------------------------------------------------------*/
-/* MACRO TYPEDEF CONSTANT ENUM                                        */
-/*--------------------------------------------------------------------*/
-
-#define LED_PORT              0     // A
-#define LED_PIN_R             12    // 12
-#define LED_PIN_B             13    // 13
-#define LED_PIN_G             14    // 14
-#define LED_STATE_ON          0     // active-low
-
-#define BUTTON_PORT           3     // D
-#define BUTTON_PIN            5     // 5
-#define BUTTON_STATE_ACTIVE   0     // active-low
-
-/*--------------------------------------------------------------------*/
-/* Forward USB interrupt events to TinyUSB IRQ Handler                */
-/*--------------------------------------------------------------------*/
-
-void USB_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-/*--------------------------------------------------------------------*/
-/* Fault Handlers                                                     */
-/*--------------------------------------------------------------------*/
-
-void HardFault_Handler(void)
-{
-  asm("bkpt");
-}
-
-void MemManage_Handler(void)
-{
-  asm("bkpt");
-}
-
-void BusFault_Handler(void)
-{
-  asm("bkpt");
-}
-
-void UsageFault_Handler(void)
-{
-  asm("bkpt");
-}
-
-/*--------------------------------------------------------------------*/
-/* Startup                                                            */
-/*--------------------------------------------------------------------*/
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
-}
-
-/*--------------------------------------------------------------------*/
-/* Initing Funcs                                                      */
-/*--------------------------------------------------------------------*/
-
-void emu_init(uint8_t immediate_switch)
-{
-  EMU->PWRCTRL = (immediate_switch ? EMU_PWRCTRL_IMMEDIATEPWRSWITCH : 0) | EMU_PWRCTRL_REGPWRSEL_DVDD | EMU_PWRCTRL_ANASW_AVDD;
-}
-
-void emu_reg_init(float target_voltage)
-{
-    if(target_voltage < 2300.f || target_voltage >= 3800.f)
-        return;
-
-    uint8_t level = ((target_voltage - 2300.f) / 100.f);
-
-    EMU->R5VCTRL = EMU_R5VCTRL_INPUTMODE_AUTO;
-
-    EMU->R5VOUTLEVEL = level; /* Reg output to 3.3V*/
-}
-
-void emu_dcdc_init(float target_voltage, float max_ln_current, float max_lp_current, float max_reverse_current)
-{
-    if(target_voltage < 1800.f || target_voltage >= 3000.f)
-        return;
-
-    if(max_ln_current <= 0.f || max_ln_current > 200.f)
-        return;
-
-    if(max_lp_current <= 0.f || max_lp_current > 10000.f)
-        return;
-
-    if(max_reverse_current < 0.f || max_reverse_current > 160.f)
-        return;
-
-    // Low Power & Low Noise current limit
-    uint8_t lp_bias = 0;
-
-    if(max_lp_current < 75.f)
-        lp_bias = 0;
-    else if(max_lp_current < 500.f)
-        lp_bias = 1;
-    else if(max_lp_current < 2500.f)
-        lp_bias = 2;
-    else
-        lp_bias = 3;
-
-    EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK) | ((uint32_t)lp_bias << _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT);
-    EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LNFORCECCM; // Force CCM to prevent reverse current
-    EMU->DCDCLPCTRL |= EMU_DCDCLPCTRL_LPVREFDUTYEN; // Enable duty cycling of the bias for LP mode
-    EMU->DCDCLNFREQCTRL = (EMU->DCDCLNFREQCTRL & ~_EMU_DCDCLNFREQCTRL_RCOBAND_MASK) | 4; // Set RCO Band to 7MHz
-
-    uint8_t fet_count = 0;
-
-    if(max_ln_current < 20.f)
-        fet_count = 4;
-    else if(max_ln_current >= 20.f && max_ln_current < 40.f)
-        fet_count = 8;
-    else
-        fet_count = 16;
-
-    EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~_EMU_DCDCMISCCTRL_NFETCNT_MASK) | ((uint32_t)(fet_count - 1) << _EMU_DCDCMISCCTRL_NFETCNT_SHIFT);
-    EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~_EMU_DCDCMISCCTRL_PFETCNT_MASK) | ((uint32_t)(fet_count - 1) << _EMU_DCDCMISCCTRL_PFETCNT_SHIFT);
-
-    uint8_t ln_current_limit = (((max_ln_current + 40.f) * 1.5f) / (5.f * fet_count)) - 1;
-    uint8_t lp_current_limit = 1; // Recommended value
-
-    EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK | _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK)) | ((uint32_t)ln_current_limit << _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT) | ((uint32_t)lp_current_limit << _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT);
-
-    uint8_t z_det_limit = ((max_reverse_current + 40.f) * 1.5f) / (2.5f * fet_count);
-
-    EMU->DCDCZDETCTRL = (EMU->DCDCZDETCTRL & ~_EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK) | ((uint32_t)z_det_limit << _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT);
-
-    EMU->DCDCCLIMCTRL |= EMU_DCDCCLIMCTRL_BYPLIMEN; // Enable bypass current limiter to prevent overcurrent when switching modes
-
-    // Output Voltage
-    if(target_voltage > 1800.f)
-    {
-        float max_vout = 3000.f;
-        float min_vout = 1800.f;
-        float diff_vout = max_vout - min_vout;
-
-        uint8_t ln_vref_high = (DEVINFO->DCDCLNVCTRL0 & _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK) >> _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT;
-        uint8_t ln_vref_low = (DEVINFO->DCDCLNVCTRL0 & _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK) >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT;
-
-        uint8_t ln_vref = ((target_voltage - min_vout) * (float)(ln_vref_high - ln_vref_low)) / diff_vout;
-        ln_vref += ln_vref_low;
-
-        EMU->DCDCLNVCTRL = (ln_vref << _EMU_DCDCLNVCTRL_LNVREF_SHIFT) | EMU_DCDCLNVCTRL_LNATT;
-
-        uint8_t lp_vref_low = 0;
-        uint8_t lp_vref_high = 0;
-
-        switch(lp_bias)
-        {
-            case 0:
-            {
-                lp_vref_high = (DEVINFO->DCDCLPVCTRL2 & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK) >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT;
-                lp_vref_low = (DEVINFO->DCDCLPVCTRL2 & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK) >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT;
-            }
-            break;
-            case 1:
-            {
-                lp_vref_high = (DEVINFO->DCDCLPVCTRL2 & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK) >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT;
-                lp_vref_low = (DEVINFO->DCDCLPVCTRL2 & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK) >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT;
-            }
-            break;
-            case 2:
-            {
-                lp_vref_high = (DEVINFO->DCDCLPVCTRL3 & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK) >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT;
-                lp_vref_low = (DEVINFO->DCDCLPVCTRL3 & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK) >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT;
-            }
-            break;
-            case 3:
-            {
-                lp_vref_high = (DEVINFO->DCDCLPVCTRL3 & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK) >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT;
-                lp_vref_low = (DEVINFO->DCDCLPVCTRL3 & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK) >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT;
-            }
-            break;
-        }
-
-        uint8_t lp_vref = ((target_voltage - min_vout) * (float)(lp_vref_high - lp_vref_low)) / diff_vout;
-        lp_vref += lp_vref_low;
-
-        EMU->DCDCLPVCTRL = (lp_vref << _EMU_DCDCLPVCTRL_LPVREF_SHIFT) | EMU_DCDCLPVCTRL_LPATT;
-    }
-    else
-    {
-        float max_vout = 1800.f;
-        float min_vout = 1200.f;
-        float diff_vout = max_vout - min_vout;
-
-        uint8_t ln_vref_high = (DEVINFO->DCDCLNVCTRL0 & _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK) >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT;
-        uint8_t ln_vref_low = (DEVINFO->DCDCLNVCTRL0 & _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK) >> _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT;
-
-        uint8_t ln_vref = ((target_voltage - min_vout) * (float)(ln_vref_high - ln_vref_low)) / diff_vout;
-        ln_vref += ln_vref_low;
-
-        EMU->DCDCLNVCTRL = ln_vref << _EMU_DCDCLNVCTRL_LNVREF_SHIFT;
-
-        uint8_t lp_vref_low = 0;
-        uint8_t lp_vref_high = 0;
-
-        switch(lp_bias)
-        {
-            case 0:
-            {
-                lp_vref_high = (DEVINFO->DCDCLPVCTRL0 & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK) >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT;
-                lp_vref_low = (DEVINFO->DCDCLPVCTRL0 & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK) >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT;
-            }
-            break;
-            case 1:
-            {
-                lp_vref_high = (DEVINFO->DCDCLPVCTRL0 & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK) >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT;
-                lp_vref_low = (DEVINFO->DCDCLPVCTRL0 & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK) >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT;
-            }
-            break;
-            case 2:
-            {
-                lp_vref_high = (DEVINFO->DCDCLPVCTRL1 & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK) >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT;
-                lp_vref_low = (DEVINFO->DCDCLPVCTRL1 & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK) >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT;
-            }
-            break;
-            case 3:
-            {
-                lp_vref_high = (DEVINFO->DCDCLPVCTRL1 & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK) >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT;
-                lp_vref_low = (DEVINFO->DCDCLPVCTRL1 & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK) >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT;
-            }
-            break;
-        }
-
-        uint8_t lp_vref = ((target_voltage - min_vout) * (float)(lp_vref_high - lp_vref_low)) / diff_vout;
-        lp_vref += lp_vref_low;
-
-        EMU->DCDCLPVCTRL = lp_vref << _EMU_DCDCLPVCTRL_LPVREF_SHIFT;
-    }
-
-    EMU->DCDCLPCTRL = (EMU->DCDCLPCTRL & ~_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) | (((DEVINFO->DCDCLPCMPHYSSEL1 & (((uint32_t)0xFF) << (lp_bias * 8))) >> (lp_bias * 8)) << _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT);
-
-    while(EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY); // Wait for configuration to write
-
-    // Calibration
-    //EMU->DCDCLNCOMPCTRL = 0x57204077; // Compensation for 1uF DCDC capacitor
-    EMU->DCDCLNCOMPCTRL = 0xB7102137; // Compensation for 4.7uF DCDC capacitor
-
-    // Enable DCDC converter
-    EMU->DCDCCTRL = EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER | EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER | EMU_DCDCCTRL_DCDCMODE_LOWNOISE;
-
-    // Switch digital domain to DVDD
-    EMU->PWRCTRL = EMU_PWRCTRL_REGPWRSEL_DVDD | EMU_PWRCTRL_ANASW_AVDD;
-}
-
-void cmu_hfxo_startup_calib(uint16_t ib_trim, uint16_t c_tune)
-{
-  if(CMU->STATUS & CMU_STATUS_HFXOENS)
-      return;
-
-  CMU->HFXOSTARTUPCTRL = (CMU->HFXOSTARTUPCTRL & ~(_CMU_HFXOSTARTUPCTRL_CTUNE_MASK | _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK)) | (((uint32_t)c_tune << _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT) & _CMU_HFXOSTARTUPCTRL_CTUNE_MASK) | (((uint32_t)ib_trim << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT) & _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK);
-}
-
-void cmu_hfxo_steady_calib(uint16_t ib_trim, uint16_t c_tune)
-{
-  if(CMU->STATUS & CMU_STATUS_HFXOENS)
-      return;
-
-  CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL & ~(_CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK)) | (((uint32_t)c_tune << _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT) & _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK) | (((uint32_t)ib_trim << _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT) & _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK);
-}
-
-void cmu_hfrco_calib(uint32_t calibration)
-{
-    if(CMU->STATUS & CMU_STATUS_DPLLENS)
-        return;
-
-    while(CMU->SYNCBUSY & CMU_SYNCBUSY_HFRCOBSY);
-
-    CMU->HFRCOCTRL = calibration;
-
-    while(CMU->SYNCBUSY & CMU_SYNCBUSY_HFRCOBSY);
-}
-
-void cmu_ushfrco_calib(uint8_t enable, uint32_t calibration)
-{
-    if(CMU->USBCRCTRL & CMU_USBCRCTRL_USBCREN)
-        return;
-
-    if(!enable)
-    {
-        CMU->OSCENCMD = CMU_OSCENCMD_USHFRCODIS;
-        while(CMU->STATUS & CMU_STATUS_USHFRCOENS);
-
-        return;
-    }
-
-    while(CMU->SYNCBUSY & CMU_SYNCBUSY_USHFRCOBSY);
-
-    CMU->USHFRCOCTRL = calibration | CMU_USHFRCOCTRL_FINETUNINGEN;
-
-    while(CMU->SYNCBUSY & CMU_SYNCBUSY_USHFRCOBSY);
-
-    if(enable && !(CMU->STATUS & CMU_STATUS_USHFRCOENS))
-    {
-        CMU->OSCENCMD = CMU_OSCENCMD_USHFRCOEN;
-
-        while(!(CMU->STATUS & CMU_STATUS_USHFRCORDY));
-    }
-}
-
-void cmu_auxhfrco_calib(uint8_t enable, uint32_t calibration)
-{
-    if(!enable)
-    {
-        CMU->OSCENCMD = CMU_OSCENCMD_AUXHFRCODIS;
-        while(CMU->STATUS & CMU_STATUS_AUXHFRCOENS);
-
-        return;
-    }
-
-    while(CMU->SYNCBUSY & CMU_SYNCBUSY_AUXHFRCOBSY);
-
-    CMU->AUXHFRCOCTRL = calibration;
-
-    while(CMU->SYNCBUSY & CMU_SYNCBUSY_AUXHFRCOBSY);
-
-    if(enable && !(CMU->STATUS & CMU_STATUS_AUXHFRCOENS))
-    {
-        CMU->OSCENCMD = CMU_OSCENCMD_AUXHFRCOEN;
-
-        while(!(CMU->STATUS & CMU_STATUS_AUXHFRCORDY));
-    }
-}
-
-
-void cmu_init(void)
-{
-    // Change SDIO clock to HFXO if HFRCO selected and disable it
-    CMU->SDIOCTRL = CMU_SDIOCTRL_SDIOCLKDIS | CMU_SDIOCTRL_SDIOCLKSEL_HFXO;
-    while(CMU->STATUS & CMU_STATUS_SDIOCLKENS);
-
-    // Change QSPI clock to HFXO if HFRCO selected and disable it
-    CMU->QSPICTRL = CMU_QSPICTRL_QSPI0CLKDIS | CMU_QSPICTRL_QSPI0CLKSEL_HFXO;
-    while(CMU->STATUS & CMU_STATUS_QSPI0CLKENS);
-
-    // Disable DPLL if enabled
-    if(CMU->STATUS & CMU_STATUS_DPLLENS)
-    {
-        CMU->OSCENCMD = CMU_OSCENCMD_DPLLDIS;
-        while(CMU->STATUS & CMU_STATUS_DPLLENS);
-    }
-
-    // Disable HFXO if enabled
-    if(CMU->STATUS & CMU_STATUS_HFXOENS)
-    {
-        CMU->OSCENCMD = CMU_OSCENCMD_HFXODIS;
-        while(CMU->STATUS & CMU_STATUS_HFXOENS);
-    }
-
-    // Setup HFXO
-    CMU->HFXOCTRL = CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD | CMU_HFXOCTRL_MODE_XTAL;
-    CMU->HFXOCTRL1 = CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT;
-    CMU->HFXOSTEADYSTATECTRL |= CMU_HFXOSTEADYSTATECTRL_PEAKMONEN;
-    CMU->HFXOTIMEOUTCTRL = (7 << _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT) | (8 << _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT) | (12 << _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT);
-
-    // Enable HFXO and wait for it to be ready
-    CMU->OSCENCMD = CMU_OSCENCMD_HFXOEN;
-    while(!(CMU->STATUS & CMU_STATUS_HFXORDY));
-
-    // Switch main clock to HFXO and wait for it to be selected
-    CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFXO;
-    while((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) != CMU_HFCLKSTATUS_SELECTED_HFXO);
-
-    // Calibrate HFRCO for 72MHz and enable tunning by PLL
-    cmu_hfrco_calib((DEVINFO->HFRCOCAL16) | CMU_HFRCOCTRL_FINETUNINGEN);
-
-    // Setup the PLL
-    CMU->DPLLCTRL = CMU_DPLLCTRL_REFSEL_HFXO | CMU_DPLLCTRL_AUTORECOVER | CMU_DPLLCTRL_EDGESEL_RISE | CMU_DPLLCTRL_MODE_FREQLL;
-    // 72MHz = 50MHz (HFXO) * 1.44 (144/100)
-    CMU->DPLLCTRL1 = (143 << _CMU_DPLLCTRL1_N_SHIFT) | (99 << _CMU_DPLLCTRL1_M_SHIFT); // fHFRCO = fHFXO * (N + 1) / (M + 1)
-
-    // Enable the DPLL and wait for it to be ready
-    CMU->OSCENCMD = CMU_OSCENCMD_DPLLEN;
-    while(!(CMU->STATUS & CMU_STATUS_DPLLRDY));
-
-    // Config peripherals for the new frequency (freq > 32MHz)
-    CMU->CTRL |= CMU_CTRL_WSHFLE;
-
-    // Set prescalers
-    CMU->HFPRESC = CMU_HFPRESC_HFCLKLEPRESC_DIV2 | CMU_HFPRESC_PRESC_NODIVISION;
-    CMU->HFBUSPRESC = 1 << _CMU_HFBUSPRESC_PRESC_SHIFT;
-    CMU->HFCOREPRESC = 0 << _CMU_HFCOREPRESC_PRESC_SHIFT;
-    CMU->HFPERPRESC = 1 << _CMU_HFPERPRESC_PRESC_SHIFT;
-    CMU->HFEXPPRESC = 0 << _CMU_HFEXPPRESC_PRESC_SHIFT;
-    CMU->HFPERPRESCB = 0 << _CMU_HFPERPRESCB_PRESC_SHIFT;
-    CMU->HFPERPRESCC = 1 << _CMU_HFPERPRESCC_PRESC_SHIFT;
-
-    // Enable clock to peripherals
-    CMU->CTRL |= CMU_CTRL_HFPERCLKEN;
-
-    // Switch main clock to HFRCO and wait for it to be selected
-    CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCO;
-    while((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) != CMU_HFCLKSTATUS_SELECTED_HFRCO);
-
-    // LFA Clock
-    CMU->LFACLKSEL = CMU_LFACLKSEL_LFA_LFRCO;
-
-    // LFB Clock
-    CMU->LFBCLKSEL = CMU_LFBCLKSEL_LFB_LFRCO;
-
-    // LFC Clock
-    CMU->LFCCLKSEL = CMU_LFCCLKSEL_LFC_LFRCO;
-
-    // LFE Clock
-    CMU->LFECLKSEL = CMU_LFECLKSEL_LFE_ULFRCO;
-}
-
-void systick_init(void)
-{
-    SysTick->LOAD = (72000000 / 1000) - 1;
-    SysTick->VAL = 0;
-    SysTick->CTRL = SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk;
-
-    SCB->SHP[11] = 7 << (8 - __NVIC_PRIO_BITS); // Set priority 3,1 (min)
-}
-
-void gpio_init(void)
-{
-    CMU->HFBUSCLKEN0 |= CMU_HFBUSCLKEN0_GPIO;
-
-    // NC - Not Connected (not available in mcu package)
-    // NR - Not routed (no routing to pin on pcb, floating)
-    // NU - Not used (not currently in use)
-
-    // Port A
-    GPIO->P[0].CTRL   = GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG | (6 << _GPIO_P_CTRL_SLEWRATEALT_SHIFT)
-                      | GPIO_P_CTRL_DRIVESTRENGTH_STRONG | (6 << _GPIO_P_CTRL_SLEWRATE_SHIFT);
-    GPIO->P[0].MODEL  = GPIO_P_MODEL_MODE0_DISABLED          // NU
-                      | GPIO_P_MODEL_MODE1_DISABLED          // NU
-                      | GPIO_P_MODEL_MODE2_DISABLED          // NU
-                      | GPIO_P_MODEL_MODE3_DISABLED          // NU
-                      | GPIO_P_MODEL_MODE4_DISABLED          // NU
-                      | GPIO_P_MODEL_MODE5_DISABLED          // NU
-                      | GPIO_P_MODEL_MODE6_DISABLED          // NU
-                      | GPIO_P_MODEL_MODE7_DISABLED;         // NC
-    GPIO->P[0].MODEH  = GPIO_P_MODEH_MODE8_DISABLED          // GPIO - MIC_ENABLE
-                      | GPIO_P_MODEH_MODE9_DISABLED          // NC
-                      | GPIO_P_MODEH_MODE10_DISABLED         // NC
-                      | GPIO_P_MODEH_MODE11_DISABLED         // NC
-                      | GPIO_P_MODEH_MODE12_WIREDAND         // LED0R
-                      | GPIO_P_MODEH_MODE13_WIREDAND         // LED0B
-                      | GPIO_P_MODEH_MODE14_WIREDAND         // LED0G
-                      | GPIO_P_MODEH_MODE15_DISABLED;        // NU
-    GPIO->P[0].DOUT   = 0x7000; // Leds off By default
-    GPIO->P[0].OVTDIS = 0;
-
-    // Port B
-    GPIO->P[1].CTRL   = GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG | (6 << _GPIO_P_CTRL_SLEWRATEALT_SHIFT)
-                      | GPIO_P_CTRL_DRIVESTRENGTH_STRONG | (6 << _GPIO_P_CTRL_SLEWRATE_SHIFT);
-    GPIO->P[1].MODEL  = GPIO_P_MODEL_MODE0_DISABLED                 // NC
-                      | GPIO_P_MODEL_MODE1_DISABLED                 // NC
-                      | GPIO_P_MODEL_MODE2_DISABLED                 // NC
-                      | GPIO_P_MODEL_MODE3_DISABLED                 // NU
-                      | GPIO_P_MODEL_MODE4_DISABLED                 // NU
-                      | GPIO_P_MODEL_MODE5_DISABLED                 // NU
-                      | GPIO_P_MODEL_MODE6_DISABLED                 // NU
-                      | GPIO_P_MODEL_MODE7_DISABLED;                // MAIN_LFXTAL_P
-    GPIO->P[1].MODEH  = GPIO_P_MODEH_MODE8_DISABLED                 // MAIN_LFXTAL_N
-                      | GPIO_P_MODEH_MODE9_DISABLED                 // NC
-                      | GPIO_P_MODEH_MODE10_DISABLED                // NC
-                      | GPIO_P_MODEH_MODE11_DISABLED                // PDM_DAT0 - MIC_DATA
-                      | GPIO_P_MODEH_MODE12_DISABLED                // PDM_CLK - MIC_CLOCK
-                      | GPIO_P_MODEH_MODE13_DISABLED                // MAIN_HFXTAL_P
-                      | GPIO_P_MODEH_MODE14_DISABLED                // MAIN_HFXTAL_N
-                      | GPIO_P_MODEH_MODE15_DISABLED;               // NC
-    GPIO->P[1].DOUT   = 0;
-    GPIO->P[1].OVTDIS = 0;
-
-    // Port C
-    GPIO->P[2].CTRL   = GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG | (6 << _GPIO_P_CTRL_SLEWRATEALT_SHIFT)
-                      | GPIO_P_CTRL_DRIVESTRENGTH_STRONG | (7 << _GPIO_P_CTRL_SLEWRATE_SHIFT);
-    GPIO->P[2].MODEL  = GPIO_P_MODEL_MODE0_DISABLED                 // NC
-                      | GPIO_P_MODEL_MODE1_DISABLED                 // NC
-                      | GPIO_P_MODEL_MODE2_DISABLED                 // NC
-                      | GPIO_P_MODEL_MODE3_DISABLED                 // NC
-                      | GPIO_P_MODEL_MODE4_DISABLED                 // NU
-                      | GPIO_P_MODEL_MODE5_DISABLED                 // NU
-                      | GPIO_P_MODEL_MODE6_DISABLED                 // NC
-                      | GPIO_P_MODEL_MODE7_DISABLED;                // NC
-    GPIO->P[2].MODEH  = GPIO_P_MODEH_MODE8_DISABLED                 // NC
-                      | GPIO_P_MODEH_MODE9_DISABLED                 // NC
-                      | GPIO_P_MODEH_MODE10_DISABLED                // NC
-                      | GPIO_P_MODEH_MODE11_DISABLED                // NC
-                      | GPIO_P_MODEH_MODE12_DISABLED                // NC
-                      | GPIO_P_MODEH_MODE13_DISABLED                // NC
-                      | GPIO_P_MODEH_MODE14_DISABLED                // NC
-                      | GPIO_P_MODEH_MODE15_DISABLED;               // NC
-    GPIO->P[2].DOUT   = 0;
-    GPIO->P[2].OVTDIS = 0;
-
-    // Port D
-    GPIO->P[3].CTRL   = GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG | (6 << _GPIO_P_CTRL_SLEWRATEALT_SHIFT)
-                      | GPIO_P_CTRL_DRIVESTRENGTH_STRONG | (6 << _GPIO_P_CTRL_SLEWRATE_SHIFT);
-    GPIO->P[3].MODEL  = GPIO_P_MODEL_MODE0_DISABLED                 // NU
-                      | GPIO_P_MODEL_MODE1_DISABLED                 // NU
-                      | GPIO_P_MODEL_MODE2_DISABLED                 // NU
-                      | GPIO_P_MODEL_MODE3_DISABLED                 // NU
-                      | GPIO_P_MODEL_MODE4_DISABLED                 // NU
-                      | GPIO_P_MODEL_MODE5_INPUT                    // GPIO - BTN0
-                      | GPIO_P_MODEL_MODE6_WIREDAND                 // LED1R
-                      | GPIO_P_MODEL_MODE7_DISABLED;                // NU
-    GPIO->P[3].MODEH  = GPIO_P_MODEH_MODE8_INPUT                    // GPIO - BTN1
-                      | GPIO_P_MODEH_MODE9_DISABLED                 // NC
-                      | GPIO_P_MODEH_MODE10_DISABLED                // NC
-                      | GPIO_P_MODEH_MODE11_DISABLED                // NC
-                      | GPIO_P_MODEH_MODE12_DISABLED                // NC
-                      | GPIO_P_MODEH_MODE13_DISABLED                // NC
-                      | GPIO_P_MODEH_MODE14_DISABLED                // NC
-                      | GPIO_P_MODEH_MODE15_DISABLED;               // NC
-    GPIO->P[3].DOUT   = 0;
-    GPIO->P[3].OVTDIS = 0;
-
-    // Port E
-    GPIO->P[4].CTRL   = GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG | (6 << _GPIO_P_CTRL_SLEWRATEALT_SHIFT)
-                      | GPIO_P_CTRL_DRIVESTRENGTH_STRONG | (6 << _GPIO_P_CTRL_SLEWRATE_SHIFT);
-    GPIO->P[4].MODEL  = GPIO_P_MODEL_MODE0_DISABLED                 // NC
-                      | GPIO_P_MODEL_MODE1_DISABLED                 // NC
-                      | GPIO_P_MODEL_MODE2_DISABLED                 // NC
-                      | GPIO_P_MODEL_MODE3_DISABLED                 // NC
-                      | GPIO_P_MODEL_MODE4_DISABLED                 // NU
-                      | GPIO_P_MODEL_MODE5_DISABLED                 // NU
-                      | GPIO_P_MODEL_MODE6_DISABLED                 // NU
-                      | GPIO_P_MODEL_MODE7_DISABLED;                // NU
-    GPIO->P[4].MODEH  = GPIO_P_MODEH_MODE8_DISABLED                 // NU
-                      | GPIO_P_MODEH_MODE9_DISABLED                 // NU
-                      | GPIO_P_MODEH_MODE10_DISABLED                // NU
-                      | GPIO_P_MODEH_MODE11_DISABLED                // NU
-                      | GPIO_P_MODEH_MODE12_WIREDAND                // LED1B
-                      | GPIO_P_MODEH_MODE13_DISABLED                // NU
-                      | GPIO_P_MODEH_MODE14_DISABLED                // NU
-                      | GPIO_P_MODEH_MODE15_DISABLED;               // NU
-    GPIO->P[4].DOUT   = 0;
-    GPIO->P[4].OVTDIS = 0;
-
-    // Port F
-    GPIO->P[5].CTRL   = GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG | (6 << _GPIO_P_CTRL_SLEWRATEALT_SHIFT)
-                      | GPIO_P_CTRL_DRIVESTRENGTH_STRONG | (6 << _GPIO_P_CTRL_SLEWRATE_SHIFT);
-    GPIO->P[5].MODEL  = GPIO_P_MODEL_MODE0_PUSHPULL                 // SWCLK
-                      | GPIO_P_MODEL_MODE1_PUSHPULL                 // SWDIO
-                      | GPIO_P_MODEL_MODE2_PUSHPULL                 // SWO
-                      | GPIO_P_MODEL_MODE3_DISABLED                 // NC
-                      | GPIO_P_MODEL_MODE4_DISABLED                 // NC
-                      | GPIO_P_MODEL_MODE5_DISABLED                 // NU
-                      | GPIO_P_MODEL_MODE6_DISABLED                 // NC
-                      | GPIO_P_MODEL_MODE7_DISABLED;                // NC
-    GPIO->P[5].MODEH  = GPIO_P_MODEH_MODE8_DISABLED                 // NC
-                      | GPIO_P_MODEH_MODE9_DISABLED                 // NC
-                      | GPIO_P_MODEH_MODE10_DISABLED                // USB N
-                      | GPIO_P_MODEH_MODE11_DISABLED                // USB P
-                      | GPIO_P_MODEH_MODE12_WIREDAND                // LED1G
-                      | GPIO_P_MODEH_MODE13_DISABLED                // NC
-                      | GPIO_P_MODEH_MODE14_DISABLED                // NC
-                      | GPIO_P_MODEH_MODE15_DISABLED;               // NC
-    GPIO->P[5].DOUT   = 0;
-
-    GPIO->P[5].OVTDIS = 0;
-
-    // Debugger Route
-    GPIO->ROUTEPEN &= ~(GPIO_ROUTEPEN_TDIPEN | GPIO_ROUTEPEN_TDOPEN);   // Disable JTAG
-    GPIO->ROUTEPEN |= GPIO_ROUTEPEN_SWVPEN;                             // Enable SWO
-    GPIO->ROUTELOC0 = GPIO_ROUTELOC0_SWVLOC_LOC0;                       // SWO on PF2
-
-    // External interrupts
-    GPIO->EXTIPSELL = GPIO_EXTIPSELL_EXTIPSEL0_PORTE            // NU
-                    | GPIO_EXTIPSELL_EXTIPSEL1_PORTB            // NU
-                    | GPIO_EXTIPSELL_EXTIPSEL2_PORTB            // NU
-                    | GPIO_EXTIPSELL_EXTIPSEL3_PORTB            // NU
-                    | GPIO_EXTIPSELL_EXTIPSEL4_PORTA            // NU
-                    | GPIO_EXTIPSELL_EXTIPSEL5_PORTA            // NU
-                    | GPIO_EXTIPSELL_EXTIPSEL6_PORTC            // NU
-                    | GPIO_EXTIPSELL_EXTIPSEL7_PORTC;           // NU
-    GPIO->EXTIPSELH = GPIO_EXTIPSELH_EXTIPSEL8_PORTA            // NU
-                    | GPIO_EXTIPSELH_EXTIPSEL9_PORTE            // NU
-                    | GPIO_EXTIPSELH_EXTIPSEL10_PORTF           // NU
-                    | GPIO_EXTIPSELH_EXTIPSEL11_PORTA           // NU
-                    | GPIO_EXTIPSELH_EXTIPSEL12_PORTA           // NU
-                    | GPIO_EXTIPSELH_EXTIPSEL13_PORTE           // NU
-                    | GPIO_EXTIPSELH_EXTIPSEL14_PORTF           // NU
-                    | GPIO_EXTIPSELH_EXTIPSEL15_PORTA;          // NU
-
-    GPIO->EXTIPINSELL = GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3       // NU
-                      | GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1       // NU
-                      | GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2       // NU
-                      | GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3       // NU
-                      | GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6       // NU
-                      | GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7       // NU
-                      | GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4       // NU
-                      | GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7;      // NU
-    GPIO->EXTIPINSELH = GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8       // NU
-                      | GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9       // NU
-                      | GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11     // NU
-                      | GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8      // NU
-                      | GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13     // NU
-                      | GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15     // NU
-                      | GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12     // NU
-                      | GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12;    // NU
-
-}
-
-/*--------------------------------------------------------------------*/
-/* Board Init                                                         */
-/*--------------------------------------------------------------------*/
-
-void board_init(void)
-{
-
-  emu_dcdc_init(1800.f, 50.f, 100.f, 0.f); // Init DC-DC converter (1.8 V, 50 mA active, 100 uA sleep, 0 mA reverse limit)
-  emu_init(0);
-  emu_reg_init(3300.f); // set output regulator to 3.3V
-
-  cmu_hfxo_startup_calib(0x200, 0x145); // Config HFXO Startup for 1280 uA, 36 pF (18 pF + 2 pF CLOAD)
-  cmu_hfxo_steady_calib(0x009, 0x145); // Config HFXO Steady for 12 uA, 36 pF (18 pF + 2 pF CLOAD)
-
-  cmu_init(); // Init Clock Management Unit
-
-  cmu_ushfrco_calib(1, DEVINFO->USHFRCOCAL13); // Enable and calibrate USHFRCO for 48 MHz
-  cmu_auxhfrco_calib(1, DEVINFO->AUXHFRCOCAL11); // Enable and calibrate AUXHFRCO for 32 MHz
-
-  CMU->USBCRCTRL = CMU_USBCRCTRL_USBCREN; // enable USB clock recovery
-  CMU->USBCTRL = CMU_USBCTRL_USBCLKSEL_USHFRCO | CMU_USBCTRL_USBCLKEN;  // select USHFRCO as USB Phy clock source and enable it
-
-  CMU->HFBUSCLKEN0 |= CMU_HFBUSCLKEN0_USB;  // enable USB peripheral clock
-
-  systick_init(); // Init system tick
-
-  gpio_init(); // Init IOs
-
-}
-
-/*--------------------------------------------------------------------*/
-/* Board porting API                                                  */
-/*--------------------------------------------------------------------*/
-
-void board_led_write(bool state)
-{
-  // Combine red and blue for pink Because it looks good :)
-  GPIO->P[LED_PORT].DOUT = (GPIO->P[LED_PORT].DOUT & ~((1 << LED_PIN_R) | (1 << LED_PIN_B))) | (state << LED_PIN_R) | (state << LED_PIN_B);
-}
-
-uint32_t board_button_read(void)
-{
-  return !!(GPIO->P[BUTTON_PORT].DIN & (1 << BUTTON_PIN));
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(char *file, uint32_t line)
-{ 
-  /* USER CODE BEGIN 6 */
-  /* User can add his own implementation to report the file name and line number,
-     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-  /* USER CODE END 6 */
-}
-#endif /* USE_FULL_ASSERT */
diff --git a/tinyusb/hw/bsp/spresense/board.mk b/tinyusb/hw/bsp/spresense/board.mk
deleted file mode 100755
index a46c42bd..00000000
--- a/tinyusb/hw/bsp/spresense/board.mk
+++ /dev/null
@@ -1,73 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/sony/cxd56/spresense-exported-sdk
-
-# Platforms are: Linux, Darwin, MSYS, CYGWIN
-PLATFORM := $(firstword $(subst _, ,$(shell uname -s 2>/dev/null)))
-
-ifeq ($(PLATFORM),Darwin)
-  # macOS
-  MKSPK = $(TOP)/hw/mcu/sony/cxd56/mkspk/mkspk
-else ifeq ($(PLATFORM),Linux)
-  # Linux
-  MKSPK = $(TOP)/hw/mcu/sony/cxd56/mkspk/mkspk
-else
-  # Cygwin/MSYS2
-  MKSPK = $(TOP)/hw/mcu/sony/cxd56/mkspk/mkspk.exe
-endif
-
-SERIAL ?= /dev/ttyUSB0
-
-CFLAGS += \
-	-DCONFIG_HAVE_DOUBLE \
-	-Dmain=spresense_main \
-	-pipe \
-	-std=gnu11 \
-	-mcpu=cortex-m4 \
-	-mthumb \
-	-mfpu=fpv4-sp-d16 \
-	-mfloat-abi=hard \
-	-mabi=aapcs \
-	-fno-builtin \
-	-fno-strength-reduce \
-	-fomit-frame-pointer \
-	-Wno-error=undef \
-	-Wno-error=cast-align \
-	-Wno-error=unused-parameter \
-	-DCFG_TUSB_MCU=OPT_MCU_CXD56 \
-
-# lwip/src/core/raw.c:334:43: error: declaration of 'recv' shadows a global declaration
-CFLAGS += -Wno-error=shadow
-
-SPRESENSE_SDK = $(TOP)/hw/mcu/sony/cxd56/spresense-exported-sdk
-
-SRC_C += src/portable/sony/cxd56/dcd_cxd56.c
-
-INC += \
-	$(SPRESENSE_SDK)/nuttx/include \
-	$(SPRESENSE_SDK)/nuttx/arch \
-	$(SPRESENSE_SDK)/nuttx/arch/chip \
-	$(SPRESENSE_SDK)/nuttx/arch/os \
-	$(SPRESENSE_SDK)/sdk/include \
-
-LIBS += \
-	$(SPRESENSE_SDK)/nuttx/libs/libapps.a \
-	$(SPRESENSE_SDK)/nuttx/libs/libnuttx.a \
-
-LD_FILE = hw/mcu/sony/cxd56/spresense-exported-sdk/nuttx/scripts/ramconfig.ld
-
-LDFLAGS += \
-	-Xlinker --entry=__start \
-	-nostartfiles \
-	-nodefaultlibs \
-	-Wl,--gc-sections \
-	-u spresense_main
-
-$(MKSPK): $(BUILD)/$(PROJECT).elf
-	$(MAKE) -C $(TOP)/hw/mcu/sony/cxd56/mkspk
-
-$(BUILD)/$(PROJECT).spk: $(MKSPK)
-	@echo CREATE $@
-	@$(MKSPK) -c 2 $(BUILD)/$(PROJECT).elf nuttx $@
-
-# flash
-flash: $(BUILD)/$(PROJECT).spk
-	@$(TOP)/hw/mcu/sony/cxd56/tools/flash_writer.py -s -c $(SERIAL) -d -b 115200 -n $<
diff --git a/tinyusb/hw/bsp/spresense/board_spresense.c b/tinyusb/hw/bsp/spresense/board_spresense.c
deleted file mode 100755
index 256bccd1..00000000
--- a/tinyusb/hw/bsp/spresense/board_spresense.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright 2019 Sony Semiconductor Solutions Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include <sys/boardctl.h>
-#include <nuttx/arch.h>
-#include <arch/board/board.h>
-#include <arch/chip/pin.h>
-
-#include "bsp/board.h"
-
-/*------------------------------------------------------------------*/
-/* MACRO TYPEDEF CONSTANT ENUM
- *------------------------------------------------------------------*/
-#define LED_PIN         PIN_I2S1_BCK
-
-#define BUTTON_PIN      PIN_HIF_IRQ_OUT
-
-// Initialize on-board peripherals : led, button, uart and USB
-void board_init(void)
-{
-  boardctl(BOARDIOC_INIT, 0);
-
-  board_gpio_write(PIN_I2S1_BCK, -1);
-  board_gpio_config(PIN_I2S1_BCK, 0, false, true, PIN_FLOAT);
-
-  board_gpio_write(PIN_HIF_IRQ_OUT, -1);
-  board_gpio_config(PIN_HIF_IRQ_OUT, 0, true, true, PIN_FLOAT);
-};
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-// Turn LED on or off
-void board_led_write(bool state)
-{
-  board_gpio_write(LED_PIN, state);
-}
-
-// Get the current state of button
-// a '1' means active (pressed), a '0' means inactive.
-uint32_t board_button_read(void)
-{
-  if (board_gpio_read(BUTTON_PIN)) 
-  {
-    return 0;
-  }
-
-  return 1;
-}
-
-// Get characters from UART
-int board_uart_read(uint8_t *buf, int len)
-{
-  int r = read(0, buf, len);
-
-  return r;
-}
-
-// Send characters to UART
-int board_uart_write(void const *buf, int len)
-{
-  int r = write(1, buf, len);
-
-  return r;
-}
-
-// Get current milliseconds
-uint32_t board_millis(void)
-{
-  struct timespec tp;
-
-    /* Wait until RTC is available */
-    while (g_rtc_enabled == false);
-
-    if (clock_gettime(CLOCK_MONOTONIC, &tp)) 
-    {
-        return 0;
-    }
-
-    return (((uint64_t)tp.tv_sec) * 1000 + tp.tv_nsec / 1000000);
-}
diff --git a/tinyusb/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.h b/tinyusb/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.h
deleted file mode 100755
index 7c527e2c..00000000
--- a/tinyusb/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PORT              GPIOA
-#define LED_PIN               GPIO_PIN_5
-#define LED_STATE_ON          1
-
-// Button
-#define BUTTON_PORT           GPIOC
-#define BUTTON_PIN            GPIO_PIN_13
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_DEV              USART2
-#define UART_CLK_EN           __HAL_RCC_USART2_CLK_ENABLE
-#define UART_GPIO_PORT        GPIOA
-#define UART_GPIO_AF          GPIO_AF1_USART2
-#define UART_TX_PIN           GPIO_PIN_2
-#define UART_RX_PIN           GPIO_PIN_3
-
-//--------------------------------------------------------------------+
-// RCC Clock
-//--------------------------------------------------------------------+
-static inline void board_stm32f0_clock_init(void)
-{
-  /* Configure the system clock to 48 MHz */
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
-
-  /* Enable HSE Oscillator and activate PLL with 8 MHz HSE as source */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;
-  RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
-     clocks dividers */
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1);
-
-
-  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
-  PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) ;
-}
-
-static inline void board_vbus_sense_init(void)
-{
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk b/tinyusb/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
deleted file mode 100755
index 9e636cd7..00000000
--- a/tinyusb/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-CFLAGS += -DSTM32F070xB
-
-LD_FILE = $(BOARD_PATH)/stm32F070rbtx_flash.ld
-
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f070xb.s
-
-# For flash-jlink target
-JLINK_DEVICE = stm32f070rb
-
-# flash target using on-board stlink
-flash: flash-stlink
diff --git a/tinyusb/hw/bsp/stm32f0/boards/stm32f070rbnucleo/stm32F070rbtx_flash.ld b/tinyusb/hw/bsp/stm32f0/boards/stm32f070rbnucleo/stm32F070rbtx_flash.ld
deleted file mode 100755
index 59e18f37..00000000
--- a/tinyusb/hw/bsp/stm32f0/boards/stm32f070rbnucleo/stm32F070rbtx_flash.ld
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
-******************************************************************************
-**
-**  File        : LinkerScript.ld
-**
-**  Author		: Auto-generated by STM32CubeIDE
-**
-**  Abstract    : Linker script for STM32F070RBTx Device from STM32F0 series
-**                      128Kbytes FLASH
-**                      16Kbytes RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**  Distribution: The file is distributed as is without any warranty
-**                of any kind.
-**
-*****************************************************************************
-** @attention
-**
-** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
-**
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**   1. Redistributions of source code must retain the above copyright notice,
-**      this list of conditions and the following disclaimer.
-**   2. Redistributions in binary form must reproduce the above copyright notice,
-**      this list of conditions and the following disclaimer in the documentation
-**      and/or other materials provided with the distribution.
-**   3. Neither the name of STMicroelectronics nor the names of its contributors
-**      may be used to endorse or promote products derived from this software
-**      without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20004000;	/* end of "RAM" Ram type memory */
-
-_Min_Heap_Size = 0x200;	/* required amount of heap  */
-_Min_Stack_Size = 0x400;	/* required amount of stack */
-
-/* Memories definition */
-MEMORY
-{
-    RAM	(xrw)	: ORIGIN = 0x20000000,	LENGTH = 16K
-    FLASH	(rx)	: ORIGIN = 0x8000000,	LENGTH = 128K
-}
-
-/* Sections */
-SECTIONS
-{
-  /* The startup code into "FLASH" Rom type memory */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data into "FLASH" Rom type memory */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data into "FLASH" Rom type memory */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { 
-  	. = ALIGN(4);
-  	*(.ARM.extab* .gnu.linkonce.armextab.*)
-  	. = ALIGN(4);
-  } >FLASH
-  
-  .ARM : {
-    . = ALIGN(4);
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-    . = ALIGN(4);
-  } >FLASH
-
-  .preinit_array     :
-  {
-    . = ALIGN(4);
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-    . = ALIGN(4);
-  } >FLASH
-  
-  .init_array :
-  {
-    . = ALIGN(4);
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-    . = ALIGN(4);
-  } >FLASH
-  
-  .fini_array :
-  {
-    . = ALIGN(4);
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-    . = ALIGN(4);
-  } >FLASH
-
-  /* Used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections into "RAM" Ram type memory */
-  .data : 
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-    
-  } >RAM AT> FLASH
-  
-  /* Uninitialized data section into "RAM" Ram type memory */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-  /* Remove information from the compiler libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
diff --git a/tinyusb/hw/bsp/stm32f0/boards/stm32f072disco/STM32F072RBTx_FLASH.ld b/tinyusb/hw/bsp/stm32f0/boards/stm32f072disco/STM32F072RBTx_FLASH.ld
deleted file mode 100755
index 8d31f6a0..00000000
--- a/tinyusb/hw/bsp/stm32f0/boards/stm32f072disco/STM32F072RBTx_FLASH.ld
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
-*****************************************************************************
-**
-
-**  File        : LinkerScript.ld
-**
-**  Abstract    : Linker script for STM32F072RBTx Device with
-**                128KByte FLASH, 16KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-**  (c)Copyright Ac6.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Ac6 permit registered System Workbench for MCU users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the System Workbench for MCU toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20004000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 128K
-RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 16K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-  
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
-
-
diff --git a/tinyusb/hw/bsp/stm32f0/boards/stm32f072disco/board.h b/tinyusb/hw/bsp/stm32f0/boards/stm32f072disco/board.h
deleted file mode 100755
index 0b1824b8..00000000
--- a/tinyusb/hw/bsp/stm32f0/boards/stm32f072disco/board.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PORT              GPIOC
-#define LED_PIN               GPIO_PIN_6
-#define LED_STATE_ON          1
-
-// Button
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE   1
-
-// UART
-#define UART_DEV              USART1
-#define UART_CLK_EN           __HAL_RCC_USART1_CLK_ENABLE
-#define UART_GPIO_PORT        GPIOA
-#define UART_GPIO_AF          GPIO_AF1_USART1
-#define UART_TX_PIN           GPIO_PIN_9
-#define UART_RX_PIN           GPIO_PIN_10
-
-//--------------------------------------------------------------------+
-// RCC Clock
-//--------------------------------------------------------------------+
-static inline void board_stm32f0_clock_init(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Select HSI48 Oscillator as PLL source */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
-  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI48;
-  RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
-  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL2;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1);
-}
-
-static inline void board_vbus_sense_init(void)
-{
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/stm32f0/boards/stm32f072disco/board.mk b/tinyusb/hw/bsp/stm32f0/boards/stm32f072disco/board.mk
deleted file mode 100755
index 2ef0ee63..00000000
--- a/tinyusb/hw/bsp/stm32f0/boards/stm32f072disco/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-CFLAGS += -DSTM32F072xB
-
-LD_FILE = $(BOARD_PATH)/STM32F072RBTx_FLASH.ld
-
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f072xb.s
-
-# For flash-jlink target
-JLINK_DEVICE = stm32f072rb
-
-# flash target using on-board stlink
-flash: flash-stlink
diff --git a/tinyusb/hw/bsp/stm32f0/boards/stm32f072eval/STM32F072VBTx_FLASH.ld b/tinyusb/hw/bsp/stm32f0/boards/stm32f072eval/STM32F072VBTx_FLASH.ld
deleted file mode 100755
index 581613a5..00000000
--- a/tinyusb/hw/bsp/stm32f0/boards/stm32f072eval/STM32F072VBTx_FLASH.ld
+++ /dev/null
@@ -1,177 +0,0 @@
-/**
- ******************************************************************************
- * @file      LinkerScript.ld
- * @author    Auto-generated by STM32CubeIDE
- *  Abstract    : Linker script for STM32072B-EVAL Board embedding STM32F072VBTx Device from stm32f0 series
- *                      128Kbytes FLASH
- *                      16Kbytes RAM
- *
- *            Set heap size, stack size and stack location according
- *            to application requirements.
- *
- *            Set memory bank area and size if external memory is used
- ******************************************************************************
- * @attention
- *
- * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- *                        opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */
-
-_Min_Heap_Size = 0x200 ;	/* required amount of heap  */
-_Min_Stack_Size = 0x400 ;	/* required amount of stack */
-
-/* Memories definition */
-MEMORY
-{
-  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 16K
-  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 128K
-}
-
-/* Sections */
-SECTIONS
-{
-  /* The startup code into "FLASH" Rom type memory */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data into "FLASH" Rom type memory */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data into "FLASH" Rom type memory */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : {
-    . = ALIGN(4);
-    *(.ARM.extab* .gnu.linkonce.armextab.*)
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM : {
-    . = ALIGN(4);
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-    . = ALIGN(4);
-  } >FLASH
-
-  .preinit_array     :
-  {
-    . = ALIGN(4);
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-    . = ALIGN(4);
-  } >FLASH
-
-  .init_array :
-  {
-    . = ALIGN(4);
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-    . = ALIGN(4);
-  } >FLASH
-
-  .fini_array :
-  {
-    . = ALIGN(4);
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-    . = ALIGN(4);
-  } >FLASH
-
-  /* Used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections into "RAM" Ram type memory */
-  .data :
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-    *(.RamFunc)        /* .RamFunc sections */
-    *(.RamFunc*)       /* .RamFunc* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-
-  } >RAM AT> FLASH
-
-  /* Uninitialized data section into "RAM" Ram type memory */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss section */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-  /* Remove information from the compiler libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
diff --git a/tinyusb/hw/bsp/stm32f0/boards/stm32f072eval/board.h b/tinyusb/hw/bsp/stm32f0/boards/stm32f072eval/board.h
deleted file mode 100755
index 8869d5dc..00000000
--- a/tinyusb/hw/bsp/stm32f0/boards/stm32f072eval/board.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PORT              GPIOD
-#define LED_PIN               GPIO_PIN_8	// LED1, GREEN
-// #define LED_PIN               GPIO_PIN_9	// LED2, ORANGE
-// #define LED_PIN               GPIO_PIN_10	// LED3, RED
-// #define LED_PIN               GPIO_PIN_11	// LED4, BLUE
-#define LED_STATE_ON          0
-
-// Button
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0 // JOY_SEL
-#define BUTTON_STATE_ACTIVE   1
-
-// UART
-#define UART_DEV              USART2
-#define UART_CLK_EN           __HAL_RCC_USART2_CLK_ENABLE
-#define UART_GPIO_PORT        GPIOD
-#define UART_GPIO_AF          GPIO_AF0_USART2
-#define UART_TX_PIN           GPIO_PIN_5
-#define UART_RX_PIN           GPIO_PIN_6
-
-//--------------------------------------------------------------------+
-// RCC Clock
-//--------------------------------------------------------------------+
-static inline void board_stm32f0_clock_init(void)
-{
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
-
-  /** Initializes the RCC Oscillators according to the specified parameters
-   * in the RCC_OscInitTypeDef structure.
-   */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
-  RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
-  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;
-  RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
-
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /** Initializes the CPU, AHB and APB buses clocks
-   */
-  RCC_ClkInitStruct.ClockType =
-      RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
-
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1);
-
-  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB | RCC_PERIPHCLK_USART2;
-  PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
-  PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
-
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
-}
-
-static inline void board_vbus_sense_init(void)
-{
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/stm32f0/boards/stm32f072eval/board.mk b/tinyusb/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
deleted file mode 100755
index f7f8c84e..00000000
--- a/tinyusb/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-CFLAGS += -DSTM32F072xB -DLSI_VALUE=40000
-
-LD_FILE = $(BOARD_PATH)/STM32F072VBTx_FLASH.ld
-
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f072xb.s
-
-# For flash-jlink target
-JLINK_DEVICE = stm32f072vb
-
-# flash target using on-board stlink
-flash: flash-stlink
diff --git a/tinyusb/hw/bsp/stm32f0/family.c b/tinyusb/hw/bsp/stm32f0/family.c
deleted file mode 100755
index 853bb9d6..00000000
--- a/tinyusb/hw/bsp/stm32f0/family.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "stm32f0xx_hal.h"
-#include "bsp/board.h"
-#include "board.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-UART_HandleTypeDef UartHandle;
-
-void board_init(void)
-{
-  board_stm32f0_clock_init();
-
-  // Enable All GPIOs clocks
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  __HAL_RCC_GPIOC_CLK_ENABLE();
-  __HAL_RCC_GPIOD_CLK_ENABLE();
-  __HAL_RCC_GPIOF_CLK_ENABLE();
-
-  // Enable UART Clock
-  UART_CLK_EN();
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-#endif
-
-  // LED
-  GPIO_InitTypeDef  GPIO_InitStruct;
-  GPIO_InitStruct.Pin = LED_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
-
-  // Button
-  GPIO_InitStruct.Pin = BUTTON_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
-
-  // Uart
-  GPIO_InitStruct.Pin       = UART_TX_PIN | UART_RX_PIN;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_PULLUP;
-  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
-  GPIO_InitStruct.Alternate = UART_GPIO_AF;
-  HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
-
-  UartHandle.Instance        = UART_DEV;
-  UartHandle.Init.BaudRate   = CFG_BOARD_UART_BAUDRATE;
-  UartHandle.Init.WordLength = UART_WORDLENGTH_8B;
-  UartHandle.Init.StopBits   = UART_STOPBITS_1;
-  UartHandle.Init.Parity     = UART_PARITY_NONE;
-  UartHandle.Init.HwFlowCtl  = UART_HWCONTROL_NONE;
-  UartHandle.Init.Mode       = UART_MODE_TX_RX;
-  UartHandle.Init.OverSampling = UART_OVERSAMPLING_16;
-  HAL_UART_Init(&UartHandle);
-
-  // USB Pins
-  // Configure USB DM and DP pins. This is optional, and maintained only for user guidance.
-  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  // USB Clock enable
-  __HAL_RCC_USB_CLK_ENABLE();
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  HAL_UART_Transmit(&UartHandle, (uint8_t*) buf, len, 0xffff);
-  return len;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-
-void HardFault_Handler (void)
-{
-  asm("bkpt");
-}
-
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  (void) file; (void) line;
-  /* USER CODE BEGIN 6 */
-  /* User can add his own implementation to report the file name and line number,
-     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-  /* USER CODE END 6 */
-}
-#endif /* USE_FULL_ASSERT */
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
-}
diff --git a/tinyusb/hw/bsp/stm32f0/family.mk b/tinyusb/hw/bsp/stm32f0/family.mk
deleted file mode 100755
index 08cbf562..00000000
--- a/tinyusb/hw/bsp/stm32f0/family.mk
+++ /dev/null
@@ -1,40 +0,0 @@
-UF2_FAMILY_ID = 0x647824b6
-ST_FAMILY = f0
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
-ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0 \
-  -mfloat-abi=soft \
-  -nostdlib -nostartfiles \
-  -DCFG_EXAMPLE_MSC_READONLY \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32F0
-
-# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align
-
-SRC_C += \
-  src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
-  $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-  $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-  $(TOP)/$(ST_CMSIS)/Include \
-  $(TOP)/$(ST_HAL_DRIVER)/Inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
diff --git a/tinyusb/hw/bsp/stm32f0/stm32f0xx_hal_conf.h b/tinyusb/hw/bsp/stm32f0/stm32f0xx_hal_conf.h
deleted file mode 100755
index cfa66b36..00000000
--- a/tinyusb/hw/bsp/stm32f0/stm32f0xx_hal_conf.h
+++ /dev/null
@@ -1,321 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_CONF_H
-#define __STM32F0xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-#define HAL_MODULE_ENABLED  
-/*#define HAL_ADC_MODULE_ENABLED   */
-/*#define HAL_CAN_MODULE_ENABLED   */
-/*#define HAL_CEC_MODULE_ENABLED   */
-/*#define HAL_COMP_MODULE_ENABLED   */
-#define HAL_CORTEX_MODULE_ENABLED
-/*#define HAL_CRC_MODULE_ENABLED   */
-/*#define HAL_DAC_MODULE_ENABLED   */
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_GPIO_MODULE_ENABLED
-/*#define HAL_EXTI_MODULE_ENABLED   */
-/*#define HAL_I2C_MODULE_ENABLED */
-/*#define HAL_I2S_MODULE_ENABLED */
-/*#define HAL_IRDA_MODULE_ENABLED */
-/*#define HAL_IWDG_MODULE_ENABLED */
-#define HAL_PCD_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-/*#define HAL_RTC_MODULE_ENABLED   */
-/*#define HAL_SMARTCARD_MODULE_ENABLED   */
-/*#define HAL_SMBUS_MODULE_ENABLED   */
-/*#define HAL_SPI_MODULE_ENABLED   */
-/*#define HAL_TIM_MODULE_ENABLED   */
-/*#define HAL_TSC_MODULE_ENABLED   */
-#define HAL_UART_MODULE_ENABLED
-/*#define HAL_USART_MODULE_ENABLED   */
-/*#define HAL_WWDG_MODULE_ENABLED */
-
-/* ######################### Oscillator Values adaptation ################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE            8000000U  /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-/**
-  * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
-  *        Timeout value 
-  */
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT  100U      /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE            8000000U  /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup 
-  *        Timeout value 
-  */
-#if !defined  (HSI_STARTUP_TIMEOUT) 
-  #define HSI_STARTUP_TIMEOUT  5000U     /*!< Time out for HSI start up */
-#endif /* HSI_STARTUP_TIMEOUT */  
-
-/**
-  * @brief Internal High Speed oscillator for ADC (HSI14) value.
-  */
-#if !defined  (HSI14_VALUE) 
-  #define HSI14_VALUE          14000000U /*!< Value of the Internal High Speed oscillator for ADC in Hz.
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-#endif /* HSI14_VALUE */
-
-/**
-  * @brief Internal High Speed oscillator for USB (HSI48) value.
-  */
-#if !defined  (HSI48_VALUE) 
-  #define HSI48_VALUE          48000000U /*!< Value of the Internal High Speed oscillator for USB in Hz.
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-#endif /* HSI48_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
-  #define LSI_VALUE            32000U    
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
-  #define LSE_VALUE            32768U    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */     
-
-/**
-  * @brief Time out for LSE start up value in ms.
-  */
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT  5000U     /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    3300U  /*!< Value of VDD in mv */           
-#define  TICK_INT_PRIORITY            ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default)             */
-                                                                              /*  Warning: Must be set to higher priority for HAL_Delay()  */
-                                                                              /*  and HAL_GetTick() usage under interrupt context          */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  INSTRUCTION_CACHE_ENABLE     0U
-#define  DATA_CACHE_ENABLE            0U
-#define  USE_SPI_CRC                  1U
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_COMP_REGISTER_CALLBACKS        0U /* COMP register callback disabled      */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_TSC_REGISTER_CALLBACKS         0U /* TSC register callback disabled       */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
- #define USE_FULL_ASSERT   1 
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
- #include "stm32f0xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
- #include "stm32f0xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32f0xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f0xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
- #include "stm32f0xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
- #include "stm32f0xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
- #include "stm32f0xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32f0xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_COMP_MODULE_ENABLED
- #include "stm32f0xx_hal_comp.h"
-#endif /* HAL_COMP_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
- #include "stm32f0xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
- #include "stm32f0xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
- #include "stm32f0xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f0xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f0xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f0xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f0xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f0xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f0xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f0xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f0xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32f0xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f0xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f0xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_TSC_MODULE_ENABLED
- #include "stm32f0xx_hal_tsc.h"
-#endif /* HAL_TSC_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f0xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f0xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f0xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */    
-    
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/tinyusb/hw/bsp/stm32f1/boards/stm32f103_bluepill/STM32F103X8_FLASH.ld b/tinyusb/hw/bsp/stm32f1/boards/stm32f103_bluepill/STM32F103X8_FLASH.ld
deleted file mode 100755
index ca180490..00000000
--- a/tinyusb/hw/bsp/stm32f1/boards/stm32f103_bluepill/STM32F103X8_FLASH.ld
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
-*****************************************************************************
-**
-**  File        : STM32F103XB_FLASH.ld
-**
-**  Abstract    : Linker script for STM32F103xB Device with
-**                128KByte FLASH, 20KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-**  (c)Copyright Ac6.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Ac6 permit registered System Workbench for MCU users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the System Workbench for MCU toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20004FFF;    /* end of RAM */
-
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 64K
-RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 20K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-  
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
diff --git a/tinyusb/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h b/tinyusb/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h
deleted file mode 100755
index 57a607ed..00000000
--- a/tinyusb/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PORT              GPIOC
-#define LED_PIN               GPIO_PIN_13
-#define LED_STATE_ON          0
-
-// Button
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE   1
-
-// UART
-//#define UART_DEV              USART1
-//#define UART_CLK_EN           __HAL_RCC_USART1_CLK_ENABLE
-//#define UART_GPIO_PORT        GPIOA
-//#define UART_GPIO_AF          GPIO_AF1_USART1
-//#define UART_TX_PIN           GPIO_PIN_9
-//#define UART_RX_PIN           GPIO_PIN_10
-
-//--------------------------------------------------------------------+
-// RCC Clock
-//--------------------------------------------------------------------+
-static inline void board_stm32f1_clock_init(void)
-{
-  RCC_ClkInitTypeDef clkinitstruct = {0};
-  RCC_OscInitTypeDef oscinitstruct = {0};
-  RCC_PeriphCLKInitTypeDef rccperiphclkinit = {0};
-
-  /* Enable HSE Oscillator and activate PLL with HSE as source */
-  oscinitstruct.OscillatorType  = RCC_OSCILLATORTYPE_HSE;
-  oscinitstruct.HSEState        = RCC_HSE_ON;
-  oscinitstruct.HSEPredivValue  = RCC_HSE_PREDIV_DIV1;
-  oscinitstruct.PLL.PLLMUL      = RCC_PLL_MUL9;
-  oscinitstruct.PLL.PLLState    = RCC_PLL_ON;
-  oscinitstruct.PLL.PLLSource   = RCC_PLLSOURCE_HSE;
-  HAL_RCC_OscConfig(&oscinitstruct);
-
-  /* USB clock selection */
-  rccperiphclkinit.PeriphClockSelection = RCC_PERIPHCLK_USB;
-  rccperiphclkinit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
-  HAL_RCCEx_PeriphCLKConfig(&rccperiphclkinit);
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  clkinitstruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  clkinitstruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  clkinitstruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  clkinitstruct.APB1CLKDivider = RCC_HCLK_DIV2;
-  clkinitstruct.APB2CLKDivider = RCC_HCLK_DIV1;
-  HAL_RCC_ClockConfig(&clkinitstruct, FLASH_LATENCY_2);
-}
-
-static inline void board_vbus_sense_init(void)
-{
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk b/tinyusb/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk
deleted file mode 100755
index 9c690ca7..00000000
--- a/tinyusb/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-CFLAGS += -DSTM32F103xB -DHSE_VALUE=8000000U
-
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/STM32F103X8_FLASH.ld
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f103xb.s
-
-# For flash-jlink target
-JLINK_DEVICE = stm32f103c8
-
-# flash target ROM bootloader
-flash: flash-dfu-util
diff --git a/tinyusb/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld b/tinyusb/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld
deleted file mode 100755
index da40d1eb..00000000
--- a/tinyusb/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
-*****************************************************************************
-**
-**  File        : STM32F103XB_FLASH.ld
-**
-**  Abstract    : Linker script for STM32F103xB Device with
-**                128KByte FLASH, 20KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-**  (c)Copyright Ac6.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Ac6 permit registered System Workbench for MCU users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the System Workbench for MCU toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20004FFF;    /* end of RAM */
-
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 256K
-RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 48K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-  
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
diff --git a/tinyusb/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h b/tinyusb/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h
deleted file mode 100755
index bedce7f1..00000000
--- a/tinyusb/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PORT              GPIOA
-#define LED_PIN               GPIO_PIN_8
-#define LED_STATE_ON          0
-
-// Button
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE   1
-
-// UART
-//#define UART_DEV              USART1
-//#define UART_CLK_EN           __HAL_RCC_USART1_CLK_ENABLE
-//#define UART_GPIO_PORT        GPIOA
-//#define UART_GPIO_AF          GPIO_AF1_USART1
-//#define UART_TX_PIN           GPIO_PIN_9
-//#define UART_RX_PIN           GPIO_PIN_10
-
-//--------------------------------------------------------------------+
-// RCC Clock
-//--------------------------------------------------------------------+
-static inline void board_stm32f1_clock_init(void)
-{
-  RCC_ClkInitTypeDef clkinitstruct = {0};
-  RCC_OscInitTypeDef oscinitstruct = {0};
-  RCC_PeriphCLKInitTypeDef rccperiphclkinit = {0};
-
-  /* Enable HSE Oscillator and activate PLL with HSE as source */
-  oscinitstruct.OscillatorType  = RCC_OSCILLATORTYPE_HSE;
-  oscinitstruct.HSEState        = RCC_HSE_ON;
-  oscinitstruct.HSEPredivValue  = RCC_HSE_PREDIV_DIV1;
-  oscinitstruct.PLL.PLLMUL      = RCC_PLL_MUL9;
-  oscinitstruct.PLL.PLLState    = RCC_PLL_ON;
-  oscinitstruct.PLL.PLLSource   = RCC_PLLSOURCE_HSE;
-  HAL_RCC_OscConfig(&oscinitstruct);
-
-  /* USB clock selection */
-  rccperiphclkinit.PeriphClockSelection = RCC_PERIPHCLK_USB;
-  rccperiphclkinit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
-  HAL_RCCEx_PeriphCLKConfig(&rccperiphclkinit);
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  clkinitstruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  clkinitstruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  clkinitstruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  clkinitstruct.APB1CLKDivider = RCC_HCLK_DIV2;
-  clkinitstruct.APB2CLKDivider = RCC_HCLK_DIV1;
-  HAL_RCC_ClockConfig(&clkinitstruct, FLASH_LATENCY_2);
-}
-
-static inline void board_vbus_sense_init(void)
-{
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk b/tinyusb/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk
deleted file mode 100755
index eeda8708..00000000
--- a/tinyusb/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-CFLAGS += -DSTM32F103xB -DHSE_VALUE=8000000U
-
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/STM32F103XC_FLASH.ld
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f103xb.s
-
-# For flash-jlink target
-JLINK_DEVICE = stm32f103rc
-
-# flash target ROM bootloader
-flash: flash-jlink
diff --git a/tinyusb/hw/bsp/stm32f1/family.c b/tinyusb/hw/bsp/stm32f1/family.c
deleted file mode 100755
index 8fcf9ebd..00000000
--- a/tinyusb/hw/bsp/stm32f1/family.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "stm32f1xx_hal.h"
-#include "bsp/board.h"
-#include "board.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_HP_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-void USB_LP_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-void USBWakeUp_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-void board_init(void)
-{
-  board_stm32f1_clock_init();
-  
-  // Enable All GPIOs clocks
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  __HAL_RCC_GPIOC_CLK_ENABLE();
-  __HAL_RCC_GPIOD_CLK_ENABLE();
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB_HP_CAN1_TX_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-  NVIC_SetPriority(USB_LP_CAN1_RX0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-  NVIC_SetPriority(USBWakeUp_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-#endif
-  
-  // LED
-  GPIO_InitTypeDef  GPIO_InitStruct;
-  GPIO_InitStruct.Pin = LED_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = LED_STATE_ON ? GPIO_PULLDOWN : GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
-
-  // Button
-  GPIO_InitStruct.Pin = BUTTON_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN : GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
-
-  // USB Pins
-  // Configure USB DM and DP pins.
-  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  // USB Clock enable
-  __HAL_RCC_USB_CLK_ENABLE();
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-
-void HardFault_Handler (void)
-{
-  asm("bkpt");
-}
-
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(char *file, uint32_t line)
-{ 
-  /* USER CODE BEGIN 6 */
-  /* User can add his own implementation to report the file name and line number,
-     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-  /* USER CODE END 6 */
-}
-#endif /* USE_FULL_ASSERT */
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
-}
diff --git a/tinyusb/hw/bsp/stm32f1/family.mk b/tinyusb/hw/bsp/stm32f1/family.mk
deleted file mode 100755
index 3fb2e6e7..00000000
--- a/tinyusb/hw/bsp/stm32f1/family.mk
+++ /dev/null
@@ -1,45 +0,0 @@
-ST_FAMILY = f1
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
-ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m3 \
-  -mfloat-abi=soft \
-  -nostdlib -nostartfiles \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32F1
-
-# mcu driver cause following warnings
-#CFLAGS += -Wno-error=unused-parameter
-
-# All source paths should be relative to the top level.
-SRC_C += \
-  src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
-  $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
-
-INC += \
-  $(TOP)/$(BOARD_PATH) \
-  $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-  $(TOP)/$(ST_CMSIS)/Include \
-  $(TOP)/$(ST_HAL_DRIVER)/Inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
-
-# For flash-jlink target
-JLINK_DEVICE = stm32f103c8
-
-# flash target ROM bootloader
-flash-dfu-util: $(BUILD)/$(PROJECT).bin
-	dfu-util -R -a 0 --dfuse-address 0x08000000 -D $<
diff --git a/tinyusb/hw/bsp/stm32f1/stm32f1xx_hal_conf.h b/tinyusb/hw/bsp/stm32f1/stm32f1xx_hal_conf.h
deleted file mode 100755
index a4a3f308..00000000
--- a/tinyusb/hw/bsp/stm32f1/stm32f1xx_hal_conf.h
+++ /dev/null
@@ -1,379 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USB_Device/HID_Standalone/Inc/stm32f1xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration template file.
-  *          This file should be copied to the application folder and renamed
-  *          to stm32f1xx_hal_conf.h.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_CONF_H
-#define __STM32F1xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-#define HAL_MODULE_ENABLED
-/* #define HAL_ADC_MODULE_ENABLED */
-/* #define HAL_CAN_MODULE_ENABLED */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
-#define HAL_CORTEX_MODULE_ENABLED */
-/* #define HAL_CRC_MODULE_ENABLED */
-/* #define HAL_DAC_MODULE_ENABLED */
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_EXTI_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED */
-/* #define HAL_IRDA_MODULE_ENABLED */
-/* #define HAL_IWDG_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_PCCARD_MODULE_ENABLED */
-#define HAL_PCD_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RTC_MODULE_ENABLED */
-/* #define HAL_SD_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_SPI_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_TIM_MODULE_ENABLED */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED */
-
-/* ########################## Oscillator Values adaptation ####################*/
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-#if defined(USE_STM3210C_EVAL)
-  #define HSE_VALUE    25000000U /*!< Value of the External oscillator in Hz */
-#else
-  #define HSE_VALUE    8000000U /*!< Value of the External oscillator in Hz */
-#endif
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    100U      /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE              8000000U  /*!< Value of the Internal oscillator in Hz */
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE               40000U    /*!< LSI Typical Value in Hz */
-#endif /* LSI_VALUE */                     /*!< Value of the Internal Low Speed oscillator in Hz
-                                                The real value may vary depending on the variations
-                                                in voltage and temperature. */
-
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  *        This value is used by the UART, RTC HAL module to compute the system frequency
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE               32768U    /*!< Value of the External oscillator in Hz*/
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    5000U     /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    3300U /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            0x00U /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1U */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */   
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    8U                  /* 8 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    4U                  /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848 PHY Address*/ 
-#define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
-#define PHY_RESET_DELAY                 0x000000FFU
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                0x00000FFFU
-
-#define PHY_READ_TO                     0x0000FFFFU
-#define PHY_WRITE_TO                    0x0000FFFFU
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
- 
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
-#define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
-#define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
- 
-#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
-
-#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
-#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
-
-#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
-#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
- #include "stm32f1xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
- #include "stm32f1xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-   
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32f1xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f1xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-   
-#ifdef HAL_CAN_MODULE_ENABLED
- #include "stm32f1xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "Legacy/stm32f1xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
- #include "stm32f1xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
- #include "stm32f1xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
- #include "stm32f1xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
- #include "stm32f1xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
- #include "stm32f1xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f1xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f1xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f1xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f1xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f1xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f1xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f1xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
- #include "stm32f1xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f1xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */  
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
- #include "stm32f1xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */     
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f1xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f1xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f1xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f1xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f1xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f1xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f1xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f1xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */    
-    
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tinyusb/hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld b/tinyusb/hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld
deleted file mode 100755
index 29e387f2..00000000
--- a/tinyusb/hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
-*****************************************************************************
-**
-
-**  File        : LinkerScript.ld
-**
-**  Abstract    : Linker script for STM32F207IGHx Device with
-**                1024KByte FLASH, 128KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-**  (c)Copyright Ac6.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Ac6 permit registered System Workbench for MCU users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the System Workbench for MCU toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20020000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K
-RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-  
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
-
-
diff --git a/tinyusb/hw/bsp/stm32f207nucleo/board.mk b/tinyusb/hw/bsp/stm32f207nucleo/board.mk
deleted file mode 100755
index 2b979f3d..00000000
--- a/tinyusb/hw/bsp/stm32f207nucleo/board.mk
+++ /dev/null
@@ -1,48 +0,0 @@
-ST_FAMILY = f2
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
-ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m3 \
-  -mfloat-abi=soft \
-  -nostdlib -nostartfiles \
-  -DSTM32F207xx \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32F2
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=sign-compare
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/STM32F207ZGTx_FLASH.ld
-
-SRC_C += \
-  src/portable/st/synopsys/dcd_synopsys.c \
-  $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
-
-SRC_S += \
-  $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f207xx.s
-
-INC += \
-  $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-  $(TOP)/$(ST_CMSIS)/Include \
-  $(TOP)/$(ST_HAL_DRIVER)/Inc \
-  $(TOP)/hw/bsp/$(BOARD)
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
-
-# For flash-jlink target
-JLINK_DEVICE = stm32f207zg
-
-# flash target using on-board stlink
-flash: flash-stlink
diff --git a/tinyusb/hw/bsp/stm32f207nucleo/stm32f207nucleo.c b/tinyusb/hw/bsp/stm32f207nucleo/stm32f207nucleo.c
deleted file mode 100755
index 619c90d6..00000000
--- a/tinyusb/hw/bsp/stm32f207nucleo/stm32f207nucleo.c
+++ /dev/null
@@ -1,213 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "../board.h"
-
-#include "stm32f2xx_hal.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void OTG_FS_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-#define LED_PORT              GPIOB
-#define LED_PIN               GPIO_PIN_14
-#define LED_STATE_ON          1
-
-#define BUTTON_PORT           GPIOC
-#define BUTTON_PIN            GPIO_PIN_13
-#define BUTTON_STATE_ACTIVE   1
-
-
-// enable all LED, Button, Uart, USB clock
-static void all_rcc_clk_enable(void)
-{
-  __HAL_RCC_GPIOA_CLK_ENABLE();  // USB D+, D-
-  __HAL_RCC_GPIOB_CLK_ENABLE();  // LED
-  __HAL_RCC_GPIOC_CLK_ENABLE();  // Button
-}
-
-/**
-  * @brief  System Clock Configuration
-  *         The system Clock is configured as follow :
-  *            System Clock source            = PLL (HSE)
-  *            SYSCLK(Hz)                     = 120000000
-  *            HCLK(Hz)                       = 120000000
-  *            AHB Prescaler                  = 1
-  *            APB1 Prescaler                 = 4
-  *            APB2 Prescaler                 = 2
-  *            HSE Frequency(Hz)              = 8000000
-  *            PLL_M                          = HSE_VALUE/1000000
-  *            PLL_N                          = 240
-  *            PLL_P                          = 2
-  *            PLL_Q                          = 5
-  *            VDD(V)                         = 3.3
-  *            Flash Latency(WS)              = 3
-  * @param  None
-  * @retval None
-  */
-void SystemClock_Config(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable HSE Oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
-  RCC_OscInitStruct.PLL.PLLN = 240;
-  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
-  RCC_OscInitStruct.PLL.PLLQ = 5;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
-     clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3);
-}
-
-void board_init(void)
-{
-  SystemClock_Config();
-  
-  #if CFG_TUSB_OS  == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-  #endif
-
-
-  all_rcc_clk_enable();
-
-  GPIO_InitTypeDef  GPIO_InitStruct;
-
-  // LED
-  GPIO_InitStruct.Pin = LED_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
-
-  board_led_write(false);
-
-  // Button
-  GPIO_InitStruct.Pin = BUTTON_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
-
-  /* Configure DM DP Pins */
-  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* Configure VBUS Pin */
-  GPIO_InitStruct.Pin = GPIO_PIN_9;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* Configure ID pin */
-  GPIO_InitStruct.Pin = GPIO_PIN_10;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* Enable USB FS Clocks */
-  __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
-
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-
-void HardFault_Handler (void)
-{
-  asm("bkpt");
-}
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
-}
diff --git a/tinyusb/hw/bsp/stm32f207nucleo/stm32f2xx_hal_conf.h b/tinyusb/hw/bsp/stm32f207nucleo/stm32f2xx_hal_conf.h
deleted file mode 100755
index 2ab46b26..00000000
--- a/tinyusb/hw/bsp/stm32f207nucleo/stm32f2xx_hal_conf.h
+++ /dev/null
@@ -1,407 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f2xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_CONF_H
-#define __STM32F2xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-#define HAL_MODULE_ENABLED  
-/* #define HAL_ADC_MODULE_ENABLED   */
-/* #define HAL_CAN_MODULE_ENABLED   */
-/* #define HAL_CRC_MODULE_ENABLED   */
-/* #define HAL_CRYP_MODULE_ENABLED   */
-/* #define HAL_DAC_MODULE_ENABLED   */
-/* #define HAL_DCMI_MODULE_ENABLED  */
-/* #define HAL_DMA_MODULE_ENABLED */
-/* #define HAL_ETH_MODULE_ENABLED */
-#define HAL_EXTI_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED 
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_PCCARD_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_HASH_MODULE_ENABLED   */
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED    */
-/* #define HAL_IWDG_MODULE_ENABLED  */
-#define HAL_PWR_MODULE_ENABLED   
-#define HAL_RCC_MODULE_ENABLED 
-/* #define HAL_RNG_MODULE_ENABLED    */
-/* #define HAL_RTC_MODULE_ENABLED */
-/* #define HAL_SD_MODULE_ENABLED   */
-/* #define HAL_SPI_MODULE_ENABLED    */
-/* #define HAL_TIM_MODULE_ENABLED    */
-/* #define HAL_UART_MODULE_ENABLED  */
-/* #define HAL_USART_MODULE_ENABLED  */
-/* #define HAL_IRDA_MODULE_ENABLED  */
-/* #define HAL_SMARTCARD_MODULE_ENABLED  */
-/* #define HAL_WWDG_MODULE_ENABLED   */
-#define HAL_CORTEX_MODULE_ENABLED
-#define HAL_PCD_MODULE_ENABLED 
-/* #define HAL_HCD_MODULE_ENABLED */
-
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE                     8000000U       /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT               100U       /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE                    16000000U       /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE                        32000U       /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                                 /*!< Value of the Internal Low Speed oscillator in Hz
-                                                            The real value may vary depending on the variations
-                                                            in voltage and temperature.*/
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE                        32768U       /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT              5000U       /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE       12288000U        /*!< Value of the Internal oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                      3300U /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY              0x0FU /*!< tick interrupt priority */
-#define  USE_RTOS                          0U
-#define  PREFETCH_ENABLE                   1U
-#define  INSTRUCTION_CACHE_ENABLE          1U
-#define  DATA_CACHE_ENABLE                 1U
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1U */
-
-/* ################## Ethernet peripheral configuration for NUCLEO 144 board ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0                         2U
-#define MAC_ADDR1                         0U
-#define MAC_ADDR2                         0U
-#define MAC_ADDR3                         0U
-#define MAC_ADDR4                         0U
-#define MAC_ADDR5                         0U
-
-/* Definition of the Ethernet driver buffers size and count */   
-#define ETH_RX_BUF_SIZE                   ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                   ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                       5U       /* 5 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                       5U       /* 5 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* LAN8742A PHY Address*/
-#define LAN8742A_PHY_ADDRESS            0x00U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
-#define PHY_RESET_DELAY                 0x000000FFU
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                0x00000FFFU
-
-#define PHY_READ_TO                     0x0000FFFFU
-#define PHY_WRITE_TO                    0x0000FFFFU
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
- 
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x1F)    /*!< PHY special control/ status register Offset     */
-
-#define PHY_SPEED_STATUS                ((uint16_t)0x0004)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0010)  /*!< PHY Duplex mask                                 */
-
-
-#define PHY_ISFR                        ((uint16_t)0x1D)    /*!< PHY Interrupt Source Flag register Offset       */
-#define PHY_ISFR_INT4                   ((uint16_t)0x0010)  /*!< PHY Link down inturrupt                         */
- 
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f2xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f2xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32f2xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f2xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-   
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f2xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f2xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f2xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f2xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f2xx_hal_cryp.h" 
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f2xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f2xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f2xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f2xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
- 
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f2xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f2xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f2xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f2xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f2xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f2xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f2xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f2xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f2xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f2xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f2xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f2xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f2xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f2xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f2xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f2xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f2xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f2xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f2xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f2xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f2xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-   
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_HAL_CONF_H */
- 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tinyusb/hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld b/tinyusb/hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld
deleted file mode 100755
index ca9046d2..00000000
--- a/tinyusb/hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
-*****************************************************************************
-**
-
-**  File        : LinkerScript.ld
-**
-**  Abstract    : Linker script for STM32F303VCTx Device with
-**                256KByte FLASH, 40KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-**  (c)Copyright Ac6.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Ac6 permit registered System Workbench for MCU users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the System Workbench for MCU toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x2000a000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x800;;      /* required amount of heap  */
-_Min_Stack_Size = 0x800;; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 256K
-RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 40K
-CCMRAM (rw)      : ORIGIN = 0x10000000, LENGTH = 8K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  _siccmram = LOADADDR(.ccmram);
-
-  /* CCM-RAM section 
-  * 
-  * IMPORTANT NOTE! 
-  * If initialized variables will be placed in this section,
-  * the startup code needs to be modified to copy the init-values.  
-  */
-  .ccmram :
-  {
-    . = ALIGN(4);
-    _sccmram = .;       /* create a global symbol at ccmram start */
-    *(.ccmram)
-    *(.ccmram*)
-    
-    . = ALIGN(4);
-    _eccmram = .;       /* create a global symbol at ccmram end */
-  } >CCMRAM AT> FLASH
-
-  
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-  
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
-
-
diff --git a/tinyusb/hw/bsp/stm32f303disco/board.mk b/tinyusb/hw/bsp/stm32f303disco/board.mk
deleted file mode 100755
index 9dd27a85..00000000
--- a/tinyusb/hw/bsp/stm32f303disco/board.mk
+++ /dev/null
@@ -1,49 +0,0 @@
-ST_FAMILY = f3
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
-ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib -nostartfiles \
-  -DSTM32F303xC \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32F3
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/STM32F303VCTx_FLASH.ld
-
-SRC_C += \
-  src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
-  $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
-
-SRC_S += \
-  $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f303xc.s
-
-INC += \
-  $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-  $(TOP)/$(ST_CMSIS)/Include \
-  $(TOP)/$(ST_HAL_DRIVER)/Inc \
-  $(TOP)/hw/bsp/$(BOARD)
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = stm32f303vc
-
-# flash target using on-board stlink
-flash: flash-stlink
diff --git a/tinyusb/hw/bsp/stm32f303disco/stm32f303disco.c b/tinyusb/hw/bsp/stm32f303disco/stm32f303disco.c
deleted file mode 100755
index 33552bc0..00000000
--- a/tinyusb/hw/bsp/stm32f303disco/stm32f303disco.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "../board.h"
-#include "stm32f3xx_hal.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-
-// USB defaults to using interrupts 19, 20 and 42, however, this BSP sets the
-// SYSCFG_CFGR1.USB_IT_RMP bit remapping interrupts to 74, 75 and 76.
-
-// FIXME: Do all three need to be handled, or just the LP one?
-// USB high-priority interrupt (Channel 74): Triggered only by a correct
-// transfer event for isochronous and double-buffer bulk transfer to reach
-// the highest possible transfer rate.
-void USB_HP_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-// USB low-priority interrupt (Channel 75): Triggered by all USB events
-// (Correct transfer, USB reset, etc.). The firmware has to check the
-// interrupt source before serving the interrupt.
-void USB_LP_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-// USB wakeup interrupt (Channel 76): Triggered by the wakeup event from the USB
-// Suspend mode.
-void USBWakeUp_RMP_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-#define LED_PORT              GPIOE
-#define LED_PIN               GPIO_PIN_9
-#define LED_STATE_ON          1
-
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE   1
-
-
-/**
-  * @brief  System Clock Configuration
-  *         The system Clock is configured as follow :
-  *            System Clock source            = PLL (HSE)
-  *            SYSCLK(Hz)                     = 72000000
-  *            HCLK(Hz)                       = 72000000
-  *            AHB Prescaler                  = 1
-  *            APB1 Prescaler                 = 2
-  *            APB2 Prescaler                 = 1
-  *            HSE Frequency(Hz)              = 8000000
-  *            HSE PREDIV                     = 1
-  *            PLLMUL                         = RCC_PLL_MUL9 (9)
-  *            Flash Latency(WS)              = 2
-  * @param  None
-  * @retval None
-  */
-static void SystemClock_Config(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-  RCC_PeriphCLKInitTypeDef  RCC_PeriphClkInit;
-
-  /* Enable HSE Oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Configures the USB clock */
-  HAL_RCCEx_GetPeriphCLKConfig(&RCC_PeriphClkInit);
-  RCC_PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
-  HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit);
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
-  clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
-
-  /* Enable Power Clock */
-  __HAL_RCC_PWR_CLK_ENABLE();
-}
-
-void board_init(void)
-{
-  SystemClock_Config();
-
-  #if CFG_TUSB_OS  == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-  #endif
-
-  // Remap the USB interrupts
-  __HAL_RCC_SYSCFG_CLK_ENABLE();
-  __HAL_REMAPINTERRUPT_USB_ENABLE();
-
-  // LED
-  __HAL_RCC_GPIOE_CLK_ENABLE();
-  GPIO_InitTypeDef  GPIO_InitStruct;
-  GPIO_InitStruct.Pin = LED_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
-
-  // Button
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  GPIO_InitStruct.Pin = BUTTON_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
-
-  /* Configure USB DM and DP pins */
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF14_USB;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  // Enable USB clock
-  __HAL_RCC_USB_CLK_ENABLE();
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-
-void HardFault_Handler (void)
-{
-  asm("bkpt");
-}
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
-}
diff --git a/tinyusb/hw/bsp/stm32f303disco/stm32f3xx_hal_conf.h b/tinyusb/hw/bsp/stm32f303disco/stm32f3xx_hal_conf.h
deleted file mode 100755
index 0abcbb01..00000000
--- a/tinyusb/hw/bsp/stm32f303disco/stm32f3xx_hal_conf.h
+++ /dev/null
@@ -1,357 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f3xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_CONF_H
-#define __STM32F3xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-#define HAL_MODULE_ENABLED  
-/* #define HAL_ADC_MODULE_ENABLED */
-/* #define HAL_CAN_MODULE_ENABLED */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
-/* #define HAL_CEC_MODULE_ENABLED */
-/* #define HAL_COMP_MODULE_ENABLED */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_CRC_MODULE_ENABLED */
-/* #define HAL_DAC_MODULE_ENABLED */
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_PCCARD_MODULE_ENABLED */
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_EXTI_MODULE_ENABLED */
-/* #define HAL_HRTIM_MODULE_ENABLED */
-/* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED */
-/* #define HAL_IRDA_MODULE_ENABLED */
-/* #define HAL_IWDG_MODULE_ENABLED */
-/* #define HAL_OPAMP_MODULE_ENABLED */
-/* #define HAL_PCD_MODULE_ENABLED */
-/* #define HAL_PWR_MODULE_ENABLED */
-#define HAL_RCC_MODULE_ENABLED 
-/* #define HAL_RTC_MODULE_ENABLED */
-/* #define HAL_SDADC_MODULE_ENABLED */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_SMBUS_MODULE_ENABLED */
-/* #define HAL_SPI_MODULE_ENABLED */
-/* #define HAL_TIM_MODULE_ENABLED */
-/* #define HAL_TSC_MODULE_ENABLED */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED */
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-/**
-  * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
-  *        Timeout value 
-  */
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    (8000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup 
-  *        Timeout value 
-  */
-#if !defined  (HSI_STARTUP_TIMEOUT) 
- #define HSI_STARTUP_TIMEOUT   (5000U) /*!< Time out for HSI start up */
-#endif /* HSI_STARTUP_TIMEOUT */  
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  (40000U)    
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  (32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-/**
-  * @brief Time out for LSE start up value in ms.
-  */
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */     
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  *        - External clock generated through external PLL component on EVAL 303 (based on MCO or crystal)
-  *        - External clock not generated on EVAL 373
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    (8000000U) /*!< Value of the External oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U)   /*!< tick interrupt priority (lowest by default) */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  INSTRUCTION_CACHE_ENABLE     0U
-#define  DATA_CACHE_ENABLE            0U
-#define  USE_SPI_CRC                  1U
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_COMP_REGISTER_CALLBACKS        0U /* COMP register callback disabled      */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SDADC_REGISTER_CALLBACKS       0U /* SDADC register callback disabled     */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
-#define  USE_HAL_HRTIM_REGISTER_CALLBACKS       0U /* HRTIM register callback disabled     */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-#define  USE_HAL_OPAMP_REGISTER_CALLBACKS       0U /* OPAMP register callback disabled     */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_TSC_REGISTER_CALLBACKS         0U /* TSC register callback disabled       */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/*#define USE_FULL_ASSERT    1U*/
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
- #include "stm32f3xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
- #include "stm32f3xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32f3xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f3xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
- #include "stm32f3xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
- #include "stm32f3xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
- #include "stm32f3xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
- #include "stm32f3xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32f3xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_COMP_MODULE_ENABLED
- #include "stm32f3xx_hal_comp.h"
-#endif /* HAL_COMP_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
- #include "stm32f3xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
- #include "stm32f3xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
- #include "stm32f3xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f3xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f3xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f3xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f3xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
-#ifdef HAL_HRTIM_MODULE_ENABLED
- #include "stm32f3xx_hal_hrtim.h"
-#endif /* HAL_HRTIM_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f3xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f3xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f3xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f3xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_OPAMP_MODULE_ENABLED
- #include "stm32f3xx_hal_opamp.h"
-#endif /* HAL_OPAMP_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f3xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f3xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f3xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SDADC_MODULE_ENABLED
- #include "stm32f3xx_hal_sdadc.h"
-#endif /* HAL_SDADC_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f3xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32f3xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f3xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f3xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_TSC_MODULE_ENABLED
- #include "stm32f3xx_hal_tsc.h"
-#endif /* HAL_TSC_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f3xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f3xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f3xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tinyusb/hw/bsp/stm32f4/boards/feather_stm32f405/STM32F405RGTx_FLASH.ld b/tinyusb/hw/bsp/stm32f4/boards/feather_stm32f405/STM32F405RGTx_FLASH.ld
deleted file mode 100755
index 57ef61e2..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/feather_stm32f405/STM32F405RGTx_FLASH.ld
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
-*****************************************************************************
-**
-
-**  File        : LinkerScript.ld
-**
-**  Abstract    : Linker script for STM32F405RGTx Device with
-**                1024KByte FLASH, 128KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-**  (c)Copyright Ac6.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Ac6 permit registered System Workbench for MCU users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the System Workbench for MCU toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20020000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K
-CCMRAM (rw)      : ORIGIN = 0x10000000, LENGTH = 64K
-FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 1024K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  _siccmram = LOADADDR(.ccmram);
-
-  /* CCM-RAM section 
-  * 
-  * IMPORTANT NOTE! 
-  * If initialized variables will be placed in this section,
-  * the startup code needs to be modified to copy the init-values.  
-  */
-  .ccmram :
-  {
-    . = ALIGN(4);
-    _sccmram = .;       /* create a global symbol at ccmram start */
-    *(.ccmram)
-    *(.ccmram*)
-    
-    . = ALIGN(4);
-    _eccmram = .;       /* create a global symbol at ccmram end */
-  } >CCMRAM AT> FLASH
-
-  
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-  
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
-
-
diff --git a/tinyusb/hw/bsp/stm32f4/boards/feather_stm32f405/board.h b/tinyusb/hw/bsp/stm32f4/boards/feather_stm32f405/board.h
deleted file mode 100755
index 19d0a1ea..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/feather_stm32f405/board.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PORT              GPIOC
-#define LED_PIN               GPIO_PIN_1
-#define LED_STATE_ON          1
-
-// Button: Pin D5
-#define BUTTON_PORT           GPIOC
-#define BUTTON_PIN            GPIO_PIN_7
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_DEV              USART3
-#define UART_GPIO_PORT        GPIOB
-#define UART_GPIO_AF          GPIO_AF7_USART3
-#define UART_TX_PIN           GPIO_PIN_10
-#define UART_RX_PIN           GPIO_PIN_11
-
-//--------------------------------------------------------------------+
-// RCC Clock
-//--------------------------------------------------------------------+
-static inline void board_clock_init(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable Power Control clock */
-  __HAL_RCC_PWR_CLK_ENABLE();
-
-  /* The voltage scaling allows optimizing the power consumption when the device is
-     clocked below the maximum system frequency, to update the voltage scaling value
-     regarding system frequency refer to product datasheet.  */
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-  /* Enable HSE Oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
-  RCC_OscInitStruct.PLL.PLLN = 336;
-  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
-  RCC_OscInitStruct.PLL.PLLQ = 7;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
-     clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
-
-  // Enable clocks for LED, Button, Uart
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  __HAL_RCC_GPIOC_CLK_ENABLE();
-  __HAL_RCC_USART3_CLK_ENABLE();
-}
-
-static inline void board_vbus_sense_init(void)
-{
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/stm32f4/boards/feather_stm32f405/board.mk b/tinyusb/hw/bsp/stm32f4/boards/feather_stm32f405/board.mk
deleted file mode 100755
index 1de56fe5..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/feather_stm32f405/board.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-CFLAGS += -DSTM32F405xx
-
-LD_FILE = $(BOARD_PATH)/STM32F405RGTx_FLASH.ld
-
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f405xx.s
-
-# For flash-jlink target
-JLINK_DEVICE = stm32f405rg
-
-# flash target ROM bootloader
-flash: $(BUILD)/$(PROJECT).bin
-	dfu-util -R -a 0 --dfuse-address 0x08000000 -D $<
diff --git a/tinyusb/hw/bsp/stm32f4/boards/feather_stm32f405/stm32f4xx_hal_conf.h b/tinyusb/hw/bsp/stm32f4/boards/feather_stm32f405/stm32f4xx_hal_conf.h
deleted file mode 100755
index b892df3b..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/feather_stm32f405/stm32f4xx_hal_conf.h
+++ /dev/null
@@ -1,491 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_conf.h
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CONF_H
-#define __STM32F4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-
-/* #define HAL_ADC_MODULE_ENABLED   */
-/* #define HAL_CRYP_MODULE_ENABLED   */
-/* #define HAL_CAN_MODULE_ENABLED   */
-/* #define HAL_CRC_MODULE_ENABLED   */
-/* #define HAL_CRYP_MODULE_ENABLED   */
-/* #define HAL_DAC_MODULE_ENABLED   */
-/* #define HAL_DCMI_MODULE_ENABLED   */
-/* #define HAL_DMA2D_MODULE_ENABLED   */
-/* #define HAL_ETH_MODULE_ENABLED   */
-/* #define HAL_NAND_MODULE_ENABLED   */
-/* #define HAL_NOR_MODULE_ENABLED   */
-/* #define HAL_PCCARD_MODULE_ENABLED   */
-/* #define HAL_SRAM_MODULE_ENABLED   */
-/* #define HAL_SDRAM_MODULE_ENABLED   */
-/* #define HAL_HASH_MODULE_ENABLED   */
-/* #define HAL_I2C_MODULE_ENABLED   */
-/* #define HAL_I2S_MODULE_ENABLED   */
-/* #define HAL_IWDG_MODULE_ENABLED   */
-/* #define HAL_LTDC_MODULE_ENABLED   */
-/* #define HAL_RNG_MODULE_ENABLED   */
-/* #define HAL_RTC_MODULE_ENABLED   */
-/* #define HAL_SAI_MODULE_ENABLED   */
-/* #define HAL_SD_MODULE_ENABLED   */
-/* #define HAL_MMC_MODULE_ENABLED   */
-/* #define HAL_SPI_MODULE_ENABLED   */
-/* #define HAL_TIM_MODULE_ENABLED   */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED   */
-/* #define HAL_IRDA_MODULE_ENABLED   */
-/* #define HAL_SMARTCARD_MODULE_ENABLED   */
-/* #define HAL_WWDG_MODULE_ENABLED   */
-#define HAL_PCD_MODULE_ENABLED
-/* #define HAL_HCD_MODULE_ENABLED   */
-/* #define HAL_DSI_MODULE_ENABLED   */
-/* #define HAL_QSPI_MODULE_ENABLED   */
-/* #define HAL_QSPI_MODULE_ENABLED   */
-/* #define HAL_CEC_MODULE_ENABLED   */
-/* #define HAL_FMPI2C_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED   */
-/* #define HAL_DFSDM_MODULE_ENABLED   */
-/* #define HAL_LPTIM_MODULE_ENABLED   */
-/* #define HAL_EXTI_MODULE_ENABLED   */
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_CORTEX_MODULE_ENABLED
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)12000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE)
- #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.*/
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE		      ((uint32_t)3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0U)   /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  INSTRUCTION_CACHE_ENABLE     1U
-#define  DATA_CACHE_ENABLE            1U
-
-/* Copied over manually- STM32Cube didn't generate these for some reason. */
-#define  USE_HAL_ADC_REGISTER_CALLBACKS     0U /* ADC register callback disabled     */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS     0U /* CEC register callback disabled     */
-#define  USE_HAL_COMP_REGISTER_CALLBACKS    0U /* COMP register callback disabled    */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS    0U /* CRYP register callback disabled    */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS     0U /* DAC register callback disabled     */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS    0U /* DCMI register callback disabled    */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS   0U /* DFSDM register callback disabled   */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS   0U /* DMA2D register callback disabled   */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS     0U /* DSI register callback disabled     */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS     0U /* ETH register callback disabled     */
-#define  USE_HAL_FDCAN_REGISTER_CALLBACKS   0U /* FDCAN register callback disabled   */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS    0U /* NAND register callback disabled    */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS     0U /* NOR register callback disabled     */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS   0U /* SDRAM register callback disabled   */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS    0U /* SRAM register callback disabled    */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS    0U /* HASH register callback disabled    */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS     0U /* HCD register callback disabled     */
-#define  USE_HAL_HRTIM_REGISTER_CALLBACKS   0U /* HRTIM register callback disabled   */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS     0U /* I2C register callback disabled     */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS     0U /* I2S register callback disabled     */
-#define  USE_HAL_JPEG_REGISTER_CALLBACKS    0U /* JPEG register callback disabled    */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS   0U /* LPTIM register callback disabled   */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS    0U /* LTDC register callback disabled    */
-#define  USE_HAL_MDIOS_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
-#define  USE_HAL_OPAMP_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS     0U /* PCD register callback disabled     */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS    0U /* QSPI register callback disabled    */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS     0U /* RNG register callback disabled     */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS     0U /* RTC register callback disabled     */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS     0U /* SAI register callback disabled     */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS   0U /* SMBUS register callback disabled   */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS     0U /* SPI register callback disabled     */
-#define  USE_HAL_SWPMI_REGISTER_CALLBACKS   0U /* SWPMI register callback disabled   */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS     0U /* TIM register callback disabled     */
-#define  USE_HAL_UART_REGISTER_CALLBACKS    0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS   0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS    0U /* WWDG register callback disabled    */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1U */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)4U)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)4U)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848_PHY_ADDRESS Address*/
-#define DP83848_PHY_ADDRESS           0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY                 ((uint32_t)0x000000FFU)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFFU)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFFU)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFFU)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x0000U)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x0001U)    /*!< Transceiver Basic Status Register    */
-
-#define PHY_RESET                       ((uint16_t)0x8000U)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000U)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100U)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000U)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100U)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000U)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000U)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200U)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800U)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400U)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020U)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004U)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002U)  /*!< Jabber condition detected            */
-
-/* Section 4: Extended PHY Registers */
-#define PHY_SR                          ((uint16_t)0x10U)    /*!< PHY status register Offset                      */
-
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002U)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004U)  /*!< PHY Duplex mask                                 */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     0U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32f4xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f4xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f4xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f4xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f4xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f4xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32f4xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f4xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f4xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32f4xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_FMPI2C_MODULE_ENABLED
- #include "stm32f4xx_hal_fmpi2c.h"
-#endif /* HAL_FMPI2C_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f4xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f4xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f4xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tinyusb/hw/bsp/stm32f4/boards/pyboardv11/STM32F405RGTx_FLASH.ld b/tinyusb/hw/bsp/stm32f4/boards/pyboardv11/STM32F405RGTx_FLASH.ld
deleted file mode 100755
index 57ef61e2..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/pyboardv11/STM32F405RGTx_FLASH.ld
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
-*****************************************************************************
-**
-
-**  File        : LinkerScript.ld
-**
-**  Abstract    : Linker script for STM32F405RGTx Device with
-**                1024KByte FLASH, 128KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-**  (c)Copyright Ac6.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Ac6 permit registered System Workbench for MCU users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the System Workbench for MCU toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20020000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K
-CCMRAM (rw)      : ORIGIN = 0x10000000, LENGTH = 64K
-FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 1024K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  _siccmram = LOADADDR(.ccmram);
-
-  /* CCM-RAM section 
-  * 
-  * IMPORTANT NOTE! 
-  * If initialized variables will be placed in this section,
-  * the startup code needs to be modified to copy the init-values.  
-  */
-  .ccmram :
-  {
-    . = ALIGN(4);
-    _sccmram = .;       /* create a global symbol at ccmram start */
-    *(.ccmram)
-    *(.ccmram*)
-    
-    . = ALIGN(4);
-    _eccmram = .;       /* create a global symbol at ccmram end */
-  } >CCMRAM AT> FLASH
-
-  
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-  
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
-
-
diff --git a/tinyusb/hw/bsp/stm32f4/boards/pyboardv11/board.h b/tinyusb/hw/bsp/stm32f4/boards/pyboardv11/board.h
deleted file mode 100755
index 685919c5..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/pyboardv11/board.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// Blue LED is chosen because the other LEDs are connected to ST-LINK lines.
-#define LED_PORT              GPIOB
-#define LED_PIN               GPIO_PIN_4
-#define LED_STATE_ON          1
-
-#define BUTTON_PORT           GPIOB
-#define BUTTON_PIN            GPIO_PIN_3
-#define BUTTON_STATE_ACTIVE   1
-
-// Enable PA2 as the debug log UART
-// It is not routed to the ST/Link on the Discovery board.
-//#define UART_DEV              USART2
-//#define UART_GPIO_PORT        GPIOA
-//#define UART_GPIO_AF          GPIO_AF7_USART2
-//#define UART_TX_PIN           GPIO_PIN_2
-//#define UART_RX_PIN           GPIO_PIN_3
-
-//--------------------------------------------------------------------+
-// RCC Clock
-//--------------------------------------------------------------------+
-static inline void board_clock_init(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable Power Control clock */
-  __HAL_RCC_PWR_CLK_ENABLE();
-
-  /* The voltage scaling allows optimizing the power consumption when the device is
-     clocked below the maximum system frequency, to update the voltage scaling value
-     regarding system frequency refer to product datasheet.  */
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-  /* Enable HSE Oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
-  RCC_OscInitStruct.PLL.PLLN = 336;
-  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
-  RCC_OscInitStruct.PLL.PLLQ = 7;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
-     clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
-
-  // Enable clocks for LED, Button, Uart
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-}
-
-static inline void board_vbus_sense_init(void)
-{
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/stm32f4/boards/pyboardv11/board.mk b/tinyusb/hw/bsp/stm32f4/boards/pyboardv11/board.mk
deleted file mode 100755
index 02dcd121..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/pyboardv11/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-CFLAGS += -DSTM32F405xx
-
-LD_FILE = $(BOARD_PATH)/STM32F405RGTx_FLASH.ld
-
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f405xx.s
-
-# For flash-jlink target
-JLINK_DEVICE = stm32f405rg
-
-# flash target using on-board stlink
-flash: flash-stlink
diff --git a/tinyusb/hw/bsp/stm32f4/boards/pyboardv11/stm32f4xx_hal_conf.h b/tinyusb/hw/bsp/stm32f4/boards/pyboardv11/stm32f4xx_hal_conf.h
deleted file mode 100755
index b892df3b..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/pyboardv11/stm32f4xx_hal_conf.h
+++ /dev/null
@@ -1,491 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_conf.h
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CONF_H
-#define __STM32F4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-
-/* #define HAL_ADC_MODULE_ENABLED   */
-/* #define HAL_CRYP_MODULE_ENABLED   */
-/* #define HAL_CAN_MODULE_ENABLED   */
-/* #define HAL_CRC_MODULE_ENABLED   */
-/* #define HAL_CRYP_MODULE_ENABLED   */
-/* #define HAL_DAC_MODULE_ENABLED   */
-/* #define HAL_DCMI_MODULE_ENABLED   */
-/* #define HAL_DMA2D_MODULE_ENABLED   */
-/* #define HAL_ETH_MODULE_ENABLED   */
-/* #define HAL_NAND_MODULE_ENABLED   */
-/* #define HAL_NOR_MODULE_ENABLED   */
-/* #define HAL_PCCARD_MODULE_ENABLED   */
-/* #define HAL_SRAM_MODULE_ENABLED   */
-/* #define HAL_SDRAM_MODULE_ENABLED   */
-/* #define HAL_HASH_MODULE_ENABLED   */
-/* #define HAL_I2C_MODULE_ENABLED   */
-/* #define HAL_I2S_MODULE_ENABLED   */
-/* #define HAL_IWDG_MODULE_ENABLED   */
-/* #define HAL_LTDC_MODULE_ENABLED   */
-/* #define HAL_RNG_MODULE_ENABLED   */
-/* #define HAL_RTC_MODULE_ENABLED   */
-/* #define HAL_SAI_MODULE_ENABLED   */
-/* #define HAL_SD_MODULE_ENABLED   */
-/* #define HAL_MMC_MODULE_ENABLED   */
-/* #define HAL_SPI_MODULE_ENABLED   */
-/* #define HAL_TIM_MODULE_ENABLED   */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED   */
-/* #define HAL_IRDA_MODULE_ENABLED   */
-/* #define HAL_SMARTCARD_MODULE_ENABLED   */
-/* #define HAL_WWDG_MODULE_ENABLED   */
-#define HAL_PCD_MODULE_ENABLED
-/* #define HAL_HCD_MODULE_ENABLED   */
-/* #define HAL_DSI_MODULE_ENABLED   */
-/* #define HAL_QSPI_MODULE_ENABLED   */
-/* #define HAL_QSPI_MODULE_ENABLED   */
-/* #define HAL_CEC_MODULE_ENABLED   */
-/* #define HAL_FMPI2C_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED   */
-/* #define HAL_DFSDM_MODULE_ENABLED   */
-/* #define HAL_LPTIM_MODULE_ENABLED   */
-/* #define HAL_EXTI_MODULE_ENABLED   */
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_CORTEX_MODULE_ENABLED
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)12000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE)
- #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.*/
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE		      ((uint32_t)3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0U)   /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  INSTRUCTION_CACHE_ENABLE     1U
-#define  DATA_CACHE_ENABLE            1U
-
-/* Copied over manually- STM32Cube didn't generate these for some reason. */
-#define  USE_HAL_ADC_REGISTER_CALLBACKS     0U /* ADC register callback disabled     */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS     0U /* CEC register callback disabled     */
-#define  USE_HAL_COMP_REGISTER_CALLBACKS    0U /* COMP register callback disabled    */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS    0U /* CRYP register callback disabled    */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS     0U /* DAC register callback disabled     */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS    0U /* DCMI register callback disabled    */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS   0U /* DFSDM register callback disabled   */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS   0U /* DMA2D register callback disabled   */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS     0U /* DSI register callback disabled     */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS     0U /* ETH register callback disabled     */
-#define  USE_HAL_FDCAN_REGISTER_CALLBACKS   0U /* FDCAN register callback disabled   */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS    0U /* NAND register callback disabled    */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS     0U /* NOR register callback disabled     */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS   0U /* SDRAM register callback disabled   */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS    0U /* SRAM register callback disabled    */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS    0U /* HASH register callback disabled    */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS     0U /* HCD register callback disabled     */
-#define  USE_HAL_HRTIM_REGISTER_CALLBACKS   0U /* HRTIM register callback disabled   */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS     0U /* I2C register callback disabled     */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS     0U /* I2S register callback disabled     */
-#define  USE_HAL_JPEG_REGISTER_CALLBACKS    0U /* JPEG register callback disabled    */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS   0U /* LPTIM register callback disabled   */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS    0U /* LTDC register callback disabled    */
-#define  USE_HAL_MDIOS_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
-#define  USE_HAL_OPAMP_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS     0U /* PCD register callback disabled     */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS    0U /* QSPI register callback disabled    */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS     0U /* RNG register callback disabled     */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS     0U /* RTC register callback disabled     */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS     0U /* SAI register callback disabled     */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS   0U /* SMBUS register callback disabled   */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS     0U /* SPI register callback disabled     */
-#define  USE_HAL_SWPMI_REGISTER_CALLBACKS   0U /* SWPMI register callback disabled   */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS     0U /* TIM register callback disabled     */
-#define  USE_HAL_UART_REGISTER_CALLBACKS    0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS   0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS    0U /* WWDG register callback disabled    */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1U */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)4U)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)4U)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848_PHY_ADDRESS Address*/
-#define DP83848_PHY_ADDRESS           0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY                 ((uint32_t)0x000000FFU)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFFU)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFFU)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFFU)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x0000U)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x0001U)    /*!< Transceiver Basic Status Register    */
-
-#define PHY_RESET                       ((uint16_t)0x8000U)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000U)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100U)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000U)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100U)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000U)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000U)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200U)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800U)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400U)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020U)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004U)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002U)  /*!< Jabber condition detected            */
-
-/* Section 4: Extended PHY Registers */
-#define PHY_SR                          ((uint16_t)0x10U)    /*!< PHY status register Offset                      */
-
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002U)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004U)  /*!< PHY Duplex mask                                 */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     0U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32f4xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f4xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f4xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f4xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f4xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f4xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32f4xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f4xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f4xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32f4xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_FMPI2C_MODULE_ENABLED
- #include "stm32f4xx_hal_fmpi2c.h"
-#endif /* HAL_FMPI2C_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f4xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f4xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f4xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tinyusb/hw/bsp/stm32f4/boards/stm32f401blackpill/STM32F401VCTx_FLASH.ld b/tinyusb/hw/bsp/stm32f4/boards/stm32f401blackpill/STM32F401VCTx_FLASH.ld
deleted file mode 100755
index f51f1ab4..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/stm32f401blackpill/STM32F401VCTx_FLASH.ld
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
-*****************************************************************************
-**
-
-**  File        : LinkerScript.ld
-**
-**  Abstract    : Linker script for STM32F401VCTx Device with
-**                256KByte FLASH, 64KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-**  (c)Copyright Ac6.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Ac6 permit registered System Workbench for MCU users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the System Workbench for MCU toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20010000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;;      /* required amount of heap  */
-_Min_Stack_Size = 0x400;; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 256K
-RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 64K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-  
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
-
-
diff --git a/tinyusb/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h b/tinyusb/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h
deleted file mode 100755
index 0f820512..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PORT              GPIOC
-#define LED_PIN               GPIO_PIN_13
-#define LED_STATE_ON          0
-
-// Button
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE   0
-
-// Enable PA2 as the debug log UART
-//#define UART_DEV              USART2
-//#define UART_GPIO_PORT        GPIOA
-//#define UART_GPIO_AF          GPIO_AF7_USART2
-//#define UART_TX_PIN           GPIO_PIN_2
-//#define UART_RX_PIN           GPIO_PIN_3
-
-
-//--------------------------------------------------------------------+
-// RCC Clock
-//--------------------------------------------------------------------+
-static inline void board_clock_init(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable Power Control clock */
-  __HAL_RCC_PWR_CLK_ENABLE();
-
-  /* The voltage scaling allows optimizing the power consumption when the device is
-     clocked below the maximum system frequency, to update the voltage scaling value
-     regarding system frequency refer to product datasheet.  */
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
-
-  /* Enable HSE Oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
-  RCC_OscInitStruct.PLL.PLLN = 336;
-  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
-  RCC_OscInitStruct.PLL.PLLQ = 7;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
-     clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
-
-  // Enable clocks for LED, Button, Uart
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOC_CLK_ENABLE();
-  //__HAL_RCC_USART2_CLK_ENABLE();
-}
-
-static inline void board_vbus_sense_init(void)
-{
-  // Blackpill doens't use VBUS sense (B device) explicitly disable it
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/stm32f4/boards/stm32f401blackpill/board.mk b/tinyusb/hw/bsp/stm32f4/boards/stm32f401blackpill/board.mk
deleted file mode 100755
index de0f3d4c..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/stm32f401blackpill/board.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-CFLAGS += -DSTM32F401xC
-
-LD_FILE = $(BOARD_PATH)/STM32F401VCTx_FLASH.ld
-
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f401xc.s
-
-# For flash-jlink target
-JLINK_DEVICE = stm32f401cc
-
-# flash target ROM bootloader
-flash: $(BUILD)/$(PROJECT).bin
-	dfu-util -R -a 0 --dfuse-address 0x08000000 -D $<
diff --git a/tinyusb/hw/bsp/stm32f4/boards/stm32f401blackpill/stm32f4xx_hal_conf.h b/tinyusb/hw/bsp/stm32f4/boards/stm32f401blackpill/stm32f4xx_hal_conf.h
deleted file mode 100755
index 2ab9a1d5..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/stm32f401blackpill/stm32f4xx_hal_conf.h
+++ /dev/null
@@ -1,493 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_conf_template.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CONF_H
-#define __STM32F4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-#define HAL_MODULE_ENABLED         
-/* #define HAL_ADC_MODULE_ENABLED      */
-/* #define HAL_CAN_MODULE_ENABLED      */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
-/* #define HAL_CRC_MODULE_ENABLED      */ 
-/* #define HAL_CEC_MODULE_ENABLED      */ 
-/* #define HAL_CRYP_MODULE_ENABLED     */ 
-/* #define HAL_DAC_MODULE_ENABLED      */ 
-/* #define HAL_DCMI_MODULE_ENABLED     */ 
-#define HAL_DMA_MODULE_ENABLED 
-/* #define HAL_DMA2D_MODULE_ENABLED    */ 
-/* #define HAL_ETH_MODULE_ENABLED      */
-#define HAL_FLASH_MODULE_ENABLED 
-/* #define HAL_NAND_MODULE_ENABLED     */
-/* #define HAL_NOR_MODULE_ENABLED      */
-/* #define HAL_PCCARD_MODULE_ENABLED   */
-/* #define HAL_SRAM_MODULE_ENABLED     */
-/* #define HAL_SDRAM_MODULE_ENABLED    */
-/* #define HAL_HASH_MODULE_ENABLED     */  
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_EXTI_MODULE_ENABLED     */
-/* #define HAL_I2C_MODULE_ENABLED      */
-/* #define HAL_SMBUS_MODULE_ENABLED    */
-/* #define HAL_I2S_MODULE_ENABLED      */
-/* #define HAL_IWDG_MODULE_ENABLED     */ 
-/* #define HAL_LTDC_MODULE_ENABLED     */
-/* #define HAL_DSI_MODULE_ENABLED      */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED     */
-#define HAL_RCC_MODULE_ENABLED      
-/* #define HAL_RNG_MODULE_ENABLED      */
-/* #define HAL_RTC_MODULE_ENABLED      */
-/* #define HAL_SAI_MODULE_ENABLED      */
-/* #define HAL_SD_MODULE_ENABLED       */
-// #define HAL_SPI_MODULE_ENABLED
-/* #define HAL_TIM_MODULE_ENABLED      */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED    */ 
-/* #define HAL_IRDA_MODULE_ENABLED     */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED     */
-#define HAL_CORTEX_MODULE_ENABLED   
-/* #define HAL_PCD_MODULE_ENABLED      */
-/* #define HAL_HCD_MODULE_ENABLED      */
-/* #define HAL_FMPI2C_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED  */
-/* #define HAL_DFSDM_MODULE_ENABLED    */
-/* #define HAL_LPTIM_MODULE_ENABLED    */
-/* #define HAL_MMC_MODULE_ENABLED      */
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    (25000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  (32000U)    
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  (32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */           
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  INSTRUCTION_CACHE_ENABLE     1U
-#define  DATA_CACHE_ENABLE            1U
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1U */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */   
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    4U                  /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848 PHY Address*/ 
-#define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
-#define PHY_RESET_DELAY                 0x000000FFU
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                0x00000FFFU
-
-#define PHY_READ_TO                     0x0000FFFFU
-#define PHY_WRITE_TO                    0x0000FFFFU
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
- 
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
-#define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
-#define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
- 
-#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
-
-#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
-#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
-
-#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
-#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32f4xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-   
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f4xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h" 
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f4xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f4xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
- 
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f4xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32f4xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f4xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f4xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-   
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f4xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f4xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32f4xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_FMPI2C_MODULE_ENABLED
- #include "stm32f4xx_hal_fmpi2c.h"
-#endif /* HAL_FMPI2C_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f4xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f4xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f4xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32f4xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tinyusb/hw/bsp/stm32f4/boards/stm32f407disco/STM32F407VGTx_FLASH.ld b/tinyusb/hw/bsp/stm32f4/boards/stm32f407disco/STM32F407VGTx_FLASH.ld
deleted file mode 100755
index c4160272..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/stm32f407disco/STM32F407VGTx_FLASH.ld
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
-*****************************************************************************
-**
-
-**  File        : LinkerScript.ld
-**
-**  Abstract    : Linker script for STM32F407VGTx Device with
-**                1024KByte FLASH, 128KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-**  (c)Copyright Ac6.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Ac6 permit registered System Workbench for MCU users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the System Workbench for MCU toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20020000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x1000;      /* required amount of heap  */
-_Min_Stack_Size = 0x4000; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-  RAM (xrw)    : ORIGIN = 0x20000000, LENGTH = 128K
-  CCMRAM (rw)  : ORIGIN = 0x10000000, LENGTH = 64K
-  FLASH (rx)   : ORIGIN = 0x8000000, LENGTH = 1024K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  _siccmram = LOADADDR(.ccmram);
-
-  /* CCM-RAM section 
-  * 
-  * IMPORTANT NOTE! 
-  * If initialized variables will be placed in this section,
-  * the startup code needs to be modified to copy the init-values.  
-  */
-  .ccmram :
-  {
-    . = ALIGN(4);
-    _sccmram = .;       /* create a global symbol at ccmram start */
-    *(.ccmram)
-    *(.ccmram*)
-    
-    . = ALIGN(4);
-    _eccmram = .;       /* create a global symbol at ccmram end */
-  } >CCMRAM AT> FLASH
-
-  
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-  
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
-
-
diff --git a/tinyusb/hw/bsp/stm32f4/boards/stm32f407disco/board.h b/tinyusb/hw/bsp/stm32f4/boards/stm32f407disco/board.h
deleted file mode 100755
index 693e0393..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/stm32f407disco/board.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PORT              GPIOD
-#define LED_PIN               GPIO_PIN_14
-#define LED_STATE_ON          1
-
-// Button
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE   1
-
-// Enable PA2 as the debug log UART
-// It is not routed to the ST/Link on the Discovery board.
-#define UART_DEV              USART2
-#define UART_GPIO_PORT        GPIOA
-#define UART_GPIO_AF          GPIO_AF7_USART2
-#define UART_TX_PIN           GPIO_PIN_2
-#define UART_RX_PIN           GPIO_PIN_3
-
-//--------------------------------------------------------------------+
-// RCC Clock
-//--------------------------------------------------------------------+
-static inline void board_clock_init(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable Power Control clock */
-  __HAL_RCC_PWR_CLK_ENABLE();
-
-  /* The voltage scaling allows optimizing the power consumption when the device is
-     clocked below the maximum system frequency, to update the voltage scaling value
-     regarding system frequency refer to product datasheet.  */
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-  /* Enable HSE Oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
-  RCC_OscInitStruct.PLL.PLLN = 336;
-  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
-  RCC_OscInitStruct.PLL.PLLQ = 7;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
-     clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
-
-  // Enable clocks for LED, Button, Uart
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOD_CLK_ENABLE();
-  __HAL_RCC_USART2_CLK_ENABLE();
-}
-
-static inline void board_vbus_sense_init(void)
-{
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/stm32f4/boards/stm32f407disco/board.mk b/tinyusb/hw/bsp/stm32f4/boards/stm32f407disco/board.mk
deleted file mode 100755
index 212b924b..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/stm32f407disco/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-CFLAGS += -DSTM32F407xx
-
-LD_FILE = $(BOARD_PATH)/STM32F407VGTx_FLASH.ld
-
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f407xx.s
-
-# For flash-jlink target
-JLINK_DEVICE = stm32f407vg
-
-# flash target using on-board stlink
-flash: flash-stlink
diff --git a/tinyusb/hw/bsp/stm32f4/boards/stm32f407disco/stm32f4xx_hal_conf.h b/tinyusb/hw/bsp/stm32f4/boards/stm32f407disco/stm32f4xx_hal_conf.h
deleted file mode 100755
index 7864f8d5..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/stm32f407disco/stm32f4xx_hal_conf.h
+++ /dev/null
@@ -1,493 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_conf_template.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CONF_H
-#define __STM32F4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-#define HAL_MODULE_ENABLED         
-/* #define HAL_ADC_MODULE_ENABLED      */
-/* #define HAL_CAN_MODULE_ENABLED      */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
-/* #define HAL_CRC_MODULE_ENABLED      */ 
-/* #define HAL_CEC_MODULE_ENABLED      */ 
-/* #define HAL_CRYP_MODULE_ENABLED     */ 
-/* #define HAL_DAC_MODULE_ENABLED      */ 
-/* #define HAL_DCMI_MODULE_ENABLED     */ 
-#define HAL_DMA_MODULE_ENABLED 
-/* #define HAL_DMA2D_MODULE_ENABLED    */ 
-/* #define HAL_ETH_MODULE_ENABLED      */
-#define HAL_FLASH_MODULE_ENABLED 
-/* #define HAL_NAND_MODULE_ENABLED     */
-/* #define HAL_NOR_MODULE_ENABLED      */
-/* #define HAL_PCCARD_MODULE_ENABLED   */
-/* #define HAL_SRAM_MODULE_ENABLED     */
-/* #define HAL_SDRAM_MODULE_ENABLED    */
-/* #define HAL_HASH_MODULE_ENABLED     */  
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_EXTI_MODULE_ENABLED     */
-/* #define HAL_I2C_MODULE_ENABLED      */
-/* #define HAL_SMBUS_MODULE_ENABLED    */
-/* #define HAL_I2S_MODULE_ENABLED      */
-/* #define HAL_IWDG_MODULE_ENABLED     */ 
-/* #define HAL_LTDC_MODULE_ENABLED     */
-/* #define HAL_DSI_MODULE_ENABLED      */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED     */
-#define HAL_RCC_MODULE_ENABLED      
-/* #define HAL_RNG_MODULE_ENABLED      */
-/* #define HAL_RTC_MODULE_ENABLED      */
-/* #define HAL_SAI_MODULE_ENABLED      */
-/* #define HAL_SD_MODULE_ENABLED       */
-// #define HAL_SPI_MODULE_ENABLED
-/* #define HAL_TIM_MODULE_ENABLED      */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED    */ 
-/* #define HAL_IRDA_MODULE_ENABLED     */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED     */
-#define HAL_CORTEX_MODULE_ENABLED   
-/* #define HAL_PCD_MODULE_ENABLED      */
-/* #define HAL_HCD_MODULE_ENABLED      */
-/* #define HAL_FMPI2C_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED  */
-/* #define HAL_DFSDM_MODULE_ENABLED    */
-/* #define HAL_LPTIM_MODULE_ENABLED    */
-/* #define HAL_MMC_MODULE_ENABLED      */
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  (32000U)    
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  (32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */           
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  INSTRUCTION_CACHE_ENABLE     1U
-#define  DATA_CACHE_ENABLE            1U
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1U */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */   
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    4U                  /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848 PHY Address*/ 
-#define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
-#define PHY_RESET_DELAY                 0x000000FFU
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                0x00000FFFU
-
-#define PHY_READ_TO                     0x0000FFFFU
-#define PHY_WRITE_TO                    0x0000FFFFU
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
- 
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
-#define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
-#define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
- 
-#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
-
-#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
-#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
-
-#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
-#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32f4xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-   
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f4xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h" 
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f4xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f4xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
- 
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f4xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32f4xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f4xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f4xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-   
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f4xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f4xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32f4xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_FMPI2C_MODULE_ENABLED
- #include "stm32f4xx_hal_fmpi2c.h"
-#endif /* HAL_FMPI2C_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f4xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f4xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f4xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32f4xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tinyusb/hw/bsp/stm32f4/boards/stm32f411blackpill/STM32F411CEUx_FLASH.ld b/tinyusb/hw/bsp/stm32f4/boards/stm32f411blackpill/STM32F411CEUx_FLASH.ld
deleted file mode 100755
index efea1e06..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/stm32f411blackpill/STM32F411CEUx_FLASH.ld
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
-*****************************************************************************
-**
-
-**  File        : LinkerScript.ld
-**
-**  Abstract    : Linker script for STM32F411CEUx Device with
-**                512KByte FLASH, 128KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-**  (c)Copyright Ac6.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Ac6 permit registered System Workbench for MCU users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the System Workbench for MCU toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20020000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;;      /* required amount of heap  */
-_Min_Stack_Size = 0x400;; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K
-RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(4);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(4);
-  } >RAM
-
-  
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
-
-
diff --git a/tinyusb/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h b/tinyusb/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h
deleted file mode 100755
index 0f820512..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PORT              GPIOC
-#define LED_PIN               GPIO_PIN_13
-#define LED_STATE_ON          0
-
-// Button
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE   0
-
-// Enable PA2 as the debug log UART
-//#define UART_DEV              USART2
-//#define UART_GPIO_PORT        GPIOA
-//#define UART_GPIO_AF          GPIO_AF7_USART2
-//#define UART_TX_PIN           GPIO_PIN_2
-//#define UART_RX_PIN           GPIO_PIN_3
-
-
-//--------------------------------------------------------------------+
-// RCC Clock
-//--------------------------------------------------------------------+
-static inline void board_clock_init(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable Power Control clock */
-  __HAL_RCC_PWR_CLK_ENABLE();
-
-  /* The voltage scaling allows optimizing the power consumption when the device is
-     clocked below the maximum system frequency, to update the voltage scaling value
-     regarding system frequency refer to product datasheet.  */
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
-
-  /* Enable HSE Oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
-  RCC_OscInitStruct.PLL.PLLN = 336;
-  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
-  RCC_OscInitStruct.PLL.PLLQ = 7;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
-     clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
-
-  // Enable clocks for LED, Button, Uart
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOC_CLK_ENABLE();
-  //__HAL_RCC_USART2_CLK_ENABLE();
-}
-
-static inline void board_vbus_sense_init(void)
-{
-  // Blackpill doens't use VBUS sense (B device) explicitly disable it
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk b/tinyusb/hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk
deleted file mode 100755
index 78be4348..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-CFLAGS += -DSTM32F411xE
-
-LD_FILE = $(BOARD_PATH)/STM32F411CEUx_FLASH.ld
-
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f411xe.s
-
-# For flash-jlink target
-JLINK_DEVICE = stm32f411ce
-
-# flash target ROM bootloader
-flash: $(BUILD)/$(PROJECT).bin
-	dfu-util -R -a 0 --dfuse-address 0x08000000 -D $<
diff --git a/tinyusb/hw/bsp/stm32f4/boards/stm32f411blackpill/stm32f4xx_hal_conf.h b/tinyusb/hw/bsp/stm32f4/boards/stm32f411blackpill/stm32f4xx_hal_conf.h
deleted file mode 100755
index 2ab9a1d5..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/stm32f411blackpill/stm32f4xx_hal_conf.h
+++ /dev/null
@@ -1,493 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_conf_template.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CONF_H
-#define __STM32F4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-#define HAL_MODULE_ENABLED         
-/* #define HAL_ADC_MODULE_ENABLED      */
-/* #define HAL_CAN_MODULE_ENABLED      */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
-/* #define HAL_CRC_MODULE_ENABLED      */ 
-/* #define HAL_CEC_MODULE_ENABLED      */ 
-/* #define HAL_CRYP_MODULE_ENABLED     */ 
-/* #define HAL_DAC_MODULE_ENABLED      */ 
-/* #define HAL_DCMI_MODULE_ENABLED     */ 
-#define HAL_DMA_MODULE_ENABLED 
-/* #define HAL_DMA2D_MODULE_ENABLED    */ 
-/* #define HAL_ETH_MODULE_ENABLED      */
-#define HAL_FLASH_MODULE_ENABLED 
-/* #define HAL_NAND_MODULE_ENABLED     */
-/* #define HAL_NOR_MODULE_ENABLED      */
-/* #define HAL_PCCARD_MODULE_ENABLED   */
-/* #define HAL_SRAM_MODULE_ENABLED     */
-/* #define HAL_SDRAM_MODULE_ENABLED    */
-/* #define HAL_HASH_MODULE_ENABLED     */  
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_EXTI_MODULE_ENABLED     */
-/* #define HAL_I2C_MODULE_ENABLED      */
-/* #define HAL_SMBUS_MODULE_ENABLED    */
-/* #define HAL_I2S_MODULE_ENABLED      */
-/* #define HAL_IWDG_MODULE_ENABLED     */ 
-/* #define HAL_LTDC_MODULE_ENABLED     */
-/* #define HAL_DSI_MODULE_ENABLED      */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED     */
-#define HAL_RCC_MODULE_ENABLED      
-/* #define HAL_RNG_MODULE_ENABLED      */
-/* #define HAL_RTC_MODULE_ENABLED      */
-/* #define HAL_SAI_MODULE_ENABLED      */
-/* #define HAL_SD_MODULE_ENABLED       */
-// #define HAL_SPI_MODULE_ENABLED
-/* #define HAL_TIM_MODULE_ENABLED      */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED    */ 
-/* #define HAL_IRDA_MODULE_ENABLED     */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED     */
-#define HAL_CORTEX_MODULE_ENABLED   
-/* #define HAL_PCD_MODULE_ENABLED      */
-/* #define HAL_HCD_MODULE_ENABLED      */
-/* #define HAL_FMPI2C_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED  */
-/* #define HAL_DFSDM_MODULE_ENABLED    */
-/* #define HAL_LPTIM_MODULE_ENABLED    */
-/* #define HAL_MMC_MODULE_ENABLED      */
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    (25000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  (32000U)    
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  (32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */           
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  INSTRUCTION_CACHE_ENABLE     1U
-#define  DATA_CACHE_ENABLE            1U
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1U */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */   
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    4U                  /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848 PHY Address*/ 
-#define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
-#define PHY_RESET_DELAY                 0x000000FFU
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                0x00000FFFU
-
-#define PHY_READ_TO                     0x0000FFFFU
-#define PHY_WRITE_TO                    0x0000FFFFU
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
- 
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
-#define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
-#define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
- 
-#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
-
-#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
-#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
-
-#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
-#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32f4xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-   
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f4xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h" 
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f4xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f4xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
- 
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f4xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32f4xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f4xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f4xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-   
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f4xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f4xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32f4xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_FMPI2C_MODULE_ENABLED
- #include "stm32f4xx_hal_fmpi2c.h"
-#endif /* HAL_FMPI2C_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f4xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f4xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f4xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32f4xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tinyusb/hw/bsp/stm32f4/boards/stm32f411disco/STM32F411VETx_FLASH.ld b/tinyusb/hw/bsp/stm32f4/boards/stm32f411disco/STM32F411VETx_FLASH.ld
deleted file mode 100755
index 3a0ce526..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/stm32f411disco/STM32F411VETx_FLASH.ld
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
-*****************************************************************************
-**
-
-**  File        : LinkerScript.ld
-**
-**  Abstract    : Linker script for STM32F411VETx Device with
-**                512KByte FLASH, 128KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-**  (c)Copyright Ac6.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Ac6 permit registered System Workbench for MCU users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the System Workbench for MCU toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20020000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;;      /* required amount of heap  */
-_Min_Stack_Size = 0x400;; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K
-RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-  
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
-
-
diff --git a/tinyusb/hw/bsp/stm32f4/boards/stm32f411disco/board.h b/tinyusb/hw/bsp/stm32f4/boards/stm32f411disco/board.h
deleted file mode 100755
index 008a94a5..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/stm32f411disco/board.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// Orange LED
-#define LED_PORT              GPIOD
-#define LED_PIN               GPIO_PIN_13
-#define LED_STATE_ON          1
-
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE   1
-
-// Enable PA2 as the debug log UART
-#define UART_DEV              USART2
-#define UART_GPIO_PORT        GPIOA
-#define UART_GPIO_AF          GPIO_AF7_USART2
-#define UART_TX_PIN           GPIO_PIN_2
-#define UART_RX_PIN           GPIO_PIN_3
-
-
-//--------------------------------------------------------------------+
-// RCC Clock
-//--------------------------------------------------------------------+
-static inline void board_clock_init(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable Power Control clock */
-  __HAL_RCC_PWR_CLK_ENABLE();
-
-  /* The voltage scaling allows optimizing the power consumption when the device is
-     clocked below the maximum system frequency, to update the voltage scaling value
-     regarding system frequency refer to product datasheet.  */
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
-
-  /* Enable HSE Oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
-  RCC_OscInitStruct.PLL.PLLN = 336;
-  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
-  RCC_OscInitStruct.PLL.PLLQ = 7;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
-     clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
-
-  // Enable clocks for LED, Button, Uart
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOD_CLK_ENABLE();
-  __HAL_RCC_USART2_CLK_ENABLE();
-}
-
-static inline void board_vbus_sense_init(void)
-{
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/stm32f4/boards/stm32f411disco/board.mk b/tinyusb/hw/bsp/stm32f4/boards/stm32f411disco/board.mk
deleted file mode 100755
index 48272acf..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/stm32f411disco/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-CFLAGS += -DSTM32F411xE
-
-LD_FILE = $(BOARD_PATH)/STM32F411VETx_FLASH.ld
-
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f411xe.s
-
-# For flash-jlink target
-JLINK_DEVICE = stm32f411ve
-
-# flash target using on-board stlink
-flash: flash-stlink
diff --git a/tinyusb/hw/bsp/stm32f4/boards/stm32f411disco/stm32f4xx_hal_conf.h b/tinyusb/hw/bsp/stm32f4/boards/stm32f411disco/stm32f4xx_hal_conf.h
deleted file mode 100755
index 7864f8d5..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/stm32f411disco/stm32f4xx_hal_conf.h
+++ /dev/null
@@ -1,493 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_conf_template.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CONF_H
-#define __STM32F4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-#define HAL_MODULE_ENABLED         
-/* #define HAL_ADC_MODULE_ENABLED      */
-/* #define HAL_CAN_MODULE_ENABLED      */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
-/* #define HAL_CRC_MODULE_ENABLED      */ 
-/* #define HAL_CEC_MODULE_ENABLED      */ 
-/* #define HAL_CRYP_MODULE_ENABLED     */ 
-/* #define HAL_DAC_MODULE_ENABLED      */ 
-/* #define HAL_DCMI_MODULE_ENABLED     */ 
-#define HAL_DMA_MODULE_ENABLED 
-/* #define HAL_DMA2D_MODULE_ENABLED    */ 
-/* #define HAL_ETH_MODULE_ENABLED      */
-#define HAL_FLASH_MODULE_ENABLED 
-/* #define HAL_NAND_MODULE_ENABLED     */
-/* #define HAL_NOR_MODULE_ENABLED      */
-/* #define HAL_PCCARD_MODULE_ENABLED   */
-/* #define HAL_SRAM_MODULE_ENABLED     */
-/* #define HAL_SDRAM_MODULE_ENABLED    */
-/* #define HAL_HASH_MODULE_ENABLED     */  
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_EXTI_MODULE_ENABLED     */
-/* #define HAL_I2C_MODULE_ENABLED      */
-/* #define HAL_SMBUS_MODULE_ENABLED    */
-/* #define HAL_I2S_MODULE_ENABLED      */
-/* #define HAL_IWDG_MODULE_ENABLED     */ 
-/* #define HAL_LTDC_MODULE_ENABLED     */
-/* #define HAL_DSI_MODULE_ENABLED      */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED     */
-#define HAL_RCC_MODULE_ENABLED      
-/* #define HAL_RNG_MODULE_ENABLED      */
-/* #define HAL_RTC_MODULE_ENABLED      */
-/* #define HAL_SAI_MODULE_ENABLED      */
-/* #define HAL_SD_MODULE_ENABLED       */
-// #define HAL_SPI_MODULE_ENABLED
-/* #define HAL_TIM_MODULE_ENABLED      */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED    */ 
-/* #define HAL_IRDA_MODULE_ENABLED     */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED     */
-#define HAL_CORTEX_MODULE_ENABLED   
-/* #define HAL_PCD_MODULE_ENABLED      */
-/* #define HAL_HCD_MODULE_ENABLED      */
-/* #define HAL_FMPI2C_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED  */
-/* #define HAL_DFSDM_MODULE_ENABLED    */
-/* #define HAL_LPTIM_MODULE_ENABLED    */
-/* #define HAL_MMC_MODULE_ENABLED      */
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  (32000U)    
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  (32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */           
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  INSTRUCTION_CACHE_ENABLE     1U
-#define  DATA_CACHE_ENABLE            1U
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1U */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */   
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    4U                  /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848 PHY Address*/ 
-#define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
-#define PHY_RESET_DELAY                 0x000000FFU
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                0x00000FFFU
-
-#define PHY_READ_TO                     0x0000FFFFU
-#define PHY_WRITE_TO                    0x0000FFFFU
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
- 
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
-#define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
-#define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
- 
-#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
-
-#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
-#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
-
-#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
-#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32f4xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-   
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f4xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h" 
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f4xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f4xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
- 
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f4xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32f4xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f4xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f4xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-   
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f4xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f4xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32f4xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_FMPI2C_MODULE_ENABLED
- #include "stm32f4xx_hal_fmpi2c.h"
-#endif /* HAL_FMPI2C_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f4xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f4xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f4xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32f4xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tinyusb/hw/bsp/stm32f4/boards/stm32f412disco/STM32F412ZGTx_FLASH.ld b/tinyusb/hw/bsp/stm32f4/boards/stm32f412disco/STM32F412ZGTx_FLASH.ld
deleted file mode 100755
index b00b5dbe..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/stm32f412disco/STM32F412ZGTx_FLASH.ld
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
-*****************************************************************************
-**
-
-**  File        : LinkerScript.ld
-**
-**  Abstract    : Linker script for STM32F412ZGTx Device with
-**                1024KByte FLASH, 256KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-**  (c)Copyright Ac6.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Ac6 permit registered System Workbench for MCU users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the System Workbench for MCU toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20040000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K
-RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 256K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-  
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
-
-
diff --git a/tinyusb/hw/bsp/stm32f4/boards/stm32f412disco/board.h b/tinyusb/hw/bsp/stm32f4/boards/stm32f412disco/board.h
deleted file mode 100755
index 7f4a4fa1..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/stm32f412disco/board.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PORT              GPIOE
-#define LED_PIN               GPIO_PIN_2
-#define LED_STATE_ON          0
-
-// Button
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE   1
-
-// UART Enable PA2 as the debug log UART
-#define UART_DEV              USART2
-#define UART_GPIO_PORT        GPIOA
-#define UART_GPIO_AF          GPIO_AF7_USART2
-#define UART_TX_PIN           GPIO_PIN_2
-#define UART_RX_PIN           GPIO_PIN_3
-
-//--------------------------------------------------------------------+
-// RCC Clock
-//--------------------------------------------------------------------+
-static inline void board_clock_init(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
-
-  /* Enable Power Control clock */
-  __HAL_RCC_PWR_CLK_ENABLE();
-
-  /* The voltage scaling allows optimizing the power consumption when the
-   * device is clocked below the maximum system frequency, to update the
-   * voltage scaling value regarding system frequency refer to product
-   * datasheet.  */
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-  /* Enable HSE Oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
-  RCC_OscInitStruct.PLL.PLLN = 200;
-  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
-  RCC_OscInitStruct.PLL.PLLQ = 7;
-  RCC_OscInitStruct.PLL.PLLR = 2;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Select PLLSAI output as USB clock source */
-  PeriphClkInitStruct.PLLI2S.PLLI2SM = 8;
-  PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
-  PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
-  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CK48;
-  PeriphClkInitStruct.Clk48ClockSelection = RCC_CK48CLKSOURCE_PLLI2SQ;
-  PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
-  PeriphClkInitStruct.PLLI2S.PLLI2SR = 7;
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
-   * clocks dividers */
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK |
-                                RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
-
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3);
-
-  // Enable clocks for LED, Button, Uart
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOE_CLK_ENABLE();
-  __HAL_RCC_USART2_CLK_ENABLE();
-}
-
-static inline void board_vbus_sense_init(void)
-{
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/stm32f4/boards/stm32f412disco/board.mk b/tinyusb/hw/bsp/stm32f4/boards/stm32f412disco/board.mk
deleted file mode 100755
index 50973f73..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/stm32f412disco/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-CFLAGS += -DSTM32F412Zx
-
-LD_FILE = $(BOARD_PATH)/STM32F412ZGTx_FLASH.ld
-
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f412zx.s
-
-# For flash-jlink target
-JLINK_DEVICE = stm32f412zg
-
-# flash target using on-board stlink
-flash: flash-stlink
diff --git a/tinyusb/hw/bsp/stm32f4/boards/stm32f412disco/stm32f4xx_hal_conf.h b/tinyusb/hw/bsp/stm32f4/boards/stm32f412disco/stm32f4xx_hal_conf.h
deleted file mode 100755
index 7864f8d5..00000000
--- a/tinyusb/hw/bsp/stm32f4/boards/stm32f412disco/stm32f4xx_hal_conf.h
+++ /dev/null
@@ -1,493 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_conf_template.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CONF_H
-#define __STM32F4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-#define HAL_MODULE_ENABLED         
-/* #define HAL_ADC_MODULE_ENABLED      */
-/* #define HAL_CAN_MODULE_ENABLED      */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
-/* #define HAL_CRC_MODULE_ENABLED      */ 
-/* #define HAL_CEC_MODULE_ENABLED      */ 
-/* #define HAL_CRYP_MODULE_ENABLED     */ 
-/* #define HAL_DAC_MODULE_ENABLED      */ 
-/* #define HAL_DCMI_MODULE_ENABLED     */ 
-#define HAL_DMA_MODULE_ENABLED 
-/* #define HAL_DMA2D_MODULE_ENABLED    */ 
-/* #define HAL_ETH_MODULE_ENABLED      */
-#define HAL_FLASH_MODULE_ENABLED 
-/* #define HAL_NAND_MODULE_ENABLED     */
-/* #define HAL_NOR_MODULE_ENABLED      */
-/* #define HAL_PCCARD_MODULE_ENABLED   */
-/* #define HAL_SRAM_MODULE_ENABLED     */
-/* #define HAL_SDRAM_MODULE_ENABLED    */
-/* #define HAL_HASH_MODULE_ENABLED     */  
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_EXTI_MODULE_ENABLED     */
-/* #define HAL_I2C_MODULE_ENABLED      */
-/* #define HAL_SMBUS_MODULE_ENABLED    */
-/* #define HAL_I2S_MODULE_ENABLED      */
-/* #define HAL_IWDG_MODULE_ENABLED     */ 
-/* #define HAL_LTDC_MODULE_ENABLED     */
-/* #define HAL_DSI_MODULE_ENABLED      */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED     */
-#define HAL_RCC_MODULE_ENABLED      
-/* #define HAL_RNG_MODULE_ENABLED      */
-/* #define HAL_RTC_MODULE_ENABLED      */
-/* #define HAL_SAI_MODULE_ENABLED      */
-/* #define HAL_SD_MODULE_ENABLED       */
-// #define HAL_SPI_MODULE_ENABLED
-/* #define HAL_TIM_MODULE_ENABLED      */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED    */ 
-/* #define HAL_IRDA_MODULE_ENABLED     */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED     */
-#define HAL_CORTEX_MODULE_ENABLED   
-/* #define HAL_PCD_MODULE_ENABLED      */
-/* #define HAL_HCD_MODULE_ENABLED      */
-/* #define HAL_FMPI2C_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED  */
-/* #define HAL_DFSDM_MODULE_ENABLED    */
-/* #define HAL_LPTIM_MODULE_ENABLED    */
-/* #define HAL_MMC_MODULE_ENABLED      */
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  (32000U)    
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  (32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */           
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  INSTRUCTION_CACHE_ENABLE     1U
-#define  DATA_CACHE_ENABLE            1U
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1U */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */   
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    4U                  /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848 PHY Address*/ 
-#define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
-#define PHY_RESET_DELAY                 0x000000FFU
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                0x00000FFFU
-
-#define PHY_READ_TO                     0x0000FFFFU
-#define PHY_WRITE_TO                    0x0000FFFFU
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
- 
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
-#define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
-#define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
- 
-#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
-
-#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
-#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
-
-#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
-#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32f4xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-   
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f4xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h" 
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f4xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f4xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
- 
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f4xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32f4xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f4xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f4xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-   
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f4xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f4xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32f4xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_FMPI2C_MODULE_ENABLED
- #include "stm32f4xx_hal_fmpi2c.h"
-#endif /* HAL_FMPI2C_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f4xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f4xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f4xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32f4xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tinyusb/hw/bsp/stm32f4/family.c b/tinyusb/hw/bsp/stm32f4/family.c
deleted file mode 100755
index 4a0dbcb1..00000000
--- a/tinyusb/hw/bsp/stm32f4/family.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "stm32f4xx_hal.h"
-#include "bsp/board.h"
-#include "board.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void OTG_FS_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-UART_HandleTypeDef UartHandle;
-
-void board_init(void)
-{
-  board_clock_init();
-  //SystemCoreClockUpdate();
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  GPIO_InitTypeDef  GPIO_InitStruct;
-
-  // LED
-  GPIO_InitStruct.Pin = LED_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
-
-  board_led_write(false);
-
-  // Button
-  GPIO_InitStruct.Pin = BUTTON_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN : GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
-
-#ifdef UART_DEV
-  // UART
-  GPIO_InitStruct.Pin       = UART_TX_PIN | UART_RX_PIN;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_PULLUP;
-  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
-  GPIO_InitStruct.Alternate = UART_GPIO_AF;
-  HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
-
-  UartHandle = (UART_HandleTypeDef){
-    .Instance        = UART_DEV,
-    .Init.BaudRate   = CFG_BOARD_UART_BAUDRATE,
-    .Init.WordLength = UART_WORDLENGTH_8B,
-    .Init.StopBits   = UART_STOPBITS_1,
-    .Init.Parity     = UART_PARITY_NONE,
-    .Init.HwFlowCtl  = UART_HWCONTROL_NONE,
-    .Init.Mode       = UART_MODE_TX_RX,
-    .Init.OverSampling = UART_OVERSAMPLING_16
-  };
-  HAL_UART_Init(&UartHandle);
-#endif
-
-  /* Configure USB FS GPIOs */
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-
-  /* Configure USB D+ D- Pins */
-  GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12;
-  GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* Configure VBUS Pin */
-  GPIO_InitStruct.Pin = GPIO_PIN_9;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* ID Pin */
-  GPIO_InitStruct.Pin = GPIO_PIN_10;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-#ifdef STM32F412Zx
-  /* Configure POWER_SWITCH IO pin */
-  __HAL_RCC_GPIOG_CLK_ENABLE();
-  GPIO_InitStruct.Pin = GPIO_PIN_8;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
-#endif
-
-  // Enable USB OTG clock
-  __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
-
-  board_vbus_sense_init();
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-#ifdef UART_DEV
-  HAL_UART_Transmit(&UartHandle, (uint8_t*) buf, len, 0xffff);
-  return len;
-#else
-  (void) buf; (void) len; (void) UartHandle;
-  return 0;
-#endif
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-
-void HardFault_Handler (void)
-{
-  asm("bkpt");
-}
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
-}
diff --git a/tinyusb/hw/bsp/stm32f4/family.mk b/tinyusb/hw/bsp/stm32f4/family.mk
deleted file mode 100755
index 584d6940..00000000
--- a/tinyusb/hw/bsp/stm32f4/family.mk
+++ /dev/null
@@ -1,43 +0,0 @@
-UF2_FAMILY_ID = 0x57755a57
-ST_FAMILY = f4
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
-ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib -nostartfiles \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32F4
-
-# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=cast-align
-
-SRC_C += \
-	src/portable/st/synopsys/dcd_synopsys.c \
-	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-	$(TOP)/$(ST_CMSIS)/Include \
-	$(TOP)/$(ST_HAL_DRIVER)/Inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
-# flash target using on-board stlink
-flash: flash-stlink
diff --git a/tinyusb/hw/bsp/stm32f7/boards/stlinkv3mini/STM32F723xE_FLASH.ld b/tinyusb/hw/bsp/stm32f7/boards/stlinkv3mini/STM32F723xE_FLASH.ld
deleted file mode 100755
index 8645ce5c..00000000
--- a/tinyusb/hw/bsp/stm32f7/boards/stlinkv3mini/STM32F723xE_FLASH.ld
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
-*****************************************************************************
-**
-
-**  File        : LinkerScript.ld
-**
-**  Abstract    : Linker script for STM32F723xE Device with
-**                512KByte FLASH, 256KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-**  (c)Copyright Ac6.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Ac6 permit registered System Workbench for MCU users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the System Workbench for MCU toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20040000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x460; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 256K
-FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 512K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data :
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
diff --git a/tinyusb/hw/bsp/stm32f7/boards/stlinkv3mini/board.h b/tinyusb/hw/bsp/stm32f7/boards/stlinkv3mini/board.h
deleted file mode 100755
index d0ef6625..00000000
--- a/tinyusb/hw/bsp/stm32f7/boards/stlinkv3mini/board.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define LED_PORT              GPIOA
-#define LED_PIN               GPIO_PIN_10
-#define LED_STATE_ON          1
-
-// No physical button is populated
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE   1
-
-#define UART_DEV              USART6
-#define UART_CLK_EN           __HAL_RCC_USART6_CLK_ENABLE
-#define UART_GPIO_AF          GPIO_AF8_USART6
-
-#define UART_TX_PORT          GPIOG
-#define UART_TX_PIN           GPIO_PIN_9
-
-#define UART_RX_PORT          GPIOG
-#define UART_RX_PIN           GPIO_PIN_14
-
-// VBUS Sense detection
-#define OTG_FS_VBUS_SENSE     1
-#define OTG_HS_VBUS_SENSE     0
-
-//--------------------------------------------------------------------+
-// RCC Clock
-//--------------------------------------------------------------------+
-static inline void board_clock_init(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable Power Control clock */
-  __HAL_RCC_PWR_CLK_ENABLE();
-
-  /* The voltage scaling allows optimizing the power consumption when the device is
-     clocked below the maximum system frequency, to update the voltage scaling value
-     regarding system frequency refer to product datasheet.  */
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-  /* Enable HSE Oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
-  RCC_OscInitStruct.PLL.PLLN = 432;
-  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
-  RCC_OscInitStruct.PLL.PLLQ = 9;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Activate the OverDrive to reach the 216 MHz Frequency */
-  HAL_PWREx_EnableOverDrive();
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
-
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/stm32f7/boards/stlinkv3mini/board.mk b/tinyusb/hw/bsp/stm32f7/boards/stlinkv3mini/board.mk
deleted file mode 100755
index a18b3231..00000000
--- a/tinyusb/hw/bsp/stm32f7/boards/stlinkv3mini/board.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# Only OTG-HS has a connector on this board
-PORT ?= 1
-SPEED ?= high
-
-CFLAGS += \
-  -DSTM32F723xx \
-  -DHSE_VALUE=25000000 \
-
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/STM32F723xE_FLASH.ld
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f723xx.s
-
-# flash target using on-board stlink
-flash: flash-stlink
diff --git a/tinyusb/hw/bsp/stm32f7/boards/stlinkv3mini/stm32f7xx_hal_conf.h b/tinyusb/hw/bsp/stm32f7/boards/stlinkv3mini/stm32f7xx_hal_conf.h
deleted file mode 100755
index 581f0e46..00000000
--- a/tinyusb/hw/bsp/stm32f7/boards/stlinkv3mini/stm32f7xx_hal_conf.h
+++ /dev/null
@@ -1,472 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_CONF_H
-#define __STM32F7xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-/* #define HAL_ADC_MODULE_ENABLED   */
-/* #define HAL_CAN_MODULE_ENABLED */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
-/* #define HAL_CEC_MODULE_ENABLED   */
-/* #define HAL_CRC_MODULE_ENABLED   */
-/* #define HAL_CRYP_MODULE_ENABLED   */
-/* #define HAL_DAC_MODULE_ENABLED   */
-/* #define HAL_DCMI_MODULE_ENABLED  */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED  */
-/* #define HAL_ETH_MODULE_ENABLED  */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_HASH_MODULE_ENABLED   */
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED    */
-/* #define HAL_IWDG_MODULE_ENABLED  */
-/* #define HAL_LPTIM_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED  */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED    */
-#define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RNG_MODULE_ENABLED    */
-/* #define HAL_RTC_MODULE_ENABLED */
-/* #define HAL_SAI_MODULE_ENABLED    */
-/* #define HAL_SD_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED */
-/* #define HAL_SPI_MODULE_ENABLED    */
-/* #define HAL_TIM_MODULE_ENABLED    */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED  */
-/* #define HAL_IRDA_MODULE_ENABLED  */
-/* #define HAL_SMARTCARD_MODULE_ENABLED  */
-/* #define HAL_WWDG_MODULE_ENABLED   */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_PCD_MODULE_ENABLED */
-/* #define HAL_HCD_MODULE_ENABLED */
-/* #define HAL_DFSDM_MODULE_ENABLED */
-/* #define HAL_DSI_MODULE_ENABLED */
-/* #define HAL_JPEG_MODULE_ENABLED */
-/* #define HAL_MDIOS_MODULE_ENABLED */
-
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE)
- #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x0FU) /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  ART_ACCLERATOR_ENABLE        1U /* To enable instruction cache and prefetch */
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_JPEG_REGISTER_CALLBACKS        0U /* JPEG register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MDIOS_REGISTER_CALLBACKS       0U /* MDIOS register callback disabled     */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-/* ################## Ethernet peripheral configuration for NUCLEO 144 board ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)5)       /* 5 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)5)       /* 5 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-/* LAN8742A PHY Address*/
-#define LAN8742A_PHY_ADDRESS            0x00
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY                 ((uint32_t)0x00000FFF)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
-
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x1F)    /*!< PHY special control/ status register Offset     */
-
-#define PHY_SPEED_STATUS                ((uint16_t)0x0004)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0010)  /*!< PHY Duplex mask                                 */
-
-
-#define PHY_ISFR                        ((uint16_t)0x1D)    /*!< PHY Interrupt Source Flag register Offset       */
-#define PHY_ISFR_INT4                   ((uint16_t)0x0010)  /*!< PHY Link down inturrupt                         */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f7xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f7xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f7xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f7xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f7xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f7xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
-  #include "stm32f7xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f7xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f7xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f7xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f7xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f7xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f7xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f7xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f7xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f7xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f7xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f7xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f7xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f7xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f7xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f7xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f7xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f7xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f7xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f7xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f7xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f7xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f7xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f7xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f7xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f7xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f7xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f7xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f7xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f7xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f7xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_JPEG_MODULE_ENABLED
- #include "stm32f7xx_hal_jpeg.h"
-#endif /* HAL_JPEG_MODULE_ENABLED */
-
-#ifdef HAL_MDIOS_MODULE_ENABLED
- #include "stm32f7xx_hal_mdios.h"
-#endif /* HAL_MDIOS_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tinyusb/hw/bsp/stm32f7/boards/stm32f723disco/STM32F723xE_FLASH.ld b/tinyusb/hw/bsp/stm32f7/boards/stm32f723disco/STM32F723xE_FLASH.ld
deleted file mode 100755
index 8645ce5c..00000000
--- a/tinyusb/hw/bsp/stm32f7/boards/stm32f723disco/STM32F723xE_FLASH.ld
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
-*****************************************************************************
-**
-
-**  File        : LinkerScript.ld
-**
-**  Abstract    : Linker script for STM32F723xE Device with
-**                512KByte FLASH, 256KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-**  (c)Copyright Ac6.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Ac6 permit registered System Workbench for MCU users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the System Workbench for MCU toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20040000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x460; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 256K
-FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 512K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data :
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
diff --git a/tinyusb/hw/bsp/stm32f7/boards/stm32f723disco/board.h b/tinyusb/hw/bsp/stm32f7/boards/stm32f723disco/board.h
deleted file mode 100755
index 93d83efc..00000000
--- a/tinyusb/hw/bsp/stm32f7/boards/stm32f723disco/board.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define LED_PORT              GPIOB
-#define LED_PIN               GPIO_PIN_1
-#define LED_STATE_ON          1
-
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE   1
-
-#define UART_DEV              USART6
-#define UART_CLK_EN           __HAL_RCC_USART6_CLK_ENABLE
-#define UART_GPIO_AF          GPIO_AF8_USART6
-
-#define UART_TX_PORT          GPIOC
-#define UART_TX_PIN           GPIO_PIN_6
-
-#define UART_RX_PORT          GPIOC
-#define UART_RX_PIN           GPIO_PIN_7
-
-// VBUS Sense detection
-#define OTG_FS_VBUS_SENSE     1
-#define OTG_HS_VBUS_SENSE     0
-
-//--------------------------------------------------------------------+
-// RCC Clock
-//--------------------------------------------------------------------+
-static inline void board_clock_init(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable Power Control clock */
-  __HAL_RCC_PWR_CLK_ENABLE();
-
-  /* The voltage scaling allows optimizing the power consumption when the device is
-     clocked below the maximum system frequency, to update the voltage scaling value
-     regarding system frequency refer to product datasheet.  */
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-  /* Enable HSE Oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
-  RCC_OscInitStruct.PLL.PLLN = 432;
-  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
-  RCC_OscInitStruct.PLL.PLLQ = 9;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Activate the OverDrive to reach the 216 MHz Frequency */
-  HAL_PWREx_EnableOverDrive();
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
-
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
-}
-
-//static inline void board_vbus_sense_init(void)
-//{
-//
-//}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/stm32f7/boards/stm32f723disco/board.mk b/tinyusb/hw/bsp/stm32f7/boards/stm32f723disco/board.mk
deleted file mode 100755
index 8f05199d..00000000
--- a/tinyusb/hw/bsp/stm32f7/boards/stm32f723disco/board.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-PORT ?= 1
-SPEED ?= high
-
-CFLAGS += \
-  -DSTM32F723xx \
-  -DHSE_VALUE=25000000 \
-
-LD_FILE = $(BOARD_PATH)/STM32F723xE_FLASH.ld
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f723xx.s
-
-# flash target using on-board stlink
-flash: flash-stlink
diff --git a/tinyusb/hw/bsp/stm32f7/boards/stm32f723disco/stm32f7xx_hal_conf.h b/tinyusb/hw/bsp/stm32f7/boards/stm32f723disco/stm32f7xx_hal_conf.h
deleted file mode 100755
index 581f0e46..00000000
--- a/tinyusb/hw/bsp/stm32f7/boards/stm32f723disco/stm32f7xx_hal_conf.h
+++ /dev/null
@@ -1,472 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_CONF_H
-#define __STM32F7xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-/* #define HAL_ADC_MODULE_ENABLED   */
-/* #define HAL_CAN_MODULE_ENABLED */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
-/* #define HAL_CEC_MODULE_ENABLED   */
-/* #define HAL_CRC_MODULE_ENABLED   */
-/* #define HAL_CRYP_MODULE_ENABLED   */
-/* #define HAL_DAC_MODULE_ENABLED   */
-/* #define HAL_DCMI_MODULE_ENABLED  */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED  */
-/* #define HAL_ETH_MODULE_ENABLED  */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_HASH_MODULE_ENABLED   */
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED    */
-/* #define HAL_IWDG_MODULE_ENABLED  */
-/* #define HAL_LPTIM_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED  */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED    */
-#define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RNG_MODULE_ENABLED    */
-/* #define HAL_RTC_MODULE_ENABLED */
-/* #define HAL_SAI_MODULE_ENABLED    */
-/* #define HAL_SD_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED */
-/* #define HAL_SPI_MODULE_ENABLED    */
-/* #define HAL_TIM_MODULE_ENABLED    */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED  */
-/* #define HAL_IRDA_MODULE_ENABLED  */
-/* #define HAL_SMARTCARD_MODULE_ENABLED  */
-/* #define HAL_WWDG_MODULE_ENABLED   */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_PCD_MODULE_ENABLED */
-/* #define HAL_HCD_MODULE_ENABLED */
-/* #define HAL_DFSDM_MODULE_ENABLED */
-/* #define HAL_DSI_MODULE_ENABLED */
-/* #define HAL_JPEG_MODULE_ENABLED */
-/* #define HAL_MDIOS_MODULE_ENABLED */
-
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE)
- #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x0FU) /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  ART_ACCLERATOR_ENABLE        1U /* To enable instruction cache and prefetch */
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_JPEG_REGISTER_CALLBACKS        0U /* JPEG register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MDIOS_REGISTER_CALLBACKS       0U /* MDIOS register callback disabled     */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-/* ################## Ethernet peripheral configuration for NUCLEO 144 board ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)5)       /* 5 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)5)       /* 5 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-/* LAN8742A PHY Address*/
-#define LAN8742A_PHY_ADDRESS            0x00
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY                 ((uint32_t)0x00000FFF)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
-
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x1F)    /*!< PHY special control/ status register Offset     */
-
-#define PHY_SPEED_STATUS                ((uint16_t)0x0004)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0010)  /*!< PHY Duplex mask                                 */
-
-
-#define PHY_ISFR                        ((uint16_t)0x1D)    /*!< PHY Interrupt Source Flag register Offset       */
-#define PHY_ISFR_INT4                   ((uint16_t)0x0010)  /*!< PHY Link down inturrupt                         */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f7xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f7xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f7xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f7xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f7xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f7xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
-  #include "stm32f7xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f7xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f7xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f7xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f7xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f7xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f7xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f7xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f7xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f7xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f7xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f7xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f7xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f7xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f7xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f7xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f7xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f7xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f7xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f7xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f7xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f7xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f7xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f7xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f7xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f7xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f7xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f7xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f7xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f7xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f7xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_JPEG_MODULE_ENABLED
- #include "stm32f7xx_hal_jpeg.h"
-#endif /* HAL_JPEG_MODULE_ENABLED */
-
-#ifdef HAL_MDIOS_MODULE_ENABLED
- #include "stm32f7xx_hal_mdios.h"
-#endif /* HAL_MDIOS_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tinyusb/hw/bsp/stm32f7/boards/stm32f746disco/STM32F746ZGTx_FLASH.ld b/tinyusb/hw/bsp/stm32f7/boards/stm32f746disco/STM32F746ZGTx_FLASH.ld
deleted file mode 100755
index 045ec76f..00000000
--- a/tinyusb/hw/bsp/stm32f7/boards/stm32f746disco/STM32F746ZGTx_FLASH.ld
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
-*****************************************************************************
-**
-
-**  File        : LinkerScript.ld
-**
-**  Abstract    : Linker script for STM32F746ZGTx Device with
-**                1024KByte FLASH, 320KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-**  (c)Copyright Ac6.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Ac6 permit registered System Workbench for MCU users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the System Workbench for MCU toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20050000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x460; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 320K
-FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 1024K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data :
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
diff --git a/tinyusb/hw/bsp/stm32f7/boards/stm32f746disco/board.h b/tinyusb/hw/bsp/stm32f7/boards/stm32f746disco/board.h
deleted file mode 100755
index ee342b9f..00000000
--- a/tinyusb/hw/bsp/stm32f7/boards/stm32f746disco/board.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define LED_PORT              GPIOI
-#define LED_PIN               GPIO_PIN_1
-#define LED_STATE_ON          1
-
-#define BUTTON_PORT           GPIOI
-#define BUTTON_PIN            GPIO_PIN_11
-#define BUTTON_STATE_ACTIVE   1
-
-#define UART_DEV              USART1
-#define UART_CLK_EN           __HAL_RCC_USART1_CLK_ENABLE
-#define UART_GPIO_AF          GPIO_AF7_USART1
-
-#define UART_TX_PORT          GPIOA
-#define UART_TX_PIN           GPIO_PIN_9
-
-#define UART_RX_PORT          GPIOB
-#define UART_RX_PIN           GPIO_PIN_7
-
-// VBUS Sense detection
-#define OTG_FS_VBUS_SENSE     0
-#define OTG_HS_VBUS_SENSE     0
-
-//--------------------------------------------------------------------+
-// RCC Clock
-//--------------------------------------------------------------------+
-static inline void board_clock_init(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable Power Control clock */
-  __HAL_RCC_PWR_CLK_ENABLE();
-
-  /* The voltage scaling allows optimizing the power consumption when the device is
-     clocked below the maximum system frequency, to update the voltage scaling value
-     regarding system frequency refer to product datasheet.  */
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-  /* Enable HSE Oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
-  RCC_OscInitStruct.PLL.PLLN = 432;
-  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
-  RCC_OscInitStruct.PLL.PLLQ = 9;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Activate the OverDrive to reach the 216 MHz Frequency */
-  HAL_PWREx_EnableOverDrive();
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
-
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/stm32f7/boards/stm32f746disco/board.mk b/tinyusb/hw/bsp/stm32f7/boards/stm32f746disco/board.mk
deleted file mode 100755
index 2ba59f67..00000000
--- a/tinyusb/hw/bsp/stm32f7/boards/stm32f746disco/board.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-PORT ?= 1
-SPEED ?= high
-
-CFLAGS += \
-  -DSTM32F746xx \
-  -DHSE_VALUE=25000000
-
-LD_FILE = $(BOARD_PATH)/STM32F746ZGTx_FLASH.ld
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f746xx.s
-
-# flash target using on-board stlink
-flash: flash-stlink
diff --git a/tinyusb/hw/bsp/stm32f7/boards/stm32f746disco/stm32f7xx_hal_conf.h b/tinyusb/hw/bsp/stm32f7/boards/stm32f746disco/stm32f7xx_hal_conf.h
deleted file mode 100755
index 03dec8f0..00000000
--- a/tinyusb/hw/bsp/stm32f7/boards/stm32f746disco/stm32f7xx_hal_conf.h
+++ /dev/null
@@ -1,472 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_CONF_H
-#define __STM32F7xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-/* #define HAL_ADC_MODULE_ENABLED   */
-/* #define HAL_CAN_MODULE_ENABLED */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
-/* #define HAL_CEC_MODULE_ENABLED   */
-/* #define HAL_CRC_MODULE_ENABLED   */
-/* #define HAL_CRYP_MODULE_ENABLED   */
-/* #define HAL_DAC_MODULE_ENABLED   */
-/* #define HAL_DCMI_MODULE_ENABLED  */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED  */
-/* #define HAL_ETH_MODULE_ENABLED  */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_HASH_MODULE_ENABLED   */
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED    */
-/* #define HAL_IWDG_MODULE_ENABLED  */
-/* #define HAL_LPTIM_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED  */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED    */
-#define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RNG_MODULE_ENABLED    */
-/* #define HAL_RTC_MODULE_ENABLED */
-/* #define HAL_SAI_MODULE_ENABLED    */
-/* #define HAL_SD_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED */
-/* #define HAL_SPI_MODULE_ENABLED    */
-/* #define HAL_TIM_MODULE_ENABLED    */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED  */
-/* #define HAL_IRDA_MODULE_ENABLED  */
-/* #define HAL_SMARTCARD_MODULE_ENABLED  */
-/* #define HAL_WWDG_MODULE_ENABLED   */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_PCD_MODULE_ENABLED */
-/* #define HAL_HCD_MODULE_ENABLED */
-/* #define HAL_DFSDM_MODULE_ENABLED */
-/* #define HAL_DSI_MODULE_ENABLED */
-/* #define HAL_JPEG_MODULE_ENABLED */
-/* #define HAL_MDIOS_MODULE_ENABLED */
-
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE)
- #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x0FU) /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  ART_ACCLERATOR_ENABLE        1U /* To enable instruction cache and prefetch */
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_JPEG_REGISTER_CALLBACKS        0U /* JPEG register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MDIOS_REGISTER_CALLBACKS       0U /* MDIOS register callback disabled     */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-/* ################## Ethernet peripheral configuration for NUCLEO 144 board ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)5)       /* 5 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)5)       /* 5 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-/* LAN8742A PHY Address*/
-#define LAN8742A_PHY_ADDRESS            0x00
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY                 ((uint32_t)0x00000FFF)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
-
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x1F)    /*!< PHY special control/ status register Offset     */
-
-#define PHY_SPEED_STATUS                ((uint16_t)0x0004)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0010)  /*!< PHY Duplex mask                                 */
-
-
-#define PHY_ISFR                        ((uint16_t)0x1D)    /*!< PHY Interrupt Source Flag register Offset       */
-#define PHY_ISFR_INT4                   ((uint16_t)0x0010)  /*!< PHY Link down inturrupt                         */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f7xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f7xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f7xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f7xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f7xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f7xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
-  #include "stm32f7xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f7xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f7xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f7xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f7xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f7xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f7xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f7xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f7xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f7xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f7xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f7xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f7xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f7xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f7xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f7xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f7xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f7xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f7xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f7xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f7xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f7xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f7xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f7xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f7xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f7xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f7xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f7xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f7xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f7xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f7xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_JPEG_MODULE_ENABLED
- #include "stm32f7xx_hal_jpeg.h"
-#endif /* HAL_JPEG_MODULE_ENABLED */
-
-#ifdef HAL_MDIOS_MODULE_ENABLED
- #include "stm32f7xx_hal_mdios.h"
-#endif /* HAL_MDIOS_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tinyusb/hw/bsp/stm32f7/boards/stm32f746nucleo/STM32F746ZGTx_FLASH.ld b/tinyusb/hw/bsp/stm32f7/boards/stm32f746nucleo/STM32F746ZGTx_FLASH.ld
deleted file mode 100755
index b434a01b..00000000
--- a/tinyusb/hw/bsp/stm32f7/boards/stm32f746nucleo/STM32F746ZGTx_FLASH.ld
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
-*****************************************************************************
-**
-
-**  File        : LinkerScript.ld
-**
-**  Abstract    : Linker script for STM32F746ZGTx Device with
-**                1024KByte FLASH, 320KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-**  (c)Copyright Ac6.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Ac6 permit registered System Workbench for MCU users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the System Workbench for MCU toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20050000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x460; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 320K
-FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 1024K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-  
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
diff --git a/tinyusb/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h b/tinyusb/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h
deleted file mode 100755
index 093445ed..00000000
--- a/tinyusb/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define LED_PORT              GPIOB
-#define LED_PIN               GPIO_PIN_14
-#define LED_STATE_ON          1
-
-#define BUTTON_PORT           GPIOC
-#define BUTTON_PIN            GPIO_PIN_13
-#define BUTTON_STATE_ACTIVE   1
-
-#define UART_DEV              USART3
-#define UART_CLK_EN           __HAL_RCC_USART3_CLK_ENABLE
-#define UART_GPIO_AF          GPIO_AF7_USART3
-
-#define UART_TX_PORT          GPIOD
-#define UART_TX_PIN           GPIO_PIN_8
-#define UART_RX_PORT          GPIOD
-#define UART_RX_PIN           GPIO_PIN_9
-
-// VBUS Sense detection
-#define OTG_FS_VBUS_SENSE     1
-#define OTG_HS_VBUS_SENSE     0
-
-static inline void board_clock_init(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable Power Control clock */
-  __HAL_RCC_PWR_CLK_ENABLE();
-
-  /* The voltage scaling allows optimizing the power consumption when the device is
-     clocked below the maximum system frequency, to update the voltage scaling value
-     regarding system frequency refer to product datasheet.  */
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-  /* Enable HSE Oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
-  RCC_OscInitStruct.PLL.PLLN = 432;
-  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
-  RCC_OscInitStruct.PLL.PLLQ = 9;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Activate the OverDrive to reach the 216 MHz Frequency */
-  HAL_PWREx_EnableOverDrive();
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
-
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/stm32f7/boards/stm32f746nucleo/board.mk b/tinyusb/hw/bsp/stm32f7/boards/stm32f746nucleo/board.mk
deleted file mode 100755
index 3dcf4817..00000000
--- a/tinyusb/hw/bsp/stm32f7/boards/stm32f746nucleo/board.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-PORT ?= 0
-SPEED ?= full
-
-CFLAGS += \
-  -DSTM32F746xx \
-  -DHSE_VALUE=8000000
-
-LD_FILE = $(BOARD_PATH)/STM32F746ZGTx_FLASH.ld
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f746xx.s
-
-# flash target using on-board stlink
-flash: flash-stlink
diff --git a/tinyusb/hw/bsp/stm32f7/boards/stm32f746nucleo/stm32f7xx_hal_conf.h b/tinyusb/hw/bsp/stm32f7/boards/stm32f746nucleo/stm32f7xx_hal_conf.h
deleted file mode 100755
index 234191b0..00000000
--- a/tinyusb/hw/bsp/stm32f7/boards/stm32f746nucleo/stm32f7xx_hal_conf.h
+++ /dev/null
@@ -1,472 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file. 
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_CONF_H
-#define __STM32F7xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-#define HAL_MODULE_ENABLED  
-/* #define HAL_ADC_MODULE_ENABLED   */
-/* #define HAL_CAN_MODULE_ENABLED */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
-/* #define HAL_CEC_MODULE_ENABLED   */
-/* #define HAL_CRC_MODULE_ENABLED   */
-/* #define HAL_CRYP_MODULE_ENABLED   */
-/* #define HAL_DAC_MODULE_ENABLED   */
-/* #define HAL_DCMI_MODULE_ENABLED  */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED  */
-/* #define HAL_ETH_MODULE_ENABLED  */
-#define HAL_FLASH_MODULE_ENABLED 
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_HASH_MODULE_ENABLED   */
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED    */
-/* #define HAL_IWDG_MODULE_ENABLED  */
-/* #define HAL_LPTIM_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED  */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED    */
-#define HAL_RCC_MODULE_ENABLED 
-/* #define HAL_RNG_MODULE_ENABLED    */
-/* #define HAL_RTC_MODULE_ENABLED */
-/* #define HAL_SAI_MODULE_ENABLED    */
-/* #define HAL_SD_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED */
-/* #define HAL_SPI_MODULE_ENABLED    */
-/* #define HAL_TIM_MODULE_ENABLED    */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED  */
-/* #define HAL_IRDA_MODULE_ENABLED  */
-/* #define HAL_SMARTCARD_MODULE_ENABLED  */
-/* #define HAL_WWDG_MODULE_ENABLED   */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_PCD_MODULE_ENABLED */
-/* #define HAL_HCD_MODULE_ENABLED */
-/* #define HAL_DFSDM_MODULE_ENABLED */
-/* #define HAL_DSI_MODULE_ENABLED */
-/* #define HAL_JPEG_MODULE_ENABLED */
-/* #define HAL_MDIOS_MODULE_ENABLED */
-
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x0FU) /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  ART_ACCLERATOR_ENABLE        1U /* To enable instruction cache and prefetch */
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_JPEG_REGISTER_CALLBACKS        0U /* JPEG register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MDIOS_REGISTER_CALLBACKS       0U /* MDIOS register callback disabled     */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-/* ################## Ethernet peripheral configuration for NUCLEO 144 board ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */   
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)5)       /* 5 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)5)       /* 5 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-/* LAN8742A PHY Address*/
-#define LAN8742A_PHY_ADDRESS            0x00
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
-#define PHY_RESET_DELAY                 ((uint32_t)0x00000FFF)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
- 
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x1F)    /*!< PHY special control/ status register Offset     */
-
-#define PHY_SPEED_STATUS                ((uint16_t)0x0004)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0010)  /*!< PHY Duplex mask                                 */
-
-
-#define PHY_ISFR                        ((uint16_t)0x1D)    /*!< PHY Interrupt Source Flag register Offset       */
-#define PHY_ISFR_INT4                   ((uint16_t)0x0010)  /*!< PHY Link down inturrupt                         */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f7xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f7xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-   
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f7xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f7xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f7xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f7xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
-  #include "stm32f7xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f7xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f7xx_hal_cryp.h" 
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f7xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f7xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f7xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f7xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
- 
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f7xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f7xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f7xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f7xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f7xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f7xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f7xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f7xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f7xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f7xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f7xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f7xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f7xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f7xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f7xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f7xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f7xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f7xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f7xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f7xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f7xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f7xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f7xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f7xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_JPEG_MODULE_ENABLED
- #include "stm32f7xx_hal_jpeg.h"
-#endif /* HAL_JPEG_MODULE_ENABLED */
-
-#ifdef HAL_MDIOS_MODULE_ENABLED
- #include "stm32f7xx_hal_mdios.h"
-#endif /* HAL_MDIOS_MODULE_ENABLED */
-   
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_CONF_H */
- 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tinyusb/hw/bsp/stm32f7/boards/stm32f767nucleo/STM32F767ZITx_FLASH.ld b/tinyusb/hw/bsp/stm32f7/boards/stm32f767nucleo/STM32F767ZITx_FLASH.ld
deleted file mode 100755
index 0b6d5a49..00000000
--- a/tinyusb/hw/bsp/stm32f7/boards/stm32f767nucleo/STM32F767ZITx_FLASH.ld
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
-*****************************************************************************
-**
-
-**  File        : LinkerScript.ld
-**
-**  Abstract    : Linker script for STM32F767ZITx Device with
-**                2048KByte FLASH, 512KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-**  (c)Copyright Ac6.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Ac6 permit registered System Workbench for MCU users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the System Workbench for MCU toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20080000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 2048K
-RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 512K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-  
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
-
-
diff --git a/tinyusb/hw/bsp/stm32f7/boards/stm32f767nucleo/board.h b/tinyusb/hw/bsp/stm32f7/boards/stm32f767nucleo/board.h
deleted file mode 100755
index 1283f231..00000000
--- a/tinyusb/hw/bsp/stm32f7/boards/stm32f767nucleo/board.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define LED_PORT              GPIOB
-#define LED_PIN               GPIO_PIN_14
-#define LED_STATE_ON          1
-
-#define BUTTON_PORT           GPIOC
-#define BUTTON_PIN            GPIO_PIN_13
-#define BUTTON_STATE_ACTIVE   1
-
-#define UART_DEV              USART3
-#define UART_CLK_EN           __HAL_RCC_USART3_CLK_ENABLE
-#define UART_GPIO_AF          GPIO_AF7_USART3
-
-#define UART_TX_PORT          GPIOD
-#define UART_TX_PIN           GPIO_PIN_8
-
-#define UART_RX_PORT          GPIOD
-#define UART_RX_PIN           GPIO_PIN_9
-
-// VBUS Sense detection
-#define OTG_FS_VBUS_SENSE     1
-#define OTG_HS_VBUS_SENSE     0
-
-//--------------------------------------------------------------------+
-// RCC Clock
-//--------------------------------------------------------------------+
-static inline void board_clock_init(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable Power Control clock */
-  __HAL_RCC_PWR_CLK_ENABLE();
-
-  /* The voltage scaling allows optimizing the power consumption when the device is
-     clocked below the maximum system frequency, to update the voltage scaling value
-     regarding system frequency refer to product datasheet.  */
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-  /* Enable HSE Oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
-  RCC_OscInitStruct.PLL.PLLN = 432;
-  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
-  RCC_OscInitStruct.PLL.PLLQ = 9;
-  RCC_OscInitStruct.PLL.PLLR = 7;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Activate the OverDrive to reach the 216 MHz Frequency */
-  HAL_PWREx_EnableOverDrive();
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
-
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
-}
-
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk b/tinyusb/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk
deleted file mode 100755
index 2400a4ba..00000000
--- a/tinyusb/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-PORT ?= 0
-SPEED ?= full 
-
-CFLAGS += \
-  -DSTM32F767xx \
-	-DHSE_VALUE=8000000 \
-
-LD_FILE = $(BOARD_PATH)/STM32F767ZITx_FLASH.ld
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f767xx.s
-
-# flash target using on-board stlink
-flash: flash-stlink
diff --git a/tinyusb/hw/bsp/stm32f7/boards/stm32f767nucleo/stm32f7xx_hal_conf.h b/tinyusb/hw/bsp/stm32f7/boards/stm32f767nucleo/stm32f7xx_hal_conf.h
deleted file mode 100755
index 234191b0..00000000
--- a/tinyusb/hw/bsp/stm32f7/boards/stm32f767nucleo/stm32f7xx_hal_conf.h
+++ /dev/null
@@ -1,472 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file. 
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_CONF_H
-#define __STM32F7xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-#define HAL_MODULE_ENABLED  
-/* #define HAL_ADC_MODULE_ENABLED   */
-/* #define HAL_CAN_MODULE_ENABLED */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
-/* #define HAL_CEC_MODULE_ENABLED   */
-/* #define HAL_CRC_MODULE_ENABLED   */
-/* #define HAL_CRYP_MODULE_ENABLED   */
-/* #define HAL_DAC_MODULE_ENABLED   */
-/* #define HAL_DCMI_MODULE_ENABLED  */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED  */
-/* #define HAL_ETH_MODULE_ENABLED  */
-#define HAL_FLASH_MODULE_ENABLED 
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_HASH_MODULE_ENABLED   */
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED    */
-/* #define HAL_IWDG_MODULE_ENABLED  */
-/* #define HAL_LPTIM_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED  */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED    */
-#define HAL_RCC_MODULE_ENABLED 
-/* #define HAL_RNG_MODULE_ENABLED    */
-/* #define HAL_RTC_MODULE_ENABLED */
-/* #define HAL_SAI_MODULE_ENABLED    */
-/* #define HAL_SD_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED */
-/* #define HAL_SPI_MODULE_ENABLED    */
-/* #define HAL_TIM_MODULE_ENABLED    */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED  */
-/* #define HAL_IRDA_MODULE_ENABLED  */
-/* #define HAL_SMARTCARD_MODULE_ENABLED  */
-/* #define HAL_WWDG_MODULE_ENABLED   */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_PCD_MODULE_ENABLED */
-/* #define HAL_HCD_MODULE_ENABLED */
-/* #define HAL_DFSDM_MODULE_ENABLED */
-/* #define HAL_DSI_MODULE_ENABLED */
-/* #define HAL_JPEG_MODULE_ENABLED */
-/* #define HAL_MDIOS_MODULE_ENABLED */
-
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x0FU) /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  ART_ACCLERATOR_ENABLE        1U /* To enable instruction cache and prefetch */
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_JPEG_REGISTER_CALLBACKS        0U /* JPEG register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MDIOS_REGISTER_CALLBACKS       0U /* MDIOS register callback disabled     */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-/* ################## Ethernet peripheral configuration for NUCLEO 144 board ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */   
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)5)       /* 5 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)5)       /* 5 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-/* LAN8742A PHY Address*/
-#define LAN8742A_PHY_ADDRESS            0x00
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
-#define PHY_RESET_DELAY                 ((uint32_t)0x00000FFF)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
- 
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x1F)    /*!< PHY special control/ status register Offset     */
-
-#define PHY_SPEED_STATUS                ((uint16_t)0x0004)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0010)  /*!< PHY Duplex mask                                 */
-
-
-#define PHY_ISFR                        ((uint16_t)0x1D)    /*!< PHY Interrupt Source Flag register Offset       */
-#define PHY_ISFR_INT4                   ((uint16_t)0x0010)  /*!< PHY Link down inturrupt                         */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f7xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f7xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-   
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f7xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f7xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f7xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f7xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
-  #include "stm32f7xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f7xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f7xx_hal_cryp.h" 
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f7xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f7xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f7xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f7xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
- 
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f7xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f7xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f7xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f7xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f7xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f7xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f7xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f7xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f7xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f7xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f7xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f7xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f7xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f7xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f7xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f7xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f7xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f7xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f7xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f7xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f7xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f7xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f7xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f7xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_JPEG_MODULE_ENABLED
- #include "stm32f7xx_hal_jpeg.h"
-#endif /* HAL_JPEG_MODULE_ENABLED */
-
-#ifdef HAL_MDIOS_MODULE_ENABLED
- #include "stm32f7xx_hal_mdios.h"
-#endif /* HAL_MDIOS_MODULE_ENABLED */
-   
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_CONF_H */
- 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tinyusb/hw/bsp/stm32f7/boards/stm32f769disco/STM32F769ZITx_FLASH.ld b/tinyusb/hw/bsp/stm32f7/boards/stm32f769disco/STM32F769ZITx_FLASH.ld
deleted file mode 100755
index 378ed80d..00000000
--- a/tinyusb/hw/bsp/stm32f7/boards/stm32f769disco/STM32F769ZITx_FLASH.ld
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
-*****************************************************************************
-**
-
-**  File        : LinkerScript.ld
-**
-**  Abstract    : Linker script for STM32F767ZITx Device with
-**                2048KByte FLASH, 512KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-**  (c)Copyright Ac6.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Ac6 permit registered System Workbench for MCU users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the System Workbench for MCU toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20080000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 2048K
-RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 512K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data :
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
diff --git a/tinyusb/hw/bsp/stm32f7/boards/stm32f769disco/board.h b/tinyusb/hw/bsp/stm32f7/boards/stm32f769disco/board.h
deleted file mode 100755
index 5ec217f5..00000000
--- a/tinyusb/hw/bsp/stm32f7/boards/stm32f769disco/board.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define LED_PORT              GPIOJ
-#define LED_PIN               GPIO_PIN_12
-#define LED_STATE_ON          5
-
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE   1
-
-#define UART_DEV              USART1
-#define UART_CLK_EN           __HAL_RCC_USART1_CLK_ENABLE
-#define UART_GPIO_AF          GPIO_AF7_USART1
-
-#define UART_TX_PORT          GPIOA
-#define UART_TX_PIN           GPIO_PIN_9
-
-#define UART_RX_PORT          GPIOA
-#define UART_RX_PIN           GPIO_PIN_10
-
-// VBUS Sense detection
-#define OTG_FS_VBUS_SENSE     1
-#define OTG_HS_VBUS_SENSE     0
-
-//--------------------------------------------------------------------+
-// RCC Clock
-//--------------------------------------------------------------------+
-static inline void board_clock_init(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable Power Control clock */
-  __HAL_RCC_PWR_CLK_ENABLE();
-
-  /* The voltage scaling allows optimizing the power consumption when the device is
-     clocked below the maximum system frequency, to update the voltage scaling value
-     regarding system frequency refer to product datasheet.  */
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-  /* Enable HSE Oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
-  RCC_OscInitStruct.PLL.PLLN = 432;
-  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
-  RCC_OscInitStruct.PLL.PLLQ = 9;
-  RCC_OscInitStruct.PLL.PLLR = 7;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Activate the OverDrive to reach the 216 MHz Frequency */
-  HAL_PWREx_EnableOverDrive();
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
-
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/tinyusb/hw/bsp/stm32f7/boards/stm32f769disco/board.mk b/tinyusb/hw/bsp/stm32f7/boards/stm32f769disco/board.mk
deleted file mode 100755
index 45b4a78c..00000000
--- a/tinyusb/hw/bsp/stm32f7/boards/stm32f769disco/board.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-# Only OTG-HS has a connector on this board
-PORT ?= 1
-SPEED ?= high
-
-CFLAGS += \
-  -DSTM32F769xx \
-  -DHSE_VALUE=25000000 \
-
-LD_FILE = $(BOARD_PATH)/STM32F769ZITx_FLASH.ld
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f769xx.s
-
-# flash target using on-board stlink
-flash: flash-stlink
diff --git a/tinyusb/hw/bsp/stm32f7/boards/stm32f769disco/stm32f7xx_hal_conf.h b/tinyusb/hw/bsp/stm32f7/boards/stm32f769disco/stm32f7xx_hal_conf.h
deleted file mode 100755
index 581f0e46..00000000
--- a/tinyusb/hw/bsp/stm32f7/boards/stm32f769disco/stm32f7xx_hal_conf.h
+++ /dev/null
@@ -1,472 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_CONF_H
-#define __STM32F7xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-/* #define HAL_ADC_MODULE_ENABLED   */
-/* #define HAL_CAN_MODULE_ENABLED */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
-/* #define HAL_CEC_MODULE_ENABLED   */
-/* #define HAL_CRC_MODULE_ENABLED   */
-/* #define HAL_CRYP_MODULE_ENABLED   */
-/* #define HAL_DAC_MODULE_ENABLED   */
-/* #define HAL_DCMI_MODULE_ENABLED  */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED  */
-/* #define HAL_ETH_MODULE_ENABLED  */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_HASH_MODULE_ENABLED   */
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED    */
-/* #define HAL_IWDG_MODULE_ENABLED  */
-/* #define HAL_LPTIM_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED  */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED    */
-#define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RNG_MODULE_ENABLED    */
-/* #define HAL_RTC_MODULE_ENABLED */
-/* #define HAL_SAI_MODULE_ENABLED    */
-/* #define HAL_SD_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED */
-/* #define HAL_SPI_MODULE_ENABLED    */
-/* #define HAL_TIM_MODULE_ENABLED    */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED  */
-/* #define HAL_IRDA_MODULE_ENABLED  */
-/* #define HAL_SMARTCARD_MODULE_ENABLED  */
-/* #define HAL_WWDG_MODULE_ENABLED   */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_PCD_MODULE_ENABLED */
-/* #define HAL_HCD_MODULE_ENABLED */
-/* #define HAL_DFSDM_MODULE_ENABLED */
-/* #define HAL_DSI_MODULE_ENABLED */
-/* #define HAL_JPEG_MODULE_ENABLED */
-/* #define HAL_MDIOS_MODULE_ENABLED */
-
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE)
- #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x0FU) /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  ART_ACCLERATOR_ENABLE        1U /* To enable instruction cache and prefetch */
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_JPEG_REGISTER_CALLBACKS        0U /* JPEG register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MDIOS_REGISTER_CALLBACKS       0U /* MDIOS register callback disabled     */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-/* ################## Ethernet peripheral configuration for NUCLEO 144 board ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)5)       /* 5 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)5)       /* 5 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-/* LAN8742A PHY Address*/
-#define LAN8742A_PHY_ADDRESS            0x00
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY                 ((uint32_t)0x00000FFF)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
-
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x1F)    /*!< PHY special control/ status register Offset     */
-
-#define PHY_SPEED_STATUS                ((uint16_t)0x0004)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0010)  /*!< PHY Duplex mask                                 */
-
-
-#define PHY_ISFR                        ((uint16_t)0x1D)    /*!< PHY Interrupt Source Flag register Offset       */
-#define PHY_ISFR_INT4                   ((uint16_t)0x0010)  /*!< PHY Link down inturrupt                         */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f7xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f7xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f7xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f7xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f7xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f7xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
-  #include "stm32f7xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f7xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f7xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f7xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f7xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f7xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f7xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f7xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f7xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f7xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f7xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f7xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f7xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f7xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f7xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f7xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f7xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f7xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f7xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f7xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f7xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f7xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f7xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f7xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f7xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f7xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f7xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f7xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f7xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f7xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f7xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_JPEG_MODULE_ENABLED
- #include "stm32f7xx_hal_jpeg.h"
-#endif /* HAL_JPEG_MODULE_ENABLED */
-
-#ifdef HAL_MDIOS_MODULE_ENABLED
- #include "stm32f7xx_hal_mdios.h"
-#endif /* HAL_MDIOS_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tinyusb/hw/bsp/stm32f7/family.c b/tinyusb/hw/bsp/stm32f7/family.c
deleted file mode 100755
index c0d32459..00000000
--- a/tinyusb/hw/bsp/stm32f7/family.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 William D. Jones (thor0505@comcast.net),
- * Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de),
- * Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "stm32f7xx_hal.h"
-#include "bsp/board.h"
-#include "board.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void OTG_FS_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-// Despite being call USB2_OTG
-// OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port
-void OTG_HS_IRQHandler(void)
-{
-  tud_int_handler(1);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-UART_HandleTypeDef UartHandle;
-
-void board_init(void)
-{
-  board_clock_init();
-
-  // Enable All GPIOs clocks
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  __HAL_RCC_GPIOC_CLK_ENABLE();
-  __HAL_RCC_GPIOD_CLK_ENABLE();
-  __HAL_RCC_GPIOG_CLK_ENABLE();
-  __HAL_RCC_GPIOH_CLK_ENABLE();  // ULPI NXT
-  __HAL_RCC_GPIOI_CLK_ENABLE();  // ULPI NXT
-
-#ifdef __HAL_RCC_GPIOJ_CLK_ENABLE
-  __HAL_RCC_GPIOJ_CLK_ENABLE();
-#endif
-
-  UART_CLK_EN();
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#endif
-
-  GPIO_InitTypeDef  GPIO_InitStruct;
-
-  // LED
-  GPIO_InitStruct.Pin = LED_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
-
-  // Button
-  GPIO_InitStruct.Pin = BUTTON_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
-
-  // Uart TX
-  GPIO_InitStruct.Pin       = UART_TX_PIN;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_PULLUP;
-  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
-  GPIO_InitStruct.Alternate = UART_GPIO_AF;
-  HAL_GPIO_Init(UART_TX_PORT, &GPIO_InitStruct);
-
-  // Uart RX
-  GPIO_InitStruct.Pin       = UART_RX_PIN;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_PULLUP;
-  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
-  GPIO_InitStruct.Alternate = UART_GPIO_AF;
-  HAL_GPIO_Init(UART_RX_PORT, &GPIO_InitStruct);
-
-  UartHandle.Instance          = UART_DEV;
-  UartHandle.Init.BaudRate     = CFG_BOARD_UART_BAUDRATE;
-  UartHandle.Init.WordLength   = UART_WORDLENGTH_8B;
-  UartHandle.Init.StopBits     = UART_STOPBITS_1;
-  UartHandle.Init.Parity       = UART_PARITY_NONE;
-  UartHandle.Init.HwFlowCtl    = UART_HWCONTROL_NONE;
-  UartHandle.Init.Mode         = UART_MODE_TX_RX;
-  UartHandle.Init.OverSampling = UART_OVERSAMPLING_16;
-  HAL_UART_Init(&UartHandle);
-
-#if BOARD_DEVICE_RHPORT_NUM == 0
-  // OTG_FS
-
-  /* Configure DM DP Pins */
-  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* Configure OTG-FS ID pin */
-  GPIO_InitStruct.Pin = GPIO_PIN_10;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* Enable USB FS Clocks */
-  __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
-
-#if OTG_FS_VBUS_SENSE
-  /* Configure VBUS Pin */
-  GPIO_InitStruct.Pin = GPIO_PIN_9;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-#else
-  // Disable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
-
-  // B-peripheral session valid override enable
-  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
-  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
-#endif // vbus sense
-
-#else
-  // OTG_HS
-
-  #ifdef USB_HS_PHYC
-  // MCU with built-in HS PHY such as F723, F733, F730
-
-  /* Configure DM DP Pins */
-  GPIO_InitStruct.Pin       = (GPIO_PIN_14 | GPIO_PIN_15);
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_NOPULL;
-  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
-  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
-
-  // Enable HS VBUS sense (B device) via pin PB13
-  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-
-  /* Configure OTG-HS ID pin */
-  GPIO_InitStruct.Pin       = GPIO_PIN_13;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_OD;
-  GPIO_InitStruct.Pull      = GPIO_PULLUP;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
-  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
-
-  /* Enable PHYC Clocks */
-  __HAL_RCC_OTGPHYC_CLK_ENABLE();
-
-  #else
-  // MUC with external ULPI PHY
-
-  /* ULPI CLK */
-  GPIO_InitStruct.Pin       = GPIO_PIN_5;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_NOPULL;
-  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* ULPI D0 */
-  GPIO_InitStruct.Pin       = GPIO_PIN_3;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_NOPULL;
-  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* ULPI D1 D2 D3 D4 D5 D6 D7 */
-  GPIO_InitStruct.Pin       = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_5;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_NOPULL;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
-  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
-
-  /* ULPI STP */
-  GPIO_InitStruct.Pin       = GPIO_PIN_0 | GPIO_PIN_2;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_NOPULL;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
-  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
-
-  /* NXT */
-  GPIO_InitStruct.Pin       = GPIO_PIN_4;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_NOPULL;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
-  HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
-
-  /* ULPI DIR */
-  GPIO_InitStruct.Pin       = GPIO_PIN_11;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_NOPULL;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
-  HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
-  #endif // USB_HS_PHYC
-
-  // Enable USB HS & ULPI Clocks
-  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE();
-  __HAL_RCC_USB_OTG_HS_CLK_ENABLE();
-
-#if OTG_HS_VBUS_SENSE
-  #error OTG HS VBUS Sense enabled is not implemented
-#else
-  // No VBUS sense
-  USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
-
-  // B-peripheral session valid override enable
-  USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
-  USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
-#endif
-
-  // Force device mode
-  USB_OTG_HS->GUSBCFG &= ~USB_OTG_GUSBCFG_FHMOD;
-  USB_OTG_HS->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
-
-#endif // BOARD_DEVICE_RHPORT_NUM
-
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  HAL_UART_Transmit(&UartHandle, (uint8_t*) buf, len, 0xffff);
-  return len;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-
-void HardFault_Handler (void)
-{
-  asm("bkpt");
-}
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
-}
diff --git a/tinyusb/hw/bsp/stm32f7/family.mk b/tinyusb/hw/bsp/stm32f7/family.mk
deleted file mode 100755
index ead0c977..00000000
--- a/tinyusb/hw/bsp/stm32f7/family.mk
+++ /dev/null
@@ -1,54 +0,0 @@
-UF2_FAMILY_ID = 0x53b80f00
-ST_FAMILY = f7
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
-ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m7 \
-  -mfloat-abi=hard \
-  -mfpu=fpv5-d16 \
-  -nostdlib -nostartfiles \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32F7 \
-  -DBOARD_DEVICE_RHPORT_NUM=$(PORT)
-
-ifeq ($(PORT), 1)
-  ifeq ($(SPEED), high)
-    CFLAGS += -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED
-    $(info "Using OTG_HS in HighSpeed mode")
-  else
-    CFLAGS += -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_FULL_SPEED
-    $(info "Using OTG_HS in FullSpeed mode")
-  endif
-else
-  $(info "Using OTG_FS")
-endif
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=shadow -Wno-error=cast-align
-
-SRC_C += \
-	src/portable/st/synopsys/dcd_synopsys.c \
-	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c
-
-INC += \
-  $(TOP)/$(BOARD_PATH) \
-	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-	$(TOP)/$(ST_CMSIS)/Include \
-	$(TOP)/$(ST_HAL_DRIVER)/Inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM7/r0p1
diff --git a/tinyusb/hw/bsp/stm32h7/boards/stm32h743eval/board.h b/tinyusb/hw/bsp/stm32h7/boards/stm32h743eval/board.h
deleted file mode 100755
index ab263d2b..00000000
--- a/tinyusb/hw/bsp/stm32h7/boards/stm32h743eval/board.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define LED_PORT              GPIOA
-#define LED_PIN               GPIO_PIN_4
-#define LED_STATE_ON          1
-
-// Tamper push-button
-#define BUTTON_PORT           GPIOC
-#define BUTTON_PIN            GPIO_PIN_13
-#define BUTTON_STATE_ACTIVE   0
-
-// Need to change jumper setting J7 and J8 from RS-232 to STLink
-#define UART_DEV              USART1
-#define UART_CLK_EN           __HAL_RCC_USART1_CLK_ENABLE
-#define UART_GPIO_PORT        GPIOB
-#define UART_GPIO_AF          GPIO_AF4_USART1
-#define UART_TX_PIN           GPIO_PIN_14
-#define UART_RX_PIN           GPIO_PIN_15
-
-// VBUS Sense detection
-#define OTG_FS_VBUS_SENSE     1
-#define OTG_HS_VBUS_SENSE     0
-
-//--------------------------------------------------------------------+
-// RCC Clock
-//--------------------------------------------------------------------+
-static inline void board_stm32h7_clock_init(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
-
-  /*!< Supply configuration update enable */
-  HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
-
-  /* The voltage scaling allows optimizing the power consumption when the device is
-     clocked below the maximum system frequency, to update the voltage scaling value
-     regarding system frequency refer to product datasheet.  */
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-  while ((PWR->D3CR & (PWR_D3CR_VOSRDY)) != PWR_D3CR_VOSRDY) {}
-
-  /* Enable HSE Oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
-  RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-
-  /* PLL1 for System Clock */
-  RCC_OscInitStruct.PLL.PLLM = 5;
-  RCC_OscInitStruct.PLL.PLLN = 160;
-  RCC_OscInitStruct.PLL.PLLFRACN = 0;
-  RCC_OscInitStruct.PLL.PLLP = 2;
-  RCC_OscInitStruct.PLL.PLLR = 2;
-  RCC_OscInitStruct.PLL.PLLQ = 4;
-
-  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM;
-  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* PLL3 for USB Clock */
-  PeriphClkInitStruct.PLL3.PLL3M = 25;
-  PeriphClkInitStruct.PLL3.PLL3N = 336;
-  PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
-  PeriphClkInitStruct.PLL3.PLL3P = 2;
-  PeriphClkInitStruct.PLL3.PLL3R = 2;
-  PeriphClkInitStruct.PLL3.PLL3Q = 7;
-
-  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
-  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3;
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
-
-  /* Select PLL as system clock source and configure  bus clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | \
-  RCC_CLOCKTYPE_PCLK2  | RCC_CLOCKTYPE_D3PCLK1);
-
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
-  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
-
-  /*activate CSI clock mondatory for I/O Compensation Cell*/
-  __HAL_RCC_CSI_ENABLE() ;
-
-  /* Enable SYSCFG clock mondatory for I/O Compensation Cell */
-  __HAL_RCC_SYSCFG_CLK_ENABLE() ;
-
-  /* Enables the I/O Compensation Cell */
-  HAL_EnableCompensationCell();
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif
diff --git a/tinyusb/hw/bsp/stm32h7/boards/stm32h743eval/board.mk b/tinyusb/hw/bsp/stm32h7/boards/stm32h743eval/board.mk
deleted file mode 100755
index 96d14a79..00000000
--- a/tinyusb/hw/bsp/stm32h7/boards/stm32h743eval/board.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-CFLAGS += -DSTM32H743xx -DHSE_VALUE=25000000
-
-# Default is Highspeed port
-PORT ?= 1
-
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s
-LD_FILE = $(BOARD_PATH)/stm32h743xx_flash.ld
-
-# For flash-jlink target
-JLINK_DEVICE = stm32h743xi
-
-# flash target using on-board stlink
-flash: flash-stlink
diff --git a/tinyusb/hw/bsp/stm32h7/boards/stm32h743eval/stm32h743xx_flash.ld b/tinyusb/hw/bsp/stm32h7/boards/stm32h743eval/stm32h743xx_flash.ld
deleted file mode 100755
index 59b9ff4d..00000000
--- a/tinyusb/hw/bsp/stm32h7/boards/stm32h743eval/stm32h743xx_flash.ld
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
-*****************************************************************************
-**
-
-**  File        : LinkerScript.ld
-**
-**  Abstract    : Linker script for STM32H743XIHx Device with
-**                2048KByte FLASH, 128KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-**  (c)Copyright Ac6.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Ac6 permit registered System Workbench for MCU users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the System Workbench for MCU toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20020000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-DTCMRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K
-RAM_D1 (xrw)      : ORIGIN = 0x24000000, LENGTH = 512K
-RAM_D2 (xrw)      : ORIGIN = 0x30000000, LENGTH = 288K
-RAM_D3 (xrw)      : ORIGIN = 0x38000000, LENGTH = 64K
-ITCMRAM (xrw)      : ORIGIN = 0x00000000, LENGTH = 64K
-FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 2048K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >DTCMRAM AT> FLASH
-
-  
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >DTCMRAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >DTCMRAM
-
-  
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
-
-
diff --git a/tinyusb/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h b/tinyusb/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h
deleted file mode 100755
index 3a31783a..00000000
--- a/tinyusb/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define LED_PORT              GPIOB
-#define LED_PIN               GPIO_PIN_0
-#define LED_STATE_ON          1
-
-#define BUTTON_PORT           GPIOC
-#define BUTTON_PIN            GPIO_PIN_13
-#define BUTTON_STATE_ACTIVE   1
-
-#define UART_DEV              USART3
-#define UART_CLK_EN           __HAL_RCC_USART3_CLK_ENABLE
-#define UART_GPIO_PORT        GPIOD
-#define UART_GPIO_AF          GPIO_AF7_USART3
-#define UART_TX_PIN           GPIO_PIN_8
-#define UART_RX_PIN           GPIO_PIN_9
-
-// VBUS Sense detection
-#define OTG_FS_VBUS_SENSE     1
-#define OTG_HS_VBUS_SENSE     0
-
-//--------------------------------------------------------------------+
-// RCC Clock
-//--------------------------------------------------------------------+
-static inline void board_stm32h7_clock_init(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* The PWR block is always enabled on the H7 series- there is no clock
-     enable. For now, use the default VOS3 scale mode (lowest) and limit clock
-     frequencies to avoid potential current draw problems from bus
-     power when using the max clock speeds throughout the chip. */
-
-  /* Enable HSE Oscillator and activate PLL1 with HSE as source */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
-  RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
-  RCC_OscInitStruct.PLL.PLLN = 336;
-  RCC_OscInitStruct.PLL.PLLP = 2;
-  RCC_OscInitStruct.PLL.PLLQ = 7;
-  RCC_OscInitStruct.PLL.PLLR = 2; /* Unused */
-  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_0;
-  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM;
-  RCC_OscInitStruct.PLL.PLLFRACN = 0;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | \
-    RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | \
-    RCC_CLOCKTYPE_D3PCLK1);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1;
-
-  /* Unlike on the STM32F4 family, it appears the maximum APB frequencies are
-     device-dependent- 120 MHz for this board according to Figure 2 of
-     the datasheet. Dividing by half will be safe for now. */
-  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
-  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
-
-  /* 4 wait states required for 168MHz and VOS3. */
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
-
-  /* Like on F4, on H7, USB's actual peripheral clock and bus clock are
-     separate. However, the main system PLL (PLL1) doesn't have a direct
-     connection to the USB peripheral clock to generate 48 MHz, so we do this
-     dance. This will connect PLL1's Q output to the USB peripheral clock. */
-  RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct;
-
-  RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
-  RCC_PeriphCLKInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
-  HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct);
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif
diff --git a/tinyusb/hw/bsp/stm32h7/boards/stm32h743nucleo/board.mk b/tinyusb/hw/bsp/stm32h7/boards/stm32h743nucleo/board.mk
deleted file mode 100755
index fc670fe7..00000000
--- a/tinyusb/hw/bsp/stm32h7/boards/stm32h743nucleo/board.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-CFLAGS += -DSTM32H743xx -DHSE_VALUE=8000000
-
-# Default is FulSpeed port
-PORT ?= 0
-
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s
-LD_FILE = $(BOARD_PATH)/stm32h743xx_flash.ld
-
-# For flash-jlink target
-JLINK_DEVICE = stm32h743zi
-
-# flash target using on-board stlink
-flash: flash-stlink
diff --git a/tinyusb/hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld b/tinyusb/hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld
deleted file mode 100755
index 59b9ff4d..00000000
--- a/tinyusb/hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
-*****************************************************************************
-**
-
-**  File        : LinkerScript.ld
-**
-**  Abstract    : Linker script for STM32H743XIHx Device with
-**                2048KByte FLASH, 128KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-**  (c)Copyright Ac6.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Ac6 permit registered System Workbench for MCU users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the System Workbench for MCU toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20020000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-DTCMRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K
-RAM_D1 (xrw)      : ORIGIN = 0x24000000, LENGTH = 512K
-RAM_D2 (xrw)      : ORIGIN = 0x30000000, LENGTH = 288K
-RAM_D3 (xrw)      : ORIGIN = 0x38000000, LENGTH = 64K
-ITCMRAM (xrw)      : ORIGIN = 0x00000000, LENGTH = 64K
-FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 2048K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >DTCMRAM AT> FLASH
-
-  
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >DTCMRAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >DTCMRAM
-
-  
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
-
-
diff --git a/tinyusb/hw/bsp/stm32h7/boards/stm32h745disco/board.h b/tinyusb/hw/bsp/stm32h7/boards/stm32h745disco/board.h
deleted file mode 100755
index 30a7a9ff..00000000
--- a/tinyusb/hw/bsp/stm32h7/boards/stm32h745disco/board.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define LED_PORT              GPIOJ
-#define LED_PIN               GPIO_PIN_2
-#define LED_STATE_ON          1
-
-// Blue push-button
-#define BUTTON_PORT           GPIOC
-#define BUTTON_PIN            GPIO_PIN_13
-#define BUTTON_STATE_ACTIVE   1
-
-// UART
-#define UART_DEV              USART3
-#define UART_CLK_EN           __HAL_RCC_USART3_CLK_ENABLE
-#define UART_GPIO_PORT        GPIOB
-#define UART_GPIO_AF          GPIO_AF7_USART3
-#define UART_TX_PIN           GPIO_PIN_10
-#define UART_RX_PIN           GPIO_PIN_11
-
-// VBUS Sense detection
-#define OTG_FS_VBUS_SENSE     1
-#define OTG_HS_VBUS_SENSE     0
-
-//--------------------------------------------------------------------+
-// RCC Clock
-//--------------------------------------------------------------------+
-static inline void board_stm32h7_clock_init(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
-
-  /*!< Supply configuration update enable */
-  /* For STM32H750XB, use "HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);" */
-  HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY);
-
-  /* The voltage scaling allows optimizing the power consumption when the
-     device is clocked below the maximum system frequency, to update the
-     voltage scaling value regarding system frequency refer to product
-     datasheet.  */
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-  while ((PWR->D3CR & (PWR_D3CR_VOSRDY)) != PWR_D3CR_VOSRDY) {}
-
-  /* Enable HSE Oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
-  RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
-  RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-
-  /* PLL1 for System Clock */
-  RCC_OscInitStruct.PLL.PLLM = 5;
-  RCC_OscInitStruct.PLL.PLLN = 160;
-  RCC_OscInitStruct.PLL.PLLFRACN = 0;
-  RCC_OscInitStruct.PLL.PLLP = 2;
-  RCC_OscInitStruct.PLL.PLLR = 2;
-  RCC_OscInitStruct.PLL.PLLQ = 4;
-
-  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM;
-  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* PLL3 for USB Clock */
-  PeriphClkInitStruct.PLL3.PLL3M = 25;
-  PeriphClkInitStruct.PLL3.PLL3N = 336;
-  PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
-  PeriphClkInitStruct.PLL3.PLL3P = 2;
-  PeriphClkInitStruct.PLL3.PLL3R = 2;
-  PeriphClkInitStruct.PLL3.PLL3Q = 7;
-
-  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
-  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3;
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
-
-  /* Select PLL as system clock source and configure  bus clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | \
-  RCC_CLOCKTYPE_PCLK2  | RCC_CLOCKTYPE_D3PCLK1);
-
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
-  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
-
-  /*activate CSI clock mondatory for I/O Compensation Cell*/
-  __HAL_RCC_CSI_ENABLE() ;
-
-  /* Enable SYSCFG clock mondatory for I/O Compensation Cell */
-  __HAL_RCC_SYSCFG_CLK_ENABLE() ;
-
-  /* Enables the I/O Compensation Cell */
-  HAL_EnableCompensationCell();
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif
diff --git a/tinyusb/hw/bsp/stm32h7/boards/stm32h745disco/board.mk b/tinyusb/hw/bsp/stm32h7/boards/stm32h745disco/board.mk
deleted file mode 100755
index 384065bd..00000000
--- a/tinyusb/hw/bsp/stm32h7/boards/stm32h745disco/board.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# STM32H745I-DISCO uses OTG_FS
-# FIXME: Reset enumerates, un/replug USB plug does not enumerate
-
-CFLAGS += -DSTM32H745xx -DCORE_CM7 -DHSE_VALUE=25000000
-
-# Default is FulSpeed port
-PORT ?= 0
-
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h745xx.s
-LD_FILE = $(ST_CMSIS)/Source/Templates/gcc/linker/stm32h745xx_flash_CM7.ld
-
-# For flash-jlink target
-JLINK_DEVICE = stm32h745xi_m7
-
-# flash target using on-board stlink
-flash: flash-stlink
-
diff --git a/tinyusb/hw/bsp/stm32h7/family.c b/tinyusb/hw/bsp/stm32h7/family.c
deleted file mode 100755
index 2cbd8741..00000000
--- a/tinyusb/hw/bsp/stm32h7/family.c
+++ /dev/null
@@ -1,287 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2019
- *    William D. Jones (thor0505@comcast.net),
- *    Ha Thach (tinyusb.org)
- *    Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "stm32h7xx_hal.h"
-#include "bsp/board.h"
-#include "board.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-
-// Despite being call USB2_OTG
-// OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port
-void OTG_FS_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-// Despite being call USB2_OTG
-// OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port
-void OTG_HS_IRQHandler(void)
-{
-  tud_int_handler(1);
-}
-
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-UART_HandleTypeDef UartHandle;
-
-void board_init(void)
-{
-  board_stm32h7_clock_init();
-
-  // Enable All GPIOs clocks
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOB_CLK_ENABLE(); // USB ULPI NXT
-  __HAL_RCC_GPIOC_CLK_ENABLE(); // USB ULPI NXT
-  __HAL_RCC_GPIOD_CLK_ENABLE();
-  __HAL_RCC_GPIOE_CLK_ENABLE();
-  __HAL_RCC_GPIOE_CLK_ENABLE();
-  __HAL_RCC_GPIOG_CLK_ENABLE();
-  __HAL_RCC_GPIOH_CLK_ENABLE(); // USB ULPI NXT
-  __HAL_RCC_GPIOI_CLK_ENABLE(); // USB ULPI NXT
-  __HAL_RCC_GPIOJ_CLK_ENABLE();
-
-  // Enable UART Clock
-  UART_CLK_EN();
-
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-
-#if CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-  NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-  
-  GPIO_InitTypeDef  GPIO_InitStruct;
-
-  // LED
-  GPIO_InitStruct.Pin   = LED_PIN;
-  GPIO_InitStruct.Mode  = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull  = GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
-
-  // Button
-  GPIO_InitStruct.Pin   = BUTTON_PIN;
-  GPIO_InitStruct.Mode  = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull  = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
-
-  // Uart
-  GPIO_InitStruct.Pin       = UART_TX_PIN | UART_RX_PIN;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_PULLUP;
-  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_VERY_HIGH;
-  GPIO_InitStruct.Alternate = UART_GPIO_AF;
-  HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
-
-  UartHandle.Instance        = UART_DEV;
-  UartHandle.Init.BaudRate   = CFG_BOARD_UART_BAUDRATE;
-  UartHandle.Init.WordLength = UART_WORDLENGTH_8B;
-  UartHandle.Init.StopBits   = UART_STOPBITS_1;
-  UartHandle.Init.Parity     = UART_PARITY_NONE;
-  UartHandle.Init.HwFlowCtl  = UART_HWCONTROL_NONE;
-  UartHandle.Init.Mode       = UART_MODE_TX_RX;
-  UartHandle.Init.OverSampling = UART_OVERSAMPLING_16;
-  HAL_UART_Init(&UartHandle);
-
-#if BOARD_DEVICE_RHPORT_NUM == 0
-  // Despite being call USB2_OTG
-  // OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port
-  // PA9 VUSB, PA10 ID, PA11 DM, PA12 DP
-
-  /* Configure DM DP Pins */
-  GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* This for ID line debug */
-  GPIO_InitStruct.Pin = GPIO_PIN_10;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  // https://community.st.com/s/question/0D50X00009XkYZLSA3/stm32h7-nucleo-usb-fs-cdc
-  // TODO: Board init actually works fine without this line.
-  HAL_PWREx_EnableUSBVoltageDetector();
-  __HAL_RCC_USB2_OTG_FS_CLK_ENABLE();
-
-#if OTG_FS_VBUS_SENSE
-  /* Configure VBUS Pin */
-  GPIO_InitStruct.Pin = GPIO_PIN_9;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-#else
-  // Disable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
-
-  // B-peripheral session valid override enable
-  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
-  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
-#endif // vbus sense
-
-#elif BOARD_DEVICE_RHPORT_NUM == 1
-  // Despite being call USB2_OTG
-  // OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port
-
-  /* CLK */
-  GPIO_InitStruct.Pin = GPIO_PIN_5;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* D0 */
-  GPIO_InitStruct.Pin = GPIO_PIN_3;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* D1 D2 D3 D4 D5 D6 D7 */
-  GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_5 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
-  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
-
-  /* STP */
-  GPIO_InitStruct.Pin = GPIO_PIN_0;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
-  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
-
-  /* NXT */
-  GPIO_InitStruct.Pin = GPIO_PIN_4;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
-  HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
-
-  /* DIR */
-  GPIO_InitStruct.Pin = GPIO_PIN_11;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
-  HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
-
-  // Enable USB HS & ULPI Clocks
-  __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE();
-  __HAL_RCC_USB1_OTG_HS_CLK_ENABLE();
-
-#if OTG_HS_VBUS_SENSE
-  #error OTG HS VBUS Sense enabled is not implemented
-#else
-  // No VBUS sense
-  USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
-
-  // B-peripheral session valid override enable
-  USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
-  USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
-#endif
-
-  // Force device mode
-  USB_OTG_HS->GUSBCFG &= ~USB_OTG_GUSBCFG_FHMOD;
-  USB_OTG_HS->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
-
-  HAL_PWREx_EnableUSBVoltageDetector();
-#endif // rhport = 1
-
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return (BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN)) ? 1 : 0;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  HAL_UART_Transmit(&UartHandle, (uint8_t*) buf, len, 0xffff);
-  return len;
-}
-
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-
-void HardFault_Handler (void)
-{
-  asm("bkpt");
-}
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
-}
diff --git a/tinyusb/hw/bsp/stm32h7/family.mk b/tinyusb/hw/bsp/stm32h7/family.mk
deleted file mode 100755
index e35e7561..00000000
--- a/tinyusb/hw/bsp/stm32h7/family.mk
+++ /dev/null
@@ -1,51 +0,0 @@
-UF2_FAMILY_ID = 0x6db66082
-ST_FAMILY = h7
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
-ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m7 \
-  -mfloat-abi=hard \
-  -mfpu=fpv5-d16 \
-  -nostdlib -nostartfiles \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32H7 \
-	-DBOARD_DEVICE_RHPORT_NUM=$(PORT)
-
-ifeq ($(PORT), 1)
-  CFLAGS += -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED
-  $(info "PORT1 High Speed")
-else
-  $(info "PORT0 Full Speed")
-endif
-
-# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
-
-# All source paths should be relative to the top level.
-SRC_C += \
-	src/portable/st/synopsys/dcd_synopsys.c \
-	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-	$(TOP)/$(ST_CMSIS)/Include \
-	$(TOP)/$(ST_HAL_DRIVER)/Inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM7/r0p1
-
diff --git a/tinyusb/hw/bsp/stm32h7/stm32h7xx_hal_conf.h b/tinyusb/hw/bsp/stm32h7/stm32h7xx_hal_conf.h
deleted file mode 100755
index a7cc6d82..00000000
--- a/tinyusb/hw/bsp/stm32h7/stm32h7xx_hal_conf.h
+++ /dev/null
@@ -1,483 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32h7xx_hal_conf_template.h
-  * @brief   HAL configuration template file. 
-  *          This file should be copied to the application folder and renamed
-  *          to stm32h7xx_hal_conf.h.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_CONF_H
-#define __STM32H7xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-#define HAL_ADC_MODULE_ENABLED
-/* #define HAL_CEC_MODULE_ENABLED */
-/* #define HAL_COMP_MODULE_ENABLED */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_CRC_MODULE_ENABLED */
-/* #define HAL_CRYP_MODULE_ENABLED */
-/* #define HAL_DAC_MODULE_ENABLED */
-/* #define HAL_DCMI_MODULE_ENABLED */
-/* #define HAL_DFSDM_MODULE_ENABLED */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED */
-/* #define HAL_ETH_MODULE_ENABLED */
-/* #define HAL_EXTI_MODULE_ENABLED */
-/* #define HAL_FDCAN_MODULE_ENABLED */
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_HASH_MODULE_ENABLED */
-/* #define HAL_HCD_MODULE_ENABLED */
-/* #define HAL_HRTIM_MODULE_ENABLED */
-/* #define HAL_HSEM_MODULE_ENABLED */
-/* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED */
-/* #define HAL_IRDA_MODULE_ENABLED */
-/* #define HAL_IWDG_MODULE_ENABLED */
-/* #define HAL_JPEG_MODULE_ENABLED */
-/* #define HAL_LPTIM_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED */
-/* #define HAL_MDIOS_MODULE_ENABLED */
-/* #define HAL_MDMA_MODULE_ENABLED */
-/* #define HAL_MMC_MODULE_ENABLED */
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_OPAMP_MODULE_ENABLED */
-/* #define HAL_PCD_MODULE_ENABLED */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED */
-/* #define HAL_RAMECC_MODULE_ENABLED */
-#define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RNG_MODULE_ENABLED */
-/* #define HAL_RTC_MODULE_ENABLED */
-/* #define HAL_SAI_MODULE_ENABLED */
-/* #define HAL_SD_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_SMBUS_MODULE_ENABLED */
-/* #define HAL_SPDIFRX_MODULE_ENABLED */
-#define HAL_SPI_MODULE_ENABLED
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SWPMI_MODULE_ENABLED */
-/* #define HAL_TIM_MODULE_ENABLED */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED */
-
-/* ########################## Oscillator Values adaptation ####################*/
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-//#define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
-#error HSE_VALUE is not defined
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal  oscillator (CSI) default value.
-  *        This value is the default CSI value after Reset.
-  */
-#if !defined  (CSI_VALUE)
-  #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* CSI_VALUE */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  *        This value is used by the UART, RTC HAL module to compute the system frequency
-  */
-#if !defined  (LSE_VALUE)
-  #define LSE_VALUE    ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
-#endif /* LSE_VALUE */
-
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-#if !defined  (LSI_VALUE)
-  #define LSI_VALUE  ((uint32_t)32000)      /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                              The real value may vary depending on the variations
-                                              in voltage and temperature.*/
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the External clock in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x0F) /*!< tick interrupt priority */
-#define  USE_RTOS                     0
-#define  USE_SD_TRANSCEIVER           1U               /*!< use uSD Transceiver */
-#define  USE_SPI_CRC                  1U               /*!< use CRC in SPI */
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS     0U /* ADC register callback disabled     */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS     0U /* CEC register callback disabled     */
-#define  USE_HAL_COMP_REGISTER_CALLBACKS    0U /* COMP register callback disabled    */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS    0U /* CRYP register callback disabled    */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS     0U /* DAC register callback disabled     */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS    0U /* DCMI register callback disabled    */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS   0U /* DFSDM register callback disabled   */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS   0U /* DMA2D register callback disabled   */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS     0U /* DSI register callback disabled     */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS     0U /* ETH register callback disabled     */
-#define  USE_HAL_FDCAN_REGISTER_CALLBACKS   0U /* FDCAN register callback disabled   */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS    0U /* NAND register callback disabled    */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS     0U /* NOR register callback disabled     */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS   0U /* SDRAM register callback disabled   */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS    0U /* SRAM register callback disabled    */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS    0U /* HASH register callback disabled    */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS     0U /* HCD register callback disabled     */
-#define  USE_HAL_HRTIM_REGISTER_CALLBACKS   0U /* HRTIM register callback disabled   */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS     0U /* I2C register callback disabled     */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS     0U /* I2S register callback disabled     */
-#define  USE_HAL_JPEG_REGISTER_CALLBACKS    0U /* JPEG register callback disabled    */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS   0U /* LPTIM register callback disabled   */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS    0U /* LTDC register callback disabled    */
-#define  USE_HAL_MDIOS_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
-#define  USE_HAL_OPAMP_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS     0U /* PCD register callback disabled     */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS    0U /* QSPI register callback disabled    */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS     0U /* RNG register callback disabled     */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS     0U /* RTC register callback disabled     */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS     0U /* SAI register callback disabled     */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS   0U /* SMBUS register callback disabled   */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS     0U /* SPI register callback disabled     */
-#define  USE_HAL_SWPMI_REGISTER_CALLBACKS   0U /* SWPMI register callback disabled   */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS     0U /* TIM register callback disabled     */
-#define  USE_HAL_UART_REGISTER_CALLBACKS    0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS   0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS    0U /* WWDG register callback disabled    */
-
-/* ########################### Ethernet Configuration ######################### */
-#define ETH_TX_DESC_CNT         4  /* number of Ethernet Tx DMA descriptors */
-#define ETH_RX_DESC_CNT         4  /* number of Ethernet Rx DMA descriptors */
-
-#define ETH_MAC_ADDR0    ((uint8_t)0x02)
-#define ETH_MAC_ADDR1    ((uint8_t)0x00)
-#define ETH_MAC_ADDR2    ((uint8_t)0x00)
-#define ETH_MAC_ADDR3    ((uint8_t)0x00)
-#define ETH_MAC_ADDR4    ((uint8_t)0x00)
-#define ETH_MAC_ADDR5    ((uint8_t)0x00)
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32h7xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32h7xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32h7xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_MDMA_MODULE_ENABLED
- #include "stm32h7xx_hal_mdma.h"
-#endif /* HAL_MDMA_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
-  #include "stm32h7xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32h7xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32h7xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
-  #include "stm32h7xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
-  #include "stm32h7xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32h7xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32h7xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32h7xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32h7xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_FDCAN_MODULE_ENABLED
-  #include "stm32h7xx_hal_fdcan.h"
-#endif /* HAL_FDCAN_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
-  #include "stm32h7xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_COMP_MODULE_ENABLED
-  #include "stm32h7xx_hal_comp.h"
-#endif /* HAL_COMP_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32h7xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32h7xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32h7xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32h7xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_HRTIM_MODULE_ENABLED
-  #include "stm32h7xx_hal_hrtim.h"
-#endif /* HAL_HRTIM_MODULE_ENABLED */
-
-#ifdef HAL_HSEM_MODULE_ENABLED
-  #include "stm32h7xx_hal_hsem.h"
-#endif /* HAL_HSEM_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32h7xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32h7xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32h7xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32h7xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32h7xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32h7xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_JPEG_MODULE_ENABLED
- #include "stm32h7xx_hal_jpeg.h"
-#endif /* HAL_JPEG_MODULE_ENABLED */
-
-#ifdef HAL_MDIOS_MODULE_ENABLED
- #include "stm32h7xx_hal_mdios.h"
-#endif /* HAL_MDIOS_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32h7xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
-#include "stm32h7xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
-#include "stm32h7xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_OPAMP_MODULE_ENABLED
-#include "stm32h7xx_hal_opamp.h"
-#endif /* HAL_OPAMP_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32h7xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32h7xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_RAMECC_MODULE_ENABLED
- #include "stm32h7xx_hal_ramecc.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32h7xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32h7xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32h7xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32h7xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
- #include "stm32h7xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32h7xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32h7xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_SWPMI_MODULE_ENABLED
- #include "stm32h7xx_hal_swpmi.h"
-#endif /* HAL_SWPMI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32h7xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32h7xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32h7xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32h7xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32h7xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32h7xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32h7xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32h7xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32h7xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t *file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_CONF_H */
- 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tinyusb/hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld b/tinyusb/hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld
deleted file mode 100755
index 787418e0..00000000
--- a/tinyusb/hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
-*****************************************************************************
-**
-
-**  File        : LinkerScript.ld
-**
-**  Abstract    : Linker script for STM32L053C8Tx Device with
-**                64KByte FLASH, 8KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-**  (c)Copyright Ac6.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Ac6 permit registered System Workbench for MCU users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the System Workbench for MCU toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20002000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x200; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 64K
-RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 8K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-  
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
-
-
diff --git a/tinyusb/hw/bsp/stm32l0538disco/board.mk b/tinyusb/hw/bsp/stm32l0538disco/board.mk
deleted file mode 100755
index c46887f1..00000000
--- a/tinyusb/hw/bsp/stm32l0538disco/board.mk
+++ /dev/null
@@ -1,53 +0,0 @@
-ST_FAMILY = l0
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
-ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
-  -mfloat-abi=soft \
-  -nostdlib -nostartfiles \
-  -DSTM32L053xx \
-  -DCFG_EXAMPLE_MSC_READONLY \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32L0
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=maybe-uninitialized
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/STM32L053C8Tx_FLASH.ld
-
-SRC_C += \
-  src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
-  $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
-
-SRC_S += \
-  $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l053xx.s
-
-INC += \
-  $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-  $(TOP)/$(ST_CMSIS)/Include \
-  $(TOP)/$(ST_HAL_DRIVER)/Inc \
-  $(TOP)/hw/bsp/$(BOARD)
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
-
-# For flash-jlink target
-JLINK_DEVICE = STM32L053R8
-
-# Path to STM32 Cube Programmer CLI, should be added into system path 
-STM32Prog = STM32_Programmer_CLI
-
-# flash target using on-board stlink
-flash: $(BUILD)/$(PROJECT).elf
-	$(STM32Prog) --connect port=swd --write $< --go
diff --git a/tinyusb/hw/bsp/stm32l0538disco/stm32l0538disco.c b/tinyusb/hw/bsp/stm32l0538disco/stm32l0538disco.c
deleted file mode 100755
index f0f1d028..00000000
--- a/tinyusb/hw/bsp/stm32l0538disco/stm32l0538disco.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "../board.h"
-#include "stm32l0xx_hal.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-#define LED_PORT              GPIOA
-#define LED_PIN               GPIO_PIN_5
-#define LED_STATE_ON          1
-
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE   1
-
-/**
-  * @brief  System Clock Configuration
-  *         The system Clock is configured as follow:
-  *         HSI48 used as USB clock source
-  *              - System Clock source            = HSI
-  *              - HSI Frequency(Hz)              = 16000000
-  *              - SYSCLK(Hz)                     = 16000000
-  *              - HCLK(Hz)                       = 16000000
-  *              - AHB Prescaler                  = 1
-  *              - APB1 Prescaler                 = 1
-  *              - APB2 Prescaler                 = 1
-  *              - Flash Latency(WS)              = 0
-  *              - Main regulator output voltage  = Scale1 mode
-  * @param  None
-  * @retval None
-  */
-static void SystemClock_Config(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-  RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct;
-  static RCC_CRSInitTypeDef RCC_CRSInitStruct;
-
-  /* Enable HSI Oscillator to be used as System clock source
-     Enable HSI48 Oscillator to be used as USB clock source */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
-  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
-  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Select HSI48 as USB clock source */
-  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
-  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
-
-  /* Select HSI as system clock source and configure the HCLK, PCLK1 and PCLK2
-     clock dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
-
-  /*Configure the clock recovery system (CRS)**********************************/
-
-  /*Enable CRS Clock*/
-  __HAL_RCC_CRS_CLK_ENABLE();
-
-  /* Default Synchro Signal division factor (not divided) */
-  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
-  /* Set the SYNCSRC[1:0] bits according to CRS_Source value */
-  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
-  /* HSI48 is synchronized with USB SOF at 1KHz rate */
-  RCC_CRSInitStruct.ReloadValue =  __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
-  RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
-  /* Set the TRIM[5:0] to the default value*/
-  RCC_CRSInitStruct.HSI48CalibrationValue = 0x20;
-  /* Start automatic synchronization */
-  HAL_RCCEx_CRSConfig (&RCC_CRSInitStruct);
-}
-
-void board_init(void)
-{
-  SystemClock_Config();
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  //NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  GPIO_InitTypeDef  GPIO_InitStruct;
-
-  // LED
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  GPIO_InitStruct.Pin = LED_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
-
-  board_led_write(false);
-
-  // Button
-  //__HAL_RCC_GPIOA_CLK_ENABLE();
-  GPIO_InitStruct.Pin = BUTTON_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
-
-  // USB
-  /* Configure DM DP Pins */
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* Enable USB FS Clock */
-  __HAL_RCC_USB_CLK_ENABLE();
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-
-void HardFault_Handler (void)
-{
-  asm("bkpt");
-}
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
-}
diff --git a/tinyusb/hw/bsp/stm32l0538disco/stm32l0xx_hal_conf.h b/tinyusb/hw/bsp/stm32l0538disco/stm32l0xx_hal_conf.h
deleted file mode 100755
index 773b74e2..00000000
--- a/tinyusb/hw/bsp/stm32l0538disco/stm32l0xx_hal_conf.h
+++ /dev/null
@@ -1,331 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  *
-  * Copyright (c) 2016 STMicroelectronics International N.V. All rights reserved.
-  *
-  * Redistribution and use in source and binary forms, with or without 
-  * modification, are permitted, provided that the following conditions are met:
-  *
-  * 1. Redistribution of source code must retain the above copyright notice, 
-  *    this list of conditions and the following disclaimer.
-  * 2. Redistributions in binary form must reproduce the above copyright notice,
-  *    this list of conditions and the following disclaimer in the documentation
-  *    and/or other materials provided with the distribution.
-  * 3. Neither the name of STMicroelectronics nor the names of other 
-  *    contributors to this software may be used to endorse or promote products 
-  *    derived from this software without specific written permission.
-  * 4. This software, including modifications and/or derivative works of this 
-  *    software, must execute solely and exclusively on microcontroller or
-  *    microprocessor devices manufactured by or for STMicroelectronics.
-  * 5. Redistribution and use of this software other than as permitted under 
-  *    this license is void and will automatically terminate your rights under 
-  *    this license. 
-  *
-  * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" 
-  * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT 
-  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 
-  * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
-  * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT 
-  * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 
-  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 
-  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 
-  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_HAL_CONF_H
-#define __STM32L0xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-#define HAL_MODULE_ENABLED  
-// #define HAL_ADC_MODULE_ENABLED
-/* #define HAL_COMP_MODULE_ENABLED */ 
-/* #define HAL_CRC_MODULE_ENABLED */  
-/* #define HAL_CRYP_MODULE_ENABLED */ 
-/* #define HAL_DAC_MODULE_ENABLED */   
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_FIREWALL_MODULE_ENABLED */
-#define HAL_FLASH_MODULE_ENABLED 
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED */   
-/* #define HAL_IWDG_MODULE_ENABLED */
-/* #define HAL_LCD_MODULE_ENABLED */ 
-/* #define HAL_LPTIM_MODULE_ENABLED */
-#define HAL_PWR_MODULE_ENABLED  
-#define HAL_RCC_MODULE_ENABLED 
-//#define HAL_RNG_MODULE_ENABLED
-/* #define HAL_RTC_MODULE_ENABLED */
-//#define HAL_SPI_MODULE_ENABLED
-/* #define HAL_TIM_MODULE_ENABLED */   
-/* #define HAL_TSC_MODULE_ENABLED */
-/* #define HAL_UART_MODULE_ENABLED */ 
-/* #define HAL_USART_MODULE_ENABLED */ 
-/* #define HAL_IRDA_MODULE_ENABLED */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_SMBUS_MODULE_ENABLED */   
-/* #define HAL_WWDG_MODULE_ENABLED */ 
-//#define HAL_PCD_MODULE_ENABLED
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_PCD_MODULE_ENABLED */
-
-
-/* ########################## Oscillator Values adaptation ####################*/
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal Multiple Speed oscillator (MSI) default value.
-  *        This value is the default MSI range value after Reset.
-  */
-#if !defined  (MSI_VALUE)
-  #define MSI_VALUE    ((uint32_t)2097152U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal High Speed oscillator for USB (HSI48) value.
-  */
-#if !defined  (HSI48_VALUE) 
-#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB in Hz.
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-#endif /* HSI48_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  ((uint32_t)37000U)       /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.*/
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  *        This value is used by the UART, RTC HAL module to compute the system frequency
-  */
-#if !defined  (LSE_VALUE)
-  #define LSE_VALUE    ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
-#endif /* LSE_VALUE */
-
-/**
-  * @brief Time out for LSE start up value in ms.
-  */
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-   
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */ 
-#define  TICK_INT_PRIORITY            ((uint32_t)0U)    /*!< tick interrupt priority */           
-#define  USE_RTOS                     0U     
-#define  PREFETCH_ENABLE              1U              
-#define  PREREAD_ENABLE               1U
-#define  BUFFER_CACHE_DISABLE         0U
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
- * Activated: CRC code is present inside driver
- * Deactivated: CRC code cleaned from driver
- */
-
-#define USE_SPI_CRC                   1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32l0xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32l0xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32l0xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-   
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32l0xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32l0xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_COMP_MODULE_ENABLED
-  #include "stm32l0xx_hal_comp.h"
-#endif /* HAL_COMP_MODULE_ENABLED */
-   
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32l0xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32l0xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32l0xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_FIREWALL_MODULE_ENABLED
-  #include "stm32l0xx_hal_firewall.h"
-#endif /* HAL_FIREWALL_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32l0xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
- 
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32l0xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32l0xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32l0xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LCD_MODULE_ENABLED
- #include "stm32l0xx_hal_lcd.h"
-#endif /* HAL_LCD_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
-#include "stm32l0xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-   
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32l0xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32l0xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
-  #include "stm32l0xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32l0xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32l0xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_TSC_MODULE_ENABLED
-  #include "stm32l0xx_hal_tsc.h"
-#endif /* HAL_TSC_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32l0xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32l0xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32l0xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32l0xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32l0xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32l0xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32l0xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t *file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_HAL_CONF_H */
- 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tinyusb/hw/bsp/stm32l476disco/STM32L476VGTx_FLASH.ld b/tinyusb/hw/bsp/stm32l476disco/STM32L476VGTx_FLASH.ld
deleted file mode 100755
index 98f468ac..00000000
--- a/tinyusb/hw/bsp/stm32l476disco/STM32L476VGTx_FLASH.ld
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
-*****************************************************************************
-**
-
-**  File        : LinkerScript.ld
-**
-**  Abstract    : Linker script for STM32L476VGTx Device with
-**                1024KByte FLASH, 96KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-**  (c)Copyright Ac6.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Ac6 permit registered System Workbench for MCU users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the System Workbench for MCU toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20018000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x500;      /* required amount of heap  */
-_Min_Stack_Size = 0x1000; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 1024K
-RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 96K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(8);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(8);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(8);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(8);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(8);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(8);
-  } >FLASH
-
-  .ARM.extab   : 
-  { 
-  . = ALIGN(8);
-  *(.ARM.extab* .gnu.linkonce.armextab.*)
-  . = ALIGN(8);
-  } >FLASH
-  .ARM : {
-	. = ALIGN(8);
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-	. = ALIGN(8);
-  } >FLASH
-
-  .preinit_array     :
-  {
-	. = ALIGN(8);
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-	. = ALIGN(8);
-  } >FLASH
-  
-  .init_array :
-  {
-	. = ALIGN(8);
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-	. = ALIGN(8);
-  } >FLASH
-  .fini_array :
-  {
-	. = ALIGN(8);
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-	. = ALIGN(8);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
-  {
-    . = ALIGN(8);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(8);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-  
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
-
-
diff --git a/tinyusb/hw/bsp/stm32l476disco/board.mk b/tinyusb/hw/bsp/stm32l476disco/board.mk
deleted file mode 100755
index 28824efd..00000000
--- a/tinyusb/hw/bsp/stm32l476disco/board.mk
+++ /dev/null
@@ -1,56 +0,0 @@
-ST_FAMILY = l4
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
-ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib -nostartfiles \
-  -DSTM32L476xx \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32L4
-
-# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/STM32L476VGTx_FLASH.ld
-
-SRC_C += \
-	src/portable/st/synopsys/dcd_synopsys.c \
-	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c
-
-SRC_S += \
-	$(ST_CMSIS)/Source/Templates/gcc/startup_stm32l476xx.s
-
-INC += \
-	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-	$(TOP)/$(ST_CMSIS)/Include \
-	$(TOP)/$(ST_HAL_DRIVER)/Inc \
-	$(TOP)/hw/bsp/$(BOARD)
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = stm32l476vg
-
-# Path to STM32 Cube Programmer CLI, should be added into system path
-STM32Prog = STM32_Programmer_CLI
-
-# flash target using on-board stlink
-flash: $(BUILD)/$(PROJECT).elf
-	$(STM32Prog) --connect port=swd --write $< --go
diff --git a/tinyusb/hw/bsp/stm32l476disco/stm32l476disco.c b/tinyusb/hw/bsp/stm32l476disco/stm32l476disco.c
deleted file mode 100755
index b1884668..00000000
--- a/tinyusb/hw/bsp/stm32l476disco/stm32l476disco.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "../board.h"
-
-#include "stm32l4xx_hal.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void OTG_FS_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-#define LED_PORT              GPIOB
-#define LED_PIN               GPIO_PIN_2
-#define LED_STATE_ON          1
-
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE   1
-
-
-// enable all LED, Button, Uart, USB clock
-static void all_rcc_clk_enable(void)
-{
-  __HAL_RCC_GPIOA_CLK_ENABLE(); // USB D+, D-, Button
-  __HAL_RCC_GPIOB_CLK_ENABLE(); // LED
-  __HAL_RCC_GPIOC_CLK_ENABLE(); // VBUS pin
-}
-
-
-/**
-  * @brief  System Clock Configuration
-  *         The system Clock is configured as follow :
-  *
-  *         If define USB_USE_LSE_MSI_CLOCK enabled:
-  *            System Clock source            = PLL (MSI)
-  *            SYSCLK(Hz)                     = 80000000
-  *            HCLK(Hz)                       = 80000000
-  *            AHB Prescaler                  = 1
-  *            APB1 Prescaler                 = 1
-  *            APB2 Prescaler                 = 2
-  *            MSI Frequency(Hz)              = 4800000
-  *            LSE Frequency(Hz)              = 32768
-  *            PLL_M                          = 6
-  *            PLL_N                          = 40
-  *            PLL_P                          = 7
-  *            PLL_Q                          = 4
-  *            PLL_R                          = 4
-  *            Flash Latency(WS)              = 4
-  * @param  None
-  * @retval None
-  */
-static void SystemClock_Config(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
-
-  /* Enable the LSE Oscillator */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
-  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Enable the CSS interrupt in case LSE signal is corrupted or not present */
-  HAL_RCCEx_DisableLSECSS();
-
-  /* Set tick interrupt priority, default HAL value is intentionally invalid
-     and that prevents PLL initialization in HAL_RCC_OscConfig() */
-  HAL_InitTick((1UL << __NVIC_PRIO_BITS) - 1UL);
-
-  /* Enable MSI Oscillator and activate PLL with MSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_MSI;
-  RCC_OscInitStruct.MSIState            = RCC_MSI_ON;
-  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.MSIClockRange       = RCC_MSIRANGE_11;
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_MSI;
-  RCC_OscInitStruct.PLL.PLLM            = 6;
-  RCC_OscInitStruct.PLL.PLLN            = 40;
-  RCC_OscInitStruct.PLL.PLLP            = 7;
-  RCC_OscInitStruct.PLL.PLLQ            = 4;
-  RCC_OscInitStruct.PLL.PLLR            = 4;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Enable MSI Auto-calibration through LSE */
-  HAL_RCCEx_EnableMSIPLLMode();
-
-  /* Select MSI output as USB clock source */
-  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
-  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI;
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
-  clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
-}
-
-void board_init(void)
-{
-  SystemClock_Config();
-  all_rcc_clk_enable();
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  //NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  /* Enable Power Clock*/
-  __HAL_RCC_PWR_CLK_ENABLE();
-
-  /* Enable USB power on Pwrctrl CR2 register */
-  HAL_PWREx_EnableVddUSB();
-
-  GPIO_InitTypeDef  GPIO_InitStruct;
-
-  // LED
-  GPIO_InitStruct.Pin = LED_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
-  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
-
-  board_led_write(false);
-
-  // Button
-  GPIO_InitStruct.Pin = BUTTON_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
-  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
-
-  // USB
-  /* Configure DM DP Pins */
-  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* Configure VBUS Pin */
-  GPIO_InitStruct.Pin = GPIO_PIN_11;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
-
-  /* Enable USB FS Clock */
-  __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
-
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-}
-
-//--------------------------------------------------------------------+
-// board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-
-void HardFault_Handler (void)
-{
-  asm("bkpt");
-}
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
-}
diff --git a/tinyusb/hw/bsp/stm32l476disco/stm32l4xx_hal_conf.h b/tinyusb/hw/bsp/stm32l476disco/stm32l4xx_hal_conf.h
deleted file mode 100755
index 312f86da..00000000
--- a/tinyusb/hw/bsp/stm32l476disco/stm32l4xx_hal_conf.h
+++ /dev/null
@@ -1,420 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration template file.
-  *          This file should be copied to the application folder and renamed
-  *          to stm32l4xx_hal_conf.h.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_CONF_H
-#define __STM32L4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-/* #define HAL_ADC_MODULE_ENABLED */
-/* #define HAL_CAN_MODULE_ENABLED */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
-/* #define HAL_COMP_MODULE_ENABLED */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_CRC_MODULE_ENABLED */
-/* #define HAL_CRYP_MODULE_ENABLED */
-/* #define HAL_DAC_MODULE_ENABLED */
-/* #define HAL_DFSDM_MODULE_ENABLED */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_FIREWALL_MODULE_ENABLED */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED */
-// #define HAL_NOR_MODULE_ENABLED
-// #define HAL_SRAM_MODULE_ENABLED
-/* #define HAL_HCD_MODULE_ENABLED */ 
-#define HAL_GPIO_MODULE_ENABLED
-//#define HAL_I2C_MODULE_ENABLED
-/* #define HAL_IRDA_MODULE_ENABLED */
-/* #define HAL_IWDG_MODULE_ENABLED */
-//#define HAL_LCD_MODULE_ENABLED
-/* #define HAL_LPTIM_MODULE_ENABLED */
-/* #define HAL_OPAMP_MODULE_ENABLED */
-//#define HAL_PCD_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED */
-#define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RNG_MODULE_ENABLED */
-/* #define HAL_RTC_MODULE_ENABLED */
-//#define HAL_SAI_MODULE_ENABLED
-//#define HAL_SD_MODULE_ENABLED
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_SMBUS_MODULE_ENABLED */
-/* #define HAL_SPI_MODULE_ENABLED */
-/* #define HAL_SWPMI_MODULE_ENABLED */
-/* #define HAL_TIM_MODULE_ENABLED */
-/* #define HAL_TSC_MODULE_ENABLED */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED */
-
-
-/* ########################## Oscillator Values adaptation ####################*/
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    8000000U /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    100U   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal Multiple Speed oscillator (MSI) default value.
-  *        This value is the default MSI range value after Reset.
-  */
-#if !defined  (MSI_VALUE)
-  #define MSI_VALUE    4000000U /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    16000000U /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
-  *        This internal oscillator is mainly dedicated to provide a high precision clock to
-  *        the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
-  *        When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
-  *        which is subject to manufacturing process variations.
-  */
-#if !defined  (HSI48_VALUE) 
- #define HSI48_VALUE   48000000U             /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
-                                              The real value my vary depending on manufacturing process variations.*/
-#endif /* HSI48_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  32000U                 /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                     /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.*/
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  *        This value is used by the UART, RTC HAL module to compute the system frequency
-  */
-#if !defined  (LSE_VALUE)
-  #define LSE_VALUE    32768U /*!< Value of the External oscillator in Hz*/
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    5000U  /*!< Time out for LSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for SAI1 peripheral
-  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
-  *        frequency.
-  */
-#if !defined  (EXTERNAL_SAI1_CLOCK_VALUE)
-  #define EXTERNAL_SAI1_CLOCK_VALUE    48000U /*!< Value of the SAI1 External clock source in Hz*/
-#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
-
-/**
-  * @brief External clock source for SAI2 peripheral
-  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
-  *        frequency.
-  */
-#if !defined  (EXTERNAL_SAI2_CLOCK_VALUE)
-  #define EXTERNAL_SAI2_CLOCK_VALUE    48000U /*!< Value of the SAI2 External clock source in Hz*/
-#endif /* EXTERNAL_SAI2_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    3300U /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            0U /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              0U
-#define  INSTRUCTION_CACHE_ENABLE     1U
-#define  DATA_CACHE_ENABLE            1U
-
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS     0U /* ADC register callback disabled     */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS     0U /* CEC register callback disabled     */
-#define  USE_HAL_COMP_REGISTER_CALLBACKS    0U /* COMP register callback disabled    */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS    0U /* CRYP register callback disabled    */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS     0U /* DAC register callback disabled     */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS    0U /* DCMI register callback disabled    */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS   0U /* DFSDM register callback disabled   */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS   0U /* DMA2D register callback disabled   */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS     0U /* DSI register callback disabled     */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS     0U /* ETH register callback disabled     */
-#define  USE_HAL_FDCAN_REGISTER_CALLBACKS   0U /* FDCAN register callback disabled   */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS    0U /* NAND register callback disabled    */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS     0U /* NOR register callback disabled     */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS   0U /* SDRAM register callback disabled   */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS    0U /* SRAM register callback disabled    */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS    0U /* HASH register callback disabled    */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS     0U /* HCD register callback disabled     */
-#define  USE_HAL_HRTIM_REGISTER_CALLBACKS   0U /* HRTIM register callback disabled   */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS     0U /* I2C register callback disabled     */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS     0U /* I2S register callback disabled     */
-#define  USE_HAL_JPEG_REGISTER_CALLBACKS    0U /* JPEG register callback disabled    */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS   0U /* LPTIM register callback disabled   */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS    0U /* LTDC register callback disabled    */
-#define  USE_HAL_MDIOS_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
-#define  USE_HAL_OPAMP_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS     0U /* PCD register callback disabled     */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS    0U /* QSPI register callback disabled    */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS     0U /* RNG register callback disabled     */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS     0U /* RTC register callback disabled     */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS     0U /* SAI register callback disabled     */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS   0U /* SMBUS register callback disabled   */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS     0U /* SPI register callback disabled     */
-#define  USE_HAL_SWPMI_REGISTER_CALLBACKS   0U /* SWPMI register callback disabled   */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS     0U /* TIM register callback disabled     */
-#define  USE_HAL_UART_REGISTER_CALLBACKS    0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS   0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS    0U /* WWDG register callback disabled    */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT               1U */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
- * Activated: CRC code is present inside driver
- * Deactivated: CRC code cleaned from driver
- */
-
-#define USE_SPI_CRC                   1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32l4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32l4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32l4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
-  #include "stm32l4xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32l4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32l4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32l4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "Legacy/stm32l4xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_COMP_MODULE_ENABLED
-  #include "stm32l4xx_hal_comp.h"
-#endif /* HAL_COMP_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32l4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32l4xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32l4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_FIREWALL_MODULE_ENABLED
-  #include "stm32l4xx_hal_firewall.h"
-#endif /* HAL_FIREWALL_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32l4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32l4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32l4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32l4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32l4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32l4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LCD_MODULE_ENABLED
- #include "stm32l4xx_hal_lcd.h"
-#endif /* HAL_LCD_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
-#include "stm32l4xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_OPAMP_MODULE_ENABLED
-#include "stm32l4xx_hal_opamp.h"
-#endif /* HAL_OPAMP_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32l4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32l4xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32l4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32l4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32l4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32l4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32l4xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32l4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_SWPMI_MODULE_ENABLED
- #include "stm32l4xx_hal_swpmi.h"
-#endif /* HAL_SWPMI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32l4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_TSC_MODULE_ENABLED
- #include "stm32l4xx_hal_tsc.h"
-#endif /* HAL_TSC_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32l4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32l4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32l4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32l4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32l4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32l4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32l4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t *file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L4xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tinyusb/hw/bsp/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld b/tinyusb/hw/bsp/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld
deleted file mode 100755
index f93a1604..00000000
--- a/tinyusb/hw/bsp/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
-*****************************************************************************
-**
-
-**  File        : LinkerScript.ld
-**
-**  Abstract    : Linker script for STM32L4RxI Device with
-**                2048KByte FLASH, 640KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-**  (c)Copyright Ac6.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Ac6 permit registered System Workbench for MCU users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the System Workbench for MCU toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x200a0000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x460; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 640K
-FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 2048K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-  
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
diff --git a/tinyusb/hw/bsp/stm32l4r5nucleo/board.mk b/tinyusb/hw/bsp/stm32l4r5nucleo/board.mk
deleted file mode 100755
index 12a291d0..00000000
--- a/tinyusb/hw/bsp/stm32l4r5nucleo/board.mk
+++ /dev/null
@@ -1,50 +0,0 @@
-ST_FAMILY = l4
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
-ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib -nostartfiles \
-  -DHSE_VALUE=8000000 \
-  -DSTM32L4R5xx \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32L4
-
-# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/STM32L4RXxI_FLASH.ld
-
-SRC_C += \
-	src/portable/st/synopsys/dcd_synopsys.c \
-	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c
-
-SRC_S += \
-	$(ST_CMSIS)/Source/Templates/gcc/startup_stm32l4r5xx.s
-
-INC += \
-	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-	$(TOP)/$(ST_CMSIS)/Include \
-	$(TOP)/$(ST_HAL_DRIVER)/Inc \
-	$(TOP)/hw/bsp/$(BOARD)
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
-# flash target using on-board stlink
-flash: flash-stlink
diff --git a/tinyusb/hw/bsp/stm32l4r5nucleo/stm32l4r5nucleo.c b/tinyusb/hw/bsp/stm32l4r5nucleo/stm32l4r5nucleo.c
deleted file mode 100755
index bab66b55..00000000
--- a/tinyusb/hw/bsp/stm32l4r5nucleo/stm32l4r5nucleo.c
+++ /dev/null
@@ -1,287 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 William D. Jones (thor0505@comcast.net),
- * Ha Thach (tinyusb.org)
- * Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "../board.h"
-
-#include "stm32l4xx_hal.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void OTG_FS_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-#define LED_PORT              GPIOB
-#define LED_PIN               GPIO_PIN_14
-#define LED_STATE_ON          1
-
-#define BUTTON_PORT           GPIOC
-#define BUTTON_PIN            GPIO_PIN_13
-#define BUTTON_STATE_ACTIVE   1
-
-#define UARTx                 LPUART1
-#define UART_GPIO_PORT        GPIOG
-#define UART_GPIO_AF          GPIO_AF8_LPUART1
-#define UART_TX_PIN           GPIO_PIN_7
-#define UART_RX_PIN           GPIO_PIN_8
-
-UART_HandleTypeDef UartHandle;
-
-// enable all LED, Button, Uart, USB clock
-static void all_rcc_clk_enable(void)
-{
-  __HAL_RCC_GPIOA_CLK_ENABLE();  // USB D+, D-
-  __HAL_RCC_GPIOB_CLK_ENABLE();  // LED
-  __HAL_RCC_GPIOC_CLK_ENABLE();  // Button
-  __HAL_RCC_GPIOG_CLK_ENABLE();  // Uart TX, RX
-  __HAL_RCC_LPUART1_CLK_ENABLE(); // LPUart1 module
-}
-
-/**
-  * @brief  System Clock Configuration
-  *         The system Clock is configured as follow :
-  *            System Clock source            = PLL (MSI)
-  *            SYSCLK(Hz)                     = 120000000
-  *            HCLK(Hz)                       = 120000000
-  *            AHB Prescaler                  = 1
-  *            APB1 Prescaler                 = 1
-  *            APB2 Prescaler                 = 1
-  *            MSI Frequency(Hz)              = 48000000
-  *            PLL_M                          = 12
-  *            PLL_N                          = 60
-  *            PLL_P                          = 2
-  *            PLL_Q                          = 2
-  *            VDD(V)                         = 3.3
-  *            Main regulator output voltage  = Scale1 mode
-  *            Flash Latency(WS)              = 5
-  *         The USB clock configuration from PLLSAI:
-  *            PLLSAIP                        = 8 FIXME
-  *            PLLSAIN                        = 384 FIXME
-  *            PLLSAIQ                        = 7 FIXME
-  * @param  None
-  * @retval None
-  */
-void SystemClock_Config(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
-
-  /* Activate PLL with MSI , stabilizied via PLL by LSE */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI;
-  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
-  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
-  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
-  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
-  RCC_OscInitStruct.PLL.PLLM = 12;
-  RCC_OscInitStruct.PLL.PLLN = 60;
-  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
-  RCC_OscInitStruct.PLL.PLLQ = 2;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Enable MSI Auto-calibration through LSE */
-  HAL_RCCEx_EnableMSIPLLMode();
-
-  /* Select MSI output as USB clock source */
-  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
-  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI;
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
-
-  /* Select MSI output as USB clock source */
-  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
-  PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
-  
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
-  clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  // Avoid overshoot and start with HCLK 60 MHz  
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3);
-
-  /* AHB prescaler divider at 1 as second step */
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
-}
-
-void board_init(void)
-{
-  /* Enable Power Clock*/
-  __HAL_RCC_PWR_CLK_ENABLE();
-  /* Enable voltage range 1 boost mode for frequency above 80 Mhz */
-  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
-
-  /* Set tick interrupt priority, default HAL value is intentionally invalid
-     and that prevents PLL initialization in HAL_RCC_OscConfig() */
-
-  HAL_InitTick((1UL << __NVIC_PRIO_BITS) - 1UL);
-
-  SystemClock_Config();
-  all_rcc_clk_enable();
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  //NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  /* Enable USB power on Pwrctrl CR2 register */
-  HAL_PWREx_EnableVddUSB();
-
-  GPIO_InitTypeDef  GPIO_InitStruct;
-
-  // LED
-  GPIO_InitStruct.Pin = LED_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
-
-  // Button
-  GPIO_InitStruct.Pin = BUTTON_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
-
-  // IOSV bit MUST be set to access GPIO port G[2:15] */
-  __HAL_RCC_PWR_CLK_ENABLE();
-  HAL_PWREx_EnableVddIO2();
-
-  // Uart
-  GPIO_InitStruct.Pin       = UART_TX_PIN | UART_RX_PIN;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_PULLUP;
-  GPIO_InitStruct.Alternate = UART_GPIO_AF;
-  HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
-
-  UartHandle.Instance        = UARTx;
-  UartHandle.Init.BaudRate   = CFG_BOARD_UART_BAUDRATE;
-  UartHandle.Init.WordLength = UART_WORDLENGTH_8B;
-  UartHandle.Init.StopBits   = UART_STOPBITS_1;
-  UartHandle.Init.Parity     = UART_PARITY_NONE;
-  UartHandle.Init.HwFlowCtl  = UART_HWCONTROL_NONE;
-  UartHandle.Init.Mode       = UART_MODE_TX_RX;
-  UartHandle.Init.OverSampling = UART_OVERSAMPLING_16;
-  UartHandle.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
-  UartHandle.Init.ClockPrescaler = UART_PRESCALER_DIV1;
-  UartHandle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
-
-  HAL_UART_Init(&UartHandle);
-
-  /* Configure USB FS GPIOs */
-  /* Configure DM DP Pins */
-  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* Configure VBUS Pin */
-  GPIO_InitStruct.Pin = GPIO_PIN_9;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* Configure ID pin */
-  GPIO_InitStruct.Pin = GPIO_PIN_10;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* Enable USB FS Clocks */
-  __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
-
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  HAL_UART_Transmit(&UartHandle, (uint8_t*) buf, len, 0xffff);
-  return len;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-
-void HardFault_Handler (void)
-{
-  asm("bkpt");
-}
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
-}
diff --git a/tinyusb/hw/bsp/stm32l4r5nucleo/stm32l4xx_hal_conf.h b/tinyusb/hw/bsp/stm32l4r5nucleo/stm32l4xx_hal_conf.h
deleted file mode 100755
index 470ef129..00000000
--- a/tinyusb/hw/bsp/stm32l4r5nucleo/stm32l4xx_hal_conf.h
+++ /dev/null
@@ -1,419 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration template file.
-  *          This file should be copied to the application folder and renamed
-  *          to stm32l4xx_hal_conf.h.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_CONF_H
-#define __STM32L4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-/* #define HAL_ADC_MODULE_ENABLED */
-/* #define HAL_CAN_MODULE_ENABLED */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
-/* #define HAL_COMP_MODULE_ENABLED */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_CRC_MODULE_ENABLED */
-/* #define HAL_CRYP_MODULE_ENABLED */
-/* #define HAL_DAC_MODULE_ENABLED */
-/* #define HAL_DFSDM_MODULE_ENABLED */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_FIREWALL_MODULE_ENABLED */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED */
-// #define HAL_NOR_MODULE_ENABLED
-// #define HAL_SRAM_MODULE_ENABLED
-/* #define HAL_HCD_MODULE_ENABLED */ 
-#define HAL_GPIO_MODULE_ENABLED
-//#define HAL_I2C_MODULE_ENABLED
-/* #define HAL_IRDA_MODULE_ENABLED */
-/* #define HAL_IWDG_MODULE_ENABLED */
-//#define HAL_LCD_MODULE_ENABLED
-/* #define HAL_LPTIM_MODULE_ENABLED */
-/* #define HAL_OPAMP_MODULE_ENABLED */
-//#define HAL_PCD_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED */
-#define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RNG_MODULE_ENABLED */
-/* #define HAL_RTC_MODULE_ENABLED */
-//#define HAL_SAI_MODULE_ENABLED
-//#define HAL_SD_MODULE_ENABLED
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_SMBUS_MODULE_ENABLED */
-/* #define HAL_SPI_MODULE_ENABLED */
-/* #define HAL_SWPMI_MODULE_ENABLED */
-/* #define HAL_TIM_MODULE_ENABLED */
-/* #define HAL_TSC_MODULE_ENABLED */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED */
-
-
-/* ########################## Oscillator Values adaptation ####################*/
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    8000000U /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    100U   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal Multiple Speed oscillator (MSI) default value.
-  *        This value is the default MSI range value after Reset.
-  */
-#if !defined  (MSI_VALUE)
-  #define MSI_VALUE    4000000U /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    16000000U /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
-  *        This internal oscillator is mainly dedicated to provide a high precision clock to
-  *        the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
-  *        When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
-  *        which is subject to manufacturing process variations.
-  */
-#if !defined  (HSI48_VALUE) 
- #define HSI48_VALUE   48000000U             /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
-                                              The real value my vary depending on manufacturing process variations.*/
-#endif /* HSI48_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  32000U                 /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                     /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.*/
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  *        This value is used by the UART, RTC HAL module to compute the system frequency
-  */
-#if !defined  (LSE_VALUE)
-  #define LSE_VALUE    32768U /*!< Value of the External oscillator in Hz*/
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    5000U  /*!< Time out for LSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for SAI1 peripheral
-  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
-  *        frequency.
-  */
-#if !defined  (EXTERNAL_SAI1_CLOCK_VALUE)
-  #define EXTERNAL_SAI1_CLOCK_VALUE    48000U /*!< Value of the SAI1 External clock source in Hz*/
-#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
-
-/**
-  * @brief External clock source for SAI2 peripheral
-  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
-  *        frequency.
-  */
-#if !defined  (EXTERNAL_SAI2_CLOCK_VALUE)
-  #define EXTERNAL_SAI2_CLOCK_VALUE    48000U /*!< Value of the SAI2 External clock source in Hz*/
-#endif /* EXTERNAL_SAI2_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    3300U /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            0U /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              0U
-#define  INSTRUCTION_CACHE_ENABLE     1U
-#define  DATA_CACHE_ENABLE            1U
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS     0U /* ADC register callback disabled     */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS     0U /* CEC register callback disabled     */
-#define  USE_HAL_COMP_REGISTER_CALLBACKS    0U /* COMP register callback disabled    */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS    0U /* CRYP register callback disabled    */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS     0U /* DAC register callback disabled     */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS    0U /* DCMI register callback disabled    */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS   0U /* DFSDM register callback disabled   */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS   0U /* DMA2D register callback disabled   */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS     0U /* DSI register callback disabled     */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS     0U /* ETH register callback disabled     */
-#define  USE_HAL_FDCAN_REGISTER_CALLBACKS   0U /* FDCAN register callback disabled   */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS    0U /* NAND register callback disabled    */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS     0U /* NOR register callback disabled     */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS   0U /* SDRAM register callback disabled   */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS    0U /* SRAM register callback disabled    */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS    0U /* HASH register callback disabled    */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS     0U /* HCD register callback disabled     */
-#define  USE_HAL_HRTIM_REGISTER_CALLBACKS   0U /* HRTIM register callback disabled   */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS     0U /* I2C register callback disabled     */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS     0U /* I2S register callback disabled     */
-#define  USE_HAL_JPEG_REGISTER_CALLBACKS    0U /* JPEG register callback disabled    */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS   0U /* LPTIM register callback disabled   */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS    0U /* LTDC register callback disabled    */
-#define  USE_HAL_MDIOS_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
-#define  USE_HAL_OPAMP_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS     0U /* PCD register callback disabled     */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS    0U /* QSPI register callback disabled    */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS     0U /* RNG register callback disabled     */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS     0U /* RTC register callback disabled     */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS     0U /* SAI register callback disabled     */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS   0U /* SMBUS register callback disabled   */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS     0U /* SPI register callback disabled     */
-#define  USE_HAL_SWPMI_REGISTER_CALLBACKS   0U /* SWPMI register callback disabled   */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS     0U /* TIM register callback disabled     */
-#define  USE_HAL_UART_REGISTER_CALLBACKS    0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS   0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS    0U /* WWDG register callback disabled    */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT               1U */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
- * Activated: CRC code is present inside driver
- * Deactivated: CRC code cleaned from driver
- */
-
-#define USE_SPI_CRC                   1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32l4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32l4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32l4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
-  #include "stm32l4xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32l4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32l4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32l4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "Legacy/stm32l4xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_COMP_MODULE_ENABLED
-  #include "stm32l4xx_hal_comp.h"
-#endif /* HAL_COMP_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32l4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32l4xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32l4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_FIREWALL_MODULE_ENABLED
-  #include "stm32l4xx_hal_firewall.h"
-#endif /* HAL_FIREWALL_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32l4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32l4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32l4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32l4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32l4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32l4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LCD_MODULE_ENABLED
- #include "stm32l4xx_hal_lcd.h"
-#endif /* HAL_LCD_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
-#include "stm32l4xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_OPAMP_MODULE_ENABLED
-#include "stm32l4xx_hal_opamp.h"
-#endif /* HAL_OPAMP_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32l4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32l4xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32l4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32l4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32l4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32l4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32l4xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32l4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_SWPMI_MODULE_ENABLED
- #include "stm32l4xx_hal_swpmi.h"
-#endif /* HAL_SWPMI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32l4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_TSC_MODULE_ENABLED
- #include "stm32l4xx_hal_tsc.h"
-#endif /* HAL_TSC_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32l4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32l4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32l4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32l4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32l4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32l4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32l4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t *file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L4xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tinyusb/hw/bsp/waveshare_openh743i/STM32H743IITX_FLASH.ld b/tinyusb/hw/bsp/waveshare_openh743i/STM32H743IITX_FLASH.ld
deleted file mode 100755
index 73d2dedb..00000000
--- a/tinyusb/hw/bsp/waveshare_openh743i/STM32H743IITX_FLASH.ld
+++ /dev/null
@@ -1,175 +0,0 @@
-/*
-******************************************************************************
-**
-**  File        : LinkerScript.ld
-**
-**  Author      : STM32CubeIDE
-**
-**  Abstract    : Linker script for STM32H7 series
-**                2048Kbytes FLASH and 192Kbytes RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-*****************************************************************************
-** @attention
-**
-** Copyright (c) 2019 STMicroelectronics.
-** All rights reserved.
-**
-** This software component is licensed by ST under BSD 3-Clause license,
-** the "License"; You may not use this file except in compliance with the
-** License. You may obtain a copy of the License at:
-**                        opensource.org/licenses/BSD-3-Clause
-**
-****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20020000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x2000 ;  /* required amount of heap  */
-_Min_Stack_Size = 0x2000 ; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-  FLASH (rx)     : ORIGIN = 0x08000000, LENGTH = 2048K
-  RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K
-  RAM_D1 (xrw)   : ORIGIN = 0x24000000, LENGTH = 512K
-  RAM_D2 (xrw)   : ORIGIN = 0x30000000, LENGTH = 288K
-  RAM_D3 (xrw)   : ORIGIN = 0x38000000, LENGTH = 64K
-  ITCMRAM (xrw)  : ORIGIN = 0x00000000, LENGTH = 64K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data :
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-    *(.RamFunc)        /* .RamFunc sections */
-    *(.RamFunc*)       /* .RamFunc* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
-
-
diff --git a/tinyusb/hw/bsp/waveshare_openh743i/board.c b/tinyusb/hw/bsp/waveshare_openh743i/board.c
deleted file mode 100755
index 4468c066..00000000
--- a/tinyusb/hw/bsp/waveshare_openh743i/board.c
+++ /dev/null
@@ -1,495 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2019
- *    Benjamin Evans
- *    William D. Jones (thor0505@comcast.net),
- *    Ha Thach (tinyusb.org)
- *    Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "stm32h7xx_hal.h"
-#include "stm32h7xx_hal_tim.h"
-#include "bsp/board.h"
-
-
-/* ** BOARD SETUP **
- * 
- * NOTE: This board has bad signal integrity so you may experience some problems.
- * This setup assumes you have an openh743i-c Core and breakout board. For the HS
- * examples it also assumes you have a waveshare USB3300 breakout board plugged
- * into the ULPI PMOD header on the openh743i-c.
- * 
- * UART Debugging:
- * Due to pin conflicts in the HS configuration, this BSP uses USART3 (PD8, PD9).
- * As such, you won't be able to use the UART to USB converter on board and will
- * require an external UART to USB converter. You could use the waveshare FT232
- * USB UART Board (micro) but any 3.3V UART to USB converter will be fine.
- * 
- * Fullspeed:
- * If VBUS sense is enabled, ensure the PA9-VBUS jumper is connected on the core
- * board. Connect the PB6 jumper for the LED and the Wakeup - PA0 jumper for the
- * button. Connect the USB cable to the USB connector on the core board.
- * 
- * High Speed:
- * Remove all jumpers from the openh743i-c (especially the USART1 jumpers as the
- * pins conflict). Connect the PB6 jumper for the LED and the Wakeup - PA0
- * jumper for the button.
- * 
- * The reset pin on the ULPI PMOD port is not connected to the MCU. You'll need
- * to solder a wire from the RST pin on the USB3300 to a pin of your choosing on
- * the openh743i-c board (this example assumes you've used PD14 as specified with
- * the ULPI_RST_PORT and ULPI_RST_PIN defines below).
- * 
- * Preferably power the board using the external 5VDC jack. Connect the USB cable
- * to the USB connector on the ULPI board. Adjust delays in this file as required.
- * 
- * If you're having trouble, ask a question on the tinyUSB Github Discussion boards.
- * 
- * Have fun!
- *
-*/
-
-//--------------------------------------------------------------------+
-// BOARD DEFINES
-//--------------------------------------------------------------------+
-
-//LED Pin
-#define LED_PORT GPIOB
-#define LED_PIN GPIO_PIN_6
-#define LED_STATE_ON 1
-
-//ULPI PHY reset pin
-#define ULPI_RST_PORT GPIOD
-#define ULPI_RST_PIN GPIO_PIN_14
-
-// Tamper push-button
-#define BUTTON_PORT GPIOA
-#define BUTTON_PIN GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE 1
-
-// Need external UART to USB converter as USART1 pins conflict with HS ULPI pins
-#define UART_DEV USART3
-#define UART_CLK_EN __HAL_RCC_USART3_CLK_ENABLE
-#define UART_GPIO_PORT GPIOD
-#define UART_GPIO_AF GPIO_AF7_USART3
-#define UART_TX_PIN GPIO_PIN_8
-#define UART_RX_PIN GPIO_PIN_9
-
-// VBUS Sense detection
-#define OTG_FS_VBUS_SENSE 1
-#define OTG_HS_VBUS_SENSE 0
-
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-UART_HandleTypeDef uartHandle;
-TIM_HandleTypeDef tim2Handle;
-
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-
-// Despite being call USB2_OTG
-// OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port
-void OTG_FS_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-// Despite being call USB2_OTG
-// OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port
-void OTG_HS_IRQHandler(void)
-{
-  tud_int_handler(1);
-}
-
-
-//--------------------------------------------------------------------+
-// RCC Clock
-//--------------------------------------------------------------------+
-static inline void board_stm32h7_clock_init(void)
-{
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
-
-  __HAL_RCC_SYSCFG_CLK_ENABLE();
-
-  // Supply configuration update enable
-  HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
-
-  // Configure the main internal regulator output voltage
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
-
-  while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY))
-  {
-  }
-  // Macro to configure the PLL clock source
-  __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE);
-
-  // Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef structure.
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM = 2;
-  RCC_OscInitStruct.PLL.PLLN = 240;
-  RCC_OscInitStruct.PLL.PLLP = 2;
-  RCC_OscInitStruct.PLL.PLLQ = 2;
-  RCC_OscInitStruct.PLL.PLLR = 2;
-  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
-  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
-  RCC_OscInitStruct.PLL.PLLFRACN = 0;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB | RCC_PERIPHCLK_USART3;
-  PeriphClkInitStruct.PLL3.PLL3M = 8;
-  PeriphClkInitStruct.PLL3.PLL3N = 336;
-  PeriphClkInitStruct.PLL3.PLL3P = 2;
-  PeriphClkInitStruct.PLL3.PLL3Q = 7;
-  PeriphClkInitStruct.PLL3.PLL3R = 2;
-  PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_0;
-  PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE;
-  PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
-  PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_PLL3;
-  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3;
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
-
-  // Initializes the CPU, AHB and APB buses clocks
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
-  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
-  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
-
-  __HAL_RCC_CSI_ENABLE();
-
-  // Enable SYSCFG clock mondatory for I/O Compensation Cell
-  __HAL_RCC_SYSCFG_CLK_ENABLE();
-
-  // Enables the I/O Compensation Cell
-  HAL_EnableCompensationCell();
-
-  // Enable voltage detector
-  HAL_PWREx_EnableUSBVoltageDetector();
-
-  return;
-}
-
-
-//--------------------------------------------------------------------+
-// Timer implementation for board delay
-// This should be OS safe and doesn't require the scheduler to be running
-//--------------------------------------------------------------------+
-static void init_timer(void)
-{
-  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
-
-  __HAL_RCC_TIM2_CLK_ENABLE();
-
-  //Assuming timer clock is running at 260Mhz this should configure the timer counter to 1000Hz
-  tim2Handle.Instance = TIM2;
-  tim2Handle.Init.Prescaler = 60000U - 1U;
-  tim2Handle.Init.CounterMode = TIM_COUNTERMODE_UP;
-  tim2Handle.Init.Period = 0xFFFFFFFFU;
-  tim2Handle.Init.ClockDivision = TIM_CLOCKDIVISION_DIV4;
-  tim2Handle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
-  HAL_TIM_Base_Init(&tim2Handle);
-
-  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
-  HAL_TIM_ConfigClockSource(&tim2Handle, &sClockSourceConfig);
-
-  //Start the timer
-  HAL_TIM_Base_Start(&tim2Handle);
-
-  return;
-}
-
-
-// Custom board delay implementation using timer ticks
-static inline void timer_board_delay(uint32_t ms)
-{
-  uint32_t startMs = __HAL_TIM_GET_COUNTER(&tim2Handle);
-  while ((__HAL_TIM_GET_COUNTER(&tim2Handle) - startMs) < ms)
-  {
-    asm("nop"); //do nothing
-  }
-}
-
-
-//Board initialisation
-void board_init(void)
-{
-  GPIO_InitTypeDef GPIO_InitStruct;
-
-  // Init clocks
-  board_stm32h7_clock_init();
-
-  // Init timer for delays
-  init_timer();
-
-  //Disable systick for now
-  //If using an RTOS and the systick interrupt fires without the scheduler running you might have an issue
-  //Because this init code now introduces delays, the systick should be disabled until after board init
-  SysTick->CTRL &= ~1U;
-
-  // Enable GPIO clocks
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  __HAL_RCC_GPIOC_CLK_ENABLE();
-  __HAL_RCC_GPIOD_CLK_ENABLE();
-  __HAL_RCC_GPIOH_CLK_ENABLE();
-  __HAL_RCC_GPIOI_CLK_ENABLE();
-
-  // Enable UART Clock
-  UART_CLK_EN();
-
-#if CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-  NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-#endif
-
-  // LED
-  GPIO_InitStruct.Pin = LED_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
-
-  // PHY RST Pin
-  GPIO_InitStruct.Pin = ULPI_RST_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
-  HAL_GPIO_Init(ULPI_RST_PORT, &GPIO_InitStruct);
-  HAL_GPIO_WritePin(ULPI_RST_PORT, ULPI_RST_PIN, 0U);
-
-  // Button
-  GPIO_InitStruct.Pin = BUTTON_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
-
-  // Uart
-  GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-  GPIO_InitStruct.Alternate = UART_GPIO_AF;
-  HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
-
-  uartHandle.Instance = UART_DEV;
-  uartHandle.Init.BaudRate = CFG_BOARD_UART_BAUDRATE;
-  uartHandle.Init.WordLength = UART_WORDLENGTH_8B;
-  uartHandle.Init.StopBits = UART_STOPBITS_1;
-  uartHandle.Init.Parity = UART_PARITY_NONE;
-  uartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
-  uartHandle.Init.Mode = UART_MODE_TX_RX;
-  uartHandle.Init.OverSampling = UART_OVERSAMPLING_16;
-  HAL_UART_Init(&uartHandle);
-
-#if BOARD_DEVICE_RHPORT_NUM == 0
-  //Full Speed
-
-  // Configure DM DP Pins
-  GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  // This for ID line debug
-  GPIO_InitStruct.Pin = GPIO_PIN_10;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  __HAL_RCC_USB2_OTG_FS_CLK_ENABLE();
-
-#if OTG_FS_VBUS_SENSE
-  // Configure VBUS Pin
-  GPIO_InitStruct.Pin = GPIO_PIN_9;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-#else
-  // Disable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
-
-  // B-peripheral session valid override enable
-  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
-  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
-#endif // vbus sense
-
-#elif BOARD_DEVICE_RHPORT_NUM == 1
-  //High Speed
-
-  /**USB_OTG_HS GPIO Configuration
-    PC0     ------> USB_OTG_HS_ULPI_STP
-    PC2_C   ------> USB_OTG_HS_ULPI_DIR
-    PC3_C   ------> USB_OTG_HS_ULPI_NXT
-    PA3     ------> USB_OTG_HS_ULPI_D0
-    PA5     ------> USB_OTG_HS_ULPI_CK
-    PB1     ------> USB_OTG_HS_ULPI_D2
-    PB10    ------> USB_OTG_HS_ULPI_D3
-    PB11    ------> USB_OTG_HS_ULPI_D4
-    PB12    ------> USB_OTG_HS_ULPI_D5
-    PB13    ------> USB_OTG_HS_ULPI_D6
-    PB5     ------> USB_OTG_HS_ULPI_D7
-  */
-
-  GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
-  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
-
-  GPIO_InitStruct.Pin = GPIO_PIN_3 | GPIO_PIN_5;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_5;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
-  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
-
-  // Peripheral clock enable
-  __HAL_RCC_USB_OTG_HS_CLK_ENABLE();
-  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE();
-
-#if OTG_HS_VBUS_SENSE
-#error OTG HS VBUS Sense enabled is not implemented
-#else
-  // No VBUS sense
-  USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
-
-  // B-peripheral session valid override enable
-  USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
-  USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
-#endif
-
-  // Force device mode
-  USB_OTG_HS->GUSBCFG &= ~USB_OTG_GUSBCFG_FHMOD;
-  USB_OTG_HS->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
-
-  //Reset the PHY - Change the delays as you see fit
-  timer_board_delay(5U); //Delay 5ms
-  HAL_GPIO_WritePin(ULPI_RST_PORT, ULPI_RST_PIN, 1U);
-  timer_board_delay(20U); //Delay 20ms
-  HAL_GPIO_WritePin(ULPI_RST_PORT, ULPI_RST_PIN, 0U);
-  timer_board_delay(20U); //Delay 20ms
-
-#endif // rhport = 1
-
-  //Disable the timer used for delays
-  HAL_TIM_Base_Stop(&tim2Handle);
-  __HAL_RCC_TIM2_CLK_DISABLE();
-
-  // Configure systick 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-
-  //Enable systick
-  SysTick->CTRL |= ~1U;
-
-  return;
-}
-
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
-}
-
-
-uint32_t board_button_read(void)
-{
-  return (BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN)) ? 1 : 0;
-}
-
-
-int board_uart_read(uint8_t *buf, int len)
-{
-  (void)buf;
-  (void)len;
-  return 0;
-}
-
-
-int board_uart_write(void const *buf, int len)
-{
-  HAL_UART_Transmit(&uartHandle, (uint8_t *)buf, len, 0xffff);
-  return len;
-}
-
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
-  system_ticks++;
-}
-
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-
-
-void HardFault_Handler(void)
-{
-  asm("bkpt");
-}
-
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-}
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/waveshare_openh743i/board.mk b/tinyusb/hw/bsp/waveshare_openh743i/board.mk
deleted file mode 100755
index 721df1bd..00000000
--- a/tinyusb/hw/bsp/waveshare_openh743i/board.mk
+++ /dev/null
@@ -1,64 +0,0 @@
-UF2_FAMILY_ID = 0x6db66082
-ST_FAMILY = h7
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
-ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-# Default is HS port
-PORT ?= 1
-
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s
-LD_FILE = $(BOARD_PATH)/STM32H743IITX_FLASH.ld
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m7 \
-  -mfloat-abi=hard \
-  -mfpu=fpv5-d16 \
-  -nostdlib -nostartfiles \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32H7 \
-	-DBOARD_DEVICE_RHPORT_NUM=$(PORT) \
-  -DSTM32H743xx \
-  -DHSE_VALUE=8000000
-
-ifeq ($(PORT), 1)
-  CFLAGS += -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED
-  $(info "PORT1 High Speed")
-else
-  $(info "PORT0 Full Speed")
-endif
-
-# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
-
-# All source paths should be relative to the top level.
-SRC_C += \
-	src/portable/st/synopsys/dcd_synopsys.c \
-	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_tim.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_tim_ex.c
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-	$(TOP)/$(ST_CMSIS)/Include \
-	$(TOP)/$(ST_HAL_DRIVER)/Inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM7/r0p1
-
-# For flash-jlink target
-JLINK_DEVICE = stm32h743ii
-
-# flash target using jlink
-flash: flash-jlink
\ No newline at end of file
diff --git a/tinyusb/hw/bsp/waveshare_openh743i/stm32h7xx_hal_conf.h b/tinyusb/hw/bsp/waveshare_openh743i/stm32h7xx_hal_conf.h
deleted file mode 100755
index 11d29ed6..00000000
--- a/tinyusb/hw/bsp/waveshare_openh743i/stm32h7xx_hal_conf.h
+++ /dev/null
@@ -1,483 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32h7xx_hal_conf_template.h
-  * @brief   HAL configuration template file. 
-  *          This file should be copied to the application folder and renamed
-  *          to stm32h7xx_hal_conf.h.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_CONF_H
-#define __STM32H7xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-#define HAL_ADC_MODULE_ENABLED
-/* #define HAL_CEC_MODULE_ENABLED */
-/* #define HAL_COMP_MODULE_ENABLED */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_CRC_MODULE_ENABLED */
-/* #define HAL_CRYP_MODULE_ENABLED */
-/* #define HAL_DAC_MODULE_ENABLED */
-/* #define HAL_DCMI_MODULE_ENABLED */
-/* #define HAL_DFSDM_MODULE_ENABLED */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED */
-/* #define HAL_ETH_MODULE_ENABLED */
-/* #define HAL_EXTI_MODULE_ENABLED */
-/* #define HAL_FDCAN_MODULE_ENABLED */
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_HASH_MODULE_ENABLED */
-/* #define HAL_HCD_MODULE_ENABLED */
-/* #define HAL_HRTIM_MODULE_ENABLED */
-/* #define HAL_HSEM_MODULE_ENABLED */
-/* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED */
-/* #define HAL_IRDA_MODULE_ENABLED */
-/* #define HAL_IWDG_MODULE_ENABLED */
-/* #define HAL_JPEG_MODULE_ENABLED */
-/* #define HAL_LPTIM_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED */
-/* #define HAL_MDIOS_MODULE_ENABLED */
-/* #define HAL_MDMA_MODULE_ENABLED */
-/* #define HAL_MMC_MODULE_ENABLED */
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_OPAMP_MODULE_ENABLED */
-/* #define HAL_PCD_MODULE_ENABLED */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED */
-/* #define HAL_RAMECC_MODULE_ENABLED */
-#define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RNG_MODULE_ENABLED */
-/* #define HAL_RTC_MODULE_ENABLED */
-/* #define HAL_SAI_MODULE_ENABLED */
-/* #define HAL_SD_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_SMBUS_MODULE_ENABLED */
-/* #define HAL_SPDIFRX_MODULE_ENABLED */
-#define HAL_SPI_MODULE_ENABLED
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SWPMI_MODULE_ENABLED */
-#define HAL_TIM_MODULE_ENABLED
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED */
-
-/* ########################## Oscillator Values adaptation ####################*/
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-//#define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
-#error HSE_VALUE is not defined
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal  oscillator (CSI) default value.
-  *        This value is the default CSI value after Reset.
-  */
-#if !defined  (CSI_VALUE)
-  #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* CSI_VALUE */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  *        This value is used by the UART, RTC HAL module to compute the system frequency
-  */
-#if !defined  (LSE_VALUE)
-  #define LSE_VALUE    ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
-#endif /* LSE_VALUE */
-
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-#if !defined  (LSI_VALUE)
-  #define LSI_VALUE  ((uint32_t)32000)      /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                              The real value may vary depending on the variations
-                                              in voltage and temperature.*/
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the External clock in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x0F) /*!< tick interrupt priority */
-#define  USE_RTOS                     0
-#define  USE_SD_TRANSCEIVER           1U               /*!< use uSD Transceiver */
-#define  USE_SPI_CRC                  1U               /*!< use CRC in SPI */
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS     0U /* ADC register callback disabled     */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS     0U /* CEC register callback disabled     */
-#define  USE_HAL_COMP_REGISTER_CALLBACKS    0U /* COMP register callback disabled    */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS    0U /* CRYP register callback disabled    */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS     0U /* DAC register callback disabled     */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS    0U /* DCMI register callback disabled    */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS   0U /* DFSDM register callback disabled   */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS   0U /* DMA2D register callback disabled   */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS     0U /* DSI register callback disabled     */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS     0U /* ETH register callback disabled     */
-#define  USE_HAL_FDCAN_REGISTER_CALLBACKS   0U /* FDCAN register callback disabled   */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS    0U /* NAND register callback disabled    */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS     0U /* NOR register callback disabled     */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS   0U /* SDRAM register callback disabled   */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS    0U /* SRAM register callback disabled    */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS    0U /* HASH register callback disabled    */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS     0U /* HCD register callback disabled     */
-#define  USE_HAL_HRTIM_REGISTER_CALLBACKS   0U /* HRTIM register callback disabled   */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS     0U /* I2C register callback disabled     */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS     0U /* I2S register callback disabled     */
-#define  USE_HAL_JPEG_REGISTER_CALLBACKS    0U /* JPEG register callback disabled    */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS   0U /* LPTIM register callback disabled   */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS    0U /* LTDC register callback disabled    */
-#define  USE_HAL_MDIOS_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
-#define  USE_HAL_OPAMP_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS     0U /* PCD register callback disabled     */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS    0U /* QSPI register callback disabled    */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS     0U /* RNG register callback disabled     */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS     0U /* RTC register callback disabled     */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS     0U /* SAI register callback disabled     */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS   0U /* SMBUS register callback disabled   */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS     0U /* SPI register callback disabled     */
-#define  USE_HAL_SWPMI_REGISTER_CALLBACKS   0U /* SWPMI register callback disabled   */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS     0U /* TIM register callback disabled     */
-#define  USE_HAL_UART_REGISTER_CALLBACKS    0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS   0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS    0U /* WWDG register callback disabled    */
-
-/* ########################### Ethernet Configuration ######################### */
-#define ETH_TX_DESC_CNT         4  /* number of Ethernet Tx DMA descriptors */
-#define ETH_RX_DESC_CNT         4  /* number of Ethernet Rx DMA descriptors */
-
-#define ETH_MAC_ADDR0    ((uint8_t)0x02)
-#define ETH_MAC_ADDR1    ((uint8_t)0x00)
-#define ETH_MAC_ADDR2    ((uint8_t)0x00)
-#define ETH_MAC_ADDR3    ((uint8_t)0x00)
-#define ETH_MAC_ADDR4    ((uint8_t)0x00)
-#define ETH_MAC_ADDR5    ((uint8_t)0x00)
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32h7xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32h7xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32h7xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_MDMA_MODULE_ENABLED
- #include "stm32h7xx_hal_mdma.h"
-#endif /* HAL_MDMA_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
-  #include "stm32h7xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32h7xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32h7xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
-  #include "stm32h7xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
-  #include "stm32h7xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32h7xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32h7xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32h7xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32h7xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_FDCAN_MODULE_ENABLED
-  #include "stm32h7xx_hal_fdcan.h"
-#endif /* HAL_FDCAN_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
-  #include "stm32h7xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_COMP_MODULE_ENABLED
-  #include "stm32h7xx_hal_comp.h"
-#endif /* HAL_COMP_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32h7xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32h7xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32h7xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32h7xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_HRTIM_MODULE_ENABLED
-  #include "stm32h7xx_hal_hrtim.h"
-#endif /* HAL_HRTIM_MODULE_ENABLED */
-
-#ifdef HAL_HSEM_MODULE_ENABLED
-  #include "stm32h7xx_hal_hsem.h"
-#endif /* HAL_HSEM_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32h7xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32h7xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32h7xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32h7xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32h7xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32h7xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_JPEG_MODULE_ENABLED
- #include "stm32h7xx_hal_jpeg.h"
-#endif /* HAL_JPEG_MODULE_ENABLED */
-
-#ifdef HAL_MDIOS_MODULE_ENABLED
- #include "stm32h7xx_hal_mdios.h"
-#endif /* HAL_MDIOS_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32h7xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
-#include "stm32h7xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
-#include "stm32h7xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_OPAMP_MODULE_ENABLED
-#include "stm32h7xx_hal_opamp.h"
-#endif /* HAL_OPAMP_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32h7xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32h7xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_RAMECC_MODULE_ENABLED
- #include "stm32h7xx_hal_ramecc.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32h7xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32h7xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32h7xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32h7xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
- #include "stm32h7xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32h7xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32h7xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_SWPMI_MODULE_ENABLED
- #include "stm32h7xx_hal_swpmi.h"
-#endif /* HAL_SWPMI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32h7xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32h7xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32h7xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32h7xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32h7xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32h7xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32h7xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32h7xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32h7xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t *file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_CONF_H */
- 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tinyusb/hw/mcu/dialog/README.md b/tinyusb/hw/mcu/dialog/README.md
deleted file mode 100755
index 69676f08..00000000
--- a/tinyusb/hw/mcu/dialog/README.md
+++ /dev/null
@@ -1,9 +0,0 @@
-# Dialog DA1469x MCU
-
-**Dialog Semiconductors** provides SDKs for DA146x MCU family.
-Most of the files there can't be redistributed.
-Registers definition file `DA1469xAB.h` and some **ARM** originated headers are have licenses that allow
-for redistribution.  
-Whole SDK repository can be downloaded from Dialog Semiconductor web page `https://www.dialog.com`
-
-
diff --git a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/arm_license.txt b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/arm_license.txt
deleted file mode 100755
index b324eb28..00000000
--- a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/arm_license.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
diff --git a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/DA1469xAB.h b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/DA1469xAB.h
deleted file mode 100755
index fa2ca5d9..00000000
--- a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/DA1469xAB.h
+++ /dev/null
@@ -1,8657 +0,0 @@
-/*
- * Copyright (C) 2019 Dialog Semiconductor. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * - Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * - Neither the name of Dialog Semiconductor nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * @file     DA1469xAB.h
- * @brief    CMSIS HeaderFile
- * @version  1.2
- * @date     22. April 2019
- * @note     Generated by SVDConv V3.3.25 on Monday, 22.04.2019 11:06:30
- *           from File 'DA1469xAB.xml',
- */
-
-
-
-/** @addtogroup PLA_BSP_REGISTERS
-  * @{
-  */
-
-
-/** @addtogroup DA1469x
-  * @{
-  */
-
-
-#ifndef DA1469X_H
-#define DA1469X_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/** @addtogroup Configuration_of_CMSIS
-  * @{
-  */
-
-
-/* =========================================================================================================================== */
-/* ================                                Interrupt Number Definition                                ================ */
-/* =========================================================================================================================== */
-
-/**
-  * @brief Interrupt Number Definition
-  */
-
-typedef enum {
-/* =======================================  ARM Cortex-M33 Specific Interrupt Numbers  ======================================= */
-  Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
-  NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
-  HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */
-  MemoryManagement_IRQn     = -12,              /*!< -12  Memory Management, MPU mismatch, including Access Violation
-                                                     and No Match                                                              */
-  BusFault_IRQn             = -11,              /*!< -11  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
-                                                     related Fault                                                             */
-  UsageFault_IRQn           = -10,              /*!< -10  Usage Fault, i.e. Undef Instruction, Illegal State Transition        */
-  SecureFault_IRQn          =  -9,              /*!< -9 Secure Fault Handler                                                   */
-  SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */
-  DebugMonitor_IRQn         =  -4,              /*!< -4 Debug Monitor                                                          */
-  PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */
-  SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */
-/* ==========================================  DA1469x Specific Interrupt Numbers  =========================================== */
-  SNC_IRQn                  =   0,              /*!< 0  Sensor Node Controller interrupt request.                              */
-  DMA_IRQn                  =   1,              /*!< 1  General Purpose DMA interrupt request.                                 */
-  CHARGER_STATE_IRQn        =   2,              /*!< 2  Charger State interrupt request.                                       */
-  CHARGER_ERROR_IRQn        =   3,              /*!< 3  Charger Error interrupt request.                                       */
-  CMAC2SYS_IRQn             =   4,              /*!< 4  CMAC and mailbox interrupt request.                                    */
-  UART_IRQn                 =   5,              /*!< 5  UART interrupt request.                                                */
-  UART2_IRQn                =   6,              /*!< 6  UART2 interrupt request.                                               */
-  UART3_IRQn                =   7,              /*!< 7  UART3 interrupt request.                                               */
-  I2C_IRQn                  =   8,              /*!< 8  I2C interrupt request.                                                 */
-  I2C2_IRQn                 =   9,              /*!< 9  I2C2 interrupt request.                                                */
-  SPI_IRQn                  =  10,              /*!< 10 SPI interrupt request.                                                 */
-  SPI2_IRQn                 =  11,              /*!< 11 SPI2 interrupt request.                                                */
-  PCM_IRQn                  =  12,              /*!< 12 PCM interrupt request.                                                 */
-  SRC_IN_IRQn               =  13,              /*!< 13 SRC input interrupt request.                                           */
-  SRC_OUT_IRQn              =  14,              /*!< 14 SRC output interrupt request.                                          */
-  USB_IRQn                  =  15,              /*!< 15 USB interrupt request.                                                 */
-  TIMER_IRQn                =  16,              /*!< 16 TIMER interrupt request.                                               */
-  TIMER2_IRQn               =  17,              /*!< 17 TIMER2 interrupt request.                                              */
-  RTC_IRQn                  =  18,              /*!< 18 RTC interrupt request.                                                 */
-  KEY_WKUP_GPIO_IRQn        =  19,              /*!< 19 Debounced button press interrupt request.                              */
-  PDC_IRQn                  =  20,              /*!< 20 Wakeup IRQ from PDC to CM33                                            */
-  VBUS_IRQn                 =  21,              /*!< 21 VBUS presence interrupt request.                                       */
-  MRM_IRQn                  =  22,              /*!< 22 Cache Miss Rate Monitor interrupt request.                             */
-  MOTOR_CONTROLLER_IRQn     =  23,              /*!< 23 MOTOR and mailbox interrupt request.                                   */
-  TRNG_IRQn                 =  24,              /*!< 24 True Random Number Generation interrupt request.                       */
-  DCDC_IRQn                 =  25,              /*!< 25 DCDC interrupt request.                                                */
-  XTAL32M_RDY_IRQn          =  26,              /*!< 26 XTAL32M trimmed and ready interrupt request.                           */
-  GPADC_IRQn                =  27,              /*!< 27 General Purpose Analog-Digital Converter interrupt request.            */
-  SDADC_IRQn                =  28,              /*!< 28 Sigma Delta Analog-Digital Converter interrupt request.                */
-  CRYPTO_IRQn               =  29,              /*!< 29 Crypto interrupt request.                                              */
-  CAPTIMER_IRQn             =  30,              /*!< 30 GPIO triggered Timer Capture interrupt request.                        */
-  RFDIAG_IRQn               =  31,              /*!< 31 Baseband or Radio Diagnostics interrupt request.                       */
-  LCD_CONTROLLER_IRQn       =  32,              /*!< 32 Parallel LCD Controller interrupt request.                             */
-  PLL_LOCK_IRQn             =  33,              /*!< 33 Pll lock interrupt request.                                            */
-  TIMER3_IRQn               =  34,              /*!< 34 TIMER3 interrupt request.                                              */
-  TIMER4_IRQn               =  35,              /*!< 35 TIMER4 interrupt request.                                              */
-  LRA_IRQn                  =  36,              /*!< 36 LRA/ERM interrupt request.                                             */
-  RTC_EVENT_IRQn            =  37,              /*!< 37 RTC event interrupt request.                                           */
-  GPIO_P0_IRQn              =  38,              /*!< 38 GPIO port 0 toggle interrupt request.                                  */
-  GPIO_P1_IRQn              =  39               /*!< 39 GPIO port 1 toggle interrupt request.                                  */
-} IRQn_Type;
-
-
-
-/* =========================================================================================================================== */
-/* ================                           Processor and Core Peripheral Section                           ================ */
-/* =========================================================================================================================== */
-
-/* ==========================  Configuration of the ARM Cortex-M33 Processor and Core Peripherals  =========================== */
-#define __CM33_REV                 0x0000U      /*!< CM33 Core Revision                                                        */
-#define __NVIC_PRIO_BITS               4        /*!< Number of Bits used for Priority Levels                                   */
-#define __Vendor_SysTickConfig         0        /*!< Set to 1 if different SysTick Config is used                              */
-#define __VTOR_PRESENT                 1        /*!< Set to 1 if CPU supports Vector Table Offset Register                     */
-#define __MPU_PRESENT                  1        /*!< MPU present                                                               */
-#define __FPU_PRESENT                  1        /*!< FPU present                                                               */
-#define __FPU_DP                       0        /*!< Double Precision FPU                                                      */
-#define __DSP_PRESENT                  1        /*!< DSP extension present                                                     */
-#define __SAU_REGION_PRESENT           0        /*!< SAU present                                                               */
-
-
-/** @} */ /* End of group Configuration_of_CMSIS */
-
-#include "core_cm33.h"                          /*!< ARM Cortex-M33 processor and core peripherals                             */
-#include "system_DA1469x.h"                     /*!< DA1469x System                                                            */
-
-#ifndef __IM                                    /*!< Fallback for older CMSIS versions                                         */
-  #define __IM   __I
-#endif
-#ifndef __OM                                    /*!< Fallback for older CMSIS versions                                         */
-  #define __OM   __O
-#endif
-#ifndef __IOM                                   /*!< Fallback for older CMSIS versions                                         */
-  #define __IOM  __IO
-#endif
-
-
-/* =========================================================================================================================== */
-/* ================                            Device Specific Peripheral Section                             ================ */
-/* =========================================================================================================================== */
-
-
-/** @addtogroup Device_Peripheral_peripherals
-  * @{
-  */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                         AES_HASH                                          ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief AES_HASH registers (AES_HASH)
-  */
-
-typedef struct {                                /*!< (@ 0x30040000) AES_HASH Structure                                         */
-  __IOM uint32_t  CRYPTO_CTRL_REG;              /*!< (@ 0x00000000) Crypto Control register                                    */
-  __IOM uint32_t  CRYPTO_START_REG;             /*!< (@ 0x00000004) Crypto Start calculation                                   */
-  __IOM uint32_t  CRYPTO_FETCH_ADDR_REG;        /*!< (@ 0x00000008) Crypto DMA fetch register                                  */
-  __IOM uint32_t  CRYPTO_LEN_REG;               /*!< (@ 0x0000000C) Crypto Length of the input block in bytes                  */
-  __IOM uint32_t  CRYPTO_DEST_ADDR_REG;         /*!< (@ 0x00000010) Crypto DMA destination memory                              */
-  __IOM uint32_t  CRYPTO_STATUS_REG;            /*!< (@ 0x00000014) Crypto Status register                                     */
-  __IOM uint32_t  CRYPTO_CLRIRQ_REG;            /*!< (@ 0x00000018) Crypto Clear interrupt request                             */
-  __IOM uint32_t  CRYPTO_MREG0_REG;             /*!< (@ 0x0000001C) Crypto Mode depended register 0                            */
-  __IOM uint32_t  CRYPTO_MREG1_REG;             /*!< (@ 0x00000020) Crypto Mode depended register 1                            */
-  __IOM uint32_t  CRYPTO_MREG2_REG;             /*!< (@ 0x00000024) Crypto Mode depended register 2                            */
-  __IOM uint32_t  CRYPTO_MREG3_REG;             /*!< (@ 0x00000028) Crypto Mode depended register 3                            */
-  __IM  uint32_t  RESERVED[53];
-  __IOM uint32_t  CRYPTO_KEYS_START;            /*!< (@ 0x00000100) Crypto First position of the AES keys storage
-                                                                    memory                                                     */
-} AES_HASH_Type;                                /*!< Size = 260 (0x104)                                                        */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                        ANAMISC_BIF                                        ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief ANAMISC_BIF registers (ANAMISC_BIF)
-  */
-
-typedef struct {                                /*!< (@ 0x50030B00) ANAMISC_BIF Structure                                      */
-  __IM  uint32_t  RESERVED[4];
-  __IOM uint32_t  CLK_REF_SEL_REG;              /*!< (@ 0x00000010) Select clock for oscillator calibration                    */
-  __IOM uint32_t  CLK_REF_CNT_REG;              /*!< (@ 0x00000014) Count value for oscillator calibration                     */
-  __IOM uint32_t  CLK_REF_VAL_REG;              /*!< (@ 0x00000018) DIVN reference cycles, lower 16 bits                       */
-} ANAMISC_BIF_Type;                             /*!< Size = 28 (0x1c)                                                          */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                            APU                                            ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief APU registers (APU)
-  */
-
-typedef struct {                                /*!< (@ 0x50030600) APU Structure                                              */
-  __IOM uint32_t  SRC1_CTRL_REG;                /*!< (@ 0x00000000) SRC1 control register                                      */
-  __IOM uint32_t  SRC1_IN_FS_REG;               /*!< (@ 0x00000004) SRC1 Sample input rate                                     */
-  __IOM uint32_t  SRC1_OUT_FS_REG;              /*!< (@ 0x00000008) SRC1 Sample output rate                                    */
-  __IOM uint32_t  SRC1_IN1_REG;                 /*!< (@ 0x0000000C) SRC1 data in 1                                             */
-  __IOM uint32_t  SRC1_IN2_REG;                 /*!< (@ 0x00000010) SRC1 data in 2                                             */
-  __IOM uint32_t  SRC1_OUT1_REG;                /*!< (@ 0x00000014) SRC1 data out 1                                            */
-  __IOM uint32_t  SRC1_OUT2_REG;                /*!< (@ 0x00000018) SRC1 data out 2                                            */
-  __IOM uint32_t  APU_MUX_REG;                  /*!< (@ 0x0000001C) APU mux register                                           */
-  __IOM uint32_t  COEF10_SET1_REG;              /*!< (@ 0x00000020) SRC coefficient 1,0 set 1                                  */
-  __IOM uint32_t  COEF32_SET1_REG;              /*!< (@ 0x00000024) SRC coefficient 3,2 set 1                                  */
-  __IOM uint32_t  COEF54_SET1_REG;              /*!< (@ 0x00000028) SRC coefficient 5,4 set 1                                  */
-  __IOM uint32_t  COEF76_SET1_REG;              /*!< (@ 0x0000002C) SRC coefficient 7,6 set 1                                  */
-  __IOM uint32_t  COEF98_SET1_REG;              /*!< (@ 0x00000030) SRC coefficient 9,8 set 1                                  */
-  __IOM uint32_t  COEF0A_SET1_REG;              /*!< (@ 0x00000034) SRC coefficient 10 set 1                                   */
-  __IM  uint32_t  RESERVED[50];
-  __IOM uint32_t  PCM1_CTRL_REG;                /*!< (@ 0x00000100) PCM1 Control register                                      */
-  __IOM uint32_t  PCM1_IN1_REG;                 /*!< (@ 0x00000104) PCM1 data in 1                                             */
-  __IOM uint32_t  PCM1_IN2_REG;                 /*!< (@ 0x00000108) PCM1 data in 2                                             */
-  __IOM uint32_t  PCM1_OUT1_REG;                /*!< (@ 0x0000010C) PCM1 data out 1                                            */
-  __IOM uint32_t  PCM1_OUT2_REG;                /*!< (@ 0x00000110) PCM1 data out 2                                            */
-} APU_Type;                                     /*!< Size = 276 (0x114)                                                        */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                           CACHE                                           ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief CACHE registers (CACHE)
-  */
-
-typedef struct {                                /*!< (@ 0x100C0000) CACHE Structure                                            */
-  __IOM uint32_t  CACHE_CTRL1_REG;              /*!< (@ 0x00000000) Cache control register 1                                   */
-  __IOM uint32_t  CACHE_LNSIZECFG_REG;          /*!< (@ 0x00000004) Cache line size configuration register                     */
-  __IOM uint32_t  CACHE_ASSOCCFG_REG;           /*!< (@ 0x00000008) Cache associativity configuration register                 */
-  __IM  uint32_t  RESERVED[5];
-  __IOM uint32_t  CACHE_CTRL2_REG;              /*!< (@ 0x00000020) Cache control register 2                                   */
-  __IM  uint32_t  RESERVED1;
-  __IOM uint32_t  CACHE_MRM_HITS_REG;           /*!< (@ 0x00000028) Cache MRM (Miss Rate Monitor) HITS register                */
-  __IOM uint32_t  CACHE_MRM_MISSES_REG;         /*!< (@ 0x0000002C) Cache MRM (Miss Rate Monitor) MISSES register              */
-  __IOM uint32_t  CACHE_MRM_CTRL_REG;           /*!< (@ 0x00000030) Cache MRM (Miss Rate Monitor) CONTROL register             */
-  __IOM uint32_t  CACHE_MRM_TINT_REG;           /*!< (@ 0x00000034) Cache MRM (Miss Rate Monitor) TIME INTERVAL register       */
-  __IOM uint32_t  CACHE_MRM_MISSES_THRES_REG;   /*!< (@ 0x00000038) Cache MRM (Miss Rate Monitor) THRESHOLD register           */
-  __IOM uint32_t  CACHE_MRM_HITS_THRES_REG;     /*!< (@ 0x0000003C) Cache MRM (Miss Rate Monitor) HITS THRESHOLD
-                                                                    register                                                   */
-  __IOM uint32_t  CACHE_FLASH_REG;              /*!< (@ 0x00000040) Cache Flash program size and base address register         */
-  __IM  uint32_t  RESERVED2[3];
-  __IOM uint32_t  SWD_RESET_REG;                /*!< (@ 0x00000050) SWD HW reset control register                              */
-} CACHE_Type;                                   /*!< Size = 84 (0x54)                                                          */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                          CHARGER                                          ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief CHARGER registers (CHARGER)
-  */
-
-typedef struct {                                /*!< (@ 0x50040400) CHARGER Structure                                          */
-  __IOM uint32_t  CHARGER_CTRL_REG;             /*!< (@ 0x00000000) Charger main control register                              */
-  __IOM uint32_t  CHARGER_TEST_CTRL_REG;        /*!< (@ 0x00000004) Charger test control register                              */
-  __IOM uint32_t  CHARGER_STATUS_REG;           /*!< (@ 0x00000008) Charger main status register                               */
-  __IOM uint32_t  CHARGER_VOLTAGE_PARAM_REG;    /*!< (@ 0x0000000C) Charger voltage settings register                          */
-  __IOM uint32_t  CHARGER_CURRENT_PARAM_REG;    /*!< (@ 0x00000010) Charger current settings register                          */
-  __IOM uint32_t  CHARGER_TEMPSET_PARAM_REG;    /*!< (@ 0x00000014) Charger battery temperature settings register              */
-  __IOM uint32_t  CHARGER_PRE_CHARGE_TIMER_REG; /*!< (@ 0x00000018) Maximum pre-charge time limit register                     */
-  __IOM uint32_t  CHARGER_CC_CHARGE_TIMER_REG;  /*!< (@ 0x0000001C) Maximum CC-charge time limit register                      */
-  __IOM uint32_t  CHARGER_CV_CHARGE_TIMER_REG;  /*!< (@ 0x00000020) Maximum CV-charge time limit register                      */
-  __IOM uint32_t  CHARGER_TOTAL_CHARGE_TIMER_REG;/*!< (@ 0x00000024) Maximum total charge time limit register                  */
-  __IOM uint32_t  CHARGER_JEITA_V_CHARGE_REG;   /*!< (@ 0x00000028) JEITA-compliant Charge voltage settings register           */
-  __IOM uint32_t  CHARGER_JEITA_V_PRECHARGE_REG;/*!< (@ 0x0000002C) JEITA-compliant Pre-Charge voltage settings register       */
-  __IOM uint32_t  CHARGER_JEITA_V_REPLENISH_REG;/*!< (@ 0x00000030) JEITA-compliant Replenish settings register                */
-  __IOM uint32_t  CHARGER_JEITA_V_OVP_REG;      /*!< (@ 0x00000034) JEITA-compliant OVP settings register                      */
-  __IOM uint32_t  CHARGER_JEITA_CURRENT_REG;    /*!< (@ 0x00000038) JEITA-compliant current settings register                  */
-  __IOM uint32_t  CHARGER_VBAT_COMP_TIMER_REG;  /*!< (@ 0x0000003C) Main Vbat comparator timer register                        */
-  __IOM uint32_t  CHARGER_VOVP_COMP_TIMER_REG;  /*!< (@ 0x00000040) Vbat OVP comparator timer register                         */
-  __IOM uint32_t  CHARGER_TDIE_COMP_TIMER_REG;  /*!< (@ 0x00000044) Die temperature comparator timer register                  */
-  __IOM uint32_t  CHARGER_TBAT_MON_TIMER_REG;   /*!< (@ 0x00000048) Battery temperature monitor interval timer                 */
-  __IOM uint32_t  CHARGER_TBAT_COMP_TIMER_REG;  /*!< (@ 0x0000004C) Battery temperature (main) comparator timer                */
-  __IOM uint32_t  CHARGER_THOT_COMP_TIMER_REG;  /*!< (@ 0x00000050) Battery temperature comparator timer for 'Hot'
-                                                                    zone                                                       */
-  __IOM uint32_t  CHARGER_PWR_UP_TIMER_REG;     /*!< (@ 0x00000054) Charger power-up (settling) timer                          */
-  __IOM uint32_t  CHARGER_STATE_IRQ_MASK_REG;   /*!< (@ 0x00000058) Mask register of Charger FSM IRQs                          */
-  __IOM uint32_t  CHARGER_ERROR_IRQ_MASK_REG;   /*!< (@ 0x0000005C) Mask register of Charger Error IRQs                        */
-  __IOM uint32_t  CHARGER_STATE_IRQ_STATUS_REG; /*!< (@ 0x00000060) Status register of Charger FSM IRQs                        */
-  __IOM uint32_t  CHARGER_ERROR_IRQ_STATUS_REG; /*!< (@ 0x00000064) Status register of Charger Error IRQs                      */
-  __IOM uint32_t  CHARGER_STATE_IRQ_CLR_REG;    /*!< (@ 0x00000068) Interrupt clear register of Charger FSM IRQs               */
-  __IOM uint32_t  CHARGER_ERROR_IRQ_CLR_REG;    /*!< (@ 0x0000006C) Interrupt clear register of Charger Error IRQs             */
-} CHARGER_Type;                                 /*!< Size = 112 (0x70)                                                         */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                       CHIP_VERSION                                        ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief CHIP_VERSION registers (CHIP_VERSION)
-  */
-
-typedef struct {                                /*!< (@ 0x50040200) CHIP_VERSION Structure                                     */
-  __IOM uint32_t  CHIP_ID1_REG;                 /*!< (@ 0x00000000) Chip identification register 1.                            */
-  __IOM uint32_t  CHIP_ID2_REG;                 /*!< (@ 0x00000004) Chip identification register 2.                            */
-  __IOM uint32_t  CHIP_ID3_REG;                 /*!< (@ 0x00000008) Chip identification register 3.                            */
-  __IOM uint32_t  CHIP_ID4_REG;                 /*!< (@ 0x0000000C) Chip identification register 4.                            */
-  __IOM uint32_t  CHIP_SWC_REG;                 /*!< (@ 0x00000010) Software compatibility register.                           */
-  __IOM uint32_t  CHIP_REVISION_REG;            /*!< (@ 0x00000014) Chip revision register.                                    */
-  __IM  uint32_t  RESERVED[56];
-  __IOM uint32_t  CHIP_TEST1_REG;               /*!< (@ 0x000000F8) Chip test register 1.                                      */
-  __IOM uint32_t  CHIP_TEST2_REG;               /*!< (@ 0x000000FC) Chip test register 2.                                      */
-} CHIP_VERSION_Type;                            /*!< Size = 256 (0x100)                                                        */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                          CRG_COM                                          ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief CRG_COM registers (CRG_COM)
-  */
-
-typedef struct {                                /*!< (@ 0x50020900) CRG_COM Structure                                          */
-  __IM  uint32_t  RESERVED;
-  __IOM uint32_t  CLK_COM_REG;                  /*!< (@ 0x00000004) Peripheral divider register                                */
-  __IOM uint32_t  SET_CLK_COM_REG;              /*!< (@ 0x00000008) Peripheral divider register SET register. Reads
-                                                                    back 0x0000                                                */
-  __IOM uint32_t  RESET_CLK_COM_REG;            /*!< (@ 0x0000000C) Peripheral divider register RESET register. Reads
-                                                                    back 0x0000                                                */
-} CRG_COM_Type;                                 /*!< Size = 16 (0x10)                                                          */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                          CRG_PER                                          ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief CRG_PER registers (CRG_PER)
-  */
-
-typedef struct {                                /*!< (@ 0x50030C00) CRG_PER Structure                                          */
-  __IM  uint32_t  RESERVED;
-  __IOM uint32_t  CLK_PER_REG;                  /*!< (@ 0x00000004) Peripheral divider register                                */
-  __IOM uint32_t  SET_CLK_PER_REG;              /*!< (@ 0x00000008) Peripheral divider register SET register, reads
-                                                                    0x0000                                                     */
-  __IOM uint32_t  RESET_CLK_PER_REG;            /*!< (@ 0x0000000C) Peripheral divider register RESET register, reads
-                                                                    0x0000                                                     */
-  __IM  uint32_t  RESERVED1[12];
-  __IOM uint32_t  PCM_DIV_REG;                  /*!< (@ 0x00000040) PCM divider and enables                                    */
-  __IOM uint32_t  PCM_FDIV_REG;                 /*!< (@ 0x00000044) PCM fractional division register                           */
-  __IOM uint32_t  PDM_DIV_REG;                  /*!< (@ 0x00000048) PDM divider and enables                                    */
-  __IOM uint32_t  SRC_DIV_REG;                  /*!< (@ 0x0000004C) SRC divider and enables                                    */
-} CRG_PER_Type;                                 /*!< Size = 80 (0x50)                                                          */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                          CRG_SYS                                          ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief CRG_SYS registers (CRG_SYS)
-  */
-
-typedef struct {                                /*!< (@ 0x50040500) CRG_SYS Structure                                          */
-  __IOM uint32_t  CLK_SYS_REG;                  /*!< (@ 0x00000000) Peripheral divider register                                */
-  __IOM uint32_t  BATCHECK_REG;                 /*!< (@ 0x00000004) BATCHECK_REG                                               */
-} CRG_SYS_Type;                                 /*!< Size = 8 (0x8)                                                            */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                          CRG_TOP                                          ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief CRG_TOP registers (CRG_TOP)
-  */
-
-typedef struct {                                /*!< (@ 0x50000000) CRG_TOP Structure                                          */
-  __IOM uint32_t  CLK_AMBA_REG;                 /*!< (@ 0x00000000) HCLK, PCLK, divider and clock gates                        */
-  __IM  uint32_t  RESERVED[3];
-  __IOM uint32_t  CLK_RADIO_REG;                /*!< (@ 0x00000010) Radio PLL control register                                 */
-  __IOM uint32_t  CLK_CTRL_REG;                 /*!< (@ 0x00000014) Clock control register                                     */
-  __IOM uint32_t  CLK_TMR_REG;                  /*!< (@ 0x00000018) Clock control for the timers                               */
-  __IOM uint32_t  CLK_SWITCH2XTAL_REG;          /*!< (@ 0x0000001C) Switches clock from RC32M to XTAL32M                       */
-  __IOM uint32_t  PMU_CTRL_REG;                 /*!< (@ 0x00000020) Power Management Unit control register                     */
-  __IOM uint32_t  SYS_CTRL_REG;                 /*!< (@ 0x00000024) System Control register                                    */
-  __IOM uint32_t  SYS_STAT_REG;                 /*!< (@ 0x00000028) System status register                                     */
-  __IM  uint32_t  RESERVED1[4];
-  __IOM uint32_t  CLK_RC32K_REG;                /*!< (@ 0x0000003C) 32 kHz RC oscillator register                              */
-  __IOM uint32_t  CLK_XTAL32K_REG;              /*!< (@ 0x00000040) 32 kHz XTAL oscillator register                            */
-  __IOM uint32_t  CLK_RC32M_REG;                /*!< (@ 0x00000044) Fast RC control register                                   */
-  __IOM uint32_t  CLK_RCX_REG;                  /*!< (@ 0x00000048) RCX-oscillator control register                            */
-  __IOM uint32_t  CLK_RTCDIV_REG;               /*!< (@ 0x0000004C) Divisor for RTC 100Hz clock                                */
-  __IOM uint32_t  BANDGAP_REG;                  /*!< (@ 0x00000050) bandgap trimming                                           */
-  __IOM uint32_t  VBUS_IRQ_MASK_REG;            /*!< (@ 0x00000054) IRQ masking                                                */
-  __IOM uint32_t  VBUS_IRQ_CLEAR_REG;           /*!< (@ 0x00000058) Clear pending IRQ register                                 */
-  __IM  uint32_t  RESERVED2;
-  __IOM uint32_t  BOD_CTRL_REG;                 /*!< (@ 0x00000060) Brown Out Detection control register                       */
-  __IOM uint32_t  BOD_LVL_CTRL0_REG;            /*!< (@ 0x00000064) BOD_LVL_CTRL0_REG                                          */
-  __IOM uint32_t  BOD_LVL_CTRL1_REG;            /*!< (@ 0x00000068) BOD_LVL_CTRL1_REG                                          */
-  __IOM uint32_t  BOD_LVL_CTRL2_REG;            /*!< (@ 0x0000006C) BOD_LVL_CTRL2_REG                                          */
-  __IOM uint32_t  P0_PAD_LATCH_REG;             /*!< (@ 0x00000070) Control the state retention of the GPIO ports              */
-  __IOM uint32_t  P0_SET_PAD_LATCH_REG;         /*!< (@ 0x00000074) Control the state retention of the GPIO ports              */
-  __IOM uint32_t  P0_RESET_PAD_LATCH_REG;       /*!< (@ 0x00000078) Control the state retention of the GPIO ports              */
-  __IOM uint32_t  P1_PAD_LATCH_REG;             /*!< (@ 0x0000007C) Control the state retention of the GPIO ports              */
-  __IOM uint32_t  P1_SET_PAD_LATCH_REG;         /*!< (@ 0x00000080) Control the state retention of the GPIO ports              */
-  __IOM uint32_t  P1_RESET_PAD_LATCH_REG;       /*!< (@ 0x00000084) Control the state retention of the GPIO ports              */
-  __IM  uint32_t  RESERVED3[2];
-  __IOM uint32_t  BOD_STATUS_REG;               /*!< (@ 0x00000090) BOD_STATUS_REG                                             */
-  __IOM uint32_t  POR_VBAT_CTRL_REG;            /*!< (@ 0x00000094) Controls the POR on VBAT                                   */
-  __IOM uint32_t  POR_PIN_REG;                  /*!< (@ 0x00000098) Selects a GPIO pin for POR generation                      */
-  __IOM uint32_t  POR_TIMER_REG;                /*!< (@ 0x0000009C) Time for POR to happen                                     */
-  __IOM uint32_t  LDO_VDDD_HIGH_CTRL_REG;       /*!< (@ 0x000000A0) LDO control register                                       */
-  __IOM uint32_t  BIAS_VREF_SEL_REG;            /*!< (@ 0x000000A4) BIAS_VREF_SEL_REG                                          */
-  __IM  uint32_t  RESERVED4[5];
-  __IOM uint32_t  RESET_STAT_REG;               /*!< (@ 0x000000BC) Reset status register                                      */
-  __IOM uint32_t  RAM_PWR_CTRL_REG;             /*!< (@ 0x000000C0) Control power state of System RAMS                         */
-  __IM  uint32_t  RESERVED5[2];
-  __IOM uint32_t  SECURE_BOOT_REG;              /*!< (@ 0x000000CC) Controls secure booting                                    */
-  __IM  uint32_t  RESERVED6;
-  __IOM uint32_t  DISCHARGE_RAIL_REG;           /*!< (@ 0x000000D4) Immediate rail resetting. There is no LDO/DCDC
-                                                                    gating                                                     */
-  __IM  uint32_t  RESERVED7[5];
-  __IOM uint32_t  ANA_STATUS_REG;               /*!< (@ 0x000000EC) Analog Signals Status Register                             */
-  __IOM uint32_t  POWER_CTRL_REG;               /*!< (@ 0x000000F0) Power control register                                     */
-  __IOM uint32_t  PMU_SLEEP_REG;                /*!< (@ 0x000000F4) Configures the sleep/wakeup strategy                       */
-  __IOM uint32_t  PMU_TRIM_REG;                 /*!< (@ 0x000000F8) LDO trimming register                                      */
-} CRG_TOP_Type;                                 /*!< Size = 252 (0xfc)                                                         */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                         CRG_XTAL                                          ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief CRG_XTAL registers (CRG_XTAL)
-  */
-
-typedef struct {                                /*!< (@ 0x50010000) CRG_XTAL Structure                                         */
-  __IOM uint32_t  CLK_FREQ_TRIM_REG;            /*!< (@ 0x00000000) Xtal frequency trimming register.                          */
-  __IM  uint32_t  RESERVED[3];
-  __IOM uint32_t  TRIM_CTRL_REG;                /*!< (@ 0x00000010) Control trimming of the XTAL32M                            */
-  __IM  uint32_t  RESERVED1;
-  __IOM uint32_t  XTALRDY_CTRL_REG;             /*!< (@ 0x00000018) Control register for XTALRDY IRQ                           */
-  __IOM uint32_t  XTALRDY_STAT_REG;             /*!< (@ 0x0000001C) Difference between XTAL_OK and XTALRDY_IRQ in
-                                                                    LP clock cycles                                            */
-  __IM  uint32_t  RESERVED2[4];
-  __IOM uint32_t  XTAL32M_CTRL0_REG;            /*!< (@ 0x00000030) Control register for XTAL32M                               */
-  __IOM uint32_t  XTAL32M_CTRL1_REG;            /*!< (@ 0x00000034) Control register for XTAL32M                               */
-  __IOM uint32_t  XTAL32M_CTRL2_REG;            /*!< (@ 0x00000038) Control register for XTAL32M                               */
-  __IOM uint32_t  XTAL32M_CTRL3_REG;            /*!< (@ 0x0000003C) Control register for XTAL32M                               */
-  __IOM uint32_t  XTAL32M_CTRL4_REG;            /*!< (@ 0x00000040) Control register for XTAL32M                               */
-  __IM  uint32_t  RESERVED3[3];
-  __IOM uint32_t  XTAL32M_STAT0_REG;            /*!< (@ 0x00000050) Status register for XTAL32M                                */
-  __IOM uint32_t  XTAL32M_STAT1_REG;            /*!< (@ 0x00000054) Status register for XTAL32M                                */
-  __IM  uint32_t  RESERVED4[2];
-  __IOM uint32_t  PLL_SYS_CTRL1_REG;            /*!< (@ 0x00000060) System PLL control register 1.                             */
-  __IOM uint32_t  PLL_SYS_CTRL2_REG;            /*!< (@ 0x00000064) System PLL control register 2.                             */
-  __IOM uint32_t  PLL_SYS_CTRL3_REG;            /*!< (@ 0x00000068) System PLL control register 3.                             */
-  __IM  uint32_t  RESERVED5;
-  __IOM uint32_t  PLL_SYS_STATUS_REG;           /*!< (@ 0x00000070) System PLL status register.                                */
-} CRG_XTAL_Type;                                /*!< Size = 116 (0x74)                                                         */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                           DCDC                                            ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief DCDC registers (DCDC)
-  */
-
-typedef struct {                                /*!< (@ 0x50000300) DCDC Structure                                             */
-  __IM  uint32_t  RESERVED;
-  __IOM uint32_t  DCDC_CTRL1_REG;               /*!< (@ 0x00000004) DCDC First Control Register                                */
-  __IOM uint32_t  DCDC_CTRL2_REG;               /*!< (@ 0x00000008) DCDC Second Control Register                               */
-  __IOM uint32_t  DCDC_V14_REG;                 /*!< (@ 0x0000000C) DCDC V14 Control Register                                  */
-  __IOM uint32_t  DCDC_VDD_REG;                 /*!< (@ 0x00000010) DCDC VDD Control Register                                  */
-  __IOM uint32_t  DCDC_V18_REG;                 /*!< (@ 0x00000014) DCDC V18 Control Register                                  */
-  __IOM uint32_t  DCDC_V18P_REG;                /*!< (@ 0x00000018) DCDC V18P Control Register                                 */
-  __IM  uint32_t  RESERVED1;
-  __IOM uint32_t  DCDC_STATUS1_REG;             /*!< (@ 0x00000020) DCDC First Status Register                                 */
-  __IM  uint32_t  RESERVED2[3];
-  __IOM uint32_t  DCDC_IRQ_STATUS_REG;          /*!< (@ 0x00000030) DCDC Interrupt Status Register                             */
-  __IOM uint32_t  DCDC_IRQ_CLEAR_REG;           /*!< (@ 0x00000034) DCDC Interrupt Clear Register                              */
-  __IOM uint32_t  DCDC_IRQ_MASK_REG;            /*!< (@ 0x00000038) DCDC Interrupt Mask Register                               */
-} DCDC_Type;                                    /*!< Size = 60 (0x3c)                                                          */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                            DMA                                            ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief DMA registers (DMA)
-  */
-
-typedef struct {                                /*!< (@ 0x50040800) DMA Structure                                              */
-  __IOM uint32_t  DMA0_A_START_REG;             /*!< (@ 0x00000000) Start address A of DMA channel 0                           */
-  __IOM uint32_t  DMA0_B_START_REG;             /*!< (@ 0x00000004) Start address B of DMA channel 0                           */
-  __IOM uint32_t  DMA0_INT_REG;                 /*!< (@ 0x00000008) DMA receive interrupt register channel 0                   */
-  __IOM uint32_t  DMA0_LEN_REG;                 /*!< (@ 0x0000000C) DMA receive length register channel 0                      */
-  __IOM uint32_t  DMA0_CTRL_REG;                /*!< (@ 0x00000010) Control register for the DMA channel 0                     */
-  __IOM uint32_t  DMA0_IDX_REG;                 /*!< (@ 0x00000014) Index value of DMA channel 0                               */
-  __IM  uint32_t  RESERVED[2];
-  __IOM uint32_t  DMA1_A_START_REG;             /*!< (@ 0x00000020) Start address A of DMA channel 1                           */
-  __IOM uint32_t  DMA1_B_START_REG;             /*!< (@ 0x00000024) Start address B of DMA channel 1                           */
-  __IOM uint32_t  DMA1_INT_REG;                 /*!< (@ 0x00000028) DMA receive interrupt register channel 1                   */
-  __IOM uint32_t  DMA1_LEN_REG;                 /*!< (@ 0x0000002C) DMA receive length register channel 1                      */
-  __IOM uint32_t  DMA1_CTRL_REG;                /*!< (@ 0x00000030) Control register for the DMA channel 1                     */
-  __IOM uint32_t  DMA1_IDX_REG;                 /*!< (@ 0x00000034) Index value of DMA channel 1                               */
-  __IM  uint32_t  RESERVED1[2];
-  __IOM uint32_t  DMA2_A_START_REG;             /*!< (@ 0x00000040) Start address A of DMA channel 2                           */
-  __IOM uint32_t  DMA2_B_START_REG;             /*!< (@ 0x00000044) Start address B of DMA channel 2                           */
-  __IOM uint32_t  DMA2_INT_REG;                 /*!< (@ 0x00000048) DMA receive interrupt register channel 2                   */
-  __IOM uint32_t  DMA2_LEN_REG;                 /*!< (@ 0x0000004C) DMA receive length register channel 2                      */
-  __IOM uint32_t  DMA2_CTRL_REG;                /*!< (@ 0x00000050) Control register for the DMA channel 2                     */
-  __IOM uint32_t  DMA2_IDX_REG;                 /*!< (@ 0x00000054) Index value of DMA channel 2                               */
-  __IM  uint32_t  RESERVED2[2];
-  __IOM uint32_t  DMA3_A_START_REG;             /*!< (@ 0x00000060) Start address A of DMA channel 3                           */
-  __IOM uint32_t  DMA3_B_START_REG;             /*!< (@ 0x00000064) Start address B of DMA channel 3                           */
-  __IOM uint32_t  DMA3_INT_REG;                 /*!< (@ 0x00000068) DMA receive interrupt register channel 3                   */
-  __IOM uint32_t  DMA3_LEN_REG;                 /*!< (@ 0x0000006C) DMA receive length register channel 3                      */
-  __IOM uint32_t  DMA3_CTRL_REG;                /*!< (@ 0x00000070) Control register for the DMA channel 3                     */
-  __IOM uint32_t  DMA3_IDX_REG;                 /*!< (@ 0x00000074) Index value of DMA channel 3                               */
-  __IM  uint32_t  RESERVED3[2];
-  __IOM uint32_t  DMA4_A_START_REG;             /*!< (@ 0x00000080) Start address A of DMA channel 4                           */
-  __IOM uint32_t  DMA4_B_START_REG;             /*!< (@ 0x00000084) Start address B of DMA channel 4                           */
-  __IOM uint32_t  DMA4_INT_REG;                 /*!< (@ 0x00000088) DMA receive interrupt register channel 4                   */
-  __IOM uint32_t  DMA4_LEN_REG;                 /*!< (@ 0x0000008C) DMA receive length register channel 4                      */
-  __IOM uint32_t  DMA4_CTRL_REG;                /*!< (@ 0x00000090) Control register for the DMA channel 4                     */
-  __IOM uint32_t  DMA4_IDX_REG;                 /*!< (@ 0x00000094) Index value of DMA channel 4                               */
-  __IM  uint32_t  RESERVED4[2];
-  __IOM uint32_t  DMA5_A_START_REG;             /*!< (@ 0x000000A0) Start address A of DMA channel 5                           */
-  __IOM uint32_t  DMA5_B_START_REG;             /*!< (@ 0x000000A4) Start address B of DMA channel 5                           */
-  __IOM uint32_t  DMA5_INT_REG;                 /*!< (@ 0x000000A8) DMA receive interrupt register channel 5                   */
-  __IOM uint32_t  DMA5_LEN_REG;                 /*!< (@ 0x000000AC) DMA receive length register channel 5                      */
-  __IOM uint32_t  DMA5_CTRL_REG;                /*!< (@ 0x000000B0) Control register for the DMA channel 5                     */
-  __IOM uint32_t  DMA5_IDX_REG;                 /*!< (@ 0x000000B4) Index value of DMA channel 5                               */
-  __IM  uint32_t  RESERVED5[2];
-  __IOM uint32_t  DMA6_A_START_REG;             /*!< (@ 0x000000C0) Start address A of DMA channel 6                           */
-  __IOM uint32_t  DMA6_B_START_REG;             /*!< (@ 0x000000C4) Start address B of DMA channel 6                           */
-  __IOM uint32_t  DMA6_INT_REG;                 /*!< (@ 0x000000C8) DMA receive interrupt register channel 6                   */
-  __IOM uint32_t  DMA6_LEN_REG;                 /*!< (@ 0x000000CC) DMA receive length register channel 6                      */
-  __IOM uint32_t  DMA6_CTRL_REG;                /*!< (@ 0x000000D0) Control register for the DMA channel 6                     */
-  __IOM uint32_t  DMA6_IDX_REG;                 /*!< (@ 0x000000D4) Index value of DMA channel 6                               */
-  __IM  uint32_t  RESERVED6[2];
-  __IOM uint32_t  DMA7_A_START_REG;             /*!< (@ 0x000000E0) Start address A of DMA channel 7                           */
-  __IOM uint32_t  DMA7_B_START_REG;             /*!< (@ 0x000000E4) Start address B of DMA channel 7                           */
-  __IOM uint32_t  DMA7_INT_REG;                 /*!< (@ 0x000000E8) DMA receive interrupt register channel 7                   */
-  __IOM uint32_t  DMA7_LEN_REG;                 /*!< (@ 0x000000EC) DMA receive length register channel 7                      */
-  __IOM uint32_t  DMA7_CTRL_REG;                /*!< (@ 0x000000F0) Control register for the DMA channel 7                     */
-  __IOM uint32_t  DMA7_IDX_REG;                 /*!< (@ 0x000000F4) Index value of DMA channel 7                               */
-  __IM  uint32_t  RESERVED7[2];
-  __IOM uint32_t  DMA_REQ_MUX_REG;              /*!< (@ 0x00000100) DMA channel assignments                                    */
-  __IOM uint32_t  DMA_INT_STATUS_REG;           /*!< (@ 0x00000104) DMA interrupt status register                              */
-  __IOM uint32_t  DMA_CLEAR_INT_REG;            /*!< (@ 0x00000108) DMA clear interrupt register                               */
-  __IOM uint32_t  DMA_INT_MASK_REG;             /*!< (@ 0x0000010C) DMA Interrupt mask register                                */
-} DMA_Type;                                     /*!< Size = 272 (0x110)                                                        */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                            DW                                             ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief DW registers (DW)
-  */
-
-typedef struct {                                /*!< (@ 0x30020000) DW Structure                                               */
-  __IOM uint32_t  AHB_DMA_PL1_REG;              /*!< (@ 0x00000000) AHB-DMA layer priority level for RFTP (AHB DMA
-                                                                    layer only)                                                */
-  __IOM uint32_t  AHB_DMA_PL2_REG;              /*!< (@ 0x00000004) AHB-DMA layer priority level for LCD (AHB DMA
-                                                                    layer only)                                                */
-  __IOM uint32_t  AHB_DMA_PL3_REG;              /*!< (@ 0x00000008) AHB-DMA layer Priority level for GEN-DMA (AHB
-                                                                    DMA layer only)                                            */
-  __IOM uint32_t  AHB_DMA_PL4_REG;              /*!< (@ 0x0000000C) AHB-DMA layer Priority level for CRYPTO-DMA (AHB
-                                                                    DMA layer only)                                            */
-  __IM  uint32_t  RESERVED[14];
-  __IOM uint32_t  AHB_DMA_DFLT_MASTER_REG;      /*!< (@ 0x00000048) Default master ID number (AHB DMA layer only)              */
-  __IOM uint32_t  AHB_DMA_WTEN_REG;             /*!< (@ 0x0000004C) Weighted-Token Arbitration Scheme Enable (AHB
-                                                                    DMA layer only)                                            */
-  __IOM uint32_t  AHB_DMA_TCL_REG;              /*!< (@ 0x00000050) Master clock refresh period (AHB DMA layer only)           */
-  __IOM uint32_t  AHB_DMA_CCLM1_REG;            /*!< (@ 0x00000054) USB Master clock tokens (AHB DMA layer only)               */
-  __IOM uint32_t  AHB_DMA_CCLM2_REG;            /*!< (@ 0x00000058) GenDMA Master clock tokens (AHB DMA layer only)            */
-  __IOM uint32_t  AHB_DMA_CCLM3_REG;            /*!< (@ 0x0000005C) CRYPTO Master clock tokens (AHB DMA layer only)            */
-  __IOM uint32_t  AHB_DMA_CCLM4_REG;            /*!< (@ 0x00000060) CRYPTO Master clock tokens (AHB DMA layer only)            */
-  __IM  uint32_t  RESERVED1[11];
-  __IOM uint32_t  AHB_DMA_VERSION_REG;          /*!< (@ 0x00000090) Version ID (AHB DMA layer only)                            */
-} DW_Type;                                      /*!< Size = 148 (0x94)                                                         */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                           GPADC                                           ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief GPADC registers (GPADC)
-  */
-
-typedef struct {                                /*!< (@ 0x50030900) GPADC Structure                                            */
-  __IOM uint32_t  GP_ADC_CTRL_REG;              /*!< (@ 0x00000000) General Purpose ADC Control Register                       */
-  __IOM uint32_t  GP_ADC_CTRL2_REG;             /*!< (@ 0x00000004) General Purpose ADC Second Control Register                */
-  __IOM uint32_t  GP_ADC_CTRL3_REG;             /*!< (@ 0x00000008) General Purpose ADC Third Control Register                 */
-  __IOM uint32_t  GP_ADC_OFFP_REG;              /*!< (@ 0x0000000C) General Purpose ADC Positive Offset Register               */
-  __IOM uint32_t  GP_ADC_OFFN_REG;              /*!< (@ 0x00000010) General Purpose ADC Negative Offset Register               */
-  __IOM uint32_t  GP_ADC_CLEAR_INT_REG;         /*!< (@ 0x00000014) General Purpose ADC Clear Interrupt Register               */
-  __IOM uint32_t  GP_ADC_RESULT_REG;            /*!< (@ 0x00000018) General Purpose ADC Result Register                        */
-} GPADC_Type;                                   /*!< Size = 28 (0x1c)                                                          */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                           GPIO                                            ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief GPIO registers (GPIO)
-  */
-
-typedef struct {                                /*!< (@ 0x50020A00) GPIO Structure                                             */
-  __IOM uint32_t  P0_DATA_REG;                  /*!< (@ 0x00000000) P0 Data input / output Register                            */
-  __IOM uint32_t  P1_DATA_REG;                  /*!< (@ 0x00000004) P1 Data input / output Register                            */
-  __IOM uint32_t  P0_SET_DATA_REG;              /*!< (@ 0x00000008) P0 Set port pins Register                                  */
-  __IOM uint32_t  P1_SET_DATA_REG;              /*!< (@ 0x0000000C) P1 Set port pins Register                                  */
-  __IOM uint32_t  P0_RESET_DATA_REG;            /*!< (@ 0x00000010) P0 Reset port pins Register                                */
-  __IOM uint32_t  P1_RESET_DATA_REG;            /*!< (@ 0x00000014) P1 Reset port pins Register                                */
-  __IOM uint32_t  P0_00_MODE_REG;               /*!< (@ 0x00000018) P0_00 Mode Register                                        */
-  __IOM uint32_t  P0_01_MODE_REG;               /*!< (@ 0x0000001C) P0_01 Mode Register                                        */
-  __IOM uint32_t  P0_02_MODE_REG;               /*!< (@ 0x00000020) P0_02 Mode Register                                        */
-  __IOM uint32_t  P0_03_MODE_REG;               /*!< (@ 0x00000024) P0_03 Mode Register                                        */
-  __IOM uint32_t  P0_04_MODE_REG;               /*!< (@ 0x00000028) P0_04 Mode Register                                        */
-  __IOM uint32_t  P0_05_MODE_REG;               /*!< (@ 0x0000002C) P0_05 Mode Register                                        */
-  __IOM uint32_t  P0_06_MODE_REG;               /*!< (@ 0x00000030) P0_06 Mode Register                                        */
-  __IOM uint32_t  P0_07_MODE_REG;               /*!< (@ 0x00000034) P0_07 Mode Register                                        */
-  __IOM uint32_t  P0_08_MODE_REG;               /*!< (@ 0x00000038) P0_08 Mode Register                                        */
-  __IOM uint32_t  P0_09_MODE_REG;               /*!< (@ 0x0000003C) P0_09 Mode Register                                        */
-  __IOM uint32_t  P0_10_MODE_REG;               /*!< (@ 0x00000040) P0_10 Mode Register                                        */
-  __IOM uint32_t  P0_11_MODE_REG;               /*!< (@ 0x00000044) P0_11 Mode Register                                        */
-  __IOM uint32_t  P0_12_MODE_REG;               /*!< (@ 0x00000048) P0_12 Mode Register                                        */
-  __IOM uint32_t  P0_13_MODE_REG;               /*!< (@ 0x0000004C) P0_13 Mode Register                                        */
-  __IOM uint32_t  P0_14_MODE_REG;               /*!< (@ 0x00000050) P0_14 Mode Register                                        */
-  __IOM uint32_t  P0_15_MODE_REG;               /*!< (@ 0x00000054) P0_15 Mode Register                                        */
-  __IOM uint32_t  P0_16_MODE_REG;               /*!< (@ 0x00000058) P0_16 Mode Register                                        */
-  __IOM uint32_t  P0_17_MODE_REG;               /*!< (@ 0x0000005C) P0_17 Mode Register                                        */
-  __IOM uint32_t  P0_18_MODE_REG;               /*!< (@ 0x00000060) P0_18 Mode Register                                        */
-  __IOM uint32_t  P0_19_MODE_REG;               /*!< (@ 0x00000064) P0_19 Mode Register                                        */
-  __IOM uint32_t  P0_20_MODE_REG;               /*!< (@ 0x00000068) P0_20 Mode Register                                        */
-  __IOM uint32_t  P0_21_MODE_REG;               /*!< (@ 0x0000006C) P0_21 Mode Register                                        */
-  __IOM uint32_t  P0_22_MODE_REG;               /*!< (@ 0x00000070) P0_22 Mode Register                                        */
-  __IOM uint32_t  P0_23_MODE_REG;               /*!< (@ 0x00000074) P0_23 Mode Register                                        */
-  __IOM uint32_t  P0_24_MODE_REG;               /*!< (@ 0x00000078) P0_24 Mode Register                                        */
-  __IOM uint32_t  P0_25_MODE_REG;               /*!< (@ 0x0000007C) P0_25 Mode Register                                        */
-  __IOM uint32_t  P0_26_MODE_REG;               /*!< (@ 0x00000080) P0_26 Mode Register                                        */
-  __IOM uint32_t  P0_27_MODE_REG;               /*!< (@ 0x00000084) P0_27 Mode Register                                        */
-  __IOM uint32_t  P0_28_MODE_REG;               /*!< (@ 0x00000088) P0_28 Mode Register                                        */
-  __IOM uint32_t  P0_29_MODE_REG;               /*!< (@ 0x0000008C) P0_29 Mode Register                                        */
-  __IOM uint32_t  P0_30_MODE_REG;               /*!< (@ 0x00000090) P0_30 Mode Register                                        */
-  __IOM uint32_t  P0_31_MODE_REG;               /*!< (@ 0x00000094) P0_31 Mode Register                                        */
-  __IOM uint32_t  P1_00_MODE_REG;               /*!< (@ 0x00000098) P1_00 Mode Register                                        */
-  __IOM uint32_t  P1_01_MODE_REG;               /*!< (@ 0x0000009C) P1_01 Mode Register                                        */
-  __IOM uint32_t  P1_02_MODE_REG;               /*!< (@ 0x000000A0) P1_02 Mode Register                                        */
-  __IOM uint32_t  P1_03_MODE_REG;               /*!< (@ 0x000000A4) P1_03 Mode Register                                        */
-  __IOM uint32_t  P1_04_MODE_REG;               /*!< (@ 0x000000A8) P1_04 Mode Register                                        */
-  __IOM uint32_t  P1_05_MODE_REG;               /*!< (@ 0x000000AC) P1_05 Mode Register                                        */
-  __IOM uint32_t  P1_06_MODE_REG;               /*!< (@ 0x000000B0) P1_06 Mode Register                                        */
-  __IOM uint32_t  P1_07_MODE_REG;               /*!< (@ 0x000000B4) P1_07 Mode Register                                        */
-  __IOM uint32_t  P1_08_MODE_REG;               /*!< (@ 0x000000B8) P1_08 Mode Register                                        */
-  __IOM uint32_t  P1_09_MODE_REG;               /*!< (@ 0x000000BC) P1_09 Mode Register                                        */
-  __IOM uint32_t  P1_10_MODE_REG;               /*!< (@ 0x000000C0) P1_10 Mode Register                                        */
-  __IOM uint32_t  P1_11_MODE_REG;               /*!< (@ 0x000000C4) P1_11 Mode Register                                        */
-  __IOM uint32_t  P1_12_MODE_REG;               /*!< (@ 0x000000C8) P1_12 Mode Register                                        */
-  __IOM uint32_t  P1_13_MODE_REG;               /*!< (@ 0x000000CC) P1_13 Mode Register                                        */
-  __IOM uint32_t  P1_14_MODE_REG;               /*!< (@ 0x000000D0) P1_14 Mode Register                                        */
-  __IOM uint32_t  P1_15_MODE_REG;               /*!< (@ 0x000000D4) P1_15 Mode Register                                        */
-  __IOM uint32_t  P1_16_MODE_REG;               /*!< (@ 0x000000D8) P1_16 Mode Register                                        */
-  __IOM uint32_t  P1_17_MODE_REG;               /*!< (@ 0x000000DC) P1_17 Mode Register                                        */
-  __IOM uint32_t  P1_18_MODE_REG;               /*!< (@ 0x000000E0) P1_18 Mode Register                                        */
-  __IOM uint32_t  P1_19_MODE_REG;               /*!< (@ 0x000000E4) P1_19 Mode Register                                        */
-  __IOM uint32_t  P1_20_MODE_REG;               /*!< (@ 0x000000E8) P1_20 Mode Register                                        */
-  __IOM uint32_t  P1_21_MODE_REG;               /*!< (@ 0x000000EC) P1_21 Mode Register                                        */
-  __IOM uint32_t  P1_22_MODE_REG;               /*!< (@ 0x000000F0) P1_22 Mode Register                                        */
-  __IOM uint32_t  P0_PADPWR_CTRL_REG;           /*!< (@ 0x000000F4) P0 Output Power Control Register                           */
-  __IOM uint32_t  P1_PADPWR_CTRL_REG;           /*!< (@ 0x000000F8) P1 Output Power Control Register                           */
-  __IOM uint32_t  GPIO_CLK_SEL_REG;             /*!< (@ 0x000000FC) Select which clock to map on ports P0/P1                   */
-  __IOM uint32_t  PAD_WEAK_CTRL_REG;            /*!< (@ 0x00000100) Weak Pads Control Register                                 */
-} GPIO_Type;                                    /*!< Size = 260 (0x104)                                                        */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                           GPREG                                           ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief GPREG registers (GPREG)
-  */
-
-typedef struct {                                /*!< (@ 0x50040300) GPREG Structure                                            */
-  __IOM uint32_t  SET_FREEZE_REG;               /*!< (@ 0x00000000) Controls freezing of various timers/counters
-                                                                    (incl. DMA and USB).                                       */
-  __IOM uint32_t  RESET_FREEZE_REG;             /*!< (@ 0x00000004) Controls unfreezing of various timers/counters
-                                                                    (incl. DMA and USB).                                       */
-  __IOM uint32_t  DEBUG_REG;                    /*!< (@ 0x00000008) Various debug information register.                        */
-  __IOM uint32_t  GP_STATUS_REG;                /*!< (@ 0x0000000C) General purpose system status register.                    */
-  __IOM uint32_t  GP_CONTROL_REG;               /*!< (@ 0x00000010) General purpose system control register.                   */
-  __IM  uint32_t  RESERVED;
-  __IOM uint32_t  USBPAD_REG;                   /*!< (@ 0x00000018) USB pads control register                                  */
-} GPREG_Type;                                   /*!< Size = 28 (0x1c)                                                          */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                            I2C                                            ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief I2C registers (I2C)
-  */
-
-typedef struct {                                /*!< (@ 0x50020600) I2C Structure                                              */
-  __IOM uint32_t  I2C_CON_REG;                  /*!< (@ 0x00000000) I2C Control Register                                       */
-  __IOM uint32_t  I2C_TAR_REG;                  /*!< (@ 0x00000004) I2C Target Address Register                                */
-  __IOM uint32_t  I2C_SAR_REG;                  /*!< (@ 0x00000008) I2C Slave Address Register                                 */
-  __IOM uint32_t  I2C_HS_MADDR_REG;             /*!< (@ 0x0000000C) I2C High Speed Master Mode Code Address Register           */
-  __IOM uint32_t  I2C_DATA_CMD_REG;             /*!< (@ 0x00000010) I2C Rx/Tx Data Buffer and Command Register                 */
-  __IOM uint32_t  I2C_SS_SCL_HCNT_REG;          /*!< (@ 0x00000014) Standard Speed I2C Clock SCL High Count Register           */
-  __IOM uint32_t  I2C_SS_SCL_LCNT_REG;          /*!< (@ 0x00000018) Standard Speed I2C Clock SCL Low Count Register            */
-  __IOM uint32_t  I2C_FS_SCL_HCNT_REG;          /*!< (@ 0x0000001C) Fast Speed I2C Clock SCL High Count Register               */
-  __IOM uint32_t  I2C_FS_SCL_LCNT_REG;          /*!< (@ 0x00000020) Fast Speed I2C Clock SCL Low Count Register                */
-  __IOM uint32_t  I2C_HS_SCL_HCNT_REG;          /*!< (@ 0x00000024) High Speed I2C Clock SCL High Count Register               */
-  __IOM uint32_t  I2C_HS_SCL_LCNT_REG;          /*!< (@ 0x00000028) High Speed I2C Clock SCL Low Count Register                */
-  __IOM uint32_t  I2C_INTR_STAT_REG;            /*!< (@ 0x0000002C) I2C Interrupt Status Register                              */
-  __IOM uint32_t  I2C_INTR_MASK_REG;            /*!< (@ 0x00000030) I2C Interrupt Mask Register                                */
-  __IOM uint32_t  I2C_RAW_INTR_STAT_REG;        /*!< (@ 0x00000034) I2C Raw Interrupt Status Register                          */
-  __IOM uint32_t  I2C_RX_TL_REG;                /*!< (@ 0x00000038) I2C Receive FIFO Threshold Register                        */
-  __IOM uint32_t  I2C_TX_TL_REG;                /*!< (@ 0x0000003C) I2C Transmit FIFO Threshold Register                       */
-  __IOM uint32_t  I2C_CLR_INTR_REG;             /*!< (@ 0x00000040) Clear Combined and Individual Interrupt Register           */
-  __IOM uint32_t  I2C_CLR_RX_UNDER_REG;         /*!< (@ 0x00000044) Clear RX_UNDER Interrupt Register                          */
-  __IOM uint32_t  I2C_CLR_RX_OVER_REG;          /*!< (@ 0x00000048) Clear RX_OVER Interrupt Register                           */
-  __IOM uint32_t  I2C_CLR_TX_OVER_REG;          /*!< (@ 0x0000004C) Clear TX_OVER Interrupt Register                           */
-  __IOM uint32_t  I2C_CLR_RD_REQ_REG;           /*!< (@ 0x00000050) Clear RD_REQ Interrupt Register                            */
-  __IOM uint32_t  I2C_CLR_TX_ABRT_REG;          /*!< (@ 0x00000054) Clear TX_ABRT Interrupt Register                           */
-  __IOM uint32_t  I2C_CLR_RX_DONE_REG;          /*!< (@ 0x00000058) Clear RX_DONE Interrupt Register                           */
-  __IOM uint32_t  I2C_CLR_ACTIVITY_REG;         /*!< (@ 0x0000005C) Clear ACTIVITY Interrupt Register                          */
-  __IOM uint32_t  I2C_CLR_STOP_DET_REG;         /*!< (@ 0x00000060) Clear STOP_DET Interrupt Register                          */
-  __IOM uint32_t  I2C_CLR_START_DET_REG;        /*!< (@ 0x00000064) Clear START_DET Interrupt Register                         */
-  __IOM uint32_t  I2C_CLR_GEN_CALL_REG;         /*!< (@ 0x00000068) Clear GEN_CALL Interrupt Register                          */
-  __IOM uint32_t  I2C_ENABLE_REG;               /*!< (@ 0x0000006C) I2C Enable Register                                        */
-  __IOM uint32_t  I2C_STATUS_REG;               /*!< (@ 0x00000070) I2C Status Register                                        */
-  __IOM uint32_t  I2C_TXFLR_REG;                /*!< (@ 0x00000074) I2C Transmit FIFO Level Register                           */
-  __IOM uint32_t  I2C_RXFLR_REG;                /*!< (@ 0x00000078) I2C Receive FIFO Level Register                            */
-  __IOM uint32_t  I2C_SDA_HOLD_REG;             /*!< (@ 0x0000007C) I2C SDA Hold Time Length Register                          */
-  __IOM uint32_t  I2C_TX_ABRT_SOURCE_REG;       /*!< (@ 0x00000080) I2C Transmit Abort Source Register                         */
-  __IM  uint32_t  RESERVED;
-  __IOM uint32_t  I2C_DMA_CR_REG;               /*!< (@ 0x00000088) DMA Control Register                                       */
-  __IOM uint32_t  I2C_DMA_TDLR_REG;             /*!< (@ 0x0000008C) DMA Transmit Data Level Register                           */
-  __IOM uint32_t  I2C_DMA_RDLR_REG;             /*!< (@ 0x00000090) I2C Receive Data Level Register                            */
-  __IOM uint32_t  I2C_SDA_SETUP_REG;            /*!< (@ 0x00000094) I2C SDA Setup Register                                     */
-  __IOM uint32_t  I2C_ACK_GENERAL_CALL_REG;     /*!< (@ 0x00000098) I2C ACK General Call Register                              */
-  __IOM uint32_t  I2C_ENABLE_STATUS_REG;        /*!< (@ 0x0000009C) I2C Enable Status Register                                 */
-  __IOM uint32_t  I2C_IC_FS_SPKLEN_REG;         /*!< (@ 0x000000A0) I2C SS and FS spike suppression limit Size                 */
-  __IOM uint32_t  I2C_IC_HS_SPKLEN_REG;         /*!< (@ 0x000000A4) I2C HS spike suppression limit Size                        */
-} I2C_Type;                                     /*!< Size = 168 (0xa8)                                                         */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                           I2C2                                            ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief I2C2 registers (I2C2)
-  */
-
-typedef struct {                                /*!< (@ 0x50020700) I2C2 Structure                                             */
-  __IOM uint32_t  I2C2_CON_REG;                 /*!< (@ 0x00000000) I2C Control Register                                       */
-  __IOM uint32_t  I2C2_TAR_REG;                 /*!< (@ 0x00000004) I2C Target Address Register                                */
-  __IOM uint32_t  I2C2_SAR_REG;                 /*!< (@ 0x00000008) I2C Slave Address Register                                 */
-  __IOM uint32_t  I2C2_HS_MADDR_REG;            /*!< (@ 0x0000000C) I2C High Speed Master Mode Code Address Register           */
-  __IOM uint32_t  I2C2_DATA_CMD_REG;            /*!< (@ 0x00000010) I2C Rx/Tx Data Buffer and Command Register                 */
-  __IOM uint32_t  I2C2_SS_SCL_HCNT_REG;         /*!< (@ 0x00000014) Standard Speed I2C Clock SCL High Count Register           */
-  __IOM uint32_t  I2C2_SS_SCL_LCNT_REG;         /*!< (@ 0x00000018) Standard Speed I2C Clock SCL Low Count Register            */
-  __IOM uint32_t  I2C2_FS_SCL_HCNT_REG;         /*!< (@ 0x0000001C) Fast Speed I2C Clock SCL High Count Register               */
-  __IOM uint32_t  I2C2_FS_SCL_LCNT_REG;         /*!< (@ 0x00000020) Fast Speed I2C Clock SCL Low Count Register                */
-  __IOM uint32_t  I2C2_HS_SCL_HCNT_REG;         /*!< (@ 0x00000024) High Speed I2C Clock SCL High Count Register               */
-  __IOM uint32_t  I2C2_HS_SCL_LCNT_REG;         /*!< (@ 0x00000028) High Speed I2C Clock SCL Low Count Register                */
-  __IOM uint32_t  I2C2_INTR_STAT_REG;           /*!< (@ 0x0000002C) I2C Interrupt Status Register                              */
-  __IOM uint32_t  I2C2_INTR_MASK_REG;           /*!< (@ 0x00000030) I2C Interrupt Mask Register                                */
-  __IOM uint32_t  I2C2_RAW_INTR_STAT_REG;       /*!< (@ 0x00000034) I2C Raw Interrupt Status Register                          */
-  __IOM uint32_t  I2C2_RX_TL_REG;               /*!< (@ 0x00000038) I2C Receive FIFO Threshold Register                        */
-  __IOM uint32_t  I2C2_TX_TL_REG;               /*!< (@ 0x0000003C) I2C Transmit FIFO Threshold Register                       */
-  __IOM uint32_t  I2C2_CLR_INTR_REG;            /*!< (@ 0x00000040) Clear Combined and Individual Interrupt Register           */
-  __IOM uint32_t  I2C2_CLR_RX_UNDER_REG;        /*!< (@ 0x00000044) Clear RX_UNDER Interrupt Register                          */
-  __IOM uint32_t  I2C2_CLR_RX_OVER_REG;         /*!< (@ 0x00000048) Clear RX_OVER Interrupt Register                           */
-  __IOM uint32_t  I2C2_CLR_TX_OVER_REG;         /*!< (@ 0x0000004C) Clear TX_OVER Interrupt Register                           */
-  __IOM uint32_t  I2C2_CLR_RD_REQ_REG;          /*!< (@ 0x00000050) Clear RD_REQ Interrupt Register                            */
-  __IOM uint32_t  I2C2_CLR_TX_ABRT_REG;         /*!< (@ 0x00000054) Clear TX_ABRT Interrupt Register                           */
-  __IOM uint32_t  I2C2_CLR_RX_DONE_REG;         /*!< (@ 0x00000058) Clear RX_DONE Interrupt Register                           */
-  __IOM uint32_t  I2C2_CLR_ACTIVITY_REG;        /*!< (@ 0x0000005C) Clear ACTIVITY Interrupt Register                          */
-  __IOM uint32_t  I2C2_CLR_STOP_DET_REG;        /*!< (@ 0x00000060) Clear STOP_DET Interrupt Register                          */
-  __IOM uint32_t  I2C2_CLR_START_DET_REG;       /*!< (@ 0x00000064) Clear START_DET Interrupt Register                         */
-  __IOM uint32_t  I2C2_CLR_GEN_CALL_REG;        /*!< (@ 0x00000068) Clear GEN_CALL Interrupt Register                          */
-  __IOM uint32_t  I2C2_ENABLE_REG;              /*!< (@ 0x0000006C) I2C Enable Register                                        */
-  __IOM uint32_t  I2C2_STATUS_REG;              /*!< (@ 0x00000070) I2C Status Register                                        */
-  __IOM uint32_t  I2C2_TXFLR_REG;               /*!< (@ 0x00000074) I2C Transmit FIFO Level Register                           */
-  __IOM uint32_t  I2C2_RXFLR_REG;               /*!< (@ 0x00000078) I2C Receive FIFO Level Register                            */
-  __IOM uint32_t  I2C2_SDA_HOLD_REG;            /*!< (@ 0x0000007C) I2C SDA Hold Time Length Register                          */
-  __IOM uint32_t  I2C2_TX_ABRT_SOURCE_REG;      /*!< (@ 0x00000080) I2C Transmit Abort Source Register                         */
-  __IM  uint32_t  RESERVED;
-  __IOM uint32_t  I2C2_DMA_CR_REG;              /*!< (@ 0x00000088) DMA Control Register                                       */
-  __IOM uint32_t  I2C2_DMA_TDLR_REG;            /*!< (@ 0x0000008C) DMA Transmit Data Level Register                           */
-  __IOM uint32_t  I2C2_DMA_RDLR_REG;            /*!< (@ 0x00000090) I2C Receive Data Level Register                            */
-  __IOM uint32_t  I2C2_SDA_SETUP_REG;           /*!< (@ 0x00000094) I2C SDA Setup Register                                     */
-  __IOM uint32_t  I2C2_ACK_GENERAL_CALL_REG;    /*!< (@ 0x00000098) I2C ACK General Call Register                              */
-  __IOM uint32_t  I2C2_ENABLE_STATUS_REG;       /*!< (@ 0x0000009C) I2C Enable Status Register                                 */
-  __IOM uint32_t  I2C2_IC_FS_SPKLEN_REG;        /*!< (@ 0x000000A0) I2C SS and FS spike suppression limit Size                 */
-  __IOM uint32_t  I2C2_IC_HS_SPKLEN_REG;        /*!< (@ 0x000000A4) I2C HS spike suppression limit Size                        */
-} I2C2_Type;                                    /*!< Size = 168 (0xa8)                                                         */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                           LCDC                                            ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief LCDC registers (LCDC)
-  */
-
-typedef struct {                                /*!< (@ 0x30030000) LCDC Structure                                             */
-  __IOM uint32_t  LCDC_MODE_REG;                /*!< (@ 0x00000000) Display Mode                                               */
-  __IOM uint32_t  LCDC_CLKCTRL_REG;             /*!< (@ 0x00000004) Clock Divider                                              */
-  __IOM uint32_t  LCDC_BGCOLOR_REG;             /*!< (@ 0x00000008) Background Color                                           */
-  __IOM uint32_t  LCDC_RESXY_REG;               /*!< (@ 0x0000000C) Resolution X,Y                                             */
-  __IM  uint32_t  RESERVED;
-  __IOM uint32_t  LCDC_FRONTPORCHXY_REG;        /*!< (@ 0x00000014) Front Porch X and Y                                        */
-  __IOM uint32_t  LCDC_BLANKINGXY_REG;          /*!< (@ 0x00000018) Blanking X and Y                                           */
-  __IOM uint32_t  LCDC_BACKPORCHXY_REG;         /*!< (@ 0x0000001C) Back Porch X and Y                                         */
-  __IM  uint32_t  RESERVED1[2];
-  __IOM uint32_t  LCDC_DBIB_CFG_REG;            /*!< (@ 0x00000028) MIPI Config Register                                       */
-  __IOM uint32_t  LCDC_GPIO_REG;                /*!< (@ 0x0000002C) General Purpose IO (2-bits)                                */
-  __IOM uint32_t  LCDC_LAYER0_MODE_REG;         /*!< (@ 0x00000030) Layer0 Mode                                                */
-  __IOM uint32_t  LCDC_LAYER0_STARTXY_REG;      /*!< (@ 0x00000034) Layer0 Start XY                                            */
-  __IOM uint32_t  LCDC_LAYER0_SIZEXY_REG;       /*!< (@ 0x00000038) Layer0 Size XY                                             */
-  __IOM uint32_t  LCDC_LAYER0_BASEADDR_REG;     /*!< (@ 0x0000003C) Layer0 Base Addr                                           */
-  __IOM uint32_t  LCDC_LAYER0_STRIDE_REG;       /*!< (@ 0x00000040) Layer0 Stride                                              */
-  __IOM uint32_t  LCDC_LAYER0_RESXY_REG;        /*!< (@ 0x00000044) Layer0 Res XY                                              */
-  __IM  uint32_t  RESERVED2[18];
-  __IOM uint32_t  LCDC_JDI_RESXY_REG;           /*!< (@ 0x00000090) Resolution XY for the JDI parallel I/F                     */
-  __IOM uint32_t  LCDC_JDI_FBX_BLANKING_REG;    /*!< (@ 0x00000094) Horizontal front/back blanking (hck half periods)          */
-  __IOM uint32_t  LCDC_JDI_FBY_BLANKING_REG;    /*!< (@ 0x00000098) Vertical front/back blanking (vck half periods)            */
-  __IOM uint32_t  LCDC_JDI_HCK_WIDTH_REG;       /*!< (@ 0x0000009C) HCK high/low width                                         */
-  __IOM uint32_t  LCDC_JDI_XRST_WIDTH_REG;      /*!< (@ 0x000000A0) XRST width                                                 */
-  __IOM uint32_t  LCDC_JDI_VST_DELAY_REG;       /*!< (@ 0x000000A4) XRST-to-VST delay                                          */
-  __IOM uint32_t  LCDC_JDI_VST_WIDTH_REG;       /*!< (@ 0x000000A8) VST width                                                  */
-  __IOM uint32_t  LCDC_JDI_VCK_DELAY_REG;       /*!< (@ 0x000000AC) XRST-to-VCK delay                                          */
-  __IOM uint32_t  LCDC_JDI_HST_DELAY_REG;       /*!< (@ 0x000000B0) VCK-to-HST delay                                           */
-  __IOM uint32_t  LCDC_JDI_HST_WIDTH_REG;       /*!< (@ 0x000000B4) HST width                                                  */
-  __IOM uint32_t  LCDC_JDI_ENB_START_HLINE_REG; /*!< (@ 0x000000B8) ENB start horizontal line                                  */
-  __IOM uint32_t  LCDC_JDI_ENB_END_HLINE_REG;   /*!< (@ 0x000000BC) ENB end horizontal line                                    */
-  __IOM uint32_t  LCDC_JDI_ENB_START_CLK_REG;   /*!< (@ 0x000000C0) ENB start delay                                            */
-  __IOM uint32_t  LCDC_JDI_ENB_WIDTH_CLK_REG;   /*!< (@ 0x000000C4) ENB width                                                  */
-  __IM  uint32_t  RESERVED3[8];
-  __IOM uint32_t  LCDC_DBIB_CMD_REG;            /*!< (@ 0x000000E8) MIPI DBIB Command Register                                 */
-  __IM  uint32_t  RESERVED4[2];
-  __IOM uint32_t  LCDC_IDREG_REG;               /*!< (@ 0x000000F4) Identification Register                                    */
-  __IOM uint32_t  LCDC_INTERRUPT_REG;           /*!< (@ 0x000000F8) Interrupt Register                                         */
-  __IOM uint32_t  LCDC_STATUS_REG;              /*!< (@ 0x000000FC) Status Register                                            */
-  __IM  uint32_t  RESERVED5[33];
-  __IOM uint32_t  LCDC_CRC_REG;                 /*!< (@ 0x00000184) CRC check                                                  */
-  __IOM uint32_t  LCDC_LAYER0_OFFSETX_REG;      /*!< (@ 0x00000188) Layer0 OffsetX and DMA prefetch                            */
-} LCDC_Type;                                    /*!< Size = 396 (0x18c)                                                        */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                            LRA                                            ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief LRA registers (LRA)
-  */
-
-typedef struct {                                /*!< (@ 0x50030A00) LRA Structure                                              */
-  __IOM uint32_t  LRA_CTRL1_REG;                /*!< (@ 0x00000000) General Purpose LRA Control Register                       */
-  __IOM uint32_t  LRA_CTRL2_REG;                /*!< (@ 0x00000004) General Purpose LRA Control Register                       */
-  __IOM uint32_t  LRA_CTRL3_REG;                /*!< (@ 0x00000008) General Purpose LRA Control Register                       */
-  __IOM uint32_t  LRA_FLT_SMP1_REG;             /*!< (@ 0x0000000C) LRA Sample Register                                        */
-  __IOM uint32_t  LRA_FLT_SMP2_REG;             /*!< (@ 0x00000010) LRA Sample Register                                        */
-  __IOM uint32_t  LRA_FLT_SMP3_REG;             /*!< (@ 0x00000014) LRA Sample Register                                        */
-  __IOM uint32_t  LRA_FLT_SMP4_REG;             /*!< (@ 0x00000018) LRA Sample Register                                        */
-  __IOM uint32_t  LRA_FLT_SMP5_REG;             /*!< (@ 0x0000001C) LRA Sample Register                                        */
-  __IOM uint32_t  LRA_FLT_SMP6_REG;             /*!< (@ 0x00000020) LRA Sample Register                                        */
-  __IOM uint32_t  LRA_FLT_SMP7_REG;             /*!< (@ 0x00000024) LRA Sample Register                                        */
-  __IOM uint32_t  LRA_FLT_SMP8_REG;             /*!< (@ 0x00000028) LRA Sample Register                                        */
-  __IOM uint32_t  LRA_FLT_COEF1_REG;            /*!< (@ 0x0000002C) LRA Filter Coefficient Register                            */
-  __IOM uint32_t  LRA_FLT_COEF2_REG;            /*!< (@ 0x00000030) LRA Filter Coefficient Register                            */
-  __IOM uint32_t  LRA_FLT_COEF3_REG;            /*!< (@ 0x00000034) LRA Filter Coefficient Register                            */
-  __IOM uint32_t  LRA_BRD_LS_REG;               /*!< (@ 0x00000038) LRA Bridge Register                                        */
-  __IOM uint32_t  LRA_BRD_HS_REG;               /*!< (@ 0x0000003C) LRA Bridge Register                                        */
-  __IOM uint32_t  LRA_BRD_STAT_REG;             /*!< (@ 0x00000040) LRA Bridge Staus Register                                  */
-  __IOM uint32_t  LRA_ADC_CTRL1_REG;            /*!< (@ 0x00000044) General Purpose ADC Control Register                       */
-  __IM  uint32_t  RESERVED[2];
-  __IOM uint32_t  LRA_ADC_RESULT_REG;           /*!< (@ 0x00000050) General Purpose ADC Result Register                        */
-  __IOM uint32_t  LRA_LDO_REG;                  /*!< (@ 0x00000054) LRA LDO Regsiter                                           */
-  __IOM uint32_t  LRA_DFT_REG;                  /*!< (@ 0x00000058) LRA test Register                                          */
-} LRA_Type;                                     /*!< Size = 92 (0x5c)                                                          */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                          MEMCTRL                                          ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief MEMCTRL registers (MEMCTRL)
-  */
-
-typedef struct {                                /*!< (@ 0x50050000) MEMCTRL Structure                                          */
-  __IM  uint32_t  RESERVED;
-  __IOM uint32_t  MEM_PRIO_REG;                 /*!< (@ 0x00000004) Priority Control Register                                  */
-  __IOM uint32_t  MEM_STALL_REG;                /*!< (@ 0x00000008) Maximum Stall cycles Control Register                      */
-  __IOM uint32_t  MEM_STATUS_REG;               /*!< (@ 0x0000000C) Memory Arbiter Status Register                             */
-  __IOM uint32_t  MEM_STATUS2_REG;              /*!< (@ 0x00000010) RAM cells Status Register                                  */
-  __IM  uint32_t  RESERVED1[3];
-  __IOM uint32_t  CMI_CODE_BASE_REG;            /*!< (@ 0x00000020) CMAC code Base Address Register                            */
-  __IOM uint32_t  CMI_DATA_BASE_REG;            /*!< (@ 0x00000024) CMAC data Base Address Register                            */
-  __IOM uint32_t  CMI_SHARED_BASE_REG;          /*!< (@ 0x00000028) CMAC shared data Base Address Register                     */
-  __IOM uint32_t  CMI_END_REG;                  /*!< (@ 0x0000002C) CMAC end Address Register                                  */
-  __IOM uint32_t  SNC_BASE_REG;                 /*!< (@ 0x00000030) Sensor Node Controller Base Address Register               */
-  __IM  uint32_t  RESERVED2[16];
-  __IOM uint32_t  BUSY_SET_REG;                 /*!< (@ 0x00000074) BSR Set Register                                           */
-  __IOM uint32_t  BUSY_RESET_REG;               /*!< (@ 0x00000078) BSR Reset Register                                         */
-  __IOM uint32_t  BUSY_STAT_REG;                /*!< (@ 0x0000007C) BSR Status Register                                        */
-} MEMCTRL_Type;                                 /*!< Size = 128 (0x80)                                                         */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                           OTPC                                            ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief OTPC registers (OTPC)
-  */
-
-typedef struct {                                /*!< (@ 0x30070000) OTPC Structure                                             */
-  __IOM uint32_t  OTPC_MODE_REG;                /*!< (@ 0x00000000) Mode register                                              */
-  __IOM uint32_t  OTPC_STAT_REG;                /*!< (@ 0x00000004) Status register                                            */
-  __IOM uint32_t  OTPC_PADDR_REG;               /*!< (@ 0x00000008) The address of the word that will be programmed,
-                                                                    when the PROG mode is used.                                */
-  __IOM uint32_t  OTPC_PWORD_REG;               /*!< (@ 0x0000000C) The 32-bit word that will be programmed, when
-                                                                    the PROG mode is used.                                     */
-  __IOM uint32_t  OTPC_TIM1_REG;                /*!< (@ 0x00000010) Various timing parameters of the OTP cell.                 */
-  __IOM uint32_t  OTPC_TIM2_REG;                /*!< (@ 0x00000014) Various timing parameters of the OTP cell.                 */
-} OTPC_Type;                                    /*!< Size = 24 (0x18)                                                          */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                            PDC                                            ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief PDC registers (PDC)
-  */
-
-typedef struct {                                /*!< (@ 0x50000200) PDC Structure                                              */
-  __IOM uint32_t  PDC_CTRL0_REG;                /*!< (@ 0x00000000) PDC control register                                       */
-  __IOM uint32_t  PDC_CTRL1_REG;                /*!< (@ 0x00000004) PDC control register                                       */
-  __IOM uint32_t  PDC_CTRL2_REG;                /*!< (@ 0x00000008) PDC control register                                       */
-  __IOM uint32_t  PDC_CTRL3_REG;                /*!< (@ 0x0000000C) PDC control register                                       */
-  __IOM uint32_t  PDC_CTRL4_REG;                /*!< (@ 0x00000010) PDC control register                                       */
-  __IOM uint32_t  PDC_CTRL5_REG;                /*!< (@ 0x00000014) PDC control register                                       */
-  __IOM uint32_t  PDC_CTRL6_REG;                /*!< (@ 0x00000018) PDC control register                                       */
-  __IOM uint32_t  PDC_CTRL7_REG;                /*!< (@ 0x0000001C) PDC control register                                       */
-  __IOM uint32_t  PDC_CTRL8_REG;                /*!< (@ 0x00000020) PDC control register                                       */
-  __IOM uint32_t  PDC_CTRL9_REG;                /*!< (@ 0x00000024) PDC control register                                       */
-  __IOM uint32_t  PDC_CTRL10_REG;               /*!< (@ 0x00000028) PDC control register                                       */
-  __IOM uint32_t  PDC_CTRL11_REG;               /*!< (@ 0x0000002C) PDC control register                                       */
-  __IOM uint32_t  PDC_CTRL12_REG;               /*!< (@ 0x00000030) PDC control register                                       */
-  __IOM uint32_t  PDC_CTRL13_REG;               /*!< (@ 0x00000034) PDC control register                                       */
-  __IOM uint32_t  PDC_CTRL14_REG;               /*!< (@ 0x00000038) PDC control register                                       */
-  __IOM uint32_t  PDC_CTRL15_REG;               /*!< (@ 0x0000003C) PDC control register                                       */
-  __IM  uint32_t  RESERVED[16];
-  __IOM uint32_t  PDC_ACKNOWLEDGE_REG;          /*!< (@ 0x00000080) Clear a pending PDC bit                                    */
-  __IOM uint32_t  PDC_PENDING_REG;              /*!< (@ 0x00000084) Shows any pending wakup event                              */
-  __IOM uint32_t  PDC_PENDING_SNC_REG;          /*!< (@ 0x00000088) Shows any pending IRQ to SNC                               */
-  __IOM uint32_t  PDC_PENDING_CM33_REG;         /*!< (@ 0x0000008C) Shows any pending IRQ to CM33                              */
-  __IOM uint32_t  PDC_PENDING_CMAC_REG;         /*!< (@ 0x00000090) Shows any pending IRQ to CM33                              */
-  __IOM uint32_t  PDC_SET_PENDING_REG;          /*!< (@ 0x00000094) Set a pending PDC bit                                      */
-} PDC_Type;                                     /*!< Size = 152 (0x98)                                                         */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                          PWMLED                                           ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief PWMLED registers (PWMLED)
-  */
-
-typedef struct {                                /*!< (@ 0x50030500) PWMLED Structure                                           */
-  __IOM uint32_t  PWMLED_DUTY_CYCLE_LED1_REG;   /*!< (@ 0x00000000) Defines duty cycle for PWM1                                */
-  __IOM uint32_t  PWMLED_DUTY_CYCLE_LED2_REG;   /*!< (@ 0x00000004) Defines duty cycle for PWM2                                */
-  __IOM uint32_t  PWMLED_FREQUENCY_REG;         /*!< (@ 0x00000008) Defines the PWM frequecny                                  */
-  __IOM uint32_t  PWMLED_CTRL_REG;              /*!< (@ 0x0000000C) PWM Control register                                       */
-} PWMLED_Type;                                  /*!< Size = 16 (0x10)                                                          */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                           QSPIC                                           ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief QSPIC registers (QSPIC)
-  */
-
-typedef struct {                                /*!< (@ 0x38000000) QSPIC Structure                                            */
-  __IOM uint32_t  QSPIC_CTRLBUS_REG;            /*!< (@ 0x00000000) SPI Bus control register for the Manual mode               */
-  __IOM uint32_t  QSPIC_CTRLMODE_REG;           /*!< (@ 0x00000004) Mode Control register                                      */
-  __IOM uint32_t  QSPIC_RECVDATA_REG;           /*!< (@ 0x00000008) Received data for the Manual mode                          */
-  __IOM uint32_t  QSPIC_BURSTCMDA_REG;          /*!< (@ 0x0000000C) The way of reading in Auto mode (command register
-                                                                    A)                                                         */
-  __IOM uint32_t  QSPIC_BURSTCMDB_REG;          /*!< (@ 0x00000010) The way of reading in Auto mode (command register
-                                                                    B)                                                         */
-  __IOM uint32_t  QSPIC_STATUS_REG;             /*!< (@ 0x00000014) The status register of the QSPI controller                 */
-  __IOM uint32_t  QSPIC_WRITEDATA_REG;          /*!< (@ 0x00000018) Write data to SPI Bus for the Manual mode                  */
-  __IOM uint32_t  QSPIC_READDATA_REG;           /*!< (@ 0x0000001C) Read data from SPI Bus for the Manual mode                 */
-  __IOM uint32_t  QSPIC_DUMMYDATA_REG;          /*!< (@ 0x00000020) Send dummy clocks to SPI Bus for the Manual mode           */
-  __IOM uint32_t  QSPIC_ERASECTRL_REG;          /*!< (@ 0x00000024) QSPI Erase control register                                */
-  __IOM uint32_t  QSPIC_ERASECMDA_REG;          /*!< (@ 0x00000028) The way of erasing in Auto mode (command register
-                                                                    A)                                                         */
-  __IOM uint32_t  QSPIC_ERASECMDB_REG;          /*!< (@ 0x0000002C) The way of erasing in Auto mode (command register
-                                                                    B)                                                         */
-  __IOM uint32_t  QSPIC_BURSTBRK_REG;           /*!< (@ 0x00000030) Read break sequence in Auto mode                           */
-  __IOM uint32_t  QSPIC_STATUSCMD_REG;          /*!< (@ 0x00000034) The way of reading the status of external device
-                                                                    in Auto mode                                               */
-  __IOM uint32_t  QSPIC_CHCKERASE_REG;          /*!< (@ 0x00000038) Check erase progress in Auto mode                          */
-  __IOM uint32_t  QSPIC_GP_REG;                 /*!< (@ 0x0000003C) QSPI General Purpose control register                      */
-  __IOM uint32_t  QSPIC_UCODE_START;            /*!< (@ 0x00000040) QSPIC uCode memory                                         */
-  __IM  uint32_t  RESERVED[15];
-  __IOM uint32_t  QSPIC_CTR_CTRL_REG;           /*!< (@ 0x00000080) Control register for the decryption engine of
-                                                                    the QSPIC                                                  */
-  __IOM uint32_t  QSPIC_CTR_SADDR_REG;          /*!< (@ 0x00000084) Start address of the encrypted content in the
-                                                                    QSPI flash                                                 */
-  __IOM uint32_t  QSPIC_CTR_EADDR_REG;          /*!< (@ 0x00000088) End address of the encrypted content in the QSPI
-                                                                    flash                                                      */
-  __IOM uint32_t  QSPIC_CTR_NONCE_0_3_REG;      /*!< (@ 0x0000008C) Nonce bytes 0 to 3 for the AES-CTR algorithm               */
-  __IOM uint32_t  QSPIC_CTR_NONCE_4_7_REG;      /*!< (@ 0x00000090) Nonce bytes 4 to 7 for the AES-CTR algorithm               */
-  __IOM uint32_t  QSPIC_CTR_KEY_0_3_REG;        /*!< (@ 0x00000094) Key bytes 0 to 3 for the AES-CTR algorithm                 */
-  __IOM uint32_t  QSPIC_CTR_KEY_4_7_REG;        /*!< (@ 0x00000098) Key bytes 4 to 7 for the AES-CTR algorithm                 */
-  __IOM uint32_t  QSPIC_CTR_KEY_8_11_REG;       /*!< (@ 0x0000009C) Key bytes 8 to 11 for the AES-CTR algorithm                */
-  __IOM uint32_t  QSPIC_CTR_KEY_12_15_REG;      /*!< (@ 0x000000A0) Key bytes 12 to 15 for the AES-CTR algorithm               */
-  __IOM uint32_t  QSPIC_CTR_KEY_16_19_REG;      /*!< (@ 0x000000A4) Key bytes 16 to 19 for the AES-CTR algorithm               */
-  __IOM uint32_t  QSPIC_CTR_KEY_20_23_REG;      /*!< (@ 0x000000A8) Key bytes 20 to 23 for the AES-CTR algorithm               */
-  __IOM uint32_t  QSPIC_CTR_KEY_24_27_REG;      /*!< (@ 0x000000AC) Key bytes 24 to 27 for the AES-CTR algorithm               */
-  __IOM uint32_t  QSPIC_CTR_KEY_28_31_REG;      /*!< (@ 0x000000B0) Key bytes 28 to 31 for the AES-CTR algorithm               */
-} QSPIC_Type;                                   /*!< Size = 180 (0xb4)                                                         */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                          QSPIC2                                           ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief QSPIC2 registers (QSPIC2)
-  */
-
-typedef struct {                                /*!< (@ 0x34000000) QSPIC2 Structure                                           */
-  __IOM uint32_t  QSPIC2_CTRLBUS_REG;           /*!< (@ 0x00000000) SPI Bus control register for the Manual mode               */
-  __IOM uint32_t  QSPIC2_CTRLMODE_REG;          /*!< (@ 0x00000004) Mode control register                                      */
-  __IOM uint32_t  QSPIC2_RECVDATA_REG;          /*!< (@ 0x00000008) Received data for the Manual mode                          */
-  __IOM uint32_t  QSPIC2_BURSTCMDA_REG;         /*!< (@ 0x0000000C) The way of reading in Auto mode (command register
-                                                                    A)                                                         */
-  __IOM uint32_t  QSPIC2_BURSTCMDB_REG;         /*!< (@ 0x00000010) The way of reading in Auto mode (command register
-                                                                    B)                                                         */
-  __IOM uint32_t  QSPIC2_STATUS_REG;            /*!< (@ 0x00000014) The status register of the QSPI controller                 */
-  __IOM uint32_t  QSPIC2_WRITEDATA_REG;         /*!< (@ 0x00000018) Write data to SPI Bus for the Manual mode                  */
-  __IOM uint32_t  QSPIC2_READDATA_REG;          /*!< (@ 0x0000001C) Read data from SPI Bus for the Manual mode                 */
-  __IOM uint32_t  QSPIC2_DUMMYDATA_REG;         /*!< (@ 0x00000020) Send dummy clocks to SPI Bus for the Manual mode           */
-  __IOM uint32_t  QSPIC2_ERASECTRL_REG;         /*!< (@ 0x00000024) Erase control register                                     */
-  __IOM uint32_t  QSPIC2_ERASECMDA_REG;         /*!< (@ 0x00000028) The way of erasing in Auto mode (command register
-                                                                    A)                                                         */
-  __IOM uint32_t  QSPIC2_ERASECMDB_REG;         /*!< (@ 0x0000002C) The way of erasing in Auto mode (command register
-                                                                    B)                                                         */
-  __IOM uint32_t  QSPIC2_BURSTBRK_REG;          /*!< (@ 0x00000030) Read break sequence in Auto mode                           */
-  __IOM uint32_t  QSPIC2_STATUSCMD_REG;         /*!< (@ 0x00000034) The way of reading the status of external device
-                                                                    in Auto mode                                               */
-  __IOM uint32_t  QSPIC2_CHCKERASE_REG;         /*!< (@ 0x00000038) Check erase progress in Auto mode                          */
-  __IOM uint32_t  QSPIC2_GP_REG;                /*!< (@ 0x0000003C) General purpose QSPIC2 register                            */
-  __IOM uint32_t  QSPIC2_AWRITECMD_REG;         /*!< (@ 0x00000040) The way of writing in Auto mode when the external
-                                                                    device is a serial SRAM                                    */
-  __IOM uint32_t  QSPIC2_MEMBLEN_REG;           /*!< (@ 0x00000044) External memory burst length configuration                 */
-} QSPIC2_Type;                                  /*!< Size = 72 (0x48)                                                          */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                           RFMON                                           ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief RFMON registers (RFMON)
-  */
-
-typedef struct {                                /*!< (@ 0x50040600) RFMON Structure                                            */
-  __IOM uint32_t  RFMON_CTRL_REG;               /*!< (@ 0x00000000) Control register                                           */
-  __IOM uint32_t  RFMON_ADDR_REG;               /*!< (@ 0x00000004) AHB master start address                                   */
-  __IOM uint32_t  RFMON_LEN_REG;                /*!< (@ 0x00000008) Data length register                                       */
-  __IOM uint32_t  RFMON_STAT_REG;               /*!< (@ 0x0000000C) Status register                                            */
-  __IOM uint32_t  RFMON_CRV_ADDR_REG;           /*!< (@ 0x00000010) AHB master current address                                 */
-  __IOM uint32_t  RFMON_CRV_LEN_REG;            /*!< (@ 0x00000014) The remaining data to be transferred                       */
-} RFMON_Type;                                   /*!< Size = 24 (0x18)                                                          */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                            RTC                                            ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief RTC registers (RTC)
-  */
-
-typedef struct {                                /*!< (@ 0x50000400) RTC Structure                                              */
-  __IOM uint32_t  RTC_CONTROL_REG;              /*!< (@ 0x00000000) RTC Control Register                                       */
-  __IOM uint32_t  RTC_HOUR_MODE_REG;            /*!< (@ 0x00000004) RTC Hour Mode Register                                     */
-  __IOM uint32_t  RTC_TIME_REG;                 /*!< (@ 0x00000008) RTC Time Register                                          */
-  __IOM uint32_t  RTC_CALENDAR_REG;             /*!< (@ 0x0000000C) RTC Calendar Register                                      */
-  __IOM uint32_t  RTC_TIME_ALARM_REG;           /*!< (@ 0x00000010) RTC Time Alarm Register                                    */
-  __IOM uint32_t  RTC_CALENDAR_ALARM_REG;       /*!< (@ 0x00000014) RTC Calendar Alram Register                                */
-  __IOM uint32_t  RTC_ALARM_ENABLE_REG;         /*!< (@ 0x00000018) RTC Alarm Enable Register                                  */
-  __IOM uint32_t  RTC_EVENT_FLAGS_REG;          /*!< (@ 0x0000001C) RTC Event Flags Register                                   */
-  __IOM uint32_t  RTC_INTERRUPT_ENABLE_REG;     /*!< (@ 0x00000020) RTC Interrupt Enable Register                              */
-  __IOM uint32_t  RTC_INTERRUPT_DISABLE_REG;    /*!< (@ 0x00000024) RTC Interrupt Disable Register                             */
-  __IOM uint32_t  RTC_INTERRUPT_MASK_REG;       /*!< (@ 0x00000028) RTC Interrupt Mask Register                                */
-  __IOM uint32_t  RTC_STATUS_REG;               /*!< (@ 0x0000002C) RTC Status Register                                        */
-  __IOM uint32_t  RTC_KEEP_RTC_REG;             /*!< (@ 0x00000030) RTC Keep RTC Register                                      */
-  __IM  uint32_t  RESERVED[19];
-  __IOM uint32_t  RTC_EVENT_CTRL_REG;           /*!< (@ 0x00000080) RTC Event Control Register                                 */
-  __IOM uint32_t  RTC_MOTOR_EVENT_PERIOD_REG;   /*!< (@ 0x00000084) RTC Motor Event Period Register                            */
-  __IOM uint32_t  RTC_PDC_EVENT_PERIOD_REG;     /*!< (@ 0x00000088) RTC PDC Event Period Register                              */
-  __IOM uint32_t  RTC_PDC_EVENT_CLEAR_REG;      /*!< (@ 0x0000008C) RTC PDC Event Clear Register                               */
-  __IOM uint32_t  RTC_MOTOR_EVENT_CNT_REG;      /*!< (@ 0x00000090) RTC Motor Event Counter Register                           */
-  __IOM uint32_t  RTC_PDC_EVENT_CNT_REG;        /*!< (@ 0x00000094) RTC PDC Event Counter Register                             */
-} RTC_Type;                                     /*!< Size = 152 (0x98)                                                         */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                           SDADC                                           ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief SDADC registers (SDADC)
-  */
-
-typedef struct {                                /*!< (@ 0x50020800) SDADC Structure                                            */
-  __IOM uint32_t  SDADC_CTRL_REG;               /*!< (@ 0x00000000) Sigma Delta ADC Control Register                           */
-  __IM  uint32_t  RESERVED;
-  __IOM uint32_t  SDADC_TEST_REG;               /*!< (@ 0x00000008) Sigma Delta ADC Test Register                              */
-  __IOM uint32_t  SDADC_GAIN_CORR_REG;          /*!< (@ 0x0000000C) Sigma Delta ADC Gain Correction Register                   */
-  __IOM uint32_t  SDADC_OFFS_CORR_REG;          /*!< (@ 0x00000010) Sigma Delta ADC Offset Correction Register                 */
-  __IOM uint32_t  SDADC_CLEAR_INT_REG;          /*!< (@ 0x00000014) Sigma Delta ADC Clear Interrupt Register                   */
-  __IOM uint32_t  SDADC_RESULT_REG;             /*!< (@ 0x00000018) Sigma Delta ADC Result Register                            */
-} SDADC_Type;                                   /*!< Size = 28 (0x1c)                                                          */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                          SMOTOR                                           ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief SMOTOR registers (SMOTOR)
-  */
-
-typedef struct {                                /*!< (@ 0x50030E00) SMOTOR Structure                                           */
-  __IOM uint32_t  SMOTOR_CTRL_REG;              /*!< (@ 0x00000000) Motor control register                                     */
-  __IOM uint32_t  PG0_CTRL_REG;                 /*!< (@ 0x00000004) Pattern generator 0 control register                       */
-  __IOM uint32_t  PG1_CTRL_REG;                 /*!< (@ 0x00000008) Pattern generator 1 control register                       */
-  __IOM uint32_t  PG2_CTRL_REG;                 /*!< (@ 0x0000000C) Pattern generator 2 control register                       */
-  __IOM uint32_t  PG3_CTRL_REG;                 /*!< (@ 0x00000010) Pattern generator 3 control register                       */
-  __IOM uint32_t  PG4_CTRL_REG;                 /*!< (@ 0x00000014) Pattern generator 4 control register                       */
-  __IOM uint32_t  SMOTOR_TRIGGER_REG;           /*!< (@ 0x00000018) Motor controller trigger register                          */
-  __IM  uint32_t  RESERVED;
-  __IOM uint32_t  SMOTOR_CMD_FIFO_REG;          /*!< (@ 0x00000020) Motor control command FIFO register                        */
-  __IOM uint32_t  SMOTOR_CMD_READ_PTR_REG;      /*!< (@ 0x00000024) Command read pointer register                              */
-  __IOM uint32_t  SMOTOR_CMD_WRITE_PTR_REG;     /*!< (@ 0x00000028) Command write pointer register                             */
-  __IOM uint32_t  SMOTOR_STATUS_REG;            /*!< (@ 0x0000002C) Motor controller status register                           */
-  __IOM uint32_t  SMOTOR_IRQ_CLEAR_REG;         /*!< (@ 0x00000030) Motor control IRQ clear register                           */
-  __IM  uint32_t  RESERVED1[3];
-  __IOM uint32_t  WAVETABLE_BASE;               /*!< (@ 0x00000040) Base address of the wavetable                              */
-  __IM  uint32_t  RESERVED2[15];
-  __IOM uint32_t  CMD_TABLE_BASE;               /*!< (@ 0x00000080) Base address of the command table                          */
-} SMOTOR_Type;                                  /*!< Size = 132 (0x84)                                                         */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                            SNC                                            ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief SNC registers (SNC)
-  */
-
-typedef struct {                                /*!< (@ 0x50020C00) SNC Structure                                              */
-  __IOM uint32_t  SNC_CTRL_REG;                 /*!< (@ 0x00000000) Sensor Node Control Register                               */
-  __IOM uint32_t  SNC_STATUS_REG;               /*!< (@ 0x00000004) Sensor Node Status Register                                */
-  __IOM uint32_t  SNC_LP_TIMER_REG;             /*!< (@ 0x00000008) Sensor Node Low-Power Timer Register                       */
-  __IOM uint32_t  SNC_PC_REG;                   /*!< (@ 0x0000000C) Sensor Node Program Counter                                */
-  __IOM uint32_t  SNC_R1_REG;                   /*!< (@ 0x00000010) Sensor Node core - Operand 1 Register                      */
-  __IOM uint32_t  SNC_R2_REG;                   /*!< (@ 0x00000014) Sensor Node core - Operand 2 Register                      */
-  __IOM uint32_t  SNC_TMP1_REG;                 /*!< (@ 0x00000018) Sensor Node core - Temporary Register 1                    */
-  __IOM uint32_t  SNC_TMP2_REG;                 /*!< (@ 0x0000001C) Sensor Node core - Temporary Register 2                    */
-} SNC_Type;                                     /*!< Size = 32 (0x20)                                                          */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                            SPI                                            ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief SPI registers (SPI)
-  */
-
-typedef struct {                                /*!< (@ 0x50020300) SPI Structure                                              */
-  __IOM uint32_t  SPI_CTRL_REG;                 /*!< (@ 0x00000000) SPI control register 0                                     */
-  __IOM uint32_t  SPI_RX_TX_REG;                /*!< (@ 0x00000004) SPI RX/TX register0                                        */
-  __IOM uint32_t  SPI_CLEAR_INT_REG;            /*!< (@ 0x00000008) SPI clear interrupt register                               */
-} SPI_Type;                                     /*!< Size = 12 (0xc)                                                           */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                           SPI2                                            ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief SPI2 registers (SPI2)
-  */
-
-typedef struct {                                /*!< (@ 0x50020400) SPI2 Structure                                             */
-  __IOM uint32_t  SPI2_CTRL_REG;                /*!< (@ 0x00000000) SPI control register 0                                     */
-  __IOM uint32_t  SPI2_RX_TX_REG;               /*!< (@ 0x00000004) SPI RX/TX register0                                        */
-  __IOM uint32_t  SPI2_CLEAR_INT_REG;           /*!< (@ 0x00000008) SPI clear interrupt register                               */
-} SPI2_Type;                                    /*!< Size = 12 (0xc)                                                           */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                         SYS_WDOG                                          ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief SYS_WDOG registers (SYS_WDOG)
-  */
-
-typedef struct {                                /*!< (@ 0x50000700) SYS_WDOG Structure                                         */
-  __IOM uint32_t  WATCHDOG_REG;                 /*!< (@ 0x00000000) Watchdog timer register.                                   */
-  __IOM uint32_t  WATCHDOG_CTRL_REG;            /*!< (@ 0x00000004) Watchdog control register.                                 */
-} SYS_WDOG_Type;                                /*!< Size = 8 (0x8)                                                            */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                           TIMER                                           ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief TIMER registers (TIMER)
-  */
-
-typedef struct {                                /*!< (@ 0x50010200) TIMER Structure                                            */
-  __IOM uint32_t  TIMER_CTRL_REG;               /*!< (@ 0x00000000) Timer control register                                     */
-  __IOM uint32_t  TIMER_TIMER_VAL_REG;          /*!< (@ 0x00000004) Timer counter value                                        */
-  __IOM uint32_t  TIMER_STATUS_REG;             /*!< (@ 0x00000008) Timer status register                                      */
-  __IOM uint32_t  TIMER_GPIO1_CONF_REG;         /*!< (@ 0x0000000C) Timer gpio1 selection                                      */
-  __IOM uint32_t  TIMER_GPIO2_CONF_REG;         /*!< (@ 0x00000010) Timer gpio2 selection                                      */
-  __IOM uint32_t  TIMER_RELOAD_REG;             /*!< (@ 0x00000014) Timer reload value and Delay in shot mode                  */
-  __IOM uint32_t  TIMER_SHOTWIDTH_REG;          /*!< (@ 0x00000018) Timer Shot duration in shot mode                           */
-  __IOM uint32_t  TIMER_PRESCALER_REG;          /*!< (@ 0x0000001C) Timer prescaler value                                      */
-  __IOM uint32_t  TIMER_CAPTURE_GPIO1_REG;      /*!< (@ 0x00000020) Timer value for event on GPIO1                             */
-  __IOM uint32_t  TIMER_CAPTURE_GPIO2_REG;      /*!< (@ 0x00000024) Timer value for event on GPIO2                             */
-  __IOM uint32_t  TIMER_PRESCALER_VAL_REG;      /*!< (@ 0x00000028) Timer prescaler counter valuew                             */
-  __IOM uint32_t  TIMER_PWM_FREQ_REG;           /*!< (@ 0x0000002C) Timer pwm frequency register                               */
-  __IOM uint32_t  TIMER_PWM_DC_REG;             /*!< (@ 0x00000030) Timer pwm dc register                                      */
-  __IOM uint32_t  TIMER_GPIO3_CONF_REG;         /*!< (@ 0x00000034) Timer gpio3 selection                                      */
-  __IOM uint32_t  TIMER_GPIO4_CONF_REG;         /*!< (@ 0x00000038) Timer gpio4 selection                                      */
-  __IOM uint32_t  TIMER_CAPTURE_GPIO3_REG;      /*!< (@ 0x0000003C) Timer value for event on GPIO1                             */
-  __IOM uint32_t  TIMER_CAPTURE_GPIO4_REG;      /*!< (@ 0x00000040) Timer value for event on GPIO1                             */
-  __IOM uint32_t  TIMER_CLEAR_GPIO_EVENT_REG;   /*!< (@ 0x00000044) Timer clear gpio event register                            */
-  __IOM uint32_t  TIMER_CLEAR_IRQ_REG;          /*!< (@ 0x00000048) Timer clear interrupt                                      */
-} TIMER_Type;                                   /*!< Size = 76 (0x4c)                                                          */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                          TIMER2                                           ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief TIMER2 registers (TIMER2)
-  */
-
-typedef struct {                                /*!< (@ 0x50010300) TIMER2 Structure                                           */
-  __IOM uint32_t  TIMER2_CTRL_REG;              /*!< (@ 0x00000000) Timer control register                                     */
-  __IOM uint32_t  TIMER2_TIMER_VAL_REG;         /*!< (@ 0x00000004) Timer counter value                                        */
-  __IOM uint32_t  TIMER2_STATUS_REG;            /*!< (@ 0x00000008) Timer status register                                      */
-  __IOM uint32_t  TIMER2_GPIO1_CONF_REG;        /*!< (@ 0x0000000C) Timer gpio1 selection                                      */
-  __IOM uint32_t  TIMER2_GPIO2_CONF_REG;        /*!< (@ 0x00000010) Timer gpio2 selection                                      */
-  __IOM uint32_t  TIMER2_RELOAD_REG;            /*!< (@ 0x00000014) Timer reload value and Delay in shot mode                  */
-  __IOM uint32_t  TIMER2_SHOTWIDTH_REG;         /*!< (@ 0x00000018) Timer Shot duration in shot mode                           */
-  __IOM uint32_t  TIMER2_PRESCALER_REG;         /*!< (@ 0x0000001C) Timer prescaler value                                      */
-  __IOM uint32_t  TIMER2_CAPTURE_GPIO1_REG;     /*!< (@ 0x00000020) Timer value for event on GPIO1                             */
-  __IOM uint32_t  TIMER2_CAPTURE_GPIO2_REG;     /*!< (@ 0x00000024) Timer value for event on GPIO2                             */
-  __IOM uint32_t  TIMER2_PRESCALER_VAL_REG;     /*!< (@ 0x00000028) Timer prescaler counter valuew                             */
-  __IOM uint32_t  TIMER2_PWM_FREQ_REG;          /*!< (@ 0x0000002C) Timer pwm frequency register                               */
-  __IOM uint32_t  TIMER2_PWM_DC_REG;            /*!< (@ 0x00000030) Timer pwm dc register                                      */
-  __IOM uint32_t  TIMER2_CLEAR_IRQ_REG;         /*!< (@ 0x00000034) Timer clear interrupt                                      */
-} TIMER2_Type;                                  /*!< Size = 56 (0x38)                                                          */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                          TIMER3                                           ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief TIMER3 registers (TIMER3)
-  */
-
-typedef struct {                                /*!< (@ 0x50040A00) TIMER3 Structure                                           */
-  __IOM uint32_t  TIMER3_CTRL_REG;              /*!< (@ 0x00000000) Timer control register                                     */
-  __IOM uint32_t  TIMER3_TIMER_VAL_REG;         /*!< (@ 0x00000004) Timer counter value                                        */
-  __IOM uint32_t  TIMER3_STATUS_REG;            /*!< (@ 0x00000008) Timer status register                                      */
-  __IOM uint32_t  TIMER3_GPIO1_CONF_REG;        /*!< (@ 0x0000000C) Timer gpio1 selection                                      */
-  __IOM uint32_t  TIMER3_GPIO2_CONF_REG;        /*!< (@ 0x00000010) Timer gpio2 selection                                      */
-  __IOM uint32_t  TIMER3_RELOAD_REG;            /*!< (@ 0x00000014) Timer reload value and Delay in shot mode                  */
-  __IM  uint32_t  RESERVED;
-  __IOM uint32_t  TIMER3_PRESCALER_REG;         /*!< (@ 0x0000001C) Timer prescaler value                                      */
-  __IOM uint32_t  TIMER3_CAPTURE_GPIO1_REG;     /*!< (@ 0x00000020) Timer value for event on GPIO1                             */
-  __IOM uint32_t  TIMER3_CAPTURE_GPIO2_REG;     /*!< (@ 0x00000024) Timer value for event on GPIO2                             */
-  __IOM uint32_t  TIMER3_PRESCALER_VAL_REG;     /*!< (@ 0x00000028) Timer prescaler counter valuew                             */
-  __IOM uint32_t  TIMER3_PWM_FREQ_REG;          /*!< (@ 0x0000002C) Timer pwm frequency register                               */
-  __IOM uint32_t  TIMER3_PWM_DC_REG;            /*!< (@ 0x00000030) Timer pwm dc register                                      */
-  __IOM uint32_t  TIMER3_CLEAR_IRQ_REG;         /*!< (@ 0x00000034) Timer clear interrupt                                      */
-} TIMER3_Type;                                  /*!< Size = 56 (0x38)                                                          */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                          TIMER4                                           ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief TIMER4 registers (TIMER4)
-  */
-
-typedef struct {                                /*!< (@ 0x50040B00) TIMER4 Structure                                           */
-  __IOM uint32_t  TIMER4_CTRL_REG;              /*!< (@ 0x00000000) Timer control register                                     */
-  __IOM uint32_t  TIMER4_TIMER_VAL_REG;         /*!< (@ 0x00000004) Timer counter value                                        */
-  __IOM uint32_t  TIMER4_STATUS_REG;            /*!< (@ 0x00000008) Timer status register                                      */
-  __IOM uint32_t  TIMER4_GPIO1_CONF_REG;        /*!< (@ 0x0000000C) Timer gpio1 selection                                      */
-  __IOM uint32_t  TIMER4_GPIO2_CONF_REG;        /*!< (@ 0x00000010) Timer gpio2 selection                                      */
-  __IOM uint32_t  TIMER4_RELOAD_REG;            /*!< (@ 0x00000014) Timer reload value and Delay in shot mode                  */
-  __IM  uint32_t  RESERVED;
-  __IOM uint32_t  TIMER4_PRESCALER_REG;         /*!< (@ 0x0000001C) Timer prescaler value                                      */
-  __IOM uint32_t  TIMER4_CAPTURE_GPIO1_REG;     /*!< (@ 0x00000020) Timer value for event on GPIO1                             */
-  __IOM uint32_t  TIMER4_CAPTURE_GPIO2_REG;     /*!< (@ 0x00000024) Timer value for event on GPIO2                             */
-  __IOM uint32_t  TIMER4_PRESCALER_VAL_REG;     /*!< (@ 0x00000028) Timer prescaler counter valuew                             */
-  __IOM uint32_t  TIMER4_PWM_FREQ_REG;          /*!< (@ 0x0000002C) Timer pwm frequency register                               */
-  __IOM uint32_t  TIMER4_PWM_DC_REG;            /*!< (@ 0x00000030) Timer pwm dc register                                      */
-  __IOM uint32_t  TIMER4_CLEAR_IRQ_REG;         /*!< (@ 0x00000034) Timer clear interrupt                                      */
-} TIMER4_Type;                                  /*!< Size = 56 (0x38)                                                          */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                           TRNG                                            ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief TRNG registers (TRNG)
-  */
-
-typedef struct {                                /*!< (@ 0x50040C00) TRNG Structure                                             */
-  __IOM uint32_t  TRNG_CTRL_REG;                /*!< (@ 0x00000000) TRNG control register                                      */
-  __IOM uint32_t  TRNG_FIFOLVL_REG;             /*!< (@ 0x00000004) TRNG FIFO level register                                   */
-  __IOM uint32_t  TRNG_VER_REG;                 /*!< (@ 0x00000008) TRNG Version register                                      */
-} TRNG_Type;                                    /*!< Size = 12 (0xc)                                                           */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                           UART                                            ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief UART registers (UART)
-  */
-
-typedef struct {                                /*!< (@ 0x50020000) UART Structure                                             */
-  __IOM uint32_t  UART_RBR_THR_DLL_REG;         /*!< (@ 0x00000000) Receive Buffer Register                                    */
-  __IOM uint32_t  UART_IER_DLH_REG;             /*!< (@ 0x00000004) Interrupt Enable Register                                  */
-  __IOM uint32_t  UART_IIR_FCR_REG;             /*!< (@ 0x00000008) Interrupt Identification Register/FIFO Control
-                                                                    Register                                                   */
-  __IOM uint32_t  UART_LCR_REG;                 /*!< (@ 0x0000000C) Line Control Register                                      */
-  __IOM uint32_t  UART_MCR_REG;                 /*!< (@ 0x00000010) Modem Control Register                                     */
-  __IOM uint32_t  UART_LSR_REG;                 /*!< (@ 0x00000014) Line Status Register                                       */
-  __IM  uint32_t  RESERVED;
-  __IOM uint32_t  UART_SCR_REG;                 /*!< (@ 0x0000001C) Scratchpad Register                                        */
-  __IM  uint32_t  RESERVED1[4];
-  __IOM uint32_t  UART_SRBR_STHR0_REG;          /*!< (@ 0x00000030) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART_SRBR_STHR1_REG;          /*!< (@ 0x00000034) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART_SRBR_STHR2_REG;          /*!< (@ 0x00000038) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART_SRBR_STHR3_REG;          /*!< (@ 0x0000003C) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART_SRBR_STHR4_REG;          /*!< (@ 0x00000040) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART_SRBR_STHR5_REG;          /*!< (@ 0x00000044) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART_SRBR_STHR6_REG;          /*!< (@ 0x00000048) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART_SRBR_STHR7_REG;          /*!< (@ 0x0000004C) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART_SRBR_STHR8_REG;          /*!< (@ 0x00000050) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART_SRBR_STHR9_REG;          /*!< (@ 0x00000054) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART_SRBR_STHR10_REG;         /*!< (@ 0x00000058) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART_SRBR_STHR11_REG;         /*!< (@ 0x0000005C) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART_SRBR_STHR12_REG;         /*!< (@ 0x00000060) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART_SRBR_STHR13_REG;         /*!< (@ 0x00000064) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART_SRBR_STHR14_REG;         /*!< (@ 0x00000068) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART_SRBR_STHR15_REG;         /*!< (@ 0x0000006C) Shadow Receive/Transmit Buffer Register                    */
-  __IM  uint32_t  RESERVED2[3];
-  __IOM uint32_t  UART_USR_REG;                 /*!< (@ 0x0000007C) UART Status register.                                      */
-  __IOM uint32_t  UART_TFL_REG;                 /*!< (@ 0x00000080) Transmit FIFO Level                                        */
-  __IOM uint32_t  UART_RFL_REG;                 /*!< (@ 0x00000084) Receive FIFO Level.                                        */
-  __IOM uint32_t  UART_SRR_REG;                 /*!< (@ 0x00000088) Software Reset Register.                                   */
-  __IM  uint32_t  RESERVED3;
-  __IOM uint32_t  UART_SBCR_REG;                /*!< (@ 0x00000090) Shadow Break Control Register                              */
-  __IOM uint32_t  UART_SDMAM_REG;               /*!< (@ 0x00000094) Shadow DMA Mode                                            */
-  __IOM uint32_t  UART_SFE_REG;                 /*!< (@ 0x00000098) Shadow FIFO Enable                                         */
-  __IOM uint32_t  UART_SRT_REG;                 /*!< (@ 0x0000009C) Shadow RCVR Trigger                                        */
-  __IOM uint32_t  UART_STET_REG;                /*!< (@ 0x000000A0) Shadow TX Empty Trigger                                    */
-  __IOM uint32_t  UART_HTX_REG;                 /*!< (@ 0x000000A4) Halt TX                                                    */
-  __IOM uint32_t  UART_DMASA_REG;               /*!< (@ 0x000000A8) DMA Software Acknowledge                                   */
-  __IM  uint32_t  RESERVED4[5];
-  __IOM uint32_t  UART_DLF_REG;                 /*!< (@ 0x000000C0) Divisor Latch Fraction Register                            */
-  __IM  uint32_t  RESERVED5[13];
-  __IOM uint32_t  UART_UCV_REG;                 /*!< (@ 0x000000F8) Component Version                                          */
-  __IOM uint32_t  UART_CTR_REG;                 /*!< (@ 0x000000FC) Component Type Register                                    */
-} UART_Type;                                    /*!< Size = 256 (0x100)                                                        */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                           UART2                                           ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief UART2 registers (UART2)
-  */
-
-typedef struct {                                /*!< (@ 0x50020100) UART2 Structure                                            */
-  __IOM uint32_t  UART2_RBR_THR_DLL_REG;        /*!< (@ 0x00000000) Receive Buffer Register                                    */
-  __IOM uint32_t  UART2_IER_DLH_REG;            /*!< (@ 0x00000004) Interrupt Enable Register                                  */
-  __IOM uint32_t  UART2_IIR_FCR_REG;            /*!< (@ 0x00000008) Interrupt Identification Register/FIFO Control
-                                                                    Register                                                   */
-  __IOM uint32_t  UART2_LCR_REG;                /*!< (@ 0x0000000C) Line Control Register                                      */
-  __IOM uint32_t  UART2_MCR_REG;                /*!< (@ 0x00000010) Modem Control Register                                     */
-  __IOM uint32_t  UART2_LSR_REG;                /*!< (@ 0x00000014) Line Status Register                                       */
-  __IOM uint32_t  UART2_MSR_REG;                /*!< (@ 0x00000018) Modem Status Register                                      */
-  __IOM uint32_t  UART2_SCR_REG;                /*!< (@ 0x0000001C) Scratchpad Register                                        */
-  __IM  uint32_t  RESERVED[4];
-  __IOM uint32_t  UART2_SRBR_STHR0_REG;         /*!< (@ 0x00000030) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART2_SRBR_STHR1_REG;         /*!< (@ 0x00000034) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART2_SRBR_STHR2_REG;         /*!< (@ 0x00000038) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART2_SRBR_STHR3_REG;         /*!< (@ 0x0000003C) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART2_SRBR_STHR4_REG;         /*!< (@ 0x00000040) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART2_SRBR_STHR5_REG;         /*!< (@ 0x00000044) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART2_SRBR_STHR6_REG;         /*!< (@ 0x00000048) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART2_SRBR_STHR7_REG;         /*!< (@ 0x0000004C) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART2_SRBR_STHR8_REG;         /*!< (@ 0x00000050) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART2_SRBR_STHR9_REG;         /*!< (@ 0x00000054) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART2_SRBR_STHR10_REG;        /*!< (@ 0x00000058) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART2_SRBR_STHR11_REG;        /*!< (@ 0x0000005C) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART2_SRBR_STHR12_REG;        /*!< (@ 0x00000060) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART2_SRBR_STHR13_REG;        /*!< (@ 0x00000064) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART2_SRBR_STHR14_REG;        /*!< (@ 0x00000068) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART2_SRBR_STHR15_REG;        /*!< (@ 0x0000006C) Shadow Receive/Transmit Buffer Register                    */
-  __IM  uint32_t  RESERVED1[3];
-  __IOM uint32_t  UART2_USR_REG;                /*!< (@ 0x0000007C) UART Status register.                                      */
-  __IOM uint32_t  UART2_TFL_REG;                /*!< (@ 0x00000080) Transmit FIFO Level                                        */
-  __IOM uint32_t  UART2_RFL_REG;                /*!< (@ 0x00000084) Receive FIFO Level.                                        */
-  __IOM uint32_t  UART2_SRR_REG;                /*!< (@ 0x00000088) Software Reset Register.                                   */
-  __IOM uint32_t  UART2_SRTS_REG;               /*!< (@ 0x0000008C) Shadow Request to Send                                     */
-  __IOM uint32_t  UART2_SBCR_REG;               /*!< (@ 0x00000090) Shadow Break Control Register                              */
-  __IOM uint32_t  UART2_SDMAM_REG;              /*!< (@ 0x00000094) Shadow DMA Mode                                            */
-  __IOM uint32_t  UART2_SFE_REG;                /*!< (@ 0x00000098) Shadow FIFO Enable                                         */
-  __IOM uint32_t  UART2_SRT_REG;                /*!< (@ 0x0000009C) Shadow RCVR Trigger                                        */
-  __IOM uint32_t  UART2_STET_REG;               /*!< (@ 0x000000A0) Shadow TX Empty Trigger                                    */
-  __IOM uint32_t  UART2_HTX_REG;                /*!< (@ 0x000000A4) Halt TX                                                    */
-  __IOM uint32_t  UART2_DMASA_REG;              /*!< (@ 0x000000A8) DMA Software Acknowledge                                   */
-  __IM  uint32_t  RESERVED2[5];
-  __IOM uint32_t  UART2_DLF_REG;                /*!< (@ 0x000000C0) Divisor Latch Fraction Register                            */
-  __IOM uint32_t  UART2_RAR_REG;                /*!< (@ 0x000000C4) Receive Address Register                                   */
-  __IOM uint32_t  UART2_TAR_REG;                /*!< (@ 0x000000C8) Transmit Address Register                                  */
-  __IOM uint32_t  UART2_LCR_EXT;                /*!< (@ 0x000000CC) Line Extended Control Register                             */
-  __IM  uint32_t  RESERVED3[10];
-  __IOM uint32_t  UART2_UCV_REG;                /*!< (@ 0x000000F8) Component Version                                          */
-  __IOM uint32_t  UART2_CTR_REG;                /*!< (@ 0x000000FC) Component Type Register                                    */
-} UART2_Type;                                   /*!< Size = 256 (0x100)                                                        */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                           UART3                                           ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief UART3 registers (UART3)
-  */
-
-typedef struct {                                /*!< (@ 0x50020200) UART3 Structure                                            */
-  __IOM uint32_t  UART3_RBR_THR_DLL_REG;        /*!< (@ 0x00000000) Receive Buffer Register                                    */
-  __IOM uint32_t  UART3_IER_DLH_REG;            /*!< (@ 0x00000004) Interrupt Enable Register                                  */
-  __IOM uint32_t  UART3_IIR_FCR_REG;            /*!< (@ 0x00000008) Interrupt Identification Register/FIFO Control
-                                                                    Register                                                   */
-  __IOM uint32_t  UART3_LCR_REG;                /*!< (@ 0x0000000C) Line Control Register                                      */
-  __IOM uint32_t  UART3_MCR_REG;                /*!< (@ 0x00000010) Modem Control Register                                     */
-  __IOM uint32_t  UART3_LSR_REG;                /*!< (@ 0x00000014) Line Status Register                                       */
-  __IOM uint32_t  UART3_MSR_REG;                /*!< (@ 0x00000018) Modem Status Register                                      */
-  __IOM uint32_t  UART3_CONFIG_REG;             /*!< (@ 0x0000001C) ISO7816 Config Register                                    */
-  __IM  uint32_t  RESERVED[4];
-  __IOM uint32_t  UART3_SRBR_STHR0_REG;         /*!< (@ 0x00000030) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART3_SRBR_STHR1_REG;         /*!< (@ 0x00000034) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART3_SRBR_STHR2_REG;         /*!< (@ 0x00000038) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART3_SRBR_STHR3_REG;         /*!< (@ 0x0000003C) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART3_SRBR_STHR4_REG;         /*!< (@ 0x00000040) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART3_SRBR_STHR5_REG;         /*!< (@ 0x00000044) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART3_SRBR_STHR6_REG;         /*!< (@ 0x00000048) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART3_SRBR_STHR7_REG;         /*!< (@ 0x0000004C) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART3_SRBR_STHR8_REG;         /*!< (@ 0x00000050) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART3_SRBR_STHR9_REG;         /*!< (@ 0x00000054) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART3_SRBR_STHR10_REG;        /*!< (@ 0x00000058) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART3_SRBR_STHR11_REG;        /*!< (@ 0x0000005C) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART3_SRBR_STHR12_REG;        /*!< (@ 0x00000060) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART3_SRBR_STHR13_REG;        /*!< (@ 0x00000064) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART3_SRBR_STHR14_REG;        /*!< (@ 0x00000068) Shadow Receive/Transmit Buffer Register                    */
-  __IOM uint32_t  UART3_SRBR_STHR15_REG;        /*!< (@ 0x0000006C) Shadow Receive/Transmit Buffer Register                    */
-  __IM  uint32_t  RESERVED1[3];
-  __IOM uint32_t  UART3_USR_REG;                /*!< (@ 0x0000007C) UART Status register.                                      */
-  __IOM uint32_t  UART3_TFL_REG;                /*!< (@ 0x00000080) Transmit FIFO Level                                        */
-  __IOM uint32_t  UART3_RFL_REG;                /*!< (@ 0x00000084) Receive FIFO Level.                                        */
-  __IOM uint32_t  UART3_SRR_REG;                /*!< (@ 0x00000088) Software Reset Register.                                   */
-  __IOM uint32_t  UART3_SRTS_REG;               /*!< (@ 0x0000008C) Shadow Request to Send                                     */
-  __IOM uint32_t  UART3_SBCR_REG;               /*!< (@ 0x00000090) Shadow Break Control Register                              */
-  __IOM uint32_t  UART3_SDMAM_REG;              /*!< (@ 0x00000094) Shadow DMA Mode                                            */
-  __IOM uint32_t  UART3_SFE_REG;                /*!< (@ 0x00000098) Shadow FIFO Enable                                         */
-  __IOM uint32_t  UART3_SRT_REG;                /*!< (@ 0x0000009C) Shadow RCVR Trigger                                        */
-  __IOM uint32_t  UART3_STET_REG;               /*!< (@ 0x000000A0) Shadow TX Empty Trigger                                    */
-  __IOM uint32_t  UART3_HTX_REG;                /*!< (@ 0x000000A4) Halt TX                                                    */
-  __IOM uint32_t  UART3_DMASA_REG;              /*!< (@ 0x000000A8) DMA Software Acknowledge                                   */
-  __IM  uint32_t  RESERVED2[5];
-  __IOM uint32_t  UART3_DLF_REG;                /*!< (@ 0x000000C0) Divisor Latch Fraction Register                            */
-  __IOM uint32_t  UART3_RAR_REG;                /*!< (@ 0x000000C4) Receive Address Register                                   */
-  __IOM uint32_t  UART3_TAR_REG;                /*!< (@ 0x000000C8) Transmit Address Register                                  */
-  __IOM uint32_t  UART3_LCR_EXT;                /*!< (@ 0x000000CC) Line Extended Control Register                             */
-  __IM  uint32_t  RESERVED3[4];
-  __IOM uint32_t  UART3_CTRL_REG;               /*!< (@ 0x000000E0) ISO7816 Control Register                                   */
-  __IOM uint32_t  UART3_TIMER_REG;              /*!< (@ 0x000000E4) ISO7816 Timer Register                                     */
-  __IOM uint32_t  UART3_ERR_CTRL_REG;           /*!< (@ 0x000000E8) ISO7816 Error Signal Control Register                      */
-  __IOM uint32_t  UART3_IRQ_STATUS_REG;         /*!< (@ 0x000000EC) ISO7816 Interrupt Status Register                          */
-  __IM  uint32_t  RESERVED4[2];
-  __IOM uint32_t  UART3_UCV_REG;                /*!< (@ 0x000000F8) Component Version                                          */
-  __IOM uint32_t  UART3_CTR_REG;                /*!< (@ 0x000000FC) Component Type Register                                    */
-} UART3_Type;                                   /*!< Size = 256 (0x100)                                                        */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                            USB                                            ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief USB registers (USB)
-  */
-
-typedef struct {                                /*!< (@ 0x50040000) USB Structure                                              */
-  __IOM uint32_t  USB_MCTRL_REG;                /*!< (@ 0x00000000) Main Control Register)                                     */
-  __IOM uint32_t  USB_XCVDIAG_REG;              /*!< (@ 0x00000004) Transceiver diagnostic Register (for test purpose
-                                                                    only)                                                      */
-  __IOM uint32_t  USB_TCR_REG;                  /*!< (@ 0x00000008) Transceiver configuration Register                         */
-  __IOM uint32_t  USB_UTR_REG;                  /*!< (@ 0x0000000C) USB test Register (for test purpose only)                  */
-  __IOM uint32_t  USB_FAR_REG;                  /*!< (@ 0x00000010) Function Address Register                                  */
-  __IOM uint32_t  USB_NFSR_REG;                 /*!< (@ 0x00000014) Node Functional State Register                             */
-  __IOM uint32_t  USB_MAEV_REG;                 /*!< (@ 0x00000018) Main Event Register                                        */
-  __IOM uint32_t  USB_MAMSK_REG;                /*!< (@ 0x0000001C) Main Mask Register                                         */
-  __IOM uint32_t  USB_ALTEV_REG;                /*!< (@ 0x00000020) Alternate Event Register                                   */
-  __IOM uint32_t  USB_ALTMSK_REG;               /*!< (@ 0x00000024) Alternate Mask Register                                    */
-  __IOM uint32_t  USB_TXEV_REG;                 /*!< (@ 0x00000028) Transmit Event Register                                    */
-  __IOM uint32_t  USB_TXMSK_REG;                /*!< (@ 0x0000002C) Transmit Mask Register                                     */
-  __IOM uint32_t  USB_RXEV_REG;                 /*!< (@ 0x00000030) Receive Event Register                                     */
-  __IOM uint32_t  USB_RXMSK_REG;                /*!< (@ 0x00000034) Receive Mask Register                                      */
-  __IOM uint32_t  USB_NAKEV_REG;                /*!< (@ 0x00000038) NAK Event Register                                         */
-  __IOM uint32_t  USB_NAKMSK_REG;               /*!< (@ 0x0000003C) NAK Mask Register                                          */
-  __IOM uint32_t  USB_FWEV_REG;                 /*!< (@ 0x00000040) FIFO Warning Event Register                                */
-  __IOM uint32_t  USB_FWMSK_REG;                /*!< (@ 0x00000044) FIFO Warning Mask Register                                 */
-  __IOM uint32_t  USB_FNH_REG;                  /*!< (@ 0x00000048) Frame Number High Byte Register                            */
-  __IOM uint32_t  USB_FNL_REG;                  /*!< (@ 0x0000004C) Frame Number Low Byte Register                             */
-  __IM  uint32_t  RESERVED[11];
-  __IOM uint32_t  USB_UX20CDR_REG;              /*!< (@ 0x0000007C) Transceiver 2.0 Configuration and Diagnostics
-                                                                    Register(for test purpose only)                            */
-  __IOM uint32_t  USB_EPC0_REG;                 /*!< (@ 0x00000080) Endpoint Control 0 Register                                */
-  __IOM uint32_t  USB_TXD0_REG;                 /*!< (@ 0x00000084) Transmit Data 0 Register                                   */
-  __IOM uint32_t  USB_TXS0_REG;                 /*!< (@ 0x00000088) Transmit Status 0 Register                                 */
-  __IOM uint32_t  USB_TXC0_REG;                 /*!< (@ 0x0000008C) Transmit command 0 Register                                */
-  __IOM uint32_t  USB_EP0_NAK_REG;              /*!< (@ 0x00000090) EP0 INNAK and OUTNAK Register                              */
-  __IOM uint32_t  USB_RXD0_REG;                 /*!< (@ 0x00000094) Receive Data 0 Register                                    */
-  __IOM uint32_t  USB_RXS0_REG;                 /*!< (@ 0x00000098) Receive Status 0 Register                                  */
-  __IOM uint32_t  USB_RXC0_REG;                 /*!< (@ 0x0000009C) Receive Command 0 Register                                 */
-  __IOM uint32_t  USB_EPC1_REG;                 /*!< (@ 0x000000A0) Endpoint Control Register 1                                */
-  __IOM uint32_t  USB_TXD1_REG;                 /*!< (@ 0x000000A4) Transmit Data Register 1                                   */
-  __IOM uint32_t  USB_TXS1_REG;                 /*!< (@ 0x000000A8) Transmit Status Register 1                                 */
-  __IOM uint32_t  USB_TXC1_REG;                 /*!< (@ 0x000000AC) Transmit Command Register 1                                */
-  __IOM uint32_t  USB_EPC2_REG;                 /*!< (@ 0x000000B0) Endpoint Control Register 2                                */
-  __IOM uint32_t  USB_RXD1_REG;                 /*!< (@ 0x000000B4) Receive Data Register,1                                    */
-  __IOM uint32_t  USB_RXS1_REG;                 /*!< (@ 0x000000B8) Receive Status Register 1                                  */
-  __IOM uint32_t  USB_RXC1_REG;                 /*!< (@ 0x000000BC) Receive Command Register 1                                 */
-  __IOM uint32_t  USB_EPC3_REG;                 /*!< (@ 0x000000C0) Endpoint Control Register 3                                */
-  __IOM uint32_t  USB_TXD2_REG;                 /*!< (@ 0x000000C4) Transmit Data Register 2                                   */
-  __IOM uint32_t  USB_TXS2_REG;                 /*!< (@ 0x000000C8) Transmit Status Register 2                                 */
-  __IOM uint32_t  USB_TXC2_REG;                 /*!< (@ 0x000000CC) Transmit Command Register 2                                */
-  __IOM uint32_t  USB_EPC4_REG;                 /*!< (@ 0x000000D0) Endpoint Control Register 4                                */
-  __IOM uint32_t  USB_RXD2_REG;                 /*!< (@ 0x000000D4) Receive Data Register 2                                    */
-  __IOM uint32_t  USB_RXS2_REG;                 /*!< (@ 0x000000D8) Receive Status Register 2                                  */
-  __IOM uint32_t  USB_RXC2_REG;                 /*!< (@ 0x000000DC) Receive Command Register 2                                 */
-  __IOM uint32_t  USB_EPC5_REG;                 /*!< (@ 0x000000E0) Endpoint Control Register 5                                */
-  __IOM uint32_t  USB_TXD3_REG;                 /*!< (@ 0x000000E4) Transmit Data Register 3                                   */
-  __IOM uint32_t  USB_TXS3_REG;                 /*!< (@ 0x000000E8) Transmit Status Register 3                                 */
-  __IOM uint32_t  USB_TXC3_REG;                 /*!< (@ 0x000000EC) Transmit Command Register 3                                */
-  __IOM uint32_t  USB_EPC6_REG;                 /*!< (@ 0x000000F0) Endpoint Control Register 6                                */
-  __IOM uint32_t  USB_RXD3_REG;                 /*!< (@ 0x000000F4) Receive Data Register 3                                    */
-  __IOM uint32_t  USB_RXS3_REG;                 /*!< (@ 0x000000F8) Receive Status Register 3                                  */
-  __IOM uint32_t  USB_RXC3_REG;                 /*!< (@ 0x000000FC) Receive Command Register 3                                 */
-  __IM  uint32_t  RESERVED1[40];
-  __IOM uint32_t  USB_DMA_CTRL_REG;             /*!< (@ 0x000001A0) USB DMA control register                                   */
-  __IM  uint32_t  RESERVED2;
-  __IOM uint32_t  USB_CHARGER_CTRL_REG;         /*!< (@ 0x000001A8) USB Charger Control Register                               */
-  __IOM uint32_t  USB_CHARGER_STAT_REG;         /*!< (@ 0x000001AC) USB Charger Status Register                                */
-} USB_Type;                                     /*!< Size = 432 (0x1b0)                                                        */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                          WAKEUP                                           ================ */
-/* =========================================================================================================================== */
-
-
-/**
-  * @brief WAKEUP registers (WAKEUP)
-  */
-
-typedef struct {                                /*!< (@ 0x50000100) WAKEUP Structure                                           */
-  __IOM uint32_t  WKUP_CTRL_REG;                /*!< (@ 0x00000000) Control register for the wakeup counter                    */
-  __IM  uint32_t  RESERVED;
-  __IOM uint32_t  WKUP_RESET_IRQ_REG;           /*!< (@ 0x00000008) Reset wakeup interrupt                                     */
-  __IM  uint32_t  RESERVED1[2];
-  __IOM uint32_t  WKUP_SELECT_P0_REG;           /*!< (@ 0x00000014) select which inputs from P0 port can trigger
-                                                                    wkup counter                                               */
-  __IOM uint32_t  WKUP_SELECT_P1_REG;           /*!< (@ 0x00000018) select which inputs from P1 port can trigger
-                                                                    wkup counter                                               */
-  __IM  uint32_t  RESERVED2[3];
-  __IOM uint32_t  WKUP_POL_P0_REG;              /*!< (@ 0x00000028) select the sesitivity polarity for each P0 input           */
-  __IOM uint32_t  WKUP_POL_P1_REG;              /*!< (@ 0x0000002C) select the sesitivity polarity for each P1 input           */
-  __IM  uint32_t  RESERVED3[3];
-  __IOM uint32_t  WKUP_STATUS_P0_REG;           /*!< (@ 0x0000003C) Event status register for P0                               */
-  __IOM uint32_t  WKUP_STATUS_P1_REG;           /*!< (@ 0x00000040) Event status register for P1                               */
-  __IM  uint32_t  RESERVED4;
-  __IOM uint32_t  WKUP_CLEAR_P0_REG;            /*!< (@ 0x00000048) Clear event register for P0                                */
-  __IOM uint32_t  WKUP_CLEAR_P1_REG;            /*!< (@ 0x0000004C) Clear event register for P1                                */
-  __IM  uint32_t  RESERVED5;
-  __IOM uint32_t  WKUP_SEL_GPIO_P0_REG;         /*!< (@ 0x00000054) select which inputs from P0 port can trigger
-                                                                    interrupt                                                  */
-  __IOM uint32_t  WKUP_SEL_GPIO_P1_REG;         /*!< (@ 0x00000058) select which inputs from P1 port can trigger
-                                                                    interrupt                                                  */
-} WAKEUP_Type;                                  /*!< Size = 92 (0x5c)                                                          */
-
-
-/** @} */ /* End of group Device_Peripheral_peripherals */
-
-
-/* =========================================================================================================================== */
-/* ================                          Device Specific Peripheral Address Map                           ================ */
-/* =========================================================================================================================== */
-
-
-#define AES_HASH_BASE               0x30040000UL
-#define ANAMISC_BIF_BASE            0x50030B00UL
-#define APU_BASE                    0x50030600UL
-#define CACHE_BASE                  0x100C0000UL
-#define CHARGER_BASE                0x50040400UL
-#define CHIP_VERSION_BASE           0x50040200UL
-#define CRG_COM_BASE                0x50020900UL
-#define CRG_PER_BASE                0x50030C00UL
-#define CRG_SYS_BASE                0x50040500UL
-#define CRG_TOP_BASE                0x50000000UL
-#define CRG_XTAL_BASE               0x50010000UL
-#define DCDC_BASE                   0x50000300UL
-#define DMA_BASE                    0x50040800UL
-#define DW_BASE                     0x30020000UL
-#define GPADC_BASE                  0x50030900UL
-#define GPIO_BASE                   0x50020A00UL
-#define GPREG_BASE                  0x50040300UL
-#define I2C_BASE                    0x50020600UL
-#define I2C2_BASE                   0x50020700UL
-#define LCDC_BASE                   0x30030000UL
-#define LRA_BASE                    0x50030A00UL
-#define MEMCTRL_BASE                0x50050000UL
-#define OTPC_BASE                   0x30070000UL
-#define PDC_BASE                    0x50000200UL
-#define PWMLED_BASE                 0x50030500UL
-#define QSPIC_BASE                  0x38000000UL
-#define QSPIC2_BASE                 0x34000000UL
-#define RFMON_BASE                  0x50040600UL
-#define RTC_BASE                    0x50000400UL
-#define SDADC_BASE                  0x50020800UL
-#define SMOTOR_BASE                 0x50030E00UL
-#define SNC_BASE                    0x50020C00UL
-#define SPI_BASE                    0x50020300UL
-#define SPI2_BASE                   0x50020400UL
-#define SYS_WDOG_BASE               0x50000700UL
-#define TIMER_BASE                  0x50010200UL
-#define TIMER2_BASE                 0x50010300UL
-#define TIMER3_BASE                 0x50040A00UL
-#define TIMER4_BASE                 0x50040B00UL
-#define TRNG_BASE                   0x50040C00UL
-#define UART_BASE                   0x50020000UL
-#define UART2_BASE                  0x50020100UL
-#define UART3_BASE                  0x50020200UL
-#define USB_BASE                    0x50040000UL
-#define WAKEUP_BASE                 0x50000100UL
-
-
-/* =========================================================================================================================== */
-/* ================                                  Peripheral declaration                                   ================ */
-/* =========================================================================================================================== */
-
-
-#define AES_HASH                    ((AES_HASH_Type*)          AES_HASH_BASE)
-#define ANAMISC_BIF                 ((ANAMISC_BIF_Type*)       ANAMISC_BIF_BASE)
-#define APU                         ((APU_Type*)               APU_BASE)
-#define CACHE                       ((CACHE_Type*)             CACHE_BASE)
-#define CHARGER                     ((CHARGER_Type*)           CHARGER_BASE)
-#define CHIP_VERSION                ((CHIP_VERSION_Type*)      CHIP_VERSION_BASE)
-#define CRG_COM                     ((CRG_COM_Type*)           CRG_COM_BASE)
-#define CRG_PER                     ((CRG_PER_Type*)           CRG_PER_BASE)
-#define CRG_SYS                     ((CRG_SYS_Type*)           CRG_SYS_BASE)
-#define CRG_TOP                     ((CRG_TOP_Type*)           CRG_TOP_BASE)
-#define CRG_XTAL                    ((CRG_XTAL_Type*)          CRG_XTAL_BASE)
-#define DCDC                        ((DCDC_Type*)              DCDC_BASE)
-#define DMA                         ((DMA_Type*)               DMA_BASE)
-#define DW                          ((DW_Type*)                DW_BASE)
-#define GPADC                       ((GPADC_Type*)             GPADC_BASE)
-#define GPIO                        ((GPIO_Type*)              GPIO_BASE)
-#define GPREG                       ((GPREG_Type*)             GPREG_BASE)
-#define I2C                         ((I2C_Type*)               I2C_BASE)
-#define I2C2                        ((I2C2_Type*)              I2C2_BASE)
-#define LCDC                        ((LCDC_Type*)              LCDC_BASE)
-#define LRA                         ((LRA_Type*)               LRA_BASE)
-#define MEMCTRL                     ((MEMCTRL_Type*)           MEMCTRL_BASE)
-#define OTPC                        ((OTPC_Type*)              OTPC_BASE)
-#define PDC                         ((PDC_Type*)               PDC_BASE)
-#define PWMLED                      ((PWMLED_Type*)            PWMLED_BASE)
-#define QSPIC                       ((QSPIC_Type*)             QSPIC_BASE)
-#define QSPIC2                      ((QSPIC2_Type*)            QSPIC2_BASE)
-#define RFMON                       ((RFMON_Type*)             RFMON_BASE)
-#define RTC                         ((RTC_Type*)               RTC_BASE)
-#define SDADC                       ((SDADC_Type*)             SDADC_BASE)
-#define SMOTOR                      ((SMOTOR_Type*)            SMOTOR_BASE)
-#define SNC                         ((SNC_Type*)               SNC_BASE)
-#define SPI                         ((SPI_Type*)               SPI_BASE)
-#define SPI2                        ((SPI2_Type*)              SPI2_BASE)
-#define SYS_WDOG                    ((SYS_WDOG_Type*)          SYS_WDOG_BASE)
-#define TIMER                       ((TIMER_Type*)             TIMER_BASE)
-#define TIMER2                      ((TIMER2_Type*)            TIMER2_BASE)
-#define TIMER3                      ((TIMER3_Type*)            TIMER3_BASE)
-#define TIMER4                      ((TIMER4_Type*)            TIMER4_BASE)
-#define TRNG                        ((TRNG_Type*)              TRNG_BASE)
-#define UART                        ((UART_Type*)              UART_BASE)
-#define UART2                       ((UART2_Type*)             UART2_BASE)
-#define UART3                       ((UART3_Type*)             UART3_BASE)
-#define USB                         ((USB_Type*)               USB_BASE)
-#define WAKEUP                      ((WAKEUP_Type*)            WAKEUP_BASE)
-
-
-/* =========================================================================================================================== */
-/* ================                                Pos/Mask Peripheral Section                                ================ */
-/* =========================================================================================================================== */
-
-
-/** @addtogroup PosMask_peripherals
-  * @{
-  */
-
-
-
-/* =========================================================================================================================== */
-/* ================                                         AES_HASH                                          ================ */
-/* =========================================================================================================================== */
-
-/* ===================================================  CRYPTO_CLRIRQ_REG  =================================================== */
-#define AES_HASH_CRYPTO_CLRIRQ_REG_CRYPTO_CLRIRQ_Pos (0UL)          /*!< CRYPTO_CLRIRQ (Bit 0)                                 */
-#define AES_HASH_CRYPTO_CLRIRQ_REG_CRYPTO_CLRIRQ_Msk (0x1UL)        /*!< CRYPTO_CLRIRQ (Bitfield-Mask: 0x01)                   */
-/* ====================================================  CRYPTO_CTRL_REG  ==================================================== */
-#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEXP_Pos (17UL)         /*!< CRYPTO_AES_KEXP (Bit 17)                              */
-#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEXP_Msk (0x20000UL)    /*!< CRYPTO_AES_KEXP (Bitfield-Mask: 0x01)                 */
-#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_MORE_IN_Pos (16UL)          /*!< CRYPTO_MORE_IN (Bit 16)                               */
-#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_MORE_IN_Msk (0x10000UL)     /*!< CRYPTO_MORE_IN (Bitfield-Mask: 0x01)                  */
-#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_OUT_LEN_Pos (10UL)     /*!< CRYPTO_HASH_OUT_LEN (Bit 10)                          */
-#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_OUT_LEN_Msk (0xfc00UL) /*!< CRYPTO_HASH_OUT_LEN (Bitfield-Mask: 0x3f)             */
-#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_SEL_Pos (9UL)          /*!< CRYPTO_HASH_SEL (Bit 9)                               */
-#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_SEL_Msk (0x200UL)      /*!< CRYPTO_HASH_SEL (Bitfield-Mask: 0x01)                 */
-#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_IRQ_EN_Pos (8UL)            /*!< CRYPTO_IRQ_EN (Bit 8)                                 */
-#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_IRQ_EN_Msk (0x100UL)        /*!< CRYPTO_IRQ_EN (Bitfield-Mask: 0x01)                   */
-#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ENCDEC_Pos (7UL)            /*!< CRYPTO_ENCDEC (Bit 7)                                 */
-#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ENCDEC_Msk (0x80UL)         /*!< CRYPTO_ENCDEC (Bitfield-Mask: 0x01)                   */
-#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Pos (5UL)        /*!< CRYPTO_AES_KEY_SZ (Bit 5)                             */
-#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Msk (0x60UL)     /*!< CRYPTO_AES_KEY_SZ (Bitfield-Mask: 0x03)               */
-#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_OUT_MD_Pos (4UL)            /*!< CRYPTO_OUT_MD (Bit 4)                                 */
-#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_OUT_MD_Msk (0x10UL)         /*!< CRYPTO_OUT_MD (Bitfield-Mask: 0x01)                   */
-#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Pos (2UL)            /*!< CRYPTO_ALG_MD (Bit 2)                                 */
-#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Msk (0xcUL)          /*!< CRYPTO_ALG_MD (Bitfield-Mask: 0x03)                   */
-#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_Pos (0UL)               /*!< CRYPTO_ALG (Bit 0)                                    */
-#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_Msk (0x3UL)             /*!< CRYPTO_ALG (Bitfield-Mask: 0x03)                      */
-/* =================================================  CRYPTO_DEST_ADDR_REG  ================================================== */
-#define AES_HASH_CRYPTO_DEST_ADDR_REG_CRYPTO_DEST_ADDR_Pos (0UL)    /*!< CRYPTO_DEST_ADDR (Bit 0)                              */
-#define AES_HASH_CRYPTO_DEST_ADDR_REG_CRYPTO_DEST_ADDR_Msk (0xffffffffUL) /*!< CRYPTO_DEST_ADDR (Bitfield-Mask: 0xffffffff)    */
-/* =================================================  CRYPTO_FETCH_ADDR_REG  ================================================= */
-#define AES_HASH_CRYPTO_FETCH_ADDR_REG_CRYPTO_FETCH_ADDR_Pos (0UL)  /*!< CRYPTO_FETCH_ADDR (Bit 0)                             */
-#define AES_HASH_CRYPTO_FETCH_ADDR_REG_CRYPTO_FETCH_ADDR_Msk (0xffffffffUL) /*!< CRYPTO_FETCH_ADDR (Bitfield-Mask: 0xffffffff) */
-/* ===================================================  CRYPTO_KEYS_START  =================================================== */
-#define AES_HASH_CRYPTO_KEYS_START_CRYPTO_KEY_X_Pos (0UL)           /*!< CRYPTO_KEY_X (Bit 0)                                  */
-#define AES_HASH_CRYPTO_KEYS_START_CRYPTO_KEY_X_Msk (0xffffffffUL)  /*!< CRYPTO_KEY_X (Bitfield-Mask: 0xffffffff)              */
-/* ====================================================  CRYPTO_LEN_REG  ===================================================== */
-#define AES_HASH_CRYPTO_LEN_REG_CRYPTO_LEN_Pos (0UL)                /*!< CRYPTO_LEN (Bit 0)                                    */
-#define AES_HASH_CRYPTO_LEN_REG_CRYPTO_LEN_Msk (0xffffffUL)         /*!< CRYPTO_LEN (Bitfield-Mask: 0xffffff)                  */
-/* ===================================================  CRYPTO_MREG0_REG  ==================================================== */
-#define AES_HASH_CRYPTO_MREG0_REG_CRYPTO_MREG0_Pos (0UL)            /*!< CRYPTO_MREG0 (Bit 0)                                  */
-#define AES_HASH_CRYPTO_MREG0_REG_CRYPTO_MREG0_Msk (0xffffffffUL)   /*!< CRYPTO_MREG0 (Bitfield-Mask: 0xffffffff)              */
-/* ===================================================  CRYPTO_MREG1_REG  ==================================================== */
-#define AES_HASH_CRYPTO_MREG1_REG_CRYPTO_MREG1_Pos (0UL)            /*!< CRYPTO_MREG1 (Bit 0)                                  */
-#define AES_HASH_CRYPTO_MREG1_REG_CRYPTO_MREG1_Msk (0xffffffffUL)   /*!< CRYPTO_MREG1 (Bitfield-Mask: 0xffffffff)              */
-/* ===================================================  CRYPTO_MREG2_REG  ==================================================== */
-#define AES_HASH_CRYPTO_MREG2_REG_CRYPTO_MREG2_Pos (0UL)            /*!< CRYPTO_MREG2 (Bit 0)                                  */
-#define AES_HASH_CRYPTO_MREG2_REG_CRYPTO_MREG2_Msk (0xffffffffUL)   /*!< CRYPTO_MREG2 (Bitfield-Mask: 0xffffffff)              */
-/* ===================================================  CRYPTO_MREG3_REG  ==================================================== */
-#define AES_HASH_CRYPTO_MREG3_REG_CRYPTO_MREG3_Pos (0UL)            /*!< CRYPTO_MREG3 (Bit 0)                                  */
-#define AES_HASH_CRYPTO_MREG3_REG_CRYPTO_MREG3_Msk (0xffffffffUL)   /*!< CRYPTO_MREG3 (Bitfield-Mask: 0xffffffff)              */
-/* ===================================================  CRYPTO_START_REG  ==================================================== */
-#define AES_HASH_CRYPTO_START_REG_CRYPTO_START_Pos (0UL)            /*!< CRYPTO_START (Bit 0)                                  */
-#define AES_HASH_CRYPTO_START_REG_CRYPTO_START_Msk (0x1UL)          /*!< CRYPTO_START (Bitfield-Mask: 0x01)                    */
-/* ===================================================  CRYPTO_STATUS_REG  =================================================== */
-#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_IRQ_ST_Pos (2UL)          /*!< CRYPTO_IRQ_ST (Bit 2)                                 */
-#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_IRQ_ST_Msk (0x4UL)        /*!< CRYPTO_IRQ_ST (Bitfield-Mask: 0x01)                   */
-#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_WAIT_FOR_IN_Pos (1UL)     /*!< CRYPTO_WAIT_FOR_IN (Bit 1)                            */
-#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_WAIT_FOR_IN_Msk (0x2UL)   /*!< CRYPTO_WAIT_FOR_IN (Bitfield-Mask: 0x01)              */
-#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_INACTIVE_Pos (0UL)        /*!< CRYPTO_INACTIVE (Bit 0)                               */
-#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_INACTIVE_Msk (0x1UL)      /*!< CRYPTO_INACTIVE (Bitfield-Mask: 0x01)                 */
-
-
-/* =========================================================================================================================== */
-/* ================                                        ANAMISC_BIF                                        ================ */
-/* =========================================================================================================================== */
-
-/* ====================================================  CLK_REF_CNT_REG  ==================================================== */
-#define ANAMISC_BIF_CLK_REF_CNT_REG_REF_CNT_VAL_Pos (0UL)           /*!< REF_CNT_VAL (Bit 0)                                   */
-#define ANAMISC_BIF_CLK_REF_CNT_REG_REF_CNT_VAL_Msk (0xffffUL)      /*!< REF_CNT_VAL (Bitfield-Mask: 0xffff)                   */
-/* ====================================================  CLK_REF_SEL_REG  ==================================================== */
-#define ANAMISC_BIF_CLK_REF_SEL_REG_CAL_CLK_SEL_Pos (5UL)           /*!< CAL_CLK_SEL (Bit 5)                                   */
-#define ANAMISC_BIF_CLK_REF_SEL_REG_CAL_CLK_SEL_Msk (0xe0UL)        /*!< CAL_CLK_SEL (Bitfield-Mask: 0x07)                     */
-#define ANAMISC_BIF_CLK_REF_SEL_REG_EXT_CNT_EN_SEL_Pos (4UL)        /*!< EXT_CNT_EN_SEL (Bit 4)                                */
-#define ANAMISC_BIF_CLK_REF_SEL_REG_EXT_CNT_EN_SEL_Msk (0x10UL)     /*!< EXT_CNT_EN_SEL (Bitfield-Mask: 0x01)                  */
-#define ANAMISC_BIF_CLK_REF_SEL_REG_REF_CAL_START_Pos (3UL)         /*!< REF_CAL_START (Bit 3)                                 */
-#define ANAMISC_BIF_CLK_REF_SEL_REG_REF_CAL_START_Msk (0x8UL)       /*!< REF_CAL_START (Bitfield-Mask: 0x01)                   */
-#define ANAMISC_BIF_CLK_REF_SEL_REG_REF_CLK_SEL_Pos (0UL)           /*!< REF_CLK_SEL (Bit 0)                                   */
-#define ANAMISC_BIF_CLK_REF_SEL_REG_REF_CLK_SEL_Msk (0x7UL)         /*!< REF_CLK_SEL (Bitfield-Mask: 0x07)                     */
-/* ====================================================  CLK_REF_VAL_REG  ==================================================== */
-#define ANAMISC_BIF_CLK_REF_VAL_REG_XTAL_CNT_VAL_Pos (0UL)          /*!< XTAL_CNT_VAL (Bit 0)                                  */
-#define ANAMISC_BIF_CLK_REF_VAL_REG_XTAL_CNT_VAL_Msk (0xffffffffUL) /*!< XTAL_CNT_VAL (Bitfield-Mask: 0xffffffff)              */
-
-
-/* =========================================================================================================================== */
-/* ================                                            APU                                            ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================  APU_MUX_REG  ====================================================== */
-#define APU_APU_MUX_REG_PDM1_MUX_IN_Pos   (6UL)                     /*!< PDM1_MUX_IN (Bit 6)                                   */
-#define APU_APU_MUX_REG_PDM1_MUX_IN_Msk   (0x40UL)                  /*!< PDM1_MUX_IN (Bitfield-Mask: 0x01)                     */
-#define APU_APU_MUX_REG_PCM1_MUX_IN_Pos   (3UL)                     /*!< PCM1_MUX_IN (Bit 3)                                   */
-#define APU_APU_MUX_REG_PCM1_MUX_IN_Msk   (0x38UL)                  /*!< PCM1_MUX_IN (Bitfield-Mask: 0x07)                     */
-#define APU_APU_MUX_REG_SRC1_MUX_IN_Pos   (0UL)                     /*!< SRC1_MUX_IN (Bit 0)                                   */
-#define APU_APU_MUX_REG_SRC1_MUX_IN_Msk   (0x7UL)                   /*!< SRC1_MUX_IN (Bitfield-Mask: 0x07)                     */
-/* ====================================================  COEF0A_SET1_REG  ==================================================== */
-#define APU_COEF0A_SET1_REG_SRC_COEF10_Pos (0UL)                    /*!< SRC_COEF10 (Bit 0)                                    */
-#define APU_COEF0A_SET1_REG_SRC_COEF10_Msk (0xffffUL)               /*!< SRC_COEF10 (Bitfield-Mask: 0xffff)                    */
-/* ====================================================  COEF10_SET1_REG  ==================================================== */
-#define APU_COEF10_SET1_REG_SRC_COEF1_Pos (16UL)                    /*!< SRC_COEF1 (Bit 16)                                    */
-#define APU_COEF10_SET1_REG_SRC_COEF1_Msk (0xffff0000UL)            /*!< SRC_COEF1 (Bitfield-Mask: 0xffff)                     */
-#define APU_COEF10_SET1_REG_SRC_COEF0_Pos (0UL)                     /*!< SRC_COEF0 (Bit 0)                                     */
-#define APU_COEF10_SET1_REG_SRC_COEF0_Msk (0xffffUL)                /*!< SRC_COEF0 (Bitfield-Mask: 0xffff)                     */
-/* ====================================================  COEF32_SET1_REG  ==================================================== */
-#define APU_COEF32_SET1_REG_SRC_COEF3_Pos (16UL)                    /*!< SRC_COEF3 (Bit 16)                                    */
-#define APU_COEF32_SET1_REG_SRC_COEF3_Msk (0xffff0000UL)            /*!< SRC_COEF3 (Bitfield-Mask: 0xffff)                     */
-#define APU_COEF32_SET1_REG_SRC_COEF2_Pos (0UL)                     /*!< SRC_COEF2 (Bit 0)                                     */
-#define APU_COEF32_SET1_REG_SRC_COEF2_Msk (0xffffUL)                /*!< SRC_COEF2 (Bitfield-Mask: 0xffff)                     */
-/* ====================================================  COEF54_SET1_REG  ==================================================== */
-#define APU_COEF54_SET1_REG_SRC_COEF5_Pos (16UL)                    /*!< SRC_COEF5 (Bit 16)                                    */
-#define APU_COEF54_SET1_REG_SRC_COEF5_Msk (0xffff0000UL)            /*!< SRC_COEF5 (Bitfield-Mask: 0xffff)                     */
-#define APU_COEF54_SET1_REG_SRC_COEF4_Pos (0UL)                     /*!< SRC_COEF4 (Bit 0)                                     */
-#define APU_COEF54_SET1_REG_SRC_COEF4_Msk (0xffffUL)                /*!< SRC_COEF4 (Bitfield-Mask: 0xffff)                     */
-/* ====================================================  COEF76_SET1_REG  ==================================================== */
-#define APU_COEF76_SET1_REG_SRC_COEF7_Pos (16UL)                    /*!< SRC_COEF7 (Bit 16)                                    */
-#define APU_COEF76_SET1_REG_SRC_COEF7_Msk (0xffff0000UL)            /*!< SRC_COEF7 (Bitfield-Mask: 0xffff)                     */
-#define APU_COEF76_SET1_REG_SRC_COEF6_Pos (0UL)                     /*!< SRC_COEF6 (Bit 0)                                     */
-#define APU_COEF76_SET1_REG_SRC_COEF6_Msk (0xffffUL)                /*!< SRC_COEF6 (Bitfield-Mask: 0xffff)                     */
-/* ====================================================  COEF98_SET1_REG  ==================================================== */
-#define APU_COEF98_SET1_REG_SRC_COEF9_Pos (16UL)                    /*!< SRC_COEF9 (Bit 16)                                    */
-#define APU_COEF98_SET1_REG_SRC_COEF9_Msk (0xffff0000UL)            /*!< SRC_COEF9 (Bitfield-Mask: 0xffff)                     */
-#define APU_COEF98_SET1_REG_SRC_COEF8_Pos (0UL)                     /*!< SRC_COEF8 (Bit 0)                                     */
-#define APU_COEF98_SET1_REG_SRC_COEF8_Msk (0xffffUL)                /*!< SRC_COEF8 (Bitfield-Mask: 0xffff)                     */
-/* =====================================================  PCM1_CTRL_REG  ===================================================== */
-#define APU_PCM1_CTRL_REG_PCM_FSC_DIV_Pos (20UL)                    /*!< PCM_FSC_DIV (Bit 20)                                  */
-#define APU_PCM1_CTRL_REG_PCM_FSC_DIV_Msk (0xfff00000UL)            /*!< PCM_FSC_DIV (Bitfield-Mask: 0xfff)                    */
-#define APU_PCM1_CTRL_REG_PCM_FSC_EDGE_Pos (16UL)                   /*!< PCM_FSC_EDGE (Bit 16)                                 */
-#define APU_PCM1_CTRL_REG_PCM_FSC_EDGE_Msk (0x10000UL)              /*!< PCM_FSC_EDGE (Bitfield-Mask: 0x01)                    */
-#define APU_PCM1_CTRL_REG_PCM_CH_DEL_Pos  (11UL)                    /*!< PCM_CH_DEL (Bit 11)                                   */
-#define APU_PCM1_CTRL_REG_PCM_CH_DEL_Msk  (0xf800UL)                /*!< PCM_CH_DEL (Bitfield-Mask: 0x1f)                      */
-#define APU_PCM1_CTRL_REG_PCM_CLK_BIT_Pos (10UL)                    /*!< PCM_CLK_BIT (Bit 10)                                  */
-#define APU_PCM1_CTRL_REG_PCM_CLK_BIT_Msk (0x400UL)                 /*!< PCM_CLK_BIT (Bitfield-Mask: 0x01)                     */
-#define APU_PCM1_CTRL_REG_PCM_FSCINV_Pos  (9UL)                     /*!< PCM_FSCINV (Bit 9)                                    */
-#define APU_PCM1_CTRL_REG_PCM_FSCINV_Msk  (0x200UL)                 /*!< PCM_FSCINV (Bitfield-Mask: 0x01)                      */
-#define APU_PCM1_CTRL_REG_PCM_CLKINV_Pos  (8UL)                     /*!< PCM_CLKINV (Bit 8)                                    */
-#define APU_PCM1_CTRL_REG_PCM_CLKINV_Msk  (0x100UL)                 /*!< PCM_CLKINV (Bitfield-Mask: 0x01)                      */
-#define APU_PCM1_CTRL_REG_PCM_PPOD_Pos    (7UL)                     /*!< PCM_PPOD (Bit 7)                                      */
-#define APU_PCM1_CTRL_REG_PCM_PPOD_Msk    (0x80UL)                  /*!< PCM_PPOD (Bitfield-Mask: 0x01)                        */
-#define APU_PCM1_CTRL_REG_PCM_FSCDEL_Pos  (6UL)                     /*!< PCM_FSCDEL (Bit 6)                                    */
-#define APU_PCM1_CTRL_REG_PCM_FSCDEL_Msk  (0x40UL)                  /*!< PCM_FSCDEL (Bitfield-Mask: 0x01)                      */
-#define APU_PCM1_CTRL_REG_PCM_FSCLEN_Pos  (2UL)                     /*!< PCM_FSCLEN (Bit 2)                                    */
-#define APU_PCM1_CTRL_REG_PCM_FSCLEN_Msk  (0x3cUL)                  /*!< PCM_FSCLEN (Bitfield-Mask: 0x0f)                      */
-#define APU_PCM1_CTRL_REG_PCM_MASTER_Pos  (1UL)                     /*!< PCM_MASTER (Bit 1)                                    */
-#define APU_PCM1_CTRL_REG_PCM_MASTER_Msk  (0x2UL)                   /*!< PCM_MASTER (Bitfield-Mask: 0x01)                      */
-#define APU_PCM1_CTRL_REG_PCM_EN_Pos      (0UL)                     /*!< PCM_EN (Bit 0)                                        */
-#define APU_PCM1_CTRL_REG_PCM_EN_Msk      (0x1UL)                   /*!< PCM_EN (Bitfield-Mask: 0x01)                          */
-/* =====================================================  PCM1_IN1_REG  ====================================================== */
-#define APU_PCM1_IN1_REG_PCM_IN_Pos       (0UL)                     /*!< PCM_IN (Bit 0)                                        */
-#define APU_PCM1_IN1_REG_PCM_IN_Msk       (0xffffffffUL)            /*!< PCM_IN (Bitfield-Mask: 0xffffffff)                    */
-/* =====================================================  PCM1_IN2_REG  ====================================================== */
-#define APU_PCM1_IN2_REG_PCM_IN_Pos       (0UL)                     /*!< PCM_IN (Bit 0)                                        */
-#define APU_PCM1_IN2_REG_PCM_IN_Msk       (0xffffffffUL)            /*!< PCM_IN (Bitfield-Mask: 0xffffffff)                    */
-/* =====================================================  PCM1_OUT1_REG  ===================================================== */
-#define APU_PCM1_OUT1_REG_PCM_OUT_Pos     (0UL)                     /*!< PCM_OUT (Bit 0)                                       */
-#define APU_PCM1_OUT1_REG_PCM_OUT_Msk     (0xffffffffUL)            /*!< PCM_OUT (Bitfield-Mask: 0xffffffff)                   */
-/* =====================================================  PCM1_OUT2_REG  ===================================================== */
-#define APU_PCM1_OUT2_REG_PCM_OUT_Pos     (0UL)                     /*!< PCM_OUT (Bit 0)                                       */
-#define APU_PCM1_OUT2_REG_PCM_OUT_Msk     (0xffffffffUL)            /*!< PCM_OUT (Bitfield-Mask: 0xffffffff)                   */
-/* =====================================================  SRC1_CTRL_REG  ===================================================== */
-#define APU_SRC1_CTRL_REG_SRC_PDM_DO_DEL_Pos (30UL)                 /*!< SRC_PDM_DO_DEL (Bit 30)                               */
-#define APU_SRC1_CTRL_REG_SRC_PDM_DO_DEL_Msk (0xc0000000UL)         /*!< SRC_PDM_DO_DEL (Bitfield-Mask: 0x03)                  */
-#define APU_SRC1_CTRL_REG_SRC_PDM_MODE_Pos (28UL)                   /*!< SRC_PDM_MODE (Bit 28)                                 */
-#define APU_SRC1_CTRL_REG_SRC_PDM_MODE_Msk (0x30000000UL)           /*!< SRC_PDM_MODE (Bitfield-Mask: 0x03)                    */
-#define APU_SRC1_CTRL_REG_SRC_PDM_DI_DEL_Pos (26UL)                 /*!< SRC_PDM_DI_DEL (Bit 26)                               */
-#define APU_SRC1_CTRL_REG_SRC_PDM_DI_DEL_Msk (0xc000000UL)          /*!< SRC_PDM_DI_DEL (Bitfield-Mask: 0x03)                  */
-#define APU_SRC1_CTRL_REG_SRC_OUT_FLOWCLR_Pos (25UL)                /*!< SRC_OUT_FLOWCLR (Bit 25)                              */
-#define APU_SRC1_CTRL_REG_SRC_OUT_FLOWCLR_Msk (0x2000000UL)         /*!< SRC_OUT_FLOWCLR (Bitfield-Mask: 0x01)                 */
-#define APU_SRC1_CTRL_REG_SRC_IN_FLOWCLR_Pos (24UL)                 /*!< SRC_IN_FLOWCLR (Bit 24)                               */
-#define APU_SRC1_CTRL_REG_SRC_IN_FLOWCLR_Msk (0x1000000UL)          /*!< SRC_IN_FLOWCLR (Bitfield-Mask: 0x01)                  */
-#define APU_SRC1_CTRL_REG_SRC_OUT_UNFLOW_Pos (23UL)                 /*!< SRC_OUT_UNFLOW (Bit 23)                               */
-#define APU_SRC1_CTRL_REG_SRC_OUT_UNFLOW_Msk (0x800000UL)           /*!< SRC_OUT_UNFLOW (Bitfield-Mask: 0x01)                  */
-#define APU_SRC1_CTRL_REG_SRC_OUT_OVFLOW_Pos (22UL)                 /*!< SRC_OUT_OVFLOW (Bit 22)                               */
-#define APU_SRC1_CTRL_REG_SRC_OUT_OVFLOW_Msk (0x400000UL)           /*!< SRC_OUT_OVFLOW (Bitfield-Mask: 0x01)                  */
-#define APU_SRC1_CTRL_REG_SRC_IN_UNFLOW_Pos (21UL)                  /*!< SRC_IN_UNFLOW (Bit 21)                                */
-#define APU_SRC1_CTRL_REG_SRC_IN_UNFLOW_Msk (0x200000UL)            /*!< SRC_IN_UNFLOW (Bitfield-Mask: 0x01)                   */
-#define APU_SRC1_CTRL_REG_SRC_IN_OVFLOW_Pos (20UL)                  /*!< SRC_IN_OVFLOW (Bit 20)                                */
-#define APU_SRC1_CTRL_REG_SRC_IN_OVFLOW_Msk (0x100000UL)            /*!< SRC_IN_OVFLOW (Bitfield-Mask: 0x01)                   */
-#define APU_SRC1_CTRL_REG_SRC_RESYNC_Pos  (19UL)                    /*!< SRC_RESYNC (Bit 19)                                   */
-#define APU_SRC1_CTRL_REG_SRC_RESYNC_Msk  (0x80000UL)               /*!< SRC_RESYNC (Bitfield-Mask: 0x01)                      */
-#define APU_SRC1_CTRL_REG_SRC_OUT_OK_Pos  (18UL)                    /*!< SRC_OUT_OK (Bit 18)                                   */
-#define APU_SRC1_CTRL_REG_SRC_OUT_OK_Msk  (0x40000UL)               /*!< SRC_OUT_OK (Bitfield-Mask: 0x01)                      */
-#define APU_SRC1_CTRL_REG_SRC_OUT_US_Pos  (16UL)                    /*!< SRC_OUT_US (Bit 16)                                   */
-#define APU_SRC1_CTRL_REG_SRC_OUT_US_Msk  (0x30000UL)               /*!< SRC_OUT_US (Bitfield-Mask: 0x03)                      */
-#define APU_SRC1_CTRL_REG_SRC_OUT_CAL_BYPASS_Pos (14UL)             /*!< SRC_OUT_CAL_BYPASS (Bit 14)                           */
-#define APU_SRC1_CTRL_REG_SRC_OUT_CAL_BYPASS_Msk (0x4000UL)         /*!< SRC_OUT_CAL_BYPASS (Bitfield-Mask: 0x01)              */
-#define APU_SRC1_CTRL_REG_SRC_OUT_AMODE_Pos (13UL)                  /*!< SRC_OUT_AMODE (Bit 13)                                */
-#define APU_SRC1_CTRL_REG_SRC_OUT_AMODE_Msk (0x2000UL)              /*!< SRC_OUT_AMODE (Bitfield-Mask: 0x01)                   */
-#define APU_SRC1_CTRL_REG_SRC_PDM_OUT_INV_Pos (12UL)                /*!< SRC_PDM_OUT_INV (Bit 12)                              */
-#define APU_SRC1_CTRL_REG_SRC_PDM_OUT_INV_Msk (0x1000UL)            /*!< SRC_PDM_OUT_INV (Bitfield-Mask: 0x01)                 */
-#define APU_SRC1_CTRL_REG_SRC_FIFO_DIRECTION_Pos (11UL)             /*!< SRC_FIFO_DIRECTION (Bit 11)                           */
-#define APU_SRC1_CTRL_REG_SRC_FIFO_DIRECTION_Msk (0x800UL)          /*!< SRC_FIFO_DIRECTION (Bitfield-Mask: 0x01)              */
-#define APU_SRC1_CTRL_REG_SRC_FIFO_ENABLE_Pos (10UL)                /*!< SRC_FIFO_ENABLE (Bit 10)                              */
-#define APU_SRC1_CTRL_REG_SRC_FIFO_ENABLE_Msk (0x400UL)             /*!< SRC_FIFO_ENABLE (Bitfield-Mask: 0x01)                 */
-#define APU_SRC1_CTRL_REG_SRC_OUT_DSD_MODE_Pos (9UL)                /*!< SRC_OUT_DSD_MODE (Bit 9)                              */
-#define APU_SRC1_CTRL_REG_SRC_OUT_DSD_MODE_Msk (0x200UL)            /*!< SRC_OUT_DSD_MODE (Bitfield-Mask: 0x01)                */
-#define APU_SRC1_CTRL_REG_SRC_IN_DSD_MODE_Pos (8UL)                 /*!< SRC_IN_DSD_MODE (Bit 8)                               */
-#define APU_SRC1_CTRL_REG_SRC_IN_DSD_MODE_Msk (0x100UL)             /*!< SRC_IN_DSD_MODE (Bitfield-Mask: 0x01)                 */
-#define APU_SRC1_CTRL_REG_SRC_DITHER_DISABLE_Pos (7UL)              /*!< SRC_DITHER_DISABLE (Bit 7)                            */
-#define APU_SRC1_CTRL_REG_SRC_DITHER_DISABLE_Msk (0x80UL)           /*!< SRC_DITHER_DISABLE (Bitfield-Mask: 0x01)              */
-#define APU_SRC1_CTRL_REG_SRC_IN_OK_Pos   (6UL)                     /*!< SRC_IN_OK (Bit 6)                                     */
-#define APU_SRC1_CTRL_REG_SRC_IN_OK_Msk   (0x40UL)                  /*!< SRC_IN_OK (Bitfield-Mask: 0x01)                       */
-#define APU_SRC1_CTRL_REG_SRC_IN_DS_Pos   (4UL)                     /*!< SRC_IN_DS (Bit 4)                                     */
-#define APU_SRC1_CTRL_REG_SRC_IN_DS_Msk   (0x30UL)                  /*!< SRC_IN_DS (Bitfield-Mask: 0x03)                       */
-#define APU_SRC1_CTRL_REG_SRC_PDM_IN_INV_Pos (3UL)                  /*!< SRC_PDM_IN_INV (Bit 3)                                */
-#define APU_SRC1_CTRL_REG_SRC_PDM_IN_INV_Msk (0x8UL)                /*!< SRC_PDM_IN_INV (Bitfield-Mask: 0x01)                  */
-#define APU_SRC1_CTRL_REG_SRC_IN_CAL_BYPASS_Pos (2UL)               /*!< SRC_IN_CAL_BYPASS (Bit 2)                             */
-#define APU_SRC1_CTRL_REG_SRC_IN_CAL_BYPASS_Msk (0x4UL)             /*!< SRC_IN_CAL_BYPASS (Bitfield-Mask: 0x01)               */
-#define APU_SRC1_CTRL_REG_SRC_IN_AMODE_Pos (1UL)                    /*!< SRC_IN_AMODE (Bit 1)                                  */
-#define APU_SRC1_CTRL_REG_SRC_IN_AMODE_Msk (0x2UL)                  /*!< SRC_IN_AMODE (Bitfield-Mask: 0x01)                    */
-#define APU_SRC1_CTRL_REG_SRC_EN_Pos      (0UL)                     /*!< SRC_EN (Bit 0)                                        */
-#define APU_SRC1_CTRL_REG_SRC_EN_Msk      (0x1UL)                   /*!< SRC_EN (Bitfield-Mask: 0x01)                          */
-/* =====================================================  SRC1_IN1_REG  ====================================================== */
-#define APU_SRC1_IN1_REG_SRC_IN_Pos       (0UL)                     /*!< SRC_IN (Bit 0)                                        */
-#define APU_SRC1_IN1_REG_SRC_IN_Msk       (0xffffffffUL)            /*!< SRC_IN (Bitfield-Mask: 0xffffffff)                    */
-/* =====================================================  SRC1_IN2_REG  ====================================================== */
-#define APU_SRC1_IN2_REG_SRC_IN_Pos       (0UL)                     /*!< SRC_IN (Bit 0)                                        */
-#define APU_SRC1_IN2_REG_SRC_IN_Msk       (0xffffffffUL)            /*!< SRC_IN (Bitfield-Mask: 0xffffffff)                    */
-/* ====================================================  SRC1_IN_FS_REG  ===================================================== */
-#define APU_SRC1_IN_FS_REG_SRC_IN_FS_Pos  (0UL)                     /*!< SRC_IN_FS (Bit 0)                                     */
-#define APU_SRC1_IN_FS_REG_SRC_IN_FS_Msk  (0xffffffUL)              /*!< SRC_IN_FS (Bitfield-Mask: 0xffffff)                   */
-/* =====================================================  SRC1_OUT1_REG  ===================================================== */
-#define APU_SRC1_OUT1_REG_SRC_OUT_Pos     (0UL)                     /*!< SRC_OUT (Bit 0)                                       */
-#define APU_SRC1_OUT1_REG_SRC_OUT_Msk     (0xffffffffUL)            /*!< SRC_OUT (Bitfield-Mask: 0xffffffff)                   */
-/* =====================================================  SRC1_OUT2_REG  ===================================================== */
-#define APU_SRC1_OUT2_REG_SRC_OUT_Pos     (0UL)                     /*!< SRC_OUT (Bit 0)                                       */
-#define APU_SRC1_OUT2_REG_SRC_OUT_Msk     (0xffffffffUL)            /*!< SRC_OUT (Bitfield-Mask: 0xffffffff)                   */
-/* ====================================================  SRC1_OUT_FS_REG  ==================================================== */
-#define APU_SRC1_OUT_FS_REG_SRC_OUT_FS_Pos (0UL)                    /*!< SRC_OUT_FS (Bit 0)                                    */
-#define APU_SRC1_OUT_FS_REG_SRC_OUT_FS_Msk (0xffffffUL)             /*!< SRC_OUT_FS (Bitfield-Mask: 0xffffff)                  */
-
-
-/* =========================================================================================================================== */
-/* ================                                           CACHE                                           ================ */
-/* =========================================================================================================================== */
-
-/* ==================================================  CACHE_ASSOCCFG_REG  =================================================== */
-#define CACHE_CACHE_ASSOCCFG_REG_CACHE_ASSOC_Pos (0UL)              /*!< CACHE_ASSOC (Bit 0)                                   */
-#define CACHE_CACHE_ASSOCCFG_REG_CACHE_ASSOC_Msk (0x3UL)            /*!< CACHE_ASSOC (Bitfield-Mask: 0x03)                     */
-/* ====================================================  CACHE_CTRL1_REG  ==================================================== */
-#define CACHE_CACHE_CTRL1_REG_CACHE_RES1_Pos (1UL)                  /*!< CACHE_RES1 (Bit 1)                                    */
-#define CACHE_CACHE_CTRL1_REG_CACHE_RES1_Msk (0x2UL)                /*!< CACHE_RES1 (Bitfield-Mask: 0x01)                      */
-#define CACHE_CACHE_CTRL1_REG_CACHE_FLUSH_Pos (0UL)                 /*!< CACHE_FLUSH (Bit 0)                                   */
-#define CACHE_CACHE_CTRL1_REG_CACHE_FLUSH_Msk (0x1UL)               /*!< CACHE_FLUSH (Bitfield-Mask: 0x01)                     */
-/* ====================================================  CACHE_CTRL2_REG  ==================================================== */
-#define CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Pos (10UL)                 /*!< CACHE_CGEN (Bit 10)                                   */
-#define CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Msk (0x400UL)              /*!< CACHE_CGEN (Bitfield-Mask: 0x01)                      */
-#define CACHE_CACHE_CTRL2_REG_CACHE_WEN_Pos (9UL)                   /*!< CACHE_WEN (Bit 9)                                     */
-#define CACHE_CACHE_CTRL2_REG_CACHE_WEN_Msk (0x200UL)               /*!< CACHE_WEN (Bitfield-Mask: 0x01)                       */
-#define CACHE_CACHE_CTRL2_REG_CACHE_LEN_Pos (0UL)                   /*!< CACHE_LEN (Bit 0)                                     */
-#define CACHE_CACHE_CTRL2_REG_CACHE_LEN_Msk (0x1ffUL)               /*!< CACHE_LEN (Bitfield-Mask: 0x1ff)                      */
-/* ====================================================  CACHE_FLASH_REG  ==================================================== */
-#define CACHE_CACHE_FLASH_REG_FLASH_REGION_BASE_Pos (16UL)          /*!< FLASH_REGION_BASE (Bit 16)                            */
-#define CACHE_CACHE_FLASH_REG_FLASH_REGION_BASE_Msk (0xffff0000UL)  /*!< FLASH_REGION_BASE (Bitfield-Mask: 0xffff)             */
-#define CACHE_CACHE_FLASH_REG_FLASH_REGION_OFFSET_Pos (4UL)         /*!< FLASH_REGION_OFFSET (Bit 4)                           */
-#define CACHE_CACHE_FLASH_REG_FLASH_REGION_OFFSET_Msk (0xfff0UL)    /*!< FLASH_REGION_OFFSET (Bitfield-Mask: 0xfff)            */
-#define CACHE_CACHE_FLASH_REG_FLASH_REGION_SIZE_Pos (0UL)           /*!< FLASH_REGION_SIZE (Bit 0)                             */
-#define CACHE_CACHE_FLASH_REG_FLASH_REGION_SIZE_Msk (0x7UL)         /*!< FLASH_REGION_SIZE (Bitfield-Mask: 0x07)               */
-/* ==================================================  CACHE_LNSIZECFG_REG  ================================================== */
-#define CACHE_CACHE_LNSIZECFG_REG_CACHE_LINE_Pos (0UL)              /*!< CACHE_LINE (Bit 0)                                    */
-#define CACHE_CACHE_LNSIZECFG_REG_CACHE_LINE_Msk (0x3UL)            /*!< CACHE_LINE (Bitfield-Mask: 0x03)                      */
-/* ==================================================  CACHE_MRM_CTRL_REG  =================================================== */
-#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_HITS_THRES_STATUS_Pos (4UL) /*!< MRM_IRQ_HITS_THRES_STATUS (Bit 4)                    */
-#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_HITS_THRES_STATUS_Msk (0x10UL) /*!< MRM_IRQ_HITS_THRES_STATUS (Bitfield-Mask: 0x01)   */
-#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MISSES_THRES_STATUS_Pos (3UL) /*!< MRM_IRQ_MISSES_THRES_STATUS (Bit 3)                */
-#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MISSES_THRES_STATUS_Msk (0x8UL) /*!< MRM_IRQ_MISSES_THRES_STATUS (Bitfield-Mask: 0x01) */
-#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Pos (2UL)      /*!< MRM_IRQ_TINT_STATUS (Bit 2)                           */
-#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Msk (0x4UL)    /*!< MRM_IRQ_TINT_STATUS (Bitfield-Mask: 0x01)             */
-#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Pos (1UL)             /*!< MRM_IRQ_MASK (Bit 1)                                  */
-#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Msk (0x2UL)           /*!< MRM_IRQ_MASK (Bitfield-Mask: 0x01)                    */
-#define CACHE_CACHE_MRM_CTRL_REG_MRM_START_Pos (0UL)                /*!< MRM_START (Bit 0)                                     */
-#define CACHE_CACHE_MRM_CTRL_REG_MRM_START_Msk (0x1UL)              /*!< MRM_START (Bitfield-Mask: 0x01)                       */
-/* ==================================================  CACHE_MRM_HITS_REG  =================================================== */
-#define CACHE_CACHE_MRM_HITS_REG_MRM_HITS_Pos (0UL)                 /*!< MRM_HITS (Bit 0)                                      */
-#define CACHE_CACHE_MRM_HITS_REG_MRM_HITS_Msk (0xffffffffUL)        /*!< MRM_HITS (Bitfield-Mask: 0xffffffff)                  */
-/* ===============================================  CACHE_MRM_HITS_THRES_REG  ================================================ */
-#define CACHE_CACHE_MRM_HITS_THRES_REG_MRM_HITS_THRES_Pos (0UL)     /*!< MRM_HITS_THRES (Bit 0)                                */
-#define CACHE_CACHE_MRM_HITS_THRES_REG_MRM_HITS_THRES_Msk (0xffffffffUL) /*!< MRM_HITS_THRES (Bitfield-Mask: 0xffffffff)       */
-/* =================================================  CACHE_MRM_MISSES_REG  ================================================== */
-#define CACHE_CACHE_MRM_MISSES_REG_MRM_MISSES_Pos (0UL)             /*!< MRM_MISSES (Bit 0)                                    */
-#define CACHE_CACHE_MRM_MISSES_REG_MRM_MISSES_Msk (0xffffffffUL)    /*!< MRM_MISSES (Bitfield-Mask: 0xffffffff)                */
-/* ==============================================  CACHE_MRM_MISSES_THRES_REG  =============================================== */
-#define CACHE_CACHE_MRM_MISSES_THRES_REG_MRM_MISSES_THRES_Pos (0UL) /*!< MRM_MISSES_THRES (Bit 0)                              */
-#define CACHE_CACHE_MRM_MISSES_THRES_REG_MRM_MISSES_THRES_Msk (0xffffffffUL) /*!< MRM_MISSES_THRES (Bitfield-Mask: 0xffffffff) */
-/* ==================================================  CACHE_MRM_TINT_REG  =================================================== */
-#define CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Pos (0UL)                 /*!< MRM_TINT (Bit 0)                                      */
-#define CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Msk (0x7ffffUL)           /*!< MRM_TINT (Bitfield-Mask: 0x7ffff)                     */
-/* =====================================================  SWD_RESET_REG  ===================================================== */
-#define CACHE_SWD_RESET_REG_SWD_HW_RESET_REQ_Pos (0UL)              /*!< SWD_HW_RESET_REQ (Bit 0)                              */
-#define CACHE_SWD_RESET_REG_SWD_HW_RESET_REQ_Msk (0x1UL)            /*!< SWD_HW_RESET_REQ (Bitfield-Mask: 0x01)                */
-
-
-/* =========================================================================================================================== */
-/* ================                                          CHARGER                                          ================ */
-/* =========================================================================================================================== */
-
-/* ==============================================  CHARGER_CC_CHARGE_TIMER_REG  ============================================== */
-#define CHARGER_CHARGER_CC_CHARGE_TIMER_REG_CC_CHARGE_TIMER_Pos (16UL) /*!< CC_CHARGE_TIMER (Bit 16)                           */
-#define CHARGER_CHARGER_CC_CHARGE_TIMER_REG_CC_CHARGE_TIMER_Msk (0x7fff0000UL) /*!< CC_CHARGE_TIMER (Bitfield-Mask: 0x7fff)    */
-#define CHARGER_CHARGER_CC_CHARGE_TIMER_REG_MAX_CC_CHARGE_TIME_Pos (0UL) /*!< MAX_CC_CHARGE_TIME (Bit 0)                       */
-#define CHARGER_CHARGER_CC_CHARGE_TIMER_REG_MAX_CC_CHARGE_TIME_Msk (0x7fffUL) /*!< MAX_CC_CHARGE_TIME (Bitfield-Mask: 0x7fff)  */
-/* ===================================================  CHARGER_CTRL_REG  ==================================================== */
-#define CHARGER_CHARGER_CTRL_REG_EOC_INTERVAL_CHECK_TIMER_Pos (22UL) /*!< EOC_INTERVAL_CHECK_TIMER (Bit 22)                    */
-#define CHARGER_CHARGER_CTRL_REG_EOC_INTERVAL_CHECK_TIMER_Msk (0xfc00000UL) /*!< EOC_INTERVAL_CHECK_TIMER (Bitfield-Mask: 0x3f) */
-#define CHARGER_CHARGER_CTRL_REG_EOC_INTERVAL_CHECK_THRES_Pos (16UL) /*!< EOC_INTERVAL_CHECK_THRES (Bit 16)                    */
-#define CHARGER_CHARGER_CTRL_REG_EOC_INTERVAL_CHECK_THRES_Msk (0x3f0000UL) /*!< EOC_INTERVAL_CHECK_THRES (Bitfield-Mask: 0x3f) */
-#define CHARGER_CHARGER_CTRL_REG_REPLENISH_MODE_Pos (15UL)          /*!< REPLENISH_MODE (Bit 15)                               */
-#define CHARGER_CHARGER_CTRL_REG_REPLENISH_MODE_Msk (0x8000UL)      /*!< REPLENISH_MODE (Bitfield-Mask: 0x01)                  */
-#define CHARGER_CHARGER_CTRL_REG_PRE_CHARGE_MODE_Pos (14UL)         /*!< PRE_CHARGE_MODE (Bit 14)                              */
-#define CHARGER_CHARGER_CTRL_REG_PRE_CHARGE_MODE_Msk (0x4000UL)     /*!< PRE_CHARGE_MODE (Bitfield-Mask: 0x01)                 */
-#define CHARGER_CHARGER_CTRL_REG_CHARGE_LOOP_HOLD_Pos (13UL)        /*!< CHARGE_LOOP_HOLD (Bit 13)                             */
-#define CHARGER_CHARGER_CTRL_REG_CHARGE_LOOP_HOLD_Msk (0x2000UL)    /*!< CHARGE_LOOP_HOLD (Bitfield-Mask: 0x01)                */
-#define CHARGER_CHARGER_CTRL_REG_JEITA_SUPPORT_DISABLED_Pos (12UL)  /*!< JEITA_SUPPORT_DISABLED (Bit 12)                       */
-#define CHARGER_CHARGER_CTRL_REG_JEITA_SUPPORT_DISABLED_Msk (0x1000UL) /*!< JEITA_SUPPORT_DISABLED (Bitfield-Mask: 0x01)       */
-#define CHARGER_CHARGER_CTRL_REG_TBAT_MONITOR_MODE_Pos (10UL)       /*!< TBAT_MONITOR_MODE (Bit 10)                            */
-#define CHARGER_CHARGER_CTRL_REG_TBAT_MONITOR_MODE_Msk (0xc00UL)    /*!< TBAT_MONITOR_MODE (Bitfield-Mask: 0x03)               */
-#define CHARGER_CHARGER_CTRL_REG_CHARGE_TIMERS_HALT_ENABLE_Pos (9UL) /*!< CHARGE_TIMERS_HALT_ENABLE (Bit 9)                    */
-#define CHARGER_CHARGER_CTRL_REG_CHARGE_TIMERS_HALT_ENABLE_Msk (0x200UL) /*!< CHARGE_TIMERS_HALT_ENABLE (Bitfield-Mask: 0x01)  */
-#define CHARGER_CHARGER_CTRL_REG_NTC_LOW_DISABLE_Pos (7UL)          /*!< NTC_LOW_DISABLE (Bit 7)                               */
-#define CHARGER_CHARGER_CTRL_REG_NTC_LOW_DISABLE_Msk (0x80UL)       /*!< NTC_LOW_DISABLE (Bitfield-Mask: 0x01)                 */
-#define CHARGER_CHARGER_CTRL_REG_TBAT_PROT_ENABLE_Pos (6UL)         /*!< TBAT_PROT_ENABLE (Bit 6)                              */
-#define CHARGER_CHARGER_CTRL_REG_TBAT_PROT_ENABLE_Msk (0x40UL)      /*!< TBAT_PROT_ENABLE (Bitfield-Mask: 0x01)                */
-#define CHARGER_CHARGER_CTRL_REG_TDIE_ERROR_RESUME_Pos (5UL)        /*!< TDIE_ERROR_RESUME (Bit 5)                             */
-#define CHARGER_CHARGER_CTRL_REG_TDIE_ERROR_RESUME_Msk (0x20UL)     /*!< TDIE_ERROR_RESUME (Bitfield-Mask: 0x01)               */
-#define CHARGER_CHARGER_CTRL_REG_TDIE_PROT_ENABLE_Pos (4UL)         /*!< TDIE_PROT_ENABLE (Bit 4)                              */
-#define CHARGER_CHARGER_CTRL_REG_TDIE_PROT_ENABLE_Msk (0x10UL)      /*!< TDIE_PROT_ENABLE (Bitfield-Mask: 0x01)                */
-#define CHARGER_CHARGER_CTRL_REG_CHARGER_RESUME_Pos (3UL)           /*!< CHARGER_RESUME (Bit 3)                                */
-#define CHARGER_CHARGER_CTRL_REG_CHARGER_RESUME_Msk (0x8UL)         /*!< CHARGER_RESUME (Bitfield-Mask: 0x01)                  */
-#define CHARGER_CHARGER_CTRL_REG_CHARGER_BYPASS_Pos (2UL)           /*!< CHARGER_BYPASS (Bit 2)                                */
-#define CHARGER_CHARGER_CTRL_REG_CHARGER_BYPASS_Msk (0x4UL)         /*!< CHARGER_BYPASS (Bitfield-Mask: 0x01)                  */
-#define CHARGER_CHARGER_CTRL_REG_CHARGE_START_Pos (1UL)             /*!< CHARGE_START (Bit 1)                                  */
-#define CHARGER_CHARGER_CTRL_REG_CHARGE_START_Msk (0x2UL)           /*!< CHARGE_START (Bitfield-Mask: 0x01)                    */
-#define CHARGER_CHARGER_CTRL_REG_CHARGER_ENABLE_Pos (0UL)           /*!< CHARGER_ENABLE (Bit 0)                                */
-#define CHARGER_CHARGER_CTRL_REG_CHARGER_ENABLE_Msk (0x1UL)         /*!< CHARGER_ENABLE (Bitfield-Mask: 0x01)                  */
-/* ===============================================  CHARGER_CURRENT_PARAM_REG  =============================================== */
-#define CHARGER_CHARGER_CURRENT_PARAM_REG_I_EOC_DOUBLE_RANGE_Pos (15UL) /*!< I_EOC_DOUBLE_RANGE (Bit 15)                       */
-#define CHARGER_CHARGER_CURRENT_PARAM_REG_I_EOC_DOUBLE_RANGE_Msk (0x8000UL) /*!< I_EOC_DOUBLE_RANGE (Bitfield-Mask: 0x01)      */
-#define CHARGER_CHARGER_CURRENT_PARAM_REG_I_END_OF_CHARGE_Pos (12UL) /*!< I_END_OF_CHARGE (Bit 12)                             */
-#define CHARGER_CHARGER_CURRENT_PARAM_REG_I_END_OF_CHARGE_Msk (0x7000UL) /*!< I_END_OF_CHARGE (Bitfield-Mask: 0x07)            */
-#define CHARGER_CHARGER_CURRENT_PARAM_REG_I_PRECHARGE_Pos (6UL)     /*!< I_PRECHARGE (Bit 6)                                   */
-#define CHARGER_CHARGER_CURRENT_PARAM_REG_I_PRECHARGE_Msk (0xfc0UL) /*!< I_PRECHARGE (Bitfield-Mask: 0x3f)                     */
-#define CHARGER_CHARGER_CURRENT_PARAM_REG_I_CHARGE_Pos (0UL)        /*!< I_CHARGE (Bit 0)                                      */
-#define CHARGER_CHARGER_CURRENT_PARAM_REG_I_CHARGE_Msk (0x3fUL)     /*!< I_CHARGE (Bitfield-Mask: 0x3f)                        */
-/* ==============================================  CHARGER_CV_CHARGE_TIMER_REG  ============================================== */
-#define CHARGER_CHARGER_CV_CHARGE_TIMER_REG_CV_CHARGE_TIMER_Pos (16UL) /*!< CV_CHARGE_TIMER (Bit 16)                           */
-#define CHARGER_CHARGER_CV_CHARGE_TIMER_REG_CV_CHARGE_TIMER_Msk (0x7fff0000UL) /*!< CV_CHARGE_TIMER (Bitfield-Mask: 0x7fff)    */
-#define CHARGER_CHARGER_CV_CHARGE_TIMER_REG_MAX_CV_CHARGE_TIME_Pos (0UL) /*!< MAX_CV_CHARGE_TIME (Bit 0)                       */
-#define CHARGER_CHARGER_CV_CHARGE_TIMER_REG_MAX_CV_CHARGE_TIME_Msk (0x7fffUL) /*!< MAX_CV_CHARGE_TIME (Bitfield-Mask: 0x7fff)  */
-/* ===============================================  CHARGER_ERROR_IRQ_CLR_REG  =============================================== */
-#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_TBAT_ERROR_IRQ_CLR_Pos (6UL) /*!< TBAT_ERROR_IRQ_CLR (Bit 6)                         */
-#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_TBAT_ERROR_IRQ_CLR_Msk (0x40UL) /*!< TBAT_ERROR_IRQ_CLR (Bitfield-Mask: 0x01)        */
-#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_TDIE_ERROR_IRQ_CLR_Pos (5UL) /*!< TDIE_ERROR_IRQ_CLR (Bit 5)                         */
-#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_TDIE_ERROR_IRQ_CLR_Msk (0x20UL) /*!< TDIE_ERROR_IRQ_CLR (Bitfield-Mask: 0x01)        */
-#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_VBAT_OVP_ERROR_IRQ_CLR_Pos (4UL) /*!< VBAT_OVP_ERROR_IRQ_CLR (Bit 4)                 */
-#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_VBAT_OVP_ERROR_IRQ_CLR_Msk (0x10UL) /*!< VBAT_OVP_ERROR_IRQ_CLR (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_TOTAL_CHARGE_TIMEOUT_IRQ_CLR_Pos (3UL) /*!< TOTAL_CHARGE_TIMEOUT_IRQ_CLR (Bit 3)     */
-#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_TOTAL_CHARGE_TIMEOUT_IRQ_CLR_Msk (0x8UL) /*!< TOTAL_CHARGE_TIMEOUT_IRQ_CLR (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_CV_CHARGE_TIMEOUT_IRQ_CLR_Pos (2UL) /*!< CV_CHARGE_TIMEOUT_IRQ_CLR (Bit 2)           */
-#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_CV_CHARGE_TIMEOUT_IRQ_CLR_Msk (0x4UL) /*!< CV_CHARGE_TIMEOUT_IRQ_CLR (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_CC_CHARGE_TIMEOUT_IRQ_CLR_Pos (1UL) /*!< CC_CHARGE_TIMEOUT_IRQ_CLR (Bit 1)           */
-#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_CC_CHARGE_TIMEOUT_IRQ_CLR_Msk (0x2UL) /*!< CC_CHARGE_TIMEOUT_IRQ_CLR (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_PRECHARGE_TIMEOUT_IRQ_CLR_Pos (0UL) /*!< PRECHARGE_TIMEOUT_IRQ_CLR (Bit 0)           */
-#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_PRECHARGE_TIMEOUT_IRQ_CLR_Msk (0x1UL) /*!< PRECHARGE_TIMEOUT_IRQ_CLR (Bitfield-Mask: 0x01) */
-/* ==============================================  CHARGER_ERROR_IRQ_MASK_REG  =============================================== */
-#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_TBAT_ERROR_IRQ_EN_Pos (6UL) /*!< TBAT_ERROR_IRQ_EN (Bit 6)                          */
-#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_TBAT_ERROR_IRQ_EN_Msk (0x40UL) /*!< TBAT_ERROR_IRQ_EN (Bitfield-Mask: 0x01)         */
-#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_TDIE_ERROR_IRQ_EN_Pos (5UL) /*!< TDIE_ERROR_IRQ_EN (Bit 5)                          */
-#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_TDIE_ERROR_IRQ_EN_Msk (0x20UL) /*!< TDIE_ERROR_IRQ_EN (Bitfield-Mask: 0x01)         */
-#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_VBAT_OVP_ERROR_IRQ_EN_Pos (4UL) /*!< VBAT_OVP_ERROR_IRQ_EN (Bit 4)                  */
-#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_VBAT_OVP_ERROR_IRQ_EN_Msk (0x10UL) /*!< VBAT_OVP_ERROR_IRQ_EN (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_TOTAL_CHARGE_TIMEOUT_IRQ_EN_Pos (3UL) /*!< TOTAL_CHARGE_TIMEOUT_IRQ_EN (Bit 3)      */
-#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_TOTAL_CHARGE_TIMEOUT_IRQ_EN_Msk (0x8UL) /*!< TOTAL_CHARGE_TIMEOUT_IRQ_EN (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_CV_CHARGE_TIMEOUT_IRQ_EN_Pos (2UL) /*!< CV_CHARGE_TIMEOUT_IRQ_EN (Bit 2)            */
-#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_CV_CHARGE_TIMEOUT_IRQ_EN_Msk (0x4UL) /*!< CV_CHARGE_TIMEOUT_IRQ_EN (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_CC_CHARGE_TIMEOUT_IRQ_EN_Pos (1UL) /*!< CC_CHARGE_TIMEOUT_IRQ_EN (Bit 1)            */
-#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_CC_CHARGE_TIMEOUT_IRQ_EN_Msk (0x2UL) /*!< CC_CHARGE_TIMEOUT_IRQ_EN (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_PRECHARGE_TIMEOUT_IRQ_EN_Pos (0UL) /*!< PRECHARGE_TIMEOUT_IRQ_EN (Bit 0)            */
-#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_PRECHARGE_TIMEOUT_IRQ_EN_Msk (0x1UL) /*!< PRECHARGE_TIMEOUT_IRQ_EN (Bitfield-Mask: 0x01) */
-/* =============================================  CHARGER_ERROR_IRQ_STATUS_REG  ============================================== */
-#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_TBAT_ERROR_IRQ_Pos (6UL) /*!< TBAT_ERROR_IRQ (Bit 6)                              */
-#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_TBAT_ERROR_IRQ_Msk (0x40UL) /*!< TBAT_ERROR_IRQ (Bitfield-Mask: 0x01)             */
-#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_TDIE_ERROR_IRQ_Pos (5UL) /*!< TDIE_ERROR_IRQ (Bit 5)                              */
-#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_TDIE_ERROR_IRQ_Msk (0x20UL) /*!< TDIE_ERROR_IRQ (Bitfield-Mask: 0x01)             */
-#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_VBAT_OVP_ERROR_IRQ_Pos (4UL) /*!< VBAT_OVP_ERROR_IRQ (Bit 4)                      */
-#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_VBAT_OVP_ERROR_IRQ_Msk (0x10UL) /*!< VBAT_OVP_ERROR_IRQ (Bitfield-Mask: 0x01)     */
-#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_TOTAL_CHARGE_TIMEOUT_IRQ_Pos (3UL) /*!< TOTAL_CHARGE_TIMEOUT_IRQ (Bit 3)          */
-#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_TOTAL_CHARGE_TIMEOUT_IRQ_Msk (0x8UL) /*!< TOTAL_CHARGE_TIMEOUT_IRQ (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_CV_CHARGE_TIMEOUT_IRQ_Pos (2UL) /*!< CV_CHARGE_TIMEOUT_IRQ (Bit 2)                */
-#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_CV_CHARGE_TIMEOUT_IRQ_Msk (0x4UL) /*!< CV_CHARGE_TIMEOUT_IRQ (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_CC_CHARGE_TIMEOUT_IRQ_Pos (1UL) /*!< CC_CHARGE_TIMEOUT_IRQ (Bit 1)                */
-#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_CC_CHARGE_TIMEOUT_IRQ_Msk (0x2UL) /*!< CC_CHARGE_TIMEOUT_IRQ (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_PRECHARGE_TIMEOUT_IRQ_Pos (0UL) /*!< PRECHARGE_TIMEOUT_IRQ (Bit 0)                */
-#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_PRECHARGE_TIMEOUT_IRQ_Msk (0x1UL) /*!< PRECHARGE_TIMEOUT_IRQ (Bitfield-Mask: 0x01) */
-/* ===============================================  CHARGER_JEITA_CURRENT_REG  =============================================== */
-#define CHARGER_CHARGER_JEITA_CURRENT_REG_I_PRECHARGE_TWARM_Pos (18UL) /*!< I_PRECHARGE_TWARM (Bit 18)                         */
-#define CHARGER_CHARGER_JEITA_CURRENT_REG_I_PRECHARGE_TWARM_Msk (0xfc0000UL) /*!< I_PRECHARGE_TWARM (Bitfield-Mask: 0x3f)      */
-#define CHARGER_CHARGER_JEITA_CURRENT_REG_I_PRECHARGE_TCOOL_Pos (12UL) /*!< I_PRECHARGE_TCOOL (Bit 12)                         */
-#define CHARGER_CHARGER_JEITA_CURRENT_REG_I_PRECHARGE_TCOOL_Msk (0x3f000UL) /*!< I_PRECHARGE_TCOOL (Bitfield-Mask: 0x3f)       */
-#define CHARGER_CHARGER_JEITA_CURRENT_REG_I_CHARGE_TWARM_Pos (6UL)  /*!< I_CHARGE_TWARM (Bit 6)                                */
-#define CHARGER_CHARGER_JEITA_CURRENT_REG_I_CHARGE_TWARM_Msk (0xfc0UL) /*!< I_CHARGE_TWARM (Bitfield-Mask: 0x3f)               */
-#define CHARGER_CHARGER_JEITA_CURRENT_REG_I_CHARGE_TCOOL_Pos (0UL)  /*!< I_CHARGE_TCOOL (Bit 0)                                */
-#define CHARGER_CHARGER_JEITA_CURRENT_REG_I_CHARGE_TCOOL_Msk (0x3fUL) /*!< I_CHARGE_TCOOL (Bitfield-Mask: 0x3f)                */
-/* ==============================================  CHARGER_JEITA_V_CHARGE_REG  =============================================== */
-#define CHARGER_CHARGER_JEITA_V_CHARGE_REG_V_CHARGE_TWARM_Pos (6UL) /*!< V_CHARGE_TWARM (Bit 6)                                */
-#define CHARGER_CHARGER_JEITA_V_CHARGE_REG_V_CHARGE_TWARM_Msk (0xfc0UL) /*!< V_CHARGE_TWARM (Bitfield-Mask: 0x3f)              */
-#define CHARGER_CHARGER_JEITA_V_CHARGE_REG_V_CHARGE_TCOOL_Pos (0UL) /*!< V_CHARGE_TCOOL (Bit 0)                                */
-#define CHARGER_CHARGER_JEITA_V_CHARGE_REG_V_CHARGE_TCOOL_Msk (0x3fUL) /*!< V_CHARGE_TCOOL (Bitfield-Mask: 0x3f)               */
-/* ================================================  CHARGER_JEITA_V_OVP_REG  ================================================ */
-#define CHARGER_CHARGER_JEITA_V_OVP_REG_V_OVP_TWARM_Pos (6UL)       /*!< V_OVP_TWARM (Bit 6)                                   */
-#define CHARGER_CHARGER_JEITA_V_OVP_REG_V_OVP_TWARM_Msk (0xfc0UL)   /*!< V_OVP_TWARM (Bitfield-Mask: 0x3f)                     */
-#define CHARGER_CHARGER_JEITA_V_OVP_REG_V_OVP_TCOOL_Pos (0UL)       /*!< V_OVP_TCOOL (Bit 0)                                   */
-#define CHARGER_CHARGER_JEITA_V_OVP_REG_V_OVP_TCOOL_Msk (0x3fUL)    /*!< V_OVP_TCOOL (Bitfield-Mask: 0x3f)                     */
-/* =============================================  CHARGER_JEITA_V_PRECHARGE_REG  ============================================= */
-#define CHARGER_CHARGER_JEITA_V_PRECHARGE_REG_V_PRECHARGE_TWARM_Pos (6UL) /*!< V_PRECHARGE_TWARM (Bit 6)                       */
-#define CHARGER_CHARGER_JEITA_V_PRECHARGE_REG_V_PRECHARGE_TWARM_Msk (0xfc0UL) /*!< V_PRECHARGE_TWARM (Bitfield-Mask: 0x3f)     */
-#define CHARGER_CHARGER_JEITA_V_PRECHARGE_REG_V_PRECHARGE_TCOOL_Pos (0UL) /*!< V_PRECHARGE_TCOOL (Bit 0)                       */
-#define CHARGER_CHARGER_JEITA_V_PRECHARGE_REG_V_PRECHARGE_TCOOL_Msk (0x3fUL) /*!< V_PRECHARGE_TCOOL (Bitfield-Mask: 0x3f)      */
-/* =============================================  CHARGER_JEITA_V_REPLENISH_REG  ============================================= */
-#define CHARGER_CHARGER_JEITA_V_REPLENISH_REG_V_REPLENISH_TWARM_Pos (6UL) /*!< V_REPLENISH_TWARM (Bit 6)                       */
-#define CHARGER_CHARGER_JEITA_V_REPLENISH_REG_V_REPLENISH_TWARM_Msk (0xfc0UL) /*!< V_REPLENISH_TWARM (Bitfield-Mask: 0x3f)     */
-#define CHARGER_CHARGER_JEITA_V_REPLENISH_REG_V_REPLENISH_TCOOL_Pos (0UL) /*!< V_REPLENISH_TCOOL (Bit 0)                       */
-#define CHARGER_CHARGER_JEITA_V_REPLENISH_REG_V_REPLENISH_TCOOL_Msk (0x3fUL) /*!< V_REPLENISH_TCOOL (Bitfield-Mask: 0x3f)      */
-/* =============================================  CHARGER_PRE_CHARGE_TIMER_REG  ============================================== */
-#define CHARGER_CHARGER_PRE_CHARGE_TIMER_REG_PRE_CHARGE_TIMER_Pos (16UL) /*!< PRE_CHARGE_TIMER (Bit 16)                        */
-#define CHARGER_CHARGER_PRE_CHARGE_TIMER_REG_PRE_CHARGE_TIMER_Msk (0x7fff0000UL) /*!< PRE_CHARGE_TIMER (Bitfield-Mask: 0x7fff) */
-#define CHARGER_CHARGER_PRE_CHARGE_TIMER_REG_MAX_PRE_CHARGE_TIME_Pos (0UL) /*!< MAX_PRE_CHARGE_TIME (Bit 0)                    */
-#define CHARGER_CHARGER_PRE_CHARGE_TIMER_REG_MAX_PRE_CHARGE_TIME_Msk (0x7fffUL) /*!< MAX_PRE_CHARGE_TIME (Bitfield-Mask: 0x7fff) */
-/* ===============================================  CHARGER_PWR_UP_TIMER_REG  ================================================ */
-#define CHARGER_CHARGER_PWR_UP_TIMER_REG_CHARGER_PWR_UP_TIMER_Pos (16UL) /*!< CHARGER_PWR_UP_TIMER (Bit 16)                    */
-#define CHARGER_CHARGER_PWR_UP_TIMER_REG_CHARGER_PWR_UP_TIMER_Msk (0x3ff0000UL) /*!< CHARGER_PWR_UP_TIMER (Bitfield-Mask: 0x3ff) */
-#define CHARGER_CHARGER_PWR_UP_TIMER_REG_CHARGER_PWR_UP_SETTLING_Pos (0UL) /*!< CHARGER_PWR_UP_SETTLING (Bit 0)                */
-#define CHARGER_CHARGER_PWR_UP_TIMER_REG_CHARGER_PWR_UP_SETTLING_Msk (0x3ffUL) /*!< CHARGER_PWR_UP_SETTLING (Bitfield-Mask: 0x3ff) */
-/* ===============================================  CHARGER_STATE_IRQ_CLR_REG  =============================================== */
-#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CV_TO_PRECHARGE_IRQ_CLR_Pos (11UL) /*!< CV_TO_PRECHARGE_IRQ_CLR (Bit 11)             */
-#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CV_TO_PRECHARGE_IRQ_CLR_Msk (0x800UL) /*!< CV_TO_PRECHARGE_IRQ_CLR (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CC_TO_PRECHARGE_IRQ_CLR_Pos (10UL) /*!< CC_TO_PRECHARGE_IRQ_CLR (Bit 10)             */
-#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CC_TO_PRECHARGE_IRQ_CLR_Msk (0x400UL) /*!< CC_TO_PRECHARGE_IRQ_CLR (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CV_TO_CC_IRQ_CLR_Pos (9UL) /*!< CV_TO_CC_IRQ_CLR (Bit 9)                             */
-#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CV_TO_CC_IRQ_CLR_Msk (0x200UL) /*!< CV_TO_CC_IRQ_CLR (Bitfield-Mask: 0x01)           */
-#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_TBAT_STATUS_UPDATE_IRQ_CLR_Pos (8UL) /*!< TBAT_STATUS_UPDATE_IRQ_CLR (Bit 8)         */
-#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_TBAT_STATUS_UPDATE_IRQ_CLR_Msk (0x100UL) /*!< TBAT_STATUS_UPDATE_IRQ_CLR (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_TBAT_PROT_TO_PRECHARGE_IRQ_CLR_Pos (7UL) /*!< TBAT_PROT_TO_PRECHARGE_IRQ_CLR (Bit 7) */
-#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_TBAT_PROT_TO_PRECHARGE_IRQ_CLR_Msk (0x80UL) /*!< TBAT_PROT_TO_PRECHARGE_IRQ_CLR (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_TDIE_PROT_TO_PRECHARGE_IRQ_CLR_Pos (6UL) /*!< TDIE_PROT_TO_PRECHARGE_IRQ_CLR (Bit 6) */
-#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_TDIE_PROT_TO_PRECHARGE_IRQ_CLR_Msk (0x40UL) /*!< TDIE_PROT_TO_PRECHARGE_IRQ_CLR (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_EOC_TO_PRECHARGE_IRQ_CLR_Pos (5UL) /*!< EOC_TO_PRECHARGE_IRQ_CLR (Bit 5)             */
-#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_EOC_TO_PRECHARGE_IRQ_CLR_Msk (0x20UL) /*!< EOC_TO_PRECHARGE_IRQ_CLR (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CV_TO_EOC_IRQ_CLR_Pos (4UL) /*!< CV_TO_EOC_IRQ_CLR (Bit 4)                           */
-#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CV_TO_EOC_IRQ_CLR_Msk (0x10UL) /*!< CV_TO_EOC_IRQ_CLR (Bitfield-Mask: 0x01)          */
-#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CC_TO_EOC_IRQ_CLR_Pos (3UL) /*!< CC_TO_EOC_IRQ_CLR (Bit 3)                           */
-#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CC_TO_EOC_IRQ_CLR_Msk (0x8UL) /*!< CC_TO_EOC_IRQ_CLR (Bitfield-Mask: 0x01)           */
-#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CC_TO_CV_IRQ_CLR_Pos (2UL) /*!< CC_TO_CV_IRQ_CLR (Bit 2)                             */
-#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CC_TO_CV_IRQ_CLR_Msk (0x4UL) /*!< CC_TO_CV_IRQ_CLR (Bitfield-Mask: 0x01)             */
-#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_PRECHARGE_TO_CC_IRQ_CLR_Pos (1UL) /*!< PRECHARGE_TO_CC_IRQ_CLR (Bit 1)               */
-#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_PRECHARGE_TO_CC_IRQ_CLR_Msk (0x2UL) /*!< PRECHARGE_TO_CC_IRQ_CLR (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_DISABLED_TO_PRECHARGE_IRQ_CLR_Pos (0UL) /*!< DISABLED_TO_PRECHARGE_IRQ_CLR (Bit 0)   */
-#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_DISABLED_TO_PRECHARGE_IRQ_CLR_Msk (0x1UL) /*!< DISABLED_TO_PRECHARGE_IRQ_CLR (Bitfield-Mask: 0x01) */
-/* ==============================================  CHARGER_STATE_IRQ_MASK_REG  =============================================== */
-#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CV_TO_PRECHARGE_IRQ_EN_Pos (11UL) /*!< CV_TO_PRECHARGE_IRQ_EN (Bit 11)              */
-#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CV_TO_PRECHARGE_IRQ_EN_Msk (0x800UL) /*!< CV_TO_PRECHARGE_IRQ_EN (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CC_TO_PRECHARGE_IRQ_EN_Pos (10UL) /*!< CC_TO_PRECHARGE_IRQ_EN (Bit 10)              */
-#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CC_TO_PRECHARGE_IRQ_EN_Msk (0x400UL) /*!< CC_TO_PRECHARGE_IRQ_EN (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CV_TO_CC_IRQ_EN_Pos (9UL) /*!< CV_TO_CC_IRQ_EN (Bit 9)                              */
-#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CV_TO_CC_IRQ_EN_Msk (0x200UL) /*!< CV_TO_CC_IRQ_EN (Bitfield-Mask: 0x01)            */
-#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_TBAT_STATUS_UPDATE_IRQ_EN_Pos (8UL) /*!< TBAT_STATUS_UPDATE_IRQ_EN (Bit 8)          */
-#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_TBAT_STATUS_UPDATE_IRQ_EN_Msk (0x100UL) /*!< TBAT_STATUS_UPDATE_IRQ_EN (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_TBAT_PROT_TO_PRECHARGE_IRQ_EN_Pos (7UL) /*!< TBAT_PROT_TO_PRECHARGE_IRQ_EN (Bit 7)  */
-#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_TBAT_PROT_TO_PRECHARGE_IRQ_EN_Msk (0x80UL) /*!< TBAT_PROT_TO_PRECHARGE_IRQ_EN (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_TDIE_PROT_TO_PRECHARGE_IRQ_EN_Pos (6UL) /*!< TDIE_PROT_TO_PRECHARGE_IRQ_EN (Bit 6)  */
-#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_TDIE_PROT_TO_PRECHARGE_IRQ_EN_Msk (0x40UL) /*!< TDIE_PROT_TO_PRECHARGE_IRQ_EN (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_EOC_TO_PRECHARGE_IRQ_EN_Pos (5UL) /*!< EOC_TO_PRECHARGE_IRQ_EN (Bit 5)              */
-#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_EOC_TO_PRECHARGE_IRQ_EN_Msk (0x20UL) /*!< EOC_TO_PRECHARGE_IRQ_EN (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CV_TO_EOC_IRQ_EN_Pos (4UL) /*!< CV_TO_EOC_IRQ_EN (Bit 4)                            */
-#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CV_TO_EOC_IRQ_EN_Msk (0x10UL) /*!< CV_TO_EOC_IRQ_EN (Bitfield-Mask: 0x01)           */
-#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CC_TO_EOC_IRQ_EN_Pos (3UL) /*!< CC_TO_EOC_IRQ_EN (Bit 3)                            */
-#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CC_TO_EOC_IRQ_EN_Msk (0x8UL) /*!< CC_TO_EOC_IRQ_EN (Bitfield-Mask: 0x01)            */
-#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CC_TO_CV_IRQ_EN_Pos (2UL) /*!< CC_TO_CV_IRQ_EN (Bit 2)                              */
-#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CC_TO_CV_IRQ_EN_Msk (0x4UL) /*!< CC_TO_CV_IRQ_EN (Bitfield-Mask: 0x01)              */
-#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_PRECHARGE_TO_CC_IRQ_EN_Pos (1UL) /*!< PRECHARGE_TO_CC_IRQ_EN (Bit 1)                */
-#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_PRECHARGE_TO_CC_IRQ_EN_Msk (0x2UL) /*!< PRECHARGE_TO_CC_IRQ_EN (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_DISABLED_TO_PRECHARGE_IRQ_EN_Pos (0UL) /*!< DISABLED_TO_PRECHARGE_IRQ_EN (Bit 0)    */
-#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_DISABLED_TO_PRECHARGE_IRQ_EN_Msk (0x1UL) /*!< DISABLED_TO_PRECHARGE_IRQ_EN (Bitfield-Mask: 0x01) */
-/* =============================================  CHARGER_STATE_IRQ_STATUS_REG  ============================================== */
-#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CV_TO_PRECHARGE_IRQ_Pos (11UL) /*!< CV_TO_PRECHARGE_IRQ (Bit 11)                  */
-#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CV_TO_PRECHARGE_IRQ_Msk (0x800UL) /*!< CV_TO_PRECHARGE_IRQ (Bitfield-Mask: 0x01)  */
-#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CC_TO_PRECHARGE_IRQ_Pos (10UL) /*!< CC_TO_PRECHARGE_IRQ (Bit 10)                  */
-#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CC_TO_PRECHARGE_IRQ_Msk (0x400UL) /*!< CC_TO_PRECHARGE_IRQ (Bitfield-Mask: 0x01)  */
-#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CV_TO_CC_IRQ_Pos (9UL) /*!< CV_TO_CC_IRQ (Bit 9)                                  */
-#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CV_TO_CC_IRQ_Msk (0x200UL) /*!< CV_TO_CC_IRQ (Bitfield-Mask: 0x01)                */
-#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_TBAT_STATUS_UPDATE_IRQ_Pos (8UL) /*!< TBAT_STATUS_UPDATE_IRQ (Bit 8)              */
-#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_TBAT_STATUS_UPDATE_IRQ_Msk (0x100UL) /*!< TBAT_STATUS_UPDATE_IRQ (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_TBAT_PROT_TO_PRECHARGE_IRQ_Pos (7UL) /*!< TBAT_PROT_TO_PRECHARGE_IRQ (Bit 7)      */
-#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_TBAT_PROT_TO_PRECHARGE_IRQ_Msk (0x80UL) /*!< TBAT_PROT_TO_PRECHARGE_IRQ (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_TDIE_PROT_TO_PRECHARGE_IRQ_Pos (6UL) /*!< TDIE_PROT_TO_PRECHARGE_IRQ (Bit 6)      */
-#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_TDIE_PROT_TO_PRECHARGE_IRQ_Msk (0x40UL) /*!< TDIE_PROT_TO_PRECHARGE_IRQ (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_EOC_TO_PRECHARGE_IRQ_Pos (5UL) /*!< EOC_TO_PRECHARGE_IRQ (Bit 5)                  */
-#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_EOC_TO_PRECHARGE_IRQ_Msk (0x20UL) /*!< EOC_TO_PRECHARGE_IRQ (Bitfield-Mask: 0x01) */
-#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CV_TO_EOC_IRQ_Pos (4UL) /*!< CV_TO_EOC_IRQ (Bit 4)                                */
-#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CV_TO_EOC_IRQ_Msk (0x10UL) /*!< CV_TO_EOC_IRQ (Bitfield-Mask: 0x01)               */
-#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CC_TO_EOC_IRQ_Pos (3UL) /*!< CC_TO_EOC_IRQ (Bit 3)                                */
-#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CC_TO_EOC_IRQ_Msk (0x8UL) /*!< CC_TO_EOC_IRQ (Bitfield-Mask: 0x01)                */
-#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CC_TO_CV_IRQ_Pos (2UL) /*!< CC_TO_CV_IRQ (Bit 2)                                  */
-#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CC_TO_CV_IRQ_Msk (0x4UL) /*!< CC_TO_CV_IRQ (Bitfield-Mask: 0x01)                  */
-#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_PRECHARGE_TO_CC_IRQ_Pos (1UL) /*!< PRECHARGE_TO_CC_IRQ (Bit 1)                    */
-#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_PRECHARGE_TO_CC_IRQ_Msk (0x2UL) /*!< PRECHARGE_TO_CC_IRQ (Bitfield-Mask: 0x01)    */
-#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_DISABLED_TO_PRECHARGE_IRQ_Pos (0UL) /*!< DISABLED_TO_PRECHARGE_IRQ (Bit 0)        */
-#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_DISABLED_TO_PRECHARGE_IRQ_Msk (0x1UL) /*!< DISABLED_TO_PRECHARGE_IRQ (Bitfield-Mask: 0x01) */
-/* ==================================================  CHARGER_STATUS_REG  =================================================== */
-#define CHARGER_CHARGER_STATUS_REG_OVP_EVENTS_DEBOUNCE_CNT_Pos (27UL) /*!< OVP_EVENTS_DEBOUNCE_CNT (Bit 27)                    */
-#define CHARGER_CHARGER_STATUS_REG_OVP_EVENTS_DEBOUNCE_CNT_Msk (0x38000000UL) /*!< OVP_EVENTS_DEBOUNCE_CNT (Bitfield-Mask: 0x07) */
-#define CHARGER_CHARGER_STATUS_REG_EOC_EVENTS_DEBOUNCE_CNT_Pos (24UL) /*!< EOC_EVENTS_DEBOUNCE_CNT (Bit 24)                    */
-#define CHARGER_CHARGER_STATUS_REG_EOC_EVENTS_DEBOUNCE_CNT_Msk (0x7000000UL) /*!< EOC_EVENTS_DEBOUNCE_CNT (Bitfield-Mask: 0x07) */
-#define CHARGER_CHARGER_STATUS_REG_TDIE_ERROR_DEBOUNCE_CNT_Pos (21UL) /*!< TDIE_ERROR_DEBOUNCE_CNT (Bit 21)                    */
-#define CHARGER_CHARGER_STATUS_REG_TDIE_ERROR_DEBOUNCE_CNT_Msk (0xe00000UL) /*!< TDIE_ERROR_DEBOUNCE_CNT (Bitfield-Mask: 0x07) */
-#define CHARGER_CHARGER_STATUS_REG_CHARGER_JEITA_STATE_Pos (18UL)   /*!< CHARGER_JEITA_STATE (Bit 18)                          */
-#define CHARGER_CHARGER_STATUS_REG_CHARGER_JEITA_STATE_Msk (0x1c0000UL) /*!< CHARGER_JEITA_STATE (Bitfield-Mask: 0x07)         */
-#define CHARGER_CHARGER_STATUS_REG_CHARGER_STATE_Pos (14UL)         /*!< CHARGER_STATE (Bit 14)                                */
-#define CHARGER_CHARGER_STATUS_REG_CHARGER_STATE_Msk (0x3c000UL)    /*!< CHARGER_STATE (Bitfield-Mask: 0x0f)                   */
-#define CHARGER_CHARGER_STATUS_REG_TBAT_STATUS_Pos (9UL)            /*!< TBAT_STATUS (Bit 9)                                   */
-#define CHARGER_CHARGER_STATUS_REG_TBAT_STATUS_Msk (0x3e00UL)       /*!< TBAT_STATUS (Bitfield-Mask: 0x1f)                     */
-#define CHARGER_CHARGER_STATUS_REG_MAIN_TBAT_COMP_OUT_Pos (8UL)     /*!< MAIN_TBAT_COMP_OUT (Bit 8)                            */
-#define CHARGER_CHARGER_STATUS_REG_MAIN_TBAT_COMP_OUT_Msk (0x100UL) /*!< MAIN_TBAT_COMP_OUT (Bitfield-Mask: 0x01)              */
-#define CHARGER_CHARGER_STATUS_REG_TBAT_HOT_COMP_OUT_Pos (7UL)      /*!< TBAT_HOT_COMP_OUT (Bit 7)                             */
-#define CHARGER_CHARGER_STATUS_REG_TBAT_HOT_COMP_OUT_Msk (0x80UL)   /*!< TBAT_HOT_COMP_OUT (Bitfield-Mask: 0x01)               */
-#define CHARGER_CHARGER_STATUS_REG_TDIE_COMP_OUT_Pos (6UL)          /*!< TDIE_COMP_OUT (Bit 6)                                 */
-#define CHARGER_CHARGER_STATUS_REG_TDIE_COMP_OUT_Msk (0x40UL)       /*!< TDIE_COMP_OUT (Bitfield-Mask: 0x01)                   */
-#define CHARGER_CHARGER_STATUS_REG_VBAT_OVP_COMP_OUT_Pos (5UL)      /*!< VBAT_OVP_COMP_OUT (Bit 5)                             */
-#define CHARGER_CHARGER_STATUS_REG_VBAT_OVP_COMP_OUT_Msk (0x20UL)   /*!< VBAT_OVP_COMP_OUT (Bitfield-Mask: 0x01)               */
-#define CHARGER_CHARGER_STATUS_REG_MAIN_VBAT_COMP_OUT_Pos (4UL)     /*!< MAIN_VBAT_COMP_OUT (Bit 4)                            */
-#define CHARGER_CHARGER_STATUS_REG_MAIN_VBAT_COMP_OUT_Msk (0x10UL)  /*!< MAIN_VBAT_COMP_OUT (Bitfield-Mask: 0x01)              */
-#define CHARGER_CHARGER_STATUS_REG_END_OF_CHARGE_Pos (3UL)          /*!< END_OF_CHARGE (Bit 3)                                 */
-#define CHARGER_CHARGER_STATUS_REG_END_OF_CHARGE_Msk (0x8UL)        /*!< END_OF_CHARGE (Bitfield-Mask: 0x01)                   */
-#define CHARGER_CHARGER_STATUS_REG_CHARGER_CV_MODE_Pos (2UL)        /*!< CHARGER_CV_MODE (Bit 2)                               */
-#define CHARGER_CHARGER_STATUS_REG_CHARGER_CV_MODE_Msk (0x4UL)      /*!< CHARGER_CV_MODE (Bitfield-Mask: 0x01)                 */
-#define CHARGER_CHARGER_STATUS_REG_CHARGER_CC_MODE_Pos (1UL)        /*!< CHARGER_CC_MODE (Bit 1)                               */
-#define CHARGER_CHARGER_STATUS_REG_CHARGER_CC_MODE_Msk (0x2UL)      /*!< CHARGER_CC_MODE (Bitfield-Mask: 0x01)                 */
-#define CHARGER_CHARGER_STATUS_REG_CHARGER_IS_POWERED_UP_Pos (0UL)  /*!< CHARGER_IS_POWERED_UP (Bit 0)                         */
-#define CHARGER_CHARGER_STATUS_REG_CHARGER_IS_POWERED_UP_Msk (0x1UL) /*!< CHARGER_IS_POWERED_UP (Bitfield-Mask: 0x01)          */
-/* ==============================================  CHARGER_TBAT_COMP_TIMER_REG  ============================================== */
-#define CHARGER_CHARGER_TBAT_COMP_TIMER_REG_TBAT_COMP_TIMER_Pos (16UL) /*!< TBAT_COMP_TIMER (Bit 16)                           */
-#define CHARGER_CHARGER_TBAT_COMP_TIMER_REG_TBAT_COMP_TIMER_Msk (0x3ff0000UL) /*!< TBAT_COMP_TIMER (Bitfield-Mask: 0x3ff)      */
-#define CHARGER_CHARGER_TBAT_COMP_TIMER_REG_TBAT_COMP_SETTLING_Pos (0UL) /*!< TBAT_COMP_SETTLING (Bit 0)                       */
-#define CHARGER_CHARGER_TBAT_COMP_TIMER_REG_TBAT_COMP_SETTLING_Msk (0x3ffUL) /*!< TBAT_COMP_SETTLING (Bitfield-Mask: 0x3ff)    */
-/* ==============================================  CHARGER_TBAT_MON_TIMER_REG  =============================================== */
-#define CHARGER_CHARGER_TBAT_MON_TIMER_REG_TBAT_MON_TIMER_Pos (16UL) /*!< TBAT_MON_TIMER (Bit 16)                              */
-#define CHARGER_CHARGER_TBAT_MON_TIMER_REG_TBAT_MON_TIMER_Msk (0x3ff0000UL) /*!< TBAT_MON_TIMER (Bitfield-Mask: 0x3ff)         */
-#define CHARGER_CHARGER_TBAT_MON_TIMER_REG_TBAT_MON_INTERVAL_Pos (0UL) /*!< TBAT_MON_INTERVAL (Bit 0)                          */
-#define CHARGER_CHARGER_TBAT_MON_TIMER_REG_TBAT_MON_INTERVAL_Msk (0x3ffUL) /*!< TBAT_MON_INTERVAL (Bitfield-Mask: 0x3ff)       */
-/* ==============================================  CHARGER_TDIE_COMP_TIMER_REG  ============================================== */
-#define CHARGER_CHARGER_TDIE_COMP_TIMER_REG_TDIE_COMP_TIMER_Pos (16UL) /*!< TDIE_COMP_TIMER (Bit 16)                           */
-#define CHARGER_CHARGER_TDIE_COMP_TIMER_REG_TDIE_COMP_TIMER_Msk (0x3ff0000UL) /*!< TDIE_COMP_TIMER (Bitfield-Mask: 0x3ff)      */
-#define CHARGER_CHARGER_TDIE_COMP_TIMER_REG_TDIE_COMP_SETTLING_Pos (0UL) /*!< TDIE_COMP_SETTLING (Bit 0)                       */
-#define CHARGER_CHARGER_TDIE_COMP_TIMER_REG_TDIE_COMP_SETTLING_Msk (0x3ffUL) /*!< TDIE_COMP_SETTLING (Bitfield-Mask: 0x3ff)    */
-/* ===============================================  CHARGER_TEMPSET_PARAM_REG  =============================================== */
-#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TDIE_MAX_Pos (24UL)       /*!< TDIE_MAX (Bit 24)                                     */
-#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TDIE_MAX_Msk (0x7000000UL) /*!< TDIE_MAX (Bitfield-Mask: 0x07)                       */
-#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TBAT_HOT_Pos (18UL)       /*!< TBAT_HOT (Bit 18)                                     */
-#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TBAT_HOT_Msk (0xfc0000UL) /*!< TBAT_HOT (Bitfield-Mask: 0x3f)                        */
-#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TBAT_WARM_Pos (12UL)      /*!< TBAT_WARM (Bit 12)                                    */
-#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TBAT_WARM_Msk (0x3f000UL) /*!< TBAT_WARM (Bitfield-Mask: 0x3f)                       */
-#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TBAT_COOL_Pos (6UL)       /*!< TBAT_COOL (Bit 6)                                     */
-#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TBAT_COOL_Msk (0xfc0UL)   /*!< TBAT_COOL (Bitfield-Mask: 0x3f)                       */
-#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TBAT_COLD_Pos (0UL)       /*!< TBAT_COLD (Bit 0)                                     */
-#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TBAT_COLD_Msk (0x3fUL)    /*!< TBAT_COLD (Bitfield-Mask: 0x3f)                       */
-/* =================================================  CHARGER_TEST_CTRL_REG  ================================================= */
-/* ==============================================  CHARGER_THOT_COMP_TIMER_REG  ============================================== */
-#define CHARGER_CHARGER_THOT_COMP_TIMER_REG_THOT_COMP_TIMER_Pos (16UL) /*!< THOT_COMP_TIMER (Bit 16)                           */
-#define CHARGER_CHARGER_THOT_COMP_TIMER_REG_THOT_COMP_TIMER_Msk (0x3ff0000UL) /*!< THOT_COMP_TIMER (Bitfield-Mask: 0x3ff)      */
-#define CHARGER_CHARGER_THOT_COMP_TIMER_REG_THOT_COMP_SETTLING_Pos (0UL) /*!< THOT_COMP_SETTLING (Bit 0)                       */
-#define CHARGER_CHARGER_THOT_COMP_TIMER_REG_THOT_COMP_SETTLING_Msk (0x3ffUL) /*!< THOT_COMP_SETTLING (Bitfield-Mask: 0x3ff)    */
-/* ============================================  CHARGER_TOTAL_CHARGE_TIMER_REG  ============================================= */
-#define CHARGER_CHARGER_TOTAL_CHARGE_TIMER_REG_TOTAL_CHARGE_TIMER_Pos (16UL) /*!< TOTAL_CHARGE_TIMER (Bit 16)                  */
-#define CHARGER_CHARGER_TOTAL_CHARGE_TIMER_REG_TOTAL_CHARGE_TIMER_Msk (0xffff0000UL) /*!< TOTAL_CHARGE_TIMER (Bitfield-Mask: 0xffff) */
-#define CHARGER_CHARGER_TOTAL_CHARGE_TIMER_REG_MAX_TOTAL_CHARGE_TIME_Pos (0UL) /*!< MAX_TOTAL_CHARGE_TIME (Bit 0)              */
-#define CHARGER_CHARGER_TOTAL_CHARGE_TIMER_REG_MAX_TOTAL_CHARGE_TIME_Msk (0xffffUL) /*!< MAX_TOTAL_CHARGE_TIME (Bitfield-Mask: 0xffff) */
-/* ==============================================  CHARGER_VBAT_COMP_TIMER_REG  ============================================== */
-#define CHARGER_CHARGER_VBAT_COMP_TIMER_REG_VBAT_COMP_TIMER_Pos (16UL) /*!< VBAT_COMP_TIMER (Bit 16)                           */
-#define CHARGER_CHARGER_VBAT_COMP_TIMER_REG_VBAT_COMP_TIMER_Msk (0x3ff0000UL) /*!< VBAT_COMP_TIMER (Bitfield-Mask: 0x3ff)      */
-#define CHARGER_CHARGER_VBAT_COMP_TIMER_REG_VBAT_COMP_SETTLING_Pos (0UL) /*!< VBAT_COMP_SETTLING (Bit 0)                       */
-#define CHARGER_CHARGER_VBAT_COMP_TIMER_REG_VBAT_COMP_SETTLING_Msk (0x3ffUL) /*!< VBAT_COMP_SETTLING (Bitfield-Mask: 0x3ff)    */
-/* ===============================================  CHARGER_VOLTAGE_PARAM_REG  =============================================== */
-#define CHARGER_CHARGER_VOLTAGE_PARAM_REG_V_OVP_Pos (18UL)          /*!< V_OVP (Bit 18)                                        */
-#define CHARGER_CHARGER_VOLTAGE_PARAM_REG_V_OVP_Msk (0xfc0000UL)    /*!< V_OVP (Bitfield-Mask: 0x3f)                           */
-#define CHARGER_CHARGER_VOLTAGE_PARAM_REG_V_REPLENISH_Pos (12UL)    /*!< V_REPLENISH (Bit 12)                                  */
-#define CHARGER_CHARGER_VOLTAGE_PARAM_REG_V_REPLENISH_Msk (0x3f000UL) /*!< V_REPLENISH (Bitfield-Mask: 0x3f)                   */
-#define CHARGER_CHARGER_VOLTAGE_PARAM_REG_V_PRECHARGE_Pos (6UL)     /*!< V_PRECHARGE (Bit 6)                                   */
-#define CHARGER_CHARGER_VOLTAGE_PARAM_REG_V_PRECHARGE_Msk (0xfc0UL) /*!< V_PRECHARGE (Bitfield-Mask: 0x3f)                     */
-#define CHARGER_CHARGER_VOLTAGE_PARAM_REG_V_CHARGE_Pos (0UL)        /*!< V_CHARGE (Bit 0)                                      */
-#define CHARGER_CHARGER_VOLTAGE_PARAM_REG_V_CHARGE_Msk (0x3fUL)     /*!< V_CHARGE (Bitfield-Mask: 0x3f)                        */
-/* ==============================================  CHARGER_VOVP_COMP_TIMER_REG  ============================================== */
-#define CHARGER_CHARGER_VOVP_COMP_TIMER_REG_OVP_INTERVAL_CHECK_TIMER_Pos (26UL) /*!< OVP_INTERVAL_CHECK_TIMER (Bit 26)         */
-#define CHARGER_CHARGER_VOVP_COMP_TIMER_REG_OVP_INTERVAL_CHECK_TIMER_Msk (0xfc000000UL) /*!< OVP_INTERVAL_CHECK_TIMER (Bitfield-Mask: 0x3f) */
-#define CHARGER_CHARGER_VOVP_COMP_TIMER_REG_VBAT_OVP_COMP_TIMER_Pos (16UL) /*!< VBAT_OVP_COMP_TIMER (Bit 16)                   */
-#define CHARGER_CHARGER_VOVP_COMP_TIMER_REG_VBAT_OVP_COMP_TIMER_Msk (0x3ff0000UL) /*!< VBAT_OVP_COMP_TIMER (Bitfield-Mask: 0x3ff) */
-#define CHARGER_CHARGER_VOVP_COMP_TIMER_REG_OVP_INTERVAL_CHECK_THRES_Pos (10UL) /*!< OVP_INTERVAL_CHECK_THRES (Bit 10)         */
-#define CHARGER_CHARGER_VOVP_COMP_TIMER_REG_OVP_INTERVAL_CHECK_THRES_Msk (0xfc00UL) /*!< OVP_INTERVAL_CHECK_THRES (Bitfield-Mask: 0x3f) */
-#define CHARGER_CHARGER_VOVP_COMP_TIMER_REG_VBAT_OVP_COMP_SETTLING_Pos (0UL) /*!< VBAT_OVP_COMP_SETTLING (Bit 0)               */
-#define CHARGER_CHARGER_VOVP_COMP_TIMER_REG_VBAT_OVP_COMP_SETTLING_Msk (0x3ffUL) /*!< VBAT_OVP_COMP_SETTLING (Bitfield-Mask: 0x3ff) */
-
-
-/* =========================================================================================================================== */
-/* ================                                       CHIP_VERSION                                        ================ */
-/* =========================================================================================================================== */
-
-/* =====================================================  CHIP_ID1_REG  ====================================================== */
-#define CHIP_VERSION_CHIP_ID1_REG_CHIP_ID1_Pos (0UL)                /*!< CHIP_ID1 (Bit 0)                                      */
-#define CHIP_VERSION_CHIP_ID1_REG_CHIP_ID1_Msk (0xffUL)             /*!< CHIP_ID1 (Bitfield-Mask: 0xff)                        */
-/* =====================================================  CHIP_ID2_REG  ====================================================== */
-#define CHIP_VERSION_CHIP_ID2_REG_CHIP_ID2_Pos (0UL)                /*!< CHIP_ID2 (Bit 0)                                      */
-#define CHIP_VERSION_CHIP_ID2_REG_CHIP_ID2_Msk (0xffUL)             /*!< CHIP_ID2 (Bitfield-Mask: 0xff)                        */
-/* =====================================================  CHIP_ID3_REG  ====================================================== */
-#define CHIP_VERSION_CHIP_ID3_REG_CHIP_ID3_Pos (0UL)                /*!< CHIP_ID3 (Bit 0)                                      */
-#define CHIP_VERSION_CHIP_ID3_REG_CHIP_ID3_Msk (0xffUL)             /*!< CHIP_ID3 (Bitfield-Mask: 0xff)                        */
-/* =====================================================  CHIP_ID4_REG  ====================================================== */
-#define CHIP_VERSION_CHIP_ID4_REG_CHIP_ID4_Pos (0UL)                /*!< CHIP_ID4 (Bit 0)                                      */
-#define CHIP_VERSION_CHIP_ID4_REG_CHIP_ID4_Msk (0xffUL)             /*!< CHIP_ID4 (Bitfield-Mask: 0xff)                        */
-/* ===================================================  CHIP_REVISION_REG  =================================================== */
-#define CHIP_VERSION_CHIP_REVISION_REG_CHIP_REVISION_Pos (0UL)      /*!< CHIP_REVISION (Bit 0)                                 */
-#define CHIP_VERSION_CHIP_REVISION_REG_CHIP_REVISION_Msk (0xffUL)   /*!< CHIP_REVISION (Bitfield-Mask: 0xff)                   */
-/* =====================================================  CHIP_SWC_REG  ====================================================== */
-#define CHIP_VERSION_CHIP_SWC_REG_CHIP_SWC_Pos (0UL)                /*!< CHIP_SWC (Bit 0)                                      */
-#define CHIP_VERSION_CHIP_SWC_REG_CHIP_SWC_Msk (0xfUL)              /*!< CHIP_SWC (Bitfield-Mask: 0x0f)                        */
-/* ====================================================  CHIP_TEST1_REG  ===================================================== */
-#define CHIP_VERSION_CHIP_TEST1_REG_CHIP_LAYOUT_REVISION_Pos (0UL)  /*!< CHIP_LAYOUT_REVISION (Bit 0)                          */
-#define CHIP_VERSION_CHIP_TEST1_REG_CHIP_LAYOUT_REVISION_Msk (0xffUL) /*!< CHIP_LAYOUT_REVISION (Bitfield-Mask: 0xff)          */
-/* ====================================================  CHIP_TEST2_REG  ===================================================== */
-#define CHIP_VERSION_CHIP_TEST2_REG_CHIP_METAL_OPTION_Pos (0UL)     /*!< CHIP_METAL_OPTION (Bit 0)                             */
-#define CHIP_VERSION_CHIP_TEST2_REG_CHIP_METAL_OPTION_Msk (0xfUL)   /*!< CHIP_METAL_OPTION (Bitfield-Mask: 0x0f)               */
-
-
-/* =========================================================================================================================== */
-/* ================                                          CRG_COM                                          ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================  CLK_COM_REG  ====================================================== */
-#define CRG_COM_CLK_COM_REG_LCD_EXT_CLK_SEL_Pos (16UL)              /*!< LCD_EXT_CLK_SEL (Bit 16)                              */
-#define CRG_COM_CLK_COM_REG_LCD_EXT_CLK_SEL_Msk (0x30000UL)         /*!< LCD_EXT_CLK_SEL (Bitfield-Mask: 0x03)                 */
-#define CRG_COM_CLK_COM_REG_SNC_DIV_Pos   (14UL)                    /*!< SNC_DIV (Bit 14)                                      */
-#define CRG_COM_CLK_COM_REG_SNC_DIV_Msk   (0xc000UL)                /*!< SNC_DIV (Bitfield-Mask: 0x03)                         */
-#define CRG_COM_CLK_COM_REG_I2C2_CLK_SEL_Pos (12UL)                 /*!< I2C2_CLK_SEL (Bit 12)                                 */
-#define CRG_COM_CLK_COM_REG_I2C2_CLK_SEL_Msk (0x1000UL)             /*!< I2C2_CLK_SEL (Bitfield-Mask: 0x01)                    */
-#define CRG_COM_CLK_COM_REG_I2C2_ENABLE_Pos (11UL)                  /*!< I2C2_ENABLE (Bit 11)                                  */
-#define CRG_COM_CLK_COM_REG_I2C2_ENABLE_Msk (0x800UL)               /*!< I2C2_ENABLE (Bitfield-Mask: 0x01)                     */
-#define CRG_COM_CLK_COM_REG_I2C_CLK_SEL_Pos (10UL)                  /*!< I2C_CLK_SEL (Bit 10)                                  */
-#define CRG_COM_CLK_COM_REG_I2C_CLK_SEL_Msk (0x400UL)               /*!< I2C_CLK_SEL (Bitfield-Mask: 0x01)                     */
-#define CRG_COM_CLK_COM_REG_I2C_ENABLE_Pos (9UL)                    /*!< I2C_ENABLE (Bit 9)                                    */
-#define CRG_COM_CLK_COM_REG_I2C_ENABLE_Msk (0x200UL)                /*!< I2C_ENABLE (Bitfield-Mask: 0x01)                      */
-#define CRG_COM_CLK_COM_REG_SPI2_CLK_SEL_Pos (8UL)                  /*!< SPI2_CLK_SEL (Bit 8)                                  */
-#define CRG_COM_CLK_COM_REG_SPI2_CLK_SEL_Msk (0x100UL)              /*!< SPI2_CLK_SEL (Bitfield-Mask: 0x01)                    */
-#define CRG_COM_CLK_COM_REG_SPI2_ENABLE_Pos (7UL)                   /*!< SPI2_ENABLE (Bit 7)                                   */
-#define CRG_COM_CLK_COM_REG_SPI2_ENABLE_Msk (0x80UL)                /*!< SPI2_ENABLE (Bitfield-Mask: 0x01)                     */
-#define CRG_COM_CLK_COM_REG_SPI_CLK_SEL_Pos (6UL)                   /*!< SPI_CLK_SEL (Bit 6)                                   */
-#define CRG_COM_CLK_COM_REG_SPI_CLK_SEL_Msk (0x40UL)                /*!< SPI_CLK_SEL (Bitfield-Mask: 0x01)                     */
-#define CRG_COM_CLK_COM_REG_SPI_ENABLE_Pos (5UL)                    /*!< SPI_ENABLE (Bit 5)                                    */
-#define CRG_COM_CLK_COM_REG_SPI_ENABLE_Msk (0x20UL)                 /*!< SPI_ENABLE (Bitfield-Mask: 0x01)                      */
-#define CRG_COM_CLK_COM_REG_UART3_CLK_SEL_Pos (4UL)                 /*!< UART3_CLK_SEL (Bit 4)                                 */
-#define CRG_COM_CLK_COM_REG_UART3_CLK_SEL_Msk (0x10UL)              /*!< UART3_CLK_SEL (Bitfield-Mask: 0x01)                   */
-#define CRG_COM_CLK_COM_REG_UART3_ENABLE_Pos (3UL)                  /*!< UART3_ENABLE (Bit 3)                                  */
-#define CRG_COM_CLK_COM_REG_UART3_ENABLE_Msk (0x8UL)                /*!< UART3_ENABLE (Bitfield-Mask: 0x01)                    */
-#define CRG_COM_CLK_COM_REG_UART2_CLK_SEL_Pos (2UL)                 /*!< UART2_CLK_SEL (Bit 2)                                 */
-#define CRG_COM_CLK_COM_REG_UART2_CLK_SEL_Msk (0x4UL)               /*!< UART2_CLK_SEL (Bitfield-Mask: 0x01)                   */
-#define CRG_COM_CLK_COM_REG_UART2_ENABLE_Pos (1UL)                  /*!< UART2_ENABLE (Bit 1)                                  */
-#define CRG_COM_CLK_COM_REG_UART2_ENABLE_Msk (0x2UL)                /*!< UART2_ENABLE (Bitfield-Mask: 0x01)                    */
-#define CRG_COM_CLK_COM_REG_UART_ENABLE_Pos (0UL)                   /*!< UART_ENABLE (Bit 0)                                   */
-#define CRG_COM_CLK_COM_REG_UART_ENABLE_Msk (0x1UL)                 /*!< UART_ENABLE (Bitfield-Mask: 0x01)                     */
-/* ===================================================  RESET_CLK_COM_REG  =================================================== */
-#define CRG_COM_RESET_CLK_COM_REG_LCD_EXT_CLK_SEL_Pos (16UL)        /*!< LCD_EXT_CLK_SEL (Bit 16)                              */
-#define CRG_COM_RESET_CLK_COM_REG_LCD_EXT_CLK_SEL_Msk (0x30000UL)   /*!< LCD_EXT_CLK_SEL (Bitfield-Mask: 0x03)                 */
-#define CRG_COM_RESET_CLK_COM_REG_SNC_DIV_Pos (14UL)                /*!< SNC_DIV (Bit 14)                                      */
-#define CRG_COM_RESET_CLK_COM_REG_SNC_DIV_Msk (0xc000UL)            /*!< SNC_DIV (Bitfield-Mask: 0x03)                         */
-#define CRG_COM_RESET_CLK_COM_REG_I2C2_CLK_SEL_Pos (12UL)           /*!< I2C2_CLK_SEL (Bit 12)                                 */
-#define CRG_COM_RESET_CLK_COM_REG_I2C2_CLK_SEL_Msk (0x1000UL)       /*!< I2C2_CLK_SEL (Bitfield-Mask: 0x01)                    */
-#define CRG_COM_RESET_CLK_COM_REG_I2C2_ENABLE_Pos (11UL)            /*!< I2C2_ENABLE (Bit 11)                                  */
-#define CRG_COM_RESET_CLK_COM_REG_I2C2_ENABLE_Msk (0x800UL)         /*!< I2C2_ENABLE (Bitfield-Mask: 0x01)                     */
-#define CRG_COM_RESET_CLK_COM_REG_I2C_CLK_SEL_Pos (10UL)            /*!< I2C_CLK_SEL (Bit 10)                                  */
-#define CRG_COM_RESET_CLK_COM_REG_I2C_CLK_SEL_Msk (0x400UL)         /*!< I2C_CLK_SEL (Bitfield-Mask: 0x01)                     */
-#define CRG_COM_RESET_CLK_COM_REG_I2C_ENABLE_Pos (9UL)              /*!< I2C_ENABLE (Bit 9)                                    */
-#define CRG_COM_RESET_CLK_COM_REG_I2C_ENABLE_Msk (0x200UL)          /*!< I2C_ENABLE (Bitfield-Mask: 0x01)                      */
-#define CRG_COM_RESET_CLK_COM_REG_SPI2_CLK_SEL_Pos (8UL)            /*!< SPI2_CLK_SEL (Bit 8)                                  */
-#define CRG_COM_RESET_CLK_COM_REG_SPI2_CLK_SEL_Msk (0x100UL)        /*!< SPI2_CLK_SEL (Bitfield-Mask: 0x01)                    */
-#define CRG_COM_RESET_CLK_COM_REG_SPI2_ENABLE_Pos (7UL)             /*!< SPI2_ENABLE (Bit 7)                                   */
-#define CRG_COM_RESET_CLK_COM_REG_SPI2_ENABLE_Msk (0x80UL)          /*!< SPI2_ENABLE (Bitfield-Mask: 0x01)                     */
-#define CRG_COM_RESET_CLK_COM_REG_SPI_CLK_SEL_Pos (6UL)             /*!< SPI_CLK_SEL (Bit 6)                                   */
-#define CRG_COM_RESET_CLK_COM_REG_SPI_CLK_SEL_Msk (0x40UL)          /*!< SPI_CLK_SEL (Bitfield-Mask: 0x01)                     */
-#define CRG_COM_RESET_CLK_COM_REG_SPI_ENABLE_Pos (5UL)              /*!< SPI_ENABLE (Bit 5)                                    */
-#define CRG_COM_RESET_CLK_COM_REG_SPI_ENABLE_Msk (0x20UL)           /*!< SPI_ENABLE (Bitfield-Mask: 0x01)                      */
-#define CRG_COM_RESET_CLK_COM_REG_UART3_CLK_SEL_Pos (4UL)           /*!< UART3_CLK_SEL (Bit 4)                                 */
-#define CRG_COM_RESET_CLK_COM_REG_UART3_CLK_SEL_Msk (0x10UL)        /*!< UART3_CLK_SEL (Bitfield-Mask: 0x01)                   */
-#define CRG_COM_RESET_CLK_COM_REG_UART3_ENABLE_Pos (3UL)            /*!< UART3_ENABLE (Bit 3)                                  */
-#define CRG_COM_RESET_CLK_COM_REG_UART3_ENABLE_Msk (0x8UL)          /*!< UART3_ENABLE (Bitfield-Mask: 0x01)                    */
-#define CRG_COM_RESET_CLK_COM_REG_UART2_CLK_SEL_Pos (2UL)           /*!< UART2_CLK_SEL (Bit 2)                                 */
-#define CRG_COM_RESET_CLK_COM_REG_UART2_CLK_SEL_Msk (0x4UL)         /*!< UART2_CLK_SEL (Bitfield-Mask: 0x01)                   */
-#define CRG_COM_RESET_CLK_COM_REG_UART2_ENABLE_Pos (1UL)            /*!< UART2_ENABLE (Bit 1)                                  */
-#define CRG_COM_RESET_CLK_COM_REG_UART2_ENABLE_Msk (0x2UL)          /*!< UART2_ENABLE (Bitfield-Mask: 0x01)                    */
-#define CRG_COM_RESET_CLK_COM_REG_UART_ENABLE_Pos (0UL)             /*!< UART_ENABLE (Bit 0)                                   */
-#define CRG_COM_RESET_CLK_COM_REG_UART_ENABLE_Msk (0x1UL)           /*!< UART_ENABLE (Bitfield-Mask: 0x01)                     */
-/* ====================================================  SET_CLK_COM_REG  ==================================================== */
-#define CRG_COM_SET_CLK_COM_REG_LCD_EXT_CLK_SEL_Pos (16UL)          /*!< LCD_EXT_CLK_SEL (Bit 16)                              */
-#define CRG_COM_SET_CLK_COM_REG_LCD_EXT_CLK_SEL_Msk (0x30000UL)     /*!< LCD_EXT_CLK_SEL (Bitfield-Mask: 0x03)                 */
-#define CRG_COM_SET_CLK_COM_REG_SNC_DIV_Pos (14UL)                  /*!< SNC_DIV (Bit 14)                                      */
-#define CRG_COM_SET_CLK_COM_REG_SNC_DIV_Msk (0xc000UL)              /*!< SNC_DIV (Bitfield-Mask: 0x03)                         */
-#define CRG_COM_SET_CLK_COM_REG_I2C2_CLK_SEL_Pos (12UL)             /*!< I2C2_CLK_SEL (Bit 12)                                 */
-#define CRG_COM_SET_CLK_COM_REG_I2C2_CLK_SEL_Msk (0x1000UL)         /*!< I2C2_CLK_SEL (Bitfield-Mask: 0x01)                    */
-#define CRG_COM_SET_CLK_COM_REG_I2C2_ENABLE_Pos (11UL)              /*!< I2C2_ENABLE (Bit 11)                                  */
-#define CRG_COM_SET_CLK_COM_REG_I2C2_ENABLE_Msk (0x800UL)           /*!< I2C2_ENABLE (Bitfield-Mask: 0x01)                     */
-#define CRG_COM_SET_CLK_COM_REG_I2C_CLK_SEL_Pos (10UL)              /*!< I2C_CLK_SEL (Bit 10)                                  */
-#define CRG_COM_SET_CLK_COM_REG_I2C_CLK_SEL_Msk (0x400UL)           /*!< I2C_CLK_SEL (Bitfield-Mask: 0x01)                     */
-#define CRG_COM_SET_CLK_COM_REG_I2C_ENABLE_Pos (9UL)                /*!< I2C_ENABLE (Bit 9)                                    */
-#define CRG_COM_SET_CLK_COM_REG_I2C_ENABLE_Msk (0x200UL)            /*!< I2C_ENABLE (Bitfield-Mask: 0x01)                      */
-#define CRG_COM_SET_CLK_COM_REG_SPI2_CLK_SEL_Pos (8UL)              /*!< SPI2_CLK_SEL (Bit 8)                                  */
-#define CRG_COM_SET_CLK_COM_REG_SPI2_CLK_SEL_Msk (0x100UL)          /*!< SPI2_CLK_SEL (Bitfield-Mask: 0x01)                    */
-#define CRG_COM_SET_CLK_COM_REG_SPI2_ENABLE_Pos (7UL)               /*!< SPI2_ENABLE (Bit 7)                                   */
-#define CRG_COM_SET_CLK_COM_REG_SPI2_ENABLE_Msk (0x80UL)            /*!< SPI2_ENABLE (Bitfield-Mask: 0x01)                     */
-#define CRG_COM_SET_CLK_COM_REG_SPI_CLK_SEL_Pos (6UL)               /*!< SPI_CLK_SEL (Bit 6)                                   */
-#define CRG_COM_SET_CLK_COM_REG_SPI_CLK_SEL_Msk (0x40UL)            /*!< SPI_CLK_SEL (Bitfield-Mask: 0x01)                     */
-#define CRG_COM_SET_CLK_COM_REG_SPI_ENABLE_Pos (5UL)                /*!< SPI_ENABLE (Bit 5)                                    */
-#define CRG_COM_SET_CLK_COM_REG_SPI_ENABLE_Msk (0x20UL)             /*!< SPI_ENABLE (Bitfield-Mask: 0x01)                      */
-#define CRG_COM_SET_CLK_COM_REG_UART3_CLK_SEL_Pos (4UL)             /*!< UART3_CLK_SEL (Bit 4)                                 */
-#define CRG_COM_SET_CLK_COM_REG_UART3_CLK_SEL_Msk (0x10UL)          /*!< UART3_CLK_SEL (Bitfield-Mask: 0x01)                   */
-#define CRG_COM_SET_CLK_COM_REG_UART3_ENABLE_Pos (3UL)              /*!< UART3_ENABLE (Bit 3)                                  */
-#define CRG_COM_SET_CLK_COM_REG_UART3_ENABLE_Msk (0x8UL)            /*!< UART3_ENABLE (Bitfield-Mask: 0x01)                    */
-#define CRG_COM_SET_CLK_COM_REG_UART2_CLK_SEL_Pos (2UL)             /*!< UART2_CLK_SEL (Bit 2)                                 */
-#define CRG_COM_SET_CLK_COM_REG_UART2_CLK_SEL_Msk (0x4UL)           /*!< UART2_CLK_SEL (Bitfield-Mask: 0x01)                   */
-#define CRG_COM_SET_CLK_COM_REG_UART2_ENABLE_Pos (1UL)              /*!< UART2_ENABLE (Bit 1)                                  */
-#define CRG_COM_SET_CLK_COM_REG_UART2_ENABLE_Msk (0x2UL)            /*!< UART2_ENABLE (Bitfield-Mask: 0x01)                    */
-#define CRG_COM_SET_CLK_COM_REG_UART_ENABLE_Pos (0UL)               /*!< UART_ENABLE (Bit 0)                                   */
-#define CRG_COM_SET_CLK_COM_REG_UART_ENABLE_Msk (0x1UL)             /*!< UART_ENABLE (Bitfield-Mask: 0x01)                     */
-
-
-/* =========================================================================================================================== */
-/* ================                                          CRG_PER                                          ================ */
-/* =========================================================================================================================== */
-
-/* ======================================================  CLK_PER_REG  ====================================================== */
-#define CRG_PER_CLK_PER_REG_MC_TRIG_DIV_Pos (8UL)                   /*!< MC_TRIG_DIV (Bit 8)                                   */
-#define CRG_PER_CLK_PER_REG_MC_TRIG_DIV_Msk (0x1f00UL)              /*!< MC_TRIG_DIV (Bitfield-Mask: 0x1f)                     */
-#define CRG_PER_CLK_PER_REG_MC_CLK_DIV_Pos (3UL)                    /*!< MC_CLK_DIV (Bit 3)                                    */
-#define CRG_PER_CLK_PER_REG_MC_CLK_DIV_Msk (0xf8UL)                 /*!< MC_CLK_DIV (Bitfield-Mask: 0x1f)                      */
-#define CRG_PER_CLK_PER_REG_MC_CLK_EN_Pos (2UL)                     /*!< MC_CLK_EN (Bit 2)                                     */
-#define CRG_PER_CLK_PER_REG_MC_CLK_EN_Msk (0x4UL)                   /*!< MC_CLK_EN (Bitfield-Mask: 0x01)                       */
-#define CRG_PER_CLK_PER_REG_LRA_CLK_EN_Pos (1UL)                    /*!< LRA_CLK_EN (Bit 1)                                    */
-#define CRG_PER_CLK_PER_REG_LRA_CLK_EN_Msk (0x2UL)                  /*!< LRA_CLK_EN (Bitfield-Mask: 0x01)                      */
-#define CRG_PER_CLK_PER_REG_GPADC_CLK_SEL_Pos (0UL)                 /*!< GPADC_CLK_SEL (Bit 0)                                 */
-#define CRG_PER_CLK_PER_REG_GPADC_CLK_SEL_Msk (0x1UL)               /*!< GPADC_CLK_SEL (Bitfield-Mask: 0x01)                   */
-/* ======================================================  PCM_DIV_REG  ====================================================== */
-#define CRG_PER_PCM_DIV_REG_PCM_SRC_SEL_Pos (13UL)                  /*!< PCM_SRC_SEL (Bit 13)                                  */
-#define CRG_PER_PCM_DIV_REG_PCM_SRC_SEL_Msk (0x2000UL)              /*!< PCM_SRC_SEL (Bitfield-Mask: 0x01)                     */
-#define CRG_PER_PCM_DIV_REG_CLK_PCM_EN_Pos (12UL)                   /*!< CLK_PCM_EN (Bit 12)                                   */
-#define CRG_PER_PCM_DIV_REG_CLK_PCM_EN_Msk (0x1000UL)               /*!< CLK_PCM_EN (Bitfield-Mask: 0x01)                      */
-#define CRG_PER_PCM_DIV_REG_PCM_DIV_Pos   (0UL)                     /*!< PCM_DIV (Bit 0)                                       */
-#define CRG_PER_PCM_DIV_REG_PCM_DIV_Msk   (0xfffUL)                 /*!< PCM_DIV (Bitfield-Mask: 0xfff)                        */
-/* =====================================================  PCM_FDIV_REG  ====================================================== */
-#define CRG_PER_PCM_FDIV_REG_PCM_FDIV_Pos (0UL)                     /*!< PCM_FDIV (Bit 0)                                      */
-#define CRG_PER_PCM_FDIV_REG_PCM_FDIV_Msk (0xffffUL)                /*!< PCM_FDIV (Bitfield-Mask: 0xffff)                      */
-/* ======================================================  PDM_DIV_REG  ====================================================== */
-#define CRG_PER_PDM_DIV_REG_PDM_MASTER_MODE_Pos (9UL)               /*!< PDM_MASTER_MODE (Bit 9)                               */
-#define CRG_PER_PDM_DIV_REG_PDM_MASTER_MODE_Msk (0x200UL)           /*!< PDM_MASTER_MODE (Bitfield-Mask: 0x01)                 */
-#define CRG_PER_PDM_DIV_REG_CLK_PDM_EN_Pos (8UL)                    /*!< CLK_PDM_EN (Bit 8)                                    */
-#define CRG_PER_PDM_DIV_REG_CLK_PDM_EN_Msk (0x100UL)                /*!< CLK_PDM_EN (Bitfield-Mask: 0x01)                      */
-#define CRG_PER_PDM_DIV_REG_PDM_DIV_Pos   (0UL)                     /*!< PDM_DIV (Bit 0)                                       */
-#define CRG_PER_PDM_DIV_REG_PDM_DIV_Msk   (0xffUL)                  /*!< PDM_DIV (Bitfield-Mask: 0xff)                         */
-/* ===================================================  RESET_CLK_PER_REG  =================================================== */
-#define CRG_PER_RESET_CLK_PER_REG_MC_TRIG_DIV_Pos (8UL)             /*!< MC_TRIG_DIV (Bit 8)                                   */
-#define CRG_PER_RESET_CLK_PER_REG_MC_TRIG_DIV_Msk (0x1f00UL)        /*!< MC_TRIG_DIV (Bitfield-Mask: 0x1f)                     */
-#define CRG_PER_RESET_CLK_PER_REG_MC_CLK_DIV_Pos (3UL)              /*!< MC_CLK_DIV (Bit 3)                                    */
-#define CRG_PER_RESET_CLK_PER_REG_MC_CLK_DIV_Msk (0xf8UL)           /*!< MC_CLK_DIV (Bitfield-Mask: 0x1f)                      */
-#define CRG_PER_RESET_CLK_PER_REG_MC_CLK_EN_Pos (2UL)               /*!< MC_CLK_EN (Bit 2)                                     */
-#define CRG_PER_RESET_CLK_PER_REG_MC_CLK_EN_Msk (0x4UL)             /*!< MC_CLK_EN (Bitfield-Mask: 0x01)                       */
-#define CRG_PER_RESET_CLK_PER_REG_LRA_CLK_EN_Pos (1UL)              /*!< LRA_CLK_EN (Bit 1)                                    */
-#define CRG_PER_RESET_CLK_PER_REG_LRA_CLK_EN_Msk (0x2UL)            /*!< LRA_CLK_EN (Bitfield-Mask: 0x01)                      */
-#define CRG_PER_RESET_CLK_PER_REG_GPADC_CLK_SEL_Pos (0UL)           /*!< GPADC_CLK_SEL (Bit 0)                                 */
-#define CRG_PER_RESET_CLK_PER_REG_GPADC_CLK_SEL_Msk (0x1UL)         /*!< GPADC_CLK_SEL (Bitfield-Mask: 0x01)                   */
-/* ====================================================  SET_CLK_PER_REG  ==================================================== */
-#define CRG_PER_SET_CLK_PER_REG_MC_TRIG_DIV_Pos (8UL)               /*!< MC_TRIG_DIV (Bit 8)                                   */
-#define CRG_PER_SET_CLK_PER_REG_MC_TRIG_DIV_Msk (0x1f00UL)          /*!< MC_TRIG_DIV (Bitfield-Mask: 0x1f)                     */
-#define CRG_PER_SET_CLK_PER_REG_MC_CLK_DIV_Pos (3UL)                /*!< MC_CLK_DIV (Bit 3)                                    */
-#define CRG_PER_SET_CLK_PER_REG_MC_CLK_DIV_Msk (0xf8UL)             /*!< MC_CLK_DIV (Bitfield-Mask: 0x1f)                      */
-#define CRG_PER_SET_CLK_PER_REG_MC_CLK_EN_Pos (2UL)                 /*!< MC_CLK_EN (Bit 2)                                     */
-#define CRG_PER_SET_CLK_PER_REG_MC_CLK_EN_Msk (0x4UL)               /*!< MC_CLK_EN (Bitfield-Mask: 0x01)                       */
-#define CRG_PER_SET_CLK_PER_REG_LRA_CLK_EN_Pos (1UL)                /*!< LRA_CLK_EN (Bit 1)                                    */
-#define CRG_PER_SET_CLK_PER_REG_LRA_CLK_EN_Msk (0x2UL)              /*!< LRA_CLK_EN (Bitfield-Mask: 0x01)                      */
-#define CRG_PER_SET_CLK_PER_REG_GPADC_CLK_SEL_Pos (0UL)             /*!< GPADC_CLK_SEL (Bit 0)                                 */
-#define CRG_PER_SET_CLK_PER_REG_GPADC_CLK_SEL_Msk (0x1UL)           /*!< GPADC_CLK_SEL (Bitfield-Mask: 0x01)                   */
-/* ======================================================  SRC_DIV_REG  ====================================================== */
-#define CRG_PER_SRC_DIV_REG_CLK_SRC_EN_Pos (8UL)                    /*!< CLK_SRC_EN (Bit 8)                                    */
-#define CRG_PER_SRC_DIV_REG_CLK_SRC_EN_Msk (0x100UL)                /*!< CLK_SRC_EN (Bitfield-Mask: 0x01)                      */
-#define CRG_PER_SRC_DIV_REG_SRC_DIV_Pos   (0UL)                     /*!< SRC_DIV (Bit 0)                                       */
-#define CRG_PER_SRC_DIV_REG_SRC_DIV_Msk   (0xffUL)                  /*!< SRC_DIV (Bitfield-Mask: 0xff)                         */
-
-
-/* =========================================================================================================================== */
-/* ================                                          CRG_SYS                                          ================ */
-/* =========================================================================================================================== */
-
-/* =====================================================  BATCHECK_REG  ====================================================== */
-#define CRG_SYS_BATCHECK_REG_BATCHECK_LOAD_ENABLE_Pos (7UL)         /*!< BATCHECK_LOAD_ENABLE (Bit 7)                          */
-#define CRG_SYS_BATCHECK_REG_BATCHECK_LOAD_ENABLE_Msk (0x80UL)      /*!< BATCHECK_LOAD_ENABLE (Bitfield-Mask: 0x01)            */
-#define CRG_SYS_BATCHECK_REG_BATCHECK_ILOAD_Pos (4UL)               /*!< BATCHECK_ILOAD (Bit 4)                                */
-#define CRG_SYS_BATCHECK_REG_BATCHECK_ILOAD_Msk (0x70UL)            /*!< BATCHECK_ILOAD (Bitfield-Mask: 0x07)                  */
-#define CRG_SYS_BATCHECK_REG_BATCHECK_TRIM_Pos (0UL)                /*!< BATCHECK_TRIM (Bit 0)                                 */
-#define CRG_SYS_BATCHECK_REG_BATCHECK_TRIM_Msk (0xfUL)              /*!< BATCHECK_TRIM (Bitfield-Mask: 0x0f)                   */
-/* ======================================================  CLK_SYS_REG  ====================================================== */
-#define CRG_SYS_CLK_SYS_REG_CLK_CHG_EN_Pos (5UL)                    /*!< CLK_CHG_EN (Bit 5)                                    */
-#define CRG_SYS_CLK_SYS_REG_CLK_CHG_EN_Msk (0x20UL)                 /*!< CLK_CHG_EN (Bitfield-Mask: 0x01)                      */
-#define CRG_SYS_CLK_SYS_REG_LCD_RESET_REQ_Pos (4UL)                 /*!< LCD_RESET_REQ (Bit 4)                                 */
-#define CRG_SYS_CLK_SYS_REG_LCD_RESET_REQ_Msk (0x10UL)              /*!< LCD_RESET_REQ (Bitfield-Mask: 0x01)                   */
-#define CRG_SYS_CLK_SYS_REG_LCD_CLK_SEL_Pos (1UL)                   /*!< LCD_CLK_SEL (Bit 1)                                   */
-#define CRG_SYS_CLK_SYS_REG_LCD_CLK_SEL_Msk (0x2UL)                 /*!< LCD_CLK_SEL (Bitfield-Mask: 0x01)                     */
-#define CRG_SYS_CLK_SYS_REG_LCD_ENABLE_Pos (0UL)                    /*!< LCD_ENABLE (Bit 0)                                    */
-#define CRG_SYS_CLK_SYS_REG_LCD_ENABLE_Msk (0x1UL)                  /*!< LCD_ENABLE (Bitfield-Mask: 0x01)                      */
-
-
-/* =========================================================================================================================== */
-/* ================                                          CRG_TOP                                          ================ */
-/* =========================================================================================================================== */
-
-/* ====================================================  ANA_STATUS_REG  ===================================================== */
-#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_HIGH_Pos (14UL)            /*!< COMP_VBUS_HIGH (Bit 14)                               */
-#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_HIGH_Msk (0x4000UL)        /*!< COMP_VBUS_HIGH (Bitfield-Mask: 0x01)                  */
-#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_LOW_Pos (13UL)             /*!< COMP_VBUS_LOW (Bit 13)                                */
-#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_LOW_Msk (0x2000UL)         /*!< COMP_VBUS_LOW (Bitfield-Mask: 0x01)                   */
-#define CRG_TOP_ANA_STATUS_REG_COMP_VBAT_HIGH_Pos (12UL)            /*!< COMP_VBAT_HIGH (Bit 12)                               */
-#define CRG_TOP_ANA_STATUS_REG_COMP_VBAT_HIGH_Msk (0x1000UL)        /*!< COMP_VBAT_HIGH (Bitfield-Mask: 0x01)                  */
-#define CRG_TOP_ANA_STATUS_REG_COMP_VBAT_LOW_Pos (11UL)             /*!< COMP_VBAT_LOW (Bit 11)                                */
-#define CRG_TOP_ANA_STATUS_REG_COMP_VBAT_LOW_Msk (0x800UL)          /*!< COMP_VBAT_LOW (Bitfield-Mask: 0x01)                   */
-#define CRG_TOP_ANA_STATUS_REG_COMP_VDD_OK_Pos (10UL)               /*!< COMP_VDD_OK (Bit 10)                                  */
-#define CRG_TOP_ANA_STATUS_REG_COMP_VDD_OK_Msk (0x400UL)            /*!< COMP_VDD_OK (Bitfield-Mask: 0x01)                     */
-#define CRG_TOP_ANA_STATUS_REG_VBUS_AVAILABLE_Pos (9UL)             /*!< VBUS_AVAILABLE (Bit 9)                                */
-#define CRG_TOP_ANA_STATUS_REG_VBUS_AVAILABLE_Msk (0x200UL)         /*!< VBUS_AVAILABLE (Bitfield-Mask: 0x01)                  */
-#define CRG_TOP_ANA_STATUS_REG_BANDGAP_OK_Pos (8UL)                 /*!< BANDGAP_OK (Bit 8)                                    */
-#define CRG_TOP_ANA_STATUS_REG_BANDGAP_OK_Msk (0x100UL)             /*!< BANDGAP_OK (Bitfield-Mask: 0x01)                      */
-#define CRG_TOP_ANA_STATUS_REG_LDO_3V0_VBAT_OK_Pos (7UL)            /*!< LDO_3V0_VBAT_OK (Bit 7)                               */
-#define CRG_TOP_ANA_STATUS_REG_LDO_3V0_VBAT_OK_Msk (0x80UL)         /*!< LDO_3V0_VBAT_OK (Bitfield-Mask: 0x01)                 */
-#define CRG_TOP_ANA_STATUS_REG_LDO_3V0_VBUS_OK_Pos (6UL)            /*!< LDO_3V0_VBUS_OK (Bit 6)                               */
-#define CRG_TOP_ANA_STATUS_REG_LDO_3V0_VBUS_OK_Msk (0x40UL)         /*!< LDO_3V0_VBUS_OK (Bitfield-Mask: 0x01)                 */
-#define CRG_TOP_ANA_STATUS_REG_LDO_1V8P_OK_Pos (5UL)                /*!< LDO_1V8P_OK (Bit 5)                                   */
-#define CRG_TOP_ANA_STATUS_REG_LDO_1V8P_OK_Msk (0x20UL)             /*!< LDO_1V8P_OK (Bitfield-Mask: 0x01)                     */
-#define CRG_TOP_ANA_STATUS_REG_LDO_1V8_OK_Pos (4UL)                 /*!< LDO_1V8_OK (Bit 4)                                    */
-#define CRG_TOP_ANA_STATUS_REG_LDO_1V8_OK_Msk (0x10UL)              /*!< LDO_1V8_OK (Bitfield-Mask: 0x01)                      */
-#define CRG_TOP_ANA_STATUS_REG_LDO_RADIO_OK_Pos (3UL)               /*!< LDO_RADIO_OK (Bit 3)                                  */
-#define CRG_TOP_ANA_STATUS_REG_LDO_RADIO_OK_Msk (0x8UL)             /*!< LDO_RADIO_OK (Bitfield-Mask: 0x01)                    */
-#define CRG_TOP_ANA_STATUS_REG_LDO_CORE_OK_Pos (2UL)                /*!< LDO_CORE_OK (Bit 2)                                   */
-#define CRG_TOP_ANA_STATUS_REG_LDO_CORE_OK_Msk (0x4UL)              /*!< LDO_CORE_OK (Bitfield-Mask: 0x01)                     */
-#define CRG_TOP_ANA_STATUS_REG_LDO_VDD_HIGH_OK_Pos (1UL)            /*!< LDO_VDD_HIGH_OK (Bit 1)                               */
-#define CRG_TOP_ANA_STATUS_REG_LDO_VDD_HIGH_OK_Msk (0x2UL)          /*!< LDO_VDD_HIGH_OK (Bitfield-Mask: 0x01)                 */
-#define CRG_TOP_ANA_STATUS_REG_BOD_VIN_NOK_Pos (0UL)                /*!< BOD_VIN_NOK (Bit 0)                                   */
-#define CRG_TOP_ANA_STATUS_REG_BOD_VIN_NOK_Msk (0x1UL)              /*!< BOD_VIN_NOK (Bitfield-Mask: 0x01)                     */
-/* ======================================================  BANDGAP_REG  ====================================================== */
-#define CRG_TOP_BANDGAP_REG_BANDGAP_ENABLE_CLAMP_Pos (12UL)         /*!< BANDGAP_ENABLE_CLAMP (Bit 12)                         */
-#define CRG_TOP_BANDGAP_REG_BANDGAP_ENABLE_CLAMP_Msk (0x1000UL)     /*!< BANDGAP_ENABLE_CLAMP (Bitfield-Mask: 0x01)            */
-#define CRG_TOP_BANDGAP_REG_BGR_ITRIM_Pos (6UL)                     /*!< BGR_ITRIM (Bit 6)                                     */
-#define CRG_TOP_BANDGAP_REG_BGR_ITRIM_Msk (0xfc0UL)                 /*!< BGR_ITRIM (Bitfield-Mask: 0x3f)                       */
-#define CRG_TOP_BANDGAP_REG_SYSRAM_LPMX_Pos (5UL)                   /*!< SYSRAM_LPMX (Bit 5)                                   */
-#define CRG_TOP_BANDGAP_REG_SYSRAM_LPMX_Msk (0x20UL)                /*!< SYSRAM_LPMX (Bitfield-Mask: 0x01)                     */
-#define CRG_TOP_BANDGAP_REG_BGR_TRIM_Pos  (0UL)                     /*!< BGR_TRIM (Bit 0)                                      */
-#define CRG_TOP_BANDGAP_REG_BGR_TRIM_Msk  (0x1fUL)                  /*!< BGR_TRIM (Bitfield-Mask: 0x1f)                        */
-/* ===================================================  BIAS_VREF_SEL_REG  =================================================== */
-#define CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF2_SEL_Pos (4UL)       /*!< BIAS_VREF_RF2_SEL (Bit 4)                             */
-#define CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF2_SEL_Msk (0xf0UL)    /*!< BIAS_VREF_RF2_SEL (Bitfield-Mask: 0x0f)               */
-#define CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF1_SEL_Pos (0UL)       /*!< BIAS_VREF_RF1_SEL (Bit 0)                             */
-#define CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF1_SEL_Msk (0xfUL)     /*!< BIAS_VREF_RF1_SEL (Bitfield-Mask: 0x0f)               */
-/* =====================================================  BOD_CTRL_REG  ====================================================== */
-#define CRG_TOP_BOD_CTRL_REG_BOD_V14_RST_EN_Pos (16UL)              /*!< BOD_V14_RST_EN (Bit 16)                               */
-#define CRG_TOP_BOD_CTRL_REG_BOD_V14_RST_EN_Msk (0x10000UL)         /*!< BOD_V14_RST_EN (Bitfield-Mask: 0x01)                  */
-#define CRG_TOP_BOD_CTRL_REG_BOD_V18F_RST_EN_Pos (15UL)             /*!< BOD_V18F_RST_EN (Bit 15)                              */
-#define CRG_TOP_BOD_CTRL_REG_BOD_V18F_RST_EN_Msk (0x8000UL)         /*!< BOD_V18F_RST_EN (Bitfield-Mask: 0x01)                 */
-#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_RST_EN_Pos (14UL)              /*!< BOD_VDD_RST_EN (Bit 14)                               */
-#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_RST_EN_Msk (0x4000UL)          /*!< BOD_VDD_RST_EN (Bitfield-Mask: 0x01)                  */
-#define CRG_TOP_BOD_CTRL_REG_BOD_V18P_RST_EN_Pos (13UL)             /*!< BOD_V18P_RST_EN (Bit 13)                              */
-#define CRG_TOP_BOD_CTRL_REG_BOD_V18P_RST_EN_Msk (0x2000UL)         /*!< BOD_V18P_RST_EN (Bitfield-Mask: 0x01)                 */
-#define CRG_TOP_BOD_CTRL_REG_BOD_V18_RST_EN_Pos (12UL)              /*!< BOD_V18_RST_EN (Bit 12)                               */
-#define CRG_TOP_BOD_CTRL_REG_BOD_V18_RST_EN_Msk (0x1000UL)          /*!< BOD_V18_RST_EN (Bitfield-Mask: 0x01)                  */
-#define CRG_TOP_BOD_CTRL_REG_BOD_V30_RST_EN_Pos (11UL)              /*!< BOD_V30_RST_EN (Bit 11)                               */
-#define CRG_TOP_BOD_CTRL_REG_BOD_V30_RST_EN_Msk (0x800UL)           /*!< BOD_V30_RST_EN (Bitfield-Mask: 0x01)                  */
-#define CRG_TOP_BOD_CTRL_REG_BOD_VBAT_RST_EN_Pos (10UL)             /*!< BOD_VBAT_RST_EN (Bit 10)                              */
-#define CRG_TOP_BOD_CTRL_REG_BOD_VBAT_RST_EN_Msk (0x400UL)          /*!< BOD_VBAT_RST_EN (Bitfield-Mask: 0x01)                 */
-#define CRG_TOP_BOD_CTRL_REG_BOD_V14_EN_Pos (9UL)                   /*!< BOD_V14_EN (Bit 9)                                    */
-#define CRG_TOP_BOD_CTRL_REG_BOD_V14_EN_Msk (0x200UL)               /*!< BOD_V14_EN (Bitfield-Mask: 0x01)                      */
-#define CRG_TOP_BOD_CTRL_REG_BOD_V18F_EN_Pos (8UL)                  /*!< BOD_V18F_EN (Bit 8)                                   */
-#define CRG_TOP_BOD_CTRL_REG_BOD_V18F_EN_Msk (0x100UL)              /*!< BOD_V18F_EN (Bitfield-Mask: 0x01)                     */
-#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_EN_Pos (7UL)                   /*!< BOD_VDD_EN (Bit 7)                                    */
-#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_EN_Msk (0x80UL)                /*!< BOD_VDD_EN (Bitfield-Mask: 0x01)                      */
-#define CRG_TOP_BOD_CTRL_REG_BOD_V18P_EN_Pos (6UL)                  /*!< BOD_V18P_EN (Bit 6)                                   */
-#define CRG_TOP_BOD_CTRL_REG_BOD_V18P_EN_Msk (0x40UL)               /*!< BOD_V18P_EN (Bitfield-Mask: 0x01)                     */
-#define CRG_TOP_BOD_CTRL_REG_BOD_V18_EN_Pos (5UL)                   /*!< BOD_V18_EN (Bit 5)                                    */
-#define CRG_TOP_BOD_CTRL_REG_BOD_V18_EN_Msk (0x20UL)                /*!< BOD_V18_EN (Bitfield-Mask: 0x01)                      */
-#define CRG_TOP_BOD_CTRL_REG_BOD_V30_EN_Pos (4UL)                   /*!< BOD_V30_EN (Bit 4)                                    */
-#define CRG_TOP_BOD_CTRL_REG_BOD_V30_EN_Msk (0x10UL)                /*!< BOD_V30_EN (Bitfield-Mask: 0x01)                      */
-#define CRG_TOP_BOD_CTRL_REG_BOD_VBAT_EN_Pos (3UL)                  /*!< BOD_VBAT_EN (Bit 3)                                   */
-#define CRG_TOP_BOD_CTRL_REG_BOD_VBAT_EN_Msk (0x8UL)                /*!< BOD_VBAT_EN (Bitfield-Mask: 0x01)                     */
-#define CRG_TOP_BOD_CTRL_REG_BOD_STATUS_CLEAR_Pos (2UL)             /*!< BOD_STATUS_CLEAR (Bit 2)                              */
-#define CRG_TOP_BOD_CTRL_REG_BOD_STATUS_CLEAR_Msk (0x4UL)           /*!< BOD_STATUS_CLEAR (Bitfield-Mask: 0x01)                */
-#define CRG_TOP_BOD_CTRL_REG_BOD_CLK_DIV_Pos (0UL)                  /*!< BOD_CLK_DIV (Bit 0)                                   */
-#define CRG_TOP_BOD_CTRL_REG_BOD_CLK_DIV_Msk (0x3UL)                /*!< BOD_CLK_DIV (Bitfield-Mask: 0x03)                     */
-/* ===================================================  BOD_LVL_CTRL0_REG  =================================================== */
-#define CRG_TOP_BOD_LVL_CTRL0_REG_BOD_LVL_V18_Pos (18UL)            /*!< BOD_LVL_V18 (Bit 18)                                  */
-#define CRG_TOP_BOD_LVL_CTRL0_REG_BOD_LVL_V18_Msk (0x7fc0000UL)     /*!< BOD_LVL_V18 (Bitfield-Mask: 0x1ff)                    */
-#define CRG_TOP_BOD_LVL_CTRL0_REG_BOD_LVL_V30_Pos (9UL)             /*!< BOD_LVL_V30 (Bit 9)                                   */
-#define CRG_TOP_BOD_LVL_CTRL0_REG_BOD_LVL_V30_Msk (0x3fe00UL)       /*!< BOD_LVL_V30 (Bitfield-Mask: 0x1ff)                    */
-#define CRG_TOP_BOD_LVL_CTRL0_REG_BOD_LVL_VBAT_Pos (0UL)            /*!< BOD_LVL_VBAT (Bit 0)                                  */
-#define CRG_TOP_BOD_LVL_CTRL0_REG_BOD_LVL_VBAT_Msk (0x1ffUL)        /*!< BOD_LVL_VBAT (Bitfield-Mask: 0x1ff)                   */
-/* ===================================================  BOD_LVL_CTRL1_REG  =================================================== */
-#define CRG_TOP_BOD_LVL_CTRL1_REG_BOD_LVL_VDD_RET_Pos (17UL)        /*!< BOD_LVL_VDD_RET (Bit 17)                              */
-#define CRG_TOP_BOD_LVL_CTRL1_REG_BOD_LVL_VDD_RET_Msk (0x1fe0000UL) /*!< BOD_LVL_VDD_RET (Bitfield-Mask: 0xff)                 */
-#define CRG_TOP_BOD_LVL_CTRL1_REG_BOD_LVL_VDD_ON_Pos (9UL)          /*!< BOD_LVL_VDD_ON (Bit 9)                                */
-#define CRG_TOP_BOD_LVL_CTRL1_REG_BOD_LVL_VDD_ON_Msk (0x1fe00UL)    /*!< BOD_LVL_VDD_ON (Bitfield-Mask: 0xff)                  */
-#define CRG_TOP_BOD_LVL_CTRL1_REG_BOD_LVL_V18P_Pos (0UL)            /*!< BOD_LVL_V18P (Bit 0)                                  */
-#define CRG_TOP_BOD_LVL_CTRL1_REG_BOD_LVL_V18P_Msk (0x1ffUL)        /*!< BOD_LVL_V18P (Bitfield-Mask: 0x1ff)                   */
-/* ===================================================  BOD_LVL_CTRL2_REG  =================================================== */
-#define CRG_TOP_BOD_LVL_CTRL2_REG_BOD_LVL_V14_Pos (9UL)             /*!< BOD_LVL_V14 (Bit 9)                                   */
-#define CRG_TOP_BOD_LVL_CTRL2_REG_BOD_LVL_V14_Msk (0x3fe00UL)       /*!< BOD_LVL_V14 (Bitfield-Mask: 0x1ff)                    */
-#define CRG_TOP_BOD_LVL_CTRL2_REG_BOD_LVL_V18F_Pos (0UL)            /*!< BOD_LVL_V18F (Bit 0)                                  */
-#define CRG_TOP_BOD_LVL_CTRL2_REG_BOD_LVL_V18F_Msk (0x1ffUL)        /*!< BOD_LVL_V18F (Bitfield-Mask: 0x1ff)                   */
-/* ====================================================  BOD_STATUS_REG  ===================================================== */
-#define CRG_TOP_BOD_STATUS_REG_BOD_V14_Pos (6UL)                    /*!< BOD_V14 (Bit 6)                                       */
-#define CRG_TOP_BOD_STATUS_REG_BOD_V14_Msk (0x40UL)                 /*!< BOD_V14 (Bitfield-Mask: 0x01)                         */
-#define CRG_TOP_BOD_STATUS_REG_BOD_V18F_Pos (5UL)                   /*!< BOD_V18F (Bit 5)                                      */
-#define CRG_TOP_BOD_STATUS_REG_BOD_V18F_Msk (0x20UL)                /*!< BOD_V18F (Bitfield-Mask: 0x01)                        */
-#define CRG_TOP_BOD_STATUS_REG_BOD_VDD_Pos (4UL)                    /*!< BOD_VDD (Bit 4)                                       */
-#define CRG_TOP_BOD_STATUS_REG_BOD_VDD_Msk (0x10UL)                 /*!< BOD_VDD (Bitfield-Mask: 0x01)                         */
-#define CRG_TOP_BOD_STATUS_REG_BOD_V18P_Pos (3UL)                   /*!< BOD_V18P (Bit 3)                                      */
-#define CRG_TOP_BOD_STATUS_REG_BOD_V18P_Msk (0x8UL)                 /*!< BOD_V18P (Bitfield-Mask: 0x01)                        */
-#define CRG_TOP_BOD_STATUS_REG_BOD_V18_Pos (2UL)                    /*!< BOD_V18 (Bit 2)                                       */
-#define CRG_TOP_BOD_STATUS_REG_BOD_V18_Msk (0x4UL)                  /*!< BOD_V18 (Bitfield-Mask: 0x01)                         */
-#define CRG_TOP_BOD_STATUS_REG_BOD_V30_Pos (1UL)                    /*!< BOD_V30 (Bit 1)                                       */
-#define CRG_TOP_BOD_STATUS_REG_BOD_V30_Msk (0x2UL)                  /*!< BOD_V30 (Bitfield-Mask: 0x01)                         */
-#define CRG_TOP_BOD_STATUS_REG_BOD_VBAT_Pos (0UL)                   /*!< BOD_VBAT (Bit 0)                                      */
-#define CRG_TOP_BOD_STATUS_REG_BOD_VBAT_Msk (0x1UL)                 /*!< BOD_VBAT (Bitfield-Mask: 0x01)                        */
-/* =====================================================  CLK_AMBA_REG  ====================================================== */
-#define CRG_TOP_CLK_AMBA_REG_QSPI2_ENABLE_Pos (15UL)                /*!< QSPI2_ENABLE (Bit 15)                                 */
-#define CRG_TOP_CLK_AMBA_REG_QSPI2_ENABLE_Msk (0x8000UL)            /*!< QSPI2_ENABLE (Bitfield-Mask: 0x01)                    */
-#define CRG_TOP_CLK_AMBA_REG_QSPI2_DIV_Pos (13UL)                   /*!< QSPI2_DIV (Bit 13)                                    */
-#define CRG_TOP_CLK_AMBA_REG_QSPI2_DIV_Msk (0x6000UL)               /*!< QSPI2_DIV (Bitfield-Mask: 0x03)                       */
-#define CRG_TOP_CLK_AMBA_REG_QSPI_ENABLE_Pos (12UL)                 /*!< QSPI_ENABLE (Bit 12)                                  */
-#define CRG_TOP_CLK_AMBA_REG_QSPI_ENABLE_Msk (0x1000UL)             /*!< QSPI_ENABLE (Bitfield-Mask: 0x01)                     */
-#define CRG_TOP_CLK_AMBA_REG_QSPI_DIV_Pos (10UL)                    /*!< QSPI_DIV (Bit 10)                                     */
-#define CRG_TOP_CLK_AMBA_REG_QSPI_DIV_Msk (0xc00UL)                 /*!< QSPI_DIV (Bitfield-Mask: 0x03)                        */
-#define CRG_TOP_CLK_AMBA_REG_OTP_ENABLE_Pos (9UL)                   /*!< OTP_ENABLE (Bit 9)                                    */
-#define CRG_TOP_CLK_AMBA_REG_OTP_ENABLE_Msk (0x200UL)               /*!< OTP_ENABLE (Bitfield-Mask: 0x01)                      */
-#define CRG_TOP_CLK_AMBA_REG_TRNG_CLK_ENABLE_Pos (8UL)              /*!< TRNG_CLK_ENABLE (Bit 8)                               */
-#define CRG_TOP_CLK_AMBA_REG_TRNG_CLK_ENABLE_Msk (0x100UL)          /*!< TRNG_CLK_ENABLE (Bitfield-Mask: 0x01)                 */
-#define CRG_TOP_CLK_AMBA_REG_AES_CLK_ENABLE_Pos (6UL)               /*!< AES_CLK_ENABLE (Bit 6)                                */
-#define CRG_TOP_CLK_AMBA_REG_AES_CLK_ENABLE_Msk (0x40UL)            /*!< AES_CLK_ENABLE (Bitfield-Mask: 0x01)                  */
-#define CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Pos (4UL)                     /*!< PCLK_DIV (Bit 4)                                      */
-#define CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk (0x30UL)                  /*!< PCLK_DIV (Bitfield-Mask: 0x03)                        */
-#define CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Pos (0UL)                     /*!< HCLK_DIV (Bit 0)                                      */
-#define CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk (0x7UL)                   /*!< HCLK_DIV (Bitfield-Mask: 0x07)                        */
-/* =====================================================  CLK_CTRL_REG  ====================================================== */
-#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Pos (15UL)           /*!< RUNNING_AT_PLL96M (Bit 15)                            */
-#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Msk (0x8000UL)       /*!< RUNNING_AT_PLL96M (Bitfield-Mask: 0x01)               */
-#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL32M_Pos (14UL)          /*!< RUNNING_AT_XTAL32M (Bit 14)                           */
-#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL32M_Msk (0x4000UL)      /*!< RUNNING_AT_XTAL32M (Bitfield-Mask: 0x01)              */
-#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC32M_Pos (13UL)            /*!< RUNNING_AT_RC32M (Bit 13)                             */
-#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC32M_Msk (0x2000UL)        /*!< RUNNING_AT_RC32M (Bitfield-Mask: 0x01)                */
-#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_LP_CLK_Pos (12UL)           /*!< RUNNING_AT_LP_CLK (Bit 12)                            */
-#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_LP_CLK_Msk (0x1000UL)       /*!< RUNNING_AT_LP_CLK (Bitfield-Mask: 0x01)               */
-#define CRG_TOP_CLK_CTRL_REG_USB_CLK_SRC_Pos (4UL)                  /*!< USB_CLK_SRC (Bit 4)                                   */
-#define CRG_TOP_CLK_CTRL_REG_USB_CLK_SRC_Msk (0x10UL)               /*!< USB_CLK_SRC (Bitfield-Mask: 0x01)                     */
-#define CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos (2UL)                   /*!< LP_CLK_SEL (Bit 2)                                    */
-#define CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk (0xcUL)                 /*!< LP_CLK_SEL (Bitfield-Mask: 0x03)                      */
-#define CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Pos (0UL)                  /*!< SYS_CLK_SEL (Bit 0)                                   */
-#define CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk (0x3UL)                /*!< SYS_CLK_SEL (Bitfield-Mask: 0x03)                     */
-/* =====================================================  CLK_RADIO_REG  ===================================================== */
-#define CRG_TOP_CLK_RADIO_REG_RFCU_ENABLE_Pos (5UL)                 /*!< RFCU_ENABLE (Bit 5)                                   */
-#define CRG_TOP_CLK_RADIO_REG_RFCU_ENABLE_Msk (0x20UL)              /*!< RFCU_ENABLE (Bitfield-Mask: 0x01)                     */
-#define CRG_TOP_CLK_RADIO_REG_CMAC_SYNCH_RESET_Pos (4UL)            /*!< CMAC_SYNCH_RESET (Bit 4)                              */
-#define CRG_TOP_CLK_RADIO_REG_CMAC_SYNCH_RESET_Msk (0x10UL)         /*!< CMAC_SYNCH_RESET (Bitfield-Mask: 0x01)                */
-#define CRG_TOP_CLK_RADIO_REG_CMAC_CLK_SEL_Pos (3UL)                /*!< CMAC_CLK_SEL (Bit 3)                                  */
-#define CRG_TOP_CLK_RADIO_REG_CMAC_CLK_SEL_Msk (0x8UL)              /*!< CMAC_CLK_SEL (Bitfield-Mask: 0x01)                    */
-#define CRG_TOP_CLK_RADIO_REG_CMAC_CLK_ENABLE_Pos (2UL)             /*!< CMAC_CLK_ENABLE (Bit 2)                               */
-#define CRG_TOP_CLK_RADIO_REG_CMAC_CLK_ENABLE_Msk (0x4UL)           /*!< CMAC_CLK_ENABLE (Bitfield-Mask: 0x01)                 */
-#define CRG_TOP_CLK_RADIO_REG_CMAC_DIV_Pos (0UL)                    /*!< CMAC_DIV (Bit 0)                                      */
-#define CRG_TOP_CLK_RADIO_REG_CMAC_DIV_Msk (0x3UL)                  /*!< CMAC_DIV (Bitfield-Mask: 0x03)                        */
-/* =====================================================  CLK_RC32K_REG  ===================================================== */
-#define CRG_TOP_CLK_RC32K_REG_RC32K_TRIM_Pos (1UL)                  /*!< RC32K_TRIM (Bit 1)                                    */
-#define CRG_TOP_CLK_RC32K_REG_RC32K_TRIM_Msk (0x1eUL)               /*!< RC32K_TRIM (Bitfield-Mask: 0x0f)                      */
-#define CRG_TOP_CLK_RC32K_REG_RC32K_ENABLE_Pos (0UL)                /*!< RC32K_ENABLE (Bit 0)                                  */
-#define CRG_TOP_CLK_RC32K_REG_RC32K_ENABLE_Msk (0x1UL)              /*!< RC32K_ENABLE (Bitfield-Mask: 0x01)                    */
-/* =====================================================  CLK_RC32M_REG  ===================================================== */
-#define CRG_TOP_CLK_RC32M_REG_RC32M_INIT_RANGE_Pos (20UL)           /*!< RC32M_INIT_RANGE (Bit 20)                             */
-#define CRG_TOP_CLK_RC32M_REG_RC32M_INIT_RANGE_Msk (0x300000UL)     /*!< RC32M_INIT_RANGE (Bitfield-Mask: 0x03)                */
-#define CRG_TOP_CLK_RC32M_REG_RC32M_INIT_DEL_Pos (12UL)             /*!< RC32M_INIT_DEL (Bit 12)                               */
-#define CRG_TOP_CLK_RC32M_REG_RC32M_INIT_DEL_Msk (0xff000UL)        /*!< RC32M_INIT_DEL (Bitfield-Mask: 0xff)                  */
-#define CRG_TOP_CLK_RC32M_REG_RC32M_INIT_DTCF_Pos (9UL)             /*!< RC32M_INIT_DTCF (Bit 9)                               */
-#define CRG_TOP_CLK_RC32M_REG_RC32M_INIT_DTCF_Msk (0xe00UL)         /*!< RC32M_INIT_DTCF (Bitfield-Mask: 0x07)                 */
-#define CRG_TOP_CLK_RC32M_REG_RC32M_INIT_DTC_Pos (5UL)              /*!< RC32M_INIT_DTC (Bit 5)                                */
-#define CRG_TOP_CLK_RC32M_REG_RC32M_INIT_DTC_Msk (0x1e0UL)          /*!< RC32M_INIT_DTC (Bitfield-Mask: 0x0f)                  */
-#define CRG_TOP_CLK_RC32M_REG_RC32M_BIAS_Pos (1UL)                  /*!< RC32M_BIAS (Bit 1)                                    */
-#define CRG_TOP_CLK_RC32M_REG_RC32M_BIAS_Msk (0x1eUL)               /*!< RC32M_BIAS (Bitfield-Mask: 0x0f)                      */
-#define CRG_TOP_CLK_RC32M_REG_RC32M_ENABLE_Pos (0UL)                /*!< RC32M_ENABLE (Bit 0)                                  */
-#define CRG_TOP_CLK_RC32M_REG_RC32M_ENABLE_Msk (0x1UL)              /*!< RC32M_ENABLE (Bitfield-Mask: 0x01)                    */
-/* ======================================================  CLK_RCX_REG  ====================================================== */
-#define CRG_TOP_CLK_RCX_REG_RCX_BIAS_Pos  (8UL)                     /*!< RCX_BIAS (Bit 8)                                      */
-#define CRG_TOP_CLK_RCX_REG_RCX_BIAS_Msk  (0xf00UL)                 /*!< RCX_BIAS (Bitfield-Mask: 0x0f)                        */
-#define CRG_TOP_CLK_RCX_REG_RCX_C0_Pos    (7UL)                     /*!< RCX_C0 (Bit 7)                                        */
-#define CRG_TOP_CLK_RCX_REG_RCX_C0_Msk    (0x80UL)                  /*!< RCX_C0 (Bitfield-Mask: 0x01)                          */
-#define CRG_TOP_CLK_RCX_REG_RCX_CADJUST_Pos (2UL)                   /*!< RCX_CADJUST (Bit 2)                                   */
-#define CRG_TOP_CLK_RCX_REG_RCX_CADJUST_Msk (0x7cUL)                /*!< RCX_CADJUST (Bitfield-Mask: 0x1f)                     */
-#define CRG_TOP_CLK_RCX_REG_RCX_RADJUST_Pos (1UL)                   /*!< RCX_RADJUST (Bit 1)                                   */
-#define CRG_TOP_CLK_RCX_REG_RCX_RADJUST_Msk (0x2UL)                 /*!< RCX_RADJUST (Bitfield-Mask: 0x01)                     */
-#define CRG_TOP_CLK_RCX_REG_RCX_ENABLE_Pos (0UL)                    /*!< RCX_ENABLE (Bit 0)                                    */
-#define CRG_TOP_CLK_RCX_REG_RCX_ENABLE_Msk (0x1UL)                  /*!< RCX_ENABLE (Bitfield-Mask: 0x01)                      */
-/* ====================================================  CLK_RTCDIV_REG  ===================================================== */
-#define CRG_TOP_CLK_RTCDIV_REG_RTC_RESET_REQ_Pos (21UL)             /*!< RTC_RESET_REQ (Bit 21)                                */
-#define CRG_TOP_CLK_RTCDIV_REG_RTC_RESET_REQ_Msk (0x200000UL)       /*!< RTC_RESET_REQ (Bitfield-Mask: 0x01)                   */
-#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_ENABLE_Pos (20UL)            /*!< RTC_DIV_ENABLE (Bit 20)                               */
-#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_ENABLE_Msk (0x100000UL)      /*!< RTC_DIV_ENABLE (Bitfield-Mask: 0x01)                  */
-#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_DENOM_Pos (19UL)             /*!< RTC_DIV_DENOM (Bit 19)                                */
-#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_DENOM_Msk (0x80000UL)        /*!< RTC_DIV_DENOM (Bitfield-Mask: 0x01)                   */
-#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_INT_Pos (10UL)               /*!< RTC_DIV_INT (Bit 10)                                  */
-#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_INT_Msk (0x7fc00UL)          /*!< RTC_DIV_INT (Bitfield-Mask: 0x1ff)                    */
-#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_FRAC_Pos (0UL)               /*!< RTC_DIV_FRAC (Bit 0)                                  */
-#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_FRAC_Msk (0x3ffUL)           /*!< RTC_DIV_FRAC (Bitfield-Mask: 0x3ff)                   */
-/* ==================================================  CLK_SWITCH2XTAL_REG  ================================================== */
-#define CRG_TOP_CLK_SWITCH2XTAL_REG_SWITCH2XTAL_Pos (0UL)           /*!< SWITCH2XTAL (Bit 0)                                   */
-#define CRG_TOP_CLK_SWITCH2XTAL_REG_SWITCH2XTAL_Msk (0x1UL)         /*!< SWITCH2XTAL (Bitfield-Mask: 0x01)                     */
-/* ======================================================  CLK_TMR_REG  ====================================================== */
-#define CRG_TOP_CLK_TMR_REG_TMR2_PWM_AON_MODE_Pos (2UL)             /*!< TMR2_PWM_AON_MODE (Bit 2)                             */
-#define CRG_TOP_CLK_TMR_REG_TMR2_PWM_AON_MODE_Msk (0x4UL)           /*!< TMR2_PWM_AON_MODE (Bitfield-Mask: 0x01)               */
-#define CRG_TOP_CLK_TMR_REG_TMR_PWM_AON_MODE_Pos (1UL)              /*!< TMR_PWM_AON_MODE (Bit 1)                              */
-#define CRG_TOP_CLK_TMR_REG_TMR_PWM_AON_MODE_Msk (0x2UL)            /*!< TMR_PWM_AON_MODE (Bitfield-Mask: 0x01)                */
-#define CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Pos (0UL)               /*!< WAKEUPCT_ENABLE (Bit 0)                               */
-#define CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Msk (0x1UL)             /*!< WAKEUPCT_ENABLE (Bitfield-Mask: 0x01)                 */
-/* ====================================================  CLK_XTAL32K_REG  ==================================================== */
-#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_DISABLE_OUTPUT_Pos (9UL)    /*!< XTAL32K_DISABLE_OUTPUT (Bit 9)                        */
-#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_DISABLE_OUTPUT_Msk (0x200UL) /*!< XTAL32K_DISABLE_OUTPUT (Bitfield-Mask: 0x01)         */
-#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_DISABLE_AMPREG_Pos (7UL)    /*!< XTAL32K_DISABLE_AMPREG (Bit 7)                        */
-#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_DISABLE_AMPREG_Msk (0x80UL) /*!< XTAL32K_DISABLE_AMPREG (Bitfield-Mask: 0x01)          */
-#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_CUR_Pos (3UL)               /*!< XTAL32K_CUR (Bit 3)                                   */
-#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_CUR_Msk (0x78UL)            /*!< XTAL32K_CUR (Bitfield-Mask: 0x0f)                     */
-#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_RBIAS_Pos (1UL)             /*!< XTAL32K_RBIAS (Bit 1)                                 */
-#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_RBIAS_Msk (0x6UL)           /*!< XTAL32K_RBIAS (Bitfield-Mask: 0x03)                   */
-#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_ENABLE_Pos (0UL)            /*!< XTAL32K_ENABLE (Bit 0)                                */
-#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_ENABLE_Msk (0x1UL)          /*!< XTAL32K_ENABLE (Bitfield-Mask: 0x01)                  */
-/* ==================================================  DISCHARGE_RAIL_REG  =================================================== */
-#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18P_Pos (2UL)             /*!< RESET_V18P (Bit 2)                                    */
-#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18P_Msk (0x4UL)           /*!< RESET_V18P (Bitfield-Mask: 0x01)                      */
-#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18_Pos (1UL)              /*!< RESET_V18 (Bit 1)                                     */
-#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18_Msk (0x2UL)            /*!< RESET_V18 (Bitfield-Mask: 0x01)                       */
-#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V14_Pos (0UL)              /*!< RESET_V14 (Bit 0)                                     */
-#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V14_Msk (0x1UL)            /*!< RESET_V14 (Bitfield-Mask: 0x01)                       */
-/* ================================================  LDO_VDDD_HIGH_CTRL_REG  ================================================= */
-#define CRG_TOP_LDO_VDDD_HIGH_CTRL_REG_LDO_VDDD_HIGH_LOW_ZOUT_DISABLE_Pos (3UL) /*!< LDO_VDDD_HIGH_LOW_ZOUT_DISABLE (Bit 3)    */
-#define CRG_TOP_LDO_VDDD_HIGH_CTRL_REG_LDO_VDDD_HIGH_LOW_ZOUT_DISABLE_Msk (0x8UL) /*!< LDO_VDDD_HIGH_LOW_ZOUT_DISABLE (Bitfield-Mask: 0x01) */
-#define CRG_TOP_LDO_VDDD_HIGH_CTRL_REG_LDO_VDDD_HIGH_STATIC_LOAD_ENABLE_Pos (2UL) /*!< LDO_VDDD_HIGH_STATIC_LOAD_ENABLE (Bit 2) */
-#define CRG_TOP_LDO_VDDD_HIGH_CTRL_REG_LDO_VDDD_HIGH_STATIC_LOAD_ENABLE_Msk (0x4UL) /*!< LDO_VDDD_HIGH_STATIC_LOAD_ENABLE (Bitfield-Mask: 0x01) */
-#define CRG_TOP_LDO_VDDD_HIGH_CTRL_REG_LDO_VDDD_HIGH_ENABLE_Pos (1UL) /*!< LDO_VDDD_HIGH_ENABLE (Bit 1)                        */
-#define CRG_TOP_LDO_VDDD_HIGH_CTRL_REG_LDO_VDDD_HIGH_ENABLE_Msk (0x2UL) /*!< LDO_VDDD_HIGH_ENABLE (Bitfield-Mask: 0x01)        */
-#define CRG_TOP_LDO_VDDD_HIGH_CTRL_REG_LDO_VDDD_HIGH_VREF_HOLD_Pos (0UL) /*!< LDO_VDDD_HIGH_VREF_HOLD (Bit 0)                  */
-#define CRG_TOP_LDO_VDDD_HIGH_CTRL_REG_LDO_VDDD_HIGH_VREF_HOLD_Msk (0x1UL) /*!< LDO_VDDD_HIGH_VREF_HOLD (Bitfield-Mask: 0x01)  */
-/* ===================================================  P0_PAD_LATCH_REG  ==================================================== */
-#define CRG_TOP_P0_PAD_LATCH_REG_P0_LATCH_EN_Pos (0UL)              /*!< P0_LATCH_EN (Bit 0)                                   */
-#define CRG_TOP_P0_PAD_LATCH_REG_P0_LATCH_EN_Msk (0xffffffffUL)     /*!< P0_LATCH_EN (Bitfield-Mask: 0xffffffff)               */
-/* ================================================  P0_RESET_PAD_LATCH_REG  ================================================= */
-#define CRG_TOP_P0_RESET_PAD_LATCH_REG_P0_RESET_LATCH_EN_Pos (0UL)  /*!< P0_RESET_LATCH_EN (Bit 0)                             */
-#define CRG_TOP_P0_RESET_PAD_LATCH_REG_P0_RESET_LATCH_EN_Msk (0xffffffffUL) /*!< P0_RESET_LATCH_EN (Bitfield-Mask: 0xffffffff) */
-/* =================================================  P0_SET_PAD_LATCH_REG  ================================================== */
-#define CRG_TOP_P0_SET_PAD_LATCH_REG_P0_SET_LATCH_EN_Pos (0UL)      /*!< P0_SET_LATCH_EN (Bit 0)                               */
-#define CRG_TOP_P0_SET_PAD_LATCH_REG_P0_SET_LATCH_EN_Msk (0xffffffffUL) /*!< P0_SET_LATCH_EN (Bitfield-Mask: 0xffffffff)       */
-/* ===================================================  P1_PAD_LATCH_REG  ==================================================== */
-#define CRG_TOP_P1_PAD_LATCH_REG_P1_LATCH_EN_Pos (0UL)              /*!< P1_LATCH_EN (Bit 0)                                   */
-#define CRG_TOP_P1_PAD_LATCH_REG_P1_LATCH_EN_Msk (0x7fffffUL)       /*!< P1_LATCH_EN (Bitfield-Mask: 0x7fffff)                 */
-/* ================================================  P1_RESET_PAD_LATCH_REG  ================================================= */
-#define CRG_TOP_P1_RESET_PAD_LATCH_REG_P1_RESET_LATCH_EN_Pos (0UL)  /*!< P1_RESET_LATCH_EN (Bit 0)                             */
-#define CRG_TOP_P1_RESET_PAD_LATCH_REG_P1_RESET_LATCH_EN_Msk (0x7fffffUL) /*!< P1_RESET_LATCH_EN (Bitfield-Mask: 0x7fffff)     */
-/* =================================================  P1_SET_PAD_LATCH_REG  ================================================== */
-#define CRG_TOP_P1_SET_PAD_LATCH_REG_P1_SET_LATCH_EN_Pos (0UL)      /*!< P1_SET_LATCH_EN (Bit 0)                               */
-#define CRG_TOP_P1_SET_PAD_LATCH_REG_P1_SET_LATCH_EN_Msk (0x7fffffUL) /*!< P1_SET_LATCH_EN (Bitfield-Mask: 0x7fffff)           */
-/* =====================================================  PMU_CTRL_REG  ====================================================== */
-#define CRG_TOP_PMU_CTRL_REG_ENABLE_CLKLESS_Pos (8UL)               /*!< ENABLE_CLKLESS (Bit 8)                                */
-#define CRG_TOP_PMU_CTRL_REG_ENABLE_CLKLESS_Msk (0x100UL)           /*!< ENABLE_CLKLESS (Bitfield-Mask: 0x01)                  */
-#define CRG_TOP_PMU_CTRL_REG_RETAIN_CACHE_Pos (7UL)                 /*!< RETAIN_CACHE (Bit 7)                                  */
-#define CRG_TOP_PMU_CTRL_REG_RETAIN_CACHE_Msk (0x80UL)              /*!< RETAIN_CACHE (Bitfield-Mask: 0x01)                    */
-#define CRG_TOP_PMU_CTRL_REG_SYS_SLEEP_Pos (6UL)                    /*!< SYS_SLEEP (Bit 6)                                     */
-#define CRG_TOP_PMU_CTRL_REG_SYS_SLEEP_Msk (0x40UL)                 /*!< SYS_SLEEP (Bitfield-Mask: 0x01)                       */
-#define CRG_TOP_PMU_CTRL_REG_RESET_ON_WAKEUP_Pos (5UL)              /*!< RESET_ON_WAKEUP (Bit 5)                               */
-#define CRG_TOP_PMU_CTRL_REG_RESET_ON_WAKEUP_Msk (0x20UL)           /*!< RESET_ON_WAKEUP (Bitfield-Mask: 0x01)                 */
-#define CRG_TOP_PMU_CTRL_REG_MAP_BANDGAP_EN_Pos (4UL)               /*!< MAP_BANDGAP_EN (Bit 4)                                */
-#define CRG_TOP_PMU_CTRL_REG_MAP_BANDGAP_EN_Msk (0x10UL)            /*!< MAP_BANDGAP_EN (Bitfield-Mask: 0x01)                  */
-#define CRG_TOP_PMU_CTRL_REG_COM_SLEEP_Pos (3UL)                    /*!< COM_SLEEP (Bit 3)                                     */
-#define CRG_TOP_PMU_CTRL_REG_COM_SLEEP_Msk (0x8UL)                  /*!< COM_SLEEP (Bitfield-Mask: 0x01)                       */
-#define CRG_TOP_PMU_CTRL_REG_TIM_SLEEP_Pos (2UL)                    /*!< TIM_SLEEP (Bit 2)                                     */
-#define CRG_TOP_PMU_CTRL_REG_TIM_SLEEP_Msk (0x4UL)                  /*!< TIM_SLEEP (Bitfield-Mask: 0x01)                       */
-#define CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Pos (1UL)                  /*!< RADIO_SLEEP (Bit 1)                                   */
-#define CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Msk (0x2UL)                /*!< RADIO_SLEEP (Bitfield-Mask: 0x01)                     */
-#define CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Pos (0UL)                 /*!< PERIPH_SLEEP (Bit 0)                                  */
-#define CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Msk (0x1UL)               /*!< PERIPH_SLEEP (Bitfield-Mask: 0x01)                    */
-/* =====================================================  PMU_SLEEP_REG  ===================================================== */
-#define CRG_TOP_PMU_SLEEP_REG_CLAMP_VDD_WKUP_MAX_Pos (18UL)         /*!< CLAMP_VDD_WKUP_MAX (Bit 18)                           */
-#define CRG_TOP_PMU_SLEEP_REG_CLAMP_VDD_WKUP_MAX_Msk (0x40000UL)    /*!< CLAMP_VDD_WKUP_MAX (Bitfield-Mask: 0x01)              */
-#define CRG_TOP_PMU_SLEEP_REG_ULTRA_FAST_WAKEUP_Pos (17UL)          /*!< ULTRA_FAST_WAKEUP (Bit 17)                            */
-#define CRG_TOP_PMU_SLEEP_REG_ULTRA_FAST_WAKEUP_Msk (0x20000UL)     /*!< ULTRA_FAST_WAKEUP (Bitfield-Mask: 0x01)               */
-#define CRG_TOP_PMU_SLEEP_REG_FAST_WAKEUP_Pos (16UL)                /*!< FAST_WAKEUP (Bit 16)                                  */
-#define CRG_TOP_PMU_SLEEP_REG_FAST_WAKEUP_Msk (0x10000UL)           /*!< FAST_WAKEUP (Bitfield-Mask: 0x01)                     */
-#define CRG_TOP_PMU_SLEEP_REG_BOD_SLEEP_INTERVAL_Pos (12UL)         /*!< BOD_SLEEP_INTERVAL (Bit 12)                           */
-#define CRG_TOP_PMU_SLEEP_REG_BOD_SLEEP_INTERVAL_Msk (0xf000UL)     /*!< BOD_SLEEP_INTERVAL (Bitfield-Mask: 0x0f)              */
-#define CRG_TOP_PMU_SLEEP_REG_BG_REFRESH_INTERVAL_Pos (0UL)         /*!< BG_REFRESH_INTERVAL (Bit 0)                           */
-#define CRG_TOP_PMU_SLEEP_REG_BG_REFRESH_INTERVAL_Msk (0xfffUL)     /*!< BG_REFRESH_INTERVAL (Bitfield-Mask: 0xfff)            */
-/* =====================================================  PMU_TRIM_REG  ====================================================== */
-#define CRG_TOP_PMU_TRIM_REG_LDO_1V8_TRIM_Pos (12UL)                /*!< LDO_1V8_TRIM (Bit 12)                                 */
-#define CRG_TOP_PMU_TRIM_REG_LDO_1V8_TRIM_Msk (0xf000UL)            /*!< LDO_1V8_TRIM (Bitfield-Mask: 0x0f)                    */
-#define CRG_TOP_PMU_TRIM_REG_LDO_1V8P_TRIM_Pos (8UL)                /*!< LDO_1V8P_TRIM (Bit 8)                                 */
-#define CRG_TOP_PMU_TRIM_REG_LDO_1V8P_TRIM_Msk (0xf00UL)            /*!< LDO_1V8P_TRIM (Bitfield-Mask: 0x0f)                   */
-#define CRG_TOP_PMU_TRIM_REG_LDO_SUPPLY_VBAT_TRIM_Pos (4UL)         /*!< LDO_SUPPLY_VBAT_TRIM (Bit 4)                          */
-#define CRG_TOP_PMU_TRIM_REG_LDO_SUPPLY_VBAT_TRIM_Msk (0xf0UL)      /*!< LDO_SUPPLY_VBAT_TRIM (Bitfield-Mask: 0x0f)            */
-#define CRG_TOP_PMU_TRIM_REG_LDO_SUPPLY_VBUS_TRIM_Pos (0UL)         /*!< LDO_SUPPLY_VBUS_TRIM (Bit 0)                          */
-#define CRG_TOP_PMU_TRIM_REG_LDO_SUPPLY_VBUS_TRIM_Msk (0xfUL)       /*!< LDO_SUPPLY_VBUS_TRIM (Bitfield-Mask: 0x0f)            */
-/* ======================================================  POR_PIN_REG  ====================================================== */
-#define CRG_TOP_POR_PIN_REG_POR_PIN_POLARITY_Pos (7UL)              /*!< POR_PIN_POLARITY (Bit 7)                              */
-#define CRG_TOP_POR_PIN_REG_POR_PIN_POLARITY_Msk (0x80UL)           /*!< POR_PIN_POLARITY (Bitfield-Mask: 0x01)                */
-#define CRG_TOP_POR_PIN_REG_POR_PIN_SELECT_Pos (0UL)                /*!< POR_PIN_SELECT (Bit 0)                                */
-#define CRG_TOP_POR_PIN_REG_POR_PIN_SELECT_Msk (0x3fUL)             /*!< POR_PIN_SELECT (Bitfield-Mask: 0x3f)                  */
-/* =====================================================  POR_TIMER_REG  ===================================================== */
-#define CRG_TOP_POR_TIMER_REG_POR_TIME_Pos (0UL)                    /*!< POR_TIME (Bit 0)                                      */
-#define CRG_TOP_POR_TIMER_REG_POR_TIME_Msk (0x7fUL)                 /*!< POR_TIME (Bitfield-Mask: 0x7f)                        */
-/* ===================================================  POR_VBAT_CTRL_REG  =================================================== */
-#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_MASK_N_Pos (13UL)        /*!< POR_VBAT_MASK_N (Bit 13)                              */
-#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_MASK_N_Msk (0x2000UL)    /*!< POR_VBAT_MASK_N (Bitfield-Mask: 0x01)                 */
-#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_ENABLE_Pos (12UL)        /*!< POR_VBAT_ENABLE (Bit 12)                              */
-#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_ENABLE_Msk (0x1000UL)    /*!< POR_VBAT_ENABLE (Bitfield-Mask: 0x01)                 */
-#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_HYST_LOW_Pos (8UL)       /*!< POR_VBAT_HYST_LOW (Bit 8)                             */
-#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_HYST_LOW_Msk (0xf00UL)   /*!< POR_VBAT_HYST_LOW (Bitfield-Mask: 0x0f)               */
-#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_HIGH_Pos (4UL)     /*!< POR_VBAT_THRES_HIGH (Bit 4)                           */
-#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_HIGH_Msk (0xf0UL)  /*!< POR_VBAT_THRES_HIGH (Bitfield-Mask: 0x0f)             */
-#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_LOW_Pos (0UL)      /*!< POR_VBAT_THRES_LOW (Bit 0)                            */
-#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_LOW_Msk (0xfUL)    /*!< POR_VBAT_THRES_LOW (Bitfield-Mask: 0x0f)              */
-/* ====================================================  POWER_CTRL_REG  ===================================================== */
-#define CRG_TOP_POWER_CTRL_REG_VDD_SLEEP_LEVEL_Pos (29UL)           /*!< VDD_SLEEP_LEVEL (Bit 29)                              */
-#define CRG_TOP_POWER_CTRL_REG_VDD_SLEEP_LEVEL_Msk (0xe0000000UL)   /*!< VDD_SLEEP_LEVEL (Bitfield-Mask: 0x07)                 */
-#define CRG_TOP_POWER_CTRL_REG_VDD_CLAMP_LEVEL_Pos (25UL)           /*!< VDD_CLAMP_LEVEL (Bit 25)                              */
-#define CRG_TOP_POWER_CTRL_REG_VDD_CLAMP_LEVEL_Msk (0x1e000000UL)   /*!< VDD_CLAMP_LEVEL (Bitfield-Mask: 0x0f)                 */
-#define CRG_TOP_POWER_CTRL_REG_CLAMP_3V0_VBAT_ENABLE_Pos (24UL)     /*!< CLAMP_3V0_VBAT_ENABLE (Bit 24)                        */
-#define CRG_TOP_POWER_CTRL_REG_CLAMP_3V0_VBAT_ENABLE_Msk (0x1000000UL) /*!< CLAMP_3V0_VBAT_ENABLE (Bitfield-Mask: 0x01)        */
-#define CRG_TOP_POWER_CTRL_REG_V18_LEVEL_Pos (23UL)                 /*!< V18_LEVEL (Bit 23)                                    */
-#define CRG_TOP_POWER_CTRL_REG_V18_LEVEL_Msk (0x800000UL)           /*!< V18_LEVEL (Bitfield-Mask: 0x01)                       */
-#define CRG_TOP_POWER_CTRL_REG_V14_LEVEL_Pos (20UL)                 /*!< V14_LEVEL (Bit 20)                                    */
-#define CRG_TOP_POWER_CTRL_REG_V14_LEVEL_Msk (0x700000UL)           /*!< V14_LEVEL (Bitfield-Mask: 0x07)                       */
-#define CRG_TOP_POWER_CTRL_REG_V30_LEVEL_Pos (18UL)                 /*!< V30_LEVEL (Bit 18)                                    */
-#define CRG_TOP_POWER_CTRL_REG_V30_LEVEL_Msk (0xc0000UL)            /*!< V30_LEVEL (Bitfield-Mask: 0x03)                       */
-#define CRG_TOP_POWER_CTRL_REG_VDD_LEVEL_Pos (16UL)                 /*!< VDD_LEVEL (Bit 16)                                    */
-#define CRG_TOP_POWER_CTRL_REG_VDD_LEVEL_Msk (0x30000UL)            /*!< VDD_LEVEL (Bitfield-Mask: 0x03)                       */
-#define CRG_TOP_POWER_CTRL_REG_LDO_3V0_REF_Pos (15UL)               /*!< LDO_3V0_REF (Bit 15)                                  */
-#define CRG_TOP_POWER_CTRL_REG_LDO_3V0_REF_Msk (0x8000UL)           /*!< LDO_3V0_REF (Bitfield-Mask: 0x01)                     */
-#define CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_SLEEP_Pos (14UL) /*!< LDO_CORE_RET_ENABLE_SLEEP (Bit 14)                    */
-#define CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_SLEEP_Msk (0x4000UL) /*!< LDO_CORE_RET_ENABLE_SLEEP (Bitfield-Mask: 0x01)   */
-#define CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_ACTIVE_Pos (13UL) /*!< LDO_CORE_RET_ENABLE_ACTIVE (Bit 13)                  */
-#define CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_ACTIVE_Msk (0x2000UL) /*!< LDO_CORE_RET_ENABLE_ACTIVE (Bitfield-Mask: 0x01) */
-#define CRG_TOP_POWER_CTRL_REG_LDO_CORE_ENABLE_Pos (12UL)           /*!< LDO_CORE_ENABLE (Bit 12)                              */
-#define CRG_TOP_POWER_CTRL_REG_LDO_CORE_ENABLE_Msk (0x1000UL)       /*!< LDO_CORE_ENABLE (Bitfield-Mask: 0x01)                 */
-#define CRG_TOP_POWER_CTRL_REG_LDO_3V0_RET_ENABLE_SLEEP_Pos (11UL)  /*!< LDO_3V0_RET_ENABLE_SLEEP (Bit 11)                     */
-#define CRG_TOP_POWER_CTRL_REG_LDO_3V0_RET_ENABLE_SLEEP_Msk (0x800UL) /*!< LDO_3V0_RET_ENABLE_SLEEP (Bitfield-Mask: 0x01)      */
-#define CRG_TOP_POWER_CTRL_REG_LDO_3V0_RET_ENABLE_ACTIVE_Pos (10UL) /*!< LDO_3V0_RET_ENABLE_ACTIVE (Bit 10)                    */
-#define CRG_TOP_POWER_CTRL_REG_LDO_3V0_RET_ENABLE_ACTIVE_Msk (0x400UL) /*!< LDO_3V0_RET_ENABLE_ACTIVE (Bitfield-Mask: 0x01)    */
-#define CRG_TOP_POWER_CTRL_REG_LDO_3V0_MODE_Pos (8UL)               /*!< LDO_3V0_MODE (Bit 8)                                  */
-#define CRG_TOP_POWER_CTRL_REG_LDO_3V0_MODE_Msk (0x300UL)           /*!< LDO_3V0_MODE (Bitfield-Mask: 0x03)                    */
-#define CRG_TOP_POWER_CTRL_REG_LDO_RADIO_ENABLE_Pos (7UL)           /*!< LDO_RADIO_ENABLE (Bit 7)                              */
-#define CRG_TOP_POWER_CTRL_REG_LDO_RADIO_ENABLE_Msk (0x80UL)        /*!< LDO_RADIO_ENABLE (Bitfield-Mask: 0x01)                */
-#define CRG_TOP_POWER_CTRL_REG_LDO_1V8_RET_ENABLE_SLEEP_Pos (6UL)   /*!< LDO_1V8_RET_ENABLE_SLEEP (Bit 6)                      */
-#define CRG_TOP_POWER_CTRL_REG_LDO_1V8_RET_ENABLE_SLEEP_Msk (0x40UL) /*!< LDO_1V8_RET_ENABLE_SLEEP (Bitfield-Mask: 0x01)       */
-#define CRG_TOP_POWER_CTRL_REG_LDO_1V8_RET_ENABLE_ACTIVE_Pos (5UL)  /*!< LDO_1V8_RET_ENABLE_ACTIVE (Bit 5)                     */
-#define CRG_TOP_POWER_CTRL_REG_LDO_1V8_RET_ENABLE_ACTIVE_Msk (0x20UL) /*!< LDO_1V8_RET_ENABLE_ACTIVE (Bitfield-Mask: 0x01)     */
-#define CRG_TOP_POWER_CTRL_REG_LDO_1V8_ENABLE_Pos (4UL)             /*!< LDO_1V8_ENABLE (Bit 4)                                */
-#define CRG_TOP_POWER_CTRL_REG_LDO_1V8_ENABLE_Msk (0x10UL)          /*!< LDO_1V8_ENABLE (Bitfield-Mask: 0x01)                  */
-#define CRG_TOP_POWER_CTRL_REG_SW_1V8F_ENABLE_FORCE_Pos (3UL)       /*!< SW_1V8F_ENABLE_FORCE (Bit 3)                          */
-#define CRG_TOP_POWER_CTRL_REG_SW_1V8F_ENABLE_FORCE_Msk (0x8UL)     /*!< SW_1V8F_ENABLE_FORCE (Bitfield-Mask: 0x01)            */
-#define CRG_TOP_POWER_CTRL_REG_LDO_1V8P_RET_ENABLE_SLEEP_Pos (2UL)  /*!< LDO_1V8P_RET_ENABLE_SLEEP (Bit 2)                     */
-#define CRG_TOP_POWER_CTRL_REG_LDO_1V8P_RET_ENABLE_SLEEP_Msk (0x4UL) /*!< LDO_1V8P_RET_ENABLE_SLEEP (Bitfield-Mask: 0x01)      */
-#define CRG_TOP_POWER_CTRL_REG_LDO_1V8P_RET_ENABLE_ACTIVE_Pos (1UL) /*!< LDO_1V8P_RET_ENABLE_ACTIVE (Bit 1)                    */
-#define CRG_TOP_POWER_CTRL_REG_LDO_1V8P_RET_ENABLE_ACTIVE_Msk (0x2UL) /*!< LDO_1V8P_RET_ENABLE_ACTIVE (Bitfield-Mask: 0x01)    */
-#define CRG_TOP_POWER_CTRL_REG_LDO_1V8P_ENABLE_Pos (0UL)            /*!< LDO_1V8P_ENABLE (Bit 0)                               */
-#define CRG_TOP_POWER_CTRL_REG_LDO_1V8P_ENABLE_Msk (0x1UL)          /*!< LDO_1V8P_ENABLE (Bitfield-Mask: 0x01)                 */
-/* ===================================================  RAM_PWR_CTRL_REG  ==================================================== */
-#define CRG_TOP_RAM_PWR_CTRL_REG_RAM8_PWR_CTRL_Pos (14UL)           /*!< RAM8_PWR_CTRL (Bit 14)                                */
-#define CRG_TOP_RAM_PWR_CTRL_REG_RAM8_PWR_CTRL_Msk (0xc000UL)       /*!< RAM8_PWR_CTRL (Bitfield-Mask: 0x03)                   */
-#define CRG_TOP_RAM_PWR_CTRL_REG_RAM7_PWR_CTRL_Pos (12UL)           /*!< RAM7_PWR_CTRL (Bit 12)                                */
-#define CRG_TOP_RAM_PWR_CTRL_REG_RAM7_PWR_CTRL_Msk (0x3000UL)       /*!< RAM7_PWR_CTRL (Bitfield-Mask: 0x03)                   */
-#define CRG_TOP_RAM_PWR_CTRL_REG_RAM6_PWR_CTRL_Pos (10UL)           /*!< RAM6_PWR_CTRL (Bit 10)                                */
-#define CRG_TOP_RAM_PWR_CTRL_REG_RAM6_PWR_CTRL_Msk (0xc00UL)        /*!< RAM6_PWR_CTRL (Bitfield-Mask: 0x03)                   */
-#define CRG_TOP_RAM_PWR_CTRL_REG_RAM5_PWR_CTRL_Pos (8UL)            /*!< RAM5_PWR_CTRL (Bit 8)                                 */
-#define CRG_TOP_RAM_PWR_CTRL_REG_RAM5_PWR_CTRL_Msk (0x300UL)        /*!< RAM5_PWR_CTRL (Bitfield-Mask: 0x03)                   */
-#define CRG_TOP_RAM_PWR_CTRL_REG_RAM4_PWR_CTRL_Pos (6UL)            /*!< RAM4_PWR_CTRL (Bit 6)                                 */
-#define CRG_TOP_RAM_PWR_CTRL_REG_RAM4_PWR_CTRL_Msk (0xc0UL)         /*!< RAM4_PWR_CTRL (Bitfield-Mask: 0x03)                   */
-#define CRG_TOP_RAM_PWR_CTRL_REG_RAM3_PWR_CTRL_Pos (4UL)            /*!< RAM3_PWR_CTRL (Bit 4)                                 */
-#define CRG_TOP_RAM_PWR_CTRL_REG_RAM3_PWR_CTRL_Msk (0x30UL)         /*!< RAM3_PWR_CTRL (Bitfield-Mask: 0x03)                   */
-#define CRG_TOP_RAM_PWR_CTRL_REG_RAM2_PWR_CTRL_Pos (2UL)            /*!< RAM2_PWR_CTRL (Bit 2)                                 */
-#define CRG_TOP_RAM_PWR_CTRL_REG_RAM2_PWR_CTRL_Msk (0xcUL)          /*!< RAM2_PWR_CTRL (Bitfield-Mask: 0x03)                   */
-#define CRG_TOP_RAM_PWR_CTRL_REG_RAM1_PWR_CTRL_Pos (0UL)            /*!< RAM1_PWR_CTRL (Bit 0)                                 */
-#define CRG_TOP_RAM_PWR_CTRL_REG_RAM1_PWR_CTRL_Msk (0x3UL)          /*!< RAM1_PWR_CTRL (Bitfield-Mask: 0x03)                   */
-/* ====================================================  RESET_STAT_REG  ===================================================== */
-#define CRG_TOP_RESET_STAT_REG_CMAC_WDOGRESET_STAT_Pos (5UL)        /*!< CMAC_WDOGRESET_STAT (Bit 5)                           */
-#define CRG_TOP_RESET_STAT_REG_CMAC_WDOGRESET_STAT_Msk (0x20UL)     /*!< CMAC_WDOGRESET_STAT (Bitfield-Mask: 0x01)             */
-#define CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Pos (4UL)           /*!< SWD_HWRESET_STAT (Bit 4)                              */
-#define CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Msk (0x10UL)        /*!< SWD_HWRESET_STAT (Bitfield-Mask: 0x01)                */
-#define CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Pos (3UL)             /*!< WDOGRESET_STAT (Bit 3)                                */
-#define CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Msk (0x8UL)           /*!< WDOGRESET_STAT (Bitfield-Mask: 0x01)                  */
-#define CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Pos (2UL)               /*!< SWRESET_STAT (Bit 2)                                  */
-#define CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Msk (0x4UL)             /*!< SWRESET_STAT (Bitfield-Mask: 0x01)                    */
-#define CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Pos (1UL)               /*!< HWRESET_STAT (Bit 1)                                  */
-#define CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Msk (0x2UL)             /*!< HWRESET_STAT (Bitfield-Mask: 0x01)                    */
-#define CRG_TOP_RESET_STAT_REG_PORESET_STAT_Pos (0UL)               /*!< PORESET_STAT (Bit 0)                                  */
-#define CRG_TOP_RESET_STAT_REG_PORESET_STAT_Msk (0x1UL)             /*!< PORESET_STAT (Bitfield-Mask: 0x01)                    */
-/* ====================================================  SECURE_BOOT_REG  ==================================================== */
-#define CRG_TOP_SECURE_BOOT_REG_PROT_QSPI_KEY_READ_Pos (7UL)        /*!< PROT_QSPI_KEY_READ (Bit 7)                            */
-#define CRG_TOP_SECURE_BOOT_REG_PROT_QSPI_KEY_READ_Msk (0x80UL)     /*!< PROT_QSPI_KEY_READ (Bitfield-Mask: 0x01)              */
-#define CRG_TOP_SECURE_BOOT_REG_PROT_QSPI_KEY_WRITE_Pos (6UL)       /*!< PROT_QSPI_KEY_WRITE (Bit 6)                           */
-#define CRG_TOP_SECURE_BOOT_REG_PROT_QSPI_KEY_WRITE_Msk (0x40UL)    /*!< PROT_QSPI_KEY_WRITE (Bitfield-Mask: 0x01)             */
-#define CRG_TOP_SECURE_BOOT_REG_PROT_AES_KEY_READ_Pos (5UL)         /*!< PROT_AES_KEY_READ (Bit 5)                             */
-#define CRG_TOP_SECURE_BOOT_REG_PROT_AES_KEY_READ_Msk (0x20UL)      /*!< PROT_AES_KEY_READ (Bitfield-Mask: 0x01)               */
-#define CRG_TOP_SECURE_BOOT_REG_PROT_AES_KEY_WRITE_Pos (4UL)        /*!< PROT_AES_KEY_WRITE (Bit 4)                            */
-#define CRG_TOP_SECURE_BOOT_REG_PROT_AES_KEY_WRITE_Msk (0x10UL)     /*!< PROT_AES_KEY_WRITE (Bitfield-Mask: 0x01)              */
-#define CRG_TOP_SECURE_BOOT_REG_PROT_SIG_KEY_WRITE_Pos (3UL)        /*!< PROT_SIG_KEY_WRITE (Bit 3)                            */
-#define CRG_TOP_SECURE_BOOT_REG_PROT_SIG_KEY_WRITE_Msk (0x8UL)      /*!< PROT_SIG_KEY_WRITE (Bitfield-Mask: 0x01)              */
-#define CRG_TOP_SECURE_BOOT_REG_FORCE_CMAC_DEBUGGER_OFF_Pos (2UL)   /*!< FORCE_CMAC_DEBUGGER_OFF (Bit 2)                       */
-#define CRG_TOP_SECURE_BOOT_REG_FORCE_CMAC_DEBUGGER_OFF_Msk (0x4UL) /*!< FORCE_CMAC_DEBUGGER_OFF (Bitfield-Mask: 0x01)         */
-#define CRG_TOP_SECURE_BOOT_REG_FORCE_DEBUGGER_OFF_Pos (1UL)        /*!< FORCE_DEBUGGER_OFF (Bit 1)                            */
-#define CRG_TOP_SECURE_BOOT_REG_FORCE_DEBUGGER_OFF_Msk (0x2UL)      /*!< FORCE_DEBUGGER_OFF (Bitfield-Mask: 0x01)              */
-#define CRG_TOP_SECURE_BOOT_REG_SECURE_BOOT_Pos (0UL)               /*!< SECURE_BOOT (Bit 0)                                   */
-#define CRG_TOP_SECURE_BOOT_REG_SECURE_BOOT_Msk (0x1UL)             /*!< SECURE_BOOT (Bitfield-Mask: 0x01)                     */
-/* =====================================================  SYS_CTRL_REG  ====================================================== */
-#define CRG_TOP_SYS_CTRL_REG_SW_RESET_Pos (15UL)                    /*!< SW_RESET (Bit 15)                                     */
-#define CRG_TOP_SYS_CTRL_REG_SW_RESET_Msk (0x8000UL)                /*!< SW_RESET (Bitfield-Mask: 0x01)                        */
-#define CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Pos (10UL)                /*!< CACHERAM_MUX (Bit 10)                                 */
-#define CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Msk (0x400UL)             /*!< CACHERAM_MUX (Bitfield-Mask: 0x01)                    */
-#define CRG_TOP_SYS_CTRL_REG_TIMEOUT_DISABLE_Pos (9UL)              /*!< TIMEOUT_DISABLE (Bit 9)                               */
-#define CRG_TOP_SYS_CTRL_REG_TIMEOUT_DISABLE_Msk (0x200UL)          /*!< TIMEOUT_DISABLE (Bitfield-Mask: 0x01)                 */
-#define CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Pos (7UL)              /*!< DEBUGGER_ENABLE (Bit 7)                               */
-#define CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Msk (0x80UL)           /*!< DEBUGGER_ENABLE (Bitfield-Mask: 0x01)                 */
-#define CRG_TOP_SYS_CTRL_REG_QSPI_INIT_Pos (4UL)                    /*!< QSPI_INIT (Bit 4)                                     */
-#define CRG_TOP_SYS_CTRL_REG_QSPI_INIT_Msk (0x10UL)                 /*!< QSPI_INIT (Bitfield-Mask: 0x01)                       */
-#define CRG_TOP_SYS_CTRL_REG_REMAP_INTVECT_Pos (3UL)                /*!< REMAP_INTVECT (Bit 3)                                 */
-#define CRG_TOP_SYS_CTRL_REG_REMAP_INTVECT_Msk (0x8UL)              /*!< REMAP_INTVECT (Bitfield-Mask: 0x01)                   */
-#define CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Pos (0UL)                   /*!< REMAP_ADR0 (Bit 0)                                    */
-#define CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Msk (0x7UL)                 /*!< REMAP_ADR0 (Bitfield-Mask: 0x07)                      */
-/* =====================================================  SYS_STAT_REG  ====================================================== */
-#define CRG_TOP_SYS_STAT_REG_POWER_IS_UP_Pos (13UL)                 /*!< POWER_IS_UP (Bit 13)                                  */
-#define CRG_TOP_SYS_STAT_REG_POWER_IS_UP_Msk (0x2000UL)             /*!< POWER_IS_UP (Bitfield-Mask: 0x01)                     */
-#define CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Pos (12UL)               /*!< DBG_IS_ACTIVE (Bit 12)                                */
-#define CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Msk (0x1000UL)           /*!< DBG_IS_ACTIVE (Bitfield-Mask: 0x01)                   */
-#define CRG_TOP_SYS_STAT_REG_COM_IS_UP_Pos (11UL)                   /*!< COM_IS_UP (Bit 11)                                    */
-#define CRG_TOP_SYS_STAT_REG_COM_IS_UP_Msk (0x800UL)                /*!< COM_IS_UP (Bitfield-Mask: 0x01)                       */
-#define CRG_TOP_SYS_STAT_REG_COM_IS_DOWN_Pos (10UL)                 /*!< COM_IS_DOWN (Bit 10)                                  */
-#define CRG_TOP_SYS_STAT_REG_COM_IS_DOWN_Msk (0x400UL)              /*!< COM_IS_DOWN (Bitfield-Mask: 0x01)                     */
-#define CRG_TOP_SYS_STAT_REG_TIM_IS_UP_Pos (9UL)                    /*!< TIM_IS_UP (Bit 9)                                     */
-#define CRG_TOP_SYS_STAT_REG_TIM_IS_UP_Msk (0x200UL)                /*!< TIM_IS_UP (Bitfield-Mask: 0x01)                       */
-#define CRG_TOP_SYS_STAT_REG_TIM_IS_DOWN_Pos (8UL)                  /*!< TIM_IS_DOWN (Bit 8)                                   */
-#define CRG_TOP_SYS_STAT_REG_TIM_IS_DOWN_Msk (0x100UL)              /*!< TIM_IS_DOWN (Bitfield-Mask: 0x01)                     */
-#define CRG_TOP_SYS_STAT_REG_MEM_IS_UP_Pos (7UL)                    /*!< MEM_IS_UP (Bit 7)                                     */
-#define CRG_TOP_SYS_STAT_REG_MEM_IS_UP_Msk (0x80UL)                 /*!< MEM_IS_UP (Bitfield-Mask: 0x01)                       */
-#define CRG_TOP_SYS_STAT_REG_MEM_IS_DOWN_Pos (6UL)                  /*!< MEM_IS_DOWN (Bit 6)                                   */
-#define CRG_TOP_SYS_STAT_REG_MEM_IS_DOWN_Msk (0x40UL)               /*!< MEM_IS_DOWN (Bitfield-Mask: 0x01)                     */
-#define CRG_TOP_SYS_STAT_REG_SYS_IS_UP_Pos (5UL)                    /*!< SYS_IS_UP (Bit 5)                                     */
-#define CRG_TOP_SYS_STAT_REG_SYS_IS_UP_Msk (0x20UL)                 /*!< SYS_IS_UP (Bitfield-Mask: 0x01)                       */
-#define CRG_TOP_SYS_STAT_REG_SYS_IS_DOWN_Pos (4UL)                  /*!< SYS_IS_DOWN (Bit 4)                                   */
-#define CRG_TOP_SYS_STAT_REG_SYS_IS_DOWN_Msk (0x10UL)               /*!< SYS_IS_DOWN (Bitfield-Mask: 0x01)                     */
-#define CRG_TOP_SYS_STAT_REG_PER_IS_UP_Pos (3UL)                    /*!< PER_IS_UP (Bit 3)                                     */
-#define CRG_TOP_SYS_STAT_REG_PER_IS_UP_Msk (0x8UL)                  /*!< PER_IS_UP (Bitfield-Mask: 0x01)                       */
-#define CRG_TOP_SYS_STAT_REG_PER_IS_DOWN_Pos (2UL)                  /*!< PER_IS_DOWN (Bit 2)                                   */
-#define CRG_TOP_SYS_STAT_REG_PER_IS_DOWN_Msk (0x4UL)                /*!< PER_IS_DOWN (Bitfield-Mask: 0x01)                     */
-#define CRG_TOP_SYS_STAT_REG_RAD_IS_UP_Pos (1UL)                    /*!< RAD_IS_UP (Bit 1)                                     */
-#define CRG_TOP_SYS_STAT_REG_RAD_IS_UP_Msk (0x2UL)                  /*!< RAD_IS_UP (Bitfield-Mask: 0x01)                       */
-#define CRG_TOP_SYS_STAT_REG_RAD_IS_DOWN_Pos (0UL)                  /*!< RAD_IS_DOWN (Bit 0)                                   */
-#define CRG_TOP_SYS_STAT_REG_RAD_IS_DOWN_Msk (0x1UL)                /*!< RAD_IS_DOWN (Bitfield-Mask: 0x01)                     */
-/* ==================================================  VBUS_IRQ_CLEAR_REG  =================================================== */
-#define CRG_TOP_VBUS_IRQ_CLEAR_REG_VBUS_IRQ_CLEAR_Pos (0UL)         /*!< VBUS_IRQ_CLEAR (Bit 0)                                */
-#define CRG_TOP_VBUS_IRQ_CLEAR_REG_VBUS_IRQ_CLEAR_Msk (0xffffUL)    /*!< VBUS_IRQ_CLEAR (Bitfield-Mask: 0xffff)                */
-/* ===================================================  VBUS_IRQ_MASK_REG  =================================================== */
-#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_RISE_Pos (1UL)        /*!< VBUS_IRQ_EN_RISE (Bit 1)                              */
-#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_RISE_Msk (0x2UL)      /*!< VBUS_IRQ_EN_RISE (Bitfield-Mask: 0x01)                */
-#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_FALL_Pos (0UL)        /*!< VBUS_IRQ_EN_FALL (Bit 0)                              */
-#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_FALL_Msk (0x1UL)      /*!< VBUS_IRQ_EN_FALL (Bitfield-Mask: 0x01)                */
-
-
-/* =========================================================================================================================== */
-/* ================                                         CRG_XTAL                                          ================ */
-/* =========================================================================================================================== */
-
-/* ===================================================  CLK_FREQ_TRIM_REG  =================================================== */
-#define CRG_XTAL_CLK_FREQ_TRIM_REG_XTAL32M_START_Pos (20UL)         /*!< XTAL32M_START (Bit 20)                                */
-#define CRG_XTAL_CLK_FREQ_TRIM_REG_XTAL32M_START_Msk (0x3ff00000UL) /*!< XTAL32M_START (Bitfield-Mask: 0x3ff)                  */
-#define CRG_XTAL_CLK_FREQ_TRIM_REG_XTAL32M_RAMP_Pos (10UL)          /*!< XTAL32M_RAMP (Bit 10)                                 */
-#define CRG_XTAL_CLK_FREQ_TRIM_REG_XTAL32M_RAMP_Msk (0xffc00UL)     /*!< XTAL32M_RAMP (Bitfield-Mask: 0x3ff)                   */
-#define CRG_XTAL_CLK_FREQ_TRIM_REG_XTAL32M_TRIM_Pos (0UL)           /*!< XTAL32M_TRIM (Bit 0)                                  */
-#define CRG_XTAL_CLK_FREQ_TRIM_REG_XTAL32M_TRIM_Msk (0x3ffUL)       /*!< XTAL32M_TRIM (Bitfield-Mask: 0x3ff)                   */
-/* ===================================================  PLL_SYS_CTRL1_REG  =================================================== */
-#define CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_SEL_MIN_CUR_INT_Pos (14UL)   /*!< PLL_SEL_MIN_CUR_INT (Bit 14)                          */
-#define CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_SEL_MIN_CUR_INT_Msk (0x4000UL) /*!< PLL_SEL_MIN_CUR_INT (Bitfield-Mask: 0x01)           */
-#define CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_PRE_DIV_Pos (11UL)           /*!< PLL_PRE_DIV (Bit 11)                                  */
-#define CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_PRE_DIV_Msk (0x800UL)        /*!< PLL_PRE_DIV (Bitfield-Mask: 0x01)                     */
-#define CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_N_DIV_Pos (4UL)              /*!< PLL_N_DIV (Bit 4)                                     */
-#define CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_N_DIV_Msk (0x7f0UL)          /*!< PLL_N_DIV (Bitfield-Mask: 0x7f)                       */
-#define CRG_XTAL_PLL_SYS_CTRL1_REG_LDO_PLL_VREF_HOLD_Pos (3UL)      /*!< LDO_PLL_VREF_HOLD (Bit 3)                             */
-#define CRG_XTAL_PLL_SYS_CTRL1_REG_LDO_PLL_VREF_HOLD_Msk (0x8UL)    /*!< LDO_PLL_VREF_HOLD (Bitfield-Mask: 0x01)               */
-#define CRG_XTAL_PLL_SYS_CTRL1_REG_LDO_PLL_ENABLE_Pos (2UL)         /*!< LDO_PLL_ENABLE (Bit 2)                                */
-#define CRG_XTAL_PLL_SYS_CTRL1_REG_LDO_PLL_ENABLE_Msk (0x4UL)       /*!< LDO_PLL_ENABLE (Bitfield-Mask: 0x01)                  */
-#define CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_EN_Pos (1UL)                 /*!< PLL_EN (Bit 1)                                        */
-#define CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_EN_Msk (0x2UL)               /*!< PLL_EN (Bitfield-Mask: 0x01)                          */
-/* ===================================================  PLL_SYS_CTRL2_REG  =================================================== */
-#define CRG_XTAL_PLL_SYS_CTRL2_REG_PLL_RECALIB_Pos (15UL)           /*!< PLL_RECALIB (Bit 15)                                  */
-#define CRG_XTAL_PLL_SYS_CTRL2_REG_PLL_RECALIB_Msk (0x8000UL)       /*!< PLL_RECALIB (Bitfield-Mask: 0x01)                     */
-/* ===================================================  PLL_SYS_CTRL3_REG  =================================================== */
-#define CRG_XTAL_PLL_SYS_CTRL3_REG_PLL_TEST_VCTR_Pos (7UL)          /*!< PLL_TEST_VCTR (Bit 7)                                 */
-#define CRG_XTAL_PLL_SYS_CTRL3_REG_PLL_TEST_VCTR_Msk (0x80UL)       /*!< PLL_TEST_VCTR (Bitfield-Mask: 0x01)                   */
-#define CRG_XTAL_PLL_SYS_CTRL3_REG_PLL_MIN_CURRENT_Pos (1UL)        /*!< PLL_MIN_CURRENT (Bit 1)                               */
-#define CRG_XTAL_PLL_SYS_CTRL3_REG_PLL_MIN_CURRENT_Msk (0x7eUL)     /*!< PLL_MIN_CURRENT (Bitfield-Mask: 0x3f)                 */
-/* ==================================================  PLL_SYS_STATUS_REG  =================================================== */
-#define CRG_XTAL_PLL_SYS_STATUS_REG_LDO_PLL_OK_Pos (15UL)           /*!< LDO_PLL_OK (Bit 15)                                   */
-#define CRG_XTAL_PLL_SYS_STATUS_REG_LDO_PLL_OK_Msk (0x8000UL)       /*!< LDO_PLL_OK (Bitfield-Mask: 0x01)                      */
-#define CRG_XTAL_PLL_SYS_STATUS_REG_PLL_CALIBRATION_END_Pos (11UL)  /*!< PLL_CALIBRATION_END (Bit 11)                          */
-#define CRG_XTAL_PLL_SYS_STATUS_REG_PLL_CALIBRATION_END_Msk (0x800UL) /*!< PLL_CALIBRATION_END (Bitfield-Mask: 0x01)           */
-#define CRG_XTAL_PLL_SYS_STATUS_REG_PLL_BEST_MIN_CUR_Pos (5UL)      /*!< PLL_BEST_MIN_CUR (Bit 5)                              */
-#define CRG_XTAL_PLL_SYS_STATUS_REG_PLL_BEST_MIN_CUR_Msk (0x7e0UL)  /*!< PLL_BEST_MIN_CUR (Bitfield-Mask: 0x3f)                */
-#define CRG_XTAL_PLL_SYS_STATUS_REG_PLL_LOCK_FINE_Pos (0UL)         /*!< PLL_LOCK_FINE (Bit 0)                                 */
-#define CRG_XTAL_PLL_SYS_STATUS_REG_PLL_LOCK_FINE_Msk (0x1UL)       /*!< PLL_LOCK_FINE (Bitfield-Mask: 0x01)                   */
-/* =====================================================  TRIM_CTRL_REG  ===================================================== */
-#define CRG_XTAL_TRIM_CTRL_REG_XTAL_SETTLE_N_Pos (8UL)              /*!< XTAL_SETTLE_N (Bit 8)                                 */
-#define CRG_XTAL_TRIM_CTRL_REG_XTAL_SETTLE_N_Msk (0x3f00UL)         /*!< XTAL_SETTLE_N (Bitfield-Mask: 0x3f)                   */
-#define CRG_XTAL_TRIM_CTRL_REG_XTAL_TRIM_SELECT_Pos (6UL)           /*!< XTAL_TRIM_SELECT (Bit 6)                              */
-#define CRG_XTAL_TRIM_CTRL_REG_XTAL_TRIM_SELECT_Msk (0xc0UL)        /*!< XTAL_TRIM_SELECT (Bitfield-Mask: 0x03)                */
-#define CRG_XTAL_TRIM_CTRL_REG_XTAL_COUNT_N_Pos (0UL)               /*!< XTAL_COUNT_N (Bit 0)                                  */
-#define CRG_XTAL_TRIM_CTRL_REG_XTAL_COUNT_N_Msk (0x3fUL)            /*!< XTAL_COUNT_N (Bitfield-Mask: 0x3f)                    */
-/* ===================================================  XTAL32M_CTRL0_REG  =================================================== */
-#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_DXTAL_SYSPLL_ENABLE_Pos (30UL) /*!< XTAL32M_DXTAL_SYSPLL_ENABLE (Bit 30)            */
-#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_DXTAL_SYSPLL_ENABLE_Msk (0x40000000UL) /*!< XTAL32M_DXTAL_SYSPLL_ENABLE (Bitfield-Mask: 0x01) */
-#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_CORE_CUR_SET_Pos (15UL)  /*!< XTAL32M_CORE_CUR_SET (Bit 15)                         */
-#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_CORE_CUR_SET_Msk (0x38000UL) /*!< XTAL32M_CORE_CUR_SET (Bitfield-Mask: 0x07)        */
-#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_RCOSC_CALIBRATE_Pos (3UL) /*!< XTAL32M_RCOSC_CALIBRATE (Bit 3)                      */
-#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_RCOSC_CALIBRATE_Msk (0x8UL) /*!< XTAL32M_RCOSC_CALIBRATE (Bitfield-Mask: 0x01)      */
-#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_RCOSC_XTAL_DRIVE_Pos (1UL) /*!< XTAL32M_RCOSC_XTAL_DRIVE (Bit 1)                    */
-#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_RCOSC_XTAL_DRIVE_Msk (0x2UL) /*!< XTAL32M_RCOSC_XTAL_DRIVE (Bitfield-Mask: 0x01)    */
-#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_CXCOMP_ENABLE_Pos (0UL)  /*!< XTAL32M_CXCOMP_ENABLE (Bit 0)                         */
-#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_CXCOMP_ENABLE_Msk (0x1UL) /*!< XTAL32M_CXCOMP_ENABLE (Bitfield-Mask: 0x01)          */
-/* ===================================================  XTAL32M_CTRL1_REG  =================================================== */
-#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_STARTUP_TDISCHARGE_Pos (28UL) /*!< XTAL32M_STARTUP_TDISCHARGE (Bit 28)              */
-#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_STARTUP_TDISCHARGE_Msk (0x70000000UL) /*!< XTAL32M_STARTUP_TDISCHARGE (Bitfield-Mask: 0x07) */
-#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_STARTUP_TSETTLE_Pos (24UL) /*!< XTAL32M_STARTUP_TSETTLE (Bit 24)                    */
-#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_STARTUP_TSETTLE_Msk (0x7000000UL) /*!< XTAL32M_STARTUP_TSETTLE (Bitfield-Mask: 0x07) */
-#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_XTAL_ENABLE_Pos (23UL)   /*!< XTAL32M_XTAL_ENABLE (Bit 23)                          */
-#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_XTAL_ENABLE_Msk (0x800000UL) /*!< XTAL32M_XTAL_ENABLE (Bitfield-Mask: 0x01)         */
-#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_STARTUP_TDRIVE_LSB_Pos (13UL) /*!< XTAL32M_STARTUP_TDRIVE_LSB (Bit 13)              */
-#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_STARTUP_TDRIVE_LSB_Msk (0x7fe000UL) /*!< XTAL32M_STARTUP_TDRIVE_LSB (Bitfield-Mask: 0x3ff) */
-#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_DRIVE_CYCLES_Pos (8UL)   /*!< XTAL32M_DRIVE_CYCLES (Bit 8)                          */
-#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_DRIVE_CYCLES_Msk (0x1f00UL) /*!< XTAL32M_DRIVE_CYCLES (Bitfield-Mask: 0x1f)         */
-#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_STARTUP_TDRIVE_Pos (5UL) /*!< XTAL32M_STARTUP_TDRIVE (Bit 5)                        */
-#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_STARTUP_TDRIVE_Msk (0xe0UL) /*!< XTAL32M_STARTUP_TDRIVE (Bitfield-Mask: 0x07)       */
-#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_RCOSC_SYNC_DELAY_TRIM_Pos (0UL) /*!< XTAL32M_RCOSC_SYNC_DELAY_TRIM (Bit 0)          */
-#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_RCOSC_SYNC_DELAY_TRIM_Msk (0x1fUL) /*!< XTAL32M_RCOSC_SYNC_DELAY_TRIM (Bitfield-Mask: 0x1f) */
-/* ===================================================  XTAL32M_CTRL2_REG  =================================================== */
-#define CRG_XTAL_XTAL32M_CTRL2_REG_XTAL32M_RCOSC_TRIM_SNS_Pos (14UL) /*!< XTAL32M_RCOSC_TRIM_SNS (Bit 14)                      */
-#define CRG_XTAL_XTAL32M_CTRL2_REG_XTAL32M_RCOSC_TRIM_SNS_Msk (0x3fc000UL) /*!< XTAL32M_RCOSC_TRIM_SNS (Bitfield-Mask: 0xff)   */
-#define CRG_XTAL_XTAL32M_CTRL2_REG_XTAL32M_CXCOMP_PHI_TRIM_Pos (12UL) /*!< XTAL32M_CXCOMP_PHI_TRIM (Bit 12)                    */
-#define CRG_XTAL_XTAL32M_CTRL2_REG_XTAL32M_CXCOMP_PHI_TRIM_Msk (0x3000UL) /*!< XTAL32M_CXCOMP_PHI_TRIM (Bitfield-Mask: 0x03)   */
-#define CRG_XTAL_XTAL32M_CTRL2_REG_XTAL32M_CXCOMP_TRIM_CAP_Pos (3UL) /*!< XTAL32M_CXCOMP_TRIM_CAP (Bit 3)                      */
-#define CRG_XTAL_XTAL32M_CTRL2_REG_XTAL32M_CXCOMP_TRIM_CAP_Msk (0xff8UL) /*!< XTAL32M_CXCOMP_TRIM_CAP (Bitfield-Mask: 0x1ff)   */
-/* ===================================================  XTAL32M_CTRL3_REG  =================================================== */
-#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_RCOSC_TRIM_STROBE_Pos (30UL) /*!< XTAL32M_RCOSC_TRIM_STROBE (Bit 30)                */
-#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_RCOSC_TRIM_STROBE_Msk (0x40000000UL) /*!< XTAL32M_RCOSC_TRIM_STROBE (Bitfield-Mask: 0x01) */
-#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_FREQ_DET_START_Pos (22UL) /*!< XTAL32M_FREQ_DET_START (Bit 22)                      */
-#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_FREQ_DET_START_Msk (0x400000UL) /*!< XTAL32M_FREQ_DET_START (Bitfield-Mask: 0x01)   */
-#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_SW_CTRL_MODE_Pos (18UL)  /*!< XTAL32M_SW_CTRL_MODE (Bit 18)                         */
-#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_SW_CTRL_MODE_Msk (0x40000UL) /*!< XTAL32M_SW_CTRL_MODE (Bitfield-Mask: 0x01)        */
-#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_RCOSC_BAND_SELECT_Pos (14UL) /*!< XTAL32M_RCOSC_BAND_SELECT (Bit 14)                */
-#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_RCOSC_BAND_SELECT_Msk (0x3c000UL) /*!< XTAL32M_RCOSC_BAND_SELECT (Bitfield-Mask: 0x0f) */
-#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_RCOSC_TRIM_Pos (4UL)     /*!< XTAL32M_RCOSC_TRIM (Bit 4)                            */
-#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_RCOSC_TRIM_Msk (0x3ff0UL) /*!< XTAL32M_RCOSC_TRIM (Bitfield-Mask: 0x3ff)            */
-/* ===================================================  XTAL32M_CTRL4_REG  =================================================== */
-/* ===================================================  XTAL32M_STAT0_REG  =================================================== */
-#define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_RCOSC_BAND_SELECT_STAT_Pos (28UL) /*!< XTAL32M_RCOSC_BAND_SELECT_STAT (Bit 28)      */
-#define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_RCOSC_BAND_SELECT_STAT_Msk (0xf0000000UL) /*!< XTAL32M_RCOSC_BAND_SELECT_STAT (Bitfield-Mask: 0x0f) */
-#define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_RCOSC_CALIBRATION_DONE_Pos (15UL) /*!< XTAL32M_RCOSC_CALIBRATION_DONE (Bit 15)      */
-#define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_RCOSC_CALIBRATION_DONE_Msk (0x8000UL) /*!< XTAL32M_RCOSC_CALIBRATION_DONE (Bitfield-Mask: 0x01) */
-/* ===================================================  XTAL32M_STAT1_REG  =================================================== */
-#define CRG_XTAL_XTAL32M_STAT1_REG_XTAL32M_CAL_STATE_Pos (4UL)      /*!< XTAL32M_CAL_STATE (Bit 4)                             */
-#define CRG_XTAL_XTAL32M_STAT1_REG_XTAL32M_CAL_STATE_Msk (0xf0UL)   /*!< XTAL32M_CAL_STATE (Bitfield-Mask: 0x0f)               */
-#define CRG_XTAL_XTAL32M_STAT1_REG_XTAL32M_STATE_Pos (0UL)          /*!< XTAL32M_STATE (Bit 0)                                 */
-#define CRG_XTAL_XTAL32M_STAT1_REG_XTAL32M_STATE_Msk (0xfUL)        /*!< XTAL32M_STATE (Bitfield-Mask: 0x0f)                   */
-/* ===================================================  XTALRDY_CTRL_REG  ==================================================== */
-#define CRG_XTAL_XTALRDY_CTRL_REG_XTALRDY_CLK_SEL_Pos (8UL)         /*!< XTALRDY_CLK_SEL (Bit 8)                               */
-#define CRG_XTAL_XTALRDY_CTRL_REG_XTALRDY_CLK_SEL_Msk (0x100UL)     /*!< XTALRDY_CLK_SEL (Bitfield-Mask: 0x01)                 */
-#define CRG_XTAL_XTALRDY_CTRL_REG_XTALRDY_CNT_Pos (0UL)             /*!< XTALRDY_CNT (Bit 0)                                   */
-#define CRG_XTAL_XTALRDY_CTRL_REG_XTALRDY_CNT_Msk (0xffUL)          /*!< XTALRDY_CNT (Bitfield-Mask: 0xff)                     */
-/* ===================================================  XTALRDY_STAT_REG  ==================================================== */
-#define CRG_XTAL_XTALRDY_STAT_REG_XTALRDY_COUNT_Pos (8UL)           /*!< XTALRDY_COUNT (Bit 8)                                 */
-#define CRG_XTAL_XTALRDY_STAT_REG_XTALRDY_COUNT_Msk (0xff00UL)      /*!< XTALRDY_COUNT (Bitfield-Mask: 0xff)                   */
-#define CRG_XTAL_XTALRDY_STAT_REG_XTALRDY_STAT_Pos (0UL)            /*!< XTALRDY_STAT (Bit 0)                                  */
-#define CRG_XTAL_XTALRDY_STAT_REG_XTALRDY_STAT_Msk (0xffUL)         /*!< XTALRDY_STAT (Bitfield-Mask: 0xff)                    */
-
-
-/* =========================================================================================================================== */
-/* ================                                           DCDC                                            ================ */
-/* =========================================================================================================================== */
-
-/* ====================================================  DCDC_CTRL1_REG  ===================================================== */
-#define DCDC_DCDC_CTRL1_REG_DCDC_SH_ENABLE_Pos (31UL)               /*!< DCDC_SH_ENABLE (Bit 31)                               */
-#define DCDC_DCDC_CTRL1_REG_DCDC_SH_ENABLE_Msk (0x80000000UL)       /*!< DCDC_SH_ENABLE (Bitfield-Mask: 0x01)                  */
-#define DCDC_DCDC_CTRL1_REG_DCDC_STARTUP_DELAY_Pos (26UL)           /*!< DCDC_STARTUP_DELAY (Bit 26)                           */
-#define DCDC_DCDC_CTRL1_REG_DCDC_STARTUP_DELAY_Msk (0x7c000000UL)   /*!< DCDC_STARTUP_DELAY (Bitfield-Mask: 0x1f)              */
-#define DCDC_DCDC_CTRL1_REG_DCDC_IDLE_MAX_FAST_DOWNRAMP_Pos (20UL)  /*!< DCDC_IDLE_MAX_FAST_DOWNRAMP (Bit 20)                  */
-#define DCDC_DCDC_CTRL1_REG_DCDC_IDLE_MAX_FAST_DOWNRAMP_Msk (0x3f00000UL) /*!< DCDC_IDLE_MAX_FAST_DOWNRAMP (Bitfield-Mask: 0x3f) */
-#define DCDC_DCDC_CTRL1_REG_DCDC_SW_TIMEOUT_Pos (15UL)              /*!< DCDC_SW_TIMEOUT (Bit 15)                              */
-#define DCDC_DCDC_CTRL1_REG_DCDC_SW_TIMEOUT_Msk (0xf8000UL)         /*!< DCDC_SW_TIMEOUT (Bitfield-Mask: 0x1f)                 */
-#define DCDC_DCDC_CTRL1_REG_DCDC_FAST_STARTUP_Pos (14UL)            /*!< DCDC_FAST_STARTUP (Bit 14)                            */
-#define DCDC_DCDC_CTRL1_REG_DCDC_FAST_STARTUP_Msk (0x4000UL)        /*!< DCDC_FAST_STARTUP (Bitfield-Mask: 0x01)               */
-#define DCDC_DCDC_CTRL1_REG_DCDC_MAN_LV_MODE_Pos (13UL)             /*!< DCDC_MAN_LV_MODE (Bit 13)                             */
-#define DCDC_DCDC_CTRL1_REG_DCDC_MAN_LV_MODE_Msk (0x2000UL)         /*!< DCDC_MAN_LV_MODE (Bitfield-Mask: 0x01)                */
-#define DCDC_DCDC_CTRL1_REG_DCDC_AUTO_LV_MODE_Pos (12UL)            /*!< DCDC_AUTO_LV_MODE (Bit 12)                            */
-#define DCDC_DCDC_CTRL1_REG_DCDC_AUTO_LV_MODE_Msk (0x1000UL)        /*!< DCDC_AUTO_LV_MODE (Bitfield-Mask: 0x01)               */
-#define DCDC_DCDC_CTRL1_REG_DCDC_IDLE_CLK_DIV_Pos (10UL)            /*!< DCDC_IDLE_CLK_DIV (Bit 10)                            */
-#define DCDC_DCDC_CTRL1_REG_DCDC_IDLE_CLK_DIV_Msk (0xc00UL)         /*!< DCDC_IDLE_CLK_DIV (Bitfield-Mask: 0x03)               */
-#define DCDC_DCDC_CTRL1_REG_DCDC_PRIORITY_Pos (2UL)                 /*!< DCDC_PRIORITY (Bit 2)                                 */
-#define DCDC_DCDC_CTRL1_REG_DCDC_PRIORITY_Msk (0x3fcUL)             /*!< DCDC_PRIORITY (Bitfield-Mask: 0xff)                   */
-#define DCDC_DCDC_CTRL1_REG_DCDC_FW_ENABLE_Pos (1UL)                /*!< DCDC_FW_ENABLE (Bit 1)                                */
-#define DCDC_DCDC_CTRL1_REG_DCDC_FW_ENABLE_Msk (0x2UL)              /*!< DCDC_FW_ENABLE (Bitfield-Mask: 0x01)                  */
-#define DCDC_DCDC_CTRL1_REG_DCDC_ENABLE_Pos (0UL)                   /*!< DCDC_ENABLE (Bit 0)                                   */
-#define DCDC_DCDC_CTRL1_REG_DCDC_ENABLE_Msk (0x1UL)                 /*!< DCDC_ENABLE (Bitfield-Mask: 0x01)                     */
-/* ====================================================  DCDC_CTRL2_REG  ===================================================== */
-#define DCDC_DCDC_CTRL2_REG_DCDC_V_NOK_CNT_MAX_Pos (24UL)           /*!< DCDC_V_NOK_CNT_MAX (Bit 24)                           */
-#define DCDC_DCDC_CTRL2_REG_DCDC_V_NOK_CNT_MAX_Msk (0xf000000UL)    /*!< DCDC_V_NOK_CNT_MAX (Bitfield-Mask: 0x0f)              */
-#define DCDC_DCDC_CTRL2_REG_DCDC_N_COMP_TRIM_MAN_Pos (22UL)         /*!< DCDC_N_COMP_TRIM_MAN (Bit 22)                         */
-#define DCDC_DCDC_CTRL2_REG_DCDC_N_COMP_TRIM_MAN_Msk (0x400000UL)   /*!< DCDC_N_COMP_TRIM_MAN (Bitfield-Mask: 0x01)            */
-#define DCDC_DCDC_CTRL2_REG_DCDC_N_COMP_TRIM_VAL_Pos (16UL)         /*!< DCDC_N_COMP_TRIM_VAL (Bit 16)                         */
-#define DCDC_DCDC_CTRL2_REG_DCDC_N_COMP_TRIM_VAL_Msk (0x3f0000UL)   /*!< DCDC_N_COMP_TRIM_VAL (Bitfield-Mask: 0x3f)            */
-#define DCDC_DCDC_CTRL2_REG_DCDC_TIMEOUT_IRQ_TRIG_Pos (12UL)        /*!< DCDC_TIMEOUT_IRQ_TRIG (Bit 12)                        */
-#define DCDC_DCDC_CTRL2_REG_DCDC_TIMEOUT_IRQ_TRIG_Msk (0xf000UL)    /*!< DCDC_TIMEOUT_IRQ_TRIG (Bitfield-Mask: 0x0f)           */
-#define DCDC_DCDC_CTRL2_REG_DCDC_TIMEOUT_IRQ_RES_Pos (8UL)          /*!< DCDC_TIMEOUT_IRQ_RES (Bit 8)                          */
-#define DCDC_DCDC_CTRL2_REG_DCDC_TIMEOUT_IRQ_RES_Msk (0xf00UL)      /*!< DCDC_TIMEOUT_IRQ_RES (Bitfield-Mask: 0x0f)            */
-#define DCDC_DCDC_CTRL2_REG_DCDC_SLOPE_CONTROL_Pos (6UL)            /*!< DCDC_SLOPE_CONTROL (Bit 6)                            */
-#define DCDC_DCDC_CTRL2_REG_DCDC_SLOPE_CONTROL_Msk (0xc0UL)         /*!< DCDC_SLOPE_CONTROL (Bitfield-Mask: 0x03)              */
-#define DCDC_DCDC_CTRL2_REG_DCDC_VBTSTRP_TRIM_Pos (4UL)             /*!< DCDC_VBTSTRP_TRIM (Bit 4)                             */
-#define DCDC_DCDC_CTRL2_REG_DCDC_VBTSTRP_TRIM_Msk (0x30UL)          /*!< DCDC_VBTSTRP_TRIM (Bitfield-Mask: 0x03)               */
-#define DCDC_DCDC_CTRL2_REG_DCDC_LSSUP_TRIM_Pos (2UL)               /*!< DCDC_LSSUP_TRIM (Bit 2)                               */
-#define DCDC_DCDC_CTRL2_REG_DCDC_LSSUP_TRIM_Msk (0xcUL)             /*!< DCDC_LSSUP_TRIM (Bitfield-Mask: 0x03)                 */
-#define DCDC_DCDC_CTRL2_REG_DCDC_HSGND_TRIM_Pos (0UL)               /*!< DCDC_HSGND_TRIM (Bit 0)                               */
-#define DCDC_DCDC_CTRL2_REG_DCDC_HSGND_TRIM_Msk (0x3UL)             /*!< DCDC_HSGND_TRIM (Bitfield-Mask: 0x03)                 */
-/* ==================================================  DCDC_IRQ_CLEAR_REG  =================================================== */
-#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_LOW_VBAT_IRQ_CLEAR_Pos (4UL)   /*!< DCDC_LOW_VBAT_IRQ_CLEAR (Bit 4)                       */
-#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_LOW_VBAT_IRQ_CLEAR_Msk (0x10UL) /*!< DCDC_LOW_VBAT_IRQ_CLEAR (Bitfield-Mask: 0x01)        */
-#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18P_TIMEOUT_IRQ_CLEAR_Pos (3UL) /*!< DCDC_V18P_TIMEOUT_IRQ_CLEAR (Bit 3)                 */
-#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18P_TIMEOUT_IRQ_CLEAR_Msk (0x8UL) /*!< DCDC_V18P_TIMEOUT_IRQ_CLEAR (Bitfield-Mask: 0x01) */
-#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_VDD_TIMEOUT_IRQ_CLEAR_Pos (2UL) /*!< DCDC_VDD_TIMEOUT_IRQ_CLEAR (Bit 2)                   */
-#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_VDD_TIMEOUT_IRQ_CLEAR_Msk (0x4UL) /*!< DCDC_VDD_TIMEOUT_IRQ_CLEAR (Bitfield-Mask: 0x01)   */
-#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18_TIMEOUT_IRQ_CLEAR_Pos (1UL) /*!< DCDC_V18_TIMEOUT_IRQ_CLEAR (Bit 1)                   */
-#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18_TIMEOUT_IRQ_CLEAR_Msk (0x2UL) /*!< DCDC_V18_TIMEOUT_IRQ_CLEAR (Bitfield-Mask: 0x01)   */
-#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V14_TIMEOUT_IRQ_CLEAR_Pos (0UL) /*!< DCDC_V14_TIMEOUT_IRQ_CLEAR (Bit 0)                   */
-#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V14_TIMEOUT_IRQ_CLEAR_Msk (0x1UL) /*!< DCDC_V14_TIMEOUT_IRQ_CLEAR (Bitfield-Mask: 0x01)   */
-/* ===================================================  DCDC_IRQ_MASK_REG  =================================================== */
-#define DCDC_DCDC_IRQ_MASK_REG_DCDC_LOW_VBAT_IRQ_MASK_Pos (4UL)     /*!< DCDC_LOW_VBAT_IRQ_MASK (Bit 4)                        */
-#define DCDC_DCDC_IRQ_MASK_REG_DCDC_LOW_VBAT_IRQ_MASK_Msk (0x10UL)  /*!< DCDC_LOW_VBAT_IRQ_MASK (Bitfield-Mask: 0x01)          */
-#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18P_TIMEOUT_IRQ_MASK_Pos (3UL) /*!< DCDC_V18P_TIMEOUT_IRQ_MASK (Bit 3)                    */
-#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18P_TIMEOUT_IRQ_MASK_Msk (0x8UL) /*!< DCDC_V18P_TIMEOUT_IRQ_MASK (Bitfield-Mask: 0x01)    */
-#define DCDC_DCDC_IRQ_MASK_REG_DCDC_VDD_TIMEOUT_IRQ_MASK_Pos (2UL)  /*!< DCDC_VDD_TIMEOUT_IRQ_MASK (Bit 2)                     */
-#define DCDC_DCDC_IRQ_MASK_REG_DCDC_VDD_TIMEOUT_IRQ_MASK_Msk (0x4UL) /*!< DCDC_VDD_TIMEOUT_IRQ_MASK (Bitfield-Mask: 0x01)      */
-#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18_TIMEOUT_IRQ_MASK_Pos (1UL)  /*!< DCDC_V18_TIMEOUT_IRQ_MASK (Bit 1)                     */
-#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18_TIMEOUT_IRQ_MASK_Msk (0x2UL) /*!< DCDC_V18_TIMEOUT_IRQ_MASK (Bitfield-Mask: 0x01)      */
-#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V14_TIMEOUT_IRQ_MASK_Pos (0UL)  /*!< DCDC_V14_TIMEOUT_IRQ_MASK (Bit 0)                     */
-#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V14_TIMEOUT_IRQ_MASK_Msk (0x1UL) /*!< DCDC_V14_TIMEOUT_IRQ_MASK (Bitfield-Mask: 0x01)      */
-/* ==================================================  DCDC_IRQ_STATUS_REG  ================================================== */
-#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_LOW_VBAT_IRQ_STATUS_Pos (4UL) /*!< DCDC_LOW_VBAT_IRQ_STATUS (Bit 4)                      */
-#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_LOW_VBAT_IRQ_STATUS_Msk (0x10UL) /*!< DCDC_LOW_VBAT_IRQ_STATUS (Bitfield-Mask: 0x01)     */
-#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18P_TIMEOUT_IRQ_STATUS_Pos (3UL) /*!< DCDC_V18P_TIMEOUT_IRQ_STATUS (Bit 3)              */
-#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18P_TIMEOUT_IRQ_STATUS_Msk (0x8UL) /*!< DCDC_V18P_TIMEOUT_IRQ_STATUS (Bitfield-Mask: 0x01) */
-#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_VDD_TIMEOUT_IRQ_STATUS_Pos (2UL) /*!< DCDC_VDD_TIMEOUT_IRQ_STATUS (Bit 2)                */
-#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_VDD_TIMEOUT_IRQ_STATUS_Msk (0x4UL) /*!< DCDC_VDD_TIMEOUT_IRQ_STATUS (Bitfield-Mask: 0x01) */
-#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18_TIMEOUT_IRQ_STATUS_Pos (1UL) /*!< DCDC_V18_TIMEOUT_IRQ_STATUS (Bit 1)                */
-#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18_TIMEOUT_IRQ_STATUS_Msk (0x2UL) /*!< DCDC_V18_TIMEOUT_IRQ_STATUS (Bitfield-Mask: 0x01) */
-#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V14_TIMEOUT_IRQ_STATUS_Pos (0UL) /*!< DCDC_V14_TIMEOUT_IRQ_STATUS (Bit 0)                */
-#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V14_TIMEOUT_IRQ_STATUS_Msk (0x1UL) /*!< DCDC_V14_TIMEOUT_IRQ_STATUS (Bitfield-Mask: 0x01) */
-/* ===================================================  DCDC_STATUS1_REG  ==================================================== */
-#define DCDC_DCDC_STATUS1_REG_DCDC_V18P_AVAILABLE_Pos (27UL)        /*!< DCDC_V18P_AVAILABLE (Bit 27)                          */
-#define DCDC_DCDC_STATUS1_REG_DCDC_V18P_AVAILABLE_Msk (0x8000000UL) /*!< DCDC_V18P_AVAILABLE (Bitfield-Mask: 0x01)             */
-#define DCDC_DCDC_STATUS1_REG_DCDC_VDD_AVAILABLE_Pos (26UL)         /*!< DCDC_VDD_AVAILABLE (Bit 26)                           */
-#define DCDC_DCDC_STATUS1_REG_DCDC_VDD_AVAILABLE_Msk (0x4000000UL)  /*!< DCDC_VDD_AVAILABLE (Bitfield-Mask: 0x01)              */
-#define DCDC_DCDC_STATUS1_REG_DCDC_V18_AVAILABLE_Pos (25UL)         /*!< DCDC_V18_AVAILABLE (Bit 25)                           */
-#define DCDC_DCDC_STATUS1_REG_DCDC_V18_AVAILABLE_Msk (0x2000000UL)  /*!< DCDC_V18_AVAILABLE (Bitfield-Mask: 0x01)              */
-#define DCDC_DCDC_STATUS1_REG_DCDC_V14_AVAILABLE_Pos (24UL)         /*!< DCDC_V14_AVAILABLE (Bit 24)                           */
-#define DCDC_DCDC_STATUS1_REG_DCDC_V14_AVAILABLE_Msk (0x1000000UL)  /*!< DCDC_V14_AVAILABLE (Bitfield-Mask: 0x01)              */
-#define DCDC_DCDC_STATUS1_REG_DCDC_V18P_COMP_OK_Pos (23UL)          /*!< DCDC_V18P_COMP_OK (Bit 23)                            */
-#define DCDC_DCDC_STATUS1_REG_DCDC_V18P_COMP_OK_Msk (0x800000UL)    /*!< DCDC_V18P_COMP_OK (Bitfield-Mask: 0x01)               */
-#define DCDC_DCDC_STATUS1_REG_DCDC_VDD_COMP_OK_Pos (22UL)           /*!< DCDC_VDD_COMP_OK (Bit 22)                             */
-#define DCDC_DCDC_STATUS1_REG_DCDC_VDD_COMP_OK_Msk (0x400000UL)     /*!< DCDC_VDD_COMP_OK (Bitfield-Mask: 0x01)                */
-#define DCDC_DCDC_STATUS1_REG_DCDC_V18_COMP_OK_Pos (21UL)           /*!< DCDC_V18_COMP_OK (Bit 21)                             */
-#define DCDC_DCDC_STATUS1_REG_DCDC_V18_COMP_OK_Msk (0x200000UL)     /*!< DCDC_V18_COMP_OK (Bitfield-Mask: 0x01)                */
-#define DCDC_DCDC_STATUS1_REG_DCDC_V14_COMP_OK_Pos (20UL)           /*!< DCDC_V14_COMP_OK (Bit 20)                             */
-#define DCDC_DCDC_STATUS1_REG_DCDC_V14_COMP_OK_Msk (0x100000UL)     /*!< DCDC_V14_COMP_OK (Bitfield-Mask: 0x01)                */
-#define DCDC_DCDC_STATUS1_REG_DCDC_V18P_COMP_NOK_Pos (19UL)         /*!< DCDC_V18P_COMP_NOK (Bit 19)                           */
-#define DCDC_DCDC_STATUS1_REG_DCDC_V18P_COMP_NOK_Msk (0x80000UL)    /*!< DCDC_V18P_COMP_NOK (Bitfield-Mask: 0x01)              */
-#define DCDC_DCDC_STATUS1_REG_DCDC_VDD_COMP_NOK_Pos (18UL)          /*!< DCDC_VDD_COMP_NOK (Bit 18)                            */
-#define DCDC_DCDC_STATUS1_REG_DCDC_VDD_COMP_NOK_Msk (0x40000UL)     /*!< DCDC_VDD_COMP_NOK (Bitfield-Mask: 0x01)               */
-#define DCDC_DCDC_STATUS1_REG_DCDC_V18_COMP_NOK_Pos (17UL)          /*!< DCDC_V18_COMP_NOK (Bit 17)                            */
-#define DCDC_DCDC_STATUS1_REG_DCDC_V18_COMP_NOK_Msk (0x20000UL)     /*!< DCDC_V18_COMP_NOK (Bitfield-Mask: 0x01)               */
-#define DCDC_DCDC_STATUS1_REG_DCDC_V14_COMP_NOK_Pos (16UL)          /*!< DCDC_V14_COMP_NOK (Bit 16)                            */
-#define DCDC_DCDC_STATUS1_REG_DCDC_V14_COMP_NOK_Msk (0x10000UL)     /*!< DCDC_V14_COMP_NOK (Bitfield-Mask: 0x01)               */
-#define DCDC_DCDC_STATUS1_REG_DCDC_N_COMP_P_Pos (11UL)              /*!< DCDC_N_COMP_P (Bit 11)                                */
-#define DCDC_DCDC_STATUS1_REG_DCDC_N_COMP_P_Msk (0x800UL)           /*!< DCDC_N_COMP_P (Bitfield-Mask: 0x01)                   */
-#define DCDC_DCDC_STATUS1_REG_DCDC_N_COMP_N_Pos (10UL)              /*!< DCDC_N_COMP_N (Bit 10)                                */
-#define DCDC_DCDC_STATUS1_REG_DCDC_N_COMP_N_Msk (0x400UL)           /*!< DCDC_N_COMP_N (Bitfield-Mask: 0x01)                   */
-#define DCDC_DCDC_STATUS1_REG_DCDC_P_COMP_Pos (9UL)                 /*!< DCDC_P_COMP (Bit 9)                                   */
-#define DCDC_DCDC_STATUS1_REG_DCDC_P_COMP_Msk (0x200UL)             /*!< DCDC_P_COMP (Bitfield-Mask: 0x01)                     */
-#define DCDC_DCDC_STATUS1_REG_DCDC_N_COMP_Pos (8UL)                 /*!< DCDC_N_COMP (Bit 8)                                   */
-#define DCDC_DCDC_STATUS1_REG_DCDC_N_COMP_Msk (0x100UL)             /*!< DCDC_N_COMP (Bitfield-Mask: 0x01)                     */
-#define DCDC_DCDC_STATUS1_REG_DCDC_LV_MODE_Pos (7UL)                /*!< DCDC_LV_MODE (Bit 7)                                  */
-#define DCDC_DCDC_STATUS1_REG_DCDC_LV_MODE_Msk (0x80UL)             /*!< DCDC_LV_MODE (Bitfield-Mask: 0x01)                    */
-#define DCDC_DCDC_STATUS1_REG_DCDC_V18P_SW_STATE_Pos (6UL)          /*!< DCDC_V18P_SW_STATE (Bit 6)                            */
-#define DCDC_DCDC_STATUS1_REG_DCDC_V18P_SW_STATE_Msk (0x40UL)       /*!< DCDC_V18P_SW_STATE (Bitfield-Mask: 0x01)              */
-#define DCDC_DCDC_STATUS1_REG_DCDC_VDD_SW_STATE_Pos (5UL)           /*!< DCDC_VDD_SW_STATE (Bit 5)                             */
-#define DCDC_DCDC_STATUS1_REG_DCDC_VDD_SW_STATE_Msk (0x20UL)        /*!< DCDC_VDD_SW_STATE (Bitfield-Mask: 0x01)               */
-#define DCDC_DCDC_STATUS1_REG_DCDC_V18_SW_STATE_Pos (4UL)           /*!< DCDC_V18_SW_STATE (Bit 4)                             */
-#define DCDC_DCDC_STATUS1_REG_DCDC_V18_SW_STATE_Msk (0x10UL)        /*!< DCDC_V18_SW_STATE (Bitfield-Mask: 0x01)               */
-#define DCDC_DCDC_STATUS1_REG_DCDC_V14_SW_STATE_Pos (3UL)           /*!< DCDC_V14_SW_STATE (Bit 3)                             */
-#define DCDC_DCDC_STATUS1_REG_DCDC_V14_SW_STATE_Msk (0x8UL)         /*!< DCDC_V14_SW_STATE (Bitfield-Mask: 0x01)               */
-#define DCDC_DCDC_STATUS1_REG_DCDC_N_SW_STATE_Pos (2UL)             /*!< DCDC_N_SW_STATE (Bit 2)                               */
-#define DCDC_DCDC_STATUS1_REG_DCDC_N_SW_STATE_Msk (0x4UL)           /*!< DCDC_N_SW_STATE (Bitfield-Mask: 0x01)                 */
-#define DCDC_DCDC_STATUS1_REG_DCDC_P_SW_STATE_Pos (1UL)             /*!< DCDC_P_SW_STATE (Bit 1)                               */
-#define DCDC_DCDC_STATUS1_REG_DCDC_P_SW_STATE_Msk (0x2UL)           /*!< DCDC_P_SW_STATE (Bitfield-Mask: 0x01)                 */
-#define DCDC_DCDC_STATUS1_REG_DCDC_STARTUP_COMPLETE_Pos (0UL)       /*!< DCDC_STARTUP_COMPLETE (Bit 0)                         */
-#define DCDC_DCDC_STATUS1_REG_DCDC_STARTUP_COMPLETE_Msk (0x1UL)     /*!< DCDC_STARTUP_COMPLETE (Bitfield-Mask: 0x01)           */
-/* =====================================================  DCDC_V14_REG  ====================================================== */
-#define DCDC_DCDC_V14_REG_DCDC_V14_FAST_RAMPING_Pos (31UL)          /*!< DCDC_V14_FAST_RAMPING (Bit 31)                        */
-#define DCDC_DCDC_V14_REG_DCDC_V14_FAST_RAMPING_Msk (0x80000000UL)  /*!< DCDC_V14_FAST_RAMPING (Bitfield-Mask: 0x01)           */
-#define DCDC_DCDC_V14_REG_DCDC_V14_TRIM_Pos (27UL)                  /*!< DCDC_V14_TRIM (Bit 27)                                */
-#define DCDC_DCDC_V14_REG_DCDC_V14_TRIM_Msk (0x8000000UL)           /*!< DCDC_V14_TRIM (Bitfield-Mask: 0x01)                   */
-#define DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MAX_HV_Pos (22UL)        /*!< DCDC_V14_CUR_LIM_MAX_HV (Bit 22)                      */
-#define DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MAX_HV_Msk (0x7c00000UL) /*!< DCDC_V14_CUR_LIM_MAX_HV (Bitfield-Mask: 0x1f)         */
-#define DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MAX_LV_Pos (17UL)        /*!< DCDC_V14_CUR_LIM_MAX_LV (Bit 17)                      */
-#define DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MAX_LV_Msk (0x3e0000UL)  /*!< DCDC_V14_CUR_LIM_MAX_LV (Bitfield-Mask: 0x1f)         */
-#define DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MIN_Pos (12UL)           /*!< DCDC_V14_CUR_LIM_MIN (Bit 12)                         */
-#define DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MIN_Msk (0x1f000UL)      /*!< DCDC_V14_CUR_LIM_MIN (Bitfield-Mask: 0x1f)            */
-#define DCDC_DCDC_V14_REG_DCDC_V14_IDLE_HYST_Pos (7UL)              /*!< DCDC_V14_IDLE_HYST (Bit 7)                            */
-#define DCDC_DCDC_V14_REG_DCDC_V14_IDLE_HYST_Msk (0xf80UL)          /*!< DCDC_V14_IDLE_HYST (Bitfield-Mask: 0x1f)              */
-#define DCDC_DCDC_V14_REG_DCDC_V14_IDLE_MIN_Pos (2UL)               /*!< DCDC_V14_IDLE_MIN (Bit 2)                             */
-#define DCDC_DCDC_V14_REG_DCDC_V14_IDLE_MIN_Msk (0x7cUL)            /*!< DCDC_V14_IDLE_MIN (Bitfield-Mask: 0x1f)               */
-#define DCDC_DCDC_V14_REG_DCDC_V14_ENABLE_HV_Pos (1UL)              /*!< DCDC_V14_ENABLE_HV (Bit 1)                            */
-#define DCDC_DCDC_V14_REG_DCDC_V14_ENABLE_HV_Msk (0x2UL)            /*!< DCDC_V14_ENABLE_HV (Bitfield-Mask: 0x01)              */
-#define DCDC_DCDC_V14_REG_DCDC_V14_ENABLE_LV_Pos (0UL)              /*!< DCDC_V14_ENABLE_LV (Bit 0)                            */
-#define DCDC_DCDC_V14_REG_DCDC_V14_ENABLE_LV_Msk (0x1UL)            /*!< DCDC_V14_ENABLE_LV (Bitfield-Mask: 0x01)              */
-/* =====================================================  DCDC_V18P_REG  ===================================================== */
-#define DCDC_DCDC_V18P_REG_DCDC_V18P_FAST_RAMPING_Pos (31UL)        /*!< DCDC_V18P_FAST_RAMPING (Bit 31)                       */
-#define DCDC_DCDC_V18P_REG_DCDC_V18P_FAST_RAMPING_Msk (0x80000000UL) /*!< DCDC_V18P_FAST_RAMPING (Bitfield-Mask: 0x01)         */
-#define DCDC_DCDC_V18P_REG_DCDC_V18P_TRIM_Pos (27UL)                /*!< DCDC_V18P_TRIM (Bit 27)                               */
-#define DCDC_DCDC_V18P_REG_DCDC_V18P_TRIM_Msk (0x78000000UL)        /*!< DCDC_V18P_TRIM (Bitfield-Mask: 0x0f)                  */
-#define DCDC_DCDC_V18P_REG_DCDC_V18P_CUR_LIM_MAX_HV_Pos (22UL)      /*!< DCDC_V18P_CUR_LIM_MAX_HV (Bit 22)                     */
-#define DCDC_DCDC_V18P_REG_DCDC_V18P_CUR_LIM_MAX_HV_Msk (0x7c00000UL) /*!< DCDC_V18P_CUR_LIM_MAX_HV (Bitfield-Mask: 0x1f)      */
-#define DCDC_DCDC_V18P_REG_DCDC_V18P_CUR_LIM_MAX_LV_Pos (17UL)      /*!< DCDC_V18P_CUR_LIM_MAX_LV (Bit 17)                     */
-#define DCDC_DCDC_V18P_REG_DCDC_V18P_CUR_LIM_MAX_LV_Msk (0x3e0000UL) /*!< DCDC_V18P_CUR_LIM_MAX_LV (Bitfield-Mask: 0x1f)       */
-#define DCDC_DCDC_V18P_REG_DCDC_V18P_CUR_LIM_MIN_Pos (12UL)         /*!< DCDC_V18P_CUR_LIM_MIN (Bit 12)                        */
-#define DCDC_DCDC_V18P_REG_DCDC_V18P_CUR_LIM_MIN_Msk (0x1f000UL)    /*!< DCDC_V18P_CUR_LIM_MIN (Bitfield-Mask: 0x1f)           */
-#define DCDC_DCDC_V18P_REG_DCDC_V18P_IDLE_HYST_Pos (7UL)            /*!< DCDC_V18P_IDLE_HYST (Bit 7)                           */
-#define DCDC_DCDC_V18P_REG_DCDC_V18P_IDLE_HYST_Msk (0xf80UL)        /*!< DCDC_V18P_IDLE_HYST (Bitfield-Mask: 0x1f)             */
-#define DCDC_DCDC_V18P_REG_DCDC_V18P_IDLE_MIN_Pos (2UL)             /*!< DCDC_V18P_IDLE_MIN (Bit 2)                            */
-#define DCDC_DCDC_V18P_REG_DCDC_V18P_IDLE_MIN_Msk (0x7cUL)          /*!< DCDC_V18P_IDLE_MIN (Bitfield-Mask: 0x1f)              */
-#define DCDC_DCDC_V18P_REG_DCDC_V18P_ENABLE_HV_Pos (1UL)            /*!< DCDC_V18P_ENABLE_HV (Bit 1)                           */
-#define DCDC_DCDC_V18P_REG_DCDC_V18P_ENABLE_HV_Msk (0x2UL)          /*!< DCDC_V18P_ENABLE_HV (Bitfield-Mask: 0x01)             */
-#define DCDC_DCDC_V18P_REG_DCDC_V18P_ENABLE_LV_Pos (0UL)            /*!< DCDC_V18P_ENABLE_LV (Bit 0)                           */
-#define DCDC_DCDC_V18P_REG_DCDC_V18P_ENABLE_LV_Msk (0x1UL)          /*!< DCDC_V18P_ENABLE_LV (Bitfield-Mask: 0x01)             */
-/* =====================================================  DCDC_V18_REG  ====================================================== */
-#define DCDC_DCDC_V18_REG_DCDC_V18_FAST_RAMPING_Pos (31UL)          /*!< DCDC_V18_FAST_RAMPING (Bit 31)                        */
-#define DCDC_DCDC_V18_REG_DCDC_V18_FAST_RAMPING_Msk (0x80000000UL)  /*!< DCDC_V18_FAST_RAMPING (Bitfield-Mask: 0x01)           */
-#define DCDC_DCDC_V18_REG_DCDC_V18_TRIM_Pos (27UL)                  /*!< DCDC_V18_TRIM (Bit 27)                                */
-#define DCDC_DCDC_V18_REG_DCDC_V18_TRIM_Msk (0x78000000UL)          /*!< DCDC_V18_TRIM (Bitfield-Mask: 0x0f)                   */
-#define DCDC_DCDC_V18_REG_DCDC_V18_CUR_LIM_MAX_HV_Pos (22UL)        /*!< DCDC_V18_CUR_LIM_MAX_HV (Bit 22)                      */
-#define DCDC_DCDC_V18_REG_DCDC_V18_CUR_LIM_MAX_HV_Msk (0x7c00000UL) /*!< DCDC_V18_CUR_LIM_MAX_HV (Bitfield-Mask: 0x1f)         */
-#define DCDC_DCDC_V18_REG_DCDC_V18_CUR_LIM_MAX_LV_Pos (17UL)        /*!< DCDC_V18_CUR_LIM_MAX_LV (Bit 17)                      */
-#define DCDC_DCDC_V18_REG_DCDC_V18_CUR_LIM_MAX_LV_Msk (0x3e0000UL)  /*!< DCDC_V18_CUR_LIM_MAX_LV (Bitfield-Mask: 0x1f)         */
-#define DCDC_DCDC_V18_REG_DCDC_V18_CUR_LIM_MIN_Pos (12UL)           /*!< DCDC_V18_CUR_LIM_MIN (Bit 12)                         */
-#define DCDC_DCDC_V18_REG_DCDC_V18_CUR_LIM_MIN_Msk (0x1f000UL)      /*!< DCDC_V18_CUR_LIM_MIN (Bitfield-Mask: 0x1f)            */
-#define DCDC_DCDC_V18_REG_DCDC_V18_IDLE_HYST_Pos (7UL)              /*!< DCDC_V18_IDLE_HYST (Bit 7)                            */
-#define DCDC_DCDC_V18_REG_DCDC_V18_IDLE_HYST_Msk (0xf80UL)          /*!< DCDC_V18_IDLE_HYST (Bitfield-Mask: 0x1f)              */
-#define DCDC_DCDC_V18_REG_DCDC_V18_IDLE_MIN_Pos (2UL)               /*!< DCDC_V18_IDLE_MIN (Bit 2)                             */
-#define DCDC_DCDC_V18_REG_DCDC_V18_IDLE_MIN_Msk (0x7cUL)            /*!< DCDC_V18_IDLE_MIN (Bitfield-Mask: 0x1f)               */
-#define DCDC_DCDC_V18_REG_DCDC_V18_ENABLE_HV_Pos (1UL)              /*!< DCDC_V18_ENABLE_HV (Bit 1)                            */
-#define DCDC_DCDC_V18_REG_DCDC_V18_ENABLE_HV_Msk (0x2UL)            /*!< DCDC_V18_ENABLE_HV (Bitfield-Mask: 0x01)              */
-#define DCDC_DCDC_V18_REG_DCDC_V18_ENABLE_LV_Pos (0UL)              /*!< DCDC_V18_ENABLE_LV (Bit 0)                            */
-#define DCDC_DCDC_V18_REG_DCDC_V18_ENABLE_LV_Msk (0x1UL)            /*!< DCDC_V18_ENABLE_LV (Bitfield-Mask: 0x01)              */
-/* =====================================================  DCDC_VDD_REG  ====================================================== */
-#define DCDC_DCDC_VDD_REG_DCDC_VDD_FAST_RAMPING_Pos (31UL)          /*!< DCDC_VDD_FAST_RAMPING (Bit 31)                        */
-#define DCDC_DCDC_VDD_REG_DCDC_VDD_FAST_RAMPING_Msk (0x80000000UL)  /*!< DCDC_VDD_FAST_RAMPING (Bitfield-Mask: 0x01)           */
-#define DCDC_DCDC_VDD_REG_DCDC_VDD_TRIM_Pos (27UL)                  /*!< DCDC_VDD_TRIM (Bit 27)                                */
-#define DCDC_DCDC_VDD_REG_DCDC_VDD_TRIM_Msk (0x38000000UL)          /*!< DCDC_VDD_TRIM (Bitfield-Mask: 0x07)                   */
-#define DCDC_DCDC_VDD_REG_DCDC_VDD_CUR_LIM_MAX_HV_Pos (22UL)        /*!< DCDC_VDD_CUR_LIM_MAX_HV (Bit 22)                      */
-#define DCDC_DCDC_VDD_REG_DCDC_VDD_CUR_LIM_MAX_HV_Msk (0x7c00000UL) /*!< DCDC_VDD_CUR_LIM_MAX_HV (Bitfield-Mask: 0x1f)         */
-#define DCDC_DCDC_VDD_REG_DCDC_VDD_CUR_LIM_MAX_LV_Pos (17UL)        /*!< DCDC_VDD_CUR_LIM_MAX_LV (Bit 17)                      */
-#define DCDC_DCDC_VDD_REG_DCDC_VDD_CUR_LIM_MAX_LV_Msk (0x3e0000UL)  /*!< DCDC_VDD_CUR_LIM_MAX_LV (Bitfield-Mask: 0x1f)         */
-#define DCDC_DCDC_VDD_REG_DCDC_VDD_CUR_LIM_MIN_Pos (12UL)           /*!< DCDC_VDD_CUR_LIM_MIN (Bit 12)                         */
-#define DCDC_DCDC_VDD_REG_DCDC_VDD_CUR_LIM_MIN_Msk (0x1f000UL)      /*!< DCDC_VDD_CUR_LIM_MIN (Bitfield-Mask: 0x1f)            */
-#define DCDC_DCDC_VDD_REG_DCDC_VDD_IDLE_HYST_Pos (7UL)              /*!< DCDC_VDD_IDLE_HYST (Bit 7)                            */
-#define DCDC_DCDC_VDD_REG_DCDC_VDD_IDLE_HYST_Msk (0xf80UL)          /*!< DCDC_VDD_IDLE_HYST (Bitfield-Mask: 0x1f)              */
-#define DCDC_DCDC_VDD_REG_DCDC_VDD_IDLE_MIN_Pos (2UL)               /*!< DCDC_VDD_IDLE_MIN (Bit 2)                             */
-#define DCDC_DCDC_VDD_REG_DCDC_VDD_IDLE_MIN_Msk (0x7cUL)            /*!< DCDC_VDD_IDLE_MIN (Bitfield-Mask: 0x1f)               */
-#define DCDC_DCDC_VDD_REG_DCDC_VDD_ENABLE_HV_Pos (1UL)              /*!< DCDC_VDD_ENABLE_HV (Bit 1)                            */
-#define DCDC_DCDC_VDD_REG_DCDC_VDD_ENABLE_HV_Msk (0x2UL)            /*!< DCDC_VDD_ENABLE_HV (Bitfield-Mask: 0x01)              */
-#define DCDC_DCDC_VDD_REG_DCDC_VDD_ENABLE_LV_Pos (0UL)              /*!< DCDC_VDD_ENABLE_LV (Bit 0)                            */
-#define DCDC_DCDC_VDD_REG_DCDC_VDD_ENABLE_LV_Msk (0x1UL)            /*!< DCDC_VDD_ENABLE_LV (Bitfield-Mask: 0x01)              */
-
-
-/* =========================================================================================================================== */
-/* ================                                            DMA                                            ================ */
-/* =========================================================================================================================== */
-
-/* ===================================================  DMA0_A_START_REG  ==================================================== */
-#define DMA_DMA0_A_START_REG_DMA0_A_START_Pos (0UL)                 /*!< DMA0_A_START (Bit 0)                                  */
-#define DMA_DMA0_A_START_REG_DMA0_A_START_Msk (0xffffffffUL)        /*!< DMA0_A_START (Bitfield-Mask: 0xffffffff)              */
-/* ===================================================  DMA0_B_START_REG  ==================================================== */
-#define DMA_DMA0_B_START_REG_DMA0_B_START_Pos (0UL)                 /*!< DMA0_B_START (Bit 0)                                  */
-#define DMA_DMA0_B_START_REG_DMA0_B_START_Msk (0xffffffffUL)        /*!< DMA0_B_START (Bitfield-Mask: 0xffffffff)              */
-/* =====================================================  DMA0_CTRL_REG  ===================================================== */
-#define DMA_DMA0_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL)               /*!< BUS_ERROR_DETECT (Bit 15)                             */
-#define DMA_DMA0_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL)           /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01)                */
-#define DMA_DMA0_CTRL_REG_BURST_MODE_Pos  (13UL)                    /*!< BURST_MODE (Bit 13)                                   */
-#define DMA_DMA0_CTRL_REG_BURST_MODE_Msk  (0x6000UL)                /*!< BURST_MODE (Bitfield-Mask: 0x03)                      */
-#define DMA_DMA0_CTRL_REG_REQ_SENSE_Pos   (12UL)                    /*!< REQ_SENSE (Bit 12)                                    */
-#define DMA_DMA0_CTRL_REG_REQ_SENSE_Msk   (0x1000UL)                /*!< REQ_SENSE (Bitfield-Mask: 0x01)                       */
-#define DMA_DMA0_CTRL_REG_DMA_INIT_Pos    (11UL)                    /*!< DMA_INIT (Bit 11)                                     */
-#define DMA_DMA0_CTRL_REG_DMA_INIT_Msk    (0x800UL)                 /*!< DMA_INIT (Bitfield-Mask: 0x01)                        */
-#define DMA_DMA0_CTRL_REG_DMA_IDLE_Pos    (10UL)                    /*!< DMA_IDLE (Bit 10)                                     */
-#define DMA_DMA0_CTRL_REG_DMA_IDLE_Msk    (0x400UL)                 /*!< DMA_IDLE (Bitfield-Mask: 0x01)                        */
-#define DMA_DMA0_CTRL_REG_DMA_PRIO_Pos    (7UL)                     /*!< DMA_PRIO (Bit 7)                                      */
-#define DMA_DMA0_CTRL_REG_DMA_PRIO_Msk    (0x380UL)                 /*!< DMA_PRIO (Bitfield-Mask: 0x07)                        */
-#define DMA_DMA0_CTRL_REG_CIRCULAR_Pos    (6UL)                     /*!< CIRCULAR (Bit 6)                                      */
-#define DMA_DMA0_CTRL_REG_CIRCULAR_Msk    (0x40UL)                  /*!< CIRCULAR (Bitfield-Mask: 0x01)                        */
-#define DMA_DMA0_CTRL_REG_AINC_Pos        (5UL)                     /*!< AINC (Bit 5)                                          */
-#define DMA_DMA0_CTRL_REG_AINC_Msk        (0x20UL)                  /*!< AINC (Bitfield-Mask: 0x01)                            */
-#define DMA_DMA0_CTRL_REG_BINC_Pos        (4UL)                     /*!< BINC (Bit 4)                                          */
-#define DMA_DMA0_CTRL_REG_BINC_Msk        (0x10UL)                  /*!< BINC (Bitfield-Mask: 0x01)                            */
-#define DMA_DMA0_CTRL_REG_DREQ_MODE_Pos   (3UL)                     /*!< DREQ_MODE (Bit 3)                                     */
-#define DMA_DMA0_CTRL_REG_DREQ_MODE_Msk   (0x8UL)                   /*!< DREQ_MODE (Bitfield-Mask: 0x01)                       */
-#define DMA_DMA0_CTRL_REG_BW_Pos          (1UL)                     /*!< BW (Bit 1)                                            */
-#define DMA_DMA0_CTRL_REG_BW_Msk          (0x6UL)                   /*!< BW (Bitfield-Mask: 0x03)                              */
-#define DMA_DMA0_CTRL_REG_DMA_ON_Pos      (0UL)                     /*!< DMA_ON (Bit 0)                                        */
-#define DMA_DMA0_CTRL_REG_DMA_ON_Msk      (0x1UL)                   /*!< DMA_ON (Bitfield-Mask: 0x01)                          */
-/* =====================================================  DMA0_IDX_REG  ====================================================== */
-#define DMA_DMA0_IDX_REG_DMA0_IDX_Pos     (0UL)                     /*!< DMA0_IDX (Bit 0)                                      */
-#define DMA_DMA0_IDX_REG_DMA0_IDX_Msk     (0xffffUL)                /*!< DMA0_IDX (Bitfield-Mask: 0xffff)                      */
-/* =====================================================  DMA0_INT_REG  ====================================================== */
-#define DMA_DMA0_INT_REG_DMA0_INT_Pos     (0UL)                     /*!< DMA0_INT (Bit 0)                                      */
-#define DMA_DMA0_INT_REG_DMA0_INT_Msk     (0xffffUL)                /*!< DMA0_INT (Bitfield-Mask: 0xffff)                      */
-/* =====================================================  DMA0_LEN_REG  ====================================================== */
-#define DMA_DMA0_LEN_REG_DMA0_LEN_Pos     (0UL)                     /*!< DMA0_LEN (Bit 0)                                      */
-#define DMA_DMA0_LEN_REG_DMA0_LEN_Msk     (0xffffUL)                /*!< DMA0_LEN (Bitfield-Mask: 0xffff)                      */
-/* ===================================================  DMA1_A_START_REG  ==================================================== */
-#define DMA_DMA1_A_START_REG_DMA1_A_START_Pos (0UL)                 /*!< DMA1_A_START (Bit 0)                                  */
-#define DMA_DMA1_A_START_REG_DMA1_A_START_Msk (0xffffffffUL)        /*!< DMA1_A_START (Bitfield-Mask: 0xffffffff)              */
-/* ===================================================  DMA1_B_START_REG  ==================================================== */
-#define DMA_DMA1_B_START_REG_DMA1_B_START_Pos (0UL)                 /*!< DMA1_B_START (Bit 0)                                  */
-#define DMA_DMA1_B_START_REG_DMA1_B_START_Msk (0xffffffffUL)        /*!< DMA1_B_START (Bitfield-Mask: 0xffffffff)              */
-/* =====================================================  DMA1_CTRL_REG  ===================================================== */
-#define DMA_DMA1_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL)               /*!< BUS_ERROR_DETECT (Bit 15)                             */
-#define DMA_DMA1_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL)           /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01)                */
-#define DMA_DMA1_CTRL_REG_BURST_MODE_Pos  (13UL)                    /*!< BURST_MODE (Bit 13)                                   */
-#define DMA_DMA1_CTRL_REG_BURST_MODE_Msk  (0x6000UL)                /*!< BURST_MODE (Bitfield-Mask: 0x03)                      */
-#define DMA_DMA1_CTRL_REG_REQ_SENSE_Pos   (12UL)                    /*!< REQ_SENSE (Bit 12)                                    */
-#define DMA_DMA1_CTRL_REG_REQ_SENSE_Msk   (0x1000UL)                /*!< REQ_SENSE (Bitfield-Mask: 0x01)                       */
-#define DMA_DMA1_CTRL_REG_DMA_INIT_Pos    (11UL)                    /*!< DMA_INIT (Bit 11)                                     */
-#define DMA_DMA1_CTRL_REG_DMA_INIT_Msk    (0x800UL)                 /*!< DMA_INIT (Bitfield-Mask: 0x01)                        */
-#define DMA_DMA1_CTRL_REG_DMA_IDLE_Pos    (10UL)                    /*!< DMA_IDLE (Bit 10)                                     */
-#define DMA_DMA1_CTRL_REG_DMA_IDLE_Msk    (0x400UL)                 /*!< DMA_IDLE (Bitfield-Mask: 0x01)                        */
-#define DMA_DMA1_CTRL_REG_DMA_PRIO_Pos    (7UL)                     /*!< DMA_PRIO (Bit 7)                                      */
-#define DMA_DMA1_CTRL_REG_DMA_PRIO_Msk    (0x380UL)                 /*!< DMA_PRIO (Bitfield-Mask: 0x07)                        */
-#define DMA_DMA1_CTRL_REG_CIRCULAR_Pos    (6UL)                     /*!< CIRCULAR (Bit 6)                                      */
-#define DMA_DMA1_CTRL_REG_CIRCULAR_Msk    (0x40UL)                  /*!< CIRCULAR (Bitfield-Mask: 0x01)                        */
-#define DMA_DMA1_CTRL_REG_AINC_Pos        (5UL)                     /*!< AINC (Bit 5)                                          */
-#define DMA_DMA1_CTRL_REG_AINC_Msk        (0x20UL)                  /*!< AINC (Bitfield-Mask: 0x01)                            */
-#define DMA_DMA1_CTRL_REG_BINC_Pos        (4UL)                     /*!< BINC (Bit 4)                                          */
-#define DMA_DMA1_CTRL_REG_BINC_Msk        (0x10UL)                  /*!< BINC (Bitfield-Mask: 0x01)                            */
-#define DMA_DMA1_CTRL_REG_DREQ_MODE_Pos   (3UL)                     /*!< DREQ_MODE (Bit 3)                                     */
-#define DMA_DMA1_CTRL_REG_DREQ_MODE_Msk   (0x8UL)                   /*!< DREQ_MODE (Bitfield-Mask: 0x01)                       */
-#define DMA_DMA1_CTRL_REG_BW_Pos          (1UL)                     /*!< BW (Bit 1)                                            */
-#define DMA_DMA1_CTRL_REG_BW_Msk          (0x6UL)                   /*!< BW (Bitfield-Mask: 0x03)                              */
-#define DMA_DMA1_CTRL_REG_DMA_ON_Pos      (0UL)                     /*!< DMA_ON (Bit 0)                                        */
-#define DMA_DMA1_CTRL_REG_DMA_ON_Msk      (0x1UL)                   /*!< DMA_ON (Bitfield-Mask: 0x01)                          */
-/* =====================================================  DMA1_IDX_REG  ====================================================== */
-#define DMA_DMA1_IDX_REG_DMA1_IDX_Pos     (0UL)                     /*!< DMA1_IDX (Bit 0)                                      */
-#define DMA_DMA1_IDX_REG_DMA1_IDX_Msk     (0xffffUL)                /*!< DMA1_IDX (Bitfield-Mask: 0xffff)                      */
-/* =====================================================  DMA1_INT_REG  ====================================================== */
-#define DMA_DMA1_INT_REG_DMA1_INT_Pos     (0UL)                     /*!< DMA1_INT (Bit 0)                                      */
-#define DMA_DMA1_INT_REG_DMA1_INT_Msk     (0xffffUL)                /*!< DMA1_INT (Bitfield-Mask: 0xffff)                      */
-/* =====================================================  DMA1_LEN_REG  ====================================================== */
-#define DMA_DMA1_LEN_REG_DMA1_LEN_Pos     (0UL)                     /*!< DMA1_LEN (Bit 0)                                      */
-#define DMA_DMA1_LEN_REG_DMA1_LEN_Msk     (0xffffUL)                /*!< DMA1_LEN (Bitfield-Mask: 0xffff)                      */
-/* ===================================================  DMA2_A_START_REG  ==================================================== */
-#define DMA_DMA2_A_START_REG_DMA2_A_START_Pos (0UL)                 /*!< DMA2_A_START (Bit 0)                                  */
-#define DMA_DMA2_A_START_REG_DMA2_A_START_Msk (0xffffffffUL)        /*!< DMA2_A_START (Bitfield-Mask: 0xffffffff)              */
-/* ===================================================  DMA2_B_START_REG  ==================================================== */
-#define DMA_DMA2_B_START_REG_DMA2_B_START_Pos (0UL)                 /*!< DMA2_B_START (Bit 0)                                  */
-#define DMA_DMA2_B_START_REG_DMA2_B_START_Msk (0xffffffffUL)        /*!< DMA2_B_START (Bitfield-Mask: 0xffffffff)              */
-/* =====================================================  DMA2_CTRL_REG  ===================================================== */
-#define DMA_DMA2_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL)               /*!< BUS_ERROR_DETECT (Bit 15)                             */
-#define DMA_DMA2_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL)           /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01)                */
-#define DMA_DMA2_CTRL_REG_BURST_MODE_Pos  (13UL)                    /*!< BURST_MODE (Bit 13)                                   */
-#define DMA_DMA2_CTRL_REG_BURST_MODE_Msk  (0x6000UL)                /*!< BURST_MODE (Bitfield-Mask: 0x03)                      */
-#define DMA_DMA2_CTRL_REG_REQ_SENSE_Pos   (12UL)                    /*!< REQ_SENSE (Bit 12)                                    */
-#define DMA_DMA2_CTRL_REG_REQ_SENSE_Msk   (0x1000UL)                /*!< REQ_SENSE (Bitfield-Mask: 0x01)                       */
-#define DMA_DMA2_CTRL_REG_DMA_INIT_Pos    (11UL)                    /*!< DMA_INIT (Bit 11)                                     */
-#define DMA_DMA2_CTRL_REG_DMA_INIT_Msk    (0x800UL)                 /*!< DMA_INIT (Bitfield-Mask: 0x01)                        */
-#define DMA_DMA2_CTRL_REG_DMA_IDLE_Pos    (10UL)                    /*!< DMA_IDLE (Bit 10)                                     */
-#define DMA_DMA2_CTRL_REG_DMA_IDLE_Msk    (0x400UL)                 /*!< DMA_IDLE (Bitfield-Mask: 0x01)                        */
-#define DMA_DMA2_CTRL_REG_DMA_PRIO_Pos    (7UL)                     /*!< DMA_PRIO (Bit 7)                                      */
-#define DMA_DMA2_CTRL_REG_DMA_PRIO_Msk    (0x380UL)                 /*!< DMA_PRIO (Bitfield-Mask: 0x07)                        */
-#define DMA_DMA2_CTRL_REG_CIRCULAR_Pos    (6UL)                     /*!< CIRCULAR (Bit 6)                                      */
-#define DMA_DMA2_CTRL_REG_CIRCULAR_Msk    (0x40UL)                  /*!< CIRCULAR (Bitfield-Mask: 0x01)                        */
-#define DMA_DMA2_CTRL_REG_AINC_Pos        (5UL)                     /*!< AINC (Bit 5)                                          */
-#define DMA_DMA2_CTRL_REG_AINC_Msk        (0x20UL)                  /*!< AINC (Bitfield-Mask: 0x01)                            */
-#define DMA_DMA2_CTRL_REG_BINC_Pos        (4UL)                     /*!< BINC (Bit 4)                                          */
-#define DMA_DMA2_CTRL_REG_BINC_Msk        (0x10UL)                  /*!< BINC (Bitfield-Mask: 0x01)                            */
-#define DMA_DMA2_CTRL_REG_DREQ_MODE_Pos   (3UL)                     /*!< DREQ_MODE (Bit 3)                                     */
-#define DMA_DMA2_CTRL_REG_DREQ_MODE_Msk   (0x8UL)                   /*!< DREQ_MODE (Bitfield-Mask: 0x01)                       */
-#define DMA_DMA2_CTRL_REG_BW_Pos          (1UL)                     /*!< BW (Bit 1)                                            */
-#define DMA_DMA2_CTRL_REG_BW_Msk          (0x6UL)                   /*!< BW (Bitfield-Mask: 0x03)                              */
-#define DMA_DMA2_CTRL_REG_DMA_ON_Pos      (0UL)                     /*!< DMA_ON (Bit 0)                                        */
-#define DMA_DMA2_CTRL_REG_DMA_ON_Msk      (0x1UL)                   /*!< DMA_ON (Bitfield-Mask: 0x01)                          */
-/* =====================================================  DMA2_IDX_REG  ====================================================== */
-#define DMA_DMA2_IDX_REG_DMA2_IDX_Pos     (0UL)                     /*!< DMA2_IDX (Bit 0)                                      */
-#define DMA_DMA2_IDX_REG_DMA2_IDX_Msk     (0xffffUL)                /*!< DMA2_IDX (Bitfield-Mask: 0xffff)                      */
-/* =====================================================  DMA2_INT_REG  ====================================================== */
-#define DMA_DMA2_INT_REG_DMA2_INT_Pos     (0UL)                     /*!< DMA2_INT (Bit 0)                                      */
-#define DMA_DMA2_INT_REG_DMA2_INT_Msk     (0xffffUL)                /*!< DMA2_INT (Bitfield-Mask: 0xffff)                      */
-/* =====================================================  DMA2_LEN_REG  ====================================================== */
-#define DMA_DMA2_LEN_REG_DMA2_LEN_Pos     (0UL)                     /*!< DMA2_LEN (Bit 0)                                      */
-#define DMA_DMA2_LEN_REG_DMA2_LEN_Msk     (0xffffUL)                /*!< DMA2_LEN (Bitfield-Mask: 0xffff)                      */
-/* ===================================================  DMA3_A_START_REG  ==================================================== */
-#define DMA_DMA3_A_START_REG_DMA3_A_START_Pos (0UL)                 /*!< DMA3_A_START (Bit 0)                                  */
-#define DMA_DMA3_A_START_REG_DMA3_A_START_Msk (0xffffffffUL)        /*!< DMA3_A_START (Bitfield-Mask: 0xffffffff)              */
-/* ===================================================  DMA3_B_START_REG  ==================================================== */
-#define DMA_DMA3_B_START_REG_DMA3_B_START_Pos (0UL)                 /*!< DMA3_B_START (Bit 0)                                  */
-#define DMA_DMA3_B_START_REG_DMA3_B_START_Msk (0xffffffffUL)        /*!< DMA3_B_START (Bitfield-Mask: 0xffffffff)              */
-/* =====================================================  DMA3_CTRL_REG  ===================================================== */
-#define DMA_DMA3_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL)               /*!< BUS_ERROR_DETECT (Bit 15)                             */
-#define DMA_DMA3_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL)           /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01)                */
-#define DMA_DMA3_CTRL_REG_BURST_MODE_Pos  (13UL)                    /*!< BURST_MODE (Bit 13)                                   */
-#define DMA_DMA3_CTRL_REG_BURST_MODE_Msk  (0x6000UL)                /*!< BURST_MODE (Bitfield-Mask: 0x03)                      */
-#define DMA_DMA3_CTRL_REG_REQ_SENSE_Pos   (12UL)                    /*!< REQ_SENSE (Bit 12)                                    */
-#define DMA_DMA3_CTRL_REG_REQ_SENSE_Msk   (0x1000UL)                /*!< REQ_SENSE (Bitfield-Mask: 0x01)                       */
-#define DMA_DMA3_CTRL_REG_DMA_INIT_Pos    (11UL)                    /*!< DMA_INIT (Bit 11)                                     */
-#define DMA_DMA3_CTRL_REG_DMA_INIT_Msk    (0x800UL)                 /*!< DMA_INIT (Bitfield-Mask: 0x01)                        */
-#define DMA_DMA3_CTRL_REG_DMA_IDLE_Pos    (10UL)                    /*!< DMA_IDLE (Bit 10)                                     */
-#define DMA_DMA3_CTRL_REG_DMA_IDLE_Msk    (0x400UL)                 /*!< DMA_IDLE (Bitfield-Mask: 0x01)                        */
-#define DMA_DMA3_CTRL_REG_DMA_PRIO_Pos    (7UL)                     /*!< DMA_PRIO (Bit 7)                                      */
-#define DMA_DMA3_CTRL_REG_DMA_PRIO_Msk    (0x380UL)                 /*!< DMA_PRIO (Bitfield-Mask: 0x07)                        */
-#define DMA_DMA3_CTRL_REG_CIRCULAR_Pos    (6UL)                     /*!< CIRCULAR (Bit 6)                                      */
-#define DMA_DMA3_CTRL_REG_CIRCULAR_Msk    (0x40UL)                  /*!< CIRCULAR (Bitfield-Mask: 0x01)                        */
-#define DMA_DMA3_CTRL_REG_AINC_Pos        (5UL)                     /*!< AINC (Bit 5)                                          */
-#define DMA_DMA3_CTRL_REG_AINC_Msk        (0x20UL)                  /*!< AINC (Bitfield-Mask: 0x01)                            */
-#define DMA_DMA3_CTRL_REG_BINC_Pos        (4UL)                     /*!< BINC (Bit 4)                                          */
-#define DMA_DMA3_CTRL_REG_BINC_Msk        (0x10UL)                  /*!< BINC (Bitfield-Mask: 0x01)                            */
-#define DMA_DMA3_CTRL_REG_DREQ_MODE_Pos   (3UL)                     /*!< DREQ_MODE (Bit 3)                                     */
-#define DMA_DMA3_CTRL_REG_DREQ_MODE_Msk   (0x8UL)                   /*!< DREQ_MODE (Bitfield-Mask: 0x01)                       */
-#define DMA_DMA3_CTRL_REG_BW_Pos          (1UL)                     /*!< BW (Bit 1)                                            */
-#define DMA_DMA3_CTRL_REG_BW_Msk          (0x6UL)                   /*!< BW (Bitfield-Mask: 0x03)                              */
-#define DMA_DMA3_CTRL_REG_DMA_ON_Pos      (0UL)                     /*!< DMA_ON (Bit 0)                                        */
-#define DMA_DMA3_CTRL_REG_DMA_ON_Msk      (0x1UL)                   /*!< DMA_ON (Bitfield-Mask: 0x01)                          */
-/* =====================================================  DMA3_IDX_REG  ====================================================== */
-#define DMA_DMA3_IDX_REG_DMA3_IDX_Pos     (0UL)                     /*!< DMA3_IDX (Bit 0)                                      */
-#define DMA_DMA3_IDX_REG_DMA3_IDX_Msk     (0xffffUL)                /*!< DMA3_IDX (Bitfield-Mask: 0xffff)                      */
-/* =====================================================  DMA3_INT_REG  ====================================================== */
-#define DMA_DMA3_INT_REG_DMA3_INT_Pos     (0UL)                     /*!< DMA3_INT (Bit 0)                                      */
-#define DMA_DMA3_INT_REG_DMA3_INT_Msk     (0xffffUL)                /*!< DMA3_INT (Bitfield-Mask: 0xffff)                      */
-/* =====================================================  DMA3_LEN_REG  ====================================================== */
-#define DMA_DMA3_LEN_REG_DMA3_LEN_Pos     (0UL)                     /*!< DMA3_LEN (Bit 0)                                      */
-#define DMA_DMA3_LEN_REG_DMA3_LEN_Msk     (0xffffUL)                /*!< DMA3_LEN (Bitfield-Mask: 0xffff)                      */
-/* ===================================================  DMA4_A_START_REG  ==================================================== */
-#define DMA_DMA4_A_START_REG_DMA4_A_START_Pos (0UL)                 /*!< DMA4_A_START (Bit 0)                                  */
-#define DMA_DMA4_A_START_REG_DMA4_A_START_Msk (0xffffffffUL)        /*!< DMA4_A_START (Bitfield-Mask: 0xffffffff)              */
-/* ===================================================  DMA4_B_START_REG  ==================================================== */
-#define DMA_DMA4_B_START_REG_DMA4_B_START_Pos (0UL)                 /*!< DMA4_B_START (Bit 0)                                  */
-#define DMA_DMA4_B_START_REG_DMA4_B_START_Msk (0xffffffffUL)        /*!< DMA4_B_START (Bitfield-Mask: 0xffffffff)              */
-/* =====================================================  DMA4_CTRL_REG  ===================================================== */
-#define DMA_DMA4_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL)               /*!< BUS_ERROR_DETECT (Bit 15)                             */
-#define DMA_DMA4_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL)           /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01)                */
-#define DMA_DMA4_CTRL_REG_BURST_MODE_Pos  (13UL)                    /*!< BURST_MODE (Bit 13)                                   */
-#define DMA_DMA4_CTRL_REG_BURST_MODE_Msk  (0x6000UL)                /*!< BURST_MODE (Bitfield-Mask: 0x03)                      */
-#define DMA_DMA4_CTRL_REG_REQ_SENSE_Pos   (12UL)                    /*!< REQ_SENSE (Bit 12)                                    */
-#define DMA_DMA4_CTRL_REG_REQ_SENSE_Msk   (0x1000UL)                /*!< REQ_SENSE (Bitfield-Mask: 0x01)                       */
-#define DMA_DMA4_CTRL_REG_DMA_INIT_Pos    (11UL)                    /*!< DMA_INIT (Bit 11)                                     */
-#define DMA_DMA4_CTRL_REG_DMA_INIT_Msk    (0x800UL)                 /*!< DMA_INIT (Bitfield-Mask: 0x01)                        */
-#define DMA_DMA4_CTRL_REG_DMA_IDLE_Pos    (10UL)                    /*!< DMA_IDLE (Bit 10)                                     */
-#define DMA_DMA4_CTRL_REG_DMA_IDLE_Msk    (0x400UL)                 /*!< DMA_IDLE (Bitfield-Mask: 0x01)                        */
-#define DMA_DMA4_CTRL_REG_DMA_PRIO_Pos    (7UL)                     /*!< DMA_PRIO (Bit 7)                                      */
-#define DMA_DMA4_CTRL_REG_DMA_PRIO_Msk    (0x380UL)                 /*!< DMA_PRIO (Bitfield-Mask: 0x07)                        */
-#define DMA_DMA4_CTRL_REG_CIRCULAR_Pos    (6UL)                     /*!< CIRCULAR (Bit 6)                                      */
-#define DMA_DMA4_CTRL_REG_CIRCULAR_Msk    (0x40UL)                  /*!< CIRCULAR (Bitfield-Mask: 0x01)                        */
-#define DMA_DMA4_CTRL_REG_AINC_Pos        (5UL)                     /*!< AINC (Bit 5)                                          */
-#define DMA_DMA4_CTRL_REG_AINC_Msk        (0x20UL)                  /*!< AINC (Bitfield-Mask: 0x01)                            */
-#define DMA_DMA4_CTRL_REG_BINC_Pos        (4UL)                     /*!< BINC (Bit 4)                                          */
-#define DMA_DMA4_CTRL_REG_BINC_Msk        (0x10UL)                  /*!< BINC (Bitfield-Mask: 0x01)                            */
-#define DMA_DMA4_CTRL_REG_DREQ_MODE_Pos   (3UL)                     /*!< DREQ_MODE (Bit 3)                                     */
-#define DMA_DMA4_CTRL_REG_DREQ_MODE_Msk   (0x8UL)                   /*!< DREQ_MODE (Bitfield-Mask: 0x01)                       */
-#define DMA_DMA4_CTRL_REG_BW_Pos          (1UL)                     /*!< BW (Bit 1)                                            */
-#define DMA_DMA4_CTRL_REG_BW_Msk          (0x6UL)                   /*!< BW (Bitfield-Mask: 0x03)                              */
-#define DMA_DMA4_CTRL_REG_DMA_ON_Pos      (0UL)                     /*!< DMA_ON (Bit 0)                                        */
-#define DMA_DMA4_CTRL_REG_DMA_ON_Msk      (0x1UL)                   /*!< DMA_ON (Bitfield-Mask: 0x01)                          */
-/* =====================================================  DMA4_IDX_REG  ====================================================== */
-#define DMA_DMA4_IDX_REG_DMA4_IDX_Pos     (0UL)                     /*!< DMA4_IDX (Bit 0)                                      */
-#define DMA_DMA4_IDX_REG_DMA4_IDX_Msk     (0xffffUL)                /*!< DMA4_IDX (Bitfield-Mask: 0xffff)                      */
-/* =====================================================  DMA4_INT_REG  ====================================================== */
-#define DMA_DMA4_INT_REG_DMA4_INT_Pos     (0UL)                     /*!< DMA4_INT (Bit 0)                                      */
-#define DMA_DMA4_INT_REG_DMA4_INT_Msk     (0xffffUL)                /*!< DMA4_INT (Bitfield-Mask: 0xffff)                      */
-/* =====================================================  DMA4_LEN_REG  ====================================================== */
-#define DMA_DMA4_LEN_REG_DMA4_LEN_Pos     (0UL)                     /*!< DMA4_LEN (Bit 0)                                      */
-#define DMA_DMA4_LEN_REG_DMA4_LEN_Msk     (0xffffUL)                /*!< DMA4_LEN (Bitfield-Mask: 0xffff)                      */
-/* ===================================================  DMA5_A_START_REG  ==================================================== */
-#define DMA_DMA5_A_START_REG_DMA5_A_START_Pos (0UL)                 /*!< DMA5_A_START (Bit 0)                                  */
-#define DMA_DMA5_A_START_REG_DMA5_A_START_Msk (0xffffffffUL)        /*!< DMA5_A_START (Bitfield-Mask: 0xffffffff)              */
-/* ===================================================  DMA5_B_START_REG  ==================================================== */
-#define DMA_DMA5_B_START_REG_DMA5_B_START_Pos (0UL)                 /*!< DMA5_B_START (Bit 0)                                  */
-#define DMA_DMA5_B_START_REG_DMA5_B_START_Msk (0xffffffffUL)        /*!< DMA5_B_START (Bitfield-Mask: 0xffffffff)              */
-/* =====================================================  DMA5_CTRL_REG  ===================================================== */
-#define DMA_DMA5_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL)               /*!< BUS_ERROR_DETECT (Bit 15)                             */
-#define DMA_DMA5_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL)           /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01)                */
-#define DMA_DMA5_CTRL_REG_BURST_MODE_Pos  (13UL)                    /*!< BURST_MODE (Bit 13)                                   */
-#define DMA_DMA5_CTRL_REG_BURST_MODE_Msk  (0x6000UL)                /*!< BURST_MODE (Bitfield-Mask: 0x03)                      */
-#define DMA_DMA5_CTRL_REG_REQ_SENSE_Pos   (12UL)                    /*!< REQ_SENSE (Bit 12)                                    */
-#define DMA_DMA5_CTRL_REG_REQ_SENSE_Msk   (0x1000UL)                /*!< REQ_SENSE (Bitfield-Mask: 0x01)                       */
-#define DMA_DMA5_CTRL_REG_DMA_INIT_Pos    (11UL)                    /*!< DMA_INIT (Bit 11)                                     */
-#define DMA_DMA5_CTRL_REG_DMA_INIT_Msk    (0x800UL)                 /*!< DMA_INIT (Bitfield-Mask: 0x01)                        */
-#define DMA_DMA5_CTRL_REG_DMA_IDLE_Pos    (10UL)                    /*!< DMA_IDLE (Bit 10)                                     */
-#define DMA_DMA5_CTRL_REG_DMA_IDLE_Msk    (0x400UL)                 /*!< DMA_IDLE (Bitfield-Mask: 0x01)                        */
-#define DMA_DMA5_CTRL_REG_DMA_PRIO_Pos    (7UL)                     /*!< DMA_PRIO (Bit 7)                                      */
-#define DMA_DMA5_CTRL_REG_DMA_PRIO_Msk    (0x380UL)                 /*!< DMA_PRIO (Bitfield-Mask: 0x07)                        */
-#define DMA_DMA5_CTRL_REG_CIRCULAR_Pos    (6UL)                     /*!< CIRCULAR (Bit 6)                                      */
-#define DMA_DMA5_CTRL_REG_CIRCULAR_Msk    (0x40UL)                  /*!< CIRCULAR (Bitfield-Mask: 0x01)                        */
-#define DMA_DMA5_CTRL_REG_AINC_Pos        (5UL)                     /*!< AINC (Bit 5)                                          */
-#define DMA_DMA5_CTRL_REG_AINC_Msk        (0x20UL)                  /*!< AINC (Bitfield-Mask: 0x01)                            */
-#define DMA_DMA5_CTRL_REG_BINC_Pos        (4UL)                     /*!< BINC (Bit 4)                                          */
-#define DMA_DMA5_CTRL_REG_BINC_Msk        (0x10UL)                  /*!< BINC (Bitfield-Mask: 0x01)                            */
-#define DMA_DMA5_CTRL_REG_DREQ_MODE_Pos   (3UL)                     /*!< DREQ_MODE (Bit 3)                                     */
-#define DMA_DMA5_CTRL_REG_DREQ_MODE_Msk   (0x8UL)                   /*!< DREQ_MODE (Bitfield-Mask: 0x01)                       */
-#define DMA_DMA5_CTRL_REG_BW_Pos          (1UL)                     /*!< BW (Bit 1)                                            */
-#define DMA_DMA5_CTRL_REG_BW_Msk          (0x6UL)                   /*!< BW (Bitfield-Mask: 0x03)                              */
-#define DMA_DMA5_CTRL_REG_DMA_ON_Pos      (0UL)                     /*!< DMA_ON (Bit 0)                                        */
-#define DMA_DMA5_CTRL_REG_DMA_ON_Msk      (0x1UL)                   /*!< DMA_ON (Bitfield-Mask: 0x01)                          */
-/* =====================================================  DMA5_IDX_REG  ====================================================== */
-#define DMA_DMA5_IDX_REG_DMA5_IDX_Pos     (0UL)                     /*!< DMA5_IDX (Bit 0)                                      */
-#define DMA_DMA5_IDX_REG_DMA5_IDX_Msk     (0xffffUL)                /*!< DMA5_IDX (Bitfield-Mask: 0xffff)                      */
-/* =====================================================  DMA5_INT_REG  ====================================================== */
-#define DMA_DMA5_INT_REG_DMA5_INT_Pos     (0UL)                     /*!< DMA5_INT (Bit 0)                                      */
-#define DMA_DMA5_INT_REG_DMA5_INT_Msk     (0xffffUL)                /*!< DMA5_INT (Bitfield-Mask: 0xffff)                      */
-/* =====================================================  DMA5_LEN_REG  ====================================================== */
-#define DMA_DMA5_LEN_REG_DMA5_LEN_Pos     (0UL)                     /*!< DMA5_LEN (Bit 0)                                      */
-#define DMA_DMA5_LEN_REG_DMA5_LEN_Msk     (0xffffUL)                /*!< DMA5_LEN (Bitfield-Mask: 0xffff)                      */
-/* ===================================================  DMA6_A_START_REG  ==================================================== */
-#define DMA_DMA6_A_START_REG_DMA6_A_START_Pos (0UL)                 /*!< DMA6_A_START (Bit 0)                                  */
-#define DMA_DMA6_A_START_REG_DMA6_A_START_Msk (0xffffffffUL)        /*!< DMA6_A_START (Bitfield-Mask: 0xffffffff)              */
-/* ===================================================  DMA6_B_START_REG  ==================================================== */
-#define DMA_DMA6_B_START_REG_DMA6_B_START_Pos (0UL)                 /*!< DMA6_B_START (Bit 0)                                  */
-#define DMA_DMA6_B_START_REG_DMA6_B_START_Msk (0xffffffffUL)        /*!< DMA6_B_START (Bitfield-Mask: 0xffffffff)              */
-/* =====================================================  DMA6_CTRL_REG  ===================================================== */
-#define DMA_DMA6_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL)               /*!< BUS_ERROR_DETECT (Bit 15)                             */
-#define DMA_DMA6_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL)           /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01)                */
-#define DMA_DMA6_CTRL_REG_BURST_MODE_Pos  (13UL)                    /*!< BURST_MODE (Bit 13)                                   */
-#define DMA_DMA6_CTRL_REG_BURST_MODE_Msk  (0x6000UL)                /*!< BURST_MODE (Bitfield-Mask: 0x03)                      */
-#define DMA_DMA6_CTRL_REG_REQ_SENSE_Pos   (12UL)                    /*!< REQ_SENSE (Bit 12)                                    */
-#define DMA_DMA6_CTRL_REG_REQ_SENSE_Msk   (0x1000UL)                /*!< REQ_SENSE (Bitfield-Mask: 0x01)                       */
-#define DMA_DMA6_CTRL_REG_DMA_INIT_Pos    (11UL)                    /*!< DMA_INIT (Bit 11)                                     */
-#define DMA_DMA6_CTRL_REG_DMA_INIT_Msk    (0x800UL)                 /*!< DMA_INIT (Bitfield-Mask: 0x01)                        */
-#define DMA_DMA6_CTRL_REG_DMA_IDLE_Pos    (10UL)                    /*!< DMA_IDLE (Bit 10)                                     */
-#define DMA_DMA6_CTRL_REG_DMA_IDLE_Msk    (0x400UL)                 /*!< DMA_IDLE (Bitfield-Mask: 0x01)                        */
-#define DMA_DMA6_CTRL_REG_DMA_PRIO_Pos    (7UL)                     /*!< DMA_PRIO (Bit 7)                                      */
-#define DMA_DMA6_CTRL_REG_DMA_PRIO_Msk    (0x380UL)                 /*!< DMA_PRIO (Bitfield-Mask: 0x07)                        */
-#define DMA_DMA6_CTRL_REG_CIRCULAR_Pos    (6UL)                     /*!< CIRCULAR (Bit 6)                                      */
-#define DMA_DMA6_CTRL_REG_CIRCULAR_Msk    (0x40UL)                  /*!< CIRCULAR (Bitfield-Mask: 0x01)                        */
-#define DMA_DMA6_CTRL_REG_AINC_Pos        (5UL)                     /*!< AINC (Bit 5)                                          */
-#define DMA_DMA6_CTRL_REG_AINC_Msk        (0x20UL)                  /*!< AINC (Bitfield-Mask: 0x01)                            */
-#define DMA_DMA6_CTRL_REG_BINC_Pos        (4UL)                     /*!< BINC (Bit 4)                                          */
-#define DMA_DMA6_CTRL_REG_BINC_Msk        (0x10UL)                  /*!< BINC (Bitfield-Mask: 0x01)                            */
-#define DMA_DMA6_CTRL_REG_DREQ_MODE_Pos   (3UL)                     /*!< DREQ_MODE (Bit 3)                                     */
-#define DMA_DMA6_CTRL_REG_DREQ_MODE_Msk   (0x8UL)                   /*!< DREQ_MODE (Bitfield-Mask: 0x01)                       */
-#define DMA_DMA6_CTRL_REG_BW_Pos          (1UL)                     /*!< BW (Bit 1)                                            */
-#define DMA_DMA6_CTRL_REG_BW_Msk          (0x6UL)                   /*!< BW (Bitfield-Mask: 0x03)                              */
-#define DMA_DMA6_CTRL_REG_DMA_ON_Pos      (0UL)                     /*!< DMA_ON (Bit 0)                                        */
-#define DMA_DMA6_CTRL_REG_DMA_ON_Msk      (0x1UL)                   /*!< DMA_ON (Bitfield-Mask: 0x01)                          */
-/* =====================================================  DMA6_IDX_REG  ====================================================== */
-#define DMA_DMA6_IDX_REG_DMA6_IDX_Pos     (0UL)                     /*!< DMA6_IDX (Bit 0)                                      */
-#define DMA_DMA6_IDX_REG_DMA6_IDX_Msk     (0xffffUL)                /*!< DMA6_IDX (Bitfield-Mask: 0xffff)                      */
-/* =====================================================  DMA6_INT_REG  ====================================================== */
-#define DMA_DMA6_INT_REG_DMA6_INT_Pos     (0UL)                     /*!< DMA6_INT (Bit 0)                                      */
-#define DMA_DMA6_INT_REG_DMA6_INT_Msk     (0xffffUL)                /*!< DMA6_INT (Bitfield-Mask: 0xffff)                      */
-/* =====================================================  DMA6_LEN_REG  ====================================================== */
-#define DMA_DMA6_LEN_REG_DMA6_LEN_Pos     (0UL)                     /*!< DMA6_LEN (Bit 0)                                      */
-#define DMA_DMA6_LEN_REG_DMA6_LEN_Msk     (0xffffUL)                /*!< DMA6_LEN (Bitfield-Mask: 0xffff)                      */
-/* ===================================================  DMA7_A_START_REG  ==================================================== */
-#define DMA_DMA7_A_START_REG_DMA7_A_START_Pos (0UL)                 /*!< DMA7_A_START (Bit 0)                                  */
-#define DMA_DMA7_A_START_REG_DMA7_A_START_Msk (0xffffffffUL)        /*!< DMA7_A_START (Bitfield-Mask: 0xffffffff)              */
-/* ===================================================  DMA7_B_START_REG  ==================================================== */
-#define DMA_DMA7_B_START_REG_DMA7_B_START_Pos (0UL)                 /*!< DMA7_B_START (Bit 0)                                  */
-#define DMA_DMA7_B_START_REG_DMA7_B_START_Msk (0xffffffffUL)        /*!< DMA7_B_START (Bitfield-Mask: 0xffffffff)              */
-/* =====================================================  DMA7_CTRL_REG  ===================================================== */
-#define DMA_DMA7_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL)               /*!< BUS_ERROR_DETECT (Bit 15)                             */
-#define DMA_DMA7_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL)           /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01)                */
-#define DMA_DMA7_CTRL_REG_BURST_MODE_Pos  (13UL)                    /*!< BURST_MODE (Bit 13)                                   */
-#define DMA_DMA7_CTRL_REG_BURST_MODE_Msk  (0x6000UL)                /*!< BURST_MODE (Bitfield-Mask: 0x03)                      */
-#define DMA_DMA7_CTRL_REG_REQ_SENSE_Pos   (12UL)                    /*!< REQ_SENSE (Bit 12)                                    */
-#define DMA_DMA7_CTRL_REG_REQ_SENSE_Msk   (0x1000UL)                /*!< REQ_SENSE (Bitfield-Mask: 0x01)                       */
-#define DMA_DMA7_CTRL_REG_DMA_INIT_Pos    (11UL)                    /*!< DMA_INIT (Bit 11)                                     */
-#define DMA_DMA7_CTRL_REG_DMA_INIT_Msk    (0x800UL)                 /*!< DMA_INIT (Bitfield-Mask: 0x01)                        */
-#define DMA_DMA7_CTRL_REG_DMA_IDLE_Pos    (10UL)                    /*!< DMA_IDLE (Bit 10)                                     */
-#define DMA_DMA7_CTRL_REG_DMA_IDLE_Msk    (0x400UL)                 /*!< DMA_IDLE (Bitfield-Mask: 0x01)                        */
-#define DMA_DMA7_CTRL_REG_DMA_PRIO_Pos    (7UL)                     /*!< DMA_PRIO (Bit 7)                                      */
-#define DMA_DMA7_CTRL_REG_DMA_PRIO_Msk    (0x380UL)                 /*!< DMA_PRIO (Bitfield-Mask: 0x07)                        */
-#define DMA_DMA7_CTRL_REG_CIRCULAR_Pos    (6UL)                     /*!< CIRCULAR (Bit 6)                                      */
-#define DMA_DMA7_CTRL_REG_CIRCULAR_Msk    (0x40UL)                  /*!< CIRCULAR (Bitfield-Mask: 0x01)                        */
-#define DMA_DMA7_CTRL_REG_AINC_Pos        (5UL)                     /*!< AINC (Bit 5)                                          */
-#define DMA_DMA7_CTRL_REG_AINC_Msk        (0x20UL)                  /*!< AINC (Bitfield-Mask: 0x01)                            */
-#define DMA_DMA7_CTRL_REG_BINC_Pos        (4UL)                     /*!< BINC (Bit 4)                                          */
-#define DMA_DMA7_CTRL_REG_BINC_Msk        (0x10UL)                  /*!< BINC (Bitfield-Mask: 0x01)                            */
-#define DMA_DMA7_CTRL_REG_DREQ_MODE_Pos   (3UL)                     /*!< DREQ_MODE (Bit 3)                                     */
-#define DMA_DMA7_CTRL_REG_DREQ_MODE_Msk   (0x8UL)                   /*!< DREQ_MODE (Bitfield-Mask: 0x01)                       */
-#define DMA_DMA7_CTRL_REG_BW_Pos          (1UL)                     /*!< BW (Bit 1)                                            */
-#define DMA_DMA7_CTRL_REG_BW_Msk          (0x6UL)                   /*!< BW (Bitfield-Mask: 0x03)                              */
-#define DMA_DMA7_CTRL_REG_DMA_ON_Pos      (0UL)                     /*!< DMA_ON (Bit 0)                                        */
-#define DMA_DMA7_CTRL_REG_DMA_ON_Msk      (0x1UL)                   /*!< DMA_ON (Bitfield-Mask: 0x01)                          */
-/* =====================================================  DMA7_IDX_REG  ====================================================== */
-#define DMA_DMA7_IDX_REG_DMA7_IDX_Pos     (0UL)                     /*!< DMA7_IDX (Bit 0)                                      */
-#define DMA_DMA7_IDX_REG_DMA7_IDX_Msk     (0xffffUL)                /*!< DMA7_IDX (Bitfield-Mask: 0xffff)                      */
-/* =====================================================  DMA7_INT_REG  ====================================================== */
-#define DMA_DMA7_INT_REG_DMA7_INT_Pos     (0UL)                     /*!< DMA7_INT (Bit 0)                                      */
-#define DMA_DMA7_INT_REG_DMA7_INT_Msk     (0xffffUL)                /*!< DMA7_INT (Bitfield-Mask: 0xffff)                      */
-/* =====================================================  DMA7_LEN_REG  ====================================================== */
-#define DMA_DMA7_LEN_REG_DMA7_LEN_Pos     (0UL)                     /*!< DMA7_LEN (Bit 0)                                      */
-#define DMA_DMA7_LEN_REG_DMA7_LEN_Msk     (0xffffUL)                /*!< DMA7_LEN (Bitfield-Mask: 0xffff)                      */
-/* ===================================================  DMA_CLEAR_INT_REG  =================================================== */
-#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH7_Pos (7UL)             /*!< DMA_RST_IRQ_CH7 (Bit 7)                               */
-#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH7_Msk (0x80UL)          /*!< DMA_RST_IRQ_CH7 (Bitfield-Mask: 0x01)                 */
-#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH6_Pos (6UL)             /*!< DMA_RST_IRQ_CH6 (Bit 6)                               */
-#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH6_Msk (0x40UL)          /*!< DMA_RST_IRQ_CH6 (Bitfield-Mask: 0x01)                 */
-#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH5_Pos (5UL)             /*!< DMA_RST_IRQ_CH5 (Bit 5)                               */
-#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH5_Msk (0x20UL)          /*!< DMA_RST_IRQ_CH5 (Bitfield-Mask: 0x01)                 */
-#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH4_Pos (4UL)             /*!< DMA_RST_IRQ_CH4 (Bit 4)                               */
-#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH4_Msk (0x10UL)          /*!< DMA_RST_IRQ_CH4 (Bitfield-Mask: 0x01)                 */
-#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH3_Pos (3UL)             /*!< DMA_RST_IRQ_CH3 (Bit 3)                               */
-#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH3_Msk (0x8UL)           /*!< DMA_RST_IRQ_CH3 (Bitfield-Mask: 0x01)                 */
-#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH2_Pos (2UL)             /*!< DMA_RST_IRQ_CH2 (Bit 2)                               */
-#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH2_Msk (0x4UL)           /*!< DMA_RST_IRQ_CH2 (Bitfield-Mask: 0x01)                 */
-#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH1_Pos (1UL)             /*!< DMA_RST_IRQ_CH1 (Bit 1)                               */
-#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH1_Msk (0x2UL)           /*!< DMA_RST_IRQ_CH1 (Bitfield-Mask: 0x01)                 */
-#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH0_Pos (0UL)             /*!< DMA_RST_IRQ_CH0 (Bit 0)                               */
-#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH0_Msk (0x1UL)           /*!< DMA_RST_IRQ_CH0 (Bitfield-Mask: 0x01)                 */
-/* ===================================================  DMA_INT_MASK_REG  ==================================================== */
-#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE7_Pos (7UL)              /*!< DMA_IRQ_ENABLE7 (Bit 7)                               */
-#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE7_Msk (0x80UL)           /*!< DMA_IRQ_ENABLE7 (Bitfield-Mask: 0x01)                 */
-#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE6_Pos (6UL)              /*!< DMA_IRQ_ENABLE6 (Bit 6)                               */
-#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE6_Msk (0x40UL)           /*!< DMA_IRQ_ENABLE6 (Bitfield-Mask: 0x01)                 */
-#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE5_Pos (5UL)              /*!< DMA_IRQ_ENABLE5 (Bit 5)                               */
-#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE5_Msk (0x20UL)           /*!< DMA_IRQ_ENABLE5 (Bitfield-Mask: 0x01)                 */
-#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE4_Pos (4UL)              /*!< DMA_IRQ_ENABLE4 (Bit 4)                               */
-#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE4_Msk (0x10UL)           /*!< DMA_IRQ_ENABLE4 (Bitfield-Mask: 0x01)                 */
-#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE3_Pos (3UL)              /*!< DMA_IRQ_ENABLE3 (Bit 3)                               */
-#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE3_Msk (0x8UL)            /*!< DMA_IRQ_ENABLE3 (Bitfield-Mask: 0x01)                 */
-#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE2_Pos (2UL)              /*!< DMA_IRQ_ENABLE2 (Bit 2)                               */
-#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE2_Msk (0x4UL)            /*!< DMA_IRQ_ENABLE2 (Bitfield-Mask: 0x01)                 */
-#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE1_Pos (1UL)              /*!< DMA_IRQ_ENABLE1 (Bit 1)                               */
-#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE1_Msk (0x2UL)            /*!< DMA_IRQ_ENABLE1 (Bitfield-Mask: 0x01)                 */
-#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE0_Pos (0UL)              /*!< DMA_IRQ_ENABLE0 (Bit 0)                               */
-#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE0_Msk (0x1UL)            /*!< DMA_IRQ_ENABLE0 (Bitfield-Mask: 0x01)                 */
-/* ==================================================  DMA_INT_STATUS_REG  =================================================== */
-#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR7_Pos (15UL)              /*!< DMA_BUS_ERR7 (Bit 15)                                 */
-#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR7_Msk (0x8000UL)          /*!< DMA_BUS_ERR7 (Bitfield-Mask: 0x01)                    */
-#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR6_Pos (14UL)              /*!< DMA_BUS_ERR6 (Bit 14)                                 */
-#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR6_Msk (0x4000UL)          /*!< DMA_BUS_ERR6 (Bitfield-Mask: 0x01)                    */
-#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR5_Pos (13UL)              /*!< DMA_BUS_ERR5 (Bit 13)                                 */
-#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR5_Msk (0x2000UL)          /*!< DMA_BUS_ERR5 (Bitfield-Mask: 0x01)                    */
-#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR4_Pos (12UL)              /*!< DMA_BUS_ERR4 (Bit 12)                                 */
-#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR4_Msk (0x1000UL)          /*!< DMA_BUS_ERR4 (Bitfield-Mask: 0x01)                    */
-#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR3_Pos (11UL)              /*!< DMA_BUS_ERR3 (Bit 11)                                 */
-#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR3_Msk (0x800UL)           /*!< DMA_BUS_ERR3 (Bitfield-Mask: 0x01)                    */
-#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR2_Pos (10UL)              /*!< DMA_BUS_ERR2 (Bit 10)                                 */
-#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR2_Msk (0x400UL)           /*!< DMA_BUS_ERR2 (Bitfield-Mask: 0x01)                    */
-#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR1_Pos (9UL)               /*!< DMA_BUS_ERR1 (Bit 9)                                  */
-#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR1_Msk (0x200UL)           /*!< DMA_BUS_ERR1 (Bitfield-Mask: 0x01)                    */
-#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR0_Pos (8UL)               /*!< DMA_BUS_ERR0 (Bit 8)                                  */
-#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR0_Msk (0x100UL)           /*!< DMA_BUS_ERR0 (Bitfield-Mask: 0x01)                    */
-#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH7_Pos (7UL)                /*!< DMA_IRQ_CH7 (Bit 7)                                   */
-#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH7_Msk (0x80UL)             /*!< DMA_IRQ_CH7 (Bitfield-Mask: 0x01)                     */
-#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH6_Pos (6UL)                /*!< DMA_IRQ_CH6 (Bit 6)                                   */
-#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH6_Msk (0x40UL)             /*!< DMA_IRQ_CH6 (Bitfield-Mask: 0x01)                     */
-#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH5_Pos (5UL)                /*!< DMA_IRQ_CH5 (Bit 5)                                   */
-#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH5_Msk (0x20UL)             /*!< DMA_IRQ_CH5 (Bitfield-Mask: 0x01)                     */
-#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH4_Pos (4UL)                /*!< DMA_IRQ_CH4 (Bit 4)                                   */
-#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH4_Msk (0x10UL)             /*!< DMA_IRQ_CH4 (Bitfield-Mask: 0x01)                     */
-#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH3_Pos (3UL)                /*!< DMA_IRQ_CH3 (Bit 3)                                   */
-#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH3_Msk (0x8UL)              /*!< DMA_IRQ_CH3 (Bitfield-Mask: 0x01)                     */
-#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH2_Pos (2UL)                /*!< DMA_IRQ_CH2 (Bit 2)                                   */
-#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH2_Msk (0x4UL)              /*!< DMA_IRQ_CH2 (Bitfield-Mask: 0x01)                     */
-#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH1_Pos (1UL)                /*!< DMA_IRQ_CH1 (Bit 1)                                   */
-#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH1_Msk (0x2UL)              /*!< DMA_IRQ_CH1 (Bitfield-Mask: 0x01)                     */
-#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH0_Pos (0UL)                /*!< DMA_IRQ_CH0 (Bit 0)                                   */
-#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH0_Msk (0x1UL)              /*!< DMA_IRQ_CH0 (Bitfield-Mask: 0x01)                     */
-/* ====================================================  DMA_REQ_MUX_REG  ==================================================== */
-#define DMA_DMA_REQ_MUX_REG_DMA67_SEL_Pos (12UL)                    /*!< DMA67_SEL (Bit 12)                                    */
-#define DMA_DMA_REQ_MUX_REG_DMA67_SEL_Msk (0xf000UL)                /*!< DMA67_SEL (Bitfield-Mask: 0x0f)                       */
-#define DMA_DMA_REQ_MUX_REG_DMA45_SEL_Pos (8UL)                     /*!< DMA45_SEL (Bit 8)                                     */
-#define DMA_DMA_REQ_MUX_REG_DMA45_SEL_Msk (0xf00UL)                 /*!< DMA45_SEL (Bitfield-Mask: 0x0f)                       */
-#define DMA_DMA_REQ_MUX_REG_DMA23_SEL_Pos (4UL)                     /*!< DMA23_SEL (Bit 4)                                     */
-#define DMA_DMA_REQ_MUX_REG_DMA23_SEL_Msk (0xf0UL)                  /*!< DMA23_SEL (Bitfield-Mask: 0x0f)                       */
-#define DMA_DMA_REQ_MUX_REG_DMA01_SEL_Pos (0UL)                     /*!< DMA01_SEL (Bit 0)                                     */
-#define DMA_DMA_REQ_MUX_REG_DMA01_SEL_Msk (0xfUL)                   /*!< DMA01_SEL (Bitfield-Mask: 0x0f)                       */
-
-
-/* =========================================================================================================================== */
-/* ================                                            DW                                             ================ */
-/* =========================================================================================================================== */
-
-/* ===================================================  AHB_DMA_CCLM1_REG  =================================================== */
-#define DW_AHB_DMA_CCLM1_REG_AHB_DMA_CCLM_Pos (0UL)                 /*!< AHB_DMA_CCLM (Bit 0)                                  */
-#define DW_AHB_DMA_CCLM1_REG_AHB_DMA_CCLM_Msk (0xffffUL)            /*!< AHB_DMA_CCLM (Bitfield-Mask: 0xffff)                  */
-/* ===================================================  AHB_DMA_CCLM2_REG  =================================================== */
-#define DW_AHB_DMA_CCLM2_REG_AHB_DMA_CCLM_Pos (0UL)                 /*!< AHB_DMA_CCLM (Bit 0)                                  */
-#define DW_AHB_DMA_CCLM2_REG_AHB_DMA_CCLM_Msk (0xffffUL)            /*!< AHB_DMA_CCLM (Bitfield-Mask: 0xffff)                  */
-/* ===================================================  AHB_DMA_CCLM3_REG  =================================================== */
-#define DW_AHB_DMA_CCLM3_REG_AHB_DMA_CCLM_Pos (0UL)                 /*!< AHB_DMA_CCLM (Bit 0)                                  */
-#define DW_AHB_DMA_CCLM3_REG_AHB_DMA_CCLM_Msk (0xffffUL)            /*!< AHB_DMA_CCLM (Bitfield-Mask: 0xffff)                  */
-/* ===================================================  AHB_DMA_CCLM4_REG  =================================================== */
-#define DW_AHB_DMA_CCLM4_REG_AHB_DMA_CCLM_Pos (0UL)                 /*!< AHB_DMA_CCLM (Bit 0)                                  */
-#define DW_AHB_DMA_CCLM4_REG_AHB_DMA_CCLM_Msk (0xffffUL)            /*!< AHB_DMA_CCLM (Bitfield-Mask: 0xffff)                  */
-/* ================================================  AHB_DMA_DFLT_MASTER_REG  ================================================ */
-#define DW_AHB_DMA_DFLT_MASTER_REG_AHB_DMA_DFLT_MASTER_Pos (0UL)    /*!< AHB_DMA_DFLT_MASTER (Bit 0)                           */
-#define DW_AHB_DMA_DFLT_MASTER_REG_AHB_DMA_DFLT_MASTER_Msk (0xfUL)  /*!< AHB_DMA_DFLT_MASTER (Bitfield-Mask: 0x0f)             */
-/* ====================================================  AHB_DMA_PL1_REG  ==================================================== */
-#define DW_AHB_DMA_PL1_REG_AHB_DMA_PL1_Pos (0UL)                    /*!< AHB_DMA_PL1 (Bit 0)                                   */
-#define DW_AHB_DMA_PL1_REG_AHB_DMA_PL1_Msk (0xfUL)                  /*!< AHB_DMA_PL1 (Bitfield-Mask: 0x0f)                     */
-/* ====================================================  AHB_DMA_PL2_REG  ==================================================== */
-#define DW_AHB_DMA_PL2_REG_AHB_DMA_PL2_Pos (0UL)                    /*!< AHB_DMA_PL2 (Bit 0)                                   */
-#define DW_AHB_DMA_PL2_REG_AHB_DMA_PL2_Msk (0xfUL)                  /*!< AHB_DMA_PL2 (Bitfield-Mask: 0x0f)                     */
-/* ====================================================  AHB_DMA_PL3_REG  ==================================================== */
-#define DW_AHB_DMA_PL3_REG_AHB_DMA_PL3_Pos (0UL)                    /*!< AHB_DMA_PL3 (Bit 0)                                   */
-#define DW_AHB_DMA_PL3_REG_AHB_DMA_PL3_Msk (0xfUL)                  /*!< AHB_DMA_PL3 (Bitfield-Mask: 0x0f)                     */
-/* ====================================================  AHB_DMA_PL4_REG  ==================================================== */
-#define DW_AHB_DMA_PL4_REG_AHB_DMA_PL4_Pos (0UL)                    /*!< AHB_DMA_PL4 (Bit 0)                                   */
-#define DW_AHB_DMA_PL4_REG_AHB_DMA_PL4_Msk (0xfUL)                  /*!< AHB_DMA_PL4 (Bitfield-Mask: 0x0f)                     */
-/* ====================================================  AHB_DMA_TCL_REG  ==================================================== */
-#define DW_AHB_DMA_TCL_REG_AHB_DMA_TCL_Pos (0UL)                    /*!< AHB_DMA_TCL (Bit 0)                                   */
-#define DW_AHB_DMA_TCL_REG_AHB_DMA_TCL_Msk (0xffffUL)               /*!< AHB_DMA_TCL (Bitfield-Mask: 0xffff)                   */
-/* ==================================================  AHB_DMA_VERSION_REG  ================================================== */
-#define DW_AHB_DMA_VERSION_REG_AHB_DMA_VERSION_Pos (0UL)            /*!< AHB_DMA_VERSION (Bit 0)                               */
-#define DW_AHB_DMA_VERSION_REG_AHB_DMA_VERSION_Msk (0xffffffffUL)   /*!< AHB_DMA_VERSION (Bitfield-Mask: 0xffffffff)           */
-/* ===================================================  AHB_DMA_WTEN_REG  ==================================================== */
-#define DW_AHB_DMA_WTEN_REG_AHB_DMA_WTEN_Pos (0UL)                  /*!< AHB_DMA_WTEN (Bit 0)                                  */
-#define DW_AHB_DMA_WTEN_REG_AHB_DMA_WTEN_Msk (0x1UL)                /*!< AHB_DMA_WTEN (Bitfield-Mask: 0x01)                    */
-
-
-/* =========================================================================================================================== */
-/* ================                                           GPADC                                           ================ */
-/* =========================================================================================================================== */
-
-/* =================================================  GP_ADC_CLEAR_INT_REG  ================================================== */
-#define GPADC_GP_ADC_CLEAR_INT_REG_GP_ADC_CLR_INT_Pos (0UL)         /*!< GP_ADC_CLR_INT (Bit 0)                                */
-#define GPADC_GP_ADC_CLEAR_INT_REG_GP_ADC_CLR_INT_Msk (0xffffUL)    /*!< GP_ADC_CLR_INT (Bitfield-Mask: 0xffff)                */
-/* ===================================================  GP_ADC_CTRL2_REG  ==================================================== */
-#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_STORE_DEL_Pos (12UL)          /*!< GP_ADC_STORE_DEL (Bit 12)                             */
-#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_STORE_DEL_Msk (0xf000UL)      /*!< GP_ADC_STORE_DEL (Bitfield-Mask: 0x0f)                */
-#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_SMPL_TIME_Pos (8UL)           /*!< GP_ADC_SMPL_TIME (Bit 8)                              */
-#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_SMPL_TIME_Msk (0xf00UL)       /*!< GP_ADC_SMPL_TIME (Bitfield-Mask: 0x0f)                */
-#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_CONV_NRS_Pos (5UL)            /*!< GP_ADC_CONV_NRS (Bit 5)                               */
-#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_CONV_NRS_Msk (0xe0UL)         /*!< GP_ADC_CONV_NRS (Bitfield-Mask: 0x07)                 */
-#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_DMA_EN_Pos (3UL)              /*!< GP_ADC_DMA_EN (Bit 3)                                 */
-#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_DMA_EN_Msk (0x8UL)            /*!< GP_ADC_DMA_EN (Bitfield-Mask: 0x01)                   */
-#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_I20U_Pos (2UL)                /*!< GP_ADC_I20U (Bit 2)                                   */
-#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_I20U_Msk (0x4UL)              /*!< GP_ADC_I20U (Bitfield-Mask: 0x01)                     */
-#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_IDYN_Pos (1UL)                /*!< GP_ADC_IDYN (Bit 1)                                   */
-#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_IDYN_Msk (0x2UL)              /*!< GP_ADC_IDYN (Bitfield-Mask: 0x01)                     */
-#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_ATTN3X_Pos (0UL)              /*!< GP_ADC_ATTN3X (Bit 0)                                 */
-#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_ATTN3X_Msk (0x1UL)            /*!< GP_ADC_ATTN3X (Bitfield-Mask: 0x01)                   */
-/* ===================================================  GP_ADC_CTRL3_REG  ==================================================== */
-#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_INTERVAL_Pos (8UL)            /*!< GP_ADC_INTERVAL (Bit 8)                               */
-#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_INTERVAL_Msk (0xff00UL)       /*!< GP_ADC_INTERVAL (Bitfield-Mask: 0xff)                 */
-#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_EN_DEL_Pos (0UL)              /*!< GP_ADC_EN_DEL (Bit 0)                                 */
-#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_EN_DEL_Msk (0xffUL)           /*!< GP_ADC_EN_DEL (Bitfield-Mask: 0xff)                   */
-/* ====================================================  GP_ADC_CTRL_REG  ==================================================== */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_DIFF_TEMP_EN_Pos (18UL)        /*!< GP_ADC_DIFF_TEMP_EN (Bit 18)                          */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_DIFF_TEMP_EN_Msk (0x40000UL)   /*!< GP_ADC_DIFF_TEMP_EN (Bitfield-Mask: 0x01)             */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_DIFF_TEMP_SEL_Pos (16UL)       /*!< GP_ADC_DIFF_TEMP_SEL (Bit 16)                         */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_DIFF_TEMP_SEL_Msk (0x30000UL)  /*!< GP_ADC_DIFF_TEMP_SEL (Bitfield-Mask: 0x03)            */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_LDO_ZERO_Pos (15UL)            /*!< GP_ADC_LDO_ZERO (Bit 15)                              */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_LDO_ZERO_Msk (0x8000UL)        /*!< GP_ADC_LDO_ZERO (Bitfield-Mask: 0x01)                 */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CHOP_Pos (14UL)                /*!< GP_ADC_CHOP (Bit 14)                                  */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CHOP_Msk (0x4000UL)            /*!< GP_ADC_CHOP (Bitfield-Mask: 0x01)                     */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SIGN_Pos (13UL)                /*!< GP_ADC_SIGN (Bit 13)                                  */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SIGN_Msk (0x2000UL)            /*!< GP_ADC_SIGN (Bitfield-Mask: 0x01)                     */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SEL_Pos (8UL)                  /*!< GP_ADC_SEL (Bit 8)                                    */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SEL_Msk (0x1f00UL)             /*!< GP_ADC_SEL (Bitfield-Mask: 0x1f)                      */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MUTE_Pos (7UL)                 /*!< GP_ADC_MUTE (Bit 7)                                   */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MUTE_Msk (0x80UL)              /*!< GP_ADC_MUTE (Bitfield-Mask: 0x01)                     */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SE_Pos (6UL)                   /*!< GP_ADC_SE (Bit 6)                                     */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SE_Msk (0x40UL)                /*!< GP_ADC_SE (Bitfield-Mask: 0x01)                       */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MINT_Pos (5UL)                 /*!< GP_ADC_MINT (Bit 5)                                   */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MINT_Msk (0x20UL)              /*!< GP_ADC_MINT (Bitfield-Mask: 0x01)                     */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_INT_Pos (4UL)                  /*!< GP_ADC_INT (Bit 4)                                    */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_INT_Msk (0x10UL)               /*!< GP_ADC_INT (Bitfield-Mask: 0x01)                      */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CLK_SEL_Pos (3UL)              /*!< GP_ADC_CLK_SEL (Bit 3)                                */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CLK_SEL_Msk (0x8UL)            /*!< GP_ADC_CLK_SEL (Bitfield-Mask: 0x01)                  */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CONT_Pos (2UL)                 /*!< GP_ADC_CONT (Bit 2)                                   */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CONT_Msk (0x4UL)               /*!< GP_ADC_CONT (Bitfield-Mask: 0x01)                     */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_START_Pos (1UL)                /*!< GP_ADC_START (Bit 1)                                  */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_START_Msk (0x2UL)              /*!< GP_ADC_START (Bitfield-Mask: 0x01)                    */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_EN_Pos (0UL)                   /*!< GP_ADC_EN (Bit 0)                                     */
-#define GPADC_GP_ADC_CTRL_REG_GP_ADC_EN_Msk (0x1UL)                 /*!< GP_ADC_EN (Bitfield-Mask: 0x01)                       */
-/* ====================================================  GP_ADC_OFFN_REG  ==================================================== */
-#define GPADC_GP_ADC_OFFN_REG_GP_ADC_OFFN_Pos (0UL)                 /*!< GP_ADC_OFFN (Bit 0)                                   */
-#define GPADC_GP_ADC_OFFN_REG_GP_ADC_OFFN_Msk (0x3ffUL)             /*!< GP_ADC_OFFN (Bitfield-Mask: 0x3ff)                    */
-/* ====================================================  GP_ADC_OFFP_REG  ==================================================== */
-#define GPADC_GP_ADC_OFFP_REG_GP_ADC_OFFP_Pos (0UL)                 /*!< GP_ADC_OFFP (Bit 0)                                   */
-#define GPADC_GP_ADC_OFFP_REG_GP_ADC_OFFP_Msk (0x3ffUL)             /*!< GP_ADC_OFFP (Bitfield-Mask: 0x3ff)                    */
-/* ===================================================  GP_ADC_RESULT_REG  =================================================== */
-#define GPADC_GP_ADC_RESULT_REG_GP_ADC_VAL_Pos (0UL)                /*!< GP_ADC_VAL (Bit 0)                                    */
-#define GPADC_GP_ADC_RESULT_REG_GP_ADC_VAL_Msk (0xffffUL)           /*!< GP_ADC_VAL (Bitfield-Mask: 0xffff)                    */
-
-
-/* =========================================================================================================================== */
-/* ================                                           GPIO                                            ================ */
-/* =========================================================================================================================== */
-
-/* ===================================================  GPIO_CLK_SEL_REG  ==================================================== */
-#define GPIO_GPIO_CLK_SEL_REG_DIVN_OUTPUT_EN_Pos (9UL)              /*!< DIVN_OUTPUT_EN (Bit 9)                                */
-#define GPIO_GPIO_CLK_SEL_REG_DIVN_OUTPUT_EN_Msk (0x200UL)          /*!< DIVN_OUTPUT_EN (Bitfield-Mask: 0x01)                  */
-#define GPIO_GPIO_CLK_SEL_REG_RC32M_OUTPUT_EN_Pos (8UL)             /*!< RC32M_OUTPUT_EN (Bit 8)                               */
-#define GPIO_GPIO_CLK_SEL_REG_RC32M_OUTPUT_EN_Msk (0x100UL)         /*!< RC32M_OUTPUT_EN (Bitfield-Mask: 0x01)                 */
-#define GPIO_GPIO_CLK_SEL_REG_XTAL32M_OUTPUT_EN_Pos (7UL)           /*!< XTAL32M_OUTPUT_EN (Bit 7)                             */
-#define GPIO_GPIO_CLK_SEL_REG_XTAL32M_OUTPUT_EN_Msk (0x80UL)        /*!< XTAL32M_OUTPUT_EN (Bitfield-Mask: 0x01)               */
-#define GPIO_GPIO_CLK_SEL_REG_RCX_OUTPUT_EN_Pos (6UL)               /*!< RCX_OUTPUT_EN (Bit 6)                                 */
-#define GPIO_GPIO_CLK_SEL_REG_RCX_OUTPUT_EN_Msk (0x40UL)            /*!< RCX_OUTPUT_EN (Bitfield-Mask: 0x01)                   */
-#define GPIO_GPIO_CLK_SEL_REG_RC32K_OUTPUT_EN_Pos (5UL)             /*!< RC32K_OUTPUT_EN (Bit 5)                               */
-#define GPIO_GPIO_CLK_SEL_REG_RC32K_OUTPUT_EN_Msk (0x20UL)          /*!< RC32K_OUTPUT_EN (Bitfield-Mask: 0x01)                 */
-#define GPIO_GPIO_CLK_SEL_REG_XTAL32K_OUTPUT_EN_Pos (4UL)           /*!< XTAL32K_OUTPUT_EN (Bit 4)                             */
-#define GPIO_GPIO_CLK_SEL_REG_XTAL32K_OUTPUT_EN_Msk (0x10UL)        /*!< XTAL32K_OUTPUT_EN (Bitfield-Mask: 0x01)               */
-#define GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_EN_Pos (3UL)               /*!< FUNC_CLOCK_EN (Bit 3)                                 */
-#define GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_EN_Msk (0x8UL)             /*!< FUNC_CLOCK_EN (Bitfield-Mask: 0x01)                   */
-#define GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_SEL_Pos (0UL)              /*!< FUNC_CLOCK_SEL (Bit 0)                                */
-#define GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_SEL_Msk (0x7UL)            /*!< FUNC_CLOCK_SEL (Bitfield-Mask: 0x07)                  */
-/* ====================================================  P0_00_MODE_REG  ===================================================== */
-#define GPIO_P0_00_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_00_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_00_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_00_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_00_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_00_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_01_MODE_REG  ===================================================== */
-#define GPIO_P0_01_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_01_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_01_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_01_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_01_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_01_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_02_MODE_REG  ===================================================== */
-#define GPIO_P0_02_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_02_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_02_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_02_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_02_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_02_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_03_MODE_REG  ===================================================== */
-#define GPIO_P0_03_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_03_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_03_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_03_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_03_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_03_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_04_MODE_REG  ===================================================== */
-#define GPIO_P0_04_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_04_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_04_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_04_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_04_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_04_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_05_MODE_REG  ===================================================== */
-#define GPIO_P0_05_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_05_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_05_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_05_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_05_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_05_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_06_MODE_REG  ===================================================== */
-#define GPIO_P0_06_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_06_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_06_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_06_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_06_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_06_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_07_MODE_REG  ===================================================== */
-#define GPIO_P0_07_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_07_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_07_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_07_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_07_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_07_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_08_MODE_REG  ===================================================== */
-#define GPIO_P0_08_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_08_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_08_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_08_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_08_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_08_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_09_MODE_REG  ===================================================== */
-#define GPIO_P0_09_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_09_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_09_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_09_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_09_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_09_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_10_MODE_REG  ===================================================== */
-#define GPIO_P0_10_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_10_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_10_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_10_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_10_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_10_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_11_MODE_REG  ===================================================== */
-#define GPIO_P0_11_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_11_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_11_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_11_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_11_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_11_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_12_MODE_REG  ===================================================== */
-#define GPIO_P0_12_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_12_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_12_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_12_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_12_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_12_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_13_MODE_REG  ===================================================== */
-#define GPIO_P0_13_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_13_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_13_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_13_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_13_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_13_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_14_MODE_REG  ===================================================== */
-#define GPIO_P0_14_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_14_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_14_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_14_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_14_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_14_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_15_MODE_REG  ===================================================== */
-#define GPIO_P0_15_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_15_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_15_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_15_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_15_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_15_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_16_MODE_REG  ===================================================== */
-#define GPIO_P0_16_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_16_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_16_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_16_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_16_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_16_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_17_MODE_REG  ===================================================== */
-#define GPIO_P0_17_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_17_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_17_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_17_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_17_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_17_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_18_MODE_REG  ===================================================== */
-#define GPIO_P0_18_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_18_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_18_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_18_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_18_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_18_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_19_MODE_REG  ===================================================== */
-#define GPIO_P0_19_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_19_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_19_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_19_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_19_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_19_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_20_MODE_REG  ===================================================== */
-#define GPIO_P0_20_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_20_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_20_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_20_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_20_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_20_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_21_MODE_REG  ===================================================== */
-#define GPIO_P0_21_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_21_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_21_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_21_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_21_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_21_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_22_MODE_REG  ===================================================== */
-#define GPIO_P0_22_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_22_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_22_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_22_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_22_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_22_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_23_MODE_REG  ===================================================== */
-#define GPIO_P0_23_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_23_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_23_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_23_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_23_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_23_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_24_MODE_REG  ===================================================== */
-#define GPIO_P0_24_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_24_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_24_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_24_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_24_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_24_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_25_MODE_REG  ===================================================== */
-#define GPIO_P0_25_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_25_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_25_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_25_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_25_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_25_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_26_MODE_REG  ===================================================== */
-#define GPIO_P0_26_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_26_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_26_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_26_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_26_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_26_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_27_MODE_REG  ===================================================== */
-#define GPIO_P0_27_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_27_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_27_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_27_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_27_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_27_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_28_MODE_REG  ===================================================== */
-#define GPIO_P0_28_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_28_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_28_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_28_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_28_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_28_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_29_MODE_REG  ===================================================== */
-#define GPIO_P0_29_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_29_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_29_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_29_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_29_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_29_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_30_MODE_REG  ===================================================== */
-#define GPIO_P0_30_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_30_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_30_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_30_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_30_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_30_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P0_31_MODE_REG  ===================================================== */
-#define GPIO_P0_31_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P0_31_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P0_31_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P0_31_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P0_31_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P0_31_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ======================================================  P0_DATA_REG  ====================================================== */
-#define GPIO_P0_DATA_REG_P0_DATA_Pos      (0UL)                     /*!< P0_DATA (Bit 0)                                       */
-#define GPIO_P0_DATA_REG_P0_DATA_Msk      (0xffffffffUL)            /*!< P0_DATA (Bitfield-Mask: 0xffffffff)                   */
-/* ==================================================  P0_PADPWR_CTRL_REG  =================================================== */
-#define GPIO_P0_PADPWR_CTRL_REG_P0_OUT_CTRL_Pos (6UL)               /*!< P0_OUT_CTRL (Bit 6)                                   */
-#define GPIO_P0_PADPWR_CTRL_REG_P0_OUT_CTRL_Msk (0xffffffc0UL)      /*!< P0_OUT_CTRL (Bitfield-Mask: 0x3ffffff)                */
-/* ===================================================  P0_RESET_DATA_REG  =================================================== */
-#define GPIO_P0_RESET_DATA_REG_P0_RESET_Pos (0UL)                   /*!< P0_RESET (Bit 0)                                      */
-#define GPIO_P0_RESET_DATA_REG_P0_RESET_Msk (0xffffffffUL)          /*!< P0_RESET (Bitfield-Mask: 0xffffffff)                  */
-/* ====================================================  P0_SET_DATA_REG  ==================================================== */
-#define GPIO_P0_SET_DATA_REG_P0_SET_Pos   (0UL)                     /*!< P0_SET (Bit 0)                                        */
-#define GPIO_P0_SET_DATA_REG_P0_SET_Msk   (0xffffffffUL)            /*!< P0_SET (Bitfield-Mask: 0xffffffff)                    */
-/* ====================================================  P1_00_MODE_REG  ===================================================== */
-#define GPIO_P1_00_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P1_00_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P1_00_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P1_00_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P1_00_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P1_00_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P1_01_MODE_REG  ===================================================== */
-#define GPIO_P1_01_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P1_01_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P1_01_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P1_01_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P1_01_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P1_01_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P1_02_MODE_REG  ===================================================== */
-#define GPIO_P1_02_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P1_02_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P1_02_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P1_02_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P1_02_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P1_02_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P1_03_MODE_REG  ===================================================== */
-#define GPIO_P1_03_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P1_03_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P1_03_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P1_03_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P1_03_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P1_03_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P1_04_MODE_REG  ===================================================== */
-#define GPIO_P1_04_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P1_04_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P1_04_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P1_04_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P1_04_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P1_04_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P1_05_MODE_REG  ===================================================== */
-#define GPIO_P1_05_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P1_05_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P1_05_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P1_05_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P1_05_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P1_05_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P1_06_MODE_REG  ===================================================== */
-#define GPIO_P1_06_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P1_06_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P1_06_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P1_06_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P1_06_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P1_06_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P1_07_MODE_REG  ===================================================== */
-#define GPIO_P1_07_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P1_07_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P1_07_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P1_07_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P1_07_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P1_07_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P1_08_MODE_REG  ===================================================== */
-#define GPIO_P1_08_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P1_08_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P1_08_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P1_08_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P1_08_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P1_08_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P1_09_MODE_REG  ===================================================== */
-#define GPIO_P1_09_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P1_09_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P1_09_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P1_09_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P1_09_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P1_09_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P1_10_MODE_REG  ===================================================== */
-#define GPIO_P1_10_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P1_10_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P1_10_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P1_10_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P1_10_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P1_10_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P1_11_MODE_REG  ===================================================== */
-#define GPIO_P1_11_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P1_11_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P1_11_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P1_11_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P1_11_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P1_11_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P1_12_MODE_REG  ===================================================== */
-#define GPIO_P1_12_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P1_12_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P1_12_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P1_12_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P1_12_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P1_12_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P1_13_MODE_REG  ===================================================== */
-#define GPIO_P1_13_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P1_13_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P1_13_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P1_13_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P1_13_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P1_13_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P1_14_MODE_REG  ===================================================== */
-#define GPIO_P1_14_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P1_14_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P1_14_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P1_14_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P1_14_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P1_14_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P1_15_MODE_REG  ===================================================== */
-#define GPIO_P1_15_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P1_15_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P1_15_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P1_15_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P1_15_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P1_15_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P1_16_MODE_REG  ===================================================== */
-#define GPIO_P1_16_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P1_16_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P1_16_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P1_16_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P1_16_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P1_16_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P1_17_MODE_REG  ===================================================== */
-#define GPIO_P1_17_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P1_17_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P1_17_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P1_17_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P1_17_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P1_17_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P1_18_MODE_REG  ===================================================== */
-#define GPIO_P1_18_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P1_18_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P1_18_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P1_18_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P1_18_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P1_18_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P1_19_MODE_REG  ===================================================== */
-#define GPIO_P1_19_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P1_19_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P1_19_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P1_19_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P1_19_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P1_19_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P1_20_MODE_REG  ===================================================== */
-#define GPIO_P1_20_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P1_20_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P1_20_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P1_20_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P1_20_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P1_20_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P1_21_MODE_REG  ===================================================== */
-#define GPIO_P1_21_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P1_21_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P1_21_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P1_21_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P1_21_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P1_21_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ====================================================  P1_22_MODE_REG  ===================================================== */
-#define GPIO_P1_22_MODE_REG_PPOD_Pos      (10UL)                    /*!< PPOD (Bit 10)                                         */
-#define GPIO_P1_22_MODE_REG_PPOD_Msk      (0x400UL)                 /*!< PPOD (Bitfield-Mask: 0x01)                            */
-#define GPIO_P1_22_MODE_REG_PUPD_Pos      (8UL)                     /*!< PUPD (Bit 8)                                          */
-#define GPIO_P1_22_MODE_REG_PUPD_Msk      (0x300UL)                 /*!< PUPD (Bitfield-Mask: 0x03)                            */
-#define GPIO_P1_22_MODE_REG_PID_Pos       (0UL)                     /*!< PID (Bit 0)                                           */
-#define GPIO_P1_22_MODE_REG_PID_Msk       (0x3fUL)                  /*!< PID (Bitfield-Mask: 0x3f)                             */
-/* ======================================================  P1_DATA_REG  ====================================================== */
-#define GPIO_P1_DATA_REG_P1_DATA_Pos      (0UL)                     /*!< P1_DATA (Bit 0)                                       */
-#define GPIO_P1_DATA_REG_P1_DATA_Msk      (0x7fffffUL)              /*!< P1_DATA (Bitfield-Mask: 0x7fffff)                     */
-/* ==================================================  P1_PADPWR_CTRL_REG  =================================================== */
-#define GPIO_P1_PADPWR_CTRL_REG_P1_OUT_CTRL_Pos (0UL)               /*!< P1_OUT_CTRL (Bit 0)                                   */
-#define GPIO_P1_PADPWR_CTRL_REG_P1_OUT_CTRL_Msk (0x7fffffUL)        /*!< P1_OUT_CTRL (Bitfield-Mask: 0x7fffff)                 */
-/* ===================================================  P1_RESET_DATA_REG  =================================================== */
-#define GPIO_P1_RESET_DATA_REG_P1_RESET_Pos (0UL)                   /*!< P1_RESET (Bit 0)                                      */
-#define GPIO_P1_RESET_DATA_REG_P1_RESET_Msk (0x7fffffUL)            /*!< P1_RESET (Bitfield-Mask: 0x7fffff)                    */
-/* ====================================================  P1_SET_DATA_REG  ==================================================== */
-#define GPIO_P1_SET_DATA_REG_P1_SET_Pos   (0UL)                     /*!< P1_SET (Bit 0)                                        */
-#define GPIO_P1_SET_DATA_REG_P1_SET_Msk   (0x7fffffUL)              /*!< P1_SET (Bitfield-Mask: 0x7fffff)                      */
-/* ===================================================  PAD_WEAK_CTRL_REG  =================================================== */
-#define GPIO_PAD_WEAK_CTRL_REG_P1_09_LOWDRV_Pos (12UL)              /*!< P1_09_LOWDRV (Bit 12)                                 */
-#define GPIO_PAD_WEAK_CTRL_REG_P1_09_LOWDRV_Msk (0x1000UL)          /*!< P1_09_LOWDRV (Bitfield-Mask: 0x01)                    */
-#define GPIO_PAD_WEAK_CTRL_REG_P1_06_LOWDRV_Pos (11UL)              /*!< P1_06_LOWDRV (Bit 11)                                 */
-#define GPIO_PAD_WEAK_CTRL_REG_P1_06_LOWDRV_Msk (0x800UL)           /*!< P1_06_LOWDRV (Bitfield-Mask: 0x01)                    */
-#define GPIO_PAD_WEAK_CTRL_REG_P1_02_LOWDRV_Pos (10UL)              /*!< P1_02_LOWDRV (Bit 10)                                 */
-#define GPIO_PAD_WEAK_CTRL_REG_P1_02_LOWDRV_Msk (0x400UL)           /*!< P1_02_LOWDRV (Bitfield-Mask: 0x01)                    */
-#define GPIO_PAD_WEAK_CTRL_REG_P1_01_LOWDRV_Pos (9UL)               /*!< P1_01_LOWDRV (Bit 9)                                  */
-#define GPIO_PAD_WEAK_CTRL_REG_P1_01_LOWDRV_Msk (0x200UL)           /*!< P1_01_LOWDRV (Bitfield-Mask: 0x01)                    */
-#define GPIO_PAD_WEAK_CTRL_REG_P1_00_LOWDRV_Pos (8UL)               /*!< P1_00_LOWDRV (Bit 8)                                  */
-#define GPIO_PAD_WEAK_CTRL_REG_P1_00_LOWDRV_Msk (0x100UL)           /*!< P1_00_LOWDRV (Bitfield-Mask: 0x01)                    */
-#define GPIO_PAD_WEAK_CTRL_REG_P0_27_LOWDRV_Pos (7UL)               /*!< P0_27_LOWDRV (Bit 7)                                  */
-#define GPIO_PAD_WEAK_CTRL_REG_P0_27_LOWDRV_Msk (0x80UL)            /*!< P0_27_LOWDRV (Bitfield-Mask: 0x01)                    */
-#define GPIO_PAD_WEAK_CTRL_REG_P0_26_LOWDRV_Pos (6UL)               /*!< P0_26_LOWDRV (Bit 6)                                  */
-#define GPIO_PAD_WEAK_CTRL_REG_P0_26_LOWDRV_Msk (0x40UL)            /*!< P0_26_LOWDRV (Bitfield-Mask: 0x01)                    */
-#define GPIO_PAD_WEAK_CTRL_REG_P0_25_LOWDRV_Pos (5UL)               /*!< P0_25_LOWDRV (Bit 5)                                  */
-#define GPIO_PAD_WEAK_CTRL_REG_P0_25_LOWDRV_Msk (0x20UL)            /*!< P0_25_LOWDRV (Bitfield-Mask: 0x01)                    */
-#define GPIO_PAD_WEAK_CTRL_REG_P0_18_LOWDRV_Pos (4UL)               /*!< P0_18_LOWDRV (Bit 4)                                  */
-#define GPIO_PAD_WEAK_CTRL_REG_P0_18_LOWDRV_Msk (0x10UL)            /*!< P0_18_LOWDRV (Bitfield-Mask: 0x01)                    */
-#define GPIO_PAD_WEAK_CTRL_REG_P0_17_LOWDRV_Pos (3UL)               /*!< P0_17_LOWDRV (Bit 3)                                  */
-#define GPIO_PAD_WEAK_CTRL_REG_P0_17_LOWDRV_Msk (0x8UL)             /*!< P0_17_LOWDRV (Bitfield-Mask: 0x01)                    */
-#define GPIO_PAD_WEAK_CTRL_REG_P0_16_LOWDRV_Pos (2UL)               /*!< P0_16_LOWDRV (Bit 2)                                  */
-#define GPIO_PAD_WEAK_CTRL_REG_P0_16_LOWDRV_Msk (0x4UL)             /*!< P0_16_LOWDRV (Bitfield-Mask: 0x01)                    */
-#define GPIO_PAD_WEAK_CTRL_REG_P0_07_LOWDRV_Pos (1UL)               /*!< P0_07_LOWDRV (Bit 1)                                  */
-#define GPIO_PAD_WEAK_CTRL_REG_P0_07_LOWDRV_Msk (0x2UL)             /*!< P0_07_LOWDRV (Bitfield-Mask: 0x01)                    */
-#define GPIO_PAD_WEAK_CTRL_REG_P0_06_LOWDRV_Pos (0UL)               /*!< P0_06_LOWDRV (Bit 0)                                  */
-#define GPIO_PAD_WEAK_CTRL_REG_P0_06_LOWDRV_Msk (0x1UL)             /*!< P0_06_LOWDRV (Bitfield-Mask: 0x01)                    */
-
-
-/* =========================================================================================================================== */
-/* ================                                           GPREG                                           ================ */
-/* =========================================================================================================================== */
-
-/* =======================================================  DEBUG_REG  ======================================================= */
-#define GPREG_DEBUG_REG_CROSS_CPU_HALT_SENSITIVITY_Pos (8UL)        /*!< CROSS_CPU_HALT_SENSITIVITY (Bit 8)                    */
-#define GPREG_DEBUG_REG_CROSS_CPU_HALT_SENSITIVITY_Msk (0x100UL)    /*!< CROSS_CPU_HALT_SENSITIVITY (Bitfield-Mask: 0x01)      */
-#define GPREG_DEBUG_REG_SYS_CPUWAIT_ON_JTAG_Pos (7UL)               /*!< SYS_CPUWAIT_ON_JTAG (Bit 7)                           */
-#define GPREG_DEBUG_REG_SYS_CPUWAIT_ON_JTAG_Msk (0x80UL)            /*!< SYS_CPUWAIT_ON_JTAG (Bitfield-Mask: 0x01)             */
-#define GPREG_DEBUG_REG_SYS_CPUWAIT_Pos   (6UL)                     /*!< SYS_CPUWAIT (Bit 6)                                   */
-#define GPREG_DEBUG_REG_SYS_CPUWAIT_Msk   (0x40UL)                  /*!< SYS_CPUWAIT (Bitfield-Mask: 0x01)                     */
-#define GPREG_DEBUG_REG_CMAC_CPU_IS_HALTED_Pos (5UL)                /*!< CMAC_CPU_IS_HALTED (Bit 5)                            */
-#define GPREG_DEBUG_REG_CMAC_CPU_IS_HALTED_Msk (0x20UL)             /*!< CMAC_CPU_IS_HALTED (Bitfield-Mask: 0x01)              */
-#define GPREG_DEBUG_REG_SYS_CPU_IS_HALTED_Pos (4UL)                 /*!< SYS_CPU_IS_HALTED (Bit 4)                             */
-#define GPREG_DEBUG_REG_SYS_CPU_IS_HALTED_Msk (0x10UL)              /*!< SYS_CPU_IS_HALTED (Bitfield-Mask: 0x01)               */
-#define GPREG_DEBUG_REG_HALT_CMAC_SYS_CPU_EN_Pos (3UL)              /*!< HALT_CMAC_SYS_CPU_EN (Bit 3)                          */
-#define GPREG_DEBUG_REG_HALT_CMAC_SYS_CPU_EN_Msk (0x8UL)            /*!< HALT_CMAC_SYS_CPU_EN (Bitfield-Mask: 0x01)            */
-#define GPREG_DEBUG_REG_HALT_SYS_CMAC_CPU_EN_Pos (2UL)              /*!< HALT_SYS_CMAC_CPU_EN (Bit 2)                          */
-#define GPREG_DEBUG_REG_HALT_SYS_CMAC_CPU_EN_Msk (0x4UL)            /*!< HALT_SYS_CMAC_CPU_EN (Bitfield-Mask: 0x01)            */
-#define GPREG_DEBUG_REG_CMAC_CPU_FREEZE_EN_Pos (1UL)                /*!< CMAC_CPU_FREEZE_EN (Bit 1)                            */
-#define GPREG_DEBUG_REG_CMAC_CPU_FREEZE_EN_Msk (0x2UL)              /*!< CMAC_CPU_FREEZE_EN (Bitfield-Mask: 0x01)              */
-#define GPREG_DEBUG_REG_SYS_CPU_FREEZE_EN_Pos (0UL)                 /*!< SYS_CPU_FREEZE_EN (Bit 0)                             */
-#define GPREG_DEBUG_REG_SYS_CPU_FREEZE_EN_Msk (0x1UL)               /*!< SYS_CPU_FREEZE_EN (Bitfield-Mask: 0x01)               */
-/* ====================================================  GP_CONTROL_REG  ===================================================== */
-#define GPREG_GP_CONTROL_REG_CMAC_H2H_BRIDGE_BYPASS_Pos (1UL)       /*!< CMAC_H2H_BRIDGE_BYPASS (Bit 1)                        */
-#define GPREG_GP_CONTROL_REG_CMAC_H2H_BRIDGE_BYPASS_Msk (0x2UL)     /*!< CMAC_H2H_BRIDGE_BYPASS (Bitfield-Mask: 0x01)          */
-/* =====================================================  GP_STATUS_REG  ===================================================== */
-#define GPREG_GP_STATUS_REG_CAL_PHASE_Pos (0UL)                     /*!< CAL_PHASE (Bit 0)                                     */
-#define GPREG_GP_STATUS_REG_CAL_PHASE_Msk (0x1UL)                   /*!< CAL_PHASE (Bitfield-Mask: 0x01)                       */
-/* ===================================================  RESET_FREEZE_REG  ==================================================== */
-#define GPREG_RESET_FREEZE_REG_FRZ_CMAC_WDOG_Pos (10UL)             /*!< FRZ_CMAC_WDOG (Bit 10)                                */
-#define GPREG_RESET_FREEZE_REG_FRZ_CMAC_WDOG_Msk (0x400UL)          /*!< FRZ_CMAC_WDOG (Bitfield-Mask: 0x01)                   */
-#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM4_Pos (9UL)                 /*!< FRZ_SWTIM4 (Bit 9)                                    */
-#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM4_Msk (0x200UL)             /*!< FRZ_SWTIM4 (Bitfield-Mask: 0x01)                      */
-#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM3_Pos (8UL)                 /*!< FRZ_SWTIM3 (Bit 8)                                    */
-#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM3_Msk (0x100UL)             /*!< FRZ_SWTIM3 (Bitfield-Mask: 0x01)                      */
-#define GPREG_RESET_FREEZE_REG_FRZ_PWMLED_Pos (7UL)                 /*!< FRZ_PWMLED (Bit 7)                                    */
-#define GPREG_RESET_FREEZE_REG_FRZ_PWMLED_Msk (0x80UL)              /*!< FRZ_PWMLED (Bitfield-Mask: 0x01)                      */
-#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM2_Pos (6UL)                 /*!< FRZ_SWTIM2 (Bit 6)                                    */
-#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM2_Msk (0x40UL)              /*!< FRZ_SWTIM2 (Bitfield-Mask: 0x01)                      */
-#define GPREG_RESET_FREEZE_REG_FRZ_DMA_Pos (5UL)                    /*!< FRZ_DMA (Bit 5)                                       */
-#define GPREG_RESET_FREEZE_REG_FRZ_DMA_Msk (0x20UL)                 /*!< FRZ_DMA (Bitfield-Mask: 0x01)                         */
-#define GPREG_RESET_FREEZE_REG_FRZ_USB_Pos (4UL)                    /*!< FRZ_USB (Bit 4)                                       */
-#define GPREG_RESET_FREEZE_REG_FRZ_USB_Msk (0x10UL)                 /*!< FRZ_USB (Bitfield-Mask: 0x01)                         */
-#define GPREG_RESET_FREEZE_REG_FRZ_SYS_WDOG_Pos (3UL)               /*!< FRZ_SYS_WDOG (Bit 3)                                  */
-#define GPREG_RESET_FREEZE_REG_FRZ_SYS_WDOG_Msk (0x8UL)             /*!< FRZ_SYS_WDOG (Bitfield-Mask: 0x01)                    */
-#define GPREG_RESET_FREEZE_REG_FRZ_RESERVED_Pos (2UL)               /*!< FRZ_RESERVED (Bit 2)                                  */
-#define GPREG_RESET_FREEZE_REG_FRZ_RESERVED_Msk (0x4UL)             /*!< FRZ_RESERVED (Bitfield-Mask: 0x01)                    */
-#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM_Pos (1UL)                  /*!< FRZ_SWTIM (Bit 1)                                     */
-#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM_Msk (0x2UL)                /*!< FRZ_SWTIM (Bitfield-Mask: 0x01)                       */
-#define GPREG_RESET_FREEZE_REG_FRZ_WKUPTIM_Pos (0UL)                /*!< FRZ_WKUPTIM (Bit 0)                                   */
-#define GPREG_RESET_FREEZE_REG_FRZ_WKUPTIM_Msk (0x1UL)              /*!< FRZ_WKUPTIM (Bitfield-Mask: 0x01)                     */
-/* ====================================================  SET_FREEZE_REG  ===================================================== */
-#define GPREG_SET_FREEZE_REG_FRZ_CMAC_WDOG_Pos (10UL)               /*!< FRZ_CMAC_WDOG (Bit 10)                                */
-#define GPREG_SET_FREEZE_REG_FRZ_CMAC_WDOG_Msk (0x400UL)            /*!< FRZ_CMAC_WDOG (Bitfield-Mask: 0x01)                   */
-#define GPREG_SET_FREEZE_REG_FRZ_SWTIM4_Pos (9UL)                   /*!< FRZ_SWTIM4 (Bit 9)                                    */
-#define GPREG_SET_FREEZE_REG_FRZ_SWTIM4_Msk (0x200UL)               /*!< FRZ_SWTIM4 (Bitfield-Mask: 0x01)                      */
-#define GPREG_SET_FREEZE_REG_FRZ_SWTIM3_Pos (8UL)                   /*!< FRZ_SWTIM3 (Bit 8)                                    */
-#define GPREG_SET_FREEZE_REG_FRZ_SWTIM3_Msk (0x100UL)               /*!< FRZ_SWTIM3 (Bitfield-Mask: 0x01)                      */
-#define GPREG_SET_FREEZE_REG_FRZ_PWMLED_Pos (7UL)                   /*!< FRZ_PWMLED (Bit 7)                                    */
-#define GPREG_SET_FREEZE_REG_FRZ_PWMLED_Msk (0x80UL)                /*!< FRZ_PWMLED (Bitfield-Mask: 0x01)                      */
-#define GPREG_SET_FREEZE_REG_FRZ_SWTIM2_Pos (6UL)                   /*!< FRZ_SWTIM2 (Bit 6)                                    */
-#define GPREG_SET_FREEZE_REG_FRZ_SWTIM2_Msk (0x40UL)                /*!< FRZ_SWTIM2 (Bitfield-Mask: 0x01)                      */
-#define GPREG_SET_FREEZE_REG_FRZ_DMA_Pos  (5UL)                     /*!< FRZ_DMA (Bit 5)                                       */
-#define GPREG_SET_FREEZE_REG_FRZ_DMA_Msk  (0x20UL)                  /*!< FRZ_DMA (Bitfield-Mask: 0x01)                         */
-#define GPREG_SET_FREEZE_REG_FRZ_USB_Pos  (4UL)                     /*!< FRZ_USB (Bit 4)                                       */
-#define GPREG_SET_FREEZE_REG_FRZ_USB_Msk  (0x10UL)                  /*!< FRZ_USB (Bitfield-Mask: 0x01)                         */
-#define GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Pos (3UL)                 /*!< FRZ_SYS_WDOG (Bit 3)                                  */
-#define GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Msk (0x8UL)               /*!< FRZ_SYS_WDOG (Bitfield-Mask: 0x01)                    */
-#define GPREG_SET_FREEZE_REG_FRZ_RESERVED_Pos (2UL)                 /*!< FRZ_RESERVED (Bit 2)                                  */
-#define GPREG_SET_FREEZE_REG_FRZ_RESERVED_Msk (0x4UL)               /*!< FRZ_RESERVED (Bitfield-Mask: 0x01)                    */
-#define GPREG_SET_FREEZE_REG_FRZ_SWTIM_Pos (1UL)                    /*!< FRZ_SWTIM (Bit 1)                                     */
-#define GPREG_SET_FREEZE_REG_FRZ_SWTIM_Msk (0x2UL)                  /*!< FRZ_SWTIM (Bitfield-Mask: 0x01)                       */
-#define GPREG_SET_FREEZE_REG_FRZ_WKUPTIM_Pos (0UL)                  /*!< FRZ_WKUPTIM (Bit 0)                                   */
-#define GPREG_SET_FREEZE_REG_FRZ_WKUPTIM_Msk (0x1UL)                /*!< FRZ_WKUPTIM (Bitfield-Mask: 0x01)                     */
-/* ======================================================  USBPAD_REG  ======================================================= */
-#define GPREG_USBPAD_REG_USBPHY_FORCE_SW2_ON_Pos (2UL)              /*!< USBPHY_FORCE_SW2_ON (Bit 2)                           */
-#define GPREG_USBPAD_REG_USBPHY_FORCE_SW2_ON_Msk (0x4UL)            /*!< USBPHY_FORCE_SW2_ON (Bitfield-Mask: 0x01)             */
-#define GPREG_USBPAD_REG_USBPHY_FORCE_SW1_OFF_Pos (1UL)             /*!< USBPHY_FORCE_SW1_OFF (Bit 1)                          */
-#define GPREG_USBPAD_REG_USBPHY_FORCE_SW1_OFF_Msk (0x2UL)           /*!< USBPHY_FORCE_SW1_OFF (Bitfield-Mask: 0x01)            */
-#define GPREG_USBPAD_REG_USBPAD_EN_Pos    (0UL)                     /*!< USBPAD_EN (Bit 0)                                     */
-#define GPREG_USBPAD_REG_USBPAD_EN_Msk    (0x1UL)                   /*!< USBPAD_EN (Bitfield-Mask: 0x01)                       */
-
-
-/* =========================================================================================================================== */
-/* ================                                            I2C                                            ================ */
-/* =========================================================================================================================== */
-
-/* ===============================================  I2C_ACK_GENERAL_CALL_REG  ================================================ */
-#define I2C_I2C_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Pos (0UL)         /*!< ACK_GEN_CALL (Bit 0)                                  */
-#define I2C_I2C_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Msk (0x1UL)       /*!< ACK_GEN_CALL (Bitfield-Mask: 0x01)                    */
-/* =================================================  I2C_CLR_ACTIVITY_REG  ================================================== */
-#define I2C_I2C_CLR_ACTIVITY_REG_CLR_ACTIVITY_Pos (0UL)             /*!< CLR_ACTIVITY (Bit 0)                                  */
-#define I2C_I2C_CLR_ACTIVITY_REG_CLR_ACTIVITY_Msk (0x1UL)           /*!< CLR_ACTIVITY (Bitfield-Mask: 0x01)                    */
-/* =================================================  I2C_CLR_GEN_CALL_REG  ================================================== */
-#define I2C_I2C_CLR_GEN_CALL_REG_CLR_GEN_CALL_Pos (0UL)             /*!< CLR_GEN_CALL (Bit 0)                                  */
-#define I2C_I2C_CLR_GEN_CALL_REG_CLR_GEN_CALL_Msk (0x1UL)           /*!< CLR_GEN_CALL (Bitfield-Mask: 0x01)                    */
-/* ===================================================  I2C_CLR_INTR_REG  ==================================================== */
-#define I2C_I2C_CLR_INTR_REG_CLR_INTR_Pos (0UL)                     /*!< CLR_INTR (Bit 0)                                      */
-#define I2C_I2C_CLR_INTR_REG_CLR_INTR_Msk (0x1UL)                   /*!< CLR_INTR (Bitfield-Mask: 0x01)                        */
-/* ==================================================  I2C_CLR_RD_REQ_REG  =================================================== */
-#define I2C_I2C_CLR_RD_REQ_REG_CLR_RD_REQ_Pos (0UL)                 /*!< CLR_RD_REQ (Bit 0)                                    */
-#define I2C_I2C_CLR_RD_REQ_REG_CLR_RD_REQ_Msk (0x1UL)               /*!< CLR_RD_REQ (Bitfield-Mask: 0x01)                      */
-/* ==================================================  I2C_CLR_RX_DONE_REG  ================================================== */
-#define I2C_I2C_CLR_RX_DONE_REG_CLR_RX_DONE_Pos (0UL)               /*!< CLR_RX_DONE (Bit 0)                                   */
-#define I2C_I2C_CLR_RX_DONE_REG_CLR_RX_DONE_Msk (0x1UL)             /*!< CLR_RX_DONE (Bitfield-Mask: 0x01)                     */
-/* ==================================================  I2C_CLR_RX_OVER_REG  ================================================== */
-#define I2C_I2C_CLR_RX_OVER_REG_CLR_RX_OVER_Pos (0UL)               /*!< CLR_RX_OVER (Bit 0)                                   */
-#define I2C_I2C_CLR_RX_OVER_REG_CLR_RX_OVER_Msk (0x1UL)             /*!< CLR_RX_OVER (Bitfield-Mask: 0x01)                     */
-/* =================================================  I2C_CLR_RX_UNDER_REG  ================================================== */
-#define I2C_I2C_CLR_RX_UNDER_REG_CLR_RX_UNDER_Pos (0UL)             /*!< CLR_RX_UNDER (Bit 0)                                  */
-#define I2C_I2C_CLR_RX_UNDER_REG_CLR_RX_UNDER_Msk (0x1UL)           /*!< CLR_RX_UNDER (Bitfield-Mask: 0x01)                    */
-/* =================================================  I2C_CLR_START_DET_REG  ================================================= */
-#define I2C_I2C_CLR_START_DET_REG_CLR_START_DET_Pos (0UL)           /*!< CLR_START_DET (Bit 0)                                 */
-#define I2C_I2C_CLR_START_DET_REG_CLR_START_DET_Msk (0x1UL)         /*!< CLR_START_DET (Bitfield-Mask: 0x01)                   */
-/* =================================================  I2C_CLR_STOP_DET_REG  ================================================== */
-#define I2C_I2C_CLR_STOP_DET_REG_CLR_STOP_DET_Pos (0UL)             /*!< CLR_STOP_DET (Bit 0)                                  */
-#define I2C_I2C_CLR_STOP_DET_REG_CLR_STOP_DET_Msk (0x1UL)           /*!< CLR_STOP_DET (Bitfield-Mask: 0x01)                    */
-/* ==================================================  I2C_CLR_TX_ABRT_REG  ================================================== */
-#define I2C_I2C_CLR_TX_ABRT_REG_CLR_TX_ABRT_Pos (0UL)               /*!< CLR_TX_ABRT (Bit 0)                                   */
-#define I2C_I2C_CLR_TX_ABRT_REG_CLR_TX_ABRT_Msk (0x1UL)             /*!< CLR_TX_ABRT (Bitfield-Mask: 0x01)                     */
-/* ==================================================  I2C_CLR_TX_OVER_REG  ================================================== */
-#define I2C_I2C_CLR_TX_OVER_REG_CLR_TX_OVER_Pos (0UL)               /*!< CLR_TX_OVER (Bit 0)                                   */
-#define I2C_I2C_CLR_TX_OVER_REG_CLR_TX_OVER_Msk (0x1UL)             /*!< CLR_TX_OVER (Bitfield-Mask: 0x01)                     */
-/* ======================================================  I2C_CON_REG  ====================================================== */
-#define I2C_I2C_CON_REG_I2C_STOP_DET_IF_MASTER_ACTIVE_Pos (10UL)    /*!< I2C_STOP_DET_IF_MASTER_ACTIVE (Bit 10)                */
-#define I2C_I2C_CON_REG_I2C_STOP_DET_IF_MASTER_ACTIVE_Msk (0x400UL) /*!< I2C_STOP_DET_IF_MASTER_ACTIVE (Bitfield-Mask: 0x01)   */
-#define I2C_I2C_CON_REG_I2C_RX_FIFO_FULL_HLD_CTRL_Pos (9UL)         /*!< I2C_RX_FIFO_FULL_HLD_CTRL (Bit 9)                     */
-#define I2C_I2C_CON_REG_I2C_RX_FIFO_FULL_HLD_CTRL_Msk (0x200UL)     /*!< I2C_RX_FIFO_FULL_HLD_CTRL (Bitfield-Mask: 0x01)       */
-#define I2C_I2C_CON_REG_I2C_TX_EMPTY_CTRL_Pos (8UL)                 /*!< I2C_TX_EMPTY_CTRL (Bit 8)                             */
-#define I2C_I2C_CON_REG_I2C_TX_EMPTY_CTRL_Msk (0x100UL)             /*!< I2C_TX_EMPTY_CTRL (Bitfield-Mask: 0x01)               */
-#define I2C_I2C_CON_REG_I2C_STOP_DET_IFADDRESSED_Pos (7UL)          /*!< I2C_STOP_DET_IFADDRESSED (Bit 7)                      */
-#define I2C_I2C_CON_REG_I2C_STOP_DET_IFADDRESSED_Msk (0x80UL)       /*!< I2C_STOP_DET_IFADDRESSED (Bitfield-Mask: 0x01)        */
-#define I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Pos (6UL)                 /*!< I2C_SLAVE_DISABLE (Bit 6)                             */
-#define I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Msk (0x40UL)              /*!< I2C_SLAVE_DISABLE (Bitfield-Mask: 0x01)               */
-#define I2C_I2C_CON_REG_I2C_RESTART_EN_Pos (5UL)                    /*!< I2C_RESTART_EN (Bit 5)                                */
-#define I2C_I2C_CON_REG_I2C_RESTART_EN_Msk (0x20UL)                 /*!< I2C_RESTART_EN (Bitfield-Mask: 0x01)                  */
-#define I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Pos (4UL)              /*!< I2C_10BITADDR_MASTER (Bit 4)                          */
-#define I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Msk (0x10UL)           /*!< I2C_10BITADDR_MASTER (Bitfield-Mask: 0x01)            */
-#define I2C_I2C_CON_REG_I2C_10BITADDR_SLAVE_Pos (3UL)               /*!< I2C_10BITADDR_SLAVE (Bit 3)                           */
-#define I2C_I2C_CON_REG_I2C_10BITADDR_SLAVE_Msk (0x8UL)             /*!< I2C_10BITADDR_SLAVE (Bitfield-Mask: 0x01)             */
-#define I2C_I2C_CON_REG_I2C_SPEED_Pos     (1UL)                     /*!< I2C_SPEED (Bit 1)                                     */
-#define I2C_I2C_CON_REG_I2C_SPEED_Msk     (0x6UL)                   /*!< I2C_SPEED (Bitfield-Mask: 0x03)                       */
-#define I2C_I2C_CON_REG_I2C_MASTER_MODE_Pos (0UL)                   /*!< I2C_MASTER_MODE (Bit 0)                               */
-#define I2C_I2C_CON_REG_I2C_MASTER_MODE_Msk (0x1UL)                 /*!< I2C_MASTER_MODE (Bitfield-Mask: 0x01)                 */
-/* ===================================================  I2C_DATA_CMD_REG  ==================================================== */
-#define I2C_I2C_DATA_CMD_REG_I2C_RESTART_Pos (10UL)                 /*!< I2C_RESTART (Bit 10)                                  */
-#define I2C_I2C_DATA_CMD_REG_I2C_RESTART_Msk (0x400UL)              /*!< I2C_RESTART (Bitfield-Mask: 0x01)                     */
-#define I2C_I2C_DATA_CMD_REG_I2C_STOP_Pos (9UL)                     /*!< I2C_STOP (Bit 9)                                      */
-#define I2C_I2C_DATA_CMD_REG_I2C_STOP_Msk (0x200UL)                 /*!< I2C_STOP (Bitfield-Mask: 0x01)                        */
-#define I2C_I2C_DATA_CMD_REG_I2C_CMD_Pos  (8UL)                     /*!< I2C_CMD (Bit 8)                                       */
-#define I2C_I2C_DATA_CMD_REG_I2C_CMD_Msk  (0x100UL)                 /*!< I2C_CMD (Bitfield-Mask: 0x01)                         */
-#define I2C_I2C_DATA_CMD_REG_I2C_DAT_Pos  (0UL)                     /*!< I2C_DAT (Bit 0)                                       */
-#define I2C_I2C_DATA_CMD_REG_I2C_DAT_Msk  (0xffUL)                  /*!< I2C_DAT (Bitfield-Mask: 0xff)                         */
-/* ====================================================  I2C_DMA_CR_REG  ===================================================== */
-#define I2C_I2C_DMA_CR_REG_TDMAE_Pos      (1UL)                     /*!< TDMAE (Bit 1)                                         */
-#define I2C_I2C_DMA_CR_REG_TDMAE_Msk      (0x2UL)                   /*!< TDMAE (Bitfield-Mask: 0x01)                           */
-#define I2C_I2C_DMA_CR_REG_RDMAE_Pos      (0UL)                     /*!< RDMAE (Bit 0)                                         */
-#define I2C_I2C_DMA_CR_REG_RDMAE_Msk      (0x1UL)                   /*!< RDMAE (Bitfield-Mask: 0x01)                           */
-/* ===================================================  I2C_DMA_RDLR_REG  ==================================================== */
-#define I2C_I2C_DMA_RDLR_REG_DMARDL_Pos   (0UL)                     /*!< DMARDL (Bit 0)                                        */
-#define I2C_I2C_DMA_RDLR_REG_DMARDL_Msk   (0x1fUL)                  /*!< DMARDL (Bitfield-Mask: 0x1f)                          */
-/* ===================================================  I2C_DMA_TDLR_REG  ==================================================== */
-#define I2C_I2C_DMA_TDLR_REG_DMATDL_Pos   (0UL)                     /*!< DMATDL (Bit 0)                                        */
-#define I2C_I2C_DMA_TDLR_REG_DMATDL_Msk   (0x1fUL)                  /*!< DMATDL (Bitfield-Mask: 0x1f)                          */
-/* ====================================================  I2C_ENABLE_REG  ===================================================== */
-#define I2C_I2C_ENABLE_REG_I2C_TX_CMD_BLOCK_Pos (2UL)               /*!< I2C_TX_CMD_BLOCK (Bit 2)                              */
-#define I2C_I2C_ENABLE_REG_I2C_TX_CMD_BLOCK_Msk (0x4UL)             /*!< I2C_TX_CMD_BLOCK (Bitfield-Mask: 0x01)                */
-#define I2C_I2C_ENABLE_REG_I2C_ABORT_Pos  (1UL)                     /*!< I2C_ABORT (Bit 1)                                     */
-#define I2C_I2C_ENABLE_REG_I2C_ABORT_Msk  (0x2UL)                   /*!< I2C_ABORT (Bitfield-Mask: 0x01)                       */
-#define I2C_I2C_ENABLE_REG_I2C_EN_Pos     (0UL)                     /*!< I2C_EN (Bit 0)                                        */
-#define I2C_I2C_ENABLE_REG_I2C_EN_Msk     (0x1UL)                   /*!< I2C_EN (Bitfield-Mask: 0x01)                          */
-/* =================================================  I2C_ENABLE_STATUS_REG  ================================================= */
-#define I2C_I2C_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Pos (2UL)        /*!< SLV_RX_DATA_LOST (Bit 2)                              */
-#define I2C_I2C_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Msk (0x4UL)      /*!< SLV_RX_DATA_LOST (Bitfield-Mask: 0x01)                */
-#define I2C_I2C_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Pos (1UL) /*!< SLV_DISABLED_WHILE_BUSY (Bit 1)                       */
-#define I2C_I2C_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Msk (0x2UL) /*!< SLV_DISABLED_WHILE_BUSY (Bitfield-Mask: 0x01)       */
-#define I2C_I2C_ENABLE_STATUS_REG_IC_EN_Pos (0UL)                   /*!< IC_EN (Bit 0)                                         */
-#define I2C_I2C_ENABLE_STATUS_REG_IC_EN_Msk (0x1UL)                 /*!< IC_EN (Bitfield-Mask: 0x01)                           */
-/* ==================================================  I2C_FS_SCL_HCNT_REG  ================================================== */
-#define I2C_I2C_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Pos (0UL)            /*!< IC_FS_SCL_HCNT (Bit 0)                                */
-#define I2C_I2C_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Msk (0xffffUL)       /*!< IC_FS_SCL_HCNT (Bitfield-Mask: 0xffff)                */
-/* ==================================================  I2C_FS_SCL_LCNT_REG  ================================================== */
-#define I2C_I2C_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Pos (0UL)            /*!< IC_FS_SCL_LCNT (Bit 0)                                */
-#define I2C_I2C_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Msk (0xffffUL)       /*!< IC_FS_SCL_LCNT (Bitfield-Mask: 0xffff)                */
-/* ===================================================  I2C_HS_MADDR_REG  ==================================================== */
-#define I2C_I2C_HS_MADDR_REG_I2C_IC_HS_MAR_Pos (0UL)                /*!< I2C_IC_HS_MAR (Bit 0)                                 */
-#define I2C_I2C_HS_MADDR_REG_I2C_IC_HS_MAR_Msk (0x7UL)              /*!< I2C_IC_HS_MAR (Bitfield-Mask: 0x07)                   */
-/* ==================================================  I2C_HS_SCL_HCNT_REG  ================================================== */
-#define I2C_I2C_HS_SCL_HCNT_REG_IC_HS_SCL_HCNT_Pos (0UL)            /*!< IC_HS_SCL_HCNT (Bit 0)                                */
-#define I2C_I2C_HS_SCL_HCNT_REG_IC_HS_SCL_HCNT_Msk (0xffffUL)       /*!< IC_HS_SCL_HCNT (Bitfield-Mask: 0xffff)                */
-/* ==================================================  I2C_HS_SCL_LCNT_REG  ================================================== */
-#define I2C_I2C_HS_SCL_LCNT_REG_IC_HS_SCL_LCNT_Pos (0UL)            /*!< IC_HS_SCL_LCNT (Bit 0)                                */
-#define I2C_I2C_HS_SCL_LCNT_REG_IC_HS_SCL_LCNT_Msk (0xffffUL)       /*!< IC_HS_SCL_LCNT (Bitfield-Mask: 0xffff)                */
-/* =================================================  I2C_IC_FS_SPKLEN_REG  ================================================== */
-#define I2C_I2C_IC_FS_SPKLEN_REG_I2C_FS_SPKLEN_Pos (0UL)            /*!< I2C_FS_SPKLEN (Bit 0)                                 */
-#define I2C_I2C_IC_FS_SPKLEN_REG_I2C_FS_SPKLEN_Msk (0xffUL)         /*!< I2C_FS_SPKLEN (Bitfield-Mask: 0xff)                   */
-/* =================================================  I2C_IC_HS_SPKLEN_REG  ================================================== */
-#define I2C_I2C_IC_HS_SPKLEN_REG_I2C_HS_SPKLEN_Pos (0UL)            /*!< I2C_HS_SPKLEN (Bit 0)                                 */
-#define I2C_I2C_IC_HS_SPKLEN_REG_I2C_HS_SPKLEN_Msk (0xffUL)         /*!< I2C_HS_SPKLEN (Bitfield-Mask: 0xff)                   */
-/* ===================================================  I2C_INTR_MASK_REG  =================================================== */
-#define I2C_I2C_INTR_MASK_REG_M_SCL_STUCK_AT_LOW_Pos (14UL)         /*!< M_SCL_STUCK_AT_LOW (Bit 14)                           */
-#define I2C_I2C_INTR_MASK_REG_M_SCL_STUCK_AT_LOW_Msk (0x4000UL)     /*!< M_SCL_STUCK_AT_LOW (Bitfield-Mask: 0x01)              */
-#define I2C_I2C_INTR_MASK_REG_M_MASTER_ON_HOLD_Pos (13UL)           /*!< M_MASTER_ON_HOLD (Bit 13)                             */
-#define I2C_I2C_INTR_MASK_REG_M_MASTER_ON_HOLD_Msk (0x2000UL)       /*!< M_MASTER_ON_HOLD (Bitfield-Mask: 0x01)                */
-#define I2C_I2C_INTR_MASK_REG_M_RESTART_DET_Pos (12UL)              /*!< M_RESTART_DET (Bit 12)                                */
-#define I2C_I2C_INTR_MASK_REG_M_RESTART_DET_Msk (0x1000UL)          /*!< M_RESTART_DET (Bitfield-Mask: 0x01)                   */
-#define I2C_I2C_INTR_MASK_REG_M_GEN_CALL_Pos (11UL)                 /*!< M_GEN_CALL (Bit 11)                                   */
-#define I2C_I2C_INTR_MASK_REG_M_GEN_CALL_Msk (0x800UL)              /*!< M_GEN_CALL (Bitfield-Mask: 0x01)                      */
-#define I2C_I2C_INTR_MASK_REG_M_START_DET_Pos (10UL)                /*!< M_START_DET (Bit 10)                                  */
-#define I2C_I2C_INTR_MASK_REG_M_START_DET_Msk (0x400UL)             /*!< M_START_DET (Bitfield-Mask: 0x01)                     */
-#define I2C_I2C_INTR_MASK_REG_M_STOP_DET_Pos (9UL)                  /*!< M_STOP_DET (Bit 9)                                    */
-#define I2C_I2C_INTR_MASK_REG_M_STOP_DET_Msk (0x200UL)              /*!< M_STOP_DET (Bitfield-Mask: 0x01)                      */
-#define I2C_I2C_INTR_MASK_REG_M_ACTIVITY_Pos (8UL)                  /*!< M_ACTIVITY (Bit 8)                                    */
-#define I2C_I2C_INTR_MASK_REG_M_ACTIVITY_Msk (0x100UL)              /*!< M_ACTIVITY (Bitfield-Mask: 0x01)                      */
-#define I2C_I2C_INTR_MASK_REG_M_RX_DONE_Pos (7UL)                   /*!< M_RX_DONE (Bit 7)                                     */
-#define I2C_I2C_INTR_MASK_REG_M_RX_DONE_Msk (0x80UL)                /*!< M_RX_DONE (Bitfield-Mask: 0x01)                       */
-#define I2C_I2C_INTR_MASK_REG_M_TX_ABRT_Pos (6UL)                   /*!< M_TX_ABRT (Bit 6)                                     */
-#define I2C_I2C_INTR_MASK_REG_M_TX_ABRT_Msk (0x40UL)                /*!< M_TX_ABRT (Bitfield-Mask: 0x01)                       */
-#define I2C_I2C_INTR_MASK_REG_M_RD_REQ_Pos (5UL)                    /*!< M_RD_REQ (Bit 5)                                      */
-#define I2C_I2C_INTR_MASK_REG_M_RD_REQ_Msk (0x20UL)                 /*!< M_RD_REQ (Bitfield-Mask: 0x01)                        */
-#define I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Pos (4UL)                  /*!< M_TX_EMPTY (Bit 4)                                    */
-#define I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Msk (0x10UL)               /*!< M_TX_EMPTY (Bitfield-Mask: 0x01)                      */
-#define I2C_I2C_INTR_MASK_REG_M_TX_OVER_Pos (3UL)                   /*!< M_TX_OVER (Bit 3)                                     */
-#define I2C_I2C_INTR_MASK_REG_M_TX_OVER_Msk (0x8UL)                 /*!< M_TX_OVER (Bitfield-Mask: 0x01)                       */
-#define I2C_I2C_INTR_MASK_REG_M_RX_FULL_Pos (2UL)                   /*!< M_RX_FULL (Bit 2)                                     */
-#define I2C_I2C_INTR_MASK_REG_M_RX_FULL_Msk (0x4UL)                 /*!< M_RX_FULL (Bitfield-Mask: 0x01)                       */
-#define I2C_I2C_INTR_MASK_REG_M_RX_OVER_Pos (1UL)                   /*!< M_RX_OVER (Bit 1)                                     */
-#define I2C_I2C_INTR_MASK_REG_M_RX_OVER_Msk (0x2UL)                 /*!< M_RX_OVER (Bitfield-Mask: 0x01)                       */
-#define I2C_I2C_INTR_MASK_REG_M_RX_UNDER_Pos (0UL)                  /*!< M_RX_UNDER (Bit 0)                                    */
-#define I2C_I2C_INTR_MASK_REG_M_RX_UNDER_Msk (0x1UL)                /*!< M_RX_UNDER (Bitfield-Mask: 0x01)                      */
-/* ===================================================  I2C_INTR_STAT_REG  =================================================== */
-#define I2C_I2C_INTR_STAT_REG_R_SCL_STUCK_AT_LOW_Pos (14UL)         /*!< R_SCL_STUCK_AT_LOW (Bit 14)                           */
-#define I2C_I2C_INTR_STAT_REG_R_SCL_STUCK_AT_LOW_Msk (0x4000UL)     /*!< R_SCL_STUCK_AT_LOW (Bitfield-Mask: 0x01)              */
-#define I2C_I2C_INTR_STAT_REG_R_MASTER_ON_HOLD_Pos (13UL)           /*!< R_MASTER_ON_HOLD (Bit 13)                             */
-#define I2C_I2C_INTR_STAT_REG_R_MASTER_ON_HOLD_Msk (0x2000UL)       /*!< R_MASTER_ON_HOLD (Bitfield-Mask: 0x01)                */
-#define I2C_I2C_INTR_STAT_REG_R_RESTART_DET_Pos (12UL)              /*!< R_RESTART_DET (Bit 12)                                */
-#define I2C_I2C_INTR_STAT_REG_R_RESTART_DET_Msk (0x1000UL)          /*!< R_RESTART_DET (Bitfield-Mask: 0x01)                   */
-#define I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Pos (11UL)                 /*!< R_GEN_CALL (Bit 11)                                   */
-#define I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Msk (0x800UL)              /*!< R_GEN_CALL (Bitfield-Mask: 0x01)                      */
-#define I2C_I2C_INTR_STAT_REG_R_START_DET_Pos (10UL)                /*!< R_START_DET (Bit 10)                                  */
-#define I2C_I2C_INTR_STAT_REG_R_START_DET_Msk (0x400UL)             /*!< R_START_DET (Bitfield-Mask: 0x01)                     */
-#define I2C_I2C_INTR_STAT_REG_R_STOP_DET_Pos (9UL)                  /*!< R_STOP_DET (Bit 9)                                    */
-#define I2C_I2C_INTR_STAT_REG_R_STOP_DET_Msk (0x200UL)              /*!< R_STOP_DET (Bitfield-Mask: 0x01)                      */
-#define I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Pos (8UL)                  /*!< R_ACTIVITY (Bit 8)                                    */
-#define I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Msk (0x100UL)              /*!< R_ACTIVITY (Bitfield-Mask: 0x01)                      */
-#define I2C_I2C_INTR_STAT_REG_R_RX_DONE_Pos (7UL)                   /*!< R_RX_DONE (Bit 7)                                     */
-#define I2C_I2C_INTR_STAT_REG_R_RX_DONE_Msk (0x80UL)                /*!< R_RX_DONE (Bitfield-Mask: 0x01)                       */
-#define I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Pos (6UL)                   /*!< R_TX_ABRT (Bit 6)                                     */
-#define I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Msk (0x40UL)                /*!< R_TX_ABRT (Bitfield-Mask: 0x01)                       */
-#define I2C_I2C_INTR_STAT_REG_R_RD_REQ_Pos (5UL)                    /*!< R_RD_REQ (Bit 5)                                      */
-#define I2C_I2C_INTR_STAT_REG_R_RD_REQ_Msk (0x20UL)                 /*!< R_RD_REQ (Bitfield-Mask: 0x01)                        */
-#define I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Pos (4UL)                  /*!< R_TX_EMPTY (Bit 4)                                    */
-#define I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Msk (0x10UL)               /*!< R_TX_EMPTY (Bitfield-Mask: 0x01)                      */
-#define I2C_I2C_INTR_STAT_REG_R_TX_OVER_Pos (3UL)                   /*!< R_TX_OVER (Bit 3)                                     */
-#define I2C_I2C_INTR_STAT_REG_R_TX_OVER_Msk (0x8UL)                 /*!< R_TX_OVER (Bitfield-Mask: 0x01)                       */
-#define I2C_I2C_INTR_STAT_REG_R_RX_FULL_Pos (2UL)                   /*!< R_RX_FULL (Bit 2)                                     */
-#define I2C_I2C_INTR_STAT_REG_R_RX_FULL_Msk (0x4UL)                 /*!< R_RX_FULL (Bitfield-Mask: 0x01)                       */
-#define I2C_I2C_INTR_STAT_REG_R_RX_OVER_Pos (1UL)                   /*!< R_RX_OVER (Bit 1)                                     */
-#define I2C_I2C_INTR_STAT_REG_R_RX_OVER_Msk (0x2UL)                 /*!< R_RX_OVER (Bitfield-Mask: 0x01)                       */
-#define I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Pos (0UL)                  /*!< R_RX_UNDER (Bit 0)                                    */
-#define I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Msk (0x1UL)                /*!< R_RX_UNDER (Bitfield-Mask: 0x01)                      */
-/* =================================================  I2C_RAW_INTR_STAT_REG  ================================================= */
-#define I2C_I2C_RAW_INTR_STAT_REG_SCL_STUCK_AT_LOW_Pos (14UL)       /*!< SCL_STUCK_AT_LOW (Bit 14)                             */
-#define I2C_I2C_RAW_INTR_STAT_REG_SCL_STUCK_AT_LOW_Msk (0x4000UL)   /*!< SCL_STUCK_AT_LOW (Bitfield-Mask: 0x01)                */
-#define I2C_I2C_RAW_INTR_STAT_REG_MASTER_ON_HOLD_Pos (13UL)         /*!< MASTER_ON_HOLD (Bit 13)                               */
-#define I2C_I2C_RAW_INTR_STAT_REG_MASTER_ON_HOLD_Msk (0x2000UL)     /*!< MASTER_ON_HOLD (Bitfield-Mask: 0x01)                  */
-#define I2C_I2C_RAW_INTR_STAT_REG_RESTART_DET_Pos (12UL)            /*!< RESTART_DET (Bit 12)                                  */
-#define I2C_I2C_RAW_INTR_STAT_REG_RESTART_DET_Msk (0x1000UL)        /*!< RESTART_DET (Bitfield-Mask: 0x01)                     */
-#define I2C_I2C_RAW_INTR_STAT_REG_GEN_CALL_Pos (11UL)               /*!< GEN_CALL (Bit 11)                                     */
-#define I2C_I2C_RAW_INTR_STAT_REG_GEN_CALL_Msk (0x800UL)            /*!< GEN_CALL (Bitfield-Mask: 0x01)                        */
-#define I2C_I2C_RAW_INTR_STAT_REG_START_DET_Pos (10UL)              /*!< START_DET (Bit 10)                                    */
-#define I2C_I2C_RAW_INTR_STAT_REG_START_DET_Msk (0x400UL)           /*!< START_DET (Bitfield-Mask: 0x01)                       */
-#define I2C_I2C_RAW_INTR_STAT_REG_STOP_DET_Pos (9UL)                /*!< STOP_DET (Bit 9)                                      */
-#define I2C_I2C_RAW_INTR_STAT_REG_STOP_DET_Msk (0x200UL)            /*!< STOP_DET (Bitfield-Mask: 0x01)                        */
-#define I2C_I2C_RAW_INTR_STAT_REG_ACTIVITY_Pos (8UL)                /*!< ACTIVITY (Bit 8)                                      */
-#define I2C_I2C_RAW_INTR_STAT_REG_ACTIVITY_Msk (0x100UL)            /*!< ACTIVITY (Bitfield-Mask: 0x01)                        */
-#define I2C_I2C_RAW_INTR_STAT_REG_RX_DONE_Pos (7UL)                 /*!< RX_DONE (Bit 7)                                       */
-#define I2C_I2C_RAW_INTR_STAT_REG_RX_DONE_Msk (0x80UL)              /*!< RX_DONE (Bitfield-Mask: 0x01)                         */
-#define I2C_I2C_RAW_INTR_STAT_REG_TX_ABRT_Pos (6UL)                 /*!< TX_ABRT (Bit 6)                                       */
-#define I2C_I2C_RAW_INTR_STAT_REG_TX_ABRT_Msk (0x40UL)              /*!< TX_ABRT (Bitfield-Mask: 0x01)                         */
-#define I2C_I2C_RAW_INTR_STAT_REG_RD_REQ_Pos (5UL)                  /*!< RD_REQ (Bit 5)                                        */
-#define I2C_I2C_RAW_INTR_STAT_REG_RD_REQ_Msk (0x20UL)               /*!< RD_REQ (Bitfield-Mask: 0x01)                          */
-#define I2C_I2C_RAW_INTR_STAT_REG_TX_EMPTY_Pos (4UL)                /*!< TX_EMPTY (Bit 4)                                      */
-#define I2C_I2C_RAW_INTR_STAT_REG_TX_EMPTY_Msk (0x10UL)             /*!< TX_EMPTY (Bitfield-Mask: 0x01)                        */
-#define I2C_I2C_RAW_INTR_STAT_REG_TX_OVER_Pos (3UL)                 /*!< TX_OVER (Bit 3)                                       */
-#define I2C_I2C_RAW_INTR_STAT_REG_TX_OVER_Msk (0x8UL)               /*!< TX_OVER (Bitfield-Mask: 0x01)                         */
-#define I2C_I2C_RAW_INTR_STAT_REG_RX_FULL_Pos (2UL)                 /*!< RX_FULL (Bit 2)                                       */
-#define I2C_I2C_RAW_INTR_STAT_REG_RX_FULL_Msk (0x4UL)               /*!< RX_FULL (Bitfield-Mask: 0x01)                         */
-#define I2C_I2C_RAW_INTR_STAT_REG_RX_OVER_Pos (1UL)                 /*!< RX_OVER (Bit 1)                                       */
-#define I2C_I2C_RAW_INTR_STAT_REG_RX_OVER_Msk (0x2UL)               /*!< RX_OVER (Bitfield-Mask: 0x01)                         */
-#define I2C_I2C_RAW_INTR_STAT_REG_RX_UNDER_Pos (0UL)                /*!< RX_UNDER (Bit 0)                                      */
-#define I2C_I2C_RAW_INTR_STAT_REG_RX_UNDER_Msk (0x1UL)              /*!< RX_UNDER (Bitfield-Mask: 0x01)                        */
-/* =====================================================  I2C_RXFLR_REG  ===================================================== */
-#define I2C_I2C_RXFLR_REG_RXFLR_Pos       (0UL)                     /*!< RXFLR (Bit 0)                                         */
-#define I2C_I2C_RXFLR_REG_RXFLR_Msk       (0x3fUL)                  /*!< RXFLR (Bitfield-Mask: 0x3f)                           */
-/* =====================================================  I2C_RX_TL_REG  ===================================================== */
-#define I2C_I2C_RX_TL_REG_RX_TL_Pos       (0UL)                     /*!< RX_TL (Bit 0)                                         */
-#define I2C_I2C_RX_TL_REG_RX_TL_Msk       (0x1fUL)                  /*!< RX_TL (Bitfield-Mask: 0x1f)                           */
-/* ======================================================  I2C_SAR_REG  ====================================================== */
-#define I2C_I2C_SAR_REG_IC_SAR_Pos        (0UL)                     /*!< IC_SAR (Bit 0)                                        */
-#define I2C_I2C_SAR_REG_IC_SAR_Msk        (0x3ffUL)                 /*!< IC_SAR (Bitfield-Mask: 0x3ff)                         */
-/* ===================================================  I2C_SDA_HOLD_REG  ==================================================== */
-#define I2C_I2C_SDA_HOLD_REG_I2C_SDA_RX_HOLD_Pos (16UL)             /*!< I2C_SDA_RX_HOLD (Bit 16)                              */
-#define I2C_I2C_SDA_HOLD_REG_I2C_SDA_RX_HOLD_Msk (0xff0000UL)       /*!< I2C_SDA_RX_HOLD (Bitfield-Mask: 0xff)                 */
-#define I2C_I2C_SDA_HOLD_REG_I2C_SDA_TX_HOLD_Pos (0UL)              /*!< I2C_SDA_TX_HOLD (Bit 0)                               */
-#define I2C_I2C_SDA_HOLD_REG_I2C_SDA_TX_HOLD_Msk (0xffffUL)         /*!< I2C_SDA_TX_HOLD (Bitfield-Mask: 0xffff)               */
-/* ===================================================  I2C_SDA_SETUP_REG  =================================================== */
-#define I2C_I2C_SDA_SETUP_REG_SDA_SETUP_Pos (0UL)                   /*!< SDA_SETUP (Bit 0)                                     */
-#define I2C_I2C_SDA_SETUP_REG_SDA_SETUP_Msk (0xffUL)                /*!< SDA_SETUP (Bitfield-Mask: 0xff)                       */
-/* ==================================================  I2C_SS_SCL_HCNT_REG  ================================================== */
-#define I2C_I2C_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Pos (0UL)            /*!< IC_SS_SCL_HCNT (Bit 0)                                */
-#define I2C_I2C_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Msk (0xffffUL)       /*!< IC_SS_SCL_HCNT (Bitfield-Mask: 0xffff)                */
-/* ==================================================  I2C_SS_SCL_LCNT_REG  ================================================== */
-#define I2C_I2C_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Pos (0UL)            /*!< IC_SS_SCL_LCNT (Bit 0)                                */
-#define I2C_I2C_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Msk (0xffffUL)       /*!< IC_SS_SCL_LCNT (Bitfield-Mask: 0xffff)                */
-/* ====================================================  I2C_STATUS_REG  ===================================================== */
-#define I2C_I2C_STATUS_REG_LV_HOLD_RX_FIFO_FULL_Pos (10UL)          /*!< LV_HOLD_RX_FIFO_FULL (Bit 10)                         */
-#define I2C_I2C_STATUS_REG_LV_HOLD_RX_FIFO_FULL_Msk (0x400UL)       /*!< LV_HOLD_RX_FIFO_FULL (Bitfield-Mask: 0x01)            */
-#define I2C_I2C_STATUS_REG_SLV_HOLD_TX_FIFO_EMPTY_Pos (9UL)         /*!< SLV_HOLD_TX_FIFO_EMPTY (Bit 9)                        */
-#define I2C_I2C_STATUS_REG_SLV_HOLD_TX_FIFO_EMPTY_Msk (0x200UL)     /*!< SLV_HOLD_TX_FIFO_EMPTY (Bitfield-Mask: 0x01)          */
-#define I2C_I2C_STATUS_REG_MST_HOLD_RX_FIFO_FULL_Pos (8UL)          /*!< MST_HOLD_RX_FIFO_FULL (Bit 8)                         */
-#define I2C_I2C_STATUS_REG_MST_HOLD_RX_FIFO_FULL_Msk (0x100UL)      /*!< MST_HOLD_RX_FIFO_FULL (Bitfield-Mask: 0x01)           */
-#define I2C_I2C_STATUS_REG_MST_HOLD_TX_FIFO_EMPTY_Pos (7UL)         /*!< MST_HOLD_TX_FIFO_EMPTY (Bit 7)                        */
-#define I2C_I2C_STATUS_REG_MST_HOLD_TX_FIFO_EMPTY_Msk (0x80UL)      /*!< MST_HOLD_TX_FIFO_EMPTY (Bitfield-Mask: 0x01)          */
-#define I2C_I2C_STATUS_REG_SLV_ACTIVITY_Pos (6UL)                   /*!< SLV_ACTIVITY (Bit 6)                                  */
-#define I2C_I2C_STATUS_REG_SLV_ACTIVITY_Msk (0x40UL)                /*!< SLV_ACTIVITY (Bitfield-Mask: 0x01)                    */
-#define I2C_I2C_STATUS_REG_MST_ACTIVITY_Pos (5UL)                   /*!< MST_ACTIVITY (Bit 5)                                  */
-#define I2C_I2C_STATUS_REG_MST_ACTIVITY_Msk (0x20UL)                /*!< MST_ACTIVITY (Bitfield-Mask: 0x01)                    */
-#define I2C_I2C_STATUS_REG_RFF_Pos        (4UL)                     /*!< RFF (Bit 4)                                           */
-#define I2C_I2C_STATUS_REG_RFF_Msk        (0x10UL)                  /*!< RFF (Bitfield-Mask: 0x01)                             */
-#define I2C_I2C_STATUS_REG_RFNE_Pos       (3UL)                     /*!< RFNE (Bit 3)                                          */
-#define I2C_I2C_STATUS_REG_RFNE_Msk       (0x8UL)                   /*!< RFNE (Bitfield-Mask: 0x01)                            */
-#define I2C_I2C_STATUS_REG_TFE_Pos        (2UL)                     /*!< TFE (Bit 2)                                           */
-#define I2C_I2C_STATUS_REG_TFE_Msk        (0x4UL)                   /*!< TFE (Bitfield-Mask: 0x01)                             */
-#define I2C_I2C_STATUS_REG_TFNF_Pos       (1UL)                     /*!< TFNF (Bit 1)                                          */
-#define I2C_I2C_STATUS_REG_TFNF_Msk       (0x2UL)                   /*!< TFNF (Bitfield-Mask: 0x01)                            */
-#define I2C_I2C_STATUS_REG_I2C_ACTIVITY_Pos (0UL)                   /*!< I2C_ACTIVITY (Bit 0)                                  */
-#define I2C_I2C_STATUS_REG_I2C_ACTIVITY_Msk (0x1UL)                 /*!< I2C_ACTIVITY (Bitfield-Mask: 0x01)                    */
-/* ======================================================  I2C_TAR_REG  ====================================================== */
-#define I2C_I2C_TAR_REG_SPECIAL_Pos       (11UL)                    /*!< SPECIAL (Bit 11)                                      */
-#define I2C_I2C_TAR_REG_SPECIAL_Msk       (0x800UL)                 /*!< SPECIAL (Bitfield-Mask: 0x01)                         */
-#define I2C_I2C_TAR_REG_GC_OR_START_Pos   (10UL)                    /*!< GC_OR_START (Bit 10)                                  */
-#define I2C_I2C_TAR_REG_GC_OR_START_Msk   (0x400UL)                 /*!< GC_OR_START (Bitfield-Mask: 0x01)                     */
-#define I2C_I2C_TAR_REG_IC_TAR_Pos        (0UL)                     /*!< IC_TAR (Bit 0)                                        */
-#define I2C_I2C_TAR_REG_IC_TAR_Msk        (0x3ffUL)                 /*!< IC_TAR (Bitfield-Mask: 0x3ff)                         */
-/* =====================================================  I2C_TXFLR_REG  ===================================================== */
-#define I2C_I2C_TXFLR_REG_TXFLR_Pos       (0UL)                     /*!< TXFLR (Bit 0)                                         */
-#define I2C_I2C_TXFLR_REG_TXFLR_Msk       (0x3fUL)                  /*!< TXFLR (Bitfield-Mask: 0x3f)                           */
-/* ================================================  I2C_TX_ABRT_SOURCE_REG  ================================================= */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_USER_ABRT_Pos (16UL)        /*!< ABRT_USER_ABRT (Bit 16)                               */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_USER_ABRT_Msk (0x10000UL)   /*!< ABRT_USER_ABRT (Bitfield-Mask: 0x01)                  */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Pos (15UL)       /*!< ABRT_SLVRD_INTX (Bit 15)                              */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Msk (0x8000UL)   /*!< ABRT_SLVRD_INTX (Bitfield-Mask: 0x01)                 */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Pos (14UL)      /*!< ABRT_SLV_ARBLOST (Bit 14)                             */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Msk (0x4000UL)  /*!< ABRT_SLV_ARBLOST (Bitfield-Mask: 0x01)                */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Pos (13UL)  /*!< ABRT_SLVFLUSH_TXFIFO (Bit 13)                         */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Msk (0x2000UL) /*!< ABRT_SLVFLUSH_TXFIFO (Bitfield-Mask: 0x01)         */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ARB_LOST_Pos (12UL)              /*!< ARB_LOST (Bit 12)                                     */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ARB_LOST_Msk (0x1000UL)          /*!< ARB_LOST (Bitfield-Mask: 0x01)                        */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Pos (11UL)       /*!< ABRT_MASTER_DIS (Bit 11)                              */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Msk (0x800UL)    /*!< ABRT_MASTER_DIS (Bitfield-Mask: 0x01)                 */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Pos (10UL)   /*!< ABRT_10B_RD_NORSTRT (Bit 10)                          */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Msk (0x400UL) /*!< ABRT_10B_RD_NORSTRT (Bitfield-Mask: 0x01)            */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Pos (9UL)     /*!< ABRT_SBYTE_NORSTRT (Bit 9)                            */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Msk (0x200UL) /*!< ABRT_SBYTE_NORSTRT (Bitfield-Mask: 0x01)              */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Pos (8UL)        /*!< ABRT_HS_NORSTRT (Bit 8)                               */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Msk (0x100UL)    /*!< ABRT_HS_NORSTRT (Bitfield-Mask: 0x01)                 */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Pos (7UL)      /*!< ABRT_SBYTE_ACKDET (Bit 7)                             */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Msk (0x80UL)   /*!< ABRT_SBYTE_ACKDET (Bitfield-Mask: 0x01)               */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Pos (6UL)         /*!< ABRT_HS_ACKDET (Bit 6)                                */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Msk (0x40UL)      /*!< ABRT_HS_ACKDET (Bitfield-Mask: 0x01)                  */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Pos (5UL)        /*!< ABRT_GCALL_READ (Bit 5)                               */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Msk (0x20UL)     /*!< ABRT_GCALL_READ (Bitfield-Mask: 0x01)                 */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Pos (4UL)       /*!< ABRT_GCALL_NOACK (Bit 4)                              */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Msk (0x10UL)    /*!< ABRT_GCALL_NOACK (Bitfield-Mask: 0x01)                */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Pos (3UL)      /*!< ABRT_TXDATA_NOACK (Bit 3)                             */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Msk (0x8UL)    /*!< ABRT_TXDATA_NOACK (Bitfield-Mask: 0x01)               */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Pos (2UL)     /*!< ABRT_10ADDR2_NOACK (Bit 2)                            */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Msk (0x4UL)   /*!< ABRT_10ADDR2_NOACK (Bitfield-Mask: 0x01)              */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Pos (1UL)     /*!< ABRT_10ADDR1_NOACK (Bit 1)                            */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Msk (0x2UL)   /*!< ABRT_10ADDR1_NOACK (Bitfield-Mask: 0x01)              */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Pos (0UL)     /*!< ABRT_7B_ADDR_NOACK (Bit 0)                            */
-#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Msk (0x1UL)   /*!< ABRT_7B_ADDR_NOACK (Bitfield-Mask: 0x01)              */
-/* =====================================================  I2C_TX_TL_REG  ===================================================== */
-#define I2C_I2C_TX_TL_REG_TX_TL_Pos       (0UL)                     /*!< TX_TL (Bit 0)                                         */
-#define I2C_I2C_TX_TL_REG_TX_TL_Msk       (0x1fUL)                  /*!< TX_TL (Bitfield-Mask: 0x1f)                           */
-
-
-/* =========================================================================================================================== */
-/* ================                                           I2C2                                            ================ */
-/* =========================================================================================================================== */
-
-/* ===============================================  I2C2_ACK_GENERAL_CALL_REG  =============================================== */
-#define I2C2_I2C2_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Pos (0UL)       /*!< ACK_GEN_CALL (Bit 0)                                  */
-#define I2C2_I2C2_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Msk (0x1UL)     /*!< ACK_GEN_CALL (Bitfield-Mask: 0x01)                    */
-/* =================================================  I2C2_CLR_ACTIVITY_REG  ================================================= */
-#define I2C2_I2C2_CLR_ACTIVITY_REG_CLR_ACTIVITY_Pos (0UL)           /*!< CLR_ACTIVITY (Bit 0)                                  */
-#define I2C2_I2C2_CLR_ACTIVITY_REG_CLR_ACTIVITY_Msk (0x1UL)         /*!< CLR_ACTIVITY (Bitfield-Mask: 0x01)                    */
-/* =================================================  I2C2_CLR_GEN_CALL_REG  ================================================= */
-#define I2C2_I2C2_CLR_GEN_CALL_REG_CLR_GEN_CALL_Pos (0UL)           /*!< CLR_GEN_CALL (Bit 0)                                  */
-#define I2C2_I2C2_CLR_GEN_CALL_REG_CLR_GEN_CALL_Msk (0x1UL)         /*!< CLR_GEN_CALL (Bitfield-Mask: 0x01)                    */
-/* ===================================================  I2C2_CLR_INTR_REG  =================================================== */
-#define I2C2_I2C2_CLR_INTR_REG_CLR_INTR_Pos (0UL)                   /*!< CLR_INTR (Bit 0)                                      */
-#define I2C2_I2C2_CLR_INTR_REG_CLR_INTR_Msk (0x1UL)                 /*!< CLR_INTR (Bitfield-Mask: 0x01)                        */
-/* ==================================================  I2C2_CLR_RD_REQ_REG  ================================================== */
-#define I2C2_I2C2_CLR_RD_REQ_REG_CLR_RD_REQ_Pos (0UL)               /*!< CLR_RD_REQ (Bit 0)                                    */
-#define I2C2_I2C2_CLR_RD_REQ_REG_CLR_RD_REQ_Msk (0x1UL)             /*!< CLR_RD_REQ (Bitfield-Mask: 0x01)                      */
-/* =================================================  I2C2_CLR_RX_DONE_REG  ================================================== */
-#define I2C2_I2C2_CLR_RX_DONE_REG_CLR_RX_DONE_Pos (0UL)             /*!< CLR_RX_DONE (Bit 0)                                   */
-#define I2C2_I2C2_CLR_RX_DONE_REG_CLR_RX_DONE_Msk (0x1UL)           /*!< CLR_RX_DONE (Bitfield-Mask: 0x01)                     */
-/* =================================================  I2C2_CLR_RX_OVER_REG  ================================================== */
-#define I2C2_I2C2_CLR_RX_OVER_REG_CLR_RX_OVER_Pos (0UL)             /*!< CLR_RX_OVER (Bit 0)                                   */
-#define I2C2_I2C2_CLR_RX_OVER_REG_CLR_RX_OVER_Msk (0x1UL)           /*!< CLR_RX_OVER (Bitfield-Mask: 0x01)                     */
-/* =================================================  I2C2_CLR_RX_UNDER_REG  ================================================= */
-#define I2C2_I2C2_CLR_RX_UNDER_REG_CLR_RX_UNDER_Pos (0UL)           /*!< CLR_RX_UNDER (Bit 0)                                  */
-#define I2C2_I2C2_CLR_RX_UNDER_REG_CLR_RX_UNDER_Msk (0x1UL)         /*!< CLR_RX_UNDER (Bitfield-Mask: 0x01)                    */
-/* ================================================  I2C2_CLR_START_DET_REG  ================================================= */
-#define I2C2_I2C2_CLR_START_DET_REG_CLR_START_DET_Pos (0UL)         /*!< CLR_START_DET (Bit 0)                                 */
-#define I2C2_I2C2_CLR_START_DET_REG_CLR_START_DET_Msk (0x1UL)       /*!< CLR_START_DET (Bitfield-Mask: 0x01)                   */
-/* =================================================  I2C2_CLR_STOP_DET_REG  ================================================= */
-#define I2C2_I2C2_CLR_STOP_DET_REG_CLR_STOP_DET_Pos (0UL)           /*!< CLR_STOP_DET (Bit 0)                                  */
-#define I2C2_I2C2_CLR_STOP_DET_REG_CLR_STOP_DET_Msk (0x1UL)         /*!< CLR_STOP_DET (Bitfield-Mask: 0x01)                    */
-/* =================================================  I2C2_CLR_TX_ABRT_REG  ================================================== */
-#define I2C2_I2C2_CLR_TX_ABRT_REG_CLR_TX_ABRT_Pos (0UL)             /*!< CLR_TX_ABRT (Bit 0)                                   */
-#define I2C2_I2C2_CLR_TX_ABRT_REG_CLR_TX_ABRT_Msk (0x1UL)           /*!< CLR_TX_ABRT (Bitfield-Mask: 0x01)                     */
-/* =================================================  I2C2_CLR_TX_OVER_REG  ================================================== */
-#define I2C2_I2C2_CLR_TX_OVER_REG_CLR_TX_OVER_Pos (0UL)             /*!< CLR_TX_OVER (Bit 0)                                   */
-#define I2C2_I2C2_CLR_TX_OVER_REG_CLR_TX_OVER_Msk (0x1UL)           /*!< CLR_TX_OVER (Bitfield-Mask: 0x01)                     */
-/* =====================================================  I2C2_CON_REG  ====================================================== */
-#define I2C2_I2C2_CON_REG_I2C_STOP_DET_IF_MASTER_ACTIVE_Pos (10UL)  /*!< I2C_STOP_DET_IF_MASTER_ACTIVE (Bit 10)                */
-#define I2C2_I2C2_CON_REG_I2C_STOP_DET_IF_MASTER_ACTIVE_Msk (0x400UL) /*!< I2C_STOP_DET_IF_MASTER_ACTIVE (Bitfield-Mask: 0x01) */
-#define I2C2_I2C2_CON_REG_I2C_RX_FIFO_FULL_HLD_CTRL_Pos (9UL)       /*!< I2C_RX_FIFO_FULL_HLD_CTRL (Bit 9)                     */
-#define I2C2_I2C2_CON_REG_I2C_RX_FIFO_FULL_HLD_CTRL_Msk (0x200UL)   /*!< I2C_RX_FIFO_FULL_HLD_CTRL (Bitfield-Mask: 0x01)       */
-#define I2C2_I2C2_CON_REG_I2C_TX_EMPTY_CTRL_Pos (8UL)               /*!< I2C_TX_EMPTY_CTRL (Bit 8)                             */
-#define I2C2_I2C2_CON_REG_I2C_TX_EMPTY_CTRL_Msk (0x100UL)           /*!< I2C_TX_EMPTY_CTRL (Bitfield-Mask: 0x01)               */
-#define I2C2_I2C2_CON_REG_I2C_STOP_DET_IFADDRESSED_Pos (7UL)        /*!< I2C_STOP_DET_IFADDRESSED (Bit 7)                      */
-#define I2C2_I2C2_CON_REG_I2C_STOP_DET_IFADDRESSED_Msk (0x80UL)     /*!< I2C_STOP_DET_IFADDRESSED (Bitfield-Mask: 0x01)        */
-#define I2C2_I2C2_CON_REG_I2C_SLAVE_DISABLE_Pos (6UL)               /*!< I2C_SLAVE_DISABLE (Bit 6)                             */
-#define I2C2_I2C2_CON_REG_I2C_SLAVE_DISABLE_Msk (0x40UL)            /*!< I2C_SLAVE_DISABLE (Bitfield-Mask: 0x01)               */
-#define I2C2_I2C2_CON_REG_I2C_RESTART_EN_Pos (5UL)                  /*!< I2C_RESTART_EN (Bit 5)                                */
-#define I2C2_I2C2_CON_REG_I2C_RESTART_EN_Msk (0x20UL)               /*!< I2C_RESTART_EN (Bitfield-Mask: 0x01)                  */
-#define I2C2_I2C2_CON_REG_I2C_10BITADDR_MASTER_Pos (4UL)            /*!< I2C_10BITADDR_MASTER (Bit 4)                          */
-#define I2C2_I2C2_CON_REG_I2C_10BITADDR_MASTER_Msk (0x10UL)         /*!< I2C_10BITADDR_MASTER (Bitfield-Mask: 0x01)            */
-#define I2C2_I2C2_CON_REG_I2C_10BITADDR_SLAVE_Pos (3UL)             /*!< I2C_10BITADDR_SLAVE (Bit 3)                           */
-#define I2C2_I2C2_CON_REG_I2C_10BITADDR_SLAVE_Msk (0x8UL)           /*!< I2C_10BITADDR_SLAVE (Bitfield-Mask: 0x01)             */
-#define I2C2_I2C2_CON_REG_I2C_SPEED_Pos   (1UL)                     /*!< I2C_SPEED (Bit 1)                                     */
-#define I2C2_I2C2_CON_REG_I2C_SPEED_Msk   (0x6UL)                   /*!< I2C_SPEED (Bitfield-Mask: 0x03)                       */
-#define I2C2_I2C2_CON_REG_I2C_MASTER_MODE_Pos (0UL)                 /*!< I2C_MASTER_MODE (Bit 0)                               */
-#define I2C2_I2C2_CON_REG_I2C_MASTER_MODE_Msk (0x1UL)               /*!< I2C_MASTER_MODE (Bitfield-Mask: 0x01)                 */
-/* ===================================================  I2C2_DATA_CMD_REG  =================================================== */
-#define I2C2_I2C2_DATA_CMD_REG_I2C_RESTART_Pos (10UL)               /*!< I2C_RESTART (Bit 10)                                  */
-#define I2C2_I2C2_DATA_CMD_REG_I2C_RESTART_Msk (0x400UL)            /*!< I2C_RESTART (Bitfield-Mask: 0x01)                     */
-#define I2C2_I2C2_DATA_CMD_REG_I2C_STOP_Pos (9UL)                   /*!< I2C_STOP (Bit 9)                                      */
-#define I2C2_I2C2_DATA_CMD_REG_I2C_STOP_Msk (0x200UL)               /*!< I2C_STOP (Bitfield-Mask: 0x01)                        */
-#define I2C2_I2C2_DATA_CMD_REG_I2C_CMD_Pos (8UL)                    /*!< I2C_CMD (Bit 8)                                       */
-#define I2C2_I2C2_DATA_CMD_REG_I2C_CMD_Msk (0x100UL)                /*!< I2C_CMD (Bitfield-Mask: 0x01)                         */
-#define I2C2_I2C2_DATA_CMD_REG_I2C_DAT_Pos (0UL)                    /*!< I2C_DAT (Bit 0)                                       */
-#define I2C2_I2C2_DATA_CMD_REG_I2C_DAT_Msk (0xffUL)                 /*!< I2C_DAT (Bitfield-Mask: 0xff)                         */
-/* ====================================================  I2C2_DMA_CR_REG  ==================================================== */
-#define I2C2_I2C2_DMA_CR_REG_TDMAE_Pos    (1UL)                     /*!< TDMAE (Bit 1)                                         */
-#define I2C2_I2C2_DMA_CR_REG_TDMAE_Msk    (0x2UL)                   /*!< TDMAE (Bitfield-Mask: 0x01)                           */
-#define I2C2_I2C2_DMA_CR_REG_RDMAE_Pos    (0UL)                     /*!< RDMAE (Bit 0)                                         */
-#define I2C2_I2C2_DMA_CR_REG_RDMAE_Msk    (0x1UL)                   /*!< RDMAE (Bitfield-Mask: 0x01)                           */
-/* ===================================================  I2C2_DMA_RDLR_REG  =================================================== */
-#define I2C2_I2C2_DMA_RDLR_REG_DMARDL_Pos (0UL)                     /*!< DMARDL (Bit 0)                                        */
-#define I2C2_I2C2_DMA_RDLR_REG_DMARDL_Msk (0x1fUL)                  /*!< DMARDL (Bitfield-Mask: 0x1f)                          */
-/* ===================================================  I2C2_DMA_TDLR_REG  =================================================== */
-#define I2C2_I2C2_DMA_TDLR_REG_DMATDL_Pos (0UL)                     /*!< DMATDL (Bit 0)                                        */
-#define I2C2_I2C2_DMA_TDLR_REG_DMATDL_Msk (0x1fUL)                  /*!< DMATDL (Bitfield-Mask: 0x1f)                          */
-/* ====================================================  I2C2_ENABLE_REG  ==================================================== */
-#define I2C2_I2C2_ENABLE_REG_I2C_TX_CMD_BLOCK_Pos (2UL)             /*!< I2C_TX_CMD_BLOCK (Bit 2)                              */
-#define I2C2_I2C2_ENABLE_REG_I2C_TX_CMD_BLOCK_Msk (0x4UL)           /*!< I2C_TX_CMD_BLOCK (Bitfield-Mask: 0x01)                */
-#define I2C2_I2C2_ENABLE_REG_I2C_ABORT_Pos (1UL)                    /*!< I2C_ABORT (Bit 1)                                     */
-#define I2C2_I2C2_ENABLE_REG_I2C_ABORT_Msk (0x2UL)                  /*!< I2C_ABORT (Bitfield-Mask: 0x01)                       */
-#define I2C2_I2C2_ENABLE_REG_I2C_EN_Pos   (0UL)                     /*!< I2C_EN (Bit 0)                                        */
-#define I2C2_I2C2_ENABLE_REG_I2C_EN_Msk   (0x1UL)                   /*!< I2C_EN (Bitfield-Mask: 0x01)                          */
-/* ================================================  I2C2_ENABLE_STATUS_REG  ================================================= */
-#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Pos (2UL)      /*!< SLV_RX_DATA_LOST (Bit 2)                              */
-#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Msk (0x4UL)    /*!< SLV_RX_DATA_LOST (Bitfield-Mask: 0x01)                */
-#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Pos (1UL) /*!< SLV_DISABLED_WHILE_BUSY (Bit 1)                     */
-#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Msk (0x2UL) /*!< SLV_DISABLED_WHILE_BUSY (Bitfield-Mask: 0x01)     */
-#define I2C2_I2C2_ENABLE_STATUS_REG_IC_EN_Pos (0UL)                 /*!< IC_EN (Bit 0)                                         */
-#define I2C2_I2C2_ENABLE_STATUS_REG_IC_EN_Msk (0x1UL)               /*!< IC_EN (Bitfield-Mask: 0x01)                           */
-/* =================================================  I2C2_FS_SCL_HCNT_REG  ================================================== */
-#define I2C2_I2C2_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Pos (0UL)          /*!< IC_FS_SCL_HCNT (Bit 0)                                */
-#define I2C2_I2C2_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Msk (0xffffUL)     /*!< IC_FS_SCL_HCNT (Bitfield-Mask: 0xffff)                */
-/* =================================================  I2C2_FS_SCL_LCNT_REG  ================================================== */
-#define I2C2_I2C2_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Pos (0UL)          /*!< IC_FS_SCL_LCNT (Bit 0)                                */
-#define I2C2_I2C2_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Msk (0xffffUL)     /*!< IC_FS_SCL_LCNT (Bitfield-Mask: 0xffff)                */
-/* ===================================================  I2C2_HS_MADDR_REG  =================================================== */
-#define I2C2_I2C2_HS_MADDR_REG_I2C_IC_HS_MAR_Pos (0UL)              /*!< I2C_IC_HS_MAR (Bit 0)                                 */
-#define I2C2_I2C2_HS_MADDR_REG_I2C_IC_HS_MAR_Msk (0x7UL)            /*!< I2C_IC_HS_MAR (Bitfield-Mask: 0x07)                   */
-/* =================================================  I2C2_HS_SCL_HCNT_REG  ================================================== */
-#define I2C2_I2C2_HS_SCL_HCNT_REG_IC_HS_SCL_HCNT_Pos (0UL)          /*!< IC_HS_SCL_HCNT (Bit 0)                                */
-#define I2C2_I2C2_HS_SCL_HCNT_REG_IC_HS_SCL_HCNT_Msk (0xffffUL)     /*!< IC_HS_SCL_HCNT (Bitfield-Mask: 0xffff)                */
-/* =================================================  I2C2_HS_SCL_LCNT_REG  ================================================== */
-#define I2C2_I2C2_HS_SCL_LCNT_REG_IC_HS_SCL_LCNT_Pos (0UL)          /*!< IC_HS_SCL_LCNT (Bit 0)                                */
-#define I2C2_I2C2_HS_SCL_LCNT_REG_IC_HS_SCL_LCNT_Msk (0xffffUL)     /*!< IC_HS_SCL_LCNT (Bitfield-Mask: 0xffff)                */
-/* =================================================  I2C2_IC_FS_SPKLEN_REG  ================================================= */
-#define I2C2_I2C2_IC_FS_SPKLEN_REG_I2C_FS_SPKLEN_Pos (0UL)          /*!< I2C_FS_SPKLEN (Bit 0)                                 */
-#define I2C2_I2C2_IC_FS_SPKLEN_REG_I2C_FS_SPKLEN_Msk (0xffUL)       /*!< I2C_FS_SPKLEN (Bitfield-Mask: 0xff)                   */
-/* =================================================  I2C2_IC_HS_SPKLEN_REG  ================================================= */
-#define I2C2_I2C2_IC_HS_SPKLEN_REG_I2C_HS_SPKLEN_Pos (0UL)          /*!< I2C_HS_SPKLEN (Bit 0)                                 */
-#define I2C2_I2C2_IC_HS_SPKLEN_REG_I2C_HS_SPKLEN_Msk (0xffUL)       /*!< I2C_HS_SPKLEN (Bitfield-Mask: 0xff)                   */
-/* ==================================================  I2C2_INTR_MASK_REG  =================================================== */
-#define I2C2_I2C2_INTR_MASK_REG_M_SCL_STUCK_AT_LOW_Pos (14UL)       /*!< M_SCL_STUCK_AT_LOW (Bit 14)                           */
-#define I2C2_I2C2_INTR_MASK_REG_M_SCL_STUCK_AT_LOW_Msk (0x4000UL)   /*!< M_SCL_STUCK_AT_LOW (Bitfield-Mask: 0x01)              */
-#define I2C2_I2C2_INTR_MASK_REG_M_MASTER_ON_HOLD_Pos (13UL)         /*!< M_MASTER_ON_HOLD (Bit 13)                             */
-#define I2C2_I2C2_INTR_MASK_REG_M_MASTER_ON_HOLD_Msk (0x2000UL)     /*!< M_MASTER_ON_HOLD (Bitfield-Mask: 0x01)                */
-#define I2C2_I2C2_INTR_MASK_REG_M_RESTART_DET_Pos (12UL)            /*!< M_RESTART_DET (Bit 12)                                */
-#define I2C2_I2C2_INTR_MASK_REG_M_RESTART_DET_Msk (0x1000UL)        /*!< M_RESTART_DET (Bitfield-Mask: 0x01)                   */
-#define I2C2_I2C2_INTR_MASK_REG_M_GEN_CALL_Pos (11UL)               /*!< M_GEN_CALL (Bit 11)                                   */
-#define I2C2_I2C2_INTR_MASK_REG_M_GEN_CALL_Msk (0x800UL)            /*!< M_GEN_CALL (Bitfield-Mask: 0x01)                      */
-#define I2C2_I2C2_INTR_MASK_REG_M_START_DET_Pos (10UL)              /*!< M_START_DET (Bit 10)                                  */
-#define I2C2_I2C2_INTR_MASK_REG_M_START_DET_Msk (0x400UL)           /*!< M_START_DET (Bitfield-Mask: 0x01)                     */
-#define I2C2_I2C2_INTR_MASK_REG_M_STOP_DET_Pos (9UL)                /*!< M_STOP_DET (Bit 9)                                    */
-#define I2C2_I2C2_INTR_MASK_REG_M_STOP_DET_Msk (0x200UL)            /*!< M_STOP_DET (Bitfield-Mask: 0x01)                      */
-#define I2C2_I2C2_INTR_MASK_REG_M_ACTIVITY_Pos (8UL)                /*!< M_ACTIVITY (Bit 8)                                    */
-#define I2C2_I2C2_INTR_MASK_REG_M_ACTIVITY_Msk (0x100UL)            /*!< M_ACTIVITY (Bitfield-Mask: 0x01)                      */
-#define I2C2_I2C2_INTR_MASK_REG_M_RX_DONE_Pos (7UL)                 /*!< M_RX_DONE (Bit 7)                                     */
-#define I2C2_I2C2_INTR_MASK_REG_M_RX_DONE_Msk (0x80UL)              /*!< M_RX_DONE (Bitfield-Mask: 0x01)                       */
-#define I2C2_I2C2_INTR_MASK_REG_M_TX_ABRT_Pos (6UL)                 /*!< M_TX_ABRT (Bit 6)                                     */
-#define I2C2_I2C2_INTR_MASK_REG_M_TX_ABRT_Msk (0x40UL)              /*!< M_TX_ABRT (Bitfield-Mask: 0x01)                       */
-#define I2C2_I2C2_INTR_MASK_REG_M_RD_REQ_Pos (5UL)                  /*!< M_RD_REQ (Bit 5)                                      */
-#define I2C2_I2C2_INTR_MASK_REG_M_RD_REQ_Msk (0x20UL)               /*!< M_RD_REQ (Bitfield-Mask: 0x01)                        */
-#define I2C2_I2C2_INTR_MASK_REG_M_TX_EMPTY_Pos (4UL)                /*!< M_TX_EMPTY (Bit 4)                                    */
-#define I2C2_I2C2_INTR_MASK_REG_M_TX_EMPTY_Msk (0x10UL)             /*!< M_TX_EMPTY (Bitfield-Mask: 0x01)                      */
-#define I2C2_I2C2_INTR_MASK_REG_M_TX_OVER_Pos (3UL)                 /*!< M_TX_OVER (Bit 3)                                     */
-#define I2C2_I2C2_INTR_MASK_REG_M_TX_OVER_Msk (0x8UL)               /*!< M_TX_OVER (Bitfield-Mask: 0x01)                       */
-#define I2C2_I2C2_INTR_MASK_REG_M_RX_FULL_Pos (2UL)                 /*!< M_RX_FULL (Bit 2)                                     */
-#define I2C2_I2C2_INTR_MASK_REG_M_RX_FULL_Msk (0x4UL)               /*!< M_RX_FULL (Bitfield-Mask: 0x01)                       */
-#define I2C2_I2C2_INTR_MASK_REG_M_RX_OVER_Pos (1UL)                 /*!< M_RX_OVER (Bit 1)                                     */
-#define I2C2_I2C2_INTR_MASK_REG_M_RX_OVER_Msk (0x2UL)               /*!< M_RX_OVER (Bitfield-Mask: 0x01)                       */
-#define I2C2_I2C2_INTR_MASK_REG_M_RX_UNDER_Pos (0UL)                /*!< M_RX_UNDER (Bit 0)                                    */
-#define I2C2_I2C2_INTR_MASK_REG_M_RX_UNDER_Msk (0x1UL)              /*!< M_RX_UNDER (Bitfield-Mask: 0x01)                      */
-/* ==================================================  I2C2_INTR_STAT_REG  =================================================== */
-#define I2C2_I2C2_INTR_STAT_REG_R_SCL_STUCK_AT_LOW_Pos (14UL)       /*!< R_SCL_STUCK_AT_LOW (Bit 14)                           */
-#define I2C2_I2C2_INTR_STAT_REG_R_SCL_STUCK_AT_LOW_Msk (0x4000UL)   /*!< R_SCL_STUCK_AT_LOW (Bitfield-Mask: 0x01)              */
-#define I2C2_I2C2_INTR_STAT_REG_R_MASTER_ON_HOLD_Pos (13UL)         /*!< R_MASTER_ON_HOLD (Bit 13)                             */
-#define I2C2_I2C2_INTR_STAT_REG_R_MASTER_ON_HOLD_Msk (0x2000UL)     /*!< R_MASTER_ON_HOLD (Bitfield-Mask: 0x01)                */
-#define I2C2_I2C2_INTR_STAT_REG_R_RESTART_DET_Pos (12UL)            /*!< R_RESTART_DET (Bit 12)                                */
-#define I2C2_I2C2_INTR_STAT_REG_R_RESTART_DET_Msk (0x1000UL)        /*!< R_RESTART_DET (Bitfield-Mask: 0x01)                   */
-#define I2C2_I2C2_INTR_STAT_REG_R_GEN_CALL_Pos (11UL)               /*!< R_GEN_CALL (Bit 11)                                   */
-#define I2C2_I2C2_INTR_STAT_REG_R_GEN_CALL_Msk (0x800UL)            /*!< R_GEN_CALL (Bitfield-Mask: 0x01)                      */
-#define I2C2_I2C2_INTR_STAT_REG_R_START_DET_Pos (10UL)              /*!< R_START_DET (Bit 10)                                  */
-#define I2C2_I2C2_INTR_STAT_REG_R_START_DET_Msk (0x400UL)           /*!< R_START_DET (Bitfield-Mask: 0x01)                     */
-#define I2C2_I2C2_INTR_STAT_REG_R_STOP_DET_Pos (9UL)                /*!< R_STOP_DET (Bit 9)                                    */
-#define I2C2_I2C2_INTR_STAT_REG_R_STOP_DET_Msk (0x200UL)            /*!< R_STOP_DET (Bitfield-Mask: 0x01)                      */
-#define I2C2_I2C2_INTR_STAT_REG_R_ACTIVITY_Pos (8UL)                /*!< R_ACTIVITY (Bit 8)                                    */
-#define I2C2_I2C2_INTR_STAT_REG_R_ACTIVITY_Msk (0x100UL)            /*!< R_ACTIVITY (Bitfield-Mask: 0x01)                      */
-#define I2C2_I2C2_INTR_STAT_REG_R_RX_DONE_Pos (7UL)                 /*!< R_RX_DONE (Bit 7)                                     */
-#define I2C2_I2C2_INTR_STAT_REG_R_RX_DONE_Msk (0x80UL)              /*!< R_RX_DONE (Bitfield-Mask: 0x01)                       */
-#define I2C2_I2C2_INTR_STAT_REG_R_TX_ABRT_Pos (6UL)                 /*!< R_TX_ABRT (Bit 6)                                     */
-#define I2C2_I2C2_INTR_STAT_REG_R_TX_ABRT_Msk (0x40UL)              /*!< R_TX_ABRT (Bitfield-Mask: 0x01)                       */
-#define I2C2_I2C2_INTR_STAT_REG_R_RD_REQ_Pos (5UL)                  /*!< R_RD_REQ (Bit 5)                                      */
-#define I2C2_I2C2_INTR_STAT_REG_R_RD_REQ_Msk (0x20UL)               /*!< R_RD_REQ (Bitfield-Mask: 0x01)                        */
-#define I2C2_I2C2_INTR_STAT_REG_R_TX_EMPTY_Pos (4UL)                /*!< R_TX_EMPTY (Bit 4)                                    */
-#define I2C2_I2C2_INTR_STAT_REG_R_TX_EMPTY_Msk (0x10UL)             /*!< R_TX_EMPTY (Bitfield-Mask: 0x01)                      */
-#define I2C2_I2C2_INTR_STAT_REG_R_TX_OVER_Pos (3UL)                 /*!< R_TX_OVER (Bit 3)                                     */
-#define I2C2_I2C2_INTR_STAT_REG_R_TX_OVER_Msk (0x8UL)               /*!< R_TX_OVER (Bitfield-Mask: 0x01)                       */
-#define I2C2_I2C2_INTR_STAT_REG_R_RX_FULL_Pos (2UL)                 /*!< R_RX_FULL (Bit 2)                                     */
-#define I2C2_I2C2_INTR_STAT_REG_R_RX_FULL_Msk (0x4UL)               /*!< R_RX_FULL (Bitfield-Mask: 0x01)                       */
-#define I2C2_I2C2_INTR_STAT_REG_R_RX_OVER_Pos (1UL)                 /*!< R_RX_OVER (Bit 1)                                     */
-#define I2C2_I2C2_INTR_STAT_REG_R_RX_OVER_Msk (0x2UL)               /*!< R_RX_OVER (Bitfield-Mask: 0x01)                       */
-#define I2C2_I2C2_INTR_STAT_REG_R_RX_UNDER_Pos (0UL)                /*!< R_RX_UNDER (Bit 0)                                    */
-#define I2C2_I2C2_INTR_STAT_REG_R_RX_UNDER_Msk (0x1UL)              /*!< R_RX_UNDER (Bitfield-Mask: 0x01)                      */
-/* ================================================  I2C2_RAW_INTR_STAT_REG  ================================================= */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_SCL_STUCK_AT_LOW_Pos (14UL)     /*!< SCL_STUCK_AT_LOW (Bit 14)                             */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_SCL_STUCK_AT_LOW_Msk (0x4000UL) /*!< SCL_STUCK_AT_LOW (Bitfield-Mask: 0x01)                */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_MASTER_ON_HOLD_Pos (13UL)       /*!< MASTER_ON_HOLD (Bit 13)                               */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_MASTER_ON_HOLD_Msk (0x2000UL)   /*!< MASTER_ON_HOLD (Bitfield-Mask: 0x01)                  */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_RESTART_DET_Pos (12UL)          /*!< RESTART_DET (Bit 12)                                  */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_RESTART_DET_Msk (0x1000UL)      /*!< RESTART_DET (Bitfield-Mask: 0x01)                     */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_GEN_CALL_Pos (11UL)             /*!< GEN_CALL (Bit 11)                                     */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_GEN_CALL_Msk (0x800UL)          /*!< GEN_CALL (Bitfield-Mask: 0x01)                        */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_START_DET_Pos (10UL)            /*!< START_DET (Bit 10)                                    */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_START_DET_Msk (0x400UL)         /*!< START_DET (Bitfield-Mask: 0x01)                       */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_STOP_DET_Pos (9UL)              /*!< STOP_DET (Bit 9)                                      */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_STOP_DET_Msk (0x200UL)          /*!< STOP_DET (Bitfield-Mask: 0x01)                        */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_ACTIVITY_Pos (8UL)              /*!< ACTIVITY (Bit 8)                                      */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_ACTIVITY_Msk (0x100UL)          /*!< ACTIVITY (Bitfield-Mask: 0x01)                        */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_DONE_Pos (7UL)               /*!< RX_DONE (Bit 7)                                       */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_DONE_Msk (0x80UL)            /*!< RX_DONE (Bitfield-Mask: 0x01)                         */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_ABRT_Pos (6UL)               /*!< TX_ABRT (Bit 6)                                       */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_ABRT_Msk (0x40UL)            /*!< TX_ABRT (Bitfield-Mask: 0x01)                         */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_RD_REQ_Pos (5UL)                /*!< RD_REQ (Bit 5)                                        */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_RD_REQ_Msk (0x20UL)             /*!< RD_REQ (Bitfield-Mask: 0x01)                          */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_EMPTY_Pos (4UL)              /*!< TX_EMPTY (Bit 4)                                      */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_EMPTY_Msk (0x10UL)           /*!< TX_EMPTY (Bitfield-Mask: 0x01)                        */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_OVER_Pos (3UL)               /*!< TX_OVER (Bit 3)                                       */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_OVER_Msk (0x8UL)             /*!< TX_OVER (Bitfield-Mask: 0x01)                         */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_FULL_Pos (2UL)               /*!< RX_FULL (Bit 2)                                       */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_FULL_Msk (0x4UL)             /*!< RX_FULL (Bitfield-Mask: 0x01)                         */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_OVER_Pos (1UL)               /*!< RX_OVER (Bit 1)                                       */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_OVER_Msk (0x2UL)             /*!< RX_OVER (Bitfield-Mask: 0x01)                         */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_UNDER_Pos (0UL)              /*!< RX_UNDER (Bit 0)                                      */
-#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_UNDER_Msk (0x1UL)            /*!< RX_UNDER (Bitfield-Mask: 0x01)                        */
-/* ====================================================  I2C2_RXFLR_REG  ===================================================== */
-#define I2C2_I2C2_RXFLR_REG_RXFLR_Pos     (0UL)                     /*!< RXFLR (Bit 0)                                         */
-#define I2C2_I2C2_RXFLR_REG_RXFLR_Msk     (0x3fUL)                  /*!< RXFLR (Bitfield-Mask: 0x3f)                           */
-/* ====================================================  I2C2_RX_TL_REG  ===================================================== */
-#define I2C2_I2C2_RX_TL_REG_RX_TL_Pos     (0UL)                     /*!< RX_TL (Bit 0)                                         */
-#define I2C2_I2C2_RX_TL_REG_RX_TL_Msk     (0x1fUL)                  /*!< RX_TL (Bitfield-Mask: 0x1f)                           */
-/* =====================================================  I2C2_SAR_REG  ====================================================== */
-#define I2C2_I2C2_SAR_REG_IC_SAR_Pos      (0UL)                     /*!< IC_SAR (Bit 0)                                        */
-#define I2C2_I2C2_SAR_REG_IC_SAR_Msk      (0x3ffUL)                 /*!< IC_SAR (Bitfield-Mask: 0x3ff)                         */
-/* ===================================================  I2C2_SDA_HOLD_REG  =================================================== */
-#define I2C2_I2C2_SDA_HOLD_REG_I2C_SDA_RX_HOLD_Pos (16UL)           /*!< I2C_SDA_RX_HOLD (Bit 16)                              */
-#define I2C2_I2C2_SDA_HOLD_REG_I2C_SDA_RX_HOLD_Msk (0xff0000UL)     /*!< I2C_SDA_RX_HOLD (Bitfield-Mask: 0xff)                 */
-#define I2C2_I2C2_SDA_HOLD_REG_I2C_SDA_TX_HOLD_Pos (0UL)            /*!< I2C_SDA_TX_HOLD (Bit 0)                               */
-#define I2C2_I2C2_SDA_HOLD_REG_I2C_SDA_TX_HOLD_Msk (0xffffUL)       /*!< I2C_SDA_TX_HOLD (Bitfield-Mask: 0xffff)               */
-/* ==================================================  I2C2_SDA_SETUP_REG  =================================================== */
-#define I2C2_I2C2_SDA_SETUP_REG_SDA_SETUP_Pos (0UL)                 /*!< SDA_SETUP (Bit 0)                                     */
-#define I2C2_I2C2_SDA_SETUP_REG_SDA_SETUP_Msk (0xffUL)              /*!< SDA_SETUP (Bitfield-Mask: 0xff)                       */
-/* =================================================  I2C2_SS_SCL_HCNT_REG  ================================================== */
-#define I2C2_I2C2_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Pos (0UL)          /*!< IC_SS_SCL_HCNT (Bit 0)                                */
-#define I2C2_I2C2_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Msk (0xffffUL)     /*!< IC_SS_SCL_HCNT (Bitfield-Mask: 0xffff)                */
-/* =================================================  I2C2_SS_SCL_LCNT_REG  ================================================== */
-#define I2C2_I2C2_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Pos (0UL)          /*!< IC_SS_SCL_LCNT (Bit 0)                                */
-#define I2C2_I2C2_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Msk (0xffffUL)     /*!< IC_SS_SCL_LCNT (Bitfield-Mask: 0xffff)                */
-/* ====================================================  I2C2_STATUS_REG  ==================================================== */
-#define I2C2_I2C2_STATUS_REG_LV_HOLD_RX_FIFO_FULL_Pos (10UL)        /*!< LV_HOLD_RX_FIFO_FULL (Bit 10)                         */
-#define I2C2_I2C2_STATUS_REG_LV_HOLD_RX_FIFO_FULL_Msk (0x400UL)     /*!< LV_HOLD_RX_FIFO_FULL (Bitfield-Mask: 0x01)            */
-#define I2C2_I2C2_STATUS_REG_SLV_HOLD_TX_FIFO_EMPTY_Pos (9UL)       /*!< SLV_HOLD_TX_FIFO_EMPTY (Bit 9)                        */
-#define I2C2_I2C2_STATUS_REG_SLV_HOLD_TX_FIFO_EMPTY_Msk (0x200UL)   /*!< SLV_HOLD_TX_FIFO_EMPTY (Bitfield-Mask: 0x01)          */
-#define I2C2_I2C2_STATUS_REG_MST_HOLD_RX_FIFO_FULL_Pos (8UL)        /*!< MST_HOLD_RX_FIFO_FULL (Bit 8)                         */
-#define I2C2_I2C2_STATUS_REG_MST_HOLD_RX_FIFO_FULL_Msk (0x100UL)    /*!< MST_HOLD_RX_FIFO_FULL (Bitfield-Mask: 0x01)           */
-#define I2C2_I2C2_STATUS_REG_MST_HOLD_TX_FIFO_EMPTY_Pos (7UL)       /*!< MST_HOLD_TX_FIFO_EMPTY (Bit 7)                        */
-#define I2C2_I2C2_STATUS_REG_MST_HOLD_TX_FIFO_EMPTY_Msk (0x80UL)    /*!< MST_HOLD_TX_FIFO_EMPTY (Bitfield-Mask: 0x01)          */
-#define I2C2_I2C2_STATUS_REG_SLV_ACTIVITY_Pos (6UL)                 /*!< SLV_ACTIVITY (Bit 6)                                  */
-#define I2C2_I2C2_STATUS_REG_SLV_ACTIVITY_Msk (0x40UL)              /*!< SLV_ACTIVITY (Bitfield-Mask: 0x01)                    */
-#define I2C2_I2C2_STATUS_REG_MST_ACTIVITY_Pos (5UL)                 /*!< MST_ACTIVITY (Bit 5)                                  */
-#define I2C2_I2C2_STATUS_REG_MST_ACTIVITY_Msk (0x20UL)              /*!< MST_ACTIVITY (Bitfield-Mask: 0x01)                    */
-#define I2C2_I2C2_STATUS_REG_RFF_Pos      (4UL)                     /*!< RFF (Bit 4)                                           */
-#define I2C2_I2C2_STATUS_REG_RFF_Msk      (0x10UL)                  /*!< RFF (Bitfield-Mask: 0x01)                             */
-#define I2C2_I2C2_STATUS_REG_RFNE_Pos     (3UL)                     /*!< RFNE (Bit 3)                                          */
-#define I2C2_I2C2_STATUS_REG_RFNE_Msk     (0x8UL)                   /*!< RFNE (Bitfield-Mask: 0x01)                            */
-#define I2C2_I2C2_STATUS_REG_TFE_Pos      (2UL)                     /*!< TFE (Bit 2)                                           */
-#define I2C2_I2C2_STATUS_REG_TFE_Msk      (0x4UL)                   /*!< TFE (Bitfield-Mask: 0x01)                             */
-#define I2C2_I2C2_STATUS_REG_TFNF_Pos     (1UL)                     /*!< TFNF (Bit 1)                                          */
-#define I2C2_I2C2_STATUS_REG_TFNF_Msk     (0x2UL)                   /*!< TFNF (Bitfield-Mask: 0x01)                            */
-#define I2C2_I2C2_STATUS_REG_I2C_ACTIVITY_Pos (0UL)                 /*!< I2C_ACTIVITY (Bit 0)                                  */
-#define I2C2_I2C2_STATUS_REG_I2C_ACTIVITY_Msk (0x1UL)               /*!< I2C_ACTIVITY (Bitfield-Mask: 0x01)                    */
-/* =====================================================  I2C2_TAR_REG  ====================================================== */
-#define I2C2_I2C2_TAR_REG_SPECIAL_Pos     (11UL)                    /*!< SPECIAL (Bit 11)                                      */
-#define I2C2_I2C2_TAR_REG_SPECIAL_Msk     (0x800UL)                 /*!< SPECIAL (Bitfield-Mask: 0x01)                         */
-#define I2C2_I2C2_TAR_REG_GC_OR_START_Pos (10UL)                    /*!< GC_OR_START (Bit 10)                                  */
-#define I2C2_I2C2_TAR_REG_GC_OR_START_Msk (0x400UL)                 /*!< GC_OR_START (Bitfield-Mask: 0x01)                     */
-#define I2C2_I2C2_TAR_REG_IC_TAR_Pos      (0UL)                     /*!< IC_TAR (Bit 0)                                        */
-#define I2C2_I2C2_TAR_REG_IC_TAR_Msk      (0x3ffUL)                 /*!< IC_TAR (Bitfield-Mask: 0x3ff)                         */
-/* ====================================================  I2C2_TXFLR_REG  ===================================================== */
-#define I2C2_I2C2_TXFLR_REG_TXFLR_Pos     (0UL)                     /*!< TXFLR (Bit 0)                                         */
-#define I2C2_I2C2_TXFLR_REG_TXFLR_Msk     (0x3fUL)                  /*!< TXFLR (Bitfield-Mask: 0x3f)                           */
-/* ================================================  I2C2_TX_ABRT_SOURCE_REG  ================================================ */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_USER_ABRT_Pos (16UL)      /*!< ABRT_USER_ABRT (Bit 16)                               */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_USER_ABRT_Msk (0x10000UL) /*!< ABRT_USER_ABRT (Bitfield-Mask: 0x01)                  */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Pos (15UL)     /*!< ABRT_SLVRD_INTX (Bit 15)                              */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Msk (0x8000UL) /*!< ABRT_SLVRD_INTX (Bitfield-Mask: 0x01)                 */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Pos (14UL)    /*!< ABRT_SLV_ARBLOST (Bit 14)                             */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Msk (0x4000UL) /*!< ABRT_SLV_ARBLOST (Bitfield-Mask: 0x01)               */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Pos (13UL) /*!< ABRT_SLVFLUSH_TXFIFO (Bit 13)                        */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Msk (0x2000UL) /*!< ABRT_SLVFLUSH_TXFIFO (Bitfield-Mask: 0x01)       */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ARB_LOST_Pos (12UL)            /*!< ARB_LOST (Bit 12)                                     */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ARB_LOST_Msk (0x1000UL)        /*!< ARB_LOST (Bitfield-Mask: 0x01)                        */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Pos (11UL)     /*!< ABRT_MASTER_DIS (Bit 11)                              */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Msk (0x800UL)  /*!< ABRT_MASTER_DIS (Bitfield-Mask: 0x01)                 */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Pos (10UL) /*!< ABRT_10B_RD_NORSTRT (Bit 10)                          */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Msk (0x400UL) /*!< ABRT_10B_RD_NORSTRT (Bitfield-Mask: 0x01)          */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Pos (9UL)   /*!< ABRT_SBYTE_NORSTRT (Bit 9)                            */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Msk (0x200UL) /*!< ABRT_SBYTE_NORSTRT (Bitfield-Mask: 0x01)            */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Pos (8UL)      /*!< ABRT_HS_NORSTRT (Bit 8)                               */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Msk (0x100UL)  /*!< ABRT_HS_NORSTRT (Bitfield-Mask: 0x01)                 */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Pos (7UL)    /*!< ABRT_SBYTE_ACKDET (Bit 7)                             */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Msk (0x80UL) /*!< ABRT_SBYTE_ACKDET (Bitfield-Mask: 0x01)               */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Pos (6UL)       /*!< ABRT_HS_ACKDET (Bit 6)                                */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Msk (0x40UL)    /*!< ABRT_HS_ACKDET (Bitfield-Mask: 0x01)                  */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Pos (5UL)      /*!< ABRT_GCALL_READ (Bit 5)                               */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Msk (0x20UL)   /*!< ABRT_GCALL_READ (Bitfield-Mask: 0x01)                 */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Pos (4UL)     /*!< ABRT_GCALL_NOACK (Bit 4)                              */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Msk (0x10UL)  /*!< ABRT_GCALL_NOACK (Bitfield-Mask: 0x01)                */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Pos (3UL)    /*!< ABRT_TXDATA_NOACK (Bit 3)                             */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Msk (0x8UL)  /*!< ABRT_TXDATA_NOACK (Bitfield-Mask: 0x01)               */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Pos (2UL)   /*!< ABRT_10ADDR2_NOACK (Bit 2)                            */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Msk (0x4UL) /*!< ABRT_10ADDR2_NOACK (Bitfield-Mask: 0x01)              */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Pos (1UL)   /*!< ABRT_10ADDR1_NOACK (Bit 1)                            */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Msk (0x2UL) /*!< ABRT_10ADDR1_NOACK (Bitfield-Mask: 0x01)              */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Pos (0UL)   /*!< ABRT_7B_ADDR_NOACK (Bit 0)                            */
-#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Msk (0x1UL) /*!< ABRT_7B_ADDR_NOACK (Bitfield-Mask: 0x01)              */
-/* ====================================================  I2C2_TX_TL_REG  ===================================================== */
-#define I2C2_I2C2_TX_TL_REG_TX_TL_Pos     (0UL)                     /*!< TX_TL (Bit 0)                                         */
-#define I2C2_I2C2_TX_TL_REG_TX_TL_Msk     (0x1fUL)                  /*!< TX_TL (Bitfield-Mask: 0x1f)                           */
-
-
-/* =========================================================================================================================== */
-/* ================                                           LCDC                                            ================ */
-/* =========================================================================================================================== */
-
-/* =================================================  LCDC_BACKPORCHXY_REG  ================================================== */
-#define LCDC_LCDC_BACKPORCHXY_REG_LCDC_BPORCH_X_Pos (16UL)          /*!< LCDC_BPORCH_X (Bit 16)                                */
-#define LCDC_LCDC_BACKPORCHXY_REG_LCDC_BPORCH_X_Msk (0xffff0000UL)  /*!< LCDC_BPORCH_X (Bitfield-Mask: 0xffff)                 */
-#define LCDC_LCDC_BACKPORCHXY_REG_LCDC_BPORCH_Y_Pos (0UL)           /*!< LCDC_BPORCH_Y (Bit 0)                                 */
-#define LCDC_LCDC_BACKPORCHXY_REG_LCDC_BPORCH_Y_Msk (0xffffUL)      /*!< LCDC_BPORCH_Y (Bitfield-Mask: 0xffff)                 */
-/* ===================================================  LCDC_BGCOLOR_REG  ==================================================== */
-#define LCDC_LCDC_BGCOLOR_REG_LCDC_BG_RED_Pos (24UL)                /*!< LCDC_BG_RED (Bit 24)                                  */
-#define LCDC_LCDC_BGCOLOR_REG_LCDC_BG_RED_Msk (0xff000000UL)        /*!< LCDC_BG_RED (Bitfield-Mask: 0xff)                     */
-#define LCDC_LCDC_BGCOLOR_REG_LCDC_BG_GREEN_Pos (16UL)              /*!< LCDC_BG_GREEN (Bit 16)                                */
-#define LCDC_LCDC_BGCOLOR_REG_LCDC_BG_GREEN_Msk (0xff0000UL)        /*!< LCDC_BG_GREEN (Bitfield-Mask: 0xff)                   */
-#define LCDC_LCDC_BGCOLOR_REG_LCDC_BG_BLUE_Pos (8UL)                /*!< LCDC_BG_BLUE (Bit 8)                                  */
-#define LCDC_LCDC_BGCOLOR_REG_LCDC_BG_BLUE_Msk (0xff00UL)           /*!< LCDC_BG_BLUE (Bitfield-Mask: 0xff)                    */
-#define LCDC_LCDC_BGCOLOR_REG_LCDC_BG_ALPHA_Pos (0UL)               /*!< LCDC_BG_ALPHA (Bit 0)                                 */
-#define LCDC_LCDC_BGCOLOR_REG_LCDC_BG_ALPHA_Msk (0xffUL)            /*!< LCDC_BG_ALPHA (Bitfield-Mask: 0xff)                   */
-/* ==================================================  LCDC_BLANKINGXY_REG  ================================================== */
-#define LCDC_LCDC_BLANKINGXY_REG_LCDC_BLANKING_X_Pos (16UL)         /*!< LCDC_BLANKING_X (Bit 16)                              */
-#define LCDC_LCDC_BLANKINGXY_REG_LCDC_BLANKING_X_Msk (0xffff0000UL) /*!< LCDC_BLANKING_X (Bitfield-Mask: 0xffff)               */
-#define LCDC_LCDC_BLANKINGXY_REG_LCDC_BLANKING_Y_Pos (0UL)          /*!< LCDC_BLANKING_Y (Bit 0)                               */
-#define LCDC_LCDC_BLANKINGXY_REG_LCDC_BLANKING_Y_Msk (0xffffUL)     /*!< LCDC_BLANKING_Y (Bitfield-Mask: 0xffff)               */
-/* ===================================================  LCDC_CLKCTRL_REG  ==================================================== */
-#define LCDC_LCDC_CLKCTRL_REG_LCDC_SEC_CLK_DIV_Pos (27UL)           /*!< LCDC_SEC_CLK_DIV (Bit 27)                             */
-#define LCDC_LCDC_CLKCTRL_REG_LCDC_SEC_CLK_DIV_Msk (0xf8000000UL)   /*!< LCDC_SEC_CLK_DIV (Bitfield-Mask: 0x1f)                */
-#define LCDC_LCDC_CLKCTRL_REG_LCDC_DMA_HOLD_Pos (8UL)               /*!< LCDC_DMA_HOLD (Bit 8)                                 */
-#define LCDC_LCDC_CLKCTRL_REG_LCDC_DMA_HOLD_Msk (0x3f00UL)          /*!< LCDC_DMA_HOLD (Bitfield-Mask: 0x3f)                   */
-#define LCDC_LCDC_CLKCTRL_REG_LCDC_CLK_DIV_Pos (0UL)                /*!< LCDC_CLK_DIV (Bit 0)                                  */
-#define LCDC_LCDC_CLKCTRL_REG_LCDC_CLK_DIV_Msk (0x3fUL)             /*!< LCDC_CLK_DIV (Bitfield-Mask: 0x3f)                    */
-/* =====================================================  LCDC_CRC_REG  ====================================================== */
-#define LCDC_LCDC_CRC_REG_LCDC_CRC_Pos    (0UL)                     /*!< LCDC_CRC (Bit 0)                                      */
-#define LCDC_LCDC_CRC_REG_LCDC_CRC_Msk    (0xffffffffUL)            /*!< LCDC_CRC (Bitfield-Mask: 0xffffffff)                  */
-/* ===================================================  LCDC_DBIB_CFG_REG  =================================================== */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_TE_DIS_Pos (31UL)          /*!< LCDC_DBIB_TE_DIS (Bit 31)                             */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_TE_DIS_Msk (0x80000000UL)  /*!< LCDC_DBIB_TE_DIS (Bitfield-Mask: 0x01)                */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_CSX_FORCE_Pos (30UL)       /*!< LCDC_DBIB_CSX_FORCE (Bit 30)                          */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_CSX_FORCE_Msk (0x40000000UL) /*!< LCDC_DBIB_CSX_FORCE (Bitfield-Mask: 0x01)           */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_CSX_FORCE_VAL_Pos (29UL)   /*!< LCDC_DBIB_CSX_FORCE_VAL (Bit 29)                      */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_CSX_FORCE_VAL_Msk (0x20000000UL) /*!< LCDC_DBIB_CSX_FORCE_VAL (Bitfield-Mask: 0x01)   */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_PAD_Pos (28UL)         /*!< LCDC_DBIB_SPI_PAD (Bit 28)                            */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_PAD_Msk (0x10000000UL) /*!< LCDC_DBIB_SPI_PAD (Bitfield-Mask: 0x01)               */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_RESX_Pos (25UL)            /*!< LCDC_DBIB_RESX (Bit 25)                               */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_RESX_Msk (0x2000000UL)     /*!< LCDC_DBIB_RESX (Bitfield-Mask: 0x01)                  */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_DMA_EN_Pos (24UL)          /*!< LCDC_DBIB_DMA_EN (Bit 24)                             */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_DMA_EN_Msk (0x1000000UL)   /*!< LCDC_DBIB_DMA_EN (Bitfield-Mask: 0x01)                */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI3_EN_Pos (23UL)         /*!< LCDC_DBIB_SPI3_EN (Bit 23)                            */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI3_EN_Msk (0x800000UL)   /*!< LCDC_DBIB_SPI3_EN (Bitfield-Mask: 0x01)               */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI4_EN_Pos (22UL)         /*!< LCDC_DBIB_SPI4_EN (Bit 22)                            */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI4_EN_Msk (0x400000UL)   /*!< LCDC_DBIB_SPI4_EN (Bitfield-Mask: 0x01)               */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_CPHA_Pos (20UL)        /*!< LCDC_DBIB_SPI_CPHA (Bit 20)                           */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_CPHA_Msk (0x100000UL)  /*!< LCDC_DBIB_SPI_CPHA (Bitfield-Mask: 0x01)              */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_CPOL_Pos (19UL)        /*!< LCDC_DBIB_SPI_CPOL (Bit 19)                           */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_CPOL_Msk (0x80000UL)   /*!< LCDC_DBIB_SPI_CPOL (Bitfield-Mask: 0x01)              */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_JDI_Pos (18UL)         /*!< LCDC_DBIB_SPI_JDI (Bit 18)                            */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_JDI_Msk (0x40000UL)    /*!< LCDC_DBIB_SPI_JDI (Bitfield-Mask: 0x01)               */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_HOLD_Pos (17UL)        /*!< LCDC_DBIB_SPI_HOLD (Bit 17)                           */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_HOLD_Msk (0x20000UL)   /*!< LCDC_DBIB_SPI_HOLD (Bitfield-Mask: 0x01)              */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_INV_ADDR_Pos (16UL)    /*!< LCDC_DBIB_SPI_INV_ADDR (Bit 16)                       */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_INV_ADDR_Msk (0x10000UL) /*!< LCDC_DBIB_SPI_INV_ADDR (Bitfield-Mask: 0x01)        */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_INV_DATA_Pos (15UL)        /*!< LCDC_DBIB_INV_DATA (Bit 15)                           */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_INV_DATA_Msk (0x8000UL)    /*!< LCDC_DBIB_INV_DATA (Bitfield-Mask: 0x01)              */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_JDI_INV_PIX_Pos (14UL)     /*!< LCDC_DBIB_JDI_INV_PIX (Bit 14)                        */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_JDI_INV_PIX_Msk (0x4000UL) /*!< LCDC_DBIB_JDI_INV_PIX (Bitfield-Mask: 0x01)           */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_JDI_SOFT_RST_Pos (13UL)    /*!< LCDC_DBIB_JDI_SOFT_RST (Bit 13)                       */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_JDI_SOFT_RST_Msk (0x2000UL) /*!< LCDC_DBIB_JDI_SOFT_RST (Bitfield-Mask: 0x01)         */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_FMT_Pos (0UL)              /*!< LCDC_DBIB_FMT (Bit 0)                                 */
-#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_FMT_Msk (0x1fUL)           /*!< LCDC_DBIB_FMT (Bitfield-Mask: 0x1f)                   */
-/* ===================================================  LCDC_DBIB_CMD_REG  =================================================== */
-#define LCDC_LCDC_DBIB_CMD_REG_LCDC_DBIB_CMD_SEND_Pos (30UL)        /*!< LCDC_DBIB_CMD_SEND (Bit 30)                           */
-#define LCDC_LCDC_DBIB_CMD_REG_LCDC_DBIB_CMD_SEND_Msk (0x40000000UL) /*!< LCDC_DBIB_CMD_SEND (Bitfield-Mask: 0x01)             */
-#define LCDC_LCDC_DBIB_CMD_REG_LCDC_DBIB_CMD_STORE_Pos (27UL)       /*!< LCDC_DBIB_CMD_STORE (Bit 27)                          */
-#define LCDC_LCDC_DBIB_CMD_REG_LCDC_DBIB_CMD_STORE_Msk (0x8000000UL) /*!< LCDC_DBIB_CMD_STORE (Bitfield-Mask: 0x01)            */
-#define LCDC_LCDC_DBIB_CMD_REG_LCDC_DBIB_CMD_VAL_Pos (0UL)          /*!< LCDC_DBIB_CMD_VAL (Bit 0)                             */
-#define LCDC_LCDC_DBIB_CMD_REG_LCDC_DBIB_CMD_VAL_Msk (0xffffUL)     /*!< LCDC_DBIB_CMD_VAL (Bitfield-Mask: 0xffff)             */
-/* =================================================  LCDC_FRONTPORCHXY_REG  ================================================= */
-#define LCDC_LCDC_FRONTPORCHXY_REG_LCDC_FPORCH_X_Pos (16UL)         /*!< LCDC_FPORCH_X (Bit 16)                                */
-#define LCDC_LCDC_FRONTPORCHXY_REG_LCDC_FPORCH_X_Msk (0xffff0000UL) /*!< LCDC_FPORCH_X (Bitfield-Mask: 0xffff)                 */
-#define LCDC_LCDC_FRONTPORCHXY_REG_LCDC_FPORCH_Y_Pos (0UL)          /*!< LCDC_FPORCH_Y (Bit 0)                                 */
-#define LCDC_LCDC_FRONTPORCHXY_REG_LCDC_FPORCH_Y_Msk (0xffffUL)     /*!< LCDC_FPORCH_Y (Bitfield-Mask: 0xffff)                 */
-/* =====================================================  LCDC_GPIO_REG  ===================================================== */
-#define LCDC_LCDC_GPIO_REG_LCDC_TE_INV_Pos (1UL)                    /*!< LCDC_TE_INV (Bit 1)                                   */
-#define LCDC_LCDC_GPIO_REG_LCDC_TE_INV_Msk (0x2UL)                  /*!< LCDC_TE_INV (Bitfield-Mask: 0x01)                     */
-#define LCDC_LCDC_GPIO_REG_LCDC_PARIF_SEL_Pos (0UL)                 /*!< LCDC_PARIF_SEL (Bit 0)                                */
-#define LCDC_LCDC_GPIO_REG_LCDC_PARIF_SEL_Msk (0x1UL)               /*!< LCDC_PARIF_SEL (Bitfield-Mask: 0x01)                  */
-/* ====================================================  LCDC_IDREG_REG  ===================================================== */
-#define LCDC_LCDC_IDREG_REG_LCDC_ID_Pos   (0UL)                     /*!< LCDC_ID (Bit 0)                                       */
-#define LCDC_LCDC_IDREG_REG_LCDC_ID_Msk   (0xffffffffUL)            /*!< LCDC_ID (Bitfield-Mask: 0xffffffff)                   */
-/* ==================================================  LCDC_INTERRUPT_REG  =================================================== */
-#define LCDC_LCDC_INTERRUPT_REG_LCDC_IRQ_TRIGGER_SEL_Pos (31UL)     /*!< LCDC_IRQ_TRIGGER_SEL (Bit 31)                         */
-#define LCDC_LCDC_INTERRUPT_REG_LCDC_IRQ_TRIGGER_SEL_Msk (0x80000000UL) /*!< LCDC_IRQ_TRIGGER_SEL (Bitfield-Mask: 0x01)        */
-#define LCDC_LCDC_INTERRUPT_REG_LCDC_FRAME_END_IRQ_EN_Pos (5UL)     /*!< LCDC_FRAME_END_IRQ_EN (Bit 5)                         */
-#define LCDC_LCDC_INTERRUPT_REG_LCDC_FRAME_END_IRQ_EN_Msk (0x20UL)  /*!< LCDC_FRAME_END_IRQ_EN (Bitfield-Mask: 0x01)           */
-#define LCDC_LCDC_INTERRUPT_REG_LCDC_TE_IRQ_EN_Pos (3UL)            /*!< LCDC_TE_IRQ_EN (Bit 3)                                */
-#define LCDC_LCDC_INTERRUPT_REG_LCDC_TE_IRQ_EN_Msk (0x8UL)          /*!< LCDC_TE_IRQ_EN (Bitfield-Mask: 0x01)                  */
-#define LCDC_LCDC_INTERRUPT_REG_LCDC_HSYNC_IRQ_EN_Pos (1UL)         /*!< LCDC_HSYNC_IRQ_EN (Bit 1)                             */
-#define LCDC_LCDC_INTERRUPT_REG_LCDC_HSYNC_IRQ_EN_Msk (0x2UL)       /*!< LCDC_HSYNC_IRQ_EN (Bitfield-Mask: 0x01)               */
-#define LCDC_LCDC_INTERRUPT_REG_LCDC_VSYNC_IRQ_EN_Pos (0UL)         /*!< LCDC_VSYNC_IRQ_EN (Bit 0)                             */
-#define LCDC_LCDC_INTERRUPT_REG_LCDC_VSYNC_IRQ_EN_Msk (0x1UL)       /*!< LCDC_VSYNC_IRQ_EN (Bitfield-Mask: 0x01)               */
-/* ==============================================  LCDC_JDI_ENB_END_HLINE_REG  =============================================== */
-#define LCDC_LCDC_JDI_ENB_END_HLINE_REG_LCDC_JDI_ENB_END_HLINE_Pos (0UL) /*!< LCDC_JDI_ENB_END_HLINE (Bit 0)                   */
-#define LCDC_LCDC_JDI_ENB_END_HLINE_REG_LCDC_JDI_ENB_END_HLINE_Msk (0xffffffffUL) /*!< LCDC_JDI_ENB_END_HLINE (Bitfield-Mask: 0xffffffff) */
-/* ==============================================  LCDC_JDI_ENB_START_CLK_REG  =============================================== */
-#define LCDC_LCDC_JDI_ENB_START_CLK_REG_LCDC_JDI_ENB_START_CLK_Pos (0UL) /*!< LCDC_JDI_ENB_START_CLK (Bit 0)                   */
-#define LCDC_LCDC_JDI_ENB_START_CLK_REG_LCDC_JDI_ENB_START_CLK_Msk (0xffffffffUL) /*!< LCDC_JDI_ENB_START_CLK (Bitfield-Mask: 0xffffffff) */
-/* =============================================  LCDC_JDI_ENB_START_HLINE_REG  ============================================== */
-#define LCDC_LCDC_JDI_ENB_START_HLINE_REG_LCDC_JDI_ENB_START_HLINE_Pos (0UL) /*!< LCDC_JDI_ENB_START_HLINE (Bit 0)             */
-#define LCDC_LCDC_JDI_ENB_START_HLINE_REG_LCDC_JDI_ENB_START_HLINE_Msk (0xffffffffUL) /*!< LCDC_JDI_ENB_START_HLINE (Bitfield-Mask: 0xffffffff) */
-/* ==============================================  LCDC_JDI_ENB_WIDTH_CLK_REG  =============================================== */
-#define LCDC_LCDC_JDI_ENB_WIDTH_CLK_REG_LCDC_JDI_ENB_WIDTH_CLK_Pos (0UL) /*!< LCDC_JDI_ENB_WIDTH_CLK (Bit 0)                   */
-#define LCDC_LCDC_JDI_ENB_WIDTH_CLK_REG_LCDC_JDI_ENB_WIDTH_CLK_Msk (0xffffffffUL) /*!< LCDC_JDI_ENB_WIDTH_CLK (Bitfield-Mask: 0xffffffff) */
-/* ===============================================  LCDC_JDI_FBX_BLANKING_REG  =============================================== */
-#define LCDC_LCDC_JDI_FBX_BLANKING_REG_LCDC_JDI_FXBLANKING_Pos (16UL) /*!< LCDC_JDI_FXBLANKING (Bit 16)                        */
-#define LCDC_LCDC_JDI_FBX_BLANKING_REG_LCDC_JDI_FXBLANKING_Msk (0xffff0000UL) /*!< LCDC_JDI_FXBLANKING (Bitfield-Mask: 0xffff) */
-#define LCDC_LCDC_JDI_FBX_BLANKING_REG_LCDC_JDI_BXBLANKING_Pos (0UL) /*!< LCDC_JDI_BXBLANKING (Bit 0)                          */
-#define LCDC_LCDC_JDI_FBX_BLANKING_REG_LCDC_JDI_BXBLANKING_Msk (0xffffUL) /*!< LCDC_JDI_BXBLANKING (Bitfield-Mask: 0xffff)     */
-/* ===============================================  LCDC_JDI_FBY_BLANKING_REG  =============================================== */
-#define LCDC_LCDC_JDI_FBY_BLANKING_REG_LCDC_JDI_FYBLANKING_Pos (16UL) /*!< LCDC_JDI_FYBLANKING (Bit 16)                        */
-#define LCDC_LCDC_JDI_FBY_BLANKING_REG_LCDC_JDI_FYBLANKING_Msk (0xffff0000UL) /*!< LCDC_JDI_FYBLANKING (Bitfield-Mask: 0xffff) */
-#define LCDC_LCDC_JDI_FBY_BLANKING_REG_LCDC_JDI_BYBLANKING_Pos (0UL) /*!< LCDC_JDI_BYBLANKING (Bit 0)                          */
-#define LCDC_LCDC_JDI_FBY_BLANKING_REG_LCDC_JDI_BYBLANKING_Msk (0xffffUL) /*!< LCDC_JDI_BYBLANKING (Bitfield-Mask: 0xffff)     */
-/* ================================================  LCDC_JDI_HCK_WIDTH_REG  ================================================= */
-#define LCDC_LCDC_JDI_HCK_WIDTH_REG_LCDC_JDI_HCK_WIDTH_Pos (0UL)    /*!< LCDC_JDI_HCK_WIDTH (Bit 0)                            */
-#define LCDC_LCDC_JDI_HCK_WIDTH_REG_LCDC_JDI_HCK_WIDTH_Msk (0xffffffffUL) /*!< LCDC_JDI_HCK_WIDTH (Bitfield-Mask: 0xffffffff)  */
-/* ================================================  LCDC_JDI_HST_DELAY_REG  ================================================= */
-#define LCDC_LCDC_JDI_HST_DELAY_REG_LCDC_JDI_HST_DELAY_Pos (0UL)    /*!< LCDC_JDI_HST_DELAY (Bit 0)                            */
-#define LCDC_LCDC_JDI_HST_DELAY_REG_LCDC_JDI_HST_DELAY_Msk (0xffffffffUL) /*!< LCDC_JDI_HST_DELAY (Bitfield-Mask: 0xffffffff)  */
-/* ================================================  LCDC_JDI_HST_WIDTH_REG  ================================================= */
-#define LCDC_LCDC_JDI_HST_WIDTH_REG_LCDC_JDI_HST_WIDTH_Pos (0UL)    /*!< LCDC_JDI_HST_WIDTH (Bit 0)                            */
-#define LCDC_LCDC_JDI_HST_WIDTH_REG_LCDC_JDI_HST_WIDTH_Msk (0xffffffffUL) /*!< LCDC_JDI_HST_WIDTH (Bitfield-Mask: 0xffffffff)  */
-/* ==================================================  LCDC_JDI_RESXY_REG  =================================================== */
-#define LCDC_LCDC_JDI_RESXY_REG_LCDC_JDI_RES_X_Pos (16UL)           /*!< LCDC_JDI_RES_X (Bit 16)                               */
-#define LCDC_LCDC_JDI_RESXY_REG_LCDC_JDI_RES_X_Msk (0xffff0000UL)   /*!< LCDC_JDI_RES_X (Bitfield-Mask: 0xffff)                */
-#define LCDC_LCDC_JDI_RESXY_REG_LCDC_JDI_RES_Y_Pos (0UL)            /*!< LCDC_JDI_RES_Y (Bit 0)                                */
-#define LCDC_LCDC_JDI_RESXY_REG_LCDC_JDI_RES_Y_Msk (0xffffUL)       /*!< LCDC_JDI_RES_Y (Bitfield-Mask: 0xffff)                */
-/* ================================================  LCDC_JDI_VCK_DELAY_REG  ================================================= */
-#define LCDC_LCDC_JDI_VCK_DELAY_REG_LCDC_JDI_VCK_DELAY_Pos (0UL)    /*!< LCDC_JDI_VCK_DELAY (Bit 0)                            */
-#define LCDC_LCDC_JDI_VCK_DELAY_REG_LCDC_JDI_VCK_DELAY_Msk (0xffffffffUL) /*!< LCDC_JDI_VCK_DELAY (Bitfield-Mask: 0xffffffff)  */
-/* ================================================  LCDC_JDI_VST_DELAY_REG  ================================================= */
-#define LCDC_LCDC_JDI_VST_DELAY_REG_LCDC_JDI_VST_DELAY_Pos (0UL)    /*!< LCDC_JDI_VST_DELAY (Bit 0)                            */
-#define LCDC_LCDC_JDI_VST_DELAY_REG_LCDC_JDI_VST_DELAY_Msk (0xffffffffUL) /*!< LCDC_JDI_VST_DELAY (Bitfield-Mask: 0xffffffff)  */
-/* ================================================  LCDC_JDI_VST_WIDTH_REG  ================================================= */
-#define LCDC_LCDC_JDI_VST_WIDTH_REG_LCDC_JDI_VST_WIDTH_Pos (0UL)    /*!< LCDC_JDI_VST_WIDTH (Bit 0)                            */
-#define LCDC_LCDC_JDI_VST_WIDTH_REG_LCDC_JDI_VST_WIDTH_Msk (0xffffffffUL) /*!< LCDC_JDI_VST_WIDTH (Bitfield-Mask: 0xffffffff)  */
-/* ================================================  LCDC_JDI_XRST_WIDTH_REG  ================================================ */
-#define LCDC_LCDC_JDI_XRST_WIDTH_REG_LCDC_JDI_XRST_WIDTH_Pos (0UL)  /*!< LCDC_JDI_XRST_WIDTH (Bit 0)                           */
-#define LCDC_LCDC_JDI_XRST_WIDTH_REG_LCDC_JDI_XRST_WIDTH_Msk (0xffffffffUL) /*!< LCDC_JDI_XRST_WIDTH (Bitfield-Mask: 0xffffffff) */
-/* ===============================================  LCDC_LAYER0_BASEADDR_REG  ================================================ */
-#define LCDC_LCDC_LAYER0_BASEADDR_REG_LCDC_L0_FB_ADDR_Pos (0UL)     /*!< LCDC_L0_FB_ADDR (Bit 0)                               */
-#define LCDC_LCDC_LAYER0_BASEADDR_REG_LCDC_L0_FB_ADDR_Msk (0xffffffffUL) /*!< LCDC_L0_FB_ADDR (Bitfield-Mask: 0xffffffff)      */
-/* =================================================  LCDC_LAYER0_MODE_REG  ================================================== */
-#define LCDC_LCDC_LAYER0_MODE_REG_LCDC_L0_EN_Pos (31UL)             /*!< LCDC_L0_EN (Bit 31)                                   */
-#define LCDC_LCDC_LAYER0_MODE_REG_LCDC_L0_EN_Msk (0x80000000UL)     /*!< LCDC_L0_EN (Bitfield-Mask: 0x01)                      */
-#define LCDC_LCDC_LAYER0_MODE_REG_LCDC_L0_COLOUR_MODE_Pos (0UL)     /*!< LCDC_L0_COLOUR_MODE (Bit 0)                           */
-#define LCDC_LCDC_LAYER0_MODE_REG_LCDC_L0_COLOUR_MODE_Msk (0x1fUL)  /*!< LCDC_L0_COLOUR_MODE (Bitfield-Mask: 0x1f)             */
-/* ================================================  LCDC_LAYER0_OFFSETX_REG  ================================================ */
-#define LCDC_LCDC_LAYER0_OFFSETX_REG_LCDC_L0_DMA_PREFETCH_Pos (16UL) /*!< LCDC_L0_DMA_PREFETCH (Bit 16)                        */
-#define LCDC_LCDC_LAYER0_OFFSETX_REG_LCDC_L0_DMA_PREFETCH_Msk (0xffff0000UL) /*!< LCDC_L0_DMA_PREFETCH (Bitfield-Mask: 0xffff) */
-#define LCDC_LCDC_LAYER0_OFFSETX_REG_LCDC_L0_OFFSETX_Pos (0UL)      /*!< LCDC_L0_OFFSETX (Bit 0)                               */
-#define LCDC_LCDC_LAYER0_OFFSETX_REG_LCDC_L0_OFFSETX_Msk (0xffffUL) /*!< LCDC_L0_OFFSETX (Bitfield-Mask: 0xffff)               */
-/* =================================================  LCDC_LAYER0_RESXY_REG  ================================================= */
-#define LCDC_LCDC_LAYER0_RESXY_REG_LCDC_L0_RES_X_Pos (16UL)         /*!< LCDC_L0_RES_X (Bit 16)                                */
-#define LCDC_LCDC_LAYER0_RESXY_REG_LCDC_L0_RES_X_Msk (0xffff0000UL) /*!< LCDC_L0_RES_X (Bitfield-Mask: 0xffff)                 */
-#define LCDC_LCDC_LAYER0_RESXY_REG_LCDC_L0_RES_Y_Pos (0UL)          /*!< LCDC_L0_RES_Y (Bit 0)                                 */
-#define LCDC_LCDC_LAYER0_RESXY_REG_LCDC_L0_RES_Y_Msk (0xffffUL)     /*!< LCDC_L0_RES_Y (Bitfield-Mask: 0xffff)                 */
-/* ================================================  LCDC_LAYER0_SIZEXY_REG  ================================================= */
-#define LCDC_LCDC_LAYER0_SIZEXY_REG_LCDC_L0_SIZE_X_Pos (16UL)       /*!< LCDC_L0_SIZE_X (Bit 16)                               */
-#define LCDC_LCDC_LAYER0_SIZEXY_REG_LCDC_L0_SIZE_X_Msk (0xffff0000UL) /*!< LCDC_L0_SIZE_X (Bitfield-Mask: 0xffff)              */
-#define LCDC_LCDC_LAYER0_SIZEXY_REG_LCDC_L0_SIZE_Y_Pos (0UL)        /*!< LCDC_L0_SIZE_Y (Bit 0)                                */
-#define LCDC_LCDC_LAYER0_SIZEXY_REG_LCDC_L0_SIZE_Y_Msk (0xffffUL)   /*!< LCDC_L0_SIZE_Y (Bitfield-Mask: 0xffff)                */
-/* ================================================  LCDC_LAYER0_STARTXY_REG  ================================================ */
-#define LCDC_LCDC_LAYER0_STARTXY_REG_LCDC_L0_START_X_Pos (16UL)     /*!< LCDC_L0_START_X (Bit 16)                              */
-#define LCDC_LCDC_LAYER0_STARTXY_REG_LCDC_L0_START_X_Msk (0xffff0000UL) /*!< LCDC_L0_START_X (Bitfield-Mask: 0xffff)           */
-#define LCDC_LCDC_LAYER0_STARTXY_REG_LCDC_L0_START_Y_Pos (0UL)      /*!< LCDC_L0_START_Y (Bit 0)                               */
-#define LCDC_LCDC_LAYER0_STARTXY_REG_LCDC_L0_START_Y_Msk (0xffffUL) /*!< LCDC_L0_START_Y (Bitfield-Mask: 0xffff)               */
-/* ================================================  LCDC_LAYER0_STRIDE_REG  ================================================= */
-#define LCDC_LCDC_LAYER0_STRIDE_REG_LCDC_L0_FIFO_THR_Pos (19UL)     /*!< LCDC_L0_FIFO_THR (Bit 19)                             */
-#define LCDC_LCDC_LAYER0_STRIDE_REG_LCDC_L0_FIFO_THR_Msk (0x180000UL) /*!< LCDC_L0_FIFO_THR (Bitfield-Mask: 0x03)              */
-#define LCDC_LCDC_LAYER0_STRIDE_REG_LCDC_L0_BURST_LEN_Pos (16UL)    /*!< LCDC_L0_BURST_LEN (Bit 16)                            */
-#define LCDC_LCDC_LAYER0_STRIDE_REG_LCDC_L0_BURST_LEN_Msk (0x70000UL) /*!< LCDC_L0_BURST_LEN (Bitfield-Mask: 0x07)             */
-#define LCDC_LCDC_LAYER0_STRIDE_REG_LCDC_L0_STRIDE_Pos (0UL)        /*!< LCDC_L0_STRIDE (Bit 0)                                */
-#define LCDC_LCDC_LAYER0_STRIDE_REG_LCDC_L0_STRIDE_Msk (0xffffUL)   /*!< LCDC_L0_STRIDE (Bitfield-Mask: 0xffff)                */
-/* =====================================================  LCDC_MODE_REG  ===================================================== */
-#define LCDC_LCDC_MODE_REG_LCDC_MODE_EN_Pos (31UL)                  /*!< LCDC_MODE_EN (Bit 31)                                 */
-#define LCDC_LCDC_MODE_REG_LCDC_MODE_EN_Msk (0x80000000UL)          /*!< LCDC_MODE_EN (Bitfield-Mask: 0x01)                    */
-#define LCDC_LCDC_MODE_REG_LCDC_VSYNC_POL_Pos (28UL)                /*!< LCDC_VSYNC_POL (Bit 28)                               */
-#define LCDC_LCDC_MODE_REG_LCDC_VSYNC_POL_Msk (0x10000000UL)        /*!< LCDC_VSYNC_POL (Bitfield-Mask: 0x01)                  */
-#define LCDC_LCDC_MODE_REG_LCDC_HSYNC_POL_Pos (27UL)                /*!< LCDC_HSYNC_POL (Bit 27)                               */
-#define LCDC_LCDC_MODE_REG_LCDC_HSYNC_POL_Msk (0x8000000UL)         /*!< LCDC_HSYNC_POL (Bitfield-Mask: 0x01)                  */
-#define LCDC_LCDC_MODE_REG_LCDC_DE_POL_Pos (26UL)                   /*!< LCDC_DE_POL (Bit 26)                                  */
-#define LCDC_LCDC_MODE_REG_LCDC_DE_POL_Msk (0x4000000UL)            /*!< LCDC_DE_POL (Bitfield-Mask: 0x01)                     */
-#define LCDC_LCDC_MODE_REG_LCDC_VSYNC_SCPL_Pos (23UL)               /*!< LCDC_VSYNC_SCPL (Bit 23)                              */
-#define LCDC_LCDC_MODE_REG_LCDC_VSYNC_SCPL_Msk (0x800000UL)         /*!< LCDC_VSYNC_SCPL (Bitfield-Mask: 0x01)                 */
-#define LCDC_LCDC_MODE_REG_LCDC_PIXCLKOUT_POL_Pos (22UL)            /*!< LCDC_PIXCLKOUT_POL (Bit 22)                           */
-#define LCDC_LCDC_MODE_REG_LCDC_PIXCLKOUT_POL_Msk (0x400000UL)      /*!< LCDC_PIXCLKOUT_POL (Bitfield-Mask: 0x01)              */
-#define LCDC_LCDC_MODE_REG_LCDC_FORCE_BLANK_Pos (19UL)              /*!< LCDC_FORCE_BLANK (Bit 19)                             */
-#define LCDC_LCDC_MODE_REG_LCDC_FORCE_BLANK_Msk (0x80000UL)         /*!< LCDC_FORCE_BLANK (Bitfield-Mask: 0x01)                */
-#define LCDC_LCDC_MODE_REG_LCDC_SFRAME_UPD_Pos (17UL)               /*!< LCDC_SFRAME_UPD (Bit 17)                              */
-#define LCDC_LCDC_MODE_REG_LCDC_SFRAME_UPD_Msk (0x20000UL)          /*!< LCDC_SFRAME_UPD (Bitfield-Mask: 0x01)                 */
-#define LCDC_LCDC_MODE_REG_LCDC_PIXCLKOUT_SEL_Pos (11UL)            /*!< LCDC_PIXCLKOUT_SEL (Bit 11)                           */
-#define LCDC_LCDC_MODE_REG_LCDC_PIXCLKOUT_SEL_Msk (0x800UL)         /*!< LCDC_PIXCLKOUT_SEL (Bitfield-Mask: 0x01)              */
-#define LCDC_LCDC_MODE_REG_LCDC_OUT_MODE_Pos (5UL)                  /*!< LCDC_OUT_MODE (Bit 5)                                 */
-#define LCDC_LCDC_MODE_REG_LCDC_OUT_MODE_Msk (0x1e0UL)              /*!< LCDC_OUT_MODE (Bitfield-Mask: 0x0f)                   */
-#define LCDC_LCDC_MODE_REG_LCDC_MIPI_OFF_Pos (4UL)                  /*!< LCDC_MIPI_OFF (Bit 4)                                 */
-#define LCDC_LCDC_MODE_REG_LCDC_MIPI_OFF_Msk (0x10UL)               /*!< LCDC_MIPI_OFF (Bitfield-Mask: 0x01)                   */
-#define LCDC_LCDC_MODE_REG_LCDC_FORM_OFF_Pos (3UL)                  /*!< LCDC_FORM_OFF (Bit 3)                                 */
-#define LCDC_LCDC_MODE_REG_LCDC_FORM_OFF_Msk (0x8UL)                /*!< LCDC_FORM_OFF (Bitfield-Mask: 0x01)                   */
-#define LCDC_LCDC_MODE_REG_LCDC_DSCAN_Pos (1UL)                     /*!< LCDC_DSCAN (Bit 1)                                    */
-#define LCDC_LCDC_MODE_REG_LCDC_DSCAN_Msk (0x2UL)                   /*!< LCDC_DSCAN (Bitfield-Mask: 0x01)                      */
-#define LCDC_LCDC_MODE_REG_LCDC_TMODE_Pos (0UL)                     /*!< LCDC_TMODE (Bit 0)                                    */
-#define LCDC_LCDC_MODE_REG_LCDC_TMODE_Msk (0x1UL)                   /*!< LCDC_TMODE (Bitfield-Mask: 0x01)                      */
-/* ====================================================  LCDC_RESXY_REG  ===================================================== */
-#define LCDC_LCDC_RESXY_REG_LCDC_RES_X_Pos (16UL)                   /*!< LCDC_RES_X (Bit 16)                                   */
-#define LCDC_LCDC_RESXY_REG_LCDC_RES_X_Msk (0xffff0000UL)           /*!< LCDC_RES_X (Bitfield-Mask: 0xffff)                    */
-#define LCDC_LCDC_RESXY_REG_LCDC_RES_Y_Pos (0UL)                    /*!< LCDC_RES_Y (Bit 0)                                    */
-#define LCDC_LCDC_RESXY_REG_LCDC_RES_Y_Msk (0xffffUL)               /*!< LCDC_RES_Y (Bitfield-Mask: 0xffff)                    */
-/* ====================================================  LCDC_STATUS_REG  ==================================================== */
-#define LCDC_LCDC_STATUS_REG_LCDC_JDI_TIM_SW_RST_Pos (15UL)         /*!< LCDC_JDI_TIM_SW_RST (Bit 15)                          */
-#define LCDC_LCDC_STATUS_REG_LCDC_JDI_TIM_SW_RST_Msk (0x8000UL)     /*!< LCDC_JDI_TIM_SW_RST (Bitfield-Mask: 0x01)             */
-#define LCDC_LCDC_STATUS_REG_LCDC_FRAME_START_Pos (14UL)            /*!< LCDC_FRAME_START (Bit 14)                             */
-#define LCDC_LCDC_STATUS_REG_LCDC_FRAME_START_Msk (0x4000UL)        /*!< LCDC_FRAME_START (Bitfield-Mask: 0x01)                */
-#define LCDC_LCDC_STATUS_REG_LCDC_FRAME_END_Pos (13UL)              /*!< LCDC_FRAME_END (Bit 13)                               */
-#define LCDC_LCDC_STATUS_REG_LCDC_FRAME_END_Msk (0x2000UL)          /*!< LCDC_FRAME_END (Bitfield-Mask: 0x01)                  */
-#define LCDC_LCDC_STATUS_REG_LCDC_DBIB_CMD_PENDING_Pos (12UL)       /*!< LCDC_DBIB_CMD_PENDING (Bit 12)                        */
-#define LCDC_LCDC_STATUS_REG_LCDC_DBIB_CMD_PENDING_Msk (0x1000UL)   /*!< LCDC_DBIB_CMD_PENDING (Bitfield-Mask: 0x01)           */
-#define LCDC_LCDC_STATUS_REG_LCDC_DBIB_CMD_FIFO_FULL_Pos (11UL)     /*!< LCDC_DBIB_CMD_FIFO_FULL (Bit 11)                      */
-#define LCDC_LCDC_STATUS_REG_LCDC_DBIB_CMD_FIFO_FULL_Msk (0x800UL)  /*!< LCDC_DBIB_CMD_FIFO_FULL (Bitfield-Mask: 0x01)         */
-#define LCDC_LCDC_STATUS_REG_LCDC_DBIB_CMD_FIFO_EMPTY_N_Pos (10UL)  /*!< LCDC_DBIB_CMD_FIFO_EMPTY_N (Bit 10)                   */
-#define LCDC_LCDC_STATUS_REG_LCDC_DBIB_CMD_FIFO_EMPTY_N_Msk (0x400UL) /*!< LCDC_DBIB_CMD_FIFO_EMPTY_N (Bitfield-Mask: 0x01)    */
-#define LCDC_LCDC_STATUS_REG_LCDC_DBIB_TE_Pos (8UL)                 /*!< LCDC_DBIB_TE (Bit 8)                                  */
-#define LCDC_LCDC_STATUS_REG_LCDC_DBIB_TE_Msk (0x100UL)             /*!< LCDC_DBIB_TE (Bitfield-Mask: 0x01)                    */
-#define LCDC_LCDC_STATUS_REG_LCDC_STICKY_UNDERFLOW_Pos (7UL)        /*!< LCDC_STICKY_UNDERFLOW (Bit 7)                         */
-#define LCDC_LCDC_STATUS_REG_LCDC_STICKY_UNDERFLOW_Msk (0x80UL)     /*!< LCDC_STICKY_UNDERFLOW (Bitfield-Mask: 0x01)           */
-#define LCDC_LCDC_STATUS_REG_LCDC_UNDERFLOW_Pos (6UL)               /*!< LCDC_UNDERFLOW (Bit 6)                                */
-#define LCDC_LCDC_STATUS_REG_LCDC_UNDERFLOW_Msk (0x40UL)            /*!< LCDC_UNDERFLOW (Bitfield-Mask: 0x01)                  */
-#define LCDC_LCDC_STATUS_REG_LCDC_LAST_ROW_Pos (5UL)                /*!< LCDC_LAST_ROW (Bit 5)                                 */
-#define LCDC_LCDC_STATUS_REG_LCDC_LAST_ROW_Msk (0x20UL)             /*!< LCDC_LAST_ROW (Bitfield-Mask: 0x01)                   */
-#define LCDC_LCDC_STATUS_REG_LCDC_STAT_CSYNC_Pos (4UL)              /*!< LCDC_STAT_CSYNC (Bit 4)                               */
-#define LCDC_LCDC_STATUS_REG_LCDC_STAT_CSYNC_Msk (0x10UL)           /*!< LCDC_STAT_CSYNC (Bitfield-Mask: 0x01)                 */
-#define LCDC_LCDC_STATUS_REG_LCDC_STAT_VSYNC_Pos (3UL)              /*!< LCDC_STAT_VSYNC (Bit 3)                               */
-#define LCDC_LCDC_STATUS_REG_LCDC_STAT_VSYNC_Msk (0x8UL)            /*!< LCDC_STAT_VSYNC (Bitfield-Mask: 0x01)                 */
-#define LCDC_LCDC_STATUS_REG_LCDC_STAT_HSYNC_Pos (2UL)              /*!< LCDC_STAT_HSYNC (Bit 2)                               */
-#define LCDC_LCDC_STATUS_REG_LCDC_STAT_HSYNC_Msk (0x4UL)            /*!< LCDC_STAT_HSYNC (Bitfield-Mask: 0x01)                 */
-#define LCDC_LCDC_STATUS_REG_LCDC_FRAMEGEN_BUSY_Pos (1UL)           /*!< LCDC_FRAMEGEN_BUSY (Bit 1)                            */
-#define LCDC_LCDC_STATUS_REG_LCDC_FRAMEGEN_BUSY_Msk (0x2UL)         /*!< LCDC_FRAMEGEN_BUSY (Bitfield-Mask: 0x01)              */
-#define LCDC_LCDC_STATUS_REG_LCDC_STAT_ACTIVE_Pos (0UL)             /*!< LCDC_STAT_ACTIVE (Bit 0)                              */
-#define LCDC_LCDC_STATUS_REG_LCDC_STAT_ACTIVE_Msk (0x1UL)           /*!< LCDC_STAT_ACTIVE (Bitfield-Mask: 0x01)                */
-
-
-/* =========================================================================================================================== */
-/* ================                                            LRA                                            ================ */
-/* =========================================================================================================================== */
-
-/* ===================================================  LRA_ADC_CTRL1_REG  =================================================== */
-#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_BUSY_Pos (31UL)               /*!< LRA_ADC_BUSY (Bit 31)                                 */
-#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_BUSY_Msk (0x80000000UL)       /*!< LRA_ADC_BUSY (Bitfield-Mask: 0x01)                    */
-#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_OFFSET_Pos (9UL)              /*!< LRA_ADC_OFFSET (Bit 9)                                */
-#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_OFFSET_Msk (0x1fe00UL)        /*!< LRA_ADC_OFFSET (Bitfield-Mask: 0xff)                  */
-#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_TEST_PARAM_Pos (8UL)          /*!< LRA_ADC_TEST_PARAM (Bit 8)                            */
-#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_TEST_PARAM_Msk (0x100UL)      /*!< LRA_ADC_TEST_PARAM (Bitfield-Mask: 0x01)              */
-#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_TEST_IN_SEL_Pos (7UL)         /*!< LRA_ADC_TEST_IN_SEL (Bit 7)                           */
-#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_TEST_IN_SEL_Msk (0x80UL)      /*!< LRA_ADC_TEST_IN_SEL (Bitfield-Mask: 0x01)             */
-#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_FREQ_Pos (3UL)                /*!< LRA_ADC_FREQ (Bit 3)                                  */
-#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_FREQ_Msk (0x78UL)             /*!< LRA_ADC_FREQ (Bitfield-Mask: 0x0f)                    */
-#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_SIGN_Pos (2UL)                /*!< LRA_ADC_SIGN (Bit 2)                                  */
-#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_SIGN_Msk (0x4UL)              /*!< LRA_ADC_SIGN (Bitfield-Mask: 0x01)                    */
-#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_MUTE_Pos (1UL)                /*!< LRA_ADC_MUTE (Bit 1)                                  */
-#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_MUTE_Msk (0x2UL)              /*!< LRA_ADC_MUTE (Bitfield-Mask: 0x01)                    */
-#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_START_Pos (0UL)               /*!< LRA_ADC_START (Bit 0)                                 */
-#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_START_Msk (0x1UL)             /*!< LRA_ADC_START (Bitfield-Mask: 0x01)                   */
-/* ==================================================  LRA_ADC_RESULT_REG  =================================================== */
-#define LRA_LRA_ADC_RESULT_REG_MAN_FLT_IN_Pos (16UL)                /*!< MAN_FLT_IN (Bit 16)                                   */
-#define LRA_LRA_ADC_RESULT_REG_MAN_FLT_IN_Msk (0xffff0000UL)        /*!< MAN_FLT_IN (Bitfield-Mask: 0xffff)                    */
-#define LRA_LRA_ADC_RESULT_REG_GP_ADC_VAL_Pos (0UL)                 /*!< GP_ADC_VAL (Bit 0)                                    */
-#define LRA_LRA_ADC_RESULT_REG_GP_ADC_VAL_Msk (0xffffUL)            /*!< GP_ADC_VAL (Bitfield-Mask: 0xffff)                    */
-/* ====================================================  LRA_BRD_HS_REG  ===================================================== */
-#define LRA_LRA_BRD_HS_REG_TRIM_GAIN_Pos  (11UL)                    /*!< TRIM_GAIN (Bit 11)                                    */
-#define LRA_LRA_BRD_HS_REG_TRIM_GAIN_Msk  (0x7800UL)                /*!< TRIM_GAIN (Bitfield-Mask: 0x0f)                       */
-#define LRA_LRA_BRD_HS_REG_HSGND_TRIM_Pos (8UL)                     /*!< HSGND_TRIM (Bit 8)                                    */
-#define LRA_LRA_BRD_HS_REG_HSGND_TRIM_Msk (0x700UL)                 /*!< HSGND_TRIM (Bitfield-Mask: 0x07)                      */
-#define LRA_LRA_BRD_HS_REG_SCP_HS_TRIM_Pos (4UL)                    /*!< SCP_HS_TRIM (Bit 4)                                   */
-#define LRA_LRA_BRD_HS_REG_SCP_HS_TRIM_Msk (0xf0UL)                 /*!< SCP_HS_TRIM (Bitfield-Mask: 0x0f)                     */
-#define LRA_LRA_BRD_HS_REG_SCP_HS_EN_Pos  (3UL)                     /*!< SCP_HS_EN (Bit 3)                                     */
-#define LRA_LRA_BRD_HS_REG_SCP_HS_EN_Msk  (0x8UL)                   /*!< SCP_HS_EN (Bitfield-Mask: 0x01)                       */
-#define LRA_LRA_BRD_HS_REG_ERC_HS_TRIM_Pos (1UL)                    /*!< ERC_HS_TRIM (Bit 1)                                   */
-#define LRA_LRA_BRD_HS_REG_ERC_HS_TRIM_Msk (0x6UL)                  /*!< ERC_HS_TRIM (Bitfield-Mask: 0x03)                     */
-#define LRA_LRA_BRD_HS_REG_ERC_HS_EN_Pos  (0UL)                     /*!< ERC_HS_EN (Bit 0)                                     */
-#define LRA_LRA_BRD_HS_REG_ERC_HS_EN_Msk  (0x1UL)                   /*!< ERC_HS_EN (Bitfield-Mask: 0x01)                       */
-/* ====================================================  LRA_BRD_LS_REG  ===================================================== */
-#define LRA_LRA_BRD_LS_REG_SCP_LS_TRIM_N_Pos (8UL)                  /*!< SCP_LS_TRIM_N (Bit 8)                                 */
-#define LRA_LRA_BRD_LS_REG_SCP_LS_TRIM_N_Msk (0xf00UL)              /*!< SCP_LS_TRIM_N (Bitfield-Mask: 0x0f)                   */
-#define LRA_LRA_BRD_LS_REG_SCP_LS_TRIM_P_Pos (4UL)                  /*!< SCP_LS_TRIM_P (Bit 4)                                 */
-#define LRA_LRA_BRD_LS_REG_SCP_LS_TRIM_P_Msk (0xf0UL)               /*!< SCP_LS_TRIM_P (Bitfield-Mask: 0x0f)                   */
-#define LRA_LRA_BRD_LS_REG_SCP_LS_EN_Pos  (3UL)                     /*!< SCP_LS_EN (Bit 3)                                     */
-#define LRA_LRA_BRD_LS_REG_SCP_LS_EN_Msk  (0x8UL)                   /*!< SCP_LS_EN (Bitfield-Mask: 0x01)                       */
-#define LRA_LRA_BRD_LS_REG_ERC_LS_TRIM_Pos (1UL)                    /*!< ERC_LS_TRIM (Bit 1)                                   */
-#define LRA_LRA_BRD_LS_REG_ERC_LS_TRIM_Msk (0x6UL)                  /*!< ERC_LS_TRIM (Bitfield-Mask: 0x03)                     */
-#define LRA_LRA_BRD_LS_REG_ERC_LS_EN_Pos  (0UL)                     /*!< ERC_LS_EN (Bit 0)                                     */
-#define LRA_LRA_BRD_LS_REG_ERC_LS_EN_Msk  (0x1UL)                   /*!< ERC_LS_EN (Bitfield-Mask: 0x01)                       */
-/* ===================================================  LRA_BRD_STAT_REG  ==================================================== */
-#define LRA_LRA_BRD_STAT_REG_SCP_HS_OUT_Pos (13UL)                  /*!< SCP_HS_OUT (Bit 13)                                   */
-#define LRA_LRA_BRD_STAT_REG_SCP_HS_OUT_Msk (0x2000UL)              /*!< SCP_HS_OUT (Bitfield-Mask: 0x01)                      */
-#define LRA_LRA_BRD_STAT_REG_SCP_LS_COMP_OUT_N_Pos (12UL)           /*!< SCP_LS_COMP_OUT_N (Bit 12)                            */
-#define LRA_LRA_BRD_STAT_REG_SCP_LS_COMP_OUT_N_Msk (0x1000UL)       /*!< SCP_LS_COMP_OUT_N (Bitfield-Mask: 0x01)               */
-#define LRA_LRA_BRD_STAT_REG_SCP_LS_COMP_OUT_P_Pos (11UL)           /*!< SCP_LS_COMP_OUT_P (Bit 11)                            */
-#define LRA_LRA_BRD_STAT_REG_SCP_LS_COMP_OUT_P_Msk (0x800UL)        /*!< SCP_LS_COMP_OUT_P (Bitfield-Mask: 0x01)               */
-#define LRA_LRA_BRD_STAT_REG_SC_EVENT_LS_Pos (10UL)                 /*!< SC_EVENT_LS (Bit 10)                                  */
-#define LRA_LRA_BRD_STAT_REG_SC_EVENT_LS_Msk (0x400UL)              /*!< SC_EVENT_LS (Bitfield-Mask: 0x01)                     */
-#define LRA_LRA_BRD_STAT_REG_SC_EVENT_HS_Pos (9UL)                  /*!< SC_EVENT_HS (Bit 9)                                   */
-#define LRA_LRA_BRD_STAT_REG_SC_EVENT_HS_Msk (0x200UL)              /*!< SC_EVENT_HS (Bitfield-Mask: 0x01)                     */
-#define LRA_LRA_BRD_STAT_REG_LOOP_STAT_Pos (8UL)                    /*!< LOOP_STAT (Bit 8)                                     */
-#define LRA_LRA_BRD_STAT_REG_LOOP_STAT_Msk (0x100UL)                /*!< LOOP_STAT (Bitfield-Mask: 0x01)                       */
-#define LRA_LRA_BRD_STAT_REG_LSN_ON_Pos   (7UL)                     /*!< LSN_ON (Bit 7)                                        */
-#define LRA_LRA_BRD_STAT_REG_LSN_ON_Msk   (0x80UL)                  /*!< LSN_ON (Bitfield-Mask: 0x01)                          */
-#define LRA_LRA_BRD_STAT_REG_LSP_ON_Pos   (6UL)                     /*!< LSP_ON (Bit 6)                                        */
-#define LRA_LRA_BRD_STAT_REG_LSP_ON_Msk   (0x40UL)                  /*!< LSP_ON (Bitfield-Mask: 0x01)                          */
-#define LRA_LRA_BRD_STAT_REG_HSN_ON_Pos   (5UL)                     /*!< HSN_ON (Bit 5)                                        */
-#define LRA_LRA_BRD_STAT_REG_HSN_ON_Msk   (0x20UL)                  /*!< HSN_ON (Bitfield-Mask: 0x01)                          */
-#define LRA_LRA_BRD_STAT_REG_HSP_ON_Pos   (4UL)                     /*!< HSP_ON (Bit 4)                                        */
-#define LRA_LRA_BRD_STAT_REG_HSP_ON_Msk   (0x10UL)                  /*!< HSP_ON (Bitfield-Mask: 0x01)                          */
-#define LRA_LRA_BRD_STAT_REG_LSN_STAT_Pos (3UL)                     /*!< LSN_STAT (Bit 3)                                      */
-#define LRA_LRA_BRD_STAT_REG_LSN_STAT_Msk (0x8UL)                   /*!< LSN_STAT (Bitfield-Mask: 0x01)                        */
-#define LRA_LRA_BRD_STAT_REG_LSP_STAT_Pos (2UL)                     /*!< LSP_STAT (Bit 2)                                      */
-#define LRA_LRA_BRD_STAT_REG_LSP_STAT_Msk (0x4UL)                   /*!< LSP_STAT (Bitfield-Mask: 0x01)                        */
-#define LRA_LRA_BRD_STAT_REG_HSN_STAT_Pos (1UL)                     /*!< HSN_STAT (Bit 1)                                      */
-#define LRA_LRA_BRD_STAT_REG_HSN_STAT_Msk (0x2UL)                   /*!< HSN_STAT (Bitfield-Mask: 0x01)                        */
-#define LRA_LRA_BRD_STAT_REG_HSP_STAT_Pos (0UL)                     /*!< HSP_STAT (Bit 0)                                      */
-#define LRA_LRA_BRD_STAT_REG_HSP_STAT_Msk (0x1UL)                   /*!< HSP_STAT (Bitfield-Mask: 0x01)                        */
-/* =====================================================  LRA_CTRL1_REG  ===================================================== */
-#define LRA_LRA_CTRL1_REG_SMP_IDX_Pos     (24UL)                    /*!< SMP_IDX (Bit 24)                                      */
-#define LRA_LRA_CTRL1_REG_SMP_IDX_Msk     (0xf000000UL)             /*!< SMP_IDX (Bitfield-Mask: 0x0f)                         */
-#define LRA_LRA_CTRL1_REG_IRQ_SCP_EVENT_EN_Pos (18UL)               /*!< IRQ_SCP_EVENT_EN (Bit 18)                             */
-#define LRA_LRA_CTRL1_REG_IRQ_SCP_EVENT_EN_Msk (0x40000UL)          /*!< IRQ_SCP_EVENT_EN (Bitfield-Mask: 0x01)                */
-#define LRA_LRA_CTRL1_REG_IRQ_ADC_EN_Pos  (17UL)                    /*!< IRQ_ADC_EN (Bit 17)                                   */
-#define LRA_LRA_CTRL1_REG_IRQ_ADC_EN_Msk  (0x20000UL)               /*!< IRQ_ADC_EN (Bitfield-Mask: 0x01)                      */
-#define LRA_LRA_CTRL1_REG_IRQ_CTRL_EN_Pos (16UL)                    /*!< IRQ_CTRL_EN (Bit 16)                                  */
-#define LRA_LRA_CTRL1_REG_IRQ_CTRL_EN_Msk (0x10000UL)               /*!< IRQ_CTRL_EN (Bitfield-Mask: 0x01)                     */
-#define LRA_LRA_CTRL1_REG_IRQ_IDX_Pos     (12UL)                    /*!< IRQ_IDX (Bit 12)                                      */
-#define LRA_LRA_CTRL1_REG_IRQ_IDX_Msk     (0xf000UL)                /*!< IRQ_IDX (Bitfield-Mask: 0x0f)                         */
-#define LRA_LRA_CTRL1_REG_IRQ_DIV_Pos     (8UL)                     /*!< IRQ_DIV (Bit 8)                                       */
-#define LRA_LRA_CTRL1_REG_IRQ_DIV_Msk     (0xf00UL)                 /*!< IRQ_DIV (Bitfield-Mask: 0x0f)                         */
-#define LRA_LRA_CTRL1_REG_SMP_SEL_Pos     (6UL)                     /*!< SMP_SEL (Bit 6)                                       */
-#define LRA_LRA_CTRL1_REG_SMP_SEL_Msk     (0xc0UL)                  /*!< SMP_SEL (Bitfield-Mask: 0x03)                         */
-#define LRA_LRA_CTRL1_REG_PULLDOWN_EN_Pos (5UL)                     /*!< PULLDOWN_EN (Bit 5)                                   */
-#define LRA_LRA_CTRL1_REG_PULLDOWN_EN_Msk (0x20UL)                  /*!< PULLDOWN_EN (Bitfield-Mask: 0x01)                     */
-#define LRA_LRA_CTRL1_REG_LOOP_EN_Pos     (4UL)                     /*!< LOOP_EN (Bit 4)                                       */
-#define LRA_LRA_CTRL1_REG_LOOP_EN_Msk     (0x10UL)                  /*!< LOOP_EN (Bitfield-Mask: 0x01)                         */
-#define LRA_LRA_CTRL1_REG_LDO_EN_Pos      (3UL)                     /*!< LDO_EN (Bit 3)                                        */
-#define LRA_LRA_CTRL1_REG_LDO_EN_Msk      (0x8UL)                   /*!< LDO_EN (Bitfield-Mask: 0x01)                          */
-#define LRA_LRA_CTRL1_REG_ADC_EN_Pos      (2UL)                     /*!< ADC_EN (Bit 2)                                        */
-#define LRA_LRA_CTRL1_REG_ADC_EN_Msk      (0x4UL)                   /*!< ADC_EN (Bitfield-Mask: 0x01)                          */
-#define LRA_LRA_CTRL1_REG_HBRIDGE_EN_Pos  (1UL)                     /*!< HBRIDGE_EN (Bit 1)                                    */
-#define LRA_LRA_CTRL1_REG_HBRIDGE_EN_Msk  (0x2UL)                   /*!< HBRIDGE_EN (Bitfield-Mask: 0x01)                      */
-#define LRA_LRA_CTRL1_REG_LRA_EN_Pos      (0UL)                     /*!< LRA_EN (Bit 0)                                        */
-#define LRA_LRA_CTRL1_REG_LRA_EN_Msk      (0x1UL)                   /*!< LRA_EN (Bitfield-Mask: 0x01)                          */
-/* =====================================================  LRA_CTRL2_REG  ===================================================== */
-#define LRA_LRA_CTRL2_REG_HALF_PERIOD_Pos (16UL)                    /*!< HALF_PERIOD (Bit 16)                                  */
-#define LRA_LRA_CTRL2_REG_HALF_PERIOD_Msk (0xffff0000UL)            /*!< HALF_PERIOD (Bitfield-Mask: 0xffff)                   */
-#define LRA_LRA_CTRL2_REG_AUTO_MODE_Pos   (5UL)                     /*!< AUTO_MODE (Bit 5)                                     */
-#define LRA_LRA_CTRL2_REG_AUTO_MODE_Msk   (0x20UL)                  /*!< AUTO_MODE (Bitfield-Mask: 0x01)                       */
-#define LRA_LRA_CTRL2_REG_SMP_MODE_Pos    (4UL)                     /*!< SMP_MODE (Bit 4)                                      */
-#define LRA_LRA_CTRL2_REG_SMP_MODE_Msk    (0x10UL)                  /*!< SMP_MODE (Bitfield-Mask: 0x01)                        */
-#define LRA_LRA_CTRL2_REG_POLARITY_Pos    (3UL)                     /*!< POLARITY (Bit 3)                                      */
-#define LRA_LRA_CTRL2_REG_POLARITY_Msk    (0x8UL)                   /*!< POLARITY (Bitfield-Mask: 0x01)                        */
-#define LRA_LRA_CTRL2_REG_FLT_IN_SEL_Pos  (2UL)                     /*!< FLT_IN_SEL (Bit 2)                                    */
-#define LRA_LRA_CTRL2_REG_FLT_IN_SEL_Msk  (0x4UL)                   /*!< FLT_IN_SEL (Bitfield-Mask: 0x01)                      */
-#define LRA_LRA_CTRL2_REG_PWM_MODE_Pos    (0UL)                     /*!< PWM_MODE (Bit 0)                                      */
-#define LRA_LRA_CTRL2_REG_PWM_MODE_Msk    (0x3UL)                   /*!< PWM_MODE (Bitfield-Mask: 0x03)                        */
-/* =====================================================  LRA_CTRL3_REG  ===================================================== */
-#define LRA_LRA_CTRL3_REG_VREF_Pos        (16UL)                    /*!< VREF (Bit 16)                                         */
-#define LRA_LRA_CTRL3_REG_VREF_Msk        (0xffff0000UL)            /*!< VREF (Bitfield-Mask: 0xffff)                          */
-#define LRA_LRA_CTRL3_REG_DREF_Pos        (0UL)                     /*!< DREF (Bit 0)                                          */
-#define LRA_LRA_CTRL3_REG_DREF_Msk        (0xffffUL)                /*!< DREF (Bitfield-Mask: 0xffff)                          */
-/* ======================================================  LRA_DFT_REG  ====================================================== */
-#define LRA_LRA_DFT_REG_SPARE_Pos         (29UL)                    /*!< SPARE (Bit 29)                                        */
-#define LRA_LRA_DFT_REG_SPARE_Msk         (0xe0000000UL)            /*!< SPARE (Bitfield-Mask: 0x07)                           */
-#define LRA_LRA_DFT_REG_SWM_SEL_Pos       (28UL)                    /*!< SWM_SEL (Bit 28)                                      */
-#define LRA_LRA_DFT_REG_SWM_SEL_Msk       (0x10000000UL)            /*!< SWM_SEL (Bitfield-Mask: 0x01)                         */
-#define LRA_LRA_DFT_REG_SWM_MAN_Pos       (27UL)                    /*!< SWM_MAN (Bit 27)                                      */
-#define LRA_LRA_DFT_REG_SWM_MAN_Msk       (0x8000000UL)             /*!< SWM_MAN (Bitfield-Mask: 0x01)                         */
-#define LRA_LRA_DFT_REG_PWM_SEL_Pos       (26UL)                    /*!< PWM_SEL (Bit 26)                                      */
-#define LRA_LRA_DFT_REG_PWM_SEL_Msk       (0x4000000UL)             /*!< PWM_SEL (Bitfield-Mask: 0x01)                         */
-#define LRA_LRA_DFT_REG_PWM_MAN_Pos       (25UL)                    /*!< PWM_MAN (Bit 25)                                      */
-#define LRA_LRA_DFT_REG_PWM_MAN_Msk       (0x2000000UL)             /*!< PWM_MAN (Bitfield-Mask: 0x01)                         */
-#define LRA_LRA_DFT_REG_TIMER_TRIM_Pos    (23UL)                    /*!< TIMER_TRIM (Bit 23)                                   */
-#define LRA_LRA_DFT_REG_TIMER_TRIM_Msk    (0x1800000UL)             /*!< TIMER_TRIM (Bitfield-Mask: 0x03)                      */
-#define LRA_LRA_DFT_REG_TIMER_SCALE_TRIM_Pos (21UL)                 /*!< TIMER_SCALE_TRIM (Bit 21)                             */
-#define LRA_LRA_DFT_REG_TIMER_SCALE_TRIM_Msk (0x600000UL)           /*!< TIMER_SCALE_TRIM (Bitfield-Mask: 0x03)                */
-#define LRA_LRA_DFT_REG_DFT_SEL_Pos       (20UL)                    /*!< DFT_SEL (Bit 20)                                      */
-#define LRA_LRA_DFT_REG_DFT_SEL_Msk       (0x100000UL)              /*!< DFT_SEL (Bitfield-Mask: 0x01)                         */
-#define LRA_LRA_DFT_REG_DFT_FORCE_HSPN_Pos (19UL)                   /*!< DFT_FORCE_HSPN (Bit 19)                               */
-#define LRA_LRA_DFT_REG_DFT_FORCE_HSPN_Msk (0x80000UL)              /*!< DFT_FORCE_HSPN (Bitfield-Mask: 0x01)                  */
-#define LRA_LRA_DFT_REG_DFT_EN_TIMER_Pos  (18UL)                    /*!< DFT_EN_TIMER (Bit 18)                                 */
-#define LRA_LRA_DFT_REG_DFT_EN_TIMER_Msk  (0x40000UL)               /*!< DFT_EN_TIMER (Bitfield-Mask: 0x01)                    */
-#define LRA_LRA_DFT_REG_DFT_STALL_Pos     (16UL)                    /*!< DFT_STALL (Bit 16)                                    */
-#define LRA_LRA_DFT_REG_DFT_STALL_Msk     (0x30000UL)               /*!< DFT_STALL (Bitfield-Mask: 0x03)                       */
-#define LRA_LRA_DFT_REG_DFT_CTRL_Pos      (0UL)                     /*!< DFT_CTRL (Bit 0)                                      */
-#define LRA_LRA_DFT_REG_DFT_CTRL_Msk      (0xffffUL)                /*!< DFT_CTRL (Bitfield-Mask: 0xffff)                      */
-/* ===================================================  LRA_FLT_COEF1_REG  =================================================== */
-#define LRA_LRA_FLT_COEF1_REG_FLT_COEF_01_Pos (16UL)                /*!< FLT_COEF_01 (Bit 16)                                  */
-#define LRA_LRA_FLT_COEF1_REG_FLT_COEF_01_Msk (0xffff0000UL)        /*!< FLT_COEF_01 (Bitfield-Mask: 0xffff)                   */
-#define LRA_LRA_FLT_COEF1_REG_FLT_COEF_00_Pos (0UL)                 /*!< FLT_COEF_00 (Bit 0)                                   */
-#define LRA_LRA_FLT_COEF1_REG_FLT_COEF_00_Msk (0xffffUL)            /*!< FLT_COEF_00 (Bitfield-Mask: 0xffff)                   */
-/* ===================================================  LRA_FLT_COEF2_REG  =================================================== */
-#define LRA_LRA_FLT_COEF2_REG_FLT_COEF_10_Pos (16UL)                /*!< FLT_COEF_10 (Bit 16)                                  */
-#define LRA_LRA_FLT_COEF2_REG_FLT_COEF_10_Msk (0xffff0000UL)        /*!< FLT_COEF_10 (Bitfield-Mask: 0xffff)                   */
-#define LRA_LRA_FLT_COEF2_REG_FLT_COEF_02_Pos (0UL)                 /*!< FLT_COEF_02 (Bit 0)                                   */
-#define LRA_LRA_FLT_COEF2_REG_FLT_COEF_02_Msk (0xffffUL)            /*!< FLT_COEF_02 (Bitfield-Mask: 0xffff)                   */
-/* ===================================================  LRA_FLT_COEF3_REG  =================================================== */
-#define LRA_LRA_FLT_COEF3_REG_FLT_COEF_12_Pos (16UL)                /*!< FLT_COEF_12 (Bit 16)                                  */
-#define LRA_LRA_FLT_COEF3_REG_FLT_COEF_12_Msk (0xffff0000UL)        /*!< FLT_COEF_12 (Bitfield-Mask: 0xffff)                   */
-#define LRA_LRA_FLT_COEF3_REG_FLT_COEF_11_Pos (0UL)                 /*!< FLT_COEF_11 (Bit 0)                                   */
-#define LRA_LRA_FLT_COEF3_REG_FLT_COEF_11_Msk (0xffffUL)            /*!< FLT_COEF_11 (Bitfield-Mask: 0xffff)                   */
-/* ===================================================  LRA_FLT_SMP1_REG  ==================================================== */
-#define LRA_LRA_FLT_SMP1_REG_LRA_SMP_2_Pos (16UL)                   /*!< LRA_SMP_2 (Bit 16)                                    */
-#define LRA_LRA_FLT_SMP1_REG_LRA_SMP_2_Msk (0xffff0000UL)           /*!< LRA_SMP_2 (Bitfield-Mask: 0xffff)                     */
-#define LRA_LRA_FLT_SMP1_REG_LRA_SMP_1_Pos (0UL)                    /*!< LRA_SMP_1 (Bit 0)                                     */
-#define LRA_LRA_FLT_SMP1_REG_LRA_SMP_1_Msk (0xffffUL)               /*!< LRA_SMP_1 (Bitfield-Mask: 0xffff)                     */
-/* ===================================================  LRA_FLT_SMP2_REG  ==================================================== */
-#define LRA_LRA_FLT_SMP2_REG_LRA_SMP_4_Pos (16UL)                   /*!< LRA_SMP_4 (Bit 16)                                    */
-#define LRA_LRA_FLT_SMP2_REG_LRA_SMP_4_Msk (0xffff0000UL)           /*!< LRA_SMP_4 (Bitfield-Mask: 0xffff)                     */
-#define LRA_LRA_FLT_SMP2_REG_LRA_SMP_3_Pos (0UL)                    /*!< LRA_SMP_3 (Bit 0)                                     */
-#define LRA_LRA_FLT_SMP2_REG_LRA_SMP_3_Msk (0xffffUL)               /*!< LRA_SMP_3 (Bitfield-Mask: 0xffff)                     */
-/* ===================================================  LRA_FLT_SMP3_REG  ==================================================== */
-#define LRA_LRA_FLT_SMP3_REG_LRA_SMP_6_Pos (16UL)                   /*!< LRA_SMP_6 (Bit 16)                                    */
-#define LRA_LRA_FLT_SMP3_REG_LRA_SMP_6_Msk (0xffff0000UL)           /*!< LRA_SMP_6 (Bitfield-Mask: 0xffff)                     */
-#define LRA_LRA_FLT_SMP3_REG_LRA_SMP_5_Pos (0UL)                    /*!< LRA_SMP_5 (Bit 0)                                     */
-#define LRA_LRA_FLT_SMP3_REG_LRA_SMP_5_Msk (0xffffUL)               /*!< LRA_SMP_5 (Bitfield-Mask: 0xffff)                     */
-/* ===================================================  LRA_FLT_SMP4_REG  ==================================================== */
-#define LRA_LRA_FLT_SMP4_REG_LRA_SMP_8_Pos (16UL)                   /*!< LRA_SMP_8 (Bit 16)                                    */
-#define LRA_LRA_FLT_SMP4_REG_LRA_SMP_8_Msk (0xffff0000UL)           /*!< LRA_SMP_8 (Bitfield-Mask: 0xffff)                     */
-#define LRA_LRA_FLT_SMP4_REG_LRA_SMP_7_Pos (0UL)                    /*!< LRA_SMP_7 (Bit 0)                                     */
-#define LRA_LRA_FLT_SMP4_REG_LRA_SMP_7_Msk (0xffffUL)               /*!< LRA_SMP_7 (Bitfield-Mask: 0xffff)                     */
-/* ===================================================  LRA_FLT_SMP5_REG  ==================================================== */
-#define LRA_LRA_FLT_SMP5_REG_LRA_SMP_10_Pos (16UL)                  /*!< LRA_SMP_10 (Bit 16)                                   */
-#define LRA_LRA_FLT_SMP5_REG_LRA_SMP_10_Msk (0xffff0000UL)          /*!< LRA_SMP_10 (Bitfield-Mask: 0xffff)                    */
-#define LRA_LRA_FLT_SMP5_REG_LRA_SMP_9_Pos (0UL)                    /*!< LRA_SMP_9 (Bit 0)                                     */
-#define LRA_LRA_FLT_SMP5_REG_LRA_SMP_9_Msk (0xffffUL)               /*!< LRA_SMP_9 (Bitfield-Mask: 0xffff)                     */
-/* ===================================================  LRA_FLT_SMP6_REG  ==================================================== */
-#define LRA_LRA_FLT_SMP6_REG_LRA_SMP_12_Pos (16UL)                  /*!< LRA_SMP_12 (Bit 16)                                   */
-#define LRA_LRA_FLT_SMP6_REG_LRA_SMP_12_Msk (0xffff0000UL)          /*!< LRA_SMP_12 (Bitfield-Mask: 0xffff)                    */
-#define LRA_LRA_FLT_SMP6_REG_LRA_SMP_11_Pos (0UL)                   /*!< LRA_SMP_11 (Bit 0)                                    */
-#define LRA_LRA_FLT_SMP6_REG_LRA_SMP_11_Msk (0xffffUL)              /*!< LRA_SMP_11 (Bitfield-Mask: 0xffff)                    */
-/* ===================================================  LRA_FLT_SMP7_REG  ==================================================== */
-#define LRA_LRA_FLT_SMP7_REG_LRA_SMP_14_Pos (16UL)                  /*!< LRA_SMP_14 (Bit 16)                                   */
-#define LRA_LRA_FLT_SMP7_REG_LRA_SMP_14_Msk (0xffff0000UL)          /*!< LRA_SMP_14 (Bitfield-Mask: 0xffff)                    */
-#define LRA_LRA_FLT_SMP7_REG_LRA_SMP_13_Pos (0UL)                   /*!< LRA_SMP_13 (Bit 0)                                    */
-#define LRA_LRA_FLT_SMP7_REG_LRA_SMP_13_Msk (0xffffUL)              /*!< LRA_SMP_13 (Bitfield-Mask: 0xffff)                    */
-/* ===================================================  LRA_FLT_SMP8_REG  ==================================================== */
-#define LRA_LRA_FLT_SMP8_REG_LRA_SMP_16_Pos (16UL)                  /*!< LRA_SMP_16 (Bit 16)                                   */
-#define LRA_LRA_FLT_SMP8_REG_LRA_SMP_16_Msk (0xffff0000UL)          /*!< LRA_SMP_16 (Bitfield-Mask: 0xffff)                    */
-#define LRA_LRA_FLT_SMP8_REG_LRA_SMP_15_Pos (0UL)                   /*!< LRA_SMP_15 (Bit 0)                                    */
-#define LRA_LRA_FLT_SMP8_REG_LRA_SMP_15_Msk (0xffffUL)              /*!< LRA_SMP_15 (Bitfield-Mask: 0xffff)                    */
-/* ======================================================  LRA_LDO_REG  ====================================================== */
-#define LRA_LRA_LDO_REG_LDO_OK_Pos        (31UL)                    /*!< LDO_OK (Bit 31)                                       */
-#define LRA_LRA_LDO_REG_LDO_OK_Msk        (0x80000000UL)            /*!< LDO_OK (Bitfield-Mask: 0x01)                          */
-#define LRA_LRA_LDO_REG_LDO_TST_Pos       (1UL)                     /*!< LDO_TST (Bit 1)                                       */
-#define LRA_LRA_LDO_REG_LDO_TST_Msk       (0x2UL)                   /*!< LDO_TST (Bitfield-Mask: 0x01)                         */
-#define LRA_LRA_LDO_REG_LDO_VREF_HOLD_Pos (0UL)                     /*!< LDO_VREF_HOLD (Bit 0)                                 */
-#define LRA_LRA_LDO_REG_LDO_VREF_HOLD_Msk (0x1UL)                   /*!< LDO_VREF_HOLD (Bitfield-Mask: 0x01)                   */
-
-
-/* =========================================================================================================================== */
-/* ================                                          MEMCTRL                                          ================ */
-/* =========================================================================================================================== */
-
-/* ====================================================  BUSY_RESET_REG  ===================================================== */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_SPARE_Pos (30UL)                /*!< BUSY_SPARE (Bit 30)                                   */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_SPARE_Msk (0xc0000000UL)        /*!< BUSY_SPARE (Bitfield-Mask: 0x03)                      */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_MOTOR_Pos (28UL)                /*!< BUSY_MOTOR (Bit 28)                                   */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_MOTOR_Msk (0x30000000UL)        /*!< BUSY_MOTOR (Bitfield-Mask: 0x03)                      */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER2_Pos (26UL)               /*!< BUSY_TIMER2 (Bit 26)                                  */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER2_Msk (0xc000000UL)        /*!< BUSY_TIMER2 (Bitfield-Mask: 0x03)                     */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER_Pos (24UL)                /*!< BUSY_TIMER (Bit 24)                                   */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER_Msk (0x3000000UL)         /*!< BUSY_TIMER (Bitfield-Mask: 0x03)                      */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_UART3_Pos (22UL)                /*!< BUSY_UART3 (Bit 22)                                   */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_UART3_Msk (0xc00000UL)          /*!< BUSY_UART3 (Bitfield-Mask: 0x03)                      */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_GPADC_Pos (20UL)                /*!< BUSY_GPADC (Bit 20)                                   */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_GPADC_Msk (0x300000UL)          /*!< BUSY_GPADC (Bitfield-Mask: 0x03)                      */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_PDM_Pos (18UL)                  /*!< BUSY_PDM (Bit 18)                                     */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_PDM_Msk (0xc0000UL)             /*!< BUSY_PDM (Bitfield-Mask: 0x03)                        */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_SRC_Pos (16UL)                  /*!< BUSY_SRC (Bit 16)                                     */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_SRC_Msk (0x30000UL)             /*!< BUSY_SRC (Bitfield-Mask: 0x03)                        */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_PCM_Pos (14UL)                  /*!< BUSY_PCM (Bit 14)                                     */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_PCM_Msk (0xc000UL)              /*!< BUSY_PCM (Bitfield-Mask: 0x03)                        */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_SDADC_Pos (12UL)                /*!< BUSY_SDADC (Bit 12)                                   */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_SDADC_Msk (0x3000UL)            /*!< BUSY_SDADC (Bitfield-Mask: 0x03)                      */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_I2C2_Pos (10UL)                 /*!< BUSY_I2C2 (Bit 10)                                    */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_I2C2_Msk (0xc00UL)              /*!< BUSY_I2C2 (Bitfield-Mask: 0x03)                       */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_I2C_Pos (8UL)                   /*!< BUSY_I2C (Bit 8)                                      */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_I2C_Msk (0x300UL)               /*!< BUSY_I2C (Bitfield-Mask: 0x03)                        */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_SPI2_Pos (6UL)                  /*!< BUSY_SPI2 (Bit 6)                                     */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_SPI2_Msk (0xc0UL)               /*!< BUSY_SPI2 (Bitfield-Mask: 0x03)                       */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_SPI_Pos (4UL)                   /*!< BUSY_SPI (Bit 4)                                      */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_SPI_Msk (0x30UL)                /*!< BUSY_SPI (Bitfield-Mask: 0x03)                        */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_UART2_Pos (2UL)                 /*!< BUSY_UART2 (Bit 2)                                    */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_UART2_Msk (0xcUL)               /*!< BUSY_UART2 (Bitfield-Mask: 0x03)                      */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_UART_Pos (0UL)                  /*!< BUSY_UART (Bit 0)                                     */
-#define MEMCTRL_BUSY_RESET_REG_BUSY_UART_Msk (0x3UL)                /*!< BUSY_UART (Bitfield-Mask: 0x03)                       */
-/* =====================================================  BUSY_SET_REG  ====================================================== */
-#define MEMCTRL_BUSY_SET_REG_BUSY_SPARE_Pos (30UL)                  /*!< BUSY_SPARE (Bit 30)                                   */
-#define MEMCTRL_BUSY_SET_REG_BUSY_SPARE_Msk (0xc0000000UL)          /*!< BUSY_SPARE (Bitfield-Mask: 0x03)                      */
-#define MEMCTRL_BUSY_SET_REG_BUSY_MOTOR_Pos (28UL)                  /*!< BUSY_MOTOR (Bit 28)                                   */
-#define MEMCTRL_BUSY_SET_REG_BUSY_MOTOR_Msk (0x30000000UL)          /*!< BUSY_MOTOR (Bitfield-Mask: 0x03)                      */
-#define MEMCTRL_BUSY_SET_REG_BUSY_TIMER2_Pos (26UL)                 /*!< BUSY_TIMER2 (Bit 26)                                  */
-#define MEMCTRL_BUSY_SET_REG_BUSY_TIMER2_Msk (0xc000000UL)          /*!< BUSY_TIMER2 (Bitfield-Mask: 0x03)                     */
-#define MEMCTRL_BUSY_SET_REG_BUSY_TIMER_Pos (24UL)                  /*!< BUSY_TIMER (Bit 24)                                   */
-#define MEMCTRL_BUSY_SET_REG_BUSY_TIMER_Msk (0x3000000UL)           /*!< BUSY_TIMER (Bitfield-Mask: 0x03)                      */
-#define MEMCTRL_BUSY_SET_REG_BUSY_UART3_Pos (22UL)                  /*!< BUSY_UART3 (Bit 22)                                   */
-#define MEMCTRL_BUSY_SET_REG_BUSY_UART3_Msk (0xc00000UL)            /*!< BUSY_UART3 (Bitfield-Mask: 0x03)                      */
-#define MEMCTRL_BUSY_SET_REG_BUSY_GPADC_Pos (20UL)                  /*!< BUSY_GPADC (Bit 20)                                   */
-#define MEMCTRL_BUSY_SET_REG_BUSY_GPADC_Msk (0x300000UL)            /*!< BUSY_GPADC (Bitfield-Mask: 0x03)                      */
-#define MEMCTRL_BUSY_SET_REG_BUSY_PDM_Pos (18UL)                    /*!< BUSY_PDM (Bit 18)                                     */
-#define MEMCTRL_BUSY_SET_REG_BUSY_PDM_Msk (0xc0000UL)               /*!< BUSY_PDM (Bitfield-Mask: 0x03)                        */
-#define MEMCTRL_BUSY_SET_REG_BUSY_SRC_Pos (16UL)                    /*!< BUSY_SRC (Bit 16)                                     */
-#define MEMCTRL_BUSY_SET_REG_BUSY_SRC_Msk (0x30000UL)               /*!< BUSY_SRC (Bitfield-Mask: 0x03)                        */
-#define MEMCTRL_BUSY_SET_REG_BUSY_PCM_Pos (14UL)                    /*!< BUSY_PCM (Bit 14)                                     */
-#define MEMCTRL_BUSY_SET_REG_BUSY_PCM_Msk (0xc000UL)                /*!< BUSY_PCM (Bitfield-Mask: 0x03)                        */
-#define MEMCTRL_BUSY_SET_REG_BUSY_SDADC_Pos (12UL)                  /*!< BUSY_SDADC (Bit 12)                                   */
-#define MEMCTRL_BUSY_SET_REG_BUSY_SDADC_Msk (0x3000UL)              /*!< BUSY_SDADC (Bitfield-Mask: 0x03)                      */
-#define MEMCTRL_BUSY_SET_REG_BUSY_I2C2_Pos (10UL)                   /*!< BUSY_I2C2 (Bit 10)                                    */
-#define MEMCTRL_BUSY_SET_REG_BUSY_I2C2_Msk (0xc00UL)                /*!< BUSY_I2C2 (Bitfield-Mask: 0x03)                       */
-#define MEMCTRL_BUSY_SET_REG_BUSY_I2C_Pos (8UL)                     /*!< BUSY_I2C (Bit 8)                                      */
-#define MEMCTRL_BUSY_SET_REG_BUSY_I2C_Msk (0x300UL)                 /*!< BUSY_I2C (Bitfield-Mask: 0x03)                        */
-#define MEMCTRL_BUSY_SET_REG_BUSY_SPI2_Pos (6UL)                    /*!< BUSY_SPI2 (Bit 6)                                     */
-#define MEMCTRL_BUSY_SET_REG_BUSY_SPI2_Msk (0xc0UL)                 /*!< BUSY_SPI2 (Bitfield-Mask: 0x03)                       */
-#define MEMCTRL_BUSY_SET_REG_BUSY_SPI_Pos (4UL)                     /*!< BUSY_SPI (Bit 4)                                      */
-#define MEMCTRL_BUSY_SET_REG_BUSY_SPI_Msk (0x30UL)                  /*!< BUSY_SPI (Bitfield-Mask: 0x03)                        */
-#define MEMCTRL_BUSY_SET_REG_BUSY_UART2_Pos (2UL)                   /*!< BUSY_UART2 (Bit 2)                                    */
-#define MEMCTRL_BUSY_SET_REG_BUSY_UART2_Msk (0xcUL)                 /*!< BUSY_UART2 (Bitfield-Mask: 0x03)                      */
-#define MEMCTRL_BUSY_SET_REG_BUSY_UART_Pos (0UL)                    /*!< BUSY_UART (Bit 0)                                     */
-#define MEMCTRL_BUSY_SET_REG_BUSY_UART_Msk (0x3UL)                  /*!< BUSY_UART (Bitfield-Mask: 0x03)                       */
-/* =====================================================  BUSY_STAT_REG  ===================================================== */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_SPARE_Pos (30UL)                 /*!< BUSY_SPARE (Bit 30)                                   */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_SPARE_Msk (0xc0000000UL)         /*!< BUSY_SPARE (Bitfield-Mask: 0x03)                      */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_MOTOR_Pos (28UL)                 /*!< BUSY_MOTOR (Bit 28)                                   */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_MOTOR_Msk (0x30000000UL)         /*!< BUSY_MOTOR (Bitfield-Mask: 0x03)                      */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER2_Pos (26UL)                /*!< BUSY_TIMER2 (Bit 26)                                  */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER2_Msk (0xc000000UL)         /*!< BUSY_TIMER2 (Bitfield-Mask: 0x03)                     */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER_Pos (24UL)                 /*!< BUSY_TIMER (Bit 24)                                   */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER_Msk (0x3000000UL)          /*!< BUSY_TIMER (Bitfield-Mask: 0x03)                      */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_UART3_Pos (22UL)                 /*!< BUSY_UART3 (Bit 22)                                   */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_UART3_Msk (0xc00000UL)           /*!< BUSY_UART3 (Bitfield-Mask: 0x03)                      */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_GPADC_Pos (20UL)                 /*!< BUSY_GPADC (Bit 20)                                   */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_GPADC_Msk (0x300000UL)           /*!< BUSY_GPADC (Bitfield-Mask: 0x03)                      */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_PDM_Pos (18UL)                   /*!< BUSY_PDM (Bit 18)                                     */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_PDM_Msk (0xc0000UL)              /*!< BUSY_PDM (Bitfield-Mask: 0x03)                        */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_SRC_Pos (16UL)                   /*!< BUSY_SRC (Bit 16)                                     */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_SRC_Msk (0x30000UL)              /*!< BUSY_SRC (Bitfield-Mask: 0x03)                        */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_PCM_Pos (14UL)                   /*!< BUSY_PCM (Bit 14)                                     */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_PCM_Msk (0xc000UL)               /*!< BUSY_PCM (Bitfield-Mask: 0x03)                        */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_SDADC_Pos (12UL)                 /*!< BUSY_SDADC (Bit 12)                                   */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_SDADC_Msk (0x3000UL)             /*!< BUSY_SDADC (Bitfield-Mask: 0x03)                      */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_I2C2_Pos (10UL)                  /*!< BUSY_I2C2 (Bit 10)                                    */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_I2C2_Msk (0xc00UL)               /*!< BUSY_I2C2 (Bitfield-Mask: 0x03)                       */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_I2C_Pos (8UL)                    /*!< BUSY_I2C (Bit 8)                                      */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_I2C_Msk (0x300UL)                /*!< BUSY_I2C (Bitfield-Mask: 0x03)                        */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_SPI2_Pos (6UL)                   /*!< BUSY_SPI2 (Bit 6)                                     */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_SPI2_Msk (0xc0UL)                /*!< BUSY_SPI2 (Bitfield-Mask: 0x03)                       */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_SPI_Pos (4UL)                    /*!< BUSY_SPI (Bit 4)                                      */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_SPI_Msk (0x30UL)                 /*!< BUSY_SPI (Bitfield-Mask: 0x03)                        */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_UART2_Pos (2UL)                  /*!< BUSY_UART2 (Bit 2)                                    */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_UART2_Msk (0xcUL)                /*!< BUSY_UART2 (Bitfield-Mask: 0x03)                      */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_UART_Pos (0UL)                   /*!< BUSY_UART (Bit 0)                                     */
-#define MEMCTRL_BUSY_STAT_REG_BUSY_UART_Msk (0x3UL)                 /*!< BUSY_UART (Bitfield-Mask: 0x03)                       */
-/* ===================================================  CMI_CODE_BASE_REG  =================================================== */
-#define MEMCTRL_CMI_CODE_BASE_REG_CMI_CODE_BASE_ADDR_Pos (10UL)     /*!< CMI_CODE_BASE_ADDR (Bit 10)                           */
-#define MEMCTRL_CMI_CODE_BASE_REG_CMI_CODE_BASE_ADDR_Msk (0x7fc00UL) /*!< CMI_CODE_BASE_ADDR (Bitfield-Mask: 0x1ff)            */
-/* ===================================================  CMI_DATA_BASE_REG  =================================================== */
-#define MEMCTRL_CMI_DATA_BASE_REG_CMI_DATA_BASE_ADDR_Pos (2UL)      /*!< CMI_DATA_BASE_ADDR (Bit 2)                            */
-#define MEMCTRL_CMI_DATA_BASE_REG_CMI_DATA_BASE_ADDR_Msk (0x7fffcUL) /*!< CMI_DATA_BASE_ADDR (Bitfield-Mask: 0x1ffff)          */
-/* ======================================================  CMI_END_REG  ====================================================== */
-#define MEMCTRL_CMI_END_REG_CMI_END_ADDR_Pos (10UL)                 /*!< CMI_END_ADDR (Bit 10)                                 */
-#define MEMCTRL_CMI_END_REG_CMI_END_ADDR_Msk (0x7fc00UL)            /*!< CMI_END_ADDR (Bitfield-Mask: 0x1ff)                   */
-/* ==================================================  CMI_SHARED_BASE_REG  ================================================== */
-#define MEMCTRL_CMI_SHARED_BASE_REG_CMI_SHARED_BASE_ADDR_Pos (10UL) /*!< CMI_SHARED_BASE_ADDR (Bit 10)                         */
-#define MEMCTRL_CMI_SHARED_BASE_REG_CMI_SHARED_BASE_ADDR_Msk (0x7fc00UL) /*!< CMI_SHARED_BASE_ADDR (Bitfield-Mask: 0x1ff)      */
-/* =====================================================  MEM_PRIO_REG  ====================================================== */
-#define MEMCTRL_MEM_PRIO_REG_AHB_PRIO_Pos (4UL)                     /*!< AHB_PRIO (Bit 4)                                      */
-#define MEMCTRL_MEM_PRIO_REG_AHB_PRIO_Msk (0x30UL)                  /*!< AHB_PRIO (Bitfield-Mask: 0x03)                        */
-#define MEMCTRL_MEM_PRIO_REG_AHB2_PRIO_Pos (2UL)                    /*!< AHB2_PRIO (Bit 2)                                     */
-#define MEMCTRL_MEM_PRIO_REG_AHB2_PRIO_Msk (0xcUL)                  /*!< AHB2_PRIO (Bitfield-Mask: 0x03)                       */
-#define MEMCTRL_MEM_PRIO_REG_SNC_PRIO_Pos (0UL)                     /*!< SNC_PRIO (Bit 0)                                      */
-#define MEMCTRL_MEM_PRIO_REG_SNC_PRIO_Msk (0x3UL)                   /*!< SNC_PRIO (Bitfield-Mask: 0x03)                        */
-/* =====================================================  MEM_STALL_REG  ===================================================== */
-#define MEMCTRL_MEM_STALL_REG_AHB_MAX_STALL_Pos (8UL)               /*!< AHB_MAX_STALL (Bit 8)                                 */
-#define MEMCTRL_MEM_STALL_REG_AHB_MAX_STALL_Msk (0xf00UL)           /*!< AHB_MAX_STALL (Bitfield-Mask: 0x0f)                   */
-#define MEMCTRL_MEM_STALL_REG_AHB2_MAX_STALL_Pos (4UL)              /*!< AHB2_MAX_STALL (Bit 4)                                */
-#define MEMCTRL_MEM_STALL_REG_AHB2_MAX_STALL_Msk (0xf0UL)           /*!< AHB2_MAX_STALL (Bitfield-Mask: 0x0f)                  */
-#define MEMCTRL_MEM_STALL_REG_SNC_MAX_STALL_Pos (0UL)               /*!< SNC_MAX_STALL (Bit 0)                                 */
-#define MEMCTRL_MEM_STALL_REG_SNC_MAX_STALL_Msk (0xfUL)             /*!< SNC_MAX_STALL (Bitfield-Mask: 0x0f)                   */
-/* ====================================================  MEM_STATUS2_REG  ==================================================== */
-#define MEMCTRL_MEM_STATUS2_REG_RAM8_OFF_BUT_ACCESS_Pos (7UL)       /*!< RAM8_OFF_BUT_ACCESS (Bit 7)                           */
-#define MEMCTRL_MEM_STATUS2_REG_RAM8_OFF_BUT_ACCESS_Msk (0x80UL)    /*!< RAM8_OFF_BUT_ACCESS (Bitfield-Mask: 0x01)             */
-#define MEMCTRL_MEM_STATUS2_REG_RAM7_OFF_BUT_ACCESS_Pos (6UL)       /*!< RAM7_OFF_BUT_ACCESS (Bit 6)                           */
-#define MEMCTRL_MEM_STATUS2_REG_RAM7_OFF_BUT_ACCESS_Msk (0x40UL)    /*!< RAM7_OFF_BUT_ACCESS (Bitfield-Mask: 0x01)             */
-#define MEMCTRL_MEM_STATUS2_REG_RAM6_OFF_BUT_ACCESS_Pos (5UL)       /*!< RAM6_OFF_BUT_ACCESS (Bit 5)                           */
-#define MEMCTRL_MEM_STATUS2_REG_RAM6_OFF_BUT_ACCESS_Msk (0x20UL)    /*!< RAM6_OFF_BUT_ACCESS (Bitfield-Mask: 0x01)             */
-#define MEMCTRL_MEM_STATUS2_REG_RAM5_OFF_BUT_ACCESS_Pos (4UL)       /*!< RAM5_OFF_BUT_ACCESS (Bit 4)                           */
-#define MEMCTRL_MEM_STATUS2_REG_RAM5_OFF_BUT_ACCESS_Msk (0x10UL)    /*!< RAM5_OFF_BUT_ACCESS (Bitfield-Mask: 0x01)             */
-#define MEMCTRL_MEM_STATUS2_REG_RAM4_OFF_BUT_ACCESS_Pos (3UL)       /*!< RAM4_OFF_BUT_ACCESS (Bit 3)                           */
-#define MEMCTRL_MEM_STATUS2_REG_RAM4_OFF_BUT_ACCESS_Msk (0x8UL)     /*!< RAM4_OFF_BUT_ACCESS (Bitfield-Mask: 0x01)             */
-#define MEMCTRL_MEM_STATUS2_REG_RAM3_OFF_BUT_ACCESS_Pos (2UL)       /*!< RAM3_OFF_BUT_ACCESS (Bit 2)                           */
-#define MEMCTRL_MEM_STATUS2_REG_RAM3_OFF_BUT_ACCESS_Msk (0x4UL)     /*!< RAM3_OFF_BUT_ACCESS (Bitfield-Mask: 0x01)             */
-#define MEMCTRL_MEM_STATUS2_REG_RAM2_OFF_BUT_ACCESS_Pos (1UL)       /*!< RAM2_OFF_BUT_ACCESS (Bit 1)                           */
-#define MEMCTRL_MEM_STATUS2_REG_RAM2_OFF_BUT_ACCESS_Msk (0x2UL)     /*!< RAM2_OFF_BUT_ACCESS (Bitfield-Mask: 0x01)             */
-#define MEMCTRL_MEM_STATUS2_REG_RAM1_OFF_BUT_ACCESS_Pos (0UL)       /*!< RAM1_OFF_BUT_ACCESS (Bit 0)                           */
-#define MEMCTRL_MEM_STATUS2_REG_RAM1_OFF_BUT_ACCESS_Msk (0x1UL)     /*!< RAM1_OFF_BUT_ACCESS (Bitfield-Mask: 0x01)             */
-/* ====================================================  MEM_STATUS_REG  ===================================================== */
-#define MEMCTRL_MEM_STATUS_REG_CMI_CLEAR_READY_Pos (13UL)           /*!< CMI_CLEAR_READY (Bit 13)                              */
-#define MEMCTRL_MEM_STATUS_REG_CMI_CLEAR_READY_Msk (0x2000UL)       /*!< CMI_CLEAR_READY (Bitfield-Mask: 0x01)                 */
-#define MEMCTRL_MEM_STATUS_REG_CMI_NOT_READY_Pos (12UL)             /*!< CMI_NOT_READY (Bit 12)                                */
-#define MEMCTRL_MEM_STATUS_REG_CMI_NOT_READY_Msk (0x1000UL)         /*!< CMI_NOT_READY (Bitfield-Mask: 0x01)                   */
-#define MEMCTRL_MEM_STATUS_REG_AHB2_WR_BUFF_CNT_Pos (8UL)           /*!< AHB2_WR_BUFF_CNT (Bit 8)                              */
-#define MEMCTRL_MEM_STATUS_REG_AHB2_WR_BUFF_CNT_Msk (0xf00UL)       /*!< AHB2_WR_BUFF_CNT (Bitfield-Mask: 0x0f)                */
-#define MEMCTRL_MEM_STATUS_REG_AHB_WR_BUFF_CNT_Pos (4UL)            /*!< AHB_WR_BUFF_CNT (Bit 4)                               */
-#define MEMCTRL_MEM_STATUS_REG_AHB_WR_BUFF_CNT_Msk (0xf0UL)         /*!< AHB_WR_BUFF_CNT (Bitfield-Mask: 0x0f)                 */
-#define MEMCTRL_MEM_STATUS_REG_AHB2_CLR_WR_BUFF_Pos (3UL)           /*!< AHB2_CLR_WR_BUFF (Bit 3)                              */
-#define MEMCTRL_MEM_STATUS_REG_AHB2_CLR_WR_BUFF_Msk (0x8UL)         /*!< AHB2_CLR_WR_BUFF (Bitfield-Mask: 0x01)                */
-#define MEMCTRL_MEM_STATUS_REG_AHB_CLR_WR_BUFF_Pos (2UL)            /*!< AHB_CLR_WR_BUFF (Bit 2)                               */
-#define MEMCTRL_MEM_STATUS_REG_AHB_CLR_WR_BUFF_Msk (0x4UL)          /*!< AHB_CLR_WR_BUFF (Bitfield-Mask: 0x01)                 */
-#define MEMCTRL_MEM_STATUS_REG_AHB2_WRITE_BUFF_Pos (1UL)            /*!< AHB2_WRITE_BUFF (Bit 1)                               */
-#define MEMCTRL_MEM_STATUS_REG_AHB2_WRITE_BUFF_Msk (0x2UL)          /*!< AHB2_WRITE_BUFF (Bitfield-Mask: 0x01)                 */
-#define MEMCTRL_MEM_STATUS_REG_AHB_WRITE_BUFF_Pos (0UL)             /*!< AHB_WRITE_BUFF (Bit 0)                                */
-#define MEMCTRL_MEM_STATUS_REG_AHB_WRITE_BUFF_Msk (0x1UL)           /*!< AHB_WRITE_BUFF (Bitfield-Mask: 0x01)                  */
-/* =====================================================  SNC_BASE_REG  ====================================================== */
-#define MEMCTRL_SNC_BASE_REG_SNC_BASE_ADDRESS_Pos (2UL)             /*!< SNC_BASE_ADDRESS (Bit 2)                              */
-#define MEMCTRL_SNC_BASE_REG_SNC_BASE_ADDRESS_Msk (0x7fffcUL)       /*!< SNC_BASE_ADDRESS (Bitfield-Mask: 0x1ffff)             */
-
-
-/* =========================================================================================================================== */
-/* ================                                           OTPC                                            ================ */
-/* =========================================================================================================================== */
-
-/* =====================================================  OTPC_MODE_REG  ===================================================== */
-#define OTPC_OTPC_MODE_REG_OTPC_MODE_PRG_SEL_Pos (6UL)              /*!< OTPC_MODE_PRG_SEL (Bit 6)                             */
-#define OTPC_OTPC_MODE_REG_OTPC_MODE_PRG_SEL_Msk (0xc0UL)           /*!< OTPC_MODE_PRG_SEL (Bitfield-Mask: 0x03)               */
-#define OTPC_OTPC_MODE_REG_OTPC_MODE_HT_MARG_EN_Pos (5UL)           /*!< OTPC_MODE_HT_MARG_EN (Bit 5)                          */
-#define OTPC_OTPC_MODE_REG_OTPC_MODE_HT_MARG_EN_Msk (0x20UL)        /*!< OTPC_MODE_HT_MARG_EN (Bitfield-Mask: 0x01)            */
-#define OTPC_OTPC_MODE_REG_OTPC_MODE_USE_TST_ROW_Pos (4UL)          /*!< OTPC_MODE_USE_TST_ROW (Bit 4)                         */
-#define OTPC_OTPC_MODE_REG_OTPC_MODE_USE_TST_ROW_Msk (0x10UL)       /*!< OTPC_MODE_USE_TST_ROW (Bitfield-Mask: 0x01)           */
-#define OTPC_OTPC_MODE_REG_OTPC_MODE_MODE_Pos (0UL)                 /*!< OTPC_MODE_MODE (Bit 0)                                */
-#define OTPC_OTPC_MODE_REG_OTPC_MODE_MODE_Msk (0x7UL)               /*!< OTPC_MODE_MODE (Bitfield-Mask: 0x07)                  */
-/* ====================================================  OTPC_PADDR_REG  ===================================================== */
-#define OTPC_OTPC_PADDR_REG_OTPC_PADDR_Pos (0UL)                    /*!< OTPC_PADDR (Bit 0)                                    */
-#define OTPC_OTPC_PADDR_REG_OTPC_PADDR_Msk (0x3ffUL)                /*!< OTPC_PADDR (Bitfield-Mask: 0x3ff)                     */
-/* ====================================================  OTPC_PWORD_REG  ===================================================== */
-#define OTPC_OTPC_PWORD_REG_OTPC_PWORD_Pos (0UL)                    /*!< OTPC_PWORD (Bit 0)                                    */
-#define OTPC_OTPC_PWORD_REG_OTPC_PWORD_Msk (0xffffffffUL)           /*!< OTPC_PWORD (Bitfield-Mask: 0xffffffff)                */
-/* =====================================================  OTPC_STAT_REG  ===================================================== */
-#define OTPC_OTPC_STAT_REG_OTPC_STAT_MRDY_Pos (2UL)                 /*!< OTPC_STAT_MRDY (Bit 2)                                */
-#define OTPC_OTPC_STAT_REG_OTPC_STAT_MRDY_Msk (0x4UL)               /*!< OTPC_STAT_MRDY (Bitfield-Mask: 0x01)                  */
-#define OTPC_OTPC_STAT_REG_OTPC_STAT_PBUF_EMPTY_Pos (1UL)           /*!< OTPC_STAT_PBUF_EMPTY (Bit 1)                          */
-#define OTPC_OTPC_STAT_REG_OTPC_STAT_PBUF_EMPTY_Msk (0x2UL)         /*!< OTPC_STAT_PBUF_EMPTY (Bitfield-Mask: 0x01)            */
-#define OTPC_OTPC_STAT_REG_OTPC_STAT_PRDY_Pos (0UL)                 /*!< OTPC_STAT_PRDY (Bit 0)                                */
-#define OTPC_OTPC_STAT_REG_OTPC_STAT_PRDY_Msk (0x1UL)               /*!< OTPC_STAT_PRDY (Bitfield-Mask: 0x01)                  */
-/* =====================================================  OTPC_TIM1_REG  ===================================================== */
-#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_CSP_Pos (24UL)            /*!< OTPC_TIM1_US_T_CSP (Bit 24)                           */
-#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_CSP_Msk (0x7f000000UL)    /*!< OTPC_TIM1_US_T_CSP (Bitfield-Mask: 0x7f)              */
-#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_CS_Pos (20UL)             /*!< OTPC_TIM1_US_T_CS (Bit 20)                            */
-#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_CS_Msk (0xf00000UL)       /*!< OTPC_TIM1_US_T_CS (Bitfield-Mask: 0x0f)               */
-#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_PL_Pos (16UL)             /*!< OTPC_TIM1_US_T_PL (Bit 16)                            */
-#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_PL_Msk (0xf0000UL)        /*!< OTPC_TIM1_US_T_PL (Bitfield-Mask: 0x0f)               */
-#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_RD_Pos (12UL)             /*!< OTPC_TIM1_CC_T_RD (Bit 12)                            */
-#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_RD_Msk (0x7000UL)         /*!< OTPC_TIM1_CC_T_RD (Bitfield-Mask: 0x07)               */
-#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_20NS_Pos (8UL)            /*!< OTPC_TIM1_CC_T_20NS (Bit 8)                           */
-#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_20NS_Msk (0x300UL)        /*!< OTPC_TIM1_CC_T_20NS (Bitfield-Mask: 0x03)             */
-#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos (0UL)             /*!< OTPC_TIM1_CC_T_1US (Bit 0)                            */
-#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Msk (0x7fUL)          /*!< OTPC_TIM1_CC_T_1US (Bitfield-Mask: 0x7f)              */
-/* =====================================================  OTPC_TIM2_REG  ===================================================== */
-#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_ADD_CC_EN_Pos (31UL)        /*!< OTPC_TIM2_US_ADD_CC_EN (Bit 31)                       */
-#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_ADD_CC_EN_Msk (0x80000000UL) /*!< OTPC_TIM2_US_ADD_CC_EN (Bitfield-Mask: 0x01)         */
-#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_SAS_Pos (29UL)            /*!< OTPC_TIM2_US_T_SAS (Bit 29)                           */
-#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_SAS_Msk (0x60000000UL)    /*!< OTPC_TIM2_US_T_SAS (Bitfield-Mask: 0x03)              */
-#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PPH_Pos (24UL)            /*!< OTPC_TIM2_US_T_PPH (Bit 24)                           */
-#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PPH_Msk (0x1f000000UL)    /*!< OTPC_TIM2_US_T_PPH (Bitfield-Mask: 0x1f)              */
-#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_VDS_Pos (21UL)            /*!< OTPC_TIM2_US_T_VDS (Bit 21)                           */
-#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_VDS_Msk (0xe00000UL)      /*!< OTPC_TIM2_US_T_VDS (Bitfield-Mask: 0x07)              */
-#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PPS_Pos (16UL)            /*!< OTPC_TIM2_US_T_PPS (Bit 16)                           */
-#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PPS_Msk (0x1f0000UL)      /*!< OTPC_TIM2_US_T_PPS (Bitfield-Mask: 0x1f)              */
-#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PPR_Pos (8UL)             /*!< OTPC_TIM2_US_T_PPR (Bit 8)                            */
-#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PPR_Msk (0x7f00UL)        /*!< OTPC_TIM2_US_T_PPR (Bitfield-Mask: 0x7f)              */
-#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PWI_Pos (5UL)             /*!< OTPC_TIM2_US_T_PWI (Bit 5)                            */
-#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PWI_Msk (0xe0UL)          /*!< OTPC_TIM2_US_T_PWI (Bitfield-Mask: 0x07)              */
-#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PW_Pos (0UL)              /*!< OTPC_TIM2_US_T_PW (Bit 0)                             */
-#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PW_Msk (0x1fUL)           /*!< OTPC_TIM2_US_T_PW (Bitfield-Mask: 0x1f)               */
-
-
-/* =========================================================================================================================== */
-/* ================                                            PDC                                            ================ */
-/* =========================================================================================================================== */
-
-/* ==================================================  PDC_ACKNOWLEDGE_REG  ================================================== */
-#define PDC_PDC_ACKNOWLEDGE_REG_PDC_ACKNOWLEDGE_Pos (0UL)           /*!< PDC_ACKNOWLEDGE (Bit 0)                               */
-#define PDC_PDC_ACKNOWLEDGE_REG_PDC_ACKNOWLEDGE_Msk (0x1fUL)        /*!< PDC_ACKNOWLEDGE (Bitfield-Mask: 0x1f)                 */
-/* =====================================================  PDC_CTRL0_REG  ===================================================== */
-#define PDC_PDC_CTRL0_REG_PDC_MASTER_Pos  (11UL)                    /*!< PDC_MASTER (Bit 11)                                   */
-#define PDC_PDC_CTRL0_REG_PDC_MASTER_Msk  (0x1800UL)                /*!< PDC_MASTER (Bitfield-Mask: 0x03)                      */
-#define PDC_PDC_CTRL0_REG_EN_COM_Pos      (10UL)                    /*!< EN_COM (Bit 10)                                       */
-#define PDC_PDC_CTRL0_REG_EN_COM_Msk      (0x400UL)                 /*!< EN_COM (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL0_REG_EN_PER_Pos      (9UL)                     /*!< EN_PER (Bit 9)                                        */
-#define PDC_PDC_CTRL0_REG_EN_PER_Msk      (0x200UL)                 /*!< EN_PER (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL0_REG_EN_TMR_Pos      (8UL)                     /*!< EN_TMR (Bit 8)                                        */
-#define PDC_PDC_CTRL0_REG_EN_TMR_Msk      (0x100UL)                 /*!< EN_TMR (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL0_REG_EN_XTAL_Pos     (7UL)                     /*!< EN_XTAL (Bit 7)                                       */
-#define PDC_PDC_CTRL0_REG_EN_XTAL_Msk     (0x80UL)                  /*!< EN_XTAL (Bitfield-Mask: 0x01)                         */
-#define PDC_PDC_CTRL0_REG_TRIG_ID_Pos     (2UL)                     /*!< TRIG_ID (Bit 2)                                       */
-#define PDC_PDC_CTRL0_REG_TRIG_ID_Msk     (0x7cUL)                  /*!< TRIG_ID (Bitfield-Mask: 0x1f)                         */
-#define PDC_PDC_CTRL0_REG_TRIG_SELECT_Pos (0UL)                     /*!< TRIG_SELECT (Bit 0)                                   */
-#define PDC_PDC_CTRL0_REG_TRIG_SELECT_Msk (0x3UL)                   /*!< TRIG_SELECT (Bitfield-Mask: 0x03)                     */
-/* ====================================================  PDC_CTRL10_REG  ===================================================== */
-#define PDC_PDC_CTRL10_REG_PDC_MASTER_Pos (11UL)                    /*!< PDC_MASTER (Bit 11)                                   */
-#define PDC_PDC_CTRL10_REG_PDC_MASTER_Msk (0x1800UL)                /*!< PDC_MASTER (Bitfield-Mask: 0x03)                      */
-#define PDC_PDC_CTRL10_REG_EN_COM_Pos     (10UL)                    /*!< EN_COM (Bit 10)                                       */
-#define PDC_PDC_CTRL10_REG_EN_COM_Msk     (0x400UL)                 /*!< EN_COM (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL10_REG_EN_PER_Pos     (9UL)                     /*!< EN_PER (Bit 9)                                        */
-#define PDC_PDC_CTRL10_REG_EN_PER_Msk     (0x200UL)                 /*!< EN_PER (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL10_REG_EN_TMR_Pos     (8UL)                     /*!< EN_TMR (Bit 8)                                        */
-#define PDC_PDC_CTRL10_REG_EN_TMR_Msk     (0x100UL)                 /*!< EN_TMR (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL10_REG_EN_XTAL_Pos    (7UL)                     /*!< EN_XTAL (Bit 7)                                       */
-#define PDC_PDC_CTRL10_REG_EN_XTAL_Msk    (0x80UL)                  /*!< EN_XTAL (Bitfield-Mask: 0x01)                         */
-#define PDC_PDC_CTRL10_REG_TRIG_ID_Pos    (2UL)                     /*!< TRIG_ID (Bit 2)                                       */
-#define PDC_PDC_CTRL10_REG_TRIG_ID_Msk    (0x7cUL)                  /*!< TRIG_ID (Bitfield-Mask: 0x1f)                         */
-#define PDC_PDC_CTRL10_REG_TRIG_SELECT_Pos (0UL)                    /*!< TRIG_SELECT (Bit 0)                                   */
-#define PDC_PDC_CTRL10_REG_TRIG_SELECT_Msk (0x3UL)                  /*!< TRIG_SELECT (Bitfield-Mask: 0x03)                     */
-/* ====================================================  PDC_CTRL11_REG  ===================================================== */
-#define PDC_PDC_CTRL11_REG_PDC_MASTER_Pos (11UL)                    /*!< PDC_MASTER (Bit 11)                                   */
-#define PDC_PDC_CTRL11_REG_PDC_MASTER_Msk (0x1800UL)                /*!< PDC_MASTER (Bitfield-Mask: 0x03)                      */
-#define PDC_PDC_CTRL11_REG_EN_COM_Pos     (10UL)                    /*!< EN_COM (Bit 10)                                       */
-#define PDC_PDC_CTRL11_REG_EN_COM_Msk     (0x400UL)                 /*!< EN_COM (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL11_REG_EN_PER_Pos     (9UL)                     /*!< EN_PER (Bit 9)                                        */
-#define PDC_PDC_CTRL11_REG_EN_PER_Msk     (0x200UL)                 /*!< EN_PER (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL11_REG_EN_TMR_Pos     (8UL)                     /*!< EN_TMR (Bit 8)                                        */
-#define PDC_PDC_CTRL11_REG_EN_TMR_Msk     (0x100UL)                 /*!< EN_TMR (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL11_REG_EN_XTAL_Pos    (7UL)                     /*!< EN_XTAL (Bit 7)                                       */
-#define PDC_PDC_CTRL11_REG_EN_XTAL_Msk    (0x80UL)                  /*!< EN_XTAL (Bitfield-Mask: 0x01)                         */
-#define PDC_PDC_CTRL11_REG_TRIG_ID_Pos    (2UL)                     /*!< TRIG_ID (Bit 2)                                       */
-#define PDC_PDC_CTRL11_REG_TRIG_ID_Msk    (0x7cUL)                  /*!< TRIG_ID (Bitfield-Mask: 0x1f)                         */
-#define PDC_PDC_CTRL11_REG_TRIG_SELECT_Pos (0UL)                    /*!< TRIG_SELECT (Bit 0)                                   */
-#define PDC_PDC_CTRL11_REG_TRIG_SELECT_Msk (0x3UL)                  /*!< TRIG_SELECT (Bitfield-Mask: 0x03)                     */
-/* ====================================================  PDC_CTRL12_REG  ===================================================== */
-#define PDC_PDC_CTRL12_REG_PDC_MASTER_Pos (11UL)                    /*!< PDC_MASTER (Bit 11)                                   */
-#define PDC_PDC_CTRL12_REG_PDC_MASTER_Msk (0x1800UL)                /*!< PDC_MASTER (Bitfield-Mask: 0x03)                      */
-#define PDC_PDC_CTRL12_REG_EN_COM_Pos     (10UL)                    /*!< EN_COM (Bit 10)                                       */
-#define PDC_PDC_CTRL12_REG_EN_COM_Msk     (0x400UL)                 /*!< EN_COM (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL12_REG_EN_PER_Pos     (9UL)                     /*!< EN_PER (Bit 9)                                        */
-#define PDC_PDC_CTRL12_REG_EN_PER_Msk     (0x200UL)                 /*!< EN_PER (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL12_REG_EN_TMR_Pos     (8UL)                     /*!< EN_TMR (Bit 8)                                        */
-#define PDC_PDC_CTRL12_REG_EN_TMR_Msk     (0x100UL)                 /*!< EN_TMR (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL12_REG_EN_XTAL_Pos    (7UL)                     /*!< EN_XTAL (Bit 7)                                       */
-#define PDC_PDC_CTRL12_REG_EN_XTAL_Msk    (0x80UL)                  /*!< EN_XTAL (Bitfield-Mask: 0x01)                         */
-#define PDC_PDC_CTRL12_REG_TRIG_ID_Pos    (2UL)                     /*!< TRIG_ID (Bit 2)                                       */
-#define PDC_PDC_CTRL12_REG_TRIG_ID_Msk    (0x7cUL)                  /*!< TRIG_ID (Bitfield-Mask: 0x1f)                         */
-#define PDC_PDC_CTRL12_REG_TRIG_SELECT_Pos (0UL)                    /*!< TRIG_SELECT (Bit 0)                                   */
-#define PDC_PDC_CTRL12_REG_TRIG_SELECT_Msk (0x3UL)                  /*!< TRIG_SELECT (Bitfield-Mask: 0x03)                     */
-/* ====================================================  PDC_CTRL13_REG  ===================================================== */
-#define PDC_PDC_CTRL13_REG_PDC_MASTER_Pos (11UL)                    /*!< PDC_MASTER (Bit 11)                                   */
-#define PDC_PDC_CTRL13_REG_PDC_MASTER_Msk (0x1800UL)                /*!< PDC_MASTER (Bitfield-Mask: 0x03)                      */
-#define PDC_PDC_CTRL13_REG_EN_COM_Pos     (10UL)                    /*!< EN_COM (Bit 10)                                       */
-#define PDC_PDC_CTRL13_REG_EN_COM_Msk     (0x400UL)                 /*!< EN_COM (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL13_REG_EN_PER_Pos     (9UL)                     /*!< EN_PER (Bit 9)                                        */
-#define PDC_PDC_CTRL13_REG_EN_PER_Msk     (0x200UL)                 /*!< EN_PER (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL13_REG_EN_TMR_Pos     (8UL)                     /*!< EN_TMR (Bit 8)                                        */
-#define PDC_PDC_CTRL13_REG_EN_TMR_Msk     (0x100UL)                 /*!< EN_TMR (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL13_REG_EN_XTAL_Pos    (7UL)                     /*!< EN_XTAL (Bit 7)                                       */
-#define PDC_PDC_CTRL13_REG_EN_XTAL_Msk    (0x80UL)                  /*!< EN_XTAL (Bitfield-Mask: 0x01)                         */
-#define PDC_PDC_CTRL13_REG_TRIG_ID_Pos    (2UL)                     /*!< TRIG_ID (Bit 2)                                       */
-#define PDC_PDC_CTRL13_REG_TRIG_ID_Msk    (0x7cUL)                  /*!< TRIG_ID (Bitfield-Mask: 0x1f)                         */
-#define PDC_PDC_CTRL13_REG_TRIG_SELECT_Pos (0UL)                    /*!< TRIG_SELECT (Bit 0)                                   */
-#define PDC_PDC_CTRL13_REG_TRIG_SELECT_Msk (0x3UL)                  /*!< TRIG_SELECT (Bitfield-Mask: 0x03)                     */
-/* ====================================================  PDC_CTRL14_REG  ===================================================== */
-#define PDC_PDC_CTRL14_REG_PDC_MASTER_Pos (11UL)                    /*!< PDC_MASTER (Bit 11)                                   */
-#define PDC_PDC_CTRL14_REG_PDC_MASTER_Msk (0x1800UL)                /*!< PDC_MASTER (Bitfield-Mask: 0x03)                      */
-#define PDC_PDC_CTRL14_REG_EN_COM_Pos     (10UL)                    /*!< EN_COM (Bit 10)                                       */
-#define PDC_PDC_CTRL14_REG_EN_COM_Msk     (0x400UL)                 /*!< EN_COM (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL14_REG_EN_PER_Pos     (9UL)                     /*!< EN_PER (Bit 9)                                        */
-#define PDC_PDC_CTRL14_REG_EN_PER_Msk     (0x200UL)                 /*!< EN_PER (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL14_REG_EN_TMR_Pos     (8UL)                     /*!< EN_TMR (Bit 8)                                        */
-#define PDC_PDC_CTRL14_REG_EN_TMR_Msk     (0x100UL)                 /*!< EN_TMR (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL14_REG_EN_XTAL_Pos    (7UL)                     /*!< EN_XTAL (Bit 7)                                       */
-#define PDC_PDC_CTRL14_REG_EN_XTAL_Msk    (0x80UL)                  /*!< EN_XTAL (Bitfield-Mask: 0x01)                         */
-#define PDC_PDC_CTRL14_REG_TRIG_ID_Pos    (2UL)                     /*!< TRIG_ID (Bit 2)                                       */
-#define PDC_PDC_CTRL14_REG_TRIG_ID_Msk    (0x7cUL)                  /*!< TRIG_ID (Bitfield-Mask: 0x1f)                         */
-#define PDC_PDC_CTRL14_REG_TRIG_SELECT_Pos (0UL)                    /*!< TRIG_SELECT (Bit 0)                                   */
-#define PDC_PDC_CTRL14_REG_TRIG_SELECT_Msk (0x3UL)                  /*!< TRIG_SELECT (Bitfield-Mask: 0x03)                     */
-/* ====================================================  PDC_CTRL15_REG  ===================================================== */
-#define PDC_PDC_CTRL15_REG_PDC_MASTER_Pos (11UL)                    /*!< PDC_MASTER (Bit 11)                                   */
-#define PDC_PDC_CTRL15_REG_PDC_MASTER_Msk (0x1800UL)                /*!< PDC_MASTER (Bitfield-Mask: 0x03)                      */
-#define PDC_PDC_CTRL15_REG_EN_COM_Pos     (10UL)                    /*!< EN_COM (Bit 10)                                       */
-#define PDC_PDC_CTRL15_REG_EN_COM_Msk     (0x400UL)                 /*!< EN_COM (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL15_REG_EN_PER_Pos     (9UL)                     /*!< EN_PER (Bit 9)                                        */
-#define PDC_PDC_CTRL15_REG_EN_PER_Msk     (0x200UL)                 /*!< EN_PER (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL15_REG_EN_TMR_Pos     (8UL)                     /*!< EN_TMR (Bit 8)                                        */
-#define PDC_PDC_CTRL15_REG_EN_TMR_Msk     (0x100UL)                 /*!< EN_TMR (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL15_REG_EN_XTAL_Pos    (7UL)                     /*!< EN_XTAL (Bit 7)                                       */
-#define PDC_PDC_CTRL15_REG_EN_XTAL_Msk    (0x80UL)                  /*!< EN_XTAL (Bitfield-Mask: 0x01)                         */
-#define PDC_PDC_CTRL15_REG_TRIG_ID_Pos    (2UL)                     /*!< TRIG_ID (Bit 2)                                       */
-#define PDC_PDC_CTRL15_REG_TRIG_ID_Msk    (0x7cUL)                  /*!< TRIG_ID (Bitfield-Mask: 0x1f)                         */
-#define PDC_PDC_CTRL15_REG_TRIG_SELECT_Pos (0UL)                    /*!< TRIG_SELECT (Bit 0)                                   */
-#define PDC_PDC_CTRL15_REG_TRIG_SELECT_Msk (0x3UL)                  /*!< TRIG_SELECT (Bitfield-Mask: 0x03)                     */
-/* =====================================================  PDC_CTRL1_REG  ===================================================== */
-#define PDC_PDC_CTRL1_REG_PDC_MASTER_Pos  (11UL)                    /*!< PDC_MASTER (Bit 11)                                   */
-#define PDC_PDC_CTRL1_REG_PDC_MASTER_Msk  (0x1800UL)                /*!< PDC_MASTER (Bitfield-Mask: 0x03)                      */
-#define PDC_PDC_CTRL1_REG_EN_COM_Pos      (10UL)                    /*!< EN_COM (Bit 10)                                       */
-#define PDC_PDC_CTRL1_REG_EN_COM_Msk      (0x400UL)                 /*!< EN_COM (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL1_REG_EN_PER_Pos      (9UL)                     /*!< EN_PER (Bit 9)                                        */
-#define PDC_PDC_CTRL1_REG_EN_PER_Msk      (0x200UL)                 /*!< EN_PER (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL1_REG_EN_TMR_Pos      (8UL)                     /*!< EN_TMR (Bit 8)                                        */
-#define PDC_PDC_CTRL1_REG_EN_TMR_Msk      (0x100UL)                 /*!< EN_TMR (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL1_REG_EN_XTAL_Pos     (7UL)                     /*!< EN_XTAL (Bit 7)                                       */
-#define PDC_PDC_CTRL1_REG_EN_XTAL_Msk     (0x80UL)                  /*!< EN_XTAL (Bitfield-Mask: 0x01)                         */
-#define PDC_PDC_CTRL1_REG_TRIG_ID_Pos     (2UL)                     /*!< TRIG_ID (Bit 2)                                       */
-#define PDC_PDC_CTRL1_REG_TRIG_ID_Msk     (0x7cUL)                  /*!< TRIG_ID (Bitfield-Mask: 0x1f)                         */
-#define PDC_PDC_CTRL1_REG_TRIG_SELECT_Pos (0UL)                     /*!< TRIG_SELECT (Bit 0)                                   */
-#define PDC_PDC_CTRL1_REG_TRIG_SELECT_Msk (0x3UL)                   /*!< TRIG_SELECT (Bitfield-Mask: 0x03)                     */
-/* =====================================================  PDC_CTRL2_REG  ===================================================== */
-#define PDC_PDC_CTRL2_REG_PDC_MASTER_Pos  (11UL)                    /*!< PDC_MASTER (Bit 11)                                   */
-#define PDC_PDC_CTRL2_REG_PDC_MASTER_Msk  (0x1800UL)                /*!< PDC_MASTER (Bitfield-Mask: 0x03)                      */
-#define PDC_PDC_CTRL2_REG_EN_COM_Pos      (10UL)                    /*!< EN_COM (Bit 10)                                       */
-#define PDC_PDC_CTRL2_REG_EN_COM_Msk      (0x400UL)                 /*!< EN_COM (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL2_REG_EN_PER_Pos      (9UL)                     /*!< EN_PER (Bit 9)                                        */
-#define PDC_PDC_CTRL2_REG_EN_PER_Msk      (0x200UL)                 /*!< EN_PER (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL2_REG_EN_TMR_Pos      (8UL)                     /*!< EN_TMR (Bit 8)                                        */
-#define PDC_PDC_CTRL2_REG_EN_TMR_Msk      (0x100UL)                 /*!< EN_TMR (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL2_REG_EN_XTAL_Pos     (7UL)                     /*!< EN_XTAL (Bit 7)                                       */
-#define PDC_PDC_CTRL2_REG_EN_XTAL_Msk     (0x80UL)                  /*!< EN_XTAL (Bitfield-Mask: 0x01)                         */
-#define PDC_PDC_CTRL2_REG_TRIG_ID_Pos     (2UL)                     /*!< TRIG_ID (Bit 2)                                       */
-#define PDC_PDC_CTRL2_REG_TRIG_ID_Msk     (0x7cUL)                  /*!< TRIG_ID (Bitfield-Mask: 0x1f)                         */
-#define PDC_PDC_CTRL2_REG_TRIG_SELECT_Pos (0UL)                     /*!< TRIG_SELECT (Bit 0)                                   */
-#define PDC_PDC_CTRL2_REG_TRIG_SELECT_Msk (0x3UL)                   /*!< TRIG_SELECT (Bitfield-Mask: 0x03)                     */
-/* =====================================================  PDC_CTRL3_REG  ===================================================== */
-#define PDC_PDC_CTRL3_REG_PDC_MASTER_Pos  (11UL)                    /*!< PDC_MASTER (Bit 11)                                   */
-#define PDC_PDC_CTRL3_REG_PDC_MASTER_Msk  (0x1800UL)                /*!< PDC_MASTER (Bitfield-Mask: 0x03)                      */
-#define PDC_PDC_CTRL3_REG_EN_COM_Pos      (10UL)                    /*!< EN_COM (Bit 10)                                       */
-#define PDC_PDC_CTRL3_REG_EN_COM_Msk      (0x400UL)                 /*!< EN_COM (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL3_REG_EN_PER_Pos      (9UL)                     /*!< EN_PER (Bit 9)                                        */
-#define PDC_PDC_CTRL3_REG_EN_PER_Msk      (0x200UL)                 /*!< EN_PER (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL3_REG_EN_TMR_Pos      (8UL)                     /*!< EN_TMR (Bit 8)                                        */
-#define PDC_PDC_CTRL3_REG_EN_TMR_Msk      (0x100UL)                 /*!< EN_TMR (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL3_REG_EN_XTAL_Pos     (7UL)                     /*!< EN_XTAL (Bit 7)                                       */
-#define PDC_PDC_CTRL3_REG_EN_XTAL_Msk     (0x80UL)                  /*!< EN_XTAL (Bitfield-Mask: 0x01)                         */
-#define PDC_PDC_CTRL3_REG_TRIG_ID_Pos     (2UL)                     /*!< TRIG_ID (Bit 2)                                       */
-#define PDC_PDC_CTRL3_REG_TRIG_ID_Msk     (0x7cUL)                  /*!< TRIG_ID (Bitfield-Mask: 0x1f)                         */
-#define PDC_PDC_CTRL3_REG_TRIG_SELECT_Pos (0UL)                     /*!< TRIG_SELECT (Bit 0)                                   */
-#define PDC_PDC_CTRL3_REG_TRIG_SELECT_Msk (0x3UL)                   /*!< TRIG_SELECT (Bitfield-Mask: 0x03)                     */
-/* =====================================================  PDC_CTRL4_REG  ===================================================== */
-#define PDC_PDC_CTRL4_REG_PDC_MASTER_Pos  (11UL)                    /*!< PDC_MASTER (Bit 11)                                   */
-#define PDC_PDC_CTRL4_REG_PDC_MASTER_Msk  (0x1800UL)                /*!< PDC_MASTER (Bitfield-Mask: 0x03)                      */
-#define PDC_PDC_CTRL4_REG_EN_COM_Pos      (10UL)                    /*!< EN_COM (Bit 10)                                       */
-#define PDC_PDC_CTRL4_REG_EN_COM_Msk      (0x400UL)                 /*!< EN_COM (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL4_REG_EN_PER_Pos      (9UL)                     /*!< EN_PER (Bit 9)                                        */
-#define PDC_PDC_CTRL4_REG_EN_PER_Msk      (0x200UL)                 /*!< EN_PER (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL4_REG_EN_TMR_Pos      (8UL)                     /*!< EN_TMR (Bit 8)                                        */
-#define PDC_PDC_CTRL4_REG_EN_TMR_Msk      (0x100UL)                 /*!< EN_TMR (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL4_REG_EN_XTAL_Pos     (7UL)                     /*!< EN_XTAL (Bit 7)                                       */
-#define PDC_PDC_CTRL4_REG_EN_XTAL_Msk     (0x80UL)                  /*!< EN_XTAL (Bitfield-Mask: 0x01)                         */
-#define PDC_PDC_CTRL4_REG_TRIG_ID_Pos     (2UL)                     /*!< TRIG_ID (Bit 2)                                       */
-#define PDC_PDC_CTRL4_REG_TRIG_ID_Msk     (0x7cUL)                  /*!< TRIG_ID (Bitfield-Mask: 0x1f)                         */
-#define PDC_PDC_CTRL4_REG_TRIG_SELECT_Pos (0UL)                     /*!< TRIG_SELECT (Bit 0)                                   */
-#define PDC_PDC_CTRL4_REG_TRIG_SELECT_Msk (0x3UL)                   /*!< TRIG_SELECT (Bitfield-Mask: 0x03)                     */
-/* =====================================================  PDC_CTRL5_REG  ===================================================== */
-#define PDC_PDC_CTRL5_REG_PDC_MASTER_Pos  (11UL)                    /*!< PDC_MASTER (Bit 11)                                   */
-#define PDC_PDC_CTRL5_REG_PDC_MASTER_Msk  (0x1800UL)                /*!< PDC_MASTER (Bitfield-Mask: 0x03)                      */
-#define PDC_PDC_CTRL5_REG_EN_COM_Pos      (10UL)                    /*!< EN_COM (Bit 10)                                       */
-#define PDC_PDC_CTRL5_REG_EN_COM_Msk      (0x400UL)                 /*!< EN_COM (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL5_REG_EN_PER_Pos      (9UL)                     /*!< EN_PER (Bit 9)                                        */
-#define PDC_PDC_CTRL5_REG_EN_PER_Msk      (0x200UL)                 /*!< EN_PER (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL5_REG_EN_TMR_Pos      (8UL)                     /*!< EN_TMR (Bit 8)                                        */
-#define PDC_PDC_CTRL5_REG_EN_TMR_Msk      (0x100UL)                 /*!< EN_TMR (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL5_REG_EN_XTAL_Pos     (7UL)                     /*!< EN_XTAL (Bit 7)                                       */
-#define PDC_PDC_CTRL5_REG_EN_XTAL_Msk     (0x80UL)                  /*!< EN_XTAL (Bitfield-Mask: 0x01)                         */
-#define PDC_PDC_CTRL5_REG_TRIG_ID_Pos     (2UL)                     /*!< TRIG_ID (Bit 2)                                       */
-#define PDC_PDC_CTRL5_REG_TRIG_ID_Msk     (0x7cUL)                  /*!< TRIG_ID (Bitfield-Mask: 0x1f)                         */
-#define PDC_PDC_CTRL5_REG_TRIG_SELECT_Pos (0UL)                     /*!< TRIG_SELECT (Bit 0)                                   */
-#define PDC_PDC_CTRL5_REG_TRIG_SELECT_Msk (0x3UL)                   /*!< TRIG_SELECT (Bitfield-Mask: 0x03)                     */
-/* =====================================================  PDC_CTRL6_REG  ===================================================== */
-#define PDC_PDC_CTRL6_REG_PDC_MASTER_Pos  (11UL)                    /*!< PDC_MASTER (Bit 11)                                   */
-#define PDC_PDC_CTRL6_REG_PDC_MASTER_Msk  (0x1800UL)                /*!< PDC_MASTER (Bitfield-Mask: 0x03)                      */
-#define PDC_PDC_CTRL6_REG_EN_COM_Pos      (10UL)                    /*!< EN_COM (Bit 10)                                       */
-#define PDC_PDC_CTRL6_REG_EN_COM_Msk      (0x400UL)                 /*!< EN_COM (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL6_REG_EN_PER_Pos      (9UL)                     /*!< EN_PER (Bit 9)                                        */
-#define PDC_PDC_CTRL6_REG_EN_PER_Msk      (0x200UL)                 /*!< EN_PER (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL6_REG_EN_TMR_Pos      (8UL)                     /*!< EN_TMR (Bit 8)                                        */
-#define PDC_PDC_CTRL6_REG_EN_TMR_Msk      (0x100UL)                 /*!< EN_TMR (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL6_REG_EN_XTAL_Pos     (7UL)                     /*!< EN_XTAL (Bit 7)                                       */
-#define PDC_PDC_CTRL6_REG_EN_XTAL_Msk     (0x80UL)                  /*!< EN_XTAL (Bitfield-Mask: 0x01)                         */
-#define PDC_PDC_CTRL6_REG_TRIG_ID_Pos     (2UL)                     /*!< TRIG_ID (Bit 2)                                       */
-#define PDC_PDC_CTRL6_REG_TRIG_ID_Msk     (0x7cUL)                  /*!< TRIG_ID (Bitfield-Mask: 0x1f)                         */
-#define PDC_PDC_CTRL6_REG_TRIG_SELECT_Pos (0UL)                     /*!< TRIG_SELECT (Bit 0)                                   */
-#define PDC_PDC_CTRL6_REG_TRIG_SELECT_Msk (0x3UL)                   /*!< TRIG_SELECT (Bitfield-Mask: 0x03)                     */
-/* =====================================================  PDC_CTRL7_REG  ===================================================== */
-#define PDC_PDC_CTRL7_REG_PDC_MASTER_Pos  (11UL)                    /*!< PDC_MASTER (Bit 11)                                   */
-#define PDC_PDC_CTRL7_REG_PDC_MASTER_Msk  (0x1800UL)                /*!< PDC_MASTER (Bitfield-Mask: 0x03)                      */
-#define PDC_PDC_CTRL7_REG_EN_COM_Pos      (10UL)                    /*!< EN_COM (Bit 10)                                       */
-#define PDC_PDC_CTRL7_REG_EN_COM_Msk      (0x400UL)                 /*!< EN_COM (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL7_REG_EN_PER_Pos      (9UL)                     /*!< EN_PER (Bit 9)                                        */
-#define PDC_PDC_CTRL7_REG_EN_PER_Msk      (0x200UL)                 /*!< EN_PER (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL7_REG_EN_TMR_Pos      (8UL)                     /*!< EN_TMR (Bit 8)                                        */
-#define PDC_PDC_CTRL7_REG_EN_TMR_Msk      (0x100UL)                 /*!< EN_TMR (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL7_REG_EN_XTAL_Pos     (7UL)                     /*!< EN_XTAL (Bit 7)                                       */
-#define PDC_PDC_CTRL7_REG_EN_XTAL_Msk     (0x80UL)                  /*!< EN_XTAL (Bitfield-Mask: 0x01)                         */
-#define PDC_PDC_CTRL7_REG_TRIG_ID_Pos     (2UL)                     /*!< TRIG_ID (Bit 2)                                       */
-#define PDC_PDC_CTRL7_REG_TRIG_ID_Msk     (0x7cUL)                  /*!< TRIG_ID (Bitfield-Mask: 0x1f)                         */
-#define PDC_PDC_CTRL7_REG_TRIG_SELECT_Pos (0UL)                     /*!< TRIG_SELECT (Bit 0)                                   */
-#define PDC_PDC_CTRL7_REG_TRIG_SELECT_Msk (0x3UL)                   /*!< TRIG_SELECT (Bitfield-Mask: 0x03)                     */
-/* =====================================================  PDC_CTRL8_REG  ===================================================== */
-#define PDC_PDC_CTRL8_REG_PDC_MASTER_Pos  (11UL)                    /*!< PDC_MASTER (Bit 11)                                   */
-#define PDC_PDC_CTRL8_REG_PDC_MASTER_Msk  (0x1800UL)                /*!< PDC_MASTER (Bitfield-Mask: 0x03)                      */
-#define PDC_PDC_CTRL8_REG_EN_COM_Pos      (10UL)                    /*!< EN_COM (Bit 10)                                       */
-#define PDC_PDC_CTRL8_REG_EN_COM_Msk      (0x400UL)                 /*!< EN_COM (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL8_REG_EN_PER_Pos      (9UL)                     /*!< EN_PER (Bit 9)                                        */
-#define PDC_PDC_CTRL8_REG_EN_PER_Msk      (0x200UL)                 /*!< EN_PER (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL8_REG_EN_TMR_Pos      (8UL)                     /*!< EN_TMR (Bit 8)                                        */
-#define PDC_PDC_CTRL8_REG_EN_TMR_Msk      (0x100UL)                 /*!< EN_TMR (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL8_REG_EN_XTAL_Pos     (7UL)                     /*!< EN_XTAL (Bit 7)                                       */
-#define PDC_PDC_CTRL8_REG_EN_XTAL_Msk     (0x80UL)                  /*!< EN_XTAL (Bitfield-Mask: 0x01)                         */
-#define PDC_PDC_CTRL8_REG_TRIG_ID_Pos     (2UL)                     /*!< TRIG_ID (Bit 2)                                       */
-#define PDC_PDC_CTRL8_REG_TRIG_ID_Msk     (0x7cUL)                  /*!< TRIG_ID (Bitfield-Mask: 0x1f)                         */
-#define PDC_PDC_CTRL8_REG_TRIG_SELECT_Pos (0UL)                     /*!< TRIG_SELECT (Bit 0)                                   */
-#define PDC_PDC_CTRL8_REG_TRIG_SELECT_Msk (0x3UL)                   /*!< TRIG_SELECT (Bitfield-Mask: 0x03)                     */
-/* =====================================================  PDC_CTRL9_REG  ===================================================== */
-#define PDC_PDC_CTRL9_REG_PDC_MASTER_Pos  (11UL)                    /*!< PDC_MASTER (Bit 11)                                   */
-#define PDC_PDC_CTRL9_REG_PDC_MASTER_Msk  (0x1800UL)                /*!< PDC_MASTER (Bitfield-Mask: 0x03)                      */
-#define PDC_PDC_CTRL9_REG_EN_COM_Pos      (10UL)                    /*!< EN_COM (Bit 10)                                       */
-#define PDC_PDC_CTRL9_REG_EN_COM_Msk      (0x400UL)                 /*!< EN_COM (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL9_REG_EN_PER_Pos      (9UL)                     /*!< EN_PER (Bit 9)                                        */
-#define PDC_PDC_CTRL9_REG_EN_PER_Msk      (0x200UL)                 /*!< EN_PER (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL9_REG_EN_TMR_Pos      (8UL)                     /*!< EN_TMR (Bit 8)                                        */
-#define PDC_PDC_CTRL9_REG_EN_TMR_Msk      (0x100UL)                 /*!< EN_TMR (Bitfield-Mask: 0x01)                          */
-#define PDC_PDC_CTRL9_REG_EN_XTAL_Pos     (7UL)                     /*!< EN_XTAL (Bit 7)                                       */
-#define PDC_PDC_CTRL9_REG_EN_XTAL_Msk     (0x80UL)                  /*!< EN_XTAL (Bitfield-Mask: 0x01)                         */
-#define PDC_PDC_CTRL9_REG_TRIG_ID_Pos     (2UL)                     /*!< TRIG_ID (Bit 2)                                       */
-#define PDC_PDC_CTRL9_REG_TRIG_ID_Msk     (0x7cUL)                  /*!< TRIG_ID (Bitfield-Mask: 0x1f)                         */
-#define PDC_PDC_CTRL9_REG_TRIG_SELECT_Pos (0UL)                     /*!< TRIG_SELECT (Bit 0)                                   */
-#define PDC_PDC_CTRL9_REG_TRIG_SELECT_Msk (0x3UL)                   /*!< TRIG_SELECT (Bitfield-Mask: 0x03)                     */
-/* =================================================  PDC_PENDING_CM33_REG  ================================================== */
-#define PDC_PDC_PENDING_CM33_REG_PDC_PENDING_Pos (0UL)              /*!< PDC_PENDING (Bit 0)                                   */
-#define PDC_PDC_PENDING_CM33_REG_PDC_PENDING_Msk (0xffffUL)         /*!< PDC_PENDING (Bitfield-Mask: 0xffff)                   */
-/* =================================================  PDC_PENDING_CMAC_REG  ================================================== */
-#define PDC_PDC_PENDING_CMAC_REG_PDC_PENDING_Pos (0UL)              /*!< PDC_PENDING (Bit 0)                                   */
-#define PDC_PDC_PENDING_CMAC_REG_PDC_PENDING_Msk (0xffffUL)         /*!< PDC_PENDING (Bitfield-Mask: 0xffff)                   */
-/* ====================================================  PDC_PENDING_REG  ==================================================== */
-#define PDC_PDC_PENDING_REG_PDC_PENDING_Pos (0UL)                   /*!< PDC_PENDING (Bit 0)                                   */
-#define PDC_PDC_PENDING_REG_PDC_PENDING_Msk (0xffffUL)              /*!< PDC_PENDING (Bitfield-Mask: 0xffff)                   */
-/* ==================================================  PDC_PENDING_SNC_REG  ================================================== */
-#define PDC_PDC_PENDING_SNC_REG_PDC_PENDING_Pos (0UL)               /*!< PDC_PENDING (Bit 0)                                   */
-#define PDC_PDC_PENDING_SNC_REG_PDC_PENDING_Msk (0xffffUL)          /*!< PDC_PENDING (Bitfield-Mask: 0xffff)                   */
-/* ==================================================  PDC_SET_PENDING_REG  ================================================== */
-#define PDC_PDC_SET_PENDING_REG_PDC_SET_PENDING_Pos (0UL)           /*!< PDC_SET_PENDING (Bit 0)                               */
-#define PDC_PDC_SET_PENDING_REG_PDC_SET_PENDING_Msk (0x1fUL)        /*!< PDC_SET_PENDING (Bitfield-Mask: 0x1f)                 */
-
-
-/* =========================================================================================================================== */
-/* ================                                          PWMLED                                           ================ */
-/* =========================================================================================================================== */
-
-/* ====================================================  PWMLED_CTRL_REG  ==================================================== */
-#define PWMLED_PWMLED_CTRL_REG_LED2_LOAD_SEL_Pos (11UL)             /*!< LED2_LOAD_SEL (Bit 11)                                */
-#define PWMLED_PWMLED_CTRL_REG_LED2_LOAD_SEL_Msk (0x3800UL)         /*!< LED2_LOAD_SEL (Bitfield-Mask: 0x07)                   */
-#define PWMLED_PWMLED_CTRL_REG_LED1_LOAD_SEL_Pos (8UL)              /*!< LED1_LOAD_SEL (Bit 8)                                 */
-#define PWMLED_PWMLED_CTRL_REG_LED1_LOAD_SEL_Msk (0x700UL)          /*!< LED1_LOAD_SEL (Bitfield-Mask: 0x07)                   */
-#define PWMLED_PWMLED_CTRL_REG_LED2_EN_Pos (7UL)                    /*!< LED2_EN (Bit 7)                                       */
-#define PWMLED_PWMLED_CTRL_REG_LED2_EN_Msk (0x80UL)                 /*!< LED2_EN (Bitfield-Mask: 0x01)                         */
-#define PWMLED_PWMLED_CTRL_REG_LED1_EN_Pos (6UL)                    /*!< LED1_EN (Bit 6)                                       */
-#define PWMLED_PWMLED_CTRL_REG_LED1_EN_Msk (0x40UL)                 /*!< LED1_EN (Bitfield-Mask: 0x01)                         */
-#define PWMLED_PWMLED_CTRL_REG_LED_TRIM_Pos (2UL)                   /*!< LED_TRIM (Bit 2)                                      */
-#define PWMLED_PWMLED_CTRL_REG_LED_TRIM_Msk (0x3cUL)                /*!< LED_TRIM (Bitfield-Mask: 0x0f)                        */
-#define PWMLED_PWMLED_CTRL_REG_SW_PAUSE_EN_Pos (1UL)                /*!< SW_PAUSE_EN (Bit 1)                                   */
-#define PWMLED_PWMLED_CTRL_REG_SW_PAUSE_EN_Msk (0x2UL)              /*!< SW_PAUSE_EN (Bitfield-Mask: 0x01)                     */
-#define PWMLED_PWMLED_CTRL_REG_PWM_ENABLE_Pos (0UL)                 /*!< PWM_ENABLE (Bit 0)                                    */
-#define PWMLED_PWMLED_CTRL_REG_PWM_ENABLE_Msk (0x1UL)               /*!< PWM_ENABLE (Bitfield-Mask: 0x01)                      */
-/* ==============================================  PWMLED_DUTY_CYCLE_LED1_REG  =============================================== */
-#define PWMLED_PWMLED_DUTY_CYCLE_LED1_REG_LED1_PWM_START_CYCLE_Pos (8UL) /*!< LED1_PWM_START_CYCLE (Bit 8)                     */
-#define PWMLED_PWMLED_DUTY_CYCLE_LED1_REG_LED1_PWM_START_CYCLE_Msk (0xff00UL) /*!< LED1_PWM_START_CYCLE (Bitfield-Mask: 0xff)  */
-#define PWMLED_PWMLED_DUTY_CYCLE_LED1_REG_LED1_PWM_END_CYCLE_Pos (0UL) /*!< LED1_PWM_END_CYCLE (Bit 0)                         */
-#define PWMLED_PWMLED_DUTY_CYCLE_LED1_REG_LED1_PWM_END_CYCLE_Msk (0xffUL) /*!< LED1_PWM_END_CYCLE (Bitfield-Mask: 0xff)        */
-/* ==============================================  PWMLED_DUTY_CYCLE_LED2_REG  =============================================== */
-#define PWMLED_PWMLED_DUTY_CYCLE_LED2_REG_LED2_PWM_START_CYCLE_Pos (8UL) /*!< LED2_PWM_START_CYCLE (Bit 8)                     */
-#define PWMLED_PWMLED_DUTY_CYCLE_LED2_REG_LED2_PWM_START_CYCLE_Msk (0xff00UL) /*!< LED2_PWM_START_CYCLE (Bitfield-Mask: 0xff)  */
-#define PWMLED_PWMLED_DUTY_CYCLE_LED2_REG_LED2_PWM_END_CYCLE_Pos (0UL) /*!< LED2_PWM_END_CYCLE (Bit 0)                         */
-#define PWMLED_PWMLED_DUTY_CYCLE_LED2_REG_LED2_PWM_END_CYCLE_Msk (0xffUL) /*!< LED2_PWM_END_CYCLE (Bitfield-Mask: 0xff)        */
-/* =================================================  PWMLED_FREQUENCY_REG  ================================================== */
-#define PWMLED_PWMLED_FREQUENCY_REG_LED_PWM_FREQUENCY_Pos (0UL)     /*!< LED_PWM_FREQUENCY (Bit 0)                             */
-#define PWMLED_PWMLED_FREQUENCY_REG_LED_PWM_FREQUENCY_Msk (0xffUL)  /*!< LED_PWM_FREQUENCY (Bitfield-Mask: 0xff)               */
-
-
-/* =========================================================================================================================== */
-/* ================                                           QSPIC                                           ================ */
-/* =========================================================================================================================== */
-
-/* ==================================================  QSPIC_BURSTBRK_REG  =================================================== */
-#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_SEC_HF_DS_Pos (20UL)         /*!< QSPIC_SEC_HF_DS (Bit 20)                              */
-#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_SEC_HF_DS_Msk (0x100000UL)   /*!< QSPIC_SEC_HF_DS (Bitfield-Mask: 0x01)                 */
-#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_TX_MD_Pos (18UL)         /*!< QSPIC_BRK_TX_MD (Bit 18)                              */
-#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_TX_MD_Msk (0xc0000UL)    /*!< QSPIC_BRK_TX_MD (Bitfield-Mask: 0x03)                 */
-#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_SZ_Pos (17UL)            /*!< QSPIC_BRK_SZ (Bit 17)                                 */
-#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_SZ_Msk (0x20000UL)       /*!< QSPIC_BRK_SZ (Bitfield-Mask: 0x01)                    */
-#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_EN_Pos (16UL)            /*!< QSPIC_BRK_EN (Bit 16)                                 */
-#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_EN_Msk (0x10000UL)       /*!< QSPIC_BRK_EN (Bitfield-Mask: 0x01)                    */
-#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_WRD_Pos (0UL)            /*!< QSPIC_BRK_WRD (Bit 0)                                 */
-#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_WRD_Msk (0xffffUL)       /*!< QSPIC_BRK_WRD (Bitfield-Mask: 0xffff)                 */
-/* ==================================================  QSPIC_BURSTCMDA_REG  ================================================== */
-#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Pos (30UL)        /*!< QSPIC_DMY_TX_MD (Bit 30)                              */
-#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Msk (0xc0000000UL) /*!< QSPIC_DMY_TX_MD (Bitfield-Mask: 0x03)                */
-#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Pos (28UL)        /*!< QSPIC_EXT_TX_MD (Bit 28)                              */
-#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Msk (0x30000000UL) /*!< QSPIC_EXT_TX_MD (Bitfield-Mask: 0x03)                */
-#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Pos (26UL)        /*!< QSPIC_ADR_TX_MD (Bit 26)                              */
-#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Msk (0xc000000UL) /*!< QSPIC_ADR_TX_MD (Bitfield-Mask: 0x03)                 */
-#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_TX_MD_Pos (24UL)       /*!< QSPIC_INST_TX_MD (Bit 24)                             */
-#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_TX_MD_Msk (0x3000000UL) /*!< QSPIC_INST_TX_MD (Bitfield-Mask: 0x03)               */
-#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_BYTE_Pos (16UL)         /*!< QSPIC_EXT_BYTE (Bit 16)                               */
-#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_BYTE_Msk (0xff0000UL)   /*!< QSPIC_EXT_BYTE (Bitfield-Mask: 0xff)                  */
-#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_WB_Pos (8UL)           /*!< QSPIC_INST_WB (Bit 8)                                 */
-#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_WB_Msk (0xff00UL)      /*!< QSPIC_INST_WB (Bitfield-Mask: 0xff)                   */
-#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_Pos (0UL)              /*!< QSPIC_INST (Bit 0)                                    */
-#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_Msk (0xffUL)           /*!< QSPIC_INST (Bitfield-Mask: 0xff)                      */
-/* ==================================================  QSPIC_BURSTCMDB_REG  ================================================== */
-#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_FORCE_Pos (15UL)        /*!< QSPIC_DMY_FORCE (Bit 15)                              */
-#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_FORCE_Msk (0x8000UL)    /*!< QSPIC_DMY_FORCE (Bitfield-Mask: 0x01)                 */
-#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Pos (12UL)      /*!< QSPIC_CS_HIGH_MIN (Bit 12)                            */
-#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Msk (0x7000UL)  /*!< QSPIC_CS_HIGH_MIN (Bitfield-Mask: 0x07)               */
-#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Pos (10UL)        /*!< QSPIC_WRAP_SIZE (Bit 10)                              */
-#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Msk (0xc00UL)     /*!< QSPIC_WRAP_SIZE (Bitfield-Mask: 0x03)                 */
-#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_LEN_Pos (8UL)          /*!< QSPIC_WRAP_LEN (Bit 8)                                */
-#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_LEN_Msk (0x300UL)      /*!< QSPIC_WRAP_LEN (Bitfield-Mask: 0x03)                  */
-#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_MD_Pos (7UL)           /*!< QSPIC_WRAP_MD (Bit 7)                                 */
-#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_MD_Msk (0x80UL)        /*!< QSPIC_WRAP_MD (Bitfield-Mask: 0x01)                   */
-#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_INST_MD_Pos (6UL)           /*!< QSPIC_INST_MD (Bit 6)                                 */
-#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_INST_MD_Msk (0x40UL)        /*!< QSPIC_INST_MD (Bitfield-Mask: 0x01)                   */
-#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_NUM_Pos (4UL)           /*!< QSPIC_DMY_NUM (Bit 4)                                 */
-#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_NUM_Msk (0x30UL)        /*!< QSPIC_DMY_NUM (Bitfield-Mask: 0x03)                   */
-#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Pos (3UL)         /*!< QSPIC_EXT_HF_DS (Bit 3)                               */
-#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Msk (0x8UL)       /*!< QSPIC_EXT_HF_DS (Bitfield-Mask: 0x01)                 */
-#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Pos (2UL)       /*!< QSPIC_EXT_BYTE_EN (Bit 2)                             */
-#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Msk (0x4UL)     /*!< QSPIC_EXT_BYTE_EN (Bitfield-Mask: 0x01)               */
-#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Pos (0UL)         /*!< QSPIC_DAT_RX_MD (Bit 0)                               */
-#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Msk (0x3UL)       /*!< QSPIC_DAT_RX_MD (Bitfield-Mask: 0x03)                 */
-/* ==================================================  QSPIC_CHCKERASE_REG  ================================================== */
-#define QSPIC_QSPIC_CHCKERASE_REG_QSPIC_CHCKERASE_Pos (0UL)         /*!< QSPIC_CHCKERASE (Bit 0)                               */
-#define QSPIC_QSPIC_CHCKERASE_REG_QSPIC_CHCKERASE_Msk (0xffffffffUL) /*!< QSPIC_CHCKERASE (Bitfield-Mask: 0xffffffff)          */
-/* ===================================================  QSPIC_CTRLBUS_REG  =================================================== */
-#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Pos (4UL)              /*!< QSPIC_DIS_CS (Bit 4)                                  */
-#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Msk (0x10UL)           /*!< QSPIC_DIS_CS (Bitfield-Mask: 0x01)                    */
-#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Pos (3UL)               /*!< QSPIC_EN_CS (Bit 3)                                   */
-#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Msk (0x8UL)             /*!< QSPIC_EN_CS (Bitfield-Mask: 0x01)                     */
-#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_QUAD_Pos (2UL)            /*!< QSPIC_SET_QUAD (Bit 2)                                */
-#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_QUAD_Msk (0x4UL)          /*!< QSPIC_SET_QUAD (Bitfield-Mask: 0x01)                  */
-#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_DUAL_Pos (1UL)            /*!< QSPIC_SET_DUAL (Bit 1)                                */
-#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_DUAL_Msk (0x2UL)          /*!< QSPIC_SET_DUAL (Bitfield-Mask: 0x01)                  */
-#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_SINGLE_Pos (0UL)          /*!< QSPIC_SET_SINGLE (Bit 0)                              */
-#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_SINGLE_Msk (0x1UL)        /*!< QSPIC_SET_SINGLE (Bitfield-Mask: 0x01)                */
-/* ==================================================  QSPIC_CTRLMODE_REG  =================================================== */
-#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_USE_32BA_Pos (13UL)          /*!< QSPIC_USE_32BA (Bit 13)                               */
-#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_USE_32BA_Msk (0x2000UL)      /*!< QSPIC_USE_32BA (Bitfield-Mask: 0x01)                  */
-#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_BUF_LIM_EN_Pos (12UL)        /*!< QSPIC_BUF_LIM_EN (Bit 12)                             */
-#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_BUF_LIM_EN_Msk (0x1000UL)    /*!< QSPIC_BUF_LIM_EN (Bitfield-Mask: 0x01)                */
-#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Pos (9UL)            /*!< QSPIC_PCLK_MD (Bit 9)                                 */
-#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Msk (0xe00UL)        /*!< QSPIC_PCLK_MD (Bitfield-Mask: 0x07)                   */
-#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RPIPE_EN_Pos (8UL)           /*!< QSPIC_RPIPE_EN (Bit 8)                                */
-#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RPIPE_EN_Msk (0x100UL)       /*!< QSPIC_RPIPE_EN (Bitfield-Mask: 0x01)                  */
-#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RXD_NEG_Pos (7UL)            /*!< QSPIC_RXD_NEG (Bit 7)                                 */
-#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RXD_NEG_Msk (0x80UL)         /*!< QSPIC_RXD_NEG (Bitfield-Mask: 0x01)                   */
-#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_HRDY_MD_Pos (6UL)            /*!< QSPIC_HRDY_MD (Bit 6)                                 */
-#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_HRDY_MD_Msk (0x40UL)         /*!< QSPIC_HRDY_MD (Bitfield-Mask: 0x01)                   */
-#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_DAT_Pos (5UL)            /*!< QSPIC_IO3_DAT (Bit 5)                                 */
-#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_DAT_Msk (0x20UL)         /*!< QSPIC_IO3_DAT (Bitfield-Mask: 0x01)                   */
-#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_DAT_Pos (4UL)            /*!< QSPIC_IO2_DAT (Bit 4)                                 */
-#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_DAT_Msk (0x10UL)         /*!< QSPIC_IO2_DAT (Bitfield-Mask: 0x01)                   */
-#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_OEN_Pos (3UL)            /*!< QSPIC_IO3_OEN (Bit 3)                                 */
-#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_OEN_Msk (0x8UL)          /*!< QSPIC_IO3_OEN (Bitfield-Mask: 0x01)                   */
-#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Pos (2UL)            /*!< QSPIC_IO2_OEN (Bit 2)                                 */
-#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Msk (0x4UL)          /*!< QSPIC_IO2_OEN (Bitfield-Mask: 0x01)                   */
-#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_MD_Pos (1UL)             /*!< QSPIC_CLK_MD (Bit 1)                                  */
-#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_MD_Msk (0x2UL)           /*!< QSPIC_CLK_MD (Bitfield-Mask: 0x01)                    */
-#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Pos (0UL)            /*!< QSPIC_AUTO_MD (Bit 0)                                 */
-#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Msk (0x1UL)          /*!< QSPIC_AUTO_MD (Bitfield-Mask: 0x01)                   */
-/* ==================================================  QSPIC_CTR_CTRL_REG  =================================================== */
-#define QSPIC_QSPIC_CTR_CTRL_REG_QSPIC_CTR_EN_Pos (0UL)             /*!< QSPIC_CTR_EN (Bit 0)                                  */
-#define QSPIC_QSPIC_CTR_CTRL_REG_QSPIC_CTR_EN_Msk (0x1UL)           /*!< QSPIC_CTR_EN (Bitfield-Mask: 0x01)                    */
-/* ==================================================  QSPIC_CTR_EADDR_REG  ================================================== */
-#define QSPIC_QSPIC_CTR_EADDR_REG_QSPIC_CTR_EADDR_Pos (10UL)        /*!< QSPIC_CTR_EADDR (Bit 10)                              */
-#define QSPIC_QSPIC_CTR_EADDR_REG_QSPIC_CTR_EADDR_Msk (0xfffffc00UL) /*!< QSPIC_CTR_EADDR (Bitfield-Mask: 0x3fffff)            */
-/* =================================================  QSPIC_CTR_KEY_0_3_REG  ================================================= */
-#define QSPIC_QSPIC_CTR_KEY_0_3_REG_QSPIC_CTR_KEY_0_3_Pos (0UL)     /*!< QSPIC_CTR_KEY_0_3 (Bit 0)                             */
-#define QSPIC_QSPIC_CTR_KEY_0_3_REG_QSPIC_CTR_KEY_0_3_Msk (0xffffffffUL) /*!< QSPIC_CTR_KEY_0_3 (Bitfield-Mask: 0xffffffff)    */
-/* ================================================  QSPIC_CTR_KEY_12_15_REG  ================================================ */
-#define QSPIC_QSPIC_CTR_KEY_12_15_REG_QSPIC_CTR_KEY_12_15_Pos (0UL) /*!< QSPIC_CTR_KEY_12_15 (Bit 0)                           */
-#define QSPIC_QSPIC_CTR_KEY_12_15_REG_QSPIC_CTR_KEY_12_15_Msk (0xffffffffUL) /*!< QSPIC_CTR_KEY_12_15 (Bitfield-Mask: 0xffffffff) */
-/* ================================================  QSPIC_CTR_KEY_16_19_REG  ================================================ */
-#define QSPIC_QSPIC_CTR_KEY_16_19_REG_QSPIC_CTR_KEY_16_19_Pos (0UL) /*!< QSPIC_CTR_KEY_16_19 (Bit 0)                           */
-#define QSPIC_QSPIC_CTR_KEY_16_19_REG_QSPIC_CTR_KEY_16_19_Msk (0xffffffffUL) /*!< QSPIC_CTR_KEY_16_19 (Bitfield-Mask: 0xffffffff) */
-/* ================================================  QSPIC_CTR_KEY_20_23_REG  ================================================ */
-#define QSPIC_QSPIC_CTR_KEY_20_23_REG_QSPIC_CTR_KEY_20_23_Pos (0UL) /*!< QSPIC_CTR_KEY_20_23 (Bit 0)                           */
-#define QSPIC_QSPIC_CTR_KEY_20_23_REG_QSPIC_CTR_KEY_20_23_Msk (0xffffffffUL) /*!< QSPIC_CTR_KEY_20_23 (Bitfield-Mask: 0xffffffff) */
-/* ================================================  QSPIC_CTR_KEY_24_27_REG  ================================================ */
-#define QSPIC_QSPIC_CTR_KEY_24_27_REG_QSPIC_CTR_KEY_24_27_Pos (0UL) /*!< QSPIC_CTR_KEY_24_27 (Bit 0)                           */
-#define QSPIC_QSPIC_CTR_KEY_24_27_REG_QSPIC_CTR_KEY_24_27_Msk (0xffffffffUL) /*!< QSPIC_CTR_KEY_24_27 (Bitfield-Mask: 0xffffffff) */
-/* ================================================  QSPIC_CTR_KEY_28_31_REG  ================================================ */
-#define QSPIC_QSPIC_CTR_KEY_28_31_REG_QSPIC_CTR_KEY_28_31_Pos (0UL) /*!< QSPIC_CTR_KEY_28_31 (Bit 0)                           */
-#define QSPIC_QSPIC_CTR_KEY_28_31_REG_QSPIC_CTR_KEY_28_31_Msk (0xffffffffUL) /*!< QSPIC_CTR_KEY_28_31 (Bitfield-Mask: 0xffffffff) */
-/* =================================================  QSPIC_CTR_KEY_4_7_REG  ================================================= */
-#define QSPIC_QSPIC_CTR_KEY_4_7_REG_QSPIC_CTR_KEY_4_7_Pos (0UL)     /*!< QSPIC_CTR_KEY_4_7 (Bit 0)                             */
-#define QSPIC_QSPIC_CTR_KEY_4_7_REG_QSPIC_CTR_KEY_4_7_Msk (0xffffffffUL) /*!< QSPIC_CTR_KEY_4_7 (Bitfield-Mask: 0xffffffff)    */
-/* ================================================  QSPIC_CTR_KEY_8_11_REG  ================================================= */
-#define QSPIC_QSPIC_CTR_KEY_8_11_REG_QSPIC_CTR_KEY_8_11_Pos (0UL)   /*!< QSPIC_CTR_KEY_8_11 (Bit 0)                            */
-#define QSPIC_QSPIC_CTR_KEY_8_11_REG_QSPIC_CTR_KEY_8_11_Msk (0xffffffffUL) /*!< QSPIC_CTR_KEY_8_11 (Bitfield-Mask: 0xffffffff) */
-/* ================================================  QSPIC_CTR_NONCE_0_3_REG  ================================================ */
-#define QSPIC_QSPIC_CTR_NONCE_0_3_REG_QSPIC_CTR_NONCE_0_3_Pos (0UL) /*!< QSPIC_CTR_NONCE_0_3 (Bit 0)                           */
-#define QSPIC_QSPIC_CTR_NONCE_0_3_REG_QSPIC_CTR_NONCE_0_3_Msk (0xffffffffUL) /*!< QSPIC_CTR_NONCE_0_3 (Bitfield-Mask: 0xffffffff) */
-/* ================================================  QSPIC_CTR_NONCE_4_7_REG  ================================================ */
-#define QSPIC_QSPIC_CTR_NONCE_4_7_REG_QSPIC_CTR_NONCE_4_7_Pos (0UL) /*!< QSPIC_CTR_NONCE_4_7 (Bit 0)                           */
-#define QSPIC_QSPIC_CTR_NONCE_4_7_REG_QSPIC_CTR_NONCE_4_7_Msk (0xffffffffUL) /*!< QSPIC_CTR_NONCE_4_7 (Bitfield-Mask: 0xffffffff) */
-/* ==================================================  QSPIC_CTR_SADDR_REG  ================================================== */
-#define QSPIC_QSPIC_CTR_SADDR_REG_QSPIC_CTR_SADDR_Pos (10UL)        /*!< QSPIC_CTR_SADDR (Bit 10)                              */
-#define QSPIC_QSPIC_CTR_SADDR_REG_QSPIC_CTR_SADDR_Msk (0xfffffc00UL) /*!< QSPIC_CTR_SADDR (Bitfield-Mask: 0x3fffff)            */
-/* ==================================================  QSPIC_DUMMYDATA_REG  ================================================== */
-#define QSPIC_QSPIC_DUMMYDATA_REG_QSPIC_DUMMYDATA_Pos (0UL)         /*!< QSPIC_DUMMYDATA (Bit 0)                               */
-#define QSPIC_QSPIC_DUMMYDATA_REG_QSPIC_DUMMYDATA_Msk (0xffffffffUL) /*!< QSPIC_DUMMYDATA (Bitfield-Mask: 0xffffffff)          */
-/* ==================================================  QSPIC_ERASECMDA_REG  ================================================== */
-#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_RES_INST_Pos (24UL)         /*!< QSPIC_RES_INST (Bit 24)                               */
-#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_RES_INST_Msk (0xff000000UL) /*!< QSPIC_RES_INST (Bitfield-Mask: 0xff)                  */
-#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_SUS_INST_Pos (16UL)         /*!< QSPIC_SUS_INST (Bit 16)                               */
-#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_SUS_INST_Msk (0xff0000UL)   /*!< QSPIC_SUS_INST (Bitfield-Mask: 0xff)                  */
-#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_WEN_INST_Pos (8UL)          /*!< QSPIC_WEN_INST (Bit 8)                                */
-#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_WEN_INST_Msk (0xff00UL)     /*!< QSPIC_WEN_INST (Bitfield-Mask: 0xff)                  */
-#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_ERS_INST_Pos (0UL)          /*!< QSPIC_ERS_INST (Bit 0)                                */
-#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_ERS_INST_Msk (0xffUL)       /*!< QSPIC_ERS_INST (Bitfield-Mask: 0xff)                  */
-/* ==================================================  QSPIC_ERASECMDB_REG  ================================================== */
-#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RESSUS_DLY_Pos (24UL)       /*!< QSPIC_RESSUS_DLY (Bit 24)                             */
-#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RESSUS_DLY_Msk (0x3f000000UL) /*!< QSPIC_RESSUS_DLY (Bitfield-Mask: 0x3f)              */
-#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERSRES_HLD_Pos (16UL)       /*!< QSPIC_ERSRES_HLD (Bit 16)                             */
-#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERSRES_HLD_Msk (0xf0000UL)  /*!< QSPIC_ERSRES_HLD (Bitfield-Mask: 0x0f)                */
-#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Pos (10UL)        /*!< QSPIC_ERS_CS_HI (Bit 10)                              */
-#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Msk (0x7c00UL)    /*!< QSPIC_ERS_CS_HI (Bitfield-Mask: 0x1f)                 */
-#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_EAD_TX_MD_Pos (8UL)         /*!< QSPIC_EAD_TX_MD (Bit 8)                               */
-#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_EAD_TX_MD_Msk (0x300UL)     /*!< QSPIC_EAD_TX_MD (Bitfield-Mask: 0x03)                 */
-#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RES_TX_MD_Pos (6UL)         /*!< QSPIC_RES_TX_MD (Bit 6)                               */
-#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RES_TX_MD_Msk (0xc0UL)      /*!< QSPIC_RES_TX_MD (Bitfield-Mask: 0x03)                 */
-#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_SUS_TX_MD_Pos (4UL)         /*!< QSPIC_SUS_TX_MD (Bit 4)                               */
-#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_SUS_TX_MD_Msk (0x30UL)      /*!< QSPIC_SUS_TX_MD (Bitfield-Mask: 0x03)                 */
-#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_WEN_TX_MD_Pos (2UL)         /*!< QSPIC_WEN_TX_MD (Bit 2)                               */
-#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_WEN_TX_MD_Msk (0xcUL)       /*!< QSPIC_WEN_TX_MD (Bitfield-Mask: 0x03)                 */
-#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_TX_MD_Pos (0UL)         /*!< QSPIC_ERS_TX_MD (Bit 0)                               */
-#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_TX_MD_Msk (0x3UL)       /*!< QSPIC_ERS_TX_MD (Bitfield-Mask: 0x03)                 */
-/* ==================================================  QSPIC_ERASECTRL_REG  ================================================== */
-#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_STATE_Pos (25UL)        /*!< QSPIC_ERS_STATE (Bit 25)                              */
-#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_STATE_Msk (0xe000000UL) /*!< QSPIC_ERS_STATE (Bitfield-Mask: 0x07)                 */
-#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERASE_EN_Pos (24UL)         /*!< QSPIC_ERASE_EN (Bit 24)                               */
-#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERASE_EN_Msk (0x1000000UL)  /*!< QSPIC_ERASE_EN (Bitfield-Mask: 0x01)                  */
-#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_ADDR_Pos (4UL)          /*!< QSPIC_ERS_ADDR (Bit 4)                                */
-#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_ADDR_Msk (0xfffff0UL)   /*!< QSPIC_ERS_ADDR (Bitfield-Mask: 0xfffff)               */
-/* =====================================================  QSPIC_GP_REG  ====================================================== */
-#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_SLEW_Pos (3UL)                /*!< QSPIC_PADS_SLEW (Bit 3)                               */
-#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_SLEW_Msk (0x18UL)             /*!< QSPIC_PADS_SLEW (Bitfield-Mask: 0x03)                 */
-#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_DRV_Pos (1UL)                 /*!< QSPIC_PADS_DRV (Bit 1)                                */
-#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_DRV_Msk (0x6UL)               /*!< QSPIC_PADS_DRV (Bitfield-Mask: 0x03)                  */
-/* ==================================================  QSPIC_READDATA_REG  =================================================== */
-#define QSPIC_QSPIC_READDATA_REG_QSPIC_READDATA_Pos (0UL)           /*!< QSPIC_READDATA (Bit 0)                                */
-#define QSPIC_QSPIC_READDATA_REG_QSPIC_READDATA_Msk (0xffffffffUL)  /*!< QSPIC_READDATA (Bitfield-Mask: 0xffffffff)            */
-/* ==================================================  QSPIC_RECVDATA_REG  =================================================== */
-#define QSPIC_QSPIC_RECVDATA_REG_QSPIC_RECVDATA_Pos (0UL)           /*!< QSPIC_RECVDATA (Bit 0)                                */
-#define QSPIC_QSPIC_RECVDATA_REG_QSPIC_RECVDATA_Msk (0xffffffffUL)  /*!< QSPIC_RECVDATA (Bitfield-Mask: 0xffffffff)            */
-/* ==================================================  QSPIC_STATUSCMD_REG  ================================================== */
-#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_STSDLY_SEL_Pos (22UL)       /*!< QSPIC_STSDLY_SEL (Bit 22)                             */
-#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_STSDLY_SEL_Msk (0x400000UL) /*!< QSPIC_STSDLY_SEL (Bitfield-Mask: 0x01)                */
-#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RESSTS_DLY_Pos (16UL)       /*!< QSPIC_RESSTS_DLY (Bit 16)                             */
-#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RESSTS_DLY_Msk (0x3f0000UL) /*!< QSPIC_RESSTS_DLY (Bitfield-Mask: 0x3f)                */
-#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_VAL_Pos (15UL)         /*!< QSPIC_BUSY_VAL (Bit 15)                               */
-#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_VAL_Msk (0x8000UL)     /*!< QSPIC_BUSY_VAL (Bitfield-Mask: 0x01)                  */
-#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_POS_Pos (12UL)         /*!< QSPIC_BUSY_POS (Bit 12)                               */
-#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_POS_Msk (0x7000UL)     /*!< QSPIC_BUSY_POS (Bitfield-Mask: 0x07)                  */
-#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Pos (10UL)      /*!< QSPIC_RSTAT_RX_MD (Bit 10)                            */
-#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Msk (0xc00UL)   /*!< QSPIC_RSTAT_RX_MD (Bitfield-Mask: 0x03)               */
-#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Pos (8UL)       /*!< QSPIC_RSTAT_TX_MD (Bit 8)                             */
-#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Msk (0x300UL)   /*!< QSPIC_RSTAT_TX_MD (Bitfield-Mask: 0x03)               */
-#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_INST_Pos (0UL)        /*!< QSPIC_RSTAT_INST (Bit 0)                              */
-#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_INST_Msk (0xffUL)     /*!< QSPIC_RSTAT_INST (Bitfield-Mask: 0xff)                */
-/* ===================================================  QSPIC_STATUS_REG  ==================================================== */
-#define QSPIC_QSPIC_STATUS_REG_QSPIC_BUSY_Pos (0UL)                 /*!< QSPIC_BUSY (Bit 0)                                    */
-#define QSPIC_QSPIC_STATUS_REG_QSPIC_BUSY_Msk (0x1UL)               /*!< QSPIC_BUSY (Bitfield-Mask: 0x01)                      */
-/* ===================================================  QSPIC_UCODE_START  =================================================== */
-#define QSPIC_QSPIC_UCODE_START_QSPIC_UCODE_X_Pos (0UL)             /*!< QSPIC_UCODE_X (Bit 0)                                 */
-#define QSPIC_QSPIC_UCODE_START_QSPIC_UCODE_X_Msk (0xffffffffUL)    /*!< QSPIC_UCODE_X (Bitfield-Mask: 0xffffffff)             */
-/* ==================================================  QSPIC_WRITEDATA_REG  ================================================== */
-#define QSPIC_QSPIC_WRITEDATA_REG_QSPIC_WRITEDATA_Pos (0UL)         /*!< QSPIC_WRITEDATA (Bit 0)                               */
-#define QSPIC_QSPIC_WRITEDATA_REG_QSPIC_WRITEDATA_Msk (0xffffffffUL) /*!< QSPIC_WRITEDATA (Bitfield-Mask: 0xffffffff)          */
-
-
-/* =========================================================================================================================== */
-/* ================                                          QSPIC2                                           ================ */
-/* =========================================================================================================================== */
-
-/* =================================================  QSPIC2_AWRITECMD_REG  ================================================== */
-#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_CS_HIGH_MIN_Pos (14UL) /*!< QSPIC_WR_CS_HIGH_MIN (Bit 14)                         */
-#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_CS_HIGH_MIN_Msk (0x7c000UL) /*!< QSPIC_WR_CS_HIGH_MIN (Bitfield-Mask: 0x1f)       */
-#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_DAT_TX_MD_Pos (12UL)   /*!< QSPIC_WR_DAT_TX_MD (Bit 12)                           */
-#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_DAT_TX_MD_Msk (0x3000UL) /*!< QSPIC_WR_DAT_TX_MD (Bitfield-Mask: 0x03)            */
-#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_ADR_TX_MD_Pos (10UL)   /*!< QSPIC_WR_ADR_TX_MD (Bit 10)                           */
-#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_ADR_TX_MD_Msk (0xc00UL) /*!< QSPIC_WR_ADR_TX_MD (Bitfield-Mask: 0x03)             */
-#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_INST_TX_MD_Pos (8UL)   /*!< QSPIC_WR_INST_TX_MD (Bit 8)                           */
-#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_INST_TX_MD_Msk (0x300UL) /*!< QSPIC_WR_INST_TX_MD (Bitfield-Mask: 0x03)           */
-#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_INST_Pos (0UL)         /*!< QSPIC_WR_INST (Bit 0)                                 */
-#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_INST_Msk (0xffUL)      /*!< QSPIC_WR_INST (Bitfield-Mask: 0xff)                   */
-/* ==================================================  QSPIC2_BURSTBRK_REG  ================================================== */
-#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_SEC_HF_DS_Pos (20UL)       /*!< QSPIC_SEC_HF_DS (Bit 20)                              */
-#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_SEC_HF_DS_Msk (0x100000UL) /*!< QSPIC_SEC_HF_DS (Bitfield-Mask: 0x01)                 */
-#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_BRK_TX_MD_Pos (18UL)       /*!< QSPIC_BRK_TX_MD (Bit 18)                              */
-#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_BRK_TX_MD_Msk (0xc0000UL)  /*!< QSPIC_BRK_TX_MD (Bitfield-Mask: 0x03)                 */
-#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_BRK_SZ_Pos (17UL)          /*!< QSPIC_BRK_SZ (Bit 17)                                 */
-#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_BRK_SZ_Msk (0x20000UL)     /*!< QSPIC_BRK_SZ (Bitfield-Mask: 0x01)                    */
-#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_BRK_EN_Pos (16UL)          /*!< QSPIC_BRK_EN (Bit 16)                                 */
-#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_BRK_EN_Msk (0x10000UL)     /*!< QSPIC_BRK_EN (Bitfield-Mask: 0x01)                    */
-#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_BRK_WRD_Pos (0UL)          /*!< QSPIC_BRK_WRD (Bit 0)                                 */
-#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_BRK_WRD_Msk (0xffffUL)     /*!< QSPIC_BRK_WRD (Bitfield-Mask: 0xffff)                 */
-/* =================================================  QSPIC2_BURSTCMDA_REG  ================================================== */
-#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Pos (30UL)      /*!< QSPIC_DMY_TX_MD (Bit 30)                              */
-#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Msk (0xc0000000UL) /*!< QSPIC_DMY_TX_MD (Bitfield-Mask: 0x03)              */
-#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Pos (28UL)      /*!< QSPIC_EXT_TX_MD (Bit 28)                              */
-#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Msk (0x30000000UL) /*!< QSPIC_EXT_TX_MD (Bitfield-Mask: 0x03)              */
-#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Pos (26UL)      /*!< QSPIC_ADR_TX_MD (Bit 26)                              */
-#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Msk (0xc000000UL) /*!< QSPIC_ADR_TX_MD (Bitfield-Mask: 0x03)               */
-#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_INST_TX_MD_Pos (24UL)     /*!< QSPIC_INST_TX_MD (Bit 24)                             */
-#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_INST_TX_MD_Msk (0x3000000UL) /*!< QSPIC_INST_TX_MD (Bitfield-Mask: 0x03)             */
-#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_EXT_BYTE_Pos (16UL)       /*!< QSPIC_EXT_BYTE (Bit 16)                               */
-#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_EXT_BYTE_Msk (0xff0000UL) /*!< QSPIC_EXT_BYTE (Bitfield-Mask: 0xff)                  */
-#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_INST_WB_Pos (8UL)         /*!< QSPIC_INST_WB (Bit 8)                                 */
-#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_INST_WB_Msk (0xff00UL)    /*!< QSPIC_INST_WB (Bitfield-Mask: 0xff)                   */
-#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_INST_Pos (0UL)            /*!< QSPIC_INST (Bit 0)                                    */
-#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_INST_Msk (0xffUL)         /*!< QSPIC_INST (Bitfield-Mask: 0xff)                      */
-/* =================================================  QSPIC2_BURSTCMDB_REG  ================================================== */
-#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_DMY_FORCE_Pos (15UL)      /*!< QSPIC_DMY_FORCE (Bit 15)                              */
-#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_DMY_FORCE_Msk (0x8000UL)  /*!< QSPIC_DMY_FORCE (Bitfield-Mask: 0x01)                 */
-#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Pos (12UL)    /*!< QSPIC_CS_HIGH_MIN (Bit 12)                            */
-#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Msk (0x7000UL) /*!< QSPIC_CS_HIGH_MIN (Bitfield-Mask: 0x07)              */
-#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Pos (10UL)      /*!< QSPIC_WRAP_SIZE (Bit 10)                              */
-#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Msk (0xc00UL)   /*!< QSPIC_WRAP_SIZE (Bitfield-Mask: 0x03)                 */
-#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_WRAP_LEN_Pos (8UL)        /*!< QSPIC_WRAP_LEN (Bit 8)                                */
-#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_WRAP_LEN_Msk (0x300UL)    /*!< QSPIC_WRAP_LEN (Bitfield-Mask: 0x03)                  */
-#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_WRAP_MD_Pos (7UL)         /*!< QSPIC_WRAP_MD (Bit 7)                                 */
-#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_WRAP_MD_Msk (0x80UL)      /*!< QSPIC_WRAP_MD (Bitfield-Mask: 0x01)                   */
-#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_INST_MD_Pos (6UL)         /*!< QSPIC_INST_MD (Bit 6)                                 */
-#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_INST_MD_Msk (0x40UL)      /*!< QSPIC_INST_MD (Bitfield-Mask: 0x01)                   */
-#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_DMY_NUM_Pos (4UL)         /*!< QSPIC_DMY_NUM (Bit 4)                                 */
-#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_DMY_NUM_Msk (0x30UL)      /*!< QSPIC_DMY_NUM (Bitfield-Mask: 0x03)                   */
-#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Pos (3UL)       /*!< QSPIC_EXT_HF_DS (Bit 3)                               */
-#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Msk (0x8UL)     /*!< QSPIC_EXT_HF_DS (Bitfield-Mask: 0x01)                 */
-#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Pos (2UL)     /*!< QSPIC_EXT_BYTE_EN (Bit 2)                             */
-#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Msk (0x4UL)   /*!< QSPIC_EXT_BYTE_EN (Bitfield-Mask: 0x01)               */
-#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Pos (0UL)       /*!< QSPIC_DAT_RX_MD (Bit 0)                               */
-#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Msk (0x3UL)     /*!< QSPIC_DAT_RX_MD (Bitfield-Mask: 0x03)                 */
-/* =================================================  QSPIC2_CHCKERASE_REG  ================================================== */
-#define QSPIC2_QSPIC2_CHCKERASE_REG_QSPIC_CHCKERASE_Pos (0UL)       /*!< QSPIC_CHCKERASE (Bit 0)                               */
-#define QSPIC2_QSPIC2_CHCKERASE_REG_QSPIC_CHCKERASE_Msk (0xffffffffUL) /*!< QSPIC_CHCKERASE (Bitfield-Mask: 0xffffffff)        */
-/* ==================================================  QSPIC2_CTRLBUS_REG  =================================================== */
-#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_DIS_CS_Pos (4UL)            /*!< QSPIC_DIS_CS (Bit 4)                                  */
-#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_DIS_CS_Msk (0x10UL)         /*!< QSPIC_DIS_CS (Bitfield-Mask: 0x01)                    */
-#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_EN_CS_Pos (3UL)             /*!< QSPIC_EN_CS (Bit 3)                                   */
-#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_EN_CS_Msk (0x8UL)           /*!< QSPIC_EN_CS (Bitfield-Mask: 0x01)                     */
-#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_SET_QUAD_Pos (2UL)          /*!< QSPIC_SET_QUAD (Bit 2)                                */
-#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_SET_QUAD_Msk (0x4UL)        /*!< QSPIC_SET_QUAD (Bitfield-Mask: 0x01)                  */
-#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_SET_DUAL_Pos (1UL)          /*!< QSPIC_SET_DUAL (Bit 1)                                */
-#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_SET_DUAL_Msk (0x2UL)        /*!< QSPIC_SET_DUAL (Bitfield-Mask: 0x01)                  */
-#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_SET_SINGLE_Pos (0UL)        /*!< QSPIC_SET_SINGLE (Bit 0)                              */
-#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_SET_SINGLE_Msk (0x1UL)      /*!< QSPIC_SET_SINGLE (Bitfield-Mask: 0x01)                */
-/* ==================================================  QSPIC2_CTRLMODE_REG  ================================================== */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_CLK_FREE_EN_Pos (16UL)     /*!< QSPIC_CLK_FREE_EN (Bit 16)                            */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_CLK_FREE_EN_Msk (0x10000UL) /*!< QSPIC_CLK_FREE_EN (Bitfield-Mask: 0x01)              */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_CS_MD_Pos (15UL)           /*!< QSPIC_CS_MD (Bit 15)                                  */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_CS_MD_Msk (0x8000UL)       /*!< QSPIC_CS_MD (Bitfield-Mask: 0x01)                     */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_SRAM_EN_Pos (14UL)         /*!< QSPIC_SRAM_EN (Bit 14)                                */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_SRAM_EN_Msk (0x4000UL)     /*!< QSPIC_SRAM_EN (Bitfield-Mask: 0x01)                   */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_USE_32BA_Pos (13UL)        /*!< QSPIC_USE_32BA (Bit 13)                               */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_USE_32BA_Msk (0x2000UL)    /*!< QSPIC_USE_32BA (Bitfield-Mask: 0x01)                  */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_FORCENSEQ_EN_Pos (12UL)    /*!< QSPIC_FORCENSEQ_EN (Bit 12)                           */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_FORCENSEQ_EN_Msk (0x1000UL) /*!< QSPIC_FORCENSEQ_EN (Bitfield-Mask: 0x01)             */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_PCLK_MD_Pos (9UL)          /*!< QSPIC_PCLK_MD (Bit 9)                                 */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_PCLK_MD_Msk (0xe00UL)      /*!< QSPIC_PCLK_MD (Bitfield-Mask: 0x07)                   */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_RPIPE_EN_Pos (8UL)         /*!< QSPIC_RPIPE_EN (Bit 8)                                */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_RPIPE_EN_Msk (0x100UL)     /*!< QSPIC_RPIPE_EN (Bitfield-Mask: 0x01)                  */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_RXD_NEG_Pos (7UL)          /*!< QSPIC_RXD_NEG (Bit 7)                                 */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_RXD_NEG_Msk (0x80UL)       /*!< QSPIC_RXD_NEG (Bitfield-Mask: 0x01)                   */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_HRDY_MD_Pos (6UL)          /*!< QSPIC_HRDY_MD (Bit 6)                                 */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_HRDY_MD_Msk (0x40UL)       /*!< QSPIC_HRDY_MD (Bitfield-Mask: 0x01)                   */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_IO3_DAT_Pos (5UL)          /*!< QSPIC_IO3_DAT (Bit 5)                                 */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_IO3_DAT_Msk (0x20UL)       /*!< QSPIC_IO3_DAT (Bitfield-Mask: 0x01)                   */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_IO2_DAT_Pos (4UL)          /*!< QSPIC_IO2_DAT (Bit 4)                                 */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_IO2_DAT_Msk (0x10UL)       /*!< QSPIC_IO2_DAT (Bitfield-Mask: 0x01)                   */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_IO3_OEN_Pos (3UL)          /*!< QSPIC_IO3_OEN (Bit 3)                                 */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_IO3_OEN_Msk (0x8UL)        /*!< QSPIC_IO3_OEN (Bitfield-Mask: 0x01)                   */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_IO2_OEN_Pos (2UL)          /*!< QSPIC_IO2_OEN (Bit 2)                                 */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_IO2_OEN_Msk (0x4UL)        /*!< QSPIC_IO2_OEN (Bitfield-Mask: 0x01)                   */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_CLK_MD_Pos (1UL)           /*!< QSPIC_CLK_MD (Bit 1)                                  */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_CLK_MD_Msk (0x2UL)         /*!< QSPIC_CLK_MD (Bitfield-Mask: 0x01)                    */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_AUTO_MD_Pos (0UL)          /*!< QSPIC_AUTO_MD (Bit 0)                                 */
-#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_AUTO_MD_Msk (0x1UL)        /*!< QSPIC_AUTO_MD (Bitfield-Mask: 0x01)                   */
-/* =================================================  QSPIC2_DUMMYDATA_REG  ================================================== */
-#define QSPIC2_QSPIC2_DUMMYDATA_REG_QSPIC_DUMMYDATA_Pos (0UL)       /*!< QSPIC_DUMMYDATA (Bit 0)                               */
-#define QSPIC2_QSPIC2_DUMMYDATA_REG_QSPIC_DUMMYDATA_Msk (0xffffffffUL) /*!< QSPIC_DUMMYDATA (Bitfield-Mask: 0xffffffff)        */
-/* =================================================  QSPIC2_ERASECMDA_REG  ================================================== */
-#define QSPIC2_QSPIC2_ERASECMDA_REG_QSPIC_RES_INST_Pos (24UL)       /*!< QSPIC_RES_INST (Bit 24)                               */
-#define QSPIC2_QSPIC2_ERASECMDA_REG_QSPIC_RES_INST_Msk (0xff000000UL) /*!< QSPIC_RES_INST (Bitfield-Mask: 0xff)                */
-#define QSPIC2_QSPIC2_ERASECMDA_REG_QSPIC_SUS_INST_Pos (16UL)       /*!< QSPIC_SUS_INST (Bit 16)                               */
-#define QSPIC2_QSPIC2_ERASECMDA_REG_QSPIC_SUS_INST_Msk (0xff0000UL) /*!< QSPIC_SUS_INST (Bitfield-Mask: 0xff)                  */
-#define QSPIC2_QSPIC2_ERASECMDA_REG_QSPIC_WEN_INST_Pos (8UL)        /*!< QSPIC_WEN_INST (Bit 8)                                */
-#define QSPIC2_QSPIC2_ERASECMDA_REG_QSPIC_WEN_INST_Msk (0xff00UL)   /*!< QSPIC_WEN_INST (Bitfield-Mask: 0xff)                  */
-#define QSPIC2_QSPIC2_ERASECMDA_REG_QSPIC_ERS_INST_Pos (0UL)        /*!< QSPIC_ERS_INST (Bit 0)                                */
-#define QSPIC2_QSPIC2_ERASECMDA_REG_QSPIC_ERS_INST_Msk (0xffUL)     /*!< QSPIC_ERS_INST (Bitfield-Mask: 0xff)                  */
-/* =================================================  QSPIC2_ERASECMDB_REG  ================================================== */
-#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_RESSUS_DLY_Pos (24UL)     /*!< QSPIC_RESSUS_DLY (Bit 24)                             */
-#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_RESSUS_DLY_Msk (0x3f000000UL) /*!< QSPIC_RESSUS_DLY (Bitfield-Mask: 0x3f)            */
-#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_ERSRES_HLD_Pos (16UL)     /*!< QSPIC_ERSRES_HLD (Bit 16)                             */
-#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_ERSRES_HLD_Msk (0xf0000UL) /*!< QSPIC_ERSRES_HLD (Bitfield-Mask: 0x0f)               */
-#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_ERS_CS_HI_Pos (10UL)      /*!< QSPIC_ERS_CS_HI (Bit 10)                              */
-#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_ERS_CS_HI_Msk (0x7c00UL)  /*!< QSPIC_ERS_CS_HI (Bitfield-Mask: 0x1f)                 */
-#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_EAD_TX_MD_Pos (8UL)       /*!< QSPIC_EAD_TX_MD (Bit 8)                               */
-#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_EAD_TX_MD_Msk (0x300UL)   /*!< QSPIC_EAD_TX_MD (Bitfield-Mask: 0x03)                 */
-#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_RES_TX_MD_Pos (6UL)       /*!< QSPIC_RES_TX_MD (Bit 6)                               */
-#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_RES_TX_MD_Msk (0xc0UL)    /*!< QSPIC_RES_TX_MD (Bitfield-Mask: 0x03)                 */
-#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_SUS_TX_MD_Pos (4UL)       /*!< QSPIC_SUS_TX_MD (Bit 4)                               */
-#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_SUS_TX_MD_Msk (0x30UL)    /*!< QSPIC_SUS_TX_MD (Bitfield-Mask: 0x03)                 */
-#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_WEN_TX_MD_Pos (2UL)       /*!< QSPIC_WEN_TX_MD (Bit 2)                               */
-#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_WEN_TX_MD_Msk (0xcUL)     /*!< QSPIC_WEN_TX_MD (Bitfield-Mask: 0x03)                 */
-#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_ERS_TX_MD_Pos (0UL)       /*!< QSPIC_ERS_TX_MD (Bit 0)                               */
-#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_ERS_TX_MD_Msk (0x3UL)     /*!< QSPIC_ERS_TX_MD (Bitfield-Mask: 0x03)                 */
-/* =================================================  QSPIC2_ERASECTRL_REG  ================================================== */
-#define QSPIC2_QSPIC2_ERASECTRL_REG_QSPIC_ERS_STATE_Pos (25UL)      /*!< QSPIC_ERS_STATE (Bit 25)                              */
-#define QSPIC2_QSPIC2_ERASECTRL_REG_QSPIC_ERS_STATE_Msk (0xe000000UL) /*!< QSPIC_ERS_STATE (Bitfield-Mask: 0x07)               */
-#define QSPIC2_QSPIC2_ERASECTRL_REG_QSPIC_ERASE_EN_Pos (24UL)       /*!< QSPIC_ERASE_EN (Bit 24)                               */
-#define QSPIC2_QSPIC2_ERASECTRL_REG_QSPIC_ERASE_EN_Msk (0x1000000UL) /*!< QSPIC_ERASE_EN (Bitfield-Mask: 0x01)                 */
-#define QSPIC2_QSPIC2_ERASECTRL_REG_QSPIC_ERS_ADDR_Pos (4UL)        /*!< QSPIC_ERS_ADDR (Bit 4)                                */
-#define QSPIC2_QSPIC2_ERASECTRL_REG_QSPIC_ERS_ADDR_Msk (0xfffff0UL) /*!< QSPIC_ERS_ADDR (Bitfield-Mask: 0xfffff)               */
-/* =====================================================  QSPIC2_GP_REG  ===================================================== */
-#define QSPIC2_QSPIC2_GP_REG_QSPIC_PADS_SLEW_Pos (3UL)              /*!< QSPIC_PADS_SLEW (Bit 3)                               */
-#define QSPIC2_QSPIC2_GP_REG_QSPIC_PADS_SLEW_Msk (0x18UL)           /*!< QSPIC_PADS_SLEW (Bitfield-Mask: 0x03)                 */
-#define QSPIC2_QSPIC2_GP_REG_QSPIC_PADS_DRV_Pos (1UL)               /*!< QSPIC_PADS_DRV (Bit 1)                                */
-#define QSPIC2_QSPIC2_GP_REG_QSPIC_PADS_DRV_Msk (0x6UL)             /*!< QSPIC_PADS_DRV (Bitfield-Mask: 0x03)                  */
-/* ==================================================  QSPIC2_MEMBLEN_REG  =================================================== */
-#define QSPIC2_QSPIC2_MEMBLEN_REG_QSPIC_T_CEM_CC_Pos (4UL)          /*!< QSPIC_T_CEM_CC (Bit 4)                                */
-#define QSPIC2_QSPIC2_MEMBLEN_REG_QSPIC_T_CEM_CC_Msk (0x3ff0UL)     /*!< QSPIC_T_CEM_CC (Bitfield-Mask: 0x3ff)                 */
-#define QSPIC2_QSPIC2_MEMBLEN_REG_QSPIC_T_CEM_EN_Pos (3UL)          /*!< QSPIC_T_CEM_EN (Bit 3)                                */
-#define QSPIC2_QSPIC2_MEMBLEN_REG_QSPIC_T_CEM_EN_Msk (0x8UL)        /*!< QSPIC_T_CEM_EN (Bitfield-Mask: 0x01)                  */
-#define QSPIC2_QSPIC2_MEMBLEN_REG_QSPIC_MEMBLEN_Pos (0UL)           /*!< QSPIC_MEMBLEN (Bit 0)                                 */
-#define QSPIC2_QSPIC2_MEMBLEN_REG_QSPIC_MEMBLEN_Msk (0x7UL)         /*!< QSPIC_MEMBLEN (Bitfield-Mask: 0x07)                   */
-/* ==================================================  QSPIC2_READDATA_REG  ================================================== */
-#define QSPIC2_QSPIC2_READDATA_REG_QSPIC_READDATA_Pos (0UL)         /*!< QSPIC_READDATA (Bit 0)                                */
-#define QSPIC2_QSPIC2_READDATA_REG_QSPIC_READDATA_Msk (0xffffffffUL) /*!< QSPIC_READDATA (Bitfield-Mask: 0xffffffff)           */
-/* ==================================================  QSPIC2_RECVDATA_REG  ================================================== */
-#define QSPIC2_QSPIC2_RECVDATA_REG_QSPIC_RECVDATA_Pos (0UL)         /*!< QSPIC_RECVDATA (Bit 0)                                */
-#define QSPIC2_QSPIC2_RECVDATA_REG_QSPIC_RECVDATA_Msk (0xffffffffUL) /*!< QSPIC_RECVDATA (Bitfield-Mask: 0xffffffff)           */
-/* =================================================  QSPIC2_STATUSCMD_REG  ================================================== */
-#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_STSDLY_SEL_Pos (22UL)     /*!< QSPIC_STSDLY_SEL (Bit 22)                             */
-#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_STSDLY_SEL_Msk (0x400000UL) /*!< QSPIC_STSDLY_SEL (Bitfield-Mask: 0x01)              */
-#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_RESSTS_DLY_Pos (16UL)     /*!< QSPIC_RESSTS_DLY (Bit 16)                             */
-#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_RESSTS_DLY_Msk (0x3f0000UL) /*!< QSPIC_RESSTS_DLY (Bitfield-Mask: 0x3f)              */
-#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_BUSY_VAL_Pos (15UL)       /*!< QSPIC_BUSY_VAL (Bit 15)                               */
-#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_BUSY_VAL_Msk (0x8000UL)   /*!< QSPIC_BUSY_VAL (Bitfield-Mask: 0x01)                  */
-#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_BUSY_POS_Pos (12UL)       /*!< QSPIC_BUSY_POS (Bit 12)                               */
-#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_BUSY_POS_Msk (0x7000UL)   /*!< QSPIC_BUSY_POS (Bitfield-Mask: 0x07)                  */
-#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Pos (10UL)    /*!< QSPIC_RSTAT_RX_MD (Bit 10)                            */
-#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Msk (0xc00UL) /*!< QSPIC_RSTAT_RX_MD (Bitfield-Mask: 0x03)               */
-#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Pos (8UL)     /*!< QSPIC_RSTAT_TX_MD (Bit 8)                             */
-#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Msk (0x300UL) /*!< QSPIC_RSTAT_TX_MD (Bitfield-Mask: 0x03)               */
-#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_RSTAT_INST_Pos (0UL)      /*!< QSPIC_RSTAT_INST (Bit 0)                              */
-#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_RSTAT_INST_Msk (0xffUL)   /*!< QSPIC_RSTAT_INST (Bitfield-Mask: 0xff)                */
-/* ===================================================  QSPIC2_STATUS_REG  =================================================== */
-#define QSPIC2_QSPIC2_STATUS_REG_QSPIC_BUSY_Pos (0UL)               /*!< QSPIC_BUSY (Bit 0)                                    */
-#define QSPIC2_QSPIC2_STATUS_REG_QSPIC_BUSY_Msk (0x1UL)             /*!< QSPIC_BUSY (Bitfield-Mask: 0x01)                      */
-/* =================================================  QSPIC2_WRITEDATA_REG  ================================================== */
-#define QSPIC2_QSPIC2_WRITEDATA_REG_QSPIC_WRITEDATA_Pos (0UL)       /*!< QSPIC_WRITEDATA (Bit 0)                               */
-#define QSPIC2_QSPIC2_WRITEDATA_REG_QSPIC_WRITEDATA_Msk (0xffffffffUL) /*!< QSPIC_WRITEDATA (Bitfield-Mask: 0xffffffff)        */
-
-
-/* =========================================================================================================================== */
-/* ================                                           RFMON                                           ================ */
-/* =========================================================================================================================== */
-
-/* ====================================================  RFMON_ADDR_REG  ===================================================== */
-#define RFMON_RFMON_ADDR_REG_RFMON_ADDR_Pos (2UL)                   /*!< RFMON_ADDR (Bit 2)                                    */
-#define RFMON_RFMON_ADDR_REG_RFMON_ADDR_Msk (0xfffffffcUL)          /*!< RFMON_ADDR (Bitfield-Mask: 0x3fffffff)                */
-/* ==================================================  RFMON_CRV_ADDR_REG  =================================================== */
-#define RFMON_RFMON_CRV_ADDR_REG_RFMON_CRV_ADDR_Pos (2UL)           /*!< RFMON_CRV_ADDR (Bit 2)                                */
-#define RFMON_RFMON_CRV_ADDR_REG_RFMON_CRV_ADDR_Msk (0xfffffffcUL)  /*!< RFMON_CRV_ADDR (Bitfield-Mask: 0x3fffffff)            */
-/* ===================================================  RFMON_CRV_LEN_REG  =================================================== */
-#define RFMON_RFMON_CRV_LEN_REG_RFMON_CRV_LEN_Pos (0UL)             /*!< RFMON_CRV_LEN (Bit 0)                                 */
-#define RFMON_RFMON_CRV_LEN_REG_RFMON_CRV_LEN_Msk (0x1ffffUL)       /*!< RFMON_CRV_LEN (Bitfield-Mask: 0x1ffff)                */
-/* ====================================================  RFMON_CTRL_REG  ===================================================== */
-#define RFMON_RFMON_CTRL_REG_RFMON_BREQ_FORCE_Pos (2UL)             /*!< RFMON_BREQ_FORCE (Bit 2)                              */
-#define RFMON_RFMON_CTRL_REG_RFMON_BREQ_FORCE_Msk (0x4UL)           /*!< RFMON_BREQ_FORCE (Bitfield-Mask: 0x01)                */
-#define RFMON_RFMON_CTRL_REG_RFMON_CIRC_EN_Pos (1UL)                /*!< RFMON_CIRC_EN (Bit 1)                                 */
-#define RFMON_RFMON_CTRL_REG_RFMON_CIRC_EN_Msk (0x2UL)              /*!< RFMON_CIRC_EN (Bitfield-Mask: 0x01)                   */
-#define RFMON_RFMON_CTRL_REG_RFMON_PACK_EN_Pos (0UL)                /*!< RFMON_PACK_EN (Bit 0)                                 */
-#define RFMON_RFMON_CTRL_REG_RFMON_PACK_EN_Msk (0x1UL)              /*!< RFMON_PACK_EN (Bitfield-Mask: 0x01)                   */
-/* =====================================================  RFMON_LEN_REG  ===================================================== */
-#define RFMON_RFMON_LEN_REG_RFMON_LEN_Pos (0UL)                     /*!< RFMON_LEN (Bit 0)                                     */
-#define RFMON_RFMON_LEN_REG_RFMON_LEN_Msk (0x1ffffUL)               /*!< RFMON_LEN (Bitfield-Mask: 0x1ffff)                    */
-/* ====================================================  RFMON_STAT_REG  ===================================================== */
-#define RFMON_RFMON_STAT_REG_RFMON_OFLOW_STK_Pos (1UL)              /*!< RFMON_OFLOW_STK (Bit 1)                               */
-#define RFMON_RFMON_STAT_REG_RFMON_OFLOW_STK_Msk (0x2UL)            /*!< RFMON_OFLOW_STK (Bitfield-Mask: 0x01)                 */
-#define RFMON_RFMON_STAT_REG_RFMON_ACTIVE_Pos (0UL)                 /*!< RFMON_ACTIVE (Bit 0)                                  */
-#define RFMON_RFMON_STAT_REG_RFMON_ACTIVE_Msk (0x1UL)               /*!< RFMON_ACTIVE (Bitfield-Mask: 0x01)                    */
-
-
-/* =========================================================================================================================== */
-/* ================                                            RTC                                            ================ */
-/* =========================================================================================================================== */
-
-/* =================================================  RTC_ALARM_ENABLE_REG  ================================================== */
-#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MNTH_EN_Pos (5UL)        /*!< RTC_ALARM_MNTH_EN (Bit 5)                             */
-#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MNTH_EN_Msk (0x20UL)     /*!< RTC_ALARM_MNTH_EN (Bitfield-Mask: 0x01)               */
-#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_DATE_EN_Pos (4UL)        /*!< RTC_ALARM_DATE_EN (Bit 4)                             */
-#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_DATE_EN_Msk (0x10UL)     /*!< RTC_ALARM_DATE_EN (Bitfield-Mask: 0x01)               */
-#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOUR_EN_Pos (3UL)        /*!< RTC_ALARM_HOUR_EN (Bit 3)                             */
-#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOUR_EN_Msk (0x8UL)      /*!< RTC_ALARM_HOUR_EN (Bitfield-Mask: 0x01)               */
-#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MIN_EN_Pos (2UL)         /*!< RTC_ALARM_MIN_EN (Bit 2)                              */
-#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MIN_EN_Msk (0x4UL)       /*!< RTC_ALARM_MIN_EN (Bitfield-Mask: 0x01)                */
-#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_SEC_EN_Pos (1UL)         /*!< RTC_ALARM_SEC_EN (Bit 1)                              */
-#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_SEC_EN_Msk (0x2UL)       /*!< RTC_ALARM_SEC_EN (Bitfield-Mask: 0x01)                */
-#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOS_EN_Pos (0UL)         /*!< RTC_ALARM_HOS_EN (Bit 0)                              */
-#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOS_EN_Msk (0x1UL)       /*!< RTC_ALARM_HOS_EN (Bitfield-Mask: 0x01)                */
-/* ================================================  RTC_CALENDAR_ALARM_REG  ================================================= */
-#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_T_Pos (12UL)           /*!< RTC_CAL_D_T (Bit 12)                                  */
-#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_T_Msk (0x3000UL)       /*!< RTC_CAL_D_T (Bitfield-Mask: 0x03)                     */
-#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_U_Pos (8UL)            /*!< RTC_CAL_D_U (Bit 8)                                   */
-#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_U_Msk (0xf00UL)        /*!< RTC_CAL_D_U (Bitfield-Mask: 0x0f)                     */
-#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_T_Pos (7UL)            /*!< RTC_CAL_M_T (Bit 7)                                   */
-#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_T_Msk (0x80UL)         /*!< RTC_CAL_M_T (Bitfield-Mask: 0x01)                     */
-#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_U_Pos (3UL)            /*!< RTC_CAL_M_U (Bit 3)                                   */
-#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_U_Msk (0x78UL)         /*!< RTC_CAL_M_U (Bitfield-Mask: 0x0f)                     */
-/* ===================================================  RTC_CALENDAR_REG  ==================================================== */
-#define RTC_RTC_CALENDAR_REG_RTC_CAL_CH_Pos (31UL)                  /*!< RTC_CAL_CH (Bit 31)                                   */
-#define RTC_RTC_CALENDAR_REG_RTC_CAL_CH_Msk (0x80000000UL)          /*!< RTC_CAL_CH (Bitfield-Mask: 0x01)                      */
-#define RTC_RTC_CALENDAR_REG_RTC_CAL_C_T_Pos (28UL)                 /*!< RTC_CAL_C_T (Bit 28)                                  */
-#define RTC_RTC_CALENDAR_REG_RTC_CAL_C_T_Msk (0x30000000UL)         /*!< RTC_CAL_C_T (Bitfield-Mask: 0x03)                     */
-#define RTC_RTC_CALENDAR_REG_RTC_CAL_C_U_Pos (24UL)                 /*!< RTC_CAL_C_U (Bit 24)                                  */
-#define RTC_RTC_CALENDAR_REG_RTC_CAL_C_U_Msk (0xf000000UL)          /*!< RTC_CAL_C_U (Bitfield-Mask: 0x0f)                     */
-#define RTC_RTC_CALENDAR_REG_RTC_CAL_Y_T_Pos (20UL)                 /*!< RTC_CAL_Y_T (Bit 20)                                  */
-#define RTC_RTC_CALENDAR_REG_RTC_CAL_Y_T_Msk (0xf00000UL)           /*!< RTC_CAL_Y_T (Bitfield-Mask: 0x0f)                     */
-#define RTC_RTC_CALENDAR_REG_RTC_CAL_Y_U_Pos (16UL)                 /*!< RTC_CAL_Y_U (Bit 16)                                  */
-#define RTC_RTC_CALENDAR_REG_RTC_CAL_Y_U_Msk (0xf0000UL)            /*!< RTC_CAL_Y_U (Bitfield-Mask: 0x0f)                     */
-#define RTC_RTC_CALENDAR_REG_RTC_CAL_D_T_Pos (12UL)                 /*!< RTC_CAL_D_T (Bit 12)                                  */
-#define RTC_RTC_CALENDAR_REG_RTC_CAL_D_T_Msk (0x3000UL)             /*!< RTC_CAL_D_T (Bitfield-Mask: 0x03)                     */
-#define RTC_RTC_CALENDAR_REG_RTC_CAL_D_U_Pos (8UL)                  /*!< RTC_CAL_D_U (Bit 8)                                   */
-#define RTC_RTC_CALENDAR_REG_RTC_CAL_D_U_Msk (0xf00UL)              /*!< RTC_CAL_D_U (Bitfield-Mask: 0x0f)                     */
-#define RTC_RTC_CALENDAR_REG_RTC_CAL_M_T_Pos (7UL)                  /*!< RTC_CAL_M_T (Bit 7)                                   */
-#define RTC_RTC_CALENDAR_REG_RTC_CAL_M_T_Msk (0x80UL)               /*!< RTC_CAL_M_T (Bitfield-Mask: 0x01)                     */
-#define RTC_RTC_CALENDAR_REG_RTC_CAL_M_U_Pos (3UL)                  /*!< RTC_CAL_M_U (Bit 3)                                   */
-#define RTC_RTC_CALENDAR_REG_RTC_CAL_M_U_Msk (0x78UL)               /*!< RTC_CAL_M_U (Bitfield-Mask: 0x0f)                     */
-#define RTC_RTC_CALENDAR_REG_RTC_DAY_Pos  (0UL)                     /*!< RTC_DAY (Bit 0)                                       */
-#define RTC_RTC_CALENDAR_REG_RTC_DAY_Msk  (0x7UL)                   /*!< RTC_DAY (Bitfield-Mask: 0x07)                         */
-/* ====================================================  RTC_CONTROL_REG  ==================================================== */
-#define RTC_RTC_CONTROL_REG_RTC_CAL_DISABLE_Pos (1UL)               /*!< RTC_CAL_DISABLE (Bit 1)                               */
-#define RTC_RTC_CONTROL_REG_RTC_CAL_DISABLE_Msk (0x2UL)             /*!< RTC_CAL_DISABLE (Bitfield-Mask: 0x01)                 */
-#define RTC_RTC_CONTROL_REG_RTC_TIME_DISABLE_Pos (0UL)              /*!< RTC_TIME_DISABLE (Bit 0)                              */
-#define RTC_RTC_CONTROL_REG_RTC_TIME_DISABLE_Msk (0x1UL)            /*!< RTC_TIME_DISABLE (Bitfield-Mask: 0x01)                */
-/* ==================================================  RTC_EVENT_CTRL_REG  =================================================== */
-#define RTC_RTC_EVENT_CTRL_REG_RTC_PDC_EVENT_EN_Pos (1UL)           /*!< RTC_PDC_EVENT_EN (Bit 1)                              */
-#define RTC_RTC_EVENT_CTRL_REG_RTC_PDC_EVENT_EN_Msk (0x2UL)         /*!< RTC_PDC_EVENT_EN (Bitfield-Mask: 0x01)                */
-#define RTC_RTC_EVENT_CTRL_REG_RTC_MOTOR_EVENT_EN_Pos (0UL)         /*!< RTC_MOTOR_EVENT_EN (Bit 0)                            */
-#define RTC_RTC_EVENT_CTRL_REG_RTC_MOTOR_EVENT_EN_Msk (0x1UL)       /*!< RTC_MOTOR_EVENT_EN (Bitfield-Mask: 0x01)              */
-/* ==================================================  RTC_EVENT_FLAGS_REG  ================================================== */
-#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_ALRM_Pos (6UL)            /*!< RTC_EVENT_ALRM (Bit 6)                                */
-#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_ALRM_Msk (0x40UL)         /*!< RTC_EVENT_ALRM (Bitfield-Mask: 0x01)                  */
-#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MNTH_Pos (5UL)            /*!< RTC_EVENT_MNTH (Bit 5)                                */
-#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MNTH_Msk (0x20UL)         /*!< RTC_EVENT_MNTH (Bitfield-Mask: 0x01)                  */
-#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_DATE_Pos (4UL)            /*!< RTC_EVENT_DATE (Bit 4)                                */
-#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_DATE_Msk (0x10UL)         /*!< RTC_EVENT_DATE (Bitfield-Mask: 0x01)                  */
-#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOUR_Pos (3UL)            /*!< RTC_EVENT_HOUR (Bit 3)                                */
-#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOUR_Msk (0x8UL)          /*!< RTC_EVENT_HOUR (Bitfield-Mask: 0x01)                  */
-#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MIN_Pos (2UL)             /*!< RTC_EVENT_MIN (Bit 2)                                 */
-#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MIN_Msk (0x4UL)           /*!< RTC_EVENT_MIN (Bitfield-Mask: 0x01)                   */
-#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_SEC_Pos (1UL)             /*!< RTC_EVENT_SEC (Bit 1)                                 */
-#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_SEC_Msk (0x2UL)           /*!< RTC_EVENT_SEC (Bitfield-Mask: 0x01)                   */
-#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOS_Pos (0UL)             /*!< RTC_EVENT_HOS (Bit 0)                                 */
-#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOS_Msk (0x1UL)           /*!< RTC_EVENT_HOS (Bitfield-Mask: 0x01)                   */
-/* ===================================================  RTC_HOUR_MODE_REG  =================================================== */
-#define RTC_RTC_HOUR_MODE_REG_RTC_HMS_Pos (0UL)                     /*!< RTC_HMS (Bit 0)                                       */
-#define RTC_RTC_HOUR_MODE_REG_RTC_HMS_Msk (0x1UL)                   /*!< RTC_HMS (Bitfield-Mask: 0x01)                         */
-/* ===============================================  RTC_INTERRUPT_DISABLE_REG  =============================================== */
-#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_ALRM_INT_DIS_Pos (6UL)    /*!< RTC_ALRM_INT_DIS (Bit 6)                              */
-#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_ALRM_INT_DIS_Msk (0x40UL) /*!< RTC_ALRM_INT_DIS (Bitfield-Mask: 0x01)                */
-#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MNTH_INT_DIS_Pos (5UL)    /*!< RTC_MNTH_INT_DIS (Bit 5)                              */
-#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MNTH_INT_DIS_Msk (0x20UL) /*!< RTC_MNTH_INT_DIS (Bitfield-Mask: 0x01)                */
-#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_DATE_INT_DIS_Pos (4UL)    /*!< RTC_DATE_INT_DIS (Bit 4)                              */
-#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_DATE_INT_DIS_Msk (0x10UL) /*!< RTC_DATE_INT_DIS (Bitfield-Mask: 0x01)                */
-#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOUR_INT_DIS_Pos (3UL)    /*!< RTC_HOUR_INT_DIS (Bit 3)                              */
-#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOUR_INT_DIS_Msk (0x8UL)  /*!< RTC_HOUR_INT_DIS (Bitfield-Mask: 0x01)                */
-#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MIN_INT_DIS_Pos (2UL)     /*!< RTC_MIN_INT_DIS (Bit 2)                               */
-#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MIN_INT_DIS_Msk (0x4UL)   /*!< RTC_MIN_INT_DIS (Bitfield-Mask: 0x01)                 */
-#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_SEC_INT_DIS_Pos (1UL)     /*!< RTC_SEC_INT_DIS (Bit 1)                               */
-#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_SEC_INT_DIS_Msk (0x2UL)   /*!< RTC_SEC_INT_DIS (Bitfield-Mask: 0x01)                 */
-#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOS_INT_DIS_Pos (0UL)     /*!< RTC_HOS_INT_DIS (Bit 0)                               */
-#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOS_INT_DIS_Msk (0x1UL)   /*!< RTC_HOS_INT_DIS (Bitfield-Mask: 0x01)                 */
-/* ===============================================  RTC_INTERRUPT_ENABLE_REG  ================================================ */
-#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_ALRM_INT_EN_Pos (6UL)      /*!< RTC_ALRM_INT_EN (Bit 6)                               */
-#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_ALRM_INT_EN_Msk (0x40UL)   /*!< RTC_ALRM_INT_EN (Bitfield-Mask: 0x01)                 */
-#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MNTH_INT_EN_Pos (5UL)      /*!< RTC_MNTH_INT_EN (Bit 5)                               */
-#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MNTH_INT_EN_Msk (0x20UL)   /*!< RTC_MNTH_INT_EN (Bitfield-Mask: 0x01)                 */
-#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_DATE_INT_EN_Pos (4UL)      /*!< RTC_DATE_INT_EN (Bit 4)                               */
-#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_DATE_INT_EN_Msk (0x10UL)   /*!< RTC_DATE_INT_EN (Bitfield-Mask: 0x01)                 */
-#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOUR_INT_EN_Pos (3UL)      /*!< RTC_HOUR_INT_EN (Bit 3)                               */
-#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOUR_INT_EN_Msk (0x8UL)    /*!< RTC_HOUR_INT_EN (Bitfield-Mask: 0x01)                 */
-#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MIN_INT_EN_Pos (2UL)       /*!< RTC_MIN_INT_EN (Bit 2)                                */
-#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MIN_INT_EN_Msk (0x4UL)     /*!< RTC_MIN_INT_EN (Bitfield-Mask: 0x01)                  */
-#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_SEC_INT_EN_Pos (1UL)       /*!< RTC_SEC_INT_EN (Bit 1)                                */
-#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_SEC_INT_EN_Msk (0x2UL)     /*!< RTC_SEC_INT_EN (Bitfield-Mask: 0x01)                  */
-#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOS_INT_EN_Pos (0UL)       /*!< RTC_HOS_INT_EN (Bit 0)                                */
-#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOS_INT_EN_Msk (0x1UL)     /*!< RTC_HOS_INT_EN (Bitfield-Mask: 0x01)                  */
-/* ================================================  RTC_INTERRUPT_MASK_REG  ================================================= */
-#define RTC_RTC_INTERRUPT_MASK_REG_RTC_ALRM_INT_MSK_Pos (6UL)       /*!< RTC_ALRM_INT_MSK (Bit 6)                              */
-#define RTC_RTC_INTERRUPT_MASK_REG_RTC_ALRM_INT_MSK_Msk (0x40UL)    /*!< RTC_ALRM_INT_MSK (Bitfield-Mask: 0x01)                */
-#define RTC_RTC_INTERRUPT_MASK_REG_RTC_MNTH_INT_MSK_Pos (5UL)       /*!< RTC_MNTH_INT_MSK (Bit 5)                              */
-#define RTC_RTC_INTERRUPT_MASK_REG_RTC_MNTH_INT_MSK_Msk (0x20UL)    /*!< RTC_MNTH_INT_MSK (Bitfield-Mask: 0x01)                */
-#define RTC_RTC_INTERRUPT_MASK_REG_RTC_DATE_INT_MSK_Pos (4UL)       /*!< RTC_DATE_INT_MSK (Bit 4)                              */
-#define RTC_RTC_INTERRUPT_MASK_REG_RTC_DATE_INT_MSK_Msk (0x10UL)    /*!< RTC_DATE_INT_MSK (Bitfield-Mask: 0x01)                */
-#define RTC_RTC_INTERRUPT_MASK_REG_RTC_HOUR_INT_MSK_Pos (3UL)       /*!< RTC_HOUR_INT_MSK (Bit 3)                              */
-#define RTC_RTC_INTERRUPT_MASK_REG_RTC_HOUR_INT_MSK_Msk (0x8UL)     /*!< RTC_HOUR_INT_MSK (Bitfield-Mask: 0x01)                */
-#define RTC_RTC_INTERRUPT_MASK_REG_RTC_MIN_INT_MSK_Pos (2UL)        /*!< RTC_MIN_INT_MSK (Bit 2)                               */
-#define RTC_RTC_INTERRUPT_MASK_REG_RTC_MIN_INT_MSK_Msk (0x4UL)      /*!< RTC_MIN_INT_MSK (Bitfield-Mask: 0x01)                 */
-#define RTC_RTC_INTERRUPT_MASK_REG_RTC_SEC_INT_MSK_Pos (1UL)        /*!< RTC_SEC_INT_MSK (Bit 1)                               */
-#define RTC_RTC_INTERRUPT_MASK_REG_RTC_SEC_INT_MSK_Msk (0x2UL)      /*!< RTC_SEC_INT_MSK (Bitfield-Mask: 0x01)                 */
-#define RTC_RTC_INTERRUPT_MASK_REG_RTC_HOS_INT_MSK_Pos (0UL)        /*!< RTC_HOS_INT_MSK (Bit 0)                               */
-#define RTC_RTC_INTERRUPT_MASK_REG_RTC_HOS_INT_MSK_Msk (0x1UL)      /*!< RTC_HOS_INT_MSK (Bitfield-Mask: 0x01)                 */
-/* ===================================================  RTC_KEEP_RTC_REG  ==================================================== */
-#define RTC_RTC_KEEP_RTC_REG_RTC_KEEP_Pos (0UL)                     /*!< RTC_KEEP (Bit 0)                                      */
-#define RTC_RTC_KEEP_RTC_REG_RTC_KEEP_Msk (0x1UL)                   /*!< RTC_KEEP (Bitfield-Mask: 0x01)                        */
-/* ================================================  RTC_MOTOR_EVENT_CNT_REG  ================================================ */
-#define RTC_RTC_MOTOR_EVENT_CNT_REG_RTC_MOTOR_EVENT_CNT_Pos (0UL)   /*!< RTC_MOTOR_EVENT_CNT (Bit 0)                           */
-#define RTC_RTC_MOTOR_EVENT_CNT_REG_RTC_MOTOR_EVENT_CNT_Msk (0xfffUL) /*!< RTC_MOTOR_EVENT_CNT (Bitfield-Mask: 0xfff)          */
-/* ==============================================  RTC_MOTOR_EVENT_PERIOD_REG  =============================================== */
-#define RTC_RTC_MOTOR_EVENT_PERIOD_REG_RTC_MOTOR_EVENT_PERIOD_Pos (0UL) /*!< RTC_MOTOR_EVENT_PERIOD (Bit 0)                    */
-#define RTC_RTC_MOTOR_EVENT_PERIOD_REG_RTC_MOTOR_EVENT_PERIOD_Msk (0xfffUL) /*!< RTC_MOTOR_EVENT_PERIOD (Bitfield-Mask: 0xfff) */
-/* ================================================  RTC_PDC_EVENT_CLEAR_REG  ================================================ */
-#define RTC_RTC_PDC_EVENT_CLEAR_REG_PDC_EVENT_CLEAR_Pos (0UL)       /*!< PDC_EVENT_CLEAR (Bit 0)                               */
-#define RTC_RTC_PDC_EVENT_CLEAR_REG_PDC_EVENT_CLEAR_Msk (0x1UL)     /*!< PDC_EVENT_CLEAR (Bitfield-Mask: 0x01)                 */
-/* =================================================  RTC_PDC_EVENT_CNT_REG  ================================================= */
-#define RTC_RTC_PDC_EVENT_CNT_REG_RTC_PDC_EVENT_CNT_Pos (0UL)       /*!< RTC_PDC_EVENT_CNT (Bit 0)                             */
-#define RTC_RTC_PDC_EVENT_CNT_REG_RTC_PDC_EVENT_CNT_Msk (0x1fffUL)  /*!< RTC_PDC_EVENT_CNT (Bitfield-Mask: 0x1fff)             */
-/* ===============================================  RTC_PDC_EVENT_PERIOD_REG  ================================================ */
-#define RTC_RTC_PDC_EVENT_PERIOD_REG_RTC_PDC_EVENT_PERIOD_Pos (0UL) /*!< RTC_PDC_EVENT_PERIOD (Bit 0)                          */
-#define RTC_RTC_PDC_EVENT_PERIOD_REG_RTC_PDC_EVENT_PERIOD_Msk (0x1fffUL) /*!< RTC_PDC_EVENT_PERIOD (Bitfield-Mask: 0x1fff)     */
-/* ====================================================  RTC_STATUS_REG  ===================================================== */
-#define RTC_RTC_STATUS_REG_RTC_VALID_CAL_ALM_Pos (3UL)              /*!< RTC_VALID_CAL_ALM (Bit 3)                             */
-#define RTC_RTC_STATUS_REG_RTC_VALID_CAL_ALM_Msk (0x8UL)            /*!< RTC_VALID_CAL_ALM (Bitfield-Mask: 0x01)               */
-#define RTC_RTC_STATUS_REG_RTC_VALID_TIME_ALM_Pos (2UL)             /*!< RTC_VALID_TIME_ALM (Bit 2)                            */
-#define RTC_RTC_STATUS_REG_RTC_VALID_TIME_ALM_Msk (0x4UL)           /*!< RTC_VALID_TIME_ALM (Bitfield-Mask: 0x01)              */
-#define RTC_RTC_STATUS_REG_RTC_VALID_CAL_Pos (1UL)                  /*!< RTC_VALID_CAL (Bit 1)                                 */
-#define RTC_RTC_STATUS_REG_RTC_VALID_CAL_Msk (0x2UL)                /*!< RTC_VALID_CAL (Bitfield-Mask: 0x01)                   */
-#define RTC_RTC_STATUS_REG_RTC_VALID_TIME_Pos (0UL)                 /*!< RTC_VALID_TIME (Bit 0)                                */
-#define RTC_RTC_STATUS_REG_RTC_VALID_TIME_Msk (0x1UL)               /*!< RTC_VALID_TIME (Bitfield-Mask: 0x01)                  */
-/* ==================================================  RTC_TIME_ALARM_REG  =================================================== */
-#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_PM_Pos (30UL)               /*!< RTC_TIME_PM (Bit 30)                                  */
-#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_PM_Msk (0x40000000UL)       /*!< RTC_TIME_PM (Bitfield-Mask: 0x01)                     */
-#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_T_Pos (28UL)             /*!< RTC_TIME_HR_T (Bit 28)                                */
-#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_T_Msk (0x30000000UL)     /*!< RTC_TIME_HR_T (Bitfield-Mask: 0x03)                   */
-#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_U_Pos (24UL)             /*!< RTC_TIME_HR_U (Bit 24)                                */
-#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_U_Msk (0xf000000UL)      /*!< RTC_TIME_HR_U (Bitfield-Mask: 0x0f)                   */
-#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_T_Pos (20UL)              /*!< RTC_TIME_M_T (Bit 20)                                 */
-#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_T_Msk (0x700000UL)        /*!< RTC_TIME_M_T (Bitfield-Mask: 0x07)                    */
-#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_U_Pos (16UL)              /*!< RTC_TIME_M_U (Bit 16)                                 */
-#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_U_Msk (0xf0000UL)         /*!< RTC_TIME_M_U (Bitfield-Mask: 0x0f)                    */
-#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_T_Pos (12UL)              /*!< RTC_TIME_S_T (Bit 12)                                 */
-#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_T_Msk (0x7000UL)          /*!< RTC_TIME_S_T (Bitfield-Mask: 0x07)                    */
-#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_U_Pos (8UL)               /*!< RTC_TIME_S_U (Bit 8)                                  */
-#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_U_Msk (0xf00UL)           /*!< RTC_TIME_S_U (Bitfield-Mask: 0x0f)                    */
-#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_T_Pos (4UL)               /*!< RTC_TIME_H_T (Bit 4)                                  */
-#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_T_Msk (0xf0UL)            /*!< RTC_TIME_H_T (Bitfield-Mask: 0x0f)                    */
-#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_U_Pos (0UL)               /*!< RTC_TIME_H_U (Bit 0)                                  */
-#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_U_Msk (0xfUL)             /*!< RTC_TIME_H_U (Bitfield-Mask: 0x0f)                    */
-/* =====================================================  RTC_TIME_REG  ====================================================== */
-#define RTC_RTC_TIME_REG_RTC_TIME_CH_Pos  (31UL)                    /*!< RTC_TIME_CH (Bit 31)                                  */
-#define RTC_RTC_TIME_REG_RTC_TIME_CH_Msk  (0x80000000UL)            /*!< RTC_TIME_CH (Bitfield-Mask: 0x01)                     */
-#define RTC_RTC_TIME_REG_RTC_TIME_PM_Pos  (30UL)                    /*!< RTC_TIME_PM (Bit 30)                                  */
-#define RTC_RTC_TIME_REG_RTC_TIME_PM_Msk  (0x40000000UL)            /*!< RTC_TIME_PM (Bitfield-Mask: 0x01)                     */
-#define RTC_RTC_TIME_REG_RTC_TIME_HR_T_Pos (28UL)                   /*!< RTC_TIME_HR_T (Bit 28)                                */
-#define RTC_RTC_TIME_REG_RTC_TIME_HR_T_Msk (0x30000000UL)           /*!< RTC_TIME_HR_T (Bitfield-Mask: 0x03)                   */
-#define RTC_RTC_TIME_REG_RTC_TIME_HR_U_Pos (24UL)                   /*!< RTC_TIME_HR_U (Bit 24)                                */
-#define RTC_RTC_TIME_REG_RTC_TIME_HR_U_Msk (0xf000000UL)            /*!< RTC_TIME_HR_U (Bitfield-Mask: 0x0f)                   */
-#define RTC_RTC_TIME_REG_RTC_TIME_M_T_Pos (20UL)                    /*!< RTC_TIME_M_T (Bit 20)                                 */
-#define RTC_RTC_TIME_REG_RTC_TIME_M_T_Msk (0x700000UL)              /*!< RTC_TIME_M_T (Bitfield-Mask: 0x07)                    */
-#define RTC_RTC_TIME_REG_RTC_TIME_M_U_Pos (16UL)                    /*!< RTC_TIME_M_U (Bit 16)                                 */
-#define RTC_RTC_TIME_REG_RTC_TIME_M_U_Msk (0xf0000UL)               /*!< RTC_TIME_M_U (Bitfield-Mask: 0x0f)                    */
-#define RTC_RTC_TIME_REG_RTC_TIME_S_T_Pos (12UL)                    /*!< RTC_TIME_S_T (Bit 12)                                 */
-#define RTC_RTC_TIME_REG_RTC_TIME_S_T_Msk (0x7000UL)                /*!< RTC_TIME_S_T (Bitfield-Mask: 0x07)                    */
-#define RTC_RTC_TIME_REG_RTC_TIME_S_U_Pos (8UL)                     /*!< RTC_TIME_S_U (Bit 8)                                  */
-#define RTC_RTC_TIME_REG_RTC_TIME_S_U_Msk (0xf00UL)                 /*!< RTC_TIME_S_U (Bitfield-Mask: 0x0f)                    */
-#define RTC_RTC_TIME_REG_RTC_TIME_H_T_Pos (4UL)                     /*!< RTC_TIME_H_T (Bit 4)                                  */
-#define RTC_RTC_TIME_REG_RTC_TIME_H_T_Msk (0xf0UL)                  /*!< RTC_TIME_H_T (Bitfield-Mask: 0x0f)                    */
-#define RTC_RTC_TIME_REG_RTC_TIME_H_U_Pos (0UL)                     /*!< RTC_TIME_H_U (Bit 0)                                  */
-#define RTC_RTC_TIME_REG_RTC_TIME_H_U_Msk (0xfUL)                   /*!< RTC_TIME_H_U (Bitfield-Mask: 0x0f)                    */
-
-
-/* =========================================================================================================================== */
-/* ================                                           SDADC                                           ================ */
-/* =========================================================================================================================== */
-
-/* ==================================================  SDADC_CLEAR_INT_REG  ================================================== */
-#define SDADC_SDADC_CLEAR_INT_REG_SDADC_CLR_INT_Pos (0UL)           /*!< SDADC_CLR_INT (Bit 0)                                 */
-#define SDADC_SDADC_CLEAR_INT_REG_SDADC_CLR_INT_Msk (0xffffUL)      /*!< SDADC_CLR_INT (Bitfield-Mask: 0xffff)                 */
-/* ====================================================  SDADC_CTRL_REG  ===================================================== */
-#define SDADC_SDADC_CTRL_REG_SDADC_DMA_EN_Pos (17UL)                /*!< SDADC_DMA_EN (Bit 17)                                 */
-#define SDADC_SDADC_CTRL_REG_SDADC_DMA_EN_Msk (0x20000UL)           /*!< SDADC_DMA_EN (Bitfield-Mask: 0x01)                    */
-#define SDADC_SDADC_CTRL_REG_SDADC_MINT_Pos (16UL)                  /*!< SDADC_MINT (Bit 16)                                   */
-#define SDADC_SDADC_CTRL_REG_SDADC_MINT_Msk (0x10000UL)             /*!< SDADC_MINT (Bitfield-Mask: 0x01)                      */
-#define SDADC_SDADC_CTRL_REG_SDADC_INT_Pos (15UL)                   /*!< SDADC_INT (Bit 15)                                    */
-#define SDADC_SDADC_CTRL_REG_SDADC_INT_Msk (0x8000UL)               /*!< SDADC_INT (Bitfield-Mask: 0x01)                       */
-#define SDADC_SDADC_CTRL_REG_SDADC_LDO_OK_Pos (14UL)                /*!< SDADC_LDO_OK (Bit 14)                                 */
-#define SDADC_SDADC_CTRL_REG_SDADC_LDO_OK_Msk (0x4000UL)            /*!< SDADC_LDO_OK (Bitfield-Mask: 0x01)                    */
-#define SDADC_SDADC_CTRL_REG_SDADC_VREF_SEL_Pos (13UL)              /*!< SDADC_VREF_SEL (Bit 13)                               */
-#define SDADC_SDADC_CTRL_REG_SDADC_VREF_SEL_Msk (0x2000UL)          /*!< SDADC_VREF_SEL (Bitfield-Mask: 0x01)                  */
-#define SDADC_SDADC_CTRL_REG_SDADC_CONT_Pos (12UL)                  /*!< SDADC_CONT (Bit 12)                                   */
-#define SDADC_SDADC_CTRL_REG_SDADC_CONT_Msk (0x1000UL)              /*!< SDADC_CONT (Bitfield-Mask: 0x01)                      */
-#define SDADC_SDADC_CTRL_REG_SDADC_OSR_Pos (10UL)                   /*!< SDADC_OSR (Bit 10)                                    */
-#define SDADC_SDADC_CTRL_REG_SDADC_OSR_Msk (0xc00UL)                /*!< SDADC_OSR (Bitfield-Mask: 0x03)                       */
-#define SDADC_SDADC_CTRL_REG_SDADC_SE_Pos (9UL)                     /*!< SDADC_SE (Bit 9)                                      */
-#define SDADC_SDADC_CTRL_REG_SDADC_SE_Msk (0x200UL)                 /*!< SDADC_SE (Bitfield-Mask: 0x01)                        */
-#define SDADC_SDADC_CTRL_REG_SDADC_INN_SEL_Pos (6UL)                /*!< SDADC_INN_SEL (Bit 6)                                 */
-#define SDADC_SDADC_CTRL_REG_SDADC_INN_SEL_Msk (0x1c0UL)            /*!< SDADC_INN_SEL (Bitfield-Mask: 0x07)                   */
-#define SDADC_SDADC_CTRL_REG_SDADC_INP_SEL_Pos (2UL)                /*!< SDADC_INP_SEL (Bit 2)                                 */
-#define SDADC_SDADC_CTRL_REG_SDADC_INP_SEL_Msk (0x3cUL)             /*!< SDADC_INP_SEL (Bitfield-Mask: 0x0f)                   */
-#define SDADC_SDADC_CTRL_REG_SDADC_START_Pos (1UL)                  /*!< SDADC_START (Bit 1)                                   */
-#define SDADC_SDADC_CTRL_REG_SDADC_START_Msk (0x2UL)                /*!< SDADC_START (Bitfield-Mask: 0x01)                     */
-#define SDADC_SDADC_CTRL_REG_SDADC_EN_Pos (0UL)                     /*!< SDADC_EN (Bit 0)                                      */
-#define SDADC_SDADC_CTRL_REG_SDADC_EN_Msk (0x1UL)                   /*!< SDADC_EN (Bitfield-Mask: 0x01)                        */
-/* ==================================================  SDADC_GAIN_CORR_REG  ================================================== */
-#define SDADC_SDADC_GAIN_CORR_REG_SDADC_GAIN_CORR_Pos (0UL)         /*!< SDADC_GAIN_CORR (Bit 0)                               */
-#define SDADC_SDADC_GAIN_CORR_REG_SDADC_GAIN_CORR_Msk (0x3ffUL)     /*!< SDADC_GAIN_CORR (Bitfield-Mask: 0x3ff)                */
-/* ==================================================  SDADC_OFFS_CORR_REG  ================================================== */
-#define SDADC_SDADC_OFFS_CORR_REG_SDADC_OFFS_CORR_Pos (0UL)         /*!< SDADC_OFFS_CORR (Bit 0)                               */
-#define SDADC_SDADC_OFFS_CORR_REG_SDADC_OFFS_CORR_Msk (0x3ffUL)     /*!< SDADC_OFFS_CORR (Bitfield-Mask: 0x3ff)                */
-/* ===================================================  SDADC_RESULT_REG  ==================================================== */
-#define SDADC_SDADC_RESULT_REG_SDADC_VAL_Pos (0UL)                  /*!< SDADC_VAL (Bit 0)                                     */
-#define SDADC_SDADC_RESULT_REG_SDADC_VAL_Msk (0xffffUL)             /*!< SDADC_VAL (Bitfield-Mask: 0xffff)                     */
-/* ====================================================  SDADC_TEST_REG  ===================================================== */
-#define SDADC_SDADC_TEST_REG_SDADC_CLK_FREQ_Pos (6UL)               /*!< SDADC_CLK_FREQ (Bit 6)                                */
-#define SDADC_SDADC_TEST_REG_SDADC_CLK_FREQ_Msk (0xc0UL)            /*!< SDADC_CLK_FREQ (Bitfield-Mask: 0x03)                  */
-
-
-/* =========================================================================================================================== */
-/* ================                                          SMOTOR                                           ================ */
-/* =========================================================================================================================== */
-
-/* ====================================================  CMD_TABLE_BASE  ===================================================== */
-/* =====================================================  PG0_CTRL_REG  ====================================================== */
-#define SMOTOR_PG0_CTRL_REG_GENEND_IRQ_EN_Pos (15UL)                /*!< GENEND_IRQ_EN (Bit 15)                                */
-#define SMOTOR_PG0_CTRL_REG_GENEND_IRQ_EN_Msk (0x8000UL)            /*!< GENEND_IRQ_EN (Bitfield-Mask: 0x01)                   */
-#define SMOTOR_PG0_CTRL_REG_GENSTART_IRQ_EN_Pos (14UL)              /*!< GENSTART_IRQ_EN (Bit 14)                              */
-#define SMOTOR_PG0_CTRL_REG_GENSTART_IRQ_EN_Msk (0x4000UL)          /*!< GENSTART_IRQ_EN (Bitfield-Mask: 0x01)                 */
-#define SMOTOR_PG0_CTRL_REG_PG_START_MODE_Pos (13UL)                /*!< PG_START_MODE (Bit 13)                                */
-#define SMOTOR_PG0_CTRL_REG_PG_START_MODE_Msk (0x2000UL)            /*!< PG_START_MODE (Bitfield-Mask: 0x01)                   */
-#define SMOTOR_PG0_CTRL_REG_PG_MODE_Pos   (12UL)                    /*!< PG_MODE (Bit 12)                                      */
-#define SMOTOR_PG0_CTRL_REG_PG_MODE_Msk   (0x1000UL)                /*!< PG_MODE (Bitfield-Mask: 0x01)                         */
-#define SMOTOR_PG0_CTRL_REG_SIG3_EN_Pos   (11UL)                    /*!< SIG3_EN (Bit 11)                                      */
-#define SMOTOR_PG0_CTRL_REG_SIG3_EN_Msk   (0x800UL)                 /*!< SIG3_EN (Bitfield-Mask: 0x01)                         */
-#define SMOTOR_PG0_CTRL_REG_SIG2_EN_Pos   (10UL)                    /*!< SIG2_EN (Bit 10)                                      */
-#define SMOTOR_PG0_CTRL_REG_SIG2_EN_Msk   (0x400UL)                 /*!< SIG2_EN (Bitfield-Mask: 0x01)                         */
-#define SMOTOR_PG0_CTRL_REG_SIG1_EN_Pos   (9UL)                     /*!< SIG1_EN (Bit 9)                                       */
-#define SMOTOR_PG0_CTRL_REG_SIG1_EN_Msk   (0x200UL)                 /*!< SIG1_EN (Bitfield-Mask: 0x01)                         */
-#define SMOTOR_PG0_CTRL_REG_SIG0_EN_Pos   (8UL)                     /*!< SIG0_EN (Bit 8)                                       */
-#define SMOTOR_PG0_CTRL_REG_SIG0_EN_Msk   (0x100UL)                 /*!< SIG0_EN (Bitfield-Mask: 0x01)                         */
-#define SMOTOR_PG0_CTRL_REG_OUT3_SIG_Pos  (6UL)                     /*!< OUT3_SIG (Bit 6)                                      */
-#define SMOTOR_PG0_CTRL_REG_OUT3_SIG_Msk  (0xc0UL)                  /*!< OUT3_SIG (Bitfield-Mask: 0x03)                        */
-#define SMOTOR_PG0_CTRL_REG_OUT2_SIG_Pos  (4UL)                     /*!< OUT2_SIG (Bit 4)                                      */
-#define SMOTOR_PG0_CTRL_REG_OUT2_SIG_Msk  (0x30UL)                  /*!< OUT2_SIG (Bitfield-Mask: 0x03)                        */
-#define SMOTOR_PG0_CTRL_REG_OUT1_SIG_Pos  (2UL)                     /*!< OUT1_SIG (Bit 2)                                      */
-#define SMOTOR_PG0_CTRL_REG_OUT1_SIG_Msk  (0xcUL)                   /*!< OUT1_SIG (Bitfield-Mask: 0x03)                        */
-#define SMOTOR_PG0_CTRL_REG_OUT0_SIG_Pos  (0UL)                     /*!< OUT0_SIG (Bit 0)                                      */
-#define SMOTOR_PG0_CTRL_REG_OUT0_SIG_Msk  (0x3UL)                   /*!< OUT0_SIG (Bitfield-Mask: 0x03)                        */
-/* =====================================================  PG1_CTRL_REG  ====================================================== */
-#define SMOTOR_PG1_CTRL_REG_GENEND_IRQ_EN_Pos (15UL)                /*!< GENEND_IRQ_EN (Bit 15)                                */
-#define SMOTOR_PG1_CTRL_REG_GENEND_IRQ_EN_Msk (0x8000UL)            /*!< GENEND_IRQ_EN (Bitfield-Mask: 0x01)                   */
-#define SMOTOR_PG1_CTRL_REG_GENSTART_IRQ_EN_Pos (14UL)              /*!< GENSTART_IRQ_EN (Bit 14)                              */
-#define SMOTOR_PG1_CTRL_REG_GENSTART_IRQ_EN_Msk (0x4000UL)          /*!< GENSTART_IRQ_EN (Bitfield-Mask: 0x01)                 */
-#define SMOTOR_PG1_CTRL_REG_PG_START_MODE_Pos (13UL)                /*!< PG_START_MODE (Bit 13)                                */
-#define SMOTOR_PG1_CTRL_REG_PG_START_MODE_Msk (0x2000UL)            /*!< PG_START_MODE (Bitfield-Mask: 0x01)                   */
-#define SMOTOR_PG1_CTRL_REG_PG_MODE_Pos   (12UL)                    /*!< PG_MODE (Bit 12)                                      */
-#define SMOTOR_PG1_CTRL_REG_PG_MODE_Msk   (0x1000UL)                /*!< PG_MODE (Bitfield-Mask: 0x01)                         */
-#define SMOTOR_PG1_CTRL_REG_SIG3_EN_Pos   (11UL)                    /*!< SIG3_EN (Bit 11)                                      */
-#define SMOTOR_PG1_CTRL_REG_SIG3_EN_Msk   (0x800UL)                 /*!< SIG3_EN (Bitfield-Mask: 0x01)                         */
-#define SMOTOR_PG1_CTRL_REG_SIG2_EN_Pos   (10UL)                    /*!< SIG2_EN (Bit 10)                                      */
-#define SMOTOR_PG1_CTRL_REG_SIG2_EN_Msk   (0x400UL)                 /*!< SIG2_EN (Bitfield-Mask: 0x01)                         */
-#define SMOTOR_PG1_CTRL_REG_SIG1_EN_Pos   (9UL)                     /*!< SIG1_EN (Bit 9)                                       */
-#define SMOTOR_PG1_CTRL_REG_SIG1_EN_Msk   (0x200UL)                 /*!< SIG1_EN (Bitfield-Mask: 0x01)                         */
-#define SMOTOR_PG1_CTRL_REG_SIG0_EN_Pos   (8UL)                     /*!< SIG0_EN (Bit 8)                                       */
-#define SMOTOR_PG1_CTRL_REG_SIG0_EN_Msk   (0x100UL)                 /*!< SIG0_EN (Bitfield-Mask: 0x01)                         */
-#define SMOTOR_PG1_CTRL_REG_OUT3_SIG_Pos  (6UL)                     /*!< OUT3_SIG (Bit 6)                                      */
-#define SMOTOR_PG1_CTRL_REG_OUT3_SIG_Msk  (0xc0UL)                  /*!< OUT3_SIG (Bitfield-Mask: 0x03)                        */
-#define SMOTOR_PG1_CTRL_REG_OUT2_SIG_Pos  (4UL)                     /*!< OUT2_SIG (Bit 4)                                      */
-#define SMOTOR_PG1_CTRL_REG_OUT2_SIG_Msk  (0x30UL)                  /*!< OUT2_SIG (Bitfield-Mask: 0x03)                        */
-#define SMOTOR_PG1_CTRL_REG_OUT1_SIG_Pos  (2UL)                     /*!< OUT1_SIG (Bit 2)                                      */
-#define SMOTOR_PG1_CTRL_REG_OUT1_SIG_Msk  (0xcUL)                   /*!< OUT1_SIG (Bitfield-Mask: 0x03)                        */
-#define SMOTOR_PG1_CTRL_REG_OUT0_SIG_Pos  (0UL)                     /*!< OUT0_SIG (Bit 0)                                      */
-#define SMOTOR_PG1_CTRL_REG_OUT0_SIG_Msk  (0x3UL)                   /*!< OUT0_SIG (Bitfield-Mask: 0x03)                        */
-/* =====================================================  PG2_CTRL_REG  ====================================================== */
-#define SMOTOR_PG2_CTRL_REG_GENEND_IRQ_EN_Pos (15UL)                /*!< GENEND_IRQ_EN (Bit 15)                                */
-#define SMOTOR_PG2_CTRL_REG_GENEND_IRQ_EN_Msk (0x8000UL)            /*!< GENEND_IRQ_EN (Bitfield-Mask: 0x01)                   */
-#define SMOTOR_PG2_CTRL_REG_GENSTART_IRQ_EN_Pos (14UL)              /*!< GENSTART_IRQ_EN (Bit 14)                              */
-#define SMOTOR_PG2_CTRL_REG_GENSTART_IRQ_EN_Msk (0x4000UL)          /*!< GENSTART_IRQ_EN (Bitfield-Mask: 0x01)                 */
-#define SMOTOR_PG2_CTRL_REG_PG_START_MODE_Pos (13UL)                /*!< PG_START_MODE (Bit 13)                                */
-#define SMOTOR_PG2_CTRL_REG_PG_START_MODE_Msk (0x2000UL)            /*!< PG_START_MODE (Bitfield-Mask: 0x01)                   */
-#define SMOTOR_PG2_CTRL_REG_PG_MODE_Pos   (12UL)                    /*!< PG_MODE (Bit 12)                                      */
-#define SMOTOR_PG2_CTRL_REG_PG_MODE_Msk   (0x1000UL)                /*!< PG_MODE (Bitfield-Mask: 0x01)                         */
-#define SMOTOR_PG2_CTRL_REG_SIG3_EN_Pos   (11UL)                    /*!< SIG3_EN (Bit 11)                                      */
-#define SMOTOR_PG2_CTRL_REG_SIG3_EN_Msk   (0x800UL)                 /*!< SIG3_EN (Bitfield-Mask: 0x01)                         */
-#define SMOTOR_PG2_CTRL_REG_SIG2_EN_Pos   (10UL)                    /*!< SIG2_EN (Bit 10)                                      */
-#define SMOTOR_PG2_CTRL_REG_SIG2_EN_Msk   (0x400UL)                 /*!< SIG2_EN (Bitfield-Mask: 0x01)                         */
-#define SMOTOR_PG2_CTRL_REG_SIG1_EN_Pos   (9UL)                     /*!< SIG1_EN (Bit 9)                                       */
-#define SMOTOR_PG2_CTRL_REG_SIG1_EN_Msk   (0x200UL)                 /*!< SIG1_EN (Bitfield-Mask: 0x01)                         */
-#define SMOTOR_PG2_CTRL_REG_SIG0_EN_Pos   (8UL)                     /*!< SIG0_EN (Bit 8)                                       */
-#define SMOTOR_PG2_CTRL_REG_SIG0_EN_Msk   (0x100UL)                 /*!< SIG0_EN (Bitfield-Mask: 0x01)                         */
-#define SMOTOR_PG2_CTRL_REG_OUT3_SIG_Pos  (6UL)                     /*!< OUT3_SIG (Bit 6)                                      */
-#define SMOTOR_PG2_CTRL_REG_OUT3_SIG_Msk  (0xc0UL)                  /*!< OUT3_SIG (Bitfield-Mask: 0x03)                        */
-#define SMOTOR_PG2_CTRL_REG_OUT2_SIG_Pos  (4UL)                     /*!< OUT2_SIG (Bit 4)                                      */
-#define SMOTOR_PG2_CTRL_REG_OUT2_SIG_Msk  (0x30UL)                  /*!< OUT2_SIG (Bitfield-Mask: 0x03)                        */
-#define SMOTOR_PG2_CTRL_REG_OUT1_SIG_Pos  (2UL)                     /*!< OUT1_SIG (Bit 2)                                      */
-#define SMOTOR_PG2_CTRL_REG_OUT1_SIG_Msk  (0xcUL)                   /*!< OUT1_SIG (Bitfield-Mask: 0x03)                        */
-#define SMOTOR_PG2_CTRL_REG_OUT0_SIG_Pos  (0UL)                     /*!< OUT0_SIG (Bit 0)                                      */
-#define SMOTOR_PG2_CTRL_REG_OUT0_SIG_Msk  (0x3UL)                   /*!< OUT0_SIG (Bitfield-Mask: 0x03)                        */
-/* =====================================================  PG3_CTRL_REG  ====================================================== */
-#define SMOTOR_PG3_CTRL_REG_GENEND_IRQ_EN_Pos (15UL)                /*!< GENEND_IRQ_EN (Bit 15)                                */
-#define SMOTOR_PG3_CTRL_REG_GENEND_IRQ_EN_Msk (0x8000UL)            /*!< GENEND_IRQ_EN (Bitfield-Mask: 0x01)                   */
-#define SMOTOR_PG3_CTRL_REG_GENSTART_IRQ_EN_Pos (14UL)              /*!< GENSTART_IRQ_EN (Bit 14)                              */
-#define SMOTOR_PG3_CTRL_REG_GENSTART_IRQ_EN_Msk (0x4000UL)          /*!< GENSTART_IRQ_EN (Bitfield-Mask: 0x01)                 */
-#define SMOTOR_PG3_CTRL_REG_PG_START_MODE_Pos (13UL)                /*!< PG_START_MODE (Bit 13)                                */
-#define SMOTOR_PG3_CTRL_REG_PG_START_MODE_Msk (0x2000UL)            /*!< PG_START_MODE (Bitfield-Mask: 0x01)                   */
-#define SMOTOR_PG3_CTRL_REG_PG_MODE_Pos   (12UL)                    /*!< PG_MODE (Bit 12)                                      */
-#define SMOTOR_PG3_CTRL_REG_PG_MODE_Msk   (0x1000UL)                /*!< PG_MODE (Bitfield-Mask: 0x01)                         */
-#define SMOTOR_PG3_CTRL_REG_SIG3_EN_Pos   (11UL)                    /*!< SIG3_EN (Bit 11)                                      */
-#define SMOTOR_PG3_CTRL_REG_SIG3_EN_Msk   (0x800UL)                 /*!< SIG3_EN (Bitfield-Mask: 0x01)                         */
-#define SMOTOR_PG3_CTRL_REG_SIG2_EN_Pos   (10UL)                    /*!< SIG2_EN (Bit 10)                                      */
-#define SMOTOR_PG3_CTRL_REG_SIG2_EN_Msk   (0x400UL)                 /*!< SIG2_EN (Bitfield-Mask: 0x01)                         */
-#define SMOTOR_PG3_CTRL_REG_SIG1_EN_Pos   (9UL)                     /*!< SIG1_EN (Bit 9)                                       */
-#define SMOTOR_PG3_CTRL_REG_SIG1_EN_Msk   (0x200UL)                 /*!< SIG1_EN (Bitfield-Mask: 0x01)                         */
-#define SMOTOR_PG3_CTRL_REG_SIG0_EN_Pos   (8UL)                     /*!< SIG0_EN (Bit 8)                                       */
-#define SMOTOR_PG3_CTRL_REG_SIG0_EN_Msk   (0x100UL)                 /*!< SIG0_EN (Bitfield-Mask: 0x01)                         */
-#define SMOTOR_PG3_CTRL_REG_OUT3_SIG_Pos  (6UL)                     /*!< OUT3_SIG (Bit 6)                                      */
-#define SMOTOR_PG3_CTRL_REG_OUT3_SIG_Msk  (0xc0UL)                  /*!< OUT3_SIG (Bitfield-Mask: 0x03)                        */
-#define SMOTOR_PG3_CTRL_REG_OUT2_SIG_Pos  (4UL)                     /*!< OUT2_SIG (Bit 4)                                      */
-#define SMOTOR_PG3_CTRL_REG_OUT2_SIG_Msk  (0x30UL)                  /*!< OUT2_SIG (Bitfield-Mask: 0x03)                        */
-#define SMOTOR_PG3_CTRL_REG_OUT1_SIG_Pos  (2UL)                     /*!< OUT1_SIG (Bit 2)                                      */
-#define SMOTOR_PG3_CTRL_REG_OUT1_SIG_Msk  (0xcUL)                   /*!< OUT1_SIG (Bitfield-Mask: 0x03)                        */
-#define SMOTOR_PG3_CTRL_REG_OUT0_SIG_Pos  (0UL)                     /*!< OUT0_SIG (Bit 0)                                      */
-#define SMOTOR_PG3_CTRL_REG_OUT0_SIG_Msk  (0x3UL)                   /*!< OUT0_SIG (Bitfield-Mask: 0x03)                        */
-/* =====================================================  PG4_CTRL_REG  ====================================================== */
-#define SMOTOR_PG4_CTRL_REG_GENEND_IRQ_EN_Pos (15UL)                /*!< GENEND_IRQ_EN (Bit 15)                                */
-#define SMOTOR_PG4_CTRL_REG_GENEND_IRQ_EN_Msk (0x8000UL)            /*!< GENEND_IRQ_EN (Bitfield-Mask: 0x01)                   */
-#define SMOTOR_PG4_CTRL_REG_GENSTART_IRQ_EN_Pos (14UL)              /*!< GENSTART_IRQ_EN (Bit 14)                              */
-#define SMOTOR_PG4_CTRL_REG_GENSTART_IRQ_EN_Msk (0x4000UL)          /*!< GENSTART_IRQ_EN (Bitfield-Mask: 0x01)                 */
-#define SMOTOR_PG4_CTRL_REG_PG_START_MODE_Pos (13UL)                /*!< PG_START_MODE (Bit 13)                                */
-#define SMOTOR_PG4_CTRL_REG_PG_START_MODE_Msk (0x2000UL)            /*!< PG_START_MODE (Bitfield-Mask: 0x01)                   */
-#define SMOTOR_PG4_CTRL_REG_PG_MODE_Pos   (12UL)                    /*!< PG_MODE (Bit 12)                                      */
-#define SMOTOR_PG4_CTRL_REG_PG_MODE_Msk   (0x1000UL)                /*!< PG_MODE (Bitfield-Mask: 0x01)                         */
-#define SMOTOR_PG4_CTRL_REG_SIG3_EN_Pos   (11UL)                    /*!< SIG3_EN (Bit 11)                                      */
-#define SMOTOR_PG4_CTRL_REG_SIG3_EN_Msk   (0x800UL)                 /*!< SIG3_EN (Bitfield-Mask: 0x01)                         */
-#define SMOTOR_PG4_CTRL_REG_SIG2_EN_Pos   (10UL)                    /*!< SIG2_EN (Bit 10)                                      */
-#define SMOTOR_PG4_CTRL_REG_SIG2_EN_Msk   (0x400UL)                 /*!< SIG2_EN (Bitfield-Mask: 0x01)                         */
-#define SMOTOR_PG4_CTRL_REG_SIG1_EN_Pos   (9UL)                     /*!< SIG1_EN (Bit 9)                                       */
-#define SMOTOR_PG4_CTRL_REG_SIG1_EN_Msk   (0x200UL)                 /*!< SIG1_EN (Bitfield-Mask: 0x01)                         */
-#define SMOTOR_PG4_CTRL_REG_SIG0_EN_Pos   (8UL)                     /*!< SIG0_EN (Bit 8)                                       */
-#define SMOTOR_PG4_CTRL_REG_SIG0_EN_Msk   (0x100UL)                 /*!< SIG0_EN (Bitfield-Mask: 0x01)                         */
-#define SMOTOR_PG4_CTRL_REG_OUT3_SIG_Pos  (6UL)                     /*!< OUT3_SIG (Bit 6)                                      */
-#define SMOTOR_PG4_CTRL_REG_OUT3_SIG_Msk  (0xc0UL)                  /*!< OUT3_SIG (Bitfield-Mask: 0x03)                        */
-#define SMOTOR_PG4_CTRL_REG_OUT2_SIG_Pos  (4UL)                     /*!< OUT2_SIG (Bit 4)                                      */
-#define SMOTOR_PG4_CTRL_REG_OUT2_SIG_Msk  (0x30UL)                  /*!< OUT2_SIG (Bitfield-Mask: 0x03)                        */
-#define SMOTOR_PG4_CTRL_REG_OUT1_SIG_Pos  (2UL)                     /*!< OUT1_SIG (Bit 2)                                      */
-#define SMOTOR_PG4_CTRL_REG_OUT1_SIG_Msk  (0xcUL)                   /*!< OUT1_SIG (Bitfield-Mask: 0x03)                        */
-#define SMOTOR_PG4_CTRL_REG_OUT0_SIG_Pos  (0UL)                     /*!< OUT0_SIG (Bit 0)                                      */
-#define SMOTOR_PG4_CTRL_REG_OUT0_SIG_Msk  (0x3UL)                   /*!< OUT0_SIG (Bitfield-Mask: 0x03)                        */
-/* ==================================================  SMOTOR_CMD_FIFO_REG  ================================================== */
-#define SMOTOR_SMOTOR_CMD_FIFO_REG_SMOTOR_CMD_FIFO_Pos (0UL)        /*!< SMOTOR_CMD_FIFO (Bit 0)                               */
-#define SMOTOR_SMOTOR_CMD_FIFO_REG_SMOTOR_CMD_FIFO_Msk (0xffffUL)   /*!< SMOTOR_CMD_FIFO (Bitfield-Mask: 0xffff)               */
-/* ================================================  SMOTOR_CMD_READ_PTR_REG  ================================================ */
-#define SMOTOR_SMOTOR_CMD_READ_PTR_REG_SMOTOR_CMD_READ_PTR_Pos (0UL) /*!< SMOTOR_CMD_READ_PTR (Bit 0)                          */
-#define SMOTOR_SMOTOR_CMD_READ_PTR_REG_SMOTOR_CMD_READ_PTR_Msk (0x3fUL) /*!< SMOTOR_CMD_READ_PTR (Bitfield-Mask: 0x3f)         */
-/* ===============================================  SMOTOR_CMD_WRITE_PTR_REG  ================================================ */
-#define SMOTOR_SMOTOR_CMD_WRITE_PTR_REG_SMOTOR_CMD_WRITE_PTR_Pos (0UL) /*!< SMOTOR_CMD_WRITE_PTR (Bit 0)                       */
-#define SMOTOR_SMOTOR_CMD_WRITE_PTR_REG_SMOTOR_CMD_WRITE_PTR_Msk (0x3fUL) /*!< SMOTOR_CMD_WRITE_PTR (Bitfield-Mask: 0x3f)      */
-/* ====================================================  SMOTOR_CTRL_REG  ==================================================== */
-#define SMOTOR_SMOTOR_CTRL_REG_TRIG_RTC_EVENT_EN_Pos (28UL)         /*!< TRIG_RTC_EVENT_EN (Bit 28)                            */
-#define SMOTOR_SMOTOR_CTRL_REG_TRIG_RTC_EVENT_EN_Msk (0x10000000UL) /*!< TRIG_RTC_EVENT_EN (Bitfield-Mask: 0x01)               */
-#define SMOTOR_SMOTOR_CTRL_REG_MC_LP_CLK_TRIG_EN_Pos (27UL)         /*!< MC_LP_CLK_TRIG_EN (Bit 27)                            */
-#define SMOTOR_SMOTOR_CTRL_REG_MC_LP_CLK_TRIG_EN_Msk (0x8000000UL)  /*!< MC_LP_CLK_TRIG_EN (Bitfield-Mask: 0x01)               */
-#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_THRESHOLD_IRQ_EN_Pos (26UL)   /*!< SMOTOR_THRESHOLD_IRQ_EN (Bit 26)                      */
-#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_THRESHOLD_IRQ_EN_Msk (0x4000000UL) /*!< SMOTOR_THRESHOLD_IRQ_EN (Bitfield-Mask: 0x01)    */
-#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_THRESHOLD_Pos (21UL)          /*!< SMOTOR_THRESHOLD (Bit 21)                             */
-#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_THRESHOLD_Msk (0x3e00000UL)   /*!< SMOTOR_THRESHOLD (Bitfield-Mask: 0x1f)                */
-#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_FIFO_UNR_IRQ_EN_Pos (20UL)    /*!< SMOTOR_FIFO_UNR_IRQ_EN (Bit 20)                       */
-#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_FIFO_UNR_IRQ_EN_Msk (0x100000UL) /*!< SMOTOR_FIFO_UNR_IRQ_EN (Bitfield-Mask: 0x01)       */
-#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_FIFO_OVF_IRQ_EN_Pos (19UL)    /*!< SMOTOR_FIFO_OVF_IRQ_EN (Bit 19)                       */
-#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_FIFO_OVF_IRQ_EN_Msk (0x80000UL) /*!< SMOTOR_FIFO_OVF_IRQ_EN (Bitfield-Mask: 0x01)        */
-#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_GENEND_IRQ_EN_Pos (18UL)      /*!< SMOTOR_GENEND_IRQ_EN (Bit 18)                         */
-#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_GENEND_IRQ_EN_Msk (0x40000UL) /*!< SMOTOR_GENEND_IRQ_EN (Bitfield-Mask: 0x01)            */
-#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_GENSTART_IRQ_EN_Pos (17UL)    /*!< SMOTOR_GENSTART_IRQ_EN (Bit 17)                       */
-#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_GENSTART_IRQ_EN_Msk (0x20000UL) /*!< SMOTOR_GENSTART_IRQ_EN (Bitfield-Mask: 0x01)        */
-#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_MOI_Pos (7UL)                 /*!< SMOTOR_MOI (Bit 7)                                    */
-#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_MOI_Msk (0x1ff80UL)           /*!< SMOTOR_MOI (Bitfield-Mask: 0x3ff)                     */
-#define SMOTOR_SMOTOR_CTRL_REG_CYCLIC_SIZE_Pos (1UL)                /*!< CYCLIC_SIZE (Bit 1)                                   */
-#define SMOTOR_SMOTOR_CTRL_REG_CYCLIC_SIZE_Msk (0x7eUL)             /*!< CYCLIC_SIZE (Bitfield-Mask: 0x3f)                     */
-#define SMOTOR_SMOTOR_CTRL_REG_CYCLIC_MODE_Pos (0UL)                /*!< CYCLIC_MODE (Bit 0)                                   */
-#define SMOTOR_SMOTOR_CTRL_REG_CYCLIC_MODE_Msk (0x1UL)              /*!< CYCLIC_MODE (Bitfield-Mask: 0x01)                     */
-/* =================================================  SMOTOR_IRQ_CLEAR_REG  ================================================== */
-#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_THRESHOLD_IRQ_CLEAR_Pos (4UL)   /*!< THRESHOLD_IRQ_CLEAR (Bit 4)                           */
-#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_THRESHOLD_IRQ_CLEAR_Msk (0x10UL) /*!< THRESHOLD_IRQ_CLEAR (Bitfield-Mask: 0x01)            */
-#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_FIFO_UNR_IRQ_CLEAR_Pos (3UL)    /*!< FIFO_UNR_IRQ_CLEAR (Bit 3)                            */
-#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_FIFO_UNR_IRQ_CLEAR_Msk (0x8UL)  /*!< FIFO_UNR_IRQ_CLEAR (Bitfield-Mask: 0x01)              */
-#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_FIFO_OVF_IRQ_CLEAR_Pos (2UL)    /*!< FIFO_OVF_IRQ_CLEAR (Bit 2)                            */
-#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_FIFO_OVF_IRQ_CLEAR_Msk (0x4UL)  /*!< FIFO_OVF_IRQ_CLEAR (Bitfield-Mask: 0x01)              */
-#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_GENEND_IRQ_CLEAR_Pos (1UL)      /*!< GENEND_IRQ_CLEAR (Bit 1)                              */
-#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_GENEND_IRQ_CLEAR_Msk (0x2UL)    /*!< GENEND_IRQ_CLEAR (Bitfield-Mask: 0x01)                */
-#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_GENSTART_IRQ_CLEAR_Pos (0UL)    /*!< GENSTART_IRQ_CLEAR (Bit 0)                            */
-#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_GENSTART_IRQ_CLEAR_Msk (0x1UL)  /*!< GENSTART_IRQ_CLEAR (Bitfield-Mask: 0x01)              */
-/* ===================================================  SMOTOR_STATUS_REG  =================================================== */
-#define SMOTOR_SMOTOR_STATUS_REG_PG4_BUSY_Pos (9UL)                 /*!< PG4_BUSY (Bit 9)                                      */
-#define SMOTOR_SMOTOR_STATUS_REG_PG4_BUSY_Msk (0x200UL)             /*!< PG4_BUSY (Bitfield-Mask: 0x01)                        */
-#define SMOTOR_SMOTOR_STATUS_REG_PG3_BUSY_Pos (8UL)                 /*!< PG3_BUSY (Bit 8)                                      */
-#define SMOTOR_SMOTOR_STATUS_REG_PG3_BUSY_Msk (0x100UL)             /*!< PG3_BUSY (Bitfield-Mask: 0x01)                        */
-#define SMOTOR_SMOTOR_STATUS_REG_PG2_BUSY_Pos (7UL)                 /*!< PG2_BUSY (Bit 7)                                      */
-#define SMOTOR_SMOTOR_STATUS_REG_PG2_BUSY_Msk (0x80UL)              /*!< PG2_BUSY (Bitfield-Mask: 0x01)                        */
-#define SMOTOR_SMOTOR_STATUS_REG_PG1_BUSY_Pos (6UL)                 /*!< PG1_BUSY (Bit 6)                                      */
-#define SMOTOR_SMOTOR_STATUS_REG_PG1_BUSY_Msk (0x40UL)              /*!< PG1_BUSY (Bitfield-Mask: 0x01)                        */
-#define SMOTOR_SMOTOR_STATUS_REG_PG0_BUSY_Pos (5UL)                 /*!< PG0_BUSY (Bit 5)                                      */
-#define SMOTOR_SMOTOR_STATUS_REG_PG0_BUSY_Msk (0x20UL)              /*!< PG0_BUSY (Bitfield-Mask: 0x01)                        */
-#define SMOTOR_SMOTOR_STATUS_REG_THRESHOLD_IRQ_STATUS_Pos (4UL)     /*!< THRESHOLD_IRQ_STATUS (Bit 4)                          */
-#define SMOTOR_SMOTOR_STATUS_REG_THRESHOLD_IRQ_STATUS_Msk (0x10UL)  /*!< THRESHOLD_IRQ_STATUS (Bitfield-Mask: 0x01)            */
-#define SMOTOR_SMOTOR_STATUS_REG_FIFO_UNR_IRQ_STATUS_Pos (3UL)      /*!< FIFO_UNR_IRQ_STATUS (Bit 3)                           */
-#define SMOTOR_SMOTOR_STATUS_REG_FIFO_UNR_IRQ_STATUS_Msk (0x8UL)    /*!< FIFO_UNR_IRQ_STATUS (Bitfield-Mask: 0x01)             */
-#define SMOTOR_SMOTOR_STATUS_REG_FIFO_OVF_IRQ_STATUS_Pos (2UL)      /*!< FIFO_OVF_IRQ_STATUS (Bit 2)                           */
-#define SMOTOR_SMOTOR_STATUS_REG_FIFO_OVF_IRQ_STATUS_Msk (0x4UL)    /*!< FIFO_OVF_IRQ_STATUS (Bitfield-Mask: 0x01)             */
-#define SMOTOR_SMOTOR_STATUS_REG_GENEND_IRQ_STATUS_Pos (1UL)        /*!< GENEND_IRQ_STATUS (Bit 1)                             */
-#define SMOTOR_SMOTOR_STATUS_REG_GENEND_IRQ_STATUS_Msk (0x2UL)      /*!< GENEND_IRQ_STATUS (Bitfield-Mask: 0x01)               */
-#define SMOTOR_SMOTOR_STATUS_REG_GENSTART_IRQ_STATUS_Pos (0UL)      /*!< GENSTART_IRQ_STATUS (Bit 0)                           */
-#define SMOTOR_SMOTOR_STATUS_REG_GENSTART_IRQ_STATUS_Msk (0x1UL)    /*!< GENSTART_IRQ_STATUS (Bitfield-Mask: 0x01)             */
-/* ==================================================  SMOTOR_TRIGGER_REG  =================================================== */
-#define SMOTOR_SMOTOR_TRIGGER_REG_PG4_START_Pos (5UL)               /*!< PG4_START (Bit 5)                                     */
-#define SMOTOR_SMOTOR_TRIGGER_REG_PG4_START_Msk (0x20UL)            /*!< PG4_START (Bitfield-Mask: 0x01)                       */
-#define SMOTOR_SMOTOR_TRIGGER_REG_PG3_START_Pos (4UL)               /*!< PG3_START (Bit 4)                                     */
-#define SMOTOR_SMOTOR_TRIGGER_REG_PG3_START_Msk (0x10UL)            /*!< PG3_START (Bitfield-Mask: 0x01)                       */
-#define SMOTOR_SMOTOR_TRIGGER_REG_PG2_START_Pos (3UL)               /*!< PG2_START (Bit 3)                                     */
-#define SMOTOR_SMOTOR_TRIGGER_REG_PG2_START_Msk (0x8UL)             /*!< PG2_START (Bitfield-Mask: 0x01)                       */
-#define SMOTOR_SMOTOR_TRIGGER_REG_PG1_START_Pos (2UL)               /*!< PG1_START (Bit 2)                                     */
-#define SMOTOR_SMOTOR_TRIGGER_REG_PG1_START_Msk (0x4UL)             /*!< PG1_START (Bitfield-Mask: 0x01)                       */
-#define SMOTOR_SMOTOR_TRIGGER_REG_PG0_START_Pos (1UL)               /*!< PG0_START (Bit 1)                                     */
-#define SMOTOR_SMOTOR_TRIGGER_REG_PG0_START_Msk (0x2UL)             /*!< PG0_START (Bitfield-Mask: 0x01)                       */
-#define SMOTOR_SMOTOR_TRIGGER_REG_POP_CMD_Pos (0UL)                 /*!< POP_CMD (Bit 0)                                       */
-#define SMOTOR_SMOTOR_TRIGGER_REG_POP_CMD_Msk (0x1UL)               /*!< POP_CMD (Bitfield-Mask: 0x01)                         */
-/* ====================================================  WAVETABLE_BASE  ===================================================== */
-
-
-/* =========================================================================================================================== */
-/* ================                                            SNC                                            ================ */
-/* =========================================================================================================================== */
-
-/* =====================================================  SNC_CTRL_REG  ====================================================== */
-#define SNC_SNC_CTRL_REG_SNC_IRQ_ACK_Pos  (8UL)                     /*!< SNC_IRQ_ACK (Bit 8)                                   */
-#define SNC_SNC_CTRL_REG_SNC_IRQ_ACK_Msk  (0x100UL)                 /*!< SNC_IRQ_ACK (Bitfield-Mask: 0x01)                     */
-#define SNC_SNC_CTRL_REG_SNC_IRQ_CONFIG_Pos (6UL)                   /*!< SNC_IRQ_CONFIG (Bit 6)                                */
-#define SNC_SNC_CTRL_REG_SNC_IRQ_CONFIG_Msk (0xc0UL)                /*!< SNC_IRQ_CONFIG (Bitfield-Mask: 0x03)                  */
-#define SNC_SNC_CTRL_REG_SNC_IRQ_EN_Pos   (5UL)                     /*!< SNC_IRQ_EN (Bit 5)                                    */
-#define SNC_SNC_CTRL_REG_SNC_IRQ_EN_Msk   (0x20UL)                  /*!< SNC_IRQ_EN (Bitfield-Mask: 0x01)                      */
-#define SNC_SNC_CTRL_REG_SNC_BRANCH_LOOP_INIT_Pos (4UL)             /*!< SNC_BRANCH_LOOP_INIT (Bit 4)                          */
-#define SNC_SNC_CTRL_REG_SNC_BRANCH_LOOP_INIT_Msk (0x10UL)          /*!< SNC_BRANCH_LOOP_INIT (Bitfield-Mask: 0x01)            */
-#define SNC_SNC_CTRL_REG_SNC_RESET_Pos    (3UL)                     /*!< SNC_RESET (Bit 3)                                     */
-#define SNC_SNC_CTRL_REG_SNC_RESET_Msk    (0x8UL)                   /*!< SNC_RESET (Bitfield-Mask: 0x01)                       */
-#define SNC_SNC_CTRL_REG_BUS_ERROR_DETECT_EN_Pos (2UL)              /*!< BUS_ERROR_DETECT_EN (Bit 2)                           */
-#define SNC_SNC_CTRL_REG_BUS_ERROR_DETECT_EN_Msk (0x4UL)            /*!< BUS_ERROR_DETECT_EN (Bitfield-Mask: 0x01)             */
-#define SNC_SNC_CTRL_REG_SNC_SW_CTRL_Pos  (1UL)                     /*!< SNC_SW_CTRL (Bit 1)                                   */
-#define SNC_SNC_CTRL_REG_SNC_SW_CTRL_Msk  (0x2UL)                   /*!< SNC_SW_CTRL (Bitfield-Mask: 0x01)                     */
-#define SNC_SNC_CTRL_REG_SNC_EN_Pos       (0UL)                     /*!< SNC_EN (Bit 0)                                        */
-#define SNC_SNC_CTRL_REG_SNC_EN_Msk       (0x1UL)                   /*!< SNC_EN (Bitfield-Mask: 0x01)                          */
-/* ===================================================  SNC_LP_TIMER_REG  ==================================================== */
-#define SNC_SNC_LP_TIMER_REG_LP_TIMER_Pos (0UL)                     /*!< LP_TIMER (Bit 0)                                      */
-#define SNC_SNC_LP_TIMER_REG_LP_TIMER_Msk (0xffUL)                  /*!< LP_TIMER (Bitfield-Mask: 0xff)                        */
-/* ======================================================  SNC_PC_REG  ======================================================= */
-#define SNC_SNC_PC_REG_PC_REG_Pos         (2UL)                     /*!< PC_REG (Bit 2)                                        */
-#define SNC_SNC_PC_REG_PC_REG_Msk         (0x7fffcUL)               /*!< PC_REG (Bitfield-Mask: 0x1ffff)                       */
-/* ======================================================  SNC_R1_REG  ======================================================= */
-#define SNC_SNC_R1_REG_R1_REG_Pos         (0UL)                     /*!< R1_REG (Bit 0)                                        */
-#define SNC_SNC_R1_REG_R1_REG_Msk         (0xffffffffUL)            /*!< R1_REG (Bitfield-Mask: 0xffffffff)                    */
-/* ======================================================  SNC_R2_REG  ======================================================= */
-#define SNC_SNC_R2_REG_R2_REG_Pos         (0UL)                     /*!< R2_REG (Bit 0)                                        */
-#define SNC_SNC_R2_REG_R2_REG_Msk         (0xffffffffUL)            /*!< R2_REG (Bitfield-Mask: 0xffffffff)                    */
-/* ====================================================  SNC_STATUS_REG  ===================================================== */
-#define SNC_SNC_STATUS_REG_SNC_PC_LOADED_Pos (6UL)                  /*!< SNC_PC_LOADED (Bit 6)                                 */
-#define SNC_SNC_STATUS_REG_SNC_PC_LOADED_Msk (0x40UL)               /*!< SNC_PC_LOADED (Bitfield-Mask: 0x01)                   */
-#define SNC_SNC_STATUS_REG_SNC_IS_STOPPED_Pos (5UL)                 /*!< SNC_IS_STOPPED (Bit 5)                                */
-#define SNC_SNC_STATUS_REG_SNC_IS_STOPPED_Msk (0x20UL)              /*!< SNC_IS_STOPPED (Bitfield-Mask: 0x01)                  */
-#define SNC_SNC_STATUS_REG_HARD_FAULT_STATUS_Pos (4UL)              /*!< HARD_FAULT_STATUS (Bit 4)                             */
-#define SNC_SNC_STATUS_REG_HARD_FAULT_STATUS_Msk (0x10UL)           /*!< HARD_FAULT_STATUS (Bitfield-Mask: 0x01)               */
-#define SNC_SNC_STATUS_REG_BUS_ERROR_STATUS_Pos (3UL)               /*!< BUS_ERROR_STATUS (Bit 3)                              */
-#define SNC_SNC_STATUS_REG_BUS_ERROR_STATUS_Msk (0x8UL)             /*!< BUS_ERROR_STATUS (Bitfield-Mask: 0x01)                */
-#define SNC_SNC_STATUS_REG_SNC_DONE_STATUS_Pos (2UL)                /*!< SNC_DONE_STATUS (Bit 2)                               */
-#define SNC_SNC_STATUS_REG_SNC_DONE_STATUS_Msk (0x4UL)              /*!< SNC_DONE_STATUS (Bitfield-Mask: 0x01)                 */
-#define SNC_SNC_STATUS_REG_GR_FLAG_Pos    (1UL)                     /*!< GR_FLAG (Bit 1)                                       */
-#define SNC_SNC_STATUS_REG_GR_FLAG_Msk    (0x2UL)                   /*!< GR_FLAG (Bitfield-Mask: 0x01)                         */
-#define SNC_SNC_STATUS_REG_EQ_FLAG_Pos    (0UL)                     /*!< EQ_FLAG (Bit 0)                                       */
-#define SNC_SNC_STATUS_REG_EQ_FLAG_Msk    (0x1UL)                   /*!< EQ_FLAG (Bitfield-Mask: 0x01)                         */
-/* =====================================================  SNC_TMP1_REG  ====================================================== */
-#define SNC_SNC_TMP1_REG_TMP1_REG_Pos     (0UL)                     /*!< TMP1_REG (Bit 0)                                      */
-#define SNC_SNC_TMP1_REG_TMP1_REG_Msk     (0xffffffffUL)            /*!< TMP1_REG (Bitfield-Mask: 0xffffffff)                  */
-/* =====================================================  SNC_TMP2_REG  ====================================================== */
-#define SNC_SNC_TMP2_REG_TMP2_REG_Pos     (0UL)                     /*!< TMP2_REG (Bit 0)                                      */
-#define SNC_SNC_TMP2_REG_TMP2_REG_Msk     (0xffffffffUL)            /*!< TMP2_REG (Bitfield-Mask: 0xffffffff)                  */
-
-
-/* =========================================================================================================================== */
-/* ================                                            SPI                                            ================ */
-/* =========================================================================================================================== */
-
-/* ===================================================  SPI_CLEAR_INT_REG  =================================================== */
-#define SPI_SPI_CLEAR_INT_REG_SPI_CLEAR_INT_Pos (0UL)               /*!< SPI_CLEAR_INT (Bit 0)                                 */
-#define SPI_SPI_CLEAR_INT_REG_SPI_CLEAR_INT_Msk (0xffffffffUL)      /*!< SPI_CLEAR_INT (Bitfield-Mask: 0xffffffff)             */
-/* =====================================================  SPI_CTRL_REG  ====================================================== */
-#define SPI_SPI_CTRL_REG_SPI_TX_FIFO_NOTFULL_MASK_Pos (25UL)        /*!< SPI_TX_FIFO_NOTFULL_MASK (Bit 25)                     */
-#define SPI_SPI_CTRL_REG_SPI_TX_FIFO_NOTFULL_MASK_Msk (0x2000000UL) /*!< SPI_TX_FIFO_NOTFULL_MASK (Bitfield-Mask: 0x01)        */
-#define SPI_SPI_CTRL_REG_SPI_DMA_TXREQ_MODE_Pos (24UL)              /*!< SPI_DMA_TXREQ_MODE (Bit 24)                           */
-#define SPI_SPI_CTRL_REG_SPI_DMA_TXREQ_MODE_Msk (0x1000000UL)       /*!< SPI_DMA_TXREQ_MODE (Bitfield-Mask: 0x01)              */
-#define SPI_SPI_CTRL_REG_SPI_TX_FIFO_EMPTY_Pos (23UL)               /*!< SPI_TX_FIFO_EMPTY (Bit 23)                            */
-#define SPI_SPI_CTRL_REG_SPI_TX_FIFO_EMPTY_Msk (0x800000UL)         /*!< SPI_TX_FIFO_EMPTY (Bitfield-Mask: 0x01)               */
-#define SPI_SPI_CTRL_REG_SPI_RX_FIFO_FULL_Pos (22UL)                /*!< SPI_RX_FIFO_FULL (Bit 22)                             */
-#define SPI_SPI_CTRL_REG_SPI_RX_FIFO_FULL_Msk (0x400000UL)          /*!< SPI_RX_FIFO_FULL (Bitfield-Mask: 0x01)                */
-#define SPI_SPI_CTRL_REG_SPI_RX_FIFO_EMPTY_Pos (21UL)               /*!< SPI_RX_FIFO_EMPTY (Bit 21)                            */
-#define SPI_SPI_CTRL_REG_SPI_RX_FIFO_EMPTY_Msk (0x200000UL)         /*!< SPI_RX_FIFO_EMPTY (Bitfield-Mask: 0x01)               */
-#define SPI_SPI_CTRL_REG_SPI_9BIT_VAL_Pos (20UL)                    /*!< SPI_9BIT_VAL (Bit 20)                                 */
-#define SPI_SPI_CTRL_REG_SPI_9BIT_VAL_Msk (0x100000UL)              /*!< SPI_9BIT_VAL (Bitfield-Mask: 0x01)                    */
-#define SPI_SPI_CTRL_REG_SPI_BUSY_Pos     (19UL)                    /*!< SPI_BUSY (Bit 19)                                     */
-#define SPI_SPI_CTRL_REG_SPI_BUSY_Msk     (0x80000UL)               /*!< SPI_BUSY (Bitfield-Mask: 0x01)                        */
-#define SPI_SPI_CTRL_REG_SPI_PRIORITY_Pos (18UL)                    /*!< SPI_PRIORITY (Bit 18)                                 */
-#define SPI_SPI_CTRL_REG_SPI_PRIORITY_Msk (0x40000UL)               /*!< SPI_PRIORITY (Bitfield-Mask: 0x01)                    */
-#define SPI_SPI_CTRL_REG_SPI_FIFO_MODE_Pos (16UL)                   /*!< SPI_FIFO_MODE (Bit 16)                                */
-#define SPI_SPI_CTRL_REG_SPI_FIFO_MODE_Msk (0x30000UL)              /*!< SPI_FIFO_MODE (Bitfield-Mask: 0x03)                   */
-#define SPI_SPI_CTRL_REG_SPI_EN_CTRL_Pos  (15UL)                    /*!< SPI_EN_CTRL (Bit 15)                                  */
-#define SPI_SPI_CTRL_REG_SPI_EN_CTRL_Msk  (0x8000UL)                /*!< SPI_EN_CTRL (Bitfield-Mask: 0x01)                     */
-#define SPI_SPI_CTRL_REG_SPI_MINT_Pos     (14UL)                    /*!< SPI_MINT (Bit 14)                                     */
-#define SPI_SPI_CTRL_REG_SPI_MINT_Msk     (0x4000UL)                /*!< SPI_MINT (Bitfield-Mask: 0x01)                        */
-#define SPI_SPI_CTRL_REG_SPI_INT_BIT_Pos  (13UL)                    /*!< SPI_INT_BIT (Bit 13)                                  */
-#define SPI_SPI_CTRL_REG_SPI_INT_BIT_Msk  (0x2000UL)                /*!< SPI_INT_BIT (Bitfield-Mask: 0x01)                     */
-#define SPI_SPI_CTRL_REG_SPI_DI_Pos       (12UL)                    /*!< SPI_DI (Bit 12)                                       */
-#define SPI_SPI_CTRL_REG_SPI_DI_Msk       (0x1000UL)                /*!< SPI_DI (Bitfield-Mask: 0x01)                          */
-#define SPI_SPI_CTRL_REG_SPI_TXH_Pos      (11UL)                    /*!< SPI_TXH (Bit 11)                                      */
-#define SPI_SPI_CTRL_REG_SPI_TXH_Msk      (0x800UL)                 /*!< SPI_TXH (Bitfield-Mask: 0x01)                         */
-#define SPI_SPI_CTRL_REG_SPI_FORCE_DO_Pos (10UL)                    /*!< SPI_FORCE_DO (Bit 10)                                 */
-#define SPI_SPI_CTRL_REG_SPI_FORCE_DO_Msk (0x400UL)                 /*!< SPI_FORCE_DO (Bitfield-Mask: 0x01)                    */
-#define SPI_SPI_CTRL_REG_SPI_WORD_Pos     (8UL)                     /*!< SPI_WORD (Bit 8)                                      */
-#define SPI_SPI_CTRL_REG_SPI_WORD_Msk     (0x300UL)                 /*!< SPI_WORD (Bitfield-Mask: 0x03)                        */
-#define SPI_SPI_CTRL_REG_SPI_RST_Pos      (7UL)                     /*!< SPI_RST (Bit 7)                                       */
-#define SPI_SPI_CTRL_REG_SPI_RST_Msk      (0x80UL)                  /*!< SPI_RST (Bitfield-Mask: 0x01)                         */
-#define SPI_SPI_CTRL_REG_SPI_SMN_Pos      (6UL)                     /*!< SPI_SMN (Bit 6)                                       */
-#define SPI_SPI_CTRL_REG_SPI_SMN_Msk      (0x40UL)                  /*!< SPI_SMN (Bitfield-Mask: 0x01)                         */
-#define SPI_SPI_CTRL_REG_SPI_DO_Pos       (5UL)                     /*!< SPI_DO (Bit 5)                                        */
-#define SPI_SPI_CTRL_REG_SPI_DO_Msk       (0x20UL)                  /*!< SPI_DO (Bitfield-Mask: 0x01)                          */
-#define SPI_SPI_CTRL_REG_SPI_CLK_Pos      (3UL)                     /*!< SPI_CLK (Bit 3)                                       */
-#define SPI_SPI_CTRL_REG_SPI_CLK_Msk      (0x18UL)                  /*!< SPI_CLK (Bitfield-Mask: 0x03)                         */
-#define SPI_SPI_CTRL_REG_SPI_POL_Pos      (2UL)                     /*!< SPI_POL (Bit 2)                                       */
-#define SPI_SPI_CTRL_REG_SPI_POL_Msk      (0x4UL)                   /*!< SPI_POL (Bitfield-Mask: 0x01)                         */
-#define SPI_SPI_CTRL_REG_SPI_PHA_Pos      (1UL)                     /*!< SPI_PHA (Bit 1)                                       */
-#define SPI_SPI_CTRL_REG_SPI_PHA_Msk      (0x2UL)                   /*!< SPI_PHA (Bitfield-Mask: 0x01)                         */
-#define SPI_SPI_CTRL_REG_SPI_ON_Pos       (0UL)                     /*!< SPI_ON (Bit 0)                                        */
-#define SPI_SPI_CTRL_REG_SPI_ON_Msk       (0x1UL)                   /*!< SPI_ON (Bitfield-Mask: 0x01)                          */
-/* =====================================================  SPI_RX_TX_REG  ===================================================== */
-#define SPI_SPI_RX_TX_REG_SPI_DATA_Pos    (0UL)                     /*!< SPI_DATA (Bit 0)                                      */
-#define SPI_SPI_RX_TX_REG_SPI_DATA_Msk    (0xffffffffUL)            /*!< SPI_DATA (Bitfield-Mask: 0xffffffff)                  */
-
-
-/* =========================================================================================================================== */
-/* ================                                           SPI2                                            ================ */
-/* =========================================================================================================================== */
-
-/* ==================================================  SPI2_CLEAR_INT_REG  =================================================== */
-#define SPI2_SPI2_CLEAR_INT_REG_SPI_CLEAR_INT_Pos (0UL)             /*!< SPI_CLEAR_INT (Bit 0)                                 */
-#define SPI2_SPI2_CLEAR_INT_REG_SPI_CLEAR_INT_Msk (0xffffffffUL)    /*!< SPI_CLEAR_INT (Bitfield-Mask: 0xffffffff)             */
-/* =====================================================  SPI2_CTRL_REG  ===================================================== */
-#define SPI2_SPI2_CTRL_REG_SPI_TX_FIFO_NOTFULL_MASK_Pos (25UL)      /*!< SPI_TX_FIFO_NOTFULL_MASK (Bit 25)                     */
-#define SPI2_SPI2_CTRL_REG_SPI_TX_FIFO_NOTFULL_MASK_Msk (0x2000000UL) /*!< SPI_TX_FIFO_NOTFULL_MASK (Bitfield-Mask: 0x01)      */
-#define SPI2_SPI2_CTRL_REG_SPI_DMA_TXREQ_MODE_Pos (24UL)            /*!< SPI_DMA_TXREQ_MODE (Bit 24)                           */
-#define SPI2_SPI2_CTRL_REG_SPI_DMA_TXREQ_MODE_Msk (0x1000000UL)     /*!< SPI_DMA_TXREQ_MODE (Bitfield-Mask: 0x01)              */
-#define SPI2_SPI2_CTRL_REG_SPI_TX_FIFO_EMPTY_Pos (23UL)             /*!< SPI_TX_FIFO_EMPTY (Bit 23)                            */
-#define SPI2_SPI2_CTRL_REG_SPI_TX_FIFO_EMPTY_Msk (0x800000UL)       /*!< SPI_TX_FIFO_EMPTY (Bitfield-Mask: 0x01)               */
-#define SPI2_SPI2_CTRL_REG_SPI_RX_FIFO_FULL_Pos (22UL)              /*!< SPI_RX_FIFO_FULL (Bit 22)                             */
-#define SPI2_SPI2_CTRL_REG_SPI_RX_FIFO_FULL_Msk (0x400000UL)        /*!< SPI_RX_FIFO_FULL (Bitfield-Mask: 0x01)                */
-#define SPI2_SPI2_CTRL_REG_SPI_RX_FIFO_EMPTY_Pos (21UL)             /*!< SPI_RX_FIFO_EMPTY (Bit 21)                            */
-#define SPI2_SPI2_CTRL_REG_SPI_RX_FIFO_EMPTY_Msk (0x200000UL)       /*!< SPI_RX_FIFO_EMPTY (Bitfield-Mask: 0x01)               */
-#define SPI2_SPI2_CTRL_REG_SPI_9BIT_VAL_Pos (20UL)                  /*!< SPI_9BIT_VAL (Bit 20)                                 */
-#define SPI2_SPI2_CTRL_REG_SPI_9BIT_VAL_Msk (0x100000UL)            /*!< SPI_9BIT_VAL (Bitfield-Mask: 0x01)                    */
-#define SPI2_SPI2_CTRL_REG_SPI_BUSY_Pos   (19UL)                    /*!< SPI_BUSY (Bit 19)                                     */
-#define SPI2_SPI2_CTRL_REG_SPI_BUSY_Msk   (0x80000UL)               /*!< SPI_BUSY (Bitfield-Mask: 0x01)                        */
-#define SPI2_SPI2_CTRL_REG_SPI_PRIORITY_Pos (18UL)                  /*!< SPI_PRIORITY (Bit 18)                                 */
-#define SPI2_SPI2_CTRL_REG_SPI_PRIORITY_Msk (0x40000UL)             /*!< SPI_PRIORITY (Bitfield-Mask: 0x01)                    */
-#define SPI2_SPI2_CTRL_REG_SPI_FIFO_MODE_Pos (16UL)                 /*!< SPI_FIFO_MODE (Bit 16)                                */
-#define SPI2_SPI2_CTRL_REG_SPI_FIFO_MODE_Msk (0x30000UL)            /*!< SPI_FIFO_MODE (Bitfield-Mask: 0x03)                   */
-#define SPI2_SPI2_CTRL_REG_SPI_EN_CTRL_Pos (15UL)                   /*!< SPI_EN_CTRL (Bit 15)                                  */
-#define SPI2_SPI2_CTRL_REG_SPI_EN_CTRL_Msk (0x8000UL)               /*!< SPI_EN_CTRL (Bitfield-Mask: 0x01)                     */
-#define SPI2_SPI2_CTRL_REG_SPI_MINT_Pos   (14UL)                    /*!< SPI_MINT (Bit 14)                                     */
-#define SPI2_SPI2_CTRL_REG_SPI_MINT_Msk   (0x4000UL)                /*!< SPI_MINT (Bitfield-Mask: 0x01)                        */
-#define SPI2_SPI2_CTRL_REG_SPI_INT_BIT_Pos (13UL)                   /*!< SPI_INT_BIT (Bit 13)                                  */
-#define SPI2_SPI2_CTRL_REG_SPI_INT_BIT_Msk (0x2000UL)               /*!< SPI_INT_BIT (Bitfield-Mask: 0x01)                     */
-#define SPI2_SPI2_CTRL_REG_SPI_DI_Pos     (12UL)                    /*!< SPI_DI (Bit 12)                                       */
-#define SPI2_SPI2_CTRL_REG_SPI_DI_Msk     (0x1000UL)                /*!< SPI_DI (Bitfield-Mask: 0x01)                          */
-#define SPI2_SPI2_CTRL_REG_SPI_TXH_Pos    (11UL)                    /*!< SPI_TXH (Bit 11)                                      */
-#define SPI2_SPI2_CTRL_REG_SPI_TXH_Msk    (0x800UL)                 /*!< SPI_TXH (Bitfield-Mask: 0x01)                         */
-#define SPI2_SPI2_CTRL_REG_SPI_FORCE_DO_Pos (10UL)                  /*!< SPI_FORCE_DO (Bit 10)                                 */
-#define SPI2_SPI2_CTRL_REG_SPI_FORCE_DO_Msk (0x400UL)               /*!< SPI_FORCE_DO (Bitfield-Mask: 0x01)                    */
-#define SPI2_SPI2_CTRL_REG_SPI_WORD_Pos   (8UL)                     /*!< SPI_WORD (Bit 8)                                      */
-#define SPI2_SPI2_CTRL_REG_SPI_WORD_Msk   (0x300UL)                 /*!< SPI_WORD (Bitfield-Mask: 0x03)                        */
-#define SPI2_SPI2_CTRL_REG_SPI_RST_Pos    (7UL)                     /*!< SPI_RST (Bit 7)                                       */
-#define SPI2_SPI2_CTRL_REG_SPI_RST_Msk    (0x80UL)                  /*!< SPI_RST (Bitfield-Mask: 0x01)                         */
-#define SPI2_SPI2_CTRL_REG_SPI_SMN_Pos    (6UL)                     /*!< SPI_SMN (Bit 6)                                       */
-#define SPI2_SPI2_CTRL_REG_SPI_SMN_Msk    (0x40UL)                  /*!< SPI_SMN (Bitfield-Mask: 0x01)                         */
-#define SPI2_SPI2_CTRL_REG_SPI_DO_Pos     (5UL)                     /*!< SPI_DO (Bit 5)                                        */
-#define SPI2_SPI2_CTRL_REG_SPI_DO_Msk     (0x20UL)                  /*!< SPI_DO (Bitfield-Mask: 0x01)                          */
-#define SPI2_SPI2_CTRL_REG_SPI_CLK_Pos    (3UL)                     /*!< SPI_CLK (Bit 3)                                       */
-#define SPI2_SPI2_CTRL_REG_SPI_CLK_Msk    (0x18UL)                  /*!< SPI_CLK (Bitfield-Mask: 0x03)                         */
-#define SPI2_SPI2_CTRL_REG_SPI_POL_Pos    (2UL)                     /*!< SPI_POL (Bit 2)                                       */
-#define SPI2_SPI2_CTRL_REG_SPI_POL_Msk    (0x4UL)                   /*!< SPI_POL (Bitfield-Mask: 0x01)                         */
-#define SPI2_SPI2_CTRL_REG_SPI_PHA_Pos    (1UL)                     /*!< SPI_PHA (Bit 1)                                       */
-#define SPI2_SPI2_CTRL_REG_SPI_PHA_Msk    (0x2UL)                   /*!< SPI_PHA (Bitfield-Mask: 0x01)                         */
-#define SPI2_SPI2_CTRL_REG_SPI_ON_Pos     (0UL)                     /*!< SPI_ON (Bit 0)                                        */
-#define SPI2_SPI2_CTRL_REG_SPI_ON_Msk     (0x1UL)                   /*!< SPI_ON (Bitfield-Mask: 0x01)                          */
-/* ====================================================  SPI2_RX_TX_REG  ===================================================== */
-#define SPI2_SPI2_RX_TX_REG_SPI_DATA_Pos  (0UL)                     /*!< SPI_DATA (Bit 0)                                      */
-#define SPI2_SPI2_RX_TX_REG_SPI_DATA_Msk  (0xffffffffUL)            /*!< SPI_DATA (Bitfield-Mask: 0xffffffff)                  */
-
-
-/* =========================================================================================================================== */
-/* ================                                         SYS_WDOG                                          ================ */
-/* =========================================================================================================================== */
-
-/* ===================================================  WATCHDOG_CTRL_REG  =================================================== */
-#define SYS_WDOG_WATCHDOG_CTRL_REG_WRITE_BUSY_Pos (3UL)             /*!< WRITE_BUSY (Bit 3)                                    */
-#define SYS_WDOG_WATCHDOG_CTRL_REG_WRITE_BUSY_Msk (0x8UL)           /*!< WRITE_BUSY (Bitfield-Mask: 0x01)                      */
-#define SYS_WDOG_WATCHDOG_CTRL_REG_WDOG_FREEZE_EN_Pos (2UL)         /*!< WDOG_FREEZE_EN (Bit 2)                                */
-#define SYS_WDOG_WATCHDOG_CTRL_REG_WDOG_FREEZE_EN_Msk (0x4UL)       /*!< WDOG_FREEZE_EN (Bitfield-Mask: 0x01)                  */
-#define SYS_WDOG_WATCHDOG_CTRL_REG_NMI_RST_Pos (0UL)                /*!< NMI_RST (Bit 0)                                       */
-#define SYS_WDOG_WATCHDOG_CTRL_REG_NMI_RST_Msk (0x1UL)              /*!< NMI_RST (Bitfield-Mask: 0x01)                         */
-/* =====================================================  WATCHDOG_REG  ====================================================== */
-#define SYS_WDOG_WATCHDOG_REG_WDOG_WEN_Pos (14UL)                   /*!< WDOG_WEN (Bit 14)                                     */
-#define SYS_WDOG_WATCHDOG_REG_WDOG_WEN_Msk (0xffffc000UL)           /*!< WDOG_WEN (Bitfield-Mask: 0x3ffff)                     */
-#define SYS_WDOG_WATCHDOG_REG_WDOG_VAL_NEG_Pos (13UL)               /*!< WDOG_VAL_NEG (Bit 13)                                 */
-#define SYS_WDOG_WATCHDOG_REG_WDOG_VAL_NEG_Msk (0x2000UL)           /*!< WDOG_VAL_NEG (Bitfield-Mask: 0x01)                    */
-#define SYS_WDOG_WATCHDOG_REG_WDOG_VAL_Pos (0UL)                    /*!< WDOG_VAL (Bit 0)                                      */
-#define SYS_WDOG_WATCHDOG_REG_WDOG_VAL_Msk (0x1fffUL)               /*!< WDOG_VAL (Bitfield-Mask: 0x1fff)                      */
-
-
-/* =========================================================================================================================== */
-/* ================                                           TIMER                                           ================ */
-/* =========================================================================================================================== */
-
-/* ================================================  TIMER_CAPTURE_GPIO1_REG  ================================================ */
-#define TIMER_TIMER_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos (0UL)   /*!< TIM_CAPTURE_GPIO1 (Bit 0)                             */
-#define TIMER_TIMER_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO1 (Bitfield-Mask: 0xffffff)      */
-/* ================================================  TIMER_CAPTURE_GPIO2_REG  ================================================ */
-#define TIMER_TIMER_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos (0UL)   /*!< TIM_CAPTURE_GPIO2 (Bit 0)                             */
-#define TIMER_TIMER_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO2 (Bitfield-Mask: 0xffffff)      */
-/* ================================================  TIMER_CAPTURE_GPIO3_REG  ================================================ */
-#define TIMER_TIMER_CAPTURE_GPIO3_REG_TIM_CAPTURE_GPIO3_Pos (0UL)   /*!< TIM_CAPTURE_GPIO3 (Bit 0)                             */
-#define TIMER_TIMER_CAPTURE_GPIO3_REG_TIM_CAPTURE_GPIO3_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO3 (Bitfield-Mask: 0xffffff)      */
-/* ================================================  TIMER_CAPTURE_GPIO4_REG  ================================================ */
-#define TIMER_TIMER_CAPTURE_GPIO4_REG_TIM_CAPTURE_GPIO4_Pos (0UL)   /*!< TIM_CAPTURE_GPIO4 (Bit 0)                             */
-#define TIMER_TIMER_CAPTURE_GPIO4_REG_TIM_CAPTURE_GPIO4_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO4 (Bitfield-Mask: 0xffffff)      */
-/* ==============================================  TIMER_CLEAR_GPIO_EVENT_REG  =============================================== */
-#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO4_EVENT_Pos (3UL) /*!< TIM_CLEAR_GPIO4_EVENT (Bit 3)                    */
-#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO4_EVENT_Msk (0x8UL) /*!< TIM_CLEAR_GPIO4_EVENT (Bitfield-Mask: 0x01)    */
-#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO3_EVENT_Pos (2UL) /*!< TIM_CLEAR_GPIO3_EVENT (Bit 2)                    */
-#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO3_EVENT_Msk (0x4UL) /*!< TIM_CLEAR_GPIO3_EVENT (Bitfield-Mask: 0x01)    */
-#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO2_EVENT_Pos (1UL) /*!< TIM_CLEAR_GPIO2_EVENT (Bit 1)                    */
-#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO2_EVENT_Msk (0x2UL) /*!< TIM_CLEAR_GPIO2_EVENT (Bitfield-Mask: 0x01)    */
-#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO1_EVENT_Pos (0UL) /*!< TIM_CLEAR_GPIO1_EVENT (Bit 0)                    */
-#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO1_EVENT_Msk (0x1UL) /*!< TIM_CLEAR_GPIO1_EVENT (Bitfield-Mask: 0x01)    */
-/* ==================================================  TIMER_CLEAR_IRQ_REG  ================================================== */
-#define TIMER_TIMER_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL)           /*!< TIM_CLEAR_IRQ (Bit 0)                                 */
-#define TIMER_TIMER_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL)         /*!< TIM_CLEAR_IRQ (Bitfield-Mask: 0x01)                   */
-/* ====================================================  TIMER_CTRL_REG  ===================================================== */
-#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO4_IRQ_EN_Pos (14UL)        /*!< TIM_CAP_GPIO4_IRQ_EN (Bit 14)                         */
-#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO4_IRQ_EN_Msk (0x4000UL)    /*!< TIM_CAP_GPIO4_IRQ_EN (Bitfield-Mask: 0x01)            */
-#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO3_IRQ_EN_Pos (13UL)        /*!< TIM_CAP_GPIO3_IRQ_EN (Bit 13)                         */
-#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO3_IRQ_EN_Msk (0x2000UL)    /*!< TIM_CAP_GPIO3_IRQ_EN (Bitfield-Mask: 0x01)            */
-#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO2_IRQ_EN_Pos (12UL)        /*!< TIM_CAP_GPIO2_IRQ_EN (Bit 12)                         */
-#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO2_IRQ_EN_Msk (0x1000UL)    /*!< TIM_CAP_GPIO2_IRQ_EN (Bitfield-Mask: 0x01)            */
-#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO1_IRQ_EN_Pos (11UL)        /*!< TIM_CAP_GPIO1_IRQ_EN (Bit 11)                         */
-#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO1_IRQ_EN_Msk (0x800UL)     /*!< TIM_CAP_GPIO1_IRQ_EN (Bitfield-Mask: 0x01)            */
-#define TIMER_TIMER_CTRL_REG_TIM_IN4_EVENT_FALL_EN_Pos (10UL)       /*!< TIM_IN4_EVENT_FALL_EN (Bit 10)                        */
-#define TIMER_TIMER_CTRL_REG_TIM_IN4_EVENT_FALL_EN_Msk (0x400UL)    /*!< TIM_IN4_EVENT_FALL_EN (Bitfield-Mask: 0x01)           */
-#define TIMER_TIMER_CTRL_REG_TIM_IN3_EVENT_FALL_EN_Pos (9UL)        /*!< TIM_IN3_EVENT_FALL_EN (Bit 9)                         */
-#define TIMER_TIMER_CTRL_REG_TIM_IN3_EVENT_FALL_EN_Msk (0x200UL)    /*!< TIM_IN3_EVENT_FALL_EN (Bitfield-Mask: 0x01)           */
-#define TIMER_TIMER_CTRL_REG_TIM_CLK_EN_Pos (8UL)                   /*!< TIM_CLK_EN (Bit 8)                                    */
-#define TIMER_TIMER_CTRL_REG_TIM_CLK_EN_Msk (0x100UL)               /*!< TIM_CLK_EN (Bitfield-Mask: 0x01)                      */
-#define TIMER_TIMER_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL)               /*!< TIM_SYS_CLK_EN (Bit 7)                                */
-#define TIMER_TIMER_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL)            /*!< TIM_SYS_CLK_EN (Bitfield-Mask: 0x01)                  */
-#define TIMER_TIMER_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL)         /*!< TIM_FREE_RUN_MODE_EN (Bit 6)                          */
-#define TIMER_TIMER_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL)      /*!< TIM_FREE_RUN_MODE_EN (Bitfield-Mask: 0x01)            */
-#define TIMER_TIMER_CTRL_REG_TIM_IRQ_EN_Pos (5UL)                   /*!< TIM_IRQ_EN (Bit 5)                                    */
-#define TIMER_TIMER_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL)                /*!< TIM_IRQ_EN (Bitfield-Mask: 0x01)                      */
-#define TIMER_TIMER_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL)        /*!< TIM_IN2_EVENT_FALL_EN (Bit 4)                         */
-#define TIMER_TIMER_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL)     /*!< TIM_IN2_EVENT_FALL_EN (Bitfield-Mask: 0x01)           */
-#define TIMER_TIMER_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL)        /*!< TIM_IN1_EVENT_FALL_EN (Bit 3)                         */
-#define TIMER_TIMER_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL)      /*!< TIM_IN1_EVENT_FALL_EN (Bitfield-Mask: 0x01)           */
-#define TIMER_TIMER_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL)            /*!< TIM_COUNT_DOWN_EN (Bit 2)                             */
-#define TIMER_TIMER_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL)          /*!< TIM_COUNT_DOWN_EN (Bitfield-Mask: 0x01)               */
-#define TIMER_TIMER_CTRL_REG_TIM_ONESHOT_MODE_EN_Pos (1UL)          /*!< TIM_ONESHOT_MODE_EN (Bit 1)                           */
-#define TIMER_TIMER_CTRL_REG_TIM_ONESHOT_MODE_EN_Msk (0x2UL)        /*!< TIM_ONESHOT_MODE_EN (Bitfield-Mask: 0x01)             */
-#define TIMER_TIMER_CTRL_REG_TIM_EN_Pos   (0UL)                     /*!< TIM_EN (Bit 0)                                        */
-#define TIMER_TIMER_CTRL_REG_TIM_EN_Msk   (0x1UL)                   /*!< TIM_EN (Bitfield-Mask: 0x01)                          */
-/* =================================================  TIMER_GPIO1_CONF_REG  ================================================== */
-#define TIMER_TIMER_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL)         /*!< TIM_GPIO1_CONF (Bit 0)                                */
-#define TIMER_TIMER_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL)      /*!< TIM_GPIO1_CONF (Bitfield-Mask: 0x3f)                  */
-/* =================================================  TIMER_GPIO2_CONF_REG  ================================================== */
-#define TIMER_TIMER_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL)         /*!< TIM_GPIO2_CONF (Bit 0)                                */
-#define TIMER_TIMER_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL)      /*!< TIM_GPIO2_CONF (Bitfield-Mask: 0x3f)                  */
-/* =================================================  TIMER_GPIO3_CONF_REG  ================================================== */
-#define TIMER_TIMER_GPIO3_CONF_REG_TIM_GPIO3_CONF_Pos (0UL)         /*!< TIM_GPIO3_CONF (Bit 0)                                */
-#define TIMER_TIMER_GPIO3_CONF_REG_TIM_GPIO3_CONF_Msk (0x3fUL)      /*!< TIM_GPIO3_CONF (Bitfield-Mask: 0x3f)                  */
-/* =================================================  TIMER_GPIO4_CONF_REG  ================================================== */
-#define TIMER_TIMER_GPIO4_CONF_REG_TIM_GPIO4_CONF_Pos (0UL)         /*!< TIM_GPIO4_CONF (Bit 0)                                */
-#define TIMER_TIMER_GPIO4_CONF_REG_TIM_GPIO4_CONF_Msk (0x3fUL)      /*!< TIM_GPIO4_CONF (Bitfield-Mask: 0x3f)                  */
-/* ==================================================  TIMER_PRESCALER_REG  ================================================== */
-#define TIMER_TIMER_PRESCALER_REG_TIM_PRESCALER_Pos (0UL)           /*!< TIM_PRESCALER (Bit 0)                                 */
-#define TIMER_TIMER_PRESCALER_REG_TIM_PRESCALER_Msk (0x1fUL)        /*!< TIM_PRESCALER (Bitfield-Mask: 0x1f)                   */
-/* ================================================  TIMER_PRESCALER_VAL_REG  ================================================ */
-#define TIMER_TIMER_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL)   /*!< TIM_PRESCALER_VAL (Bit 0)                             */
-#define TIMER_TIMER_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL) /*!< TIM_PRESCALER_VAL (Bitfield-Mask: 0x1f)              */
-/* ===================================================  TIMER_PWM_DC_REG  ==================================================== */
-#define TIMER_TIMER_PWM_DC_REG_TIM_PWM_DC_Pos (0UL)                 /*!< TIM_PWM_DC (Bit 0)                                    */
-#define TIMER_TIMER_PWM_DC_REG_TIM_PWM_DC_Msk (0xffffUL)            /*!< TIM_PWM_DC (Bitfield-Mask: 0xffff)                    */
-/* ==================================================  TIMER_PWM_FREQ_REG  =================================================== */
-#define TIMER_TIMER_PWM_FREQ_REG_TIM_PWM_FREQ_Pos (0UL)             /*!< TIM_PWM_FREQ (Bit 0)                                  */
-#define TIMER_TIMER_PWM_FREQ_REG_TIM_PWM_FREQ_Msk (0xffffUL)        /*!< TIM_PWM_FREQ (Bitfield-Mask: 0xffff)                  */
-/* ===================================================  TIMER_RELOAD_REG  ==================================================== */
-#define TIMER_TIMER_RELOAD_REG_TIM_RELOAD_Pos (0UL)                 /*!< TIM_RELOAD (Bit 0)                                    */
-#define TIMER_TIMER_RELOAD_REG_TIM_RELOAD_Msk (0xffffffUL)          /*!< TIM_RELOAD (Bitfield-Mask: 0xffffff)                  */
-/* ==================================================  TIMER_SHOTWIDTH_REG  ================================================== */
-#define TIMER_TIMER_SHOTWIDTH_REG_TIM_SHOTWIDTH_Pos (0UL)           /*!< TIM_SHOTWIDTH (Bit 0)                                 */
-#define TIMER_TIMER_SHOTWIDTH_REG_TIM_SHOTWIDTH_Msk (0xffffffUL)    /*!< TIM_SHOTWIDTH (Bitfield-Mask: 0xffffff)               */
-/* ===================================================  TIMER_STATUS_REG  ==================================================== */
-#define TIMER_TIMER_STATUS_REG_TIM_GPIO4_EVENT_PENDING_Pos (7UL)    /*!< TIM_GPIO4_EVENT_PENDING (Bit 7)                       */
-#define TIMER_TIMER_STATUS_REG_TIM_GPIO4_EVENT_PENDING_Msk (0x80UL) /*!< TIM_GPIO4_EVENT_PENDING (Bitfield-Mask: 0x01)         */
-#define TIMER_TIMER_STATUS_REG_TIM_GPIO3_EVENT_PENDING_Pos (6UL)    /*!< TIM_GPIO3_EVENT_PENDING (Bit 6)                       */
-#define TIMER_TIMER_STATUS_REG_TIM_GPIO3_EVENT_PENDING_Msk (0x40UL) /*!< TIM_GPIO3_EVENT_PENDING (Bitfield-Mask: 0x01)         */
-#define TIMER_TIMER_STATUS_REG_TIM_GPIO2_EVENT_PENDING_Pos (5UL)    /*!< TIM_GPIO2_EVENT_PENDING (Bit 5)                       */
-#define TIMER_TIMER_STATUS_REG_TIM_GPIO2_EVENT_PENDING_Msk (0x20UL) /*!< TIM_GPIO2_EVENT_PENDING (Bitfield-Mask: 0x01)         */
-#define TIMER_TIMER_STATUS_REG_TIM_GPIO1_EVENT_PENDING_Pos (4UL)    /*!< TIM_GPIO1_EVENT_PENDING (Bit 4)                       */
-#define TIMER_TIMER_STATUS_REG_TIM_GPIO1_EVENT_PENDING_Msk (0x10UL) /*!< TIM_GPIO1_EVENT_PENDING (Bitfield-Mask: 0x01)         */
-#define TIMER_TIMER_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL)          /*!< TIM_ONESHOT_PHASE (Bit 2)                             */
-#define TIMER_TIMER_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL)        /*!< TIM_ONESHOT_PHASE (Bitfield-Mask: 0x03)               */
-#define TIMER_TIMER_STATUS_REG_TIM_IN2_STATE_Pos (1UL)              /*!< TIM_IN2_STATE (Bit 1)                                 */
-#define TIMER_TIMER_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL)            /*!< TIM_IN2_STATE (Bitfield-Mask: 0x01)                   */
-#define TIMER_TIMER_STATUS_REG_TIM_IN1_STATE_Pos (0UL)              /*!< TIM_IN1_STATE (Bit 0)                                 */
-#define TIMER_TIMER_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL)            /*!< TIM_IN1_STATE (Bitfield-Mask: 0x01)                   */
-/* ==================================================  TIMER_TIMER_VAL_REG  ================================================== */
-#define TIMER_TIMER_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos (0UL)         /*!< TIM_TIMER_VALUE (Bit 0)                               */
-#define TIMER_TIMER_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk (0xffffffUL)  /*!< TIM_TIMER_VALUE (Bitfield-Mask: 0xffffff)             */
-
-
-/* =========================================================================================================================== */
-/* ================                                          TIMER2                                           ================ */
-/* =========================================================================================================================== */
-
-/* ===============================================  TIMER2_CAPTURE_GPIO1_REG  ================================================ */
-#define TIMER2_TIMER2_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos (0UL) /*!< TIM_CAPTURE_GPIO1 (Bit 0)                             */
-#define TIMER2_TIMER2_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO1 (Bitfield-Mask: 0xffffff)    */
-/* ===============================================  TIMER2_CAPTURE_GPIO2_REG  ================================================ */
-#define TIMER2_TIMER2_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos (0UL) /*!< TIM_CAPTURE_GPIO2 (Bit 0)                             */
-#define TIMER2_TIMER2_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO2 (Bitfield-Mask: 0xffffff)    */
-/* =================================================  TIMER2_CLEAR_IRQ_REG  ================================================== */
-#define TIMER2_TIMER2_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL)         /*!< TIM_CLEAR_IRQ (Bit 0)                                 */
-#define TIMER2_TIMER2_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL)       /*!< TIM_CLEAR_IRQ (Bitfield-Mask: 0x01)                   */
-/* ====================================================  TIMER2_CTRL_REG  ==================================================== */
-#define TIMER2_TIMER2_CTRL_REG_TIM_CLK_EN_Pos (8UL)                 /*!< TIM_CLK_EN (Bit 8)                                    */
-#define TIMER2_TIMER2_CTRL_REG_TIM_CLK_EN_Msk (0x100UL)             /*!< TIM_CLK_EN (Bitfield-Mask: 0x01)                      */
-#define TIMER2_TIMER2_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL)             /*!< TIM_SYS_CLK_EN (Bit 7)                                */
-#define TIMER2_TIMER2_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL)          /*!< TIM_SYS_CLK_EN (Bitfield-Mask: 0x01)                  */
-#define TIMER2_TIMER2_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL)       /*!< TIM_FREE_RUN_MODE_EN (Bit 6)                          */
-#define TIMER2_TIMER2_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL)    /*!< TIM_FREE_RUN_MODE_EN (Bitfield-Mask: 0x01)            */
-#define TIMER2_TIMER2_CTRL_REG_TIM_IRQ_EN_Pos (5UL)                 /*!< TIM_IRQ_EN (Bit 5)                                    */
-#define TIMER2_TIMER2_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL)              /*!< TIM_IRQ_EN (Bitfield-Mask: 0x01)                      */
-#define TIMER2_TIMER2_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL)      /*!< TIM_IN2_EVENT_FALL_EN (Bit 4)                         */
-#define TIMER2_TIMER2_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL)   /*!< TIM_IN2_EVENT_FALL_EN (Bitfield-Mask: 0x01)           */
-#define TIMER2_TIMER2_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL)      /*!< TIM_IN1_EVENT_FALL_EN (Bit 3)                         */
-#define TIMER2_TIMER2_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL)    /*!< TIM_IN1_EVENT_FALL_EN (Bitfield-Mask: 0x01)           */
-#define TIMER2_TIMER2_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL)          /*!< TIM_COUNT_DOWN_EN (Bit 2)                             */
-#define TIMER2_TIMER2_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL)        /*!< TIM_COUNT_DOWN_EN (Bitfield-Mask: 0x01)               */
-#define TIMER2_TIMER2_CTRL_REG_TIM_ONESHOT_MODE_EN_Pos (1UL)        /*!< TIM_ONESHOT_MODE_EN (Bit 1)                           */
-#define TIMER2_TIMER2_CTRL_REG_TIM_ONESHOT_MODE_EN_Msk (0x2UL)      /*!< TIM_ONESHOT_MODE_EN (Bitfield-Mask: 0x01)             */
-#define TIMER2_TIMER2_CTRL_REG_TIM_EN_Pos (0UL)                     /*!< TIM_EN (Bit 0)                                        */
-#define TIMER2_TIMER2_CTRL_REG_TIM_EN_Msk (0x1UL)                   /*!< TIM_EN (Bitfield-Mask: 0x01)                          */
-/* =================================================  TIMER2_GPIO1_CONF_REG  ================================================= */
-#define TIMER2_TIMER2_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL)       /*!< TIM_GPIO1_CONF (Bit 0)                                */
-#define TIMER2_TIMER2_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL)    /*!< TIM_GPIO1_CONF (Bitfield-Mask: 0x3f)                  */
-/* =================================================  TIMER2_GPIO2_CONF_REG  ================================================= */
-#define TIMER2_TIMER2_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL)       /*!< TIM_GPIO2_CONF (Bit 0)                                */
-#define TIMER2_TIMER2_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL)    /*!< TIM_GPIO2_CONF (Bitfield-Mask: 0x3f)                  */
-/* =================================================  TIMER2_PRESCALER_REG  ================================================== */
-#define TIMER2_TIMER2_PRESCALER_REG_TIM_PRESCALER_Pos (0UL)         /*!< TIM_PRESCALER (Bit 0)                                 */
-#define TIMER2_TIMER2_PRESCALER_REG_TIM_PRESCALER_Msk (0x1fUL)      /*!< TIM_PRESCALER (Bitfield-Mask: 0x1f)                   */
-/* ===============================================  TIMER2_PRESCALER_VAL_REG  ================================================ */
-#define TIMER2_TIMER2_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL) /*!< TIM_PRESCALER_VAL (Bit 0)                             */
-#define TIMER2_TIMER2_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL) /*!< TIM_PRESCALER_VAL (Bitfield-Mask: 0x1f)            */
-/* ===================================================  TIMER2_PWM_DC_REG  =================================================== */
-#define TIMER2_TIMER2_PWM_DC_REG_TIM_PWM_DC_Pos (0UL)               /*!< TIM_PWM_DC (Bit 0)                                    */
-#define TIMER2_TIMER2_PWM_DC_REG_TIM_PWM_DC_Msk (0xffffUL)          /*!< TIM_PWM_DC (Bitfield-Mask: 0xffff)                    */
-/* ==================================================  TIMER2_PWM_FREQ_REG  ================================================== */
-#define TIMER2_TIMER2_PWM_FREQ_REG_TIM_PWM_FREQ_Pos (0UL)           /*!< TIM_PWM_FREQ (Bit 0)                                  */
-#define TIMER2_TIMER2_PWM_FREQ_REG_TIM_PWM_FREQ_Msk (0xffffUL)      /*!< TIM_PWM_FREQ (Bitfield-Mask: 0xffff)                  */
-/* ===================================================  TIMER2_RELOAD_REG  =================================================== */
-#define TIMER2_TIMER2_RELOAD_REG_TIM_RELOAD_Pos (0UL)               /*!< TIM_RELOAD (Bit 0)                                    */
-#define TIMER2_TIMER2_RELOAD_REG_TIM_RELOAD_Msk (0xffffffUL)        /*!< TIM_RELOAD (Bitfield-Mask: 0xffffff)                  */
-/* =================================================  TIMER2_SHOTWIDTH_REG  ================================================== */
-#define TIMER2_TIMER2_SHOTWIDTH_REG_TIM_SHOTWIDTH_Pos (0UL)         /*!< TIM_SHOTWIDTH (Bit 0)                                 */
-#define TIMER2_TIMER2_SHOTWIDTH_REG_TIM_SHOTWIDTH_Msk (0xffffffUL)  /*!< TIM_SHOTWIDTH (Bitfield-Mask: 0xffffff)               */
-/* ===================================================  TIMER2_STATUS_REG  =================================================== */
-#define TIMER2_TIMER2_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL)        /*!< TIM_ONESHOT_PHASE (Bit 2)                             */
-#define TIMER2_TIMER2_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL)      /*!< TIM_ONESHOT_PHASE (Bitfield-Mask: 0x03)               */
-#define TIMER2_TIMER2_STATUS_REG_TIM_IN2_STATE_Pos (1UL)            /*!< TIM_IN2_STATE (Bit 1)                                 */
-#define TIMER2_TIMER2_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL)          /*!< TIM_IN2_STATE (Bitfield-Mask: 0x01)                   */
-#define TIMER2_TIMER2_STATUS_REG_TIM_IN1_STATE_Pos (0UL)            /*!< TIM_IN1_STATE (Bit 0)                                 */
-#define TIMER2_TIMER2_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL)          /*!< TIM_IN1_STATE (Bitfield-Mask: 0x01)                   */
-/* =================================================  TIMER2_TIMER_VAL_REG  ================================================== */
-#define TIMER2_TIMER2_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos (0UL)       /*!< TIM_TIMER_VALUE (Bit 0)                               */
-#define TIMER2_TIMER2_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk (0xffffffUL) /*!< TIM_TIMER_VALUE (Bitfield-Mask: 0xffffff)            */
-
-
-/* =========================================================================================================================== */
-/* ================                                          TIMER3                                           ================ */
-/* =========================================================================================================================== */
-
-/* ===============================================  TIMER3_CAPTURE_GPIO1_REG  ================================================ */
-#define TIMER3_TIMER3_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos (0UL) /*!< TIM_CAPTURE_GPIO1 (Bit 0)                             */
-#define TIMER3_TIMER3_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO1 (Bitfield-Mask: 0xffffff)    */
-/* ===============================================  TIMER3_CAPTURE_GPIO2_REG  ================================================ */
-#define TIMER3_TIMER3_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos (0UL) /*!< TIM_CAPTURE_GPIO2 (Bit 0)                             */
-#define TIMER3_TIMER3_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO2 (Bitfield-Mask: 0xffffff)    */
-/* =================================================  TIMER3_CLEAR_IRQ_REG  ================================================== */
-#define TIMER3_TIMER3_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL)         /*!< TIM_CLEAR_IRQ (Bit 0)                                 */
-#define TIMER3_TIMER3_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL)       /*!< TIM_CLEAR_IRQ (Bitfield-Mask: 0x01)                   */
-/* ====================================================  TIMER3_CTRL_REG  ==================================================== */
-#define TIMER3_TIMER3_CTRL_REG_TIM_CLK_EN_Pos (8UL)                 /*!< TIM_CLK_EN (Bit 8)                                    */
-#define TIMER3_TIMER3_CTRL_REG_TIM_CLK_EN_Msk (0x100UL)             /*!< TIM_CLK_EN (Bitfield-Mask: 0x01)                      */
-#define TIMER3_TIMER3_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL)             /*!< TIM_SYS_CLK_EN (Bit 7)                                */
-#define TIMER3_TIMER3_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL)          /*!< TIM_SYS_CLK_EN (Bitfield-Mask: 0x01)                  */
-#define TIMER3_TIMER3_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL)       /*!< TIM_FREE_RUN_MODE_EN (Bit 6)                          */
-#define TIMER3_TIMER3_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL)    /*!< TIM_FREE_RUN_MODE_EN (Bitfield-Mask: 0x01)            */
-#define TIMER3_TIMER3_CTRL_REG_TIM_IRQ_EN_Pos (5UL)                 /*!< TIM_IRQ_EN (Bit 5)                                    */
-#define TIMER3_TIMER3_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL)              /*!< TIM_IRQ_EN (Bitfield-Mask: 0x01)                      */
-#define TIMER3_TIMER3_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL)      /*!< TIM_IN2_EVENT_FALL_EN (Bit 4)                         */
-#define TIMER3_TIMER3_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL)   /*!< TIM_IN2_EVENT_FALL_EN (Bitfield-Mask: 0x01)           */
-#define TIMER3_TIMER3_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL)      /*!< TIM_IN1_EVENT_FALL_EN (Bit 3)                         */
-#define TIMER3_TIMER3_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL)    /*!< TIM_IN1_EVENT_FALL_EN (Bitfield-Mask: 0x01)           */
-#define TIMER3_TIMER3_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL)          /*!< TIM_COUNT_DOWN_EN (Bit 2)                             */
-#define TIMER3_TIMER3_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL)        /*!< TIM_COUNT_DOWN_EN (Bitfield-Mask: 0x01)               */
-#define TIMER3_TIMER3_CTRL_REG_TIM_EN_Pos (0UL)                     /*!< TIM_EN (Bit 0)                                        */
-#define TIMER3_TIMER3_CTRL_REG_TIM_EN_Msk (0x1UL)                   /*!< TIM_EN (Bitfield-Mask: 0x01)                          */
-/* =================================================  TIMER3_GPIO1_CONF_REG  ================================================= */
-#define TIMER3_TIMER3_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL)       /*!< TIM_GPIO1_CONF (Bit 0)                                */
-#define TIMER3_TIMER3_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL)    /*!< TIM_GPIO1_CONF (Bitfield-Mask: 0x3f)                  */
-/* =================================================  TIMER3_GPIO2_CONF_REG  ================================================= */
-#define TIMER3_TIMER3_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL)       /*!< TIM_GPIO2_CONF (Bit 0)                                */
-#define TIMER3_TIMER3_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL)    /*!< TIM_GPIO2_CONF (Bitfield-Mask: 0x3f)                  */
-/* =================================================  TIMER3_PRESCALER_REG  ================================================== */
-#define TIMER3_TIMER3_PRESCALER_REG_TIM_PRESCALER_Pos (0UL)         /*!< TIM_PRESCALER (Bit 0)                                 */
-#define TIMER3_TIMER3_PRESCALER_REG_TIM_PRESCALER_Msk (0x1fUL)      /*!< TIM_PRESCALER (Bitfield-Mask: 0x1f)                   */
-/* ===============================================  TIMER3_PRESCALER_VAL_REG  ================================================ */
-#define TIMER3_TIMER3_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL) /*!< TIM_PRESCALER_VAL (Bit 0)                             */
-#define TIMER3_TIMER3_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL) /*!< TIM_PRESCALER_VAL (Bitfield-Mask: 0x1f)            */
-/* ===================================================  TIMER3_PWM_DC_REG  =================================================== */
-#define TIMER3_TIMER3_PWM_DC_REG_TIM_PWM_DC_Pos (0UL)               /*!< TIM_PWM_DC (Bit 0)                                    */
-#define TIMER3_TIMER3_PWM_DC_REG_TIM_PWM_DC_Msk (0xffffUL)          /*!< TIM_PWM_DC (Bitfield-Mask: 0xffff)                    */
-/* ==================================================  TIMER3_PWM_FREQ_REG  ================================================== */
-#define TIMER3_TIMER3_PWM_FREQ_REG_TIM_PWM_FREQ_Pos (0UL)           /*!< TIM_PWM_FREQ (Bit 0)                                  */
-#define TIMER3_TIMER3_PWM_FREQ_REG_TIM_PWM_FREQ_Msk (0xffffUL)      /*!< TIM_PWM_FREQ (Bitfield-Mask: 0xffff)                  */
-/* ===================================================  TIMER3_RELOAD_REG  =================================================== */
-#define TIMER3_TIMER3_RELOAD_REG_TIM_RELOAD_Pos (0UL)               /*!< TIM_RELOAD (Bit 0)                                    */
-#define TIMER3_TIMER3_RELOAD_REG_TIM_RELOAD_Msk (0xffffffUL)        /*!< TIM_RELOAD (Bitfield-Mask: 0xffffff)                  */
-/* ===================================================  TIMER3_STATUS_REG  =================================================== */
-#define TIMER3_TIMER3_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL)        /*!< TIM_ONESHOT_PHASE (Bit 2)                             */
-#define TIMER3_TIMER3_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL)      /*!< TIM_ONESHOT_PHASE (Bitfield-Mask: 0x03)               */
-#define TIMER3_TIMER3_STATUS_REG_TIM_IN2_STATE_Pos (1UL)            /*!< TIM_IN2_STATE (Bit 1)                                 */
-#define TIMER3_TIMER3_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL)          /*!< TIM_IN2_STATE (Bitfield-Mask: 0x01)                   */
-#define TIMER3_TIMER3_STATUS_REG_TIM_IN1_STATE_Pos (0UL)            /*!< TIM_IN1_STATE (Bit 0)                                 */
-#define TIMER3_TIMER3_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL)          /*!< TIM_IN1_STATE (Bitfield-Mask: 0x01)                   */
-/* =================================================  TIMER3_TIMER_VAL_REG  ================================================== */
-#define TIMER3_TIMER3_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos (0UL)       /*!< TIM_TIMER_VALUE (Bit 0)                               */
-#define TIMER3_TIMER3_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk (0xffffffUL) /*!< TIM_TIMER_VALUE (Bitfield-Mask: 0xffffff)            */
-
-
-/* =========================================================================================================================== */
-/* ================                                          TIMER4                                           ================ */
-/* =========================================================================================================================== */
-
-/* ===============================================  TIMER4_CAPTURE_GPIO1_REG  ================================================ */
-#define TIMER4_TIMER4_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos (0UL) /*!< TIM_CAPTURE_GPIO1 (Bit 0)                             */
-#define TIMER4_TIMER4_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO1 (Bitfield-Mask: 0xffffff)    */
-/* ===============================================  TIMER4_CAPTURE_GPIO2_REG  ================================================ */
-#define TIMER4_TIMER4_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos (0UL) /*!< TIM_CAPTURE_GPIO2 (Bit 0)                             */
-#define TIMER4_TIMER4_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO2 (Bitfield-Mask: 0xffffff)    */
-/* =================================================  TIMER4_CLEAR_IRQ_REG  ================================================== */
-#define TIMER4_TIMER4_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL)         /*!< TIM_CLEAR_IRQ (Bit 0)                                 */
-#define TIMER4_TIMER4_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL)       /*!< TIM_CLEAR_IRQ (Bitfield-Mask: 0x01)                   */
-/* ====================================================  TIMER4_CTRL_REG  ==================================================== */
-#define TIMER4_TIMER4_CTRL_REG_TIM_CLK_EN_Pos (8UL)                 /*!< TIM_CLK_EN (Bit 8)                                    */
-#define TIMER4_TIMER4_CTRL_REG_TIM_CLK_EN_Msk (0x100UL)             /*!< TIM_CLK_EN (Bitfield-Mask: 0x01)                      */
-#define TIMER4_TIMER4_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL)             /*!< TIM_SYS_CLK_EN (Bit 7)                                */
-#define TIMER4_TIMER4_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL)          /*!< TIM_SYS_CLK_EN (Bitfield-Mask: 0x01)                  */
-#define TIMER4_TIMER4_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL)       /*!< TIM_FREE_RUN_MODE_EN (Bit 6)                          */
-#define TIMER4_TIMER4_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL)    /*!< TIM_FREE_RUN_MODE_EN (Bitfield-Mask: 0x01)            */
-#define TIMER4_TIMER4_CTRL_REG_TIM_IRQ_EN_Pos (5UL)                 /*!< TIM_IRQ_EN (Bit 5)                                    */
-#define TIMER4_TIMER4_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL)              /*!< TIM_IRQ_EN (Bitfield-Mask: 0x01)                      */
-#define TIMER4_TIMER4_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL)      /*!< TIM_IN2_EVENT_FALL_EN (Bit 4)                         */
-#define TIMER4_TIMER4_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL)   /*!< TIM_IN2_EVENT_FALL_EN (Bitfield-Mask: 0x01)           */
-#define TIMER4_TIMER4_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL)      /*!< TIM_IN1_EVENT_FALL_EN (Bit 3)                         */
-#define TIMER4_TIMER4_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL)    /*!< TIM_IN1_EVENT_FALL_EN (Bitfield-Mask: 0x01)           */
-#define TIMER4_TIMER4_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL)          /*!< TIM_COUNT_DOWN_EN (Bit 2)                             */
-#define TIMER4_TIMER4_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL)        /*!< TIM_COUNT_DOWN_EN (Bitfield-Mask: 0x01)               */
-#define TIMER4_TIMER4_CTRL_REG_TIM_EN_Pos (0UL)                     /*!< TIM_EN (Bit 0)                                        */
-#define TIMER4_TIMER4_CTRL_REG_TIM_EN_Msk (0x1UL)                   /*!< TIM_EN (Bitfield-Mask: 0x01)                          */
-/* =================================================  TIMER4_GPIO1_CONF_REG  ================================================= */
-#define TIMER4_TIMER4_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL)       /*!< TIM_GPIO1_CONF (Bit 0)                                */
-#define TIMER4_TIMER4_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL)    /*!< TIM_GPIO1_CONF (Bitfield-Mask: 0x3f)                  */
-/* =================================================  TIMER4_GPIO2_CONF_REG  ================================================= */
-#define TIMER4_TIMER4_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL)       /*!< TIM_GPIO2_CONF (Bit 0)                                */
-#define TIMER4_TIMER4_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL)    /*!< TIM_GPIO2_CONF (Bitfield-Mask: 0x3f)                  */
-/* =================================================  TIMER4_PRESCALER_REG  ================================================== */
-#define TIMER4_TIMER4_PRESCALER_REG_TIM_PRESCALER_Pos (0UL)         /*!< TIM_PRESCALER (Bit 0)                                 */
-#define TIMER4_TIMER4_PRESCALER_REG_TIM_PRESCALER_Msk (0x1fUL)      /*!< TIM_PRESCALER (Bitfield-Mask: 0x1f)                   */
-/* ===============================================  TIMER4_PRESCALER_VAL_REG  ================================================ */
-#define TIMER4_TIMER4_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL) /*!< TIM_PRESCALER_VAL (Bit 0)                             */
-#define TIMER4_TIMER4_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL) /*!< TIM_PRESCALER_VAL (Bitfield-Mask: 0x1f)            */
-/* ===================================================  TIMER4_PWM_DC_REG  =================================================== */
-#define TIMER4_TIMER4_PWM_DC_REG_TIM_PWM_DC_Pos (0UL)               /*!< TIM_PWM_DC (Bit 0)                                    */
-#define TIMER4_TIMER4_PWM_DC_REG_TIM_PWM_DC_Msk (0xffffUL)          /*!< TIM_PWM_DC (Bitfield-Mask: 0xffff)                    */
-/* ==================================================  TIMER4_PWM_FREQ_REG  ================================================== */
-#define TIMER4_TIMER4_PWM_FREQ_REG_TIM_PWM_FREQ_Pos (0UL)           /*!< TIM_PWM_FREQ (Bit 0)                                  */
-#define TIMER4_TIMER4_PWM_FREQ_REG_TIM_PWM_FREQ_Msk (0xffffUL)      /*!< TIM_PWM_FREQ (Bitfield-Mask: 0xffff)                  */
-/* ===================================================  TIMER4_RELOAD_REG  =================================================== */
-#define TIMER4_TIMER4_RELOAD_REG_TIM_RELOAD_Pos (0UL)               /*!< TIM_RELOAD (Bit 0)                                    */
-#define TIMER4_TIMER4_RELOAD_REG_TIM_RELOAD_Msk (0xffffffUL)        /*!< TIM_RELOAD (Bitfield-Mask: 0xffffff)                  */
-/* ===================================================  TIMER4_STATUS_REG  =================================================== */
-#define TIMER4_TIMER4_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL)        /*!< TIM_ONESHOT_PHASE (Bit 2)                             */
-#define TIMER4_TIMER4_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL)      /*!< TIM_ONESHOT_PHASE (Bitfield-Mask: 0x03)               */
-#define TIMER4_TIMER4_STATUS_REG_TIM_IN2_STATE_Pos (1UL)            /*!< TIM_IN2_STATE (Bit 1)                                 */
-#define TIMER4_TIMER4_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL)          /*!< TIM_IN2_STATE (Bitfield-Mask: 0x01)                   */
-#define TIMER4_TIMER4_STATUS_REG_TIM_IN1_STATE_Pos (0UL)            /*!< TIM_IN1_STATE (Bit 0)                                 */
-#define TIMER4_TIMER4_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL)          /*!< TIM_IN1_STATE (Bitfield-Mask: 0x01)                   */
-/* =================================================  TIMER4_TIMER_VAL_REG  ================================================== */
-#define TIMER4_TIMER4_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos (0UL)       /*!< TIM_TIMER_VALUE (Bit 0)                               */
-#define TIMER4_TIMER4_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk (0xffffffUL) /*!< TIM_TIMER_VALUE (Bitfield-Mask: 0xffffff)            */
-
-
-/* =========================================================================================================================== */
-/* ================                                           TRNG                                            ================ */
-/* =========================================================================================================================== */
-
-/* =====================================================  TRNG_CTRL_REG  ===================================================== */
-#define TRNG_TRNG_CTRL_REG_TRNG_ENABLE_Pos (0UL)                    /*!< TRNG_ENABLE (Bit 0)                                   */
-#define TRNG_TRNG_CTRL_REG_TRNG_ENABLE_Msk (0x1UL)                  /*!< TRNG_ENABLE (Bitfield-Mask: 0x01)                     */
-/* ===================================================  TRNG_FIFOLVL_REG  ==================================================== */
-#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOFULL_Pos (5UL)               /*!< TRNG_FIFOFULL (Bit 5)                                 */
-#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOFULL_Msk (0x20UL)            /*!< TRNG_FIFOFULL (Bitfield-Mask: 0x01)                   */
-#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOLVL_Pos (0UL)                /*!< TRNG_FIFOLVL (Bit 0)                                  */
-#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOLVL_Msk (0x1fUL)             /*!< TRNG_FIFOLVL (Bitfield-Mask: 0x1f)                    */
-/* =====================================================  TRNG_VER_REG  ====================================================== */
-#define TRNG_TRNG_VER_REG_TRNG_MAJ_Pos    (24UL)                    /*!< TRNG_MAJ (Bit 24)                                     */
-#define TRNG_TRNG_VER_REG_TRNG_MAJ_Msk    (0xff000000UL)            /*!< TRNG_MAJ (Bitfield-Mask: 0xff)                        */
-#define TRNG_TRNG_VER_REG_TRNG_MIN_Pos    (16UL)                    /*!< TRNG_MIN (Bit 16)                                     */
-#define TRNG_TRNG_VER_REG_TRNG_MIN_Msk    (0xff0000UL)              /*!< TRNG_MIN (Bitfield-Mask: 0xff)                        */
-#define TRNG_TRNG_VER_REG_TRNG_SVN_Pos    (0UL)                     /*!< TRNG_SVN (Bit 0)                                      */
-#define TRNG_TRNG_VER_REG_TRNG_SVN_Msk    (0xffffUL)                /*!< TRNG_SVN (Bitfield-Mask: 0xffff)                      */
-
-
-/* =========================================================================================================================== */
-/* ================                                           UART                                            ================ */
-/* =========================================================================================================================== */
-
-/* =====================================================  UART_CTR_REG  ====================================================== */
-#define UART_UART_CTR_REG_UART_CTR_Pos    (0UL)                     /*!< UART_CTR (Bit 0)                                      */
-#define UART_UART_CTR_REG_UART_CTR_Msk    (0xffffffffUL)            /*!< UART_CTR (Bitfield-Mask: 0xffffffff)                  */
-/* =====================================================  UART_DLF_REG  ====================================================== */
-#define UART_UART_DLF_REG_UART_DLF_Pos    (0UL)                     /*!< UART_DLF (Bit 0)                                      */
-#define UART_UART_DLF_REG_UART_DLF_Msk    (0xfUL)                   /*!< UART_DLF (Bitfield-Mask: 0x0f)                        */
-/* ====================================================  UART_DMASA_REG  ===================================================== */
-#define UART_UART_DMASA_REG_UART_DMASA_Pos (0UL)                    /*!< UART_DMASA (Bit 0)                                    */
-#define UART_UART_DMASA_REG_UART_DMASA_Msk (0x1UL)                  /*!< UART_DMASA (Bitfield-Mask: 0x01)                      */
-/* =====================================================  UART_HTX_REG  ====================================================== */
-#define UART_UART_HTX_REG_UART_HALT_TX_Pos (0UL)                    /*!< UART_HALT_TX (Bit 0)                                  */
-#define UART_UART_HTX_REG_UART_HALT_TX_Msk (0x1UL)                  /*!< UART_HALT_TX (Bitfield-Mask: 0x01)                    */
-/* ===================================================  UART_IER_DLH_REG  ==================================================== */
-#define UART_UART_IER_DLH_REG_PTIME_DLH7_Pos (7UL)                  /*!< PTIME_DLH7 (Bit 7)                                    */
-#define UART_UART_IER_DLH_REG_PTIME_DLH7_Msk (0x80UL)               /*!< PTIME_DLH7 (Bitfield-Mask: 0x01)                      */
-#define UART_UART_IER_DLH_REG_DLH6_5_Pos  (5UL)                     /*!< DLH6_5 (Bit 5)                                        */
-#define UART_UART_IER_DLH_REG_DLH6_5_Msk  (0x60UL)                  /*!< DLH6_5 (Bitfield-Mask: 0x03)                          */
-#define UART_UART_IER_DLH_REG_ELCOLR_DLH4_Pos (4UL)                 /*!< ELCOLR_DLH4 (Bit 4)                                   */
-#define UART_UART_IER_DLH_REG_ELCOLR_DLH4_Msk (0x10UL)              /*!< ELCOLR_DLH4 (Bitfield-Mask: 0x01)                     */
-#define UART_UART_IER_DLH_REG_EDSSI_DLH3_Pos (3UL)                  /*!< EDSSI_DLH3 (Bit 3)                                    */
-#define UART_UART_IER_DLH_REG_EDSSI_DLH3_Msk (0x8UL)                /*!< EDSSI_DLH3 (Bitfield-Mask: 0x01)                      */
-#define UART_UART_IER_DLH_REG_ELSI_DLH2_Pos (2UL)                   /*!< ELSI_DLH2 (Bit 2)                                     */
-#define UART_UART_IER_DLH_REG_ELSI_DLH2_Msk (0x4UL)                 /*!< ELSI_DLH2 (Bitfield-Mask: 0x01)                       */
-#define UART_UART_IER_DLH_REG_ETBEI_DLH1_Pos (1UL)                  /*!< ETBEI_DLH1 (Bit 1)                                    */
-#define UART_UART_IER_DLH_REG_ETBEI_DLH1_Msk (0x2UL)                /*!< ETBEI_DLH1 (Bitfield-Mask: 0x01)                      */
-#define UART_UART_IER_DLH_REG_ERBFI_DLH0_Pos (0UL)                  /*!< ERBFI_DLH0 (Bit 0)                                    */
-#define UART_UART_IER_DLH_REG_ERBFI_DLH0_Msk (0x1UL)                /*!< ERBFI_DLH0 (Bitfield-Mask: 0x01)                      */
-/* ===================================================  UART_IIR_FCR_REG  ==================================================== */
-#define UART_UART_IIR_FCR_REG_IIR_FCR_Pos (0UL)                     /*!< IIR_FCR (Bit 0)                                       */
-#define UART_UART_IIR_FCR_REG_IIR_FCR_Msk (0xffUL)                  /*!< IIR_FCR (Bitfield-Mask: 0xff)                         */
-/* =====================================================  UART_LCR_REG  ====================================================== */
-#define UART_UART_LCR_REG_UART_DLAB_Pos   (7UL)                     /*!< UART_DLAB (Bit 7)                                     */
-#define UART_UART_LCR_REG_UART_DLAB_Msk   (0x80UL)                  /*!< UART_DLAB (Bitfield-Mask: 0x01)                       */
-#define UART_UART_LCR_REG_UART_BC_Pos     (6UL)                     /*!< UART_BC (Bit 6)                                       */
-#define UART_UART_LCR_REG_UART_BC_Msk     (0x40UL)                  /*!< UART_BC (Bitfield-Mask: 0x01)                         */
-#define UART_UART_LCR_REG_UART_EPS_Pos    (4UL)                     /*!< UART_EPS (Bit 4)                                      */
-#define UART_UART_LCR_REG_UART_EPS_Msk    (0x10UL)                  /*!< UART_EPS (Bitfield-Mask: 0x01)                        */
-#define UART_UART_LCR_REG_UART_PEN_Pos    (3UL)                     /*!< UART_PEN (Bit 3)                                      */
-#define UART_UART_LCR_REG_UART_PEN_Msk    (0x8UL)                   /*!< UART_PEN (Bitfield-Mask: 0x01)                        */
-#define UART_UART_LCR_REG_UART_STOP_Pos   (2UL)                     /*!< UART_STOP (Bit 2)                                     */
-#define UART_UART_LCR_REG_UART_STOP_Msk   (0x4UL)                   /*!< UART_STOP (Bitfield-Mask: 0x01)                       */
-#define UART_UART_LCR_REG_UART_DLS_Pos    (0UL)                     /*!< UART_DLS (Bit 0)                                      */
-#define UART_UART_LCR_REG_UART_DLS_Msk    (0x3UL)                   /*!< UART_DLS (Bitfield-Mask: 0x03)                        */
-/* =====================================================  UART_LSR_REG  ====================================================== */
-#define UART_UART_LSR_REG_UART_RFE_Pos    (7UL)                     /*!< UART_RFE (Bit 7)                                      */
-#define UART_UART_LSR_REG_UART_RFE_Msk    (0x80UL)                  /*!< UART_RFE (Bitfield-Mask: 0x01)                        */
-#define UART_UART_LSR_REG_UART_TEMT_Pos   (6UL)                     /*!< UART_TEMT (Bit 6)                                     */
-#define UART_UART_LSR_REG_UART_TEMT_Msk   (0x40UL)                  /*!< UART_TEMT (Bitfield-Mask: 0x01)                       */
-#define UART_UART_LSR_REG_UART_THRE_Pos   (5UL)                     /*!< UART_THRE (Bit 5)                                     */
-#define UART_UART_LSR_REG_UART_THRE_Msk   (0x20UL)                  /*!< UART_THRE (Bitfield-Mask: 0x01)                       */
-#define UART_UART_LSR_REG_UART_BI_Pos     (4UL)                     /*!< UART_BI (Bit 4)                                       */
-#define UART_UART_LSR_REG_UART_BI_Msk     (0x10UL)                  /*!< UART_BI (Bitfield-Mask: 0x01)                         */
-#define UART_UART_LSR_REG_UART_FE_Pos     (3UL)                     /*!< UART_FE (Bit 3)                                       */
-#define UART_UART_LSR_REG_UART_FE_Msk     (0x8UL)                   /*!< UART_FE (Bitfield-Mask: 0x01)                         */
-#define UART_UART_LSR_REG_UART_PE_Pos     (2UL)                     /*!< UART_PE (Bit 2)                                       */
-#define UART_UART_LSR_REG_UART_PE_Msk     (0x4UL)                   /*!< UART_PE (Bitfield-Mask: 0x01)                         */
-#define UART_UART_LSR_REG_UART_OE_Pos     (1UL)                     /*!< UART_OE (Bit 1)                                       */
-#define UART_UART_LSR_REG_UART_OE_Msk     (0x2UL)                   /*!< UART_OE (Bitfield-Mask: 0x01)                         */
-#define UART_UART_LSR_REG_UART_DR_Pos     (0UL)                     /*!< UART_DR (Bit 0)                                       */
-#define UART_UART_LSR_REG_UART_DR_Msk     (0x1UL)                   /*!< UART_DR (Bitfield-Mask: 0x01)                         */
-/* =====================================================  UART_MCR_REG  ====================================================== */
-#define UART_UART_MCR_REG_UART_LB_Pos     (4UL)                     /*!< UART_LB (Bit 4)                                       */
-#define UART_UART_MCR_REG_UART_LB_Msk     (0x10UL)                  /*!< UART_LB (Bitfield-Mask: 0x01)                         */
-/* =================================================  UART_RBR_THR_DLL_REG  ================================================== */
-#define UART_UART_RBR_THR_DLL_REG_RBR_THR_DLL_Pos (0UL)             /*!< RBR_THR_DLL (Bit 0)                                   */
-#define UART_UART_RBR_THR_DLL_REG_RBR_THR_DLL_Msk (0xffUL)          /*!< RBR_THR_DLL (Bitfield-Mask: 0xff)                     */
-/* =====================================================  UART_RFL_REG  ====================================================== */
-#define UART_UART_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Pos (0UL)         /*!< UART_RECEIVE_FIFO_LEVEL (Bit 0)                       */
-#define UART_UART_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Msk (0x1fUL)      /*!< UART_RECEIVE_FIFO_LEVEL (Bitfield-Mask: 0x1f)         */
-/* =====================================================  UART_SBCR_REG  ===================================================== */
-#define UART_UART_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Pos (0UL)      /*!< UART_SHADOW_BREAK_CONTROL (Bit 0)                     */
-#define UART_UART_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Msk (0x1UL)    /*!< UART_SHADOW_BREAK_CONTROL (Bitfield-Mask: 0x01)       */
-/* =====================================================  UART_SCR_REG  ====================================================== */
-#define UART_UART_SCR_REG_UART_SCRATCH_PAD_Pos (0UL)                /*!< UART_SCRATCH_PAD (Bit 0)                              */
-#define UART_UART_SCR_REG_UART_SCRATCH_PAD_Msk (0xffUL)             /*!< UART_SCRATCH_PAD (Bitfield-Mask: 0xff)                */
-/* ====================================================  UART_SDMAM_REG  ===================================================== */
-#define UART_UART_SDMAM_REG_UART_SHADOW_DMA_MODE_Pos (0UL)          /*!< UART_SHADOW_DMA_MODE (Bit 0)                          */
-#define UART_UART_SDMAM_REG_UART_SHADOW_DMA_MODE_Msk (0x1UL)        /*!< UART_SHADOW_DMA_MODE (Bitfield-Mask: 0x01)            */
-/* =====================================================  UART_SFE_REG  ====================================================== */
-#define UART_UART_SFE_REG_UART_SHADOW_FIFO_ENABLE_Pos (0UL)         /*!< UART_SHADOW_FIFO_ENABLE (Bit 0)                       */
-#define UART_UART_SFE_REG_UART_SHADOW_FIFO_ENABLE_Msk (0x1UL)       /*!< UART_SHADOW_FIFO_ENABLE (Bitfield-Mask: 0x01)         */
-/* ==================================================  UART_SRBR_STHR0_REG  ================================================== */
-#define UART_UART_SRBR_STHR0_REG_SRBR_STHRx_Pos (0UL)               /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART_UART_SRBR_STHR0_REG_SRBR_STHRx_Msk (0xffUL)            /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART_SRBR_STHR10_REG  ================================================== */
-#define UART_UART_SRBR_STHR10_REG_SRBR_STHRx_Pos (0UL)              /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART_UART_SRBR_STHR10_REG_SRBR_STHRx_Msk (0xffUL)           /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART_SRBR_STHR11_REG  ================================================== */
-#define UART_UART_SRBR_STHR11_REG_SRBR_STHRx_Pos (0UL)              /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART_UART_SRBR_STHR11_REG_SRBR_STHRx_Msk (0xffUL)           /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART_SRBR_STHR12_REG  ================================================== */
-#define UART_UART_SRBR_STHR12_REG_SRBR_STHRx_Pos (0UL)              /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART_UART_SRBR_STHR12_REG_SRBR_STHRx_Msk (0xffUL)           /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART_SRBR_STHR13_REG  ================================================== */
-#define UART_UART_SRBR_STHR13_REG_SRBR_STHRx_Pos (0UL)              /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART_UART_SRBR_STHR13_REG_SRBR_STHRx_Msk (0xffUL)           /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART_SRBR_STHR14_REG  ================================================== */
-#define UART_UART_SRBR_STHR14_REG_SRBR_STHRx_Pos (0UL)              /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART_UART_SRBR_STHR14_REG_SRBR_STHRx_Msk (0xffUL)           /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART_SRBR_STHR15_REG  ================================================== */
-#define UART_UART_SRBR_STHR15_REG_SRBR_STHRx_Pos (0UL)              /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART_UART_SRBR_STHR15_REG_SRBR_STHRx_Msk (0xffUL)           /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* ==================================================  UART_SRBR_STHR1_REG  ================================================== */
-#define UART_UART_SRBR_STHR1_REG_SRBR_STHRx_Pos (0UL)               /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART_UART_SRBR_STHR1_REG_SRBR_STHRx_Msk (0xffUL)            /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* ==================================================  UART_SRBR_STHR2_REG  ================================================== */
-#define UART_UART_SRBR_STHR2_REG_SRBR_STHRx_Pos (0UL)               /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART_UART_SRBR_STHR2_REG_SRBR_STHRx_Msk (0xffUL)            /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* ==================================================  UART_SRBR_STHR3_REG  ================================================== */
-#define UART_UART_SRBR_STHR3_REG_SRBR_STHRx_Pos (0UL)               /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART_UART_SRBR_STHR3_REG_SRBR_STHRx_Msk (0xffUL)            /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* ==================================================  UART_SRBR_STHR4_REG  ================================================== */
-#define UART_UART_SRBR_STHR4_REG_SRBR_STHRx_Pos (0UL)               /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART_UART_SRBR_STHR4_REG_SRBR_STHRx_Msk (0xffUL)            /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* ==================================================  UART_SRBR_STHR5_REG  ================================================== */
-#define UART_UART_SRBR_STHR5_REG_SRBR_STHRx_Pos (0UL)               /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART_UART_SRBR_STHR5_REG_SRBR_STHRx_Msk (0xffUL)            /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* ==================================================  UART_SRBR_STHR6_REG  ================================================== */
-#define UART_UART_SRBR_STHR6_REG_SRBR_STHRx_Pos (0UL)               /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART_UART_SRBR_STHR6_REG_SRBR_STHRx_Msk (0xffUL)            /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* ==================================================  UART_SRBR_STHR7_REG  ================================================== */
-#define UART_UART_SRBR_STHR7_REG_SRBR_STHRx_Pos (0UL)               /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART_UART_SRBR_STHR7_REG_SRBR_STHRx_Msk (0xffUL)            /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* ==================================================  UART_SRBR_STHR8_REG  ================================================== */
-#define UART_UART_SRBR_STHR8_REG_SRBR_STHRx_Pos (0UL)               /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART_UART_SRBR_STHR8_REG_SRBR_STHRx_Msk (0xffUL)            /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* ==================================================  UART_SRBR_STHR9_REG  ================================================== */
-#define UART_UART_SRBR_STHR9_REG_SRBR_STHRx_Pos (0UL)               /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART_UART_SRBR_STHR9_REG_SRBR_STHRx_Msk (0xffUL)            /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =====================================================  UART_SRR_REG  ====================================================== */
-#define UART_UART_SRR_REG_UART_XFR_Pos    (2UL)                     /*!< UART_XFR (Bit 2)                                      */
-#define UART_UART_SRR_REG_UART_XFR_Msk    (0x4UL)                   /*!< UART_XFR (Bitfield-Mask: 0x01)                        */
-#define UART_UART_SRR_REG_UART_RFR_Pos    (1UL)                     /*!< UART_RFR (Bit 1)                                      */
-#define UART_UART_SRR_REG_UART_RFR_Msk    (0x2UL)                   /*!< UART_RFR (Bitfield-Mask: 0x01)                        */
-#define UART_UART_SRR_REG_UART_UR_Pos     (0UL)                     /*!< UART_UR (Bit 0)                                       */
-#define UART_UART_SRR_REG_UART_UR_Msk     (0x1UL)                   /*!< UART_UR (Bitfield-Mask: 0x01)                         */
-/* =====================================================  UART_SRT_REG  ====================================================== */
-#define UART_UART_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Pos (0UL)        /*!< UART_SHADOW_RCVR_TRIGGER (Bit 0)                      */
-#define UART_UART_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Msk (0x3UL)      /*!< UART_SHADOW_RCVR_TRIGGER (Bitfield-Mask: 0x03)        */
-/* =====================================================  UART_STET_REG  ===================================================== */
-#define UART_UART_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Pos (0UL)   /*!< UART_SHADOW_TX_EMPTY_TRIGGER (Bit 0)                  */
-#define UART_UART_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Msk (0x3UL) /*!< UART_SHADOW_TX_EMPTY_TRIGGER (Bitfield-Mask: 0x03)    */
-/* =====================================================  UART_TFL_REG  ====================================================== */
-#define UART_UART_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Pos (0UL)        /*!< UART_TRANSMIT_FIFO_LEVEL (Bit 0)                      */
-#define UART_UART_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Msk (0x1fUL)     /*!< UART_TRANSMIT_FIFO_LEVEL (Bitfield-Mask: 0x1f)        */
-/* =====================================================  UART_UCV_REG  ====================================================== */
-#define UART_UART_UCV_REG_UART_UCV_Pos    (0UL)                     /*!< UART_UCV (Bit 0)                                      */
-#define UART_UART_UCV_REG_UART_UCV_Msk    (0xffffffffUL)            /*!< UART_UCV (Bitfield-Mask: 0xffffffff)                  */
-/* =====================================================  UART_USR_REG  ====================================================== */
-#define UART_UART_USR_REG_UART_RFF_Pos    (4UL)                     /*!< UART_RFF (Bit 4)                                      */
-#define UART_UART_USR_REG_UART_RFF_Msk    (0x10UL)                  /*!< UART_RFF (Bitfield-Mask: 0x01)                        */
-#define UART_UART_USR_REG_UART_RFNE_Pos   (3UL)                     /*!< UART_RFNE (Bit 3)                                     */
-#define UART_UART_USR_REG_UART_RFNE_Msk   (0x8UL)                   /*!< UART_RFNE (Bitfield-Mask: 0x01)                       */
-#define UART_UART_USR_REG_UART_TFE_Pos    (2UL)                     /*!< UART_TFE (Bit 2)                                      */
-#define UART_UART_USR_REG_UART_TFE_Msk    (0x4UL)                   /*!< UART_TFE (Bitfield-Mask: 0x01)                        */
-#define UART_UART_USR_REG_UART_TFNF_Pos   (1UL)                     /*!< UART_TFNF (Bit 1)                                     */
-#define UART_UART_USR_REG_UART_TFNF_Msk   (0x2UL)                   /*!< UART_TFNF (Bitfield-Mask: 0x01)                       */
-#define UART_UART_USR_REG_UART_BUSY_Pos   (0UL)                     /*!< UART_BUSY (Bit 0)                                     */
-#define UART_UART_USR_REG_UART_BUSY_Msk   (0x1UL)                   /*!< UART_BUSY (Bitfield-Mask: 0x01)                       */
-
-
-/* =========================================================================================================================== */
-/* ================                                           UART2                                           ================ */
-/* =========================================================================================================================== */
-
-/* =====================================================  UART2_CTR_REG  ===================================================== */
-#define UART2_UART2_CTR_REG_UART_CTR_Pos  (0UL)                     /*!< UART_CTR (Bit 0)                                      */
-#define UART2_UART2_CTR_REG_UART_CTR_Msk  (0xffffffffUL)            /*!< UART_CTR (Bitfield-Mask: 0xffffffff)                  */
-/* =====================================================  UART2_DLF_REG  ===================================================== */
-#define UART2_UART2_DLF_REG_UART_DLF_Pos  (0UL)                     /*!< UART_DLF (Bit 0)                                      */
-#define UART2_UART2_DLF_REG_UART_DLF_Msk  (0xfUL)                   /*!< UART_DLF (Bitfield-Mask: 0x0f)                        */
-/* ====================================================  UART2_DMASA_REG  ==================================================== */
-#define UART2_UART2_DMASA_REG_UART_DMASA_Pos (0UL)                  /*!< UART_DMASA (Bit 0)                                    */
-#define UART2_UART2_DMASA_REG_UART_DMASA_Msk (0x1UL)                /*!< UART_DMASA (Bitfield-Mask: 0x01)                      */
-/* =====================================================  UART2_HTX_REG  ===================================================== */
-#define UART2_UART2_HTX_REG_UART_HALT_TX_Pos (0UL)                  /*!< UART_HALT_TX (Bit 0)                                  */
-#define UART2_UART2_HTX_REG_UART_HALT_TX_Msk (0x1UL)                /*!< UART_HALT_TX (Bitfield-Mask: 0x01)                    */
-/* ===================================================  UART2_IER_DLH_REG  =================================================== */
-#define UART2_UART2_IER_DLH_REG_PTIME_DLH7_Pos (7UL)                /*!< PTIME_DLH7 (Bit 7)                                    */
-#define UART2_UART2_IER_DLH_REG_PTIME_DLH7_Msk (0x80UL)             /*!< PTIME_DLH7 (Bitfield-Mask: 0x01)                      */
-#define UART2_UART2_IER_DLH_REG_DLH6_5_Pos (5UL)                    /*!< DLH6_5 (Bit 5)                                        */
-#define UART2_UART2_IER_DLH_REG_DLH6_5_Msk (0x60UL)                 /*!< DLH6_5 (Bitfield-Mask: 0x03)                          */
-#define UART2_UART2_IER_DLH_REG_ELCOLR_DLH4_Pos (4UL)               /*!< ELCOLR_DLH4 (Bit 4)                                   */
-#define UART2_UART2_IER_DLH_REG_ELCOLR_DLH4_Msk (0x10UL)            /*!< ELCOLR_DLH4 (Bitfield-Mask: 0x01)                     */
-#define UART2_UART2_IER_DLH_REG_EDSSI_DLH3_Pos (3UL)                /*!< EDSSI_DLH3 (Bit 3)                                    */
-#define UART2_UART2_IER_DLH_REG_EDSSI_DLH3_Msk (0x8UL)              /*!< EDSSI_DLH3 (Bitfield-Mask: 0x01)                      */
-#define UART2_UART2_IER_DLH_REG_ELSI_DLH2_Pos (2UL)                 /*!< ELSI_DLH2 (Bit 2)                                     */
-#define UART2_UART2_IER_DLH_REG_ELSI_DLH2_Msk (0x4UL)               /*!< ELSI_DLH2 (Bitfield-Mask: 0x01)                       */
-#define UART2_UART2_IER_DLH_REG_ETBEI_DLH1_Pos (1UL)                /*!< ETBEI_DLH1 (Bit 1)                                    */
-#define UART2_UART2_IER_DLH_REG_ETBEI_DLH1_Msk (0x2UL)              /*!< ETBEI_DLH1 (Bitfield-Mask: 0x01)                      */
-#define UART2_UART2_IER_DLH_REG_ERBFI_DLH0_Pos (0UL)                /*!< ERBFI_DLH0 (Bit 0)                                    */
-#define UART2_UART2_IER_DLH_REG_ERBFI_DLH0_Msk (0x1UL)              /*!< ERBFI_DLH0 (Bitfield-Mask: 0x01)                      */
-/* ===================================================  UART2_IIR_FCR_REG  =================================================== */
-#define UART2_UART2_IIR_FCR_REG_IIR_FCR_Pos (0UL)                   /*!< IIR_FCR (Bit 0)                                       */
-#define UART2_UART2_IIR_FCR_REG_IIR_FCR_Msk (0xffUL)                /*!< IIR_FCR (Bitfield-Mask: 0xff)                         */
-/* =====================================================  UART2_LCR_EXT  ===================================================== */
-#define UART2_UART2_LCR_EXT_UART_TRANSMIT_MODE_Pos (3UL)            /*!< UART_TRANSMIT_MODE (Bit 3)                            */
-#define UART2_UART2_LCR_EXT_UART_TRANSMIT_MODE_Msk (0x8UL)          /*!< UART_TRANSMIT_MODE (Bitfield-Mask: 0x01)              */
-#define UART2_UART2_LCR_EXT_UART_SEND_ADDR_Pos (2UL)                /*!< UART_SEND_ADDR (Bit 2)                                */
-#define UART2_UART2_LCR_EXT_UART_SEND_ADDR_Msk (0x4UL)              /*!< UART_SEND_ADDR (Bitfield-Mask: 0x01)                  */
-#define UART2_UART2_LCR_EXT_UART_ADDR_MATCH_Pos (1UL)               /*!< UART_ADDR_MATCH (Bit 1)                               */
-#define UART2_UART2_LCR_EXT_UART_ADDR_MATCH_Msk (0x2UL)             /*!< UART_ADDR_MATCH (Bitfield-Mask: 0x01)                 */
-#define UART2_UART2_LCR_EXT_UART_DLS_E_Pos (0UL)                    /*!< UART_DLS_E (Bit 0)                                    */
-#define UART2_UART2_LCR_EXT_UART_DLS_E_Msk (0x1UL)                  /*!< UART_DLS_E (Bitfield-Mask: 0x01)                      */
-/* =====================================================  UART2_LCR_REG  ===================================================== */
-#define UART2_UART2_LCR_REG_UART_DLAB_Pos (7UL)                     /*!< UART_DLAB (Bit 7)                                     */
-#define UART2_UART2_LCR_REG_UART_DLAB_Msk (0x80UL)                  /*!< UART_DLAB (Bitfield-Mask: 0x01)                       */
-#define UART2_UART2_LCR_REG_UART_BC_Pos   (6UL)                     /*!< UART_BC (Bit 6)                                       */
-#define UART2_UART2_LCR_REG_UART_BC_Msk   (0x40UL)                  /*!< UART_BC (Bitfield-Mask: 0x01)                         */
-#define UART2_UART2_LCR_REG_UART_SP_Pos   (5UL)                     /*!< UART_SP (Bit 5)                                       */
-#define UART2_UART2_LCR_REG_UART_SP_Msk   (0x20UL)                  /*!< UART_SP (Bitfield-Mask: 0x01)                         */
-#define UART2_UART2_LCR_REG_UART_EPS_Pos  (4UL)                     /*!< UART_EPS (Bit 4)                                      */
-#define UART2_UART2_LCR_REG_UART_EPS_Msk  (0x10UL)                  /*!< UART_EPS (Bitfield-Mask: 0x01)                        */
-#define UART2_UART2_LCR_REG_UART_PEN_Pos  (3UL)                     /*!< UART_PEN (Bit 3)                                      */
-#define UART2_UART2_LCR_REG_UART_PEN_Msk  (0x8UL)                   /*!< UART_PEN (Bitfield-Mask: 0x01)                        */
-#define UART2_UART2_LCR_REG_UART_STOP_Pos (2UL)                     /*!< UART_STOP (Bit 2)                                     */
-#define UART2_UART2_LCR_REG_UART_STOP_Msk (0x4UL)                   /*!< UART_STOP (Bitfield-Mask: 0x01)                       */
-#define UART2_UART2_LCR_REG_UART_DLS_Pos  (0UL)                     /*!< UART_DLS (Bit 0)                                      */
-#define UART2_UART2_LCR_REG_UART_DLS_Msk  (0x3UL)                   /*!< UART_DLS (Bitfield-Mask: 0x03)                        */
-/* =====================================================  UART2_LSR_REG  ===================================================== */
-#define UART2_UART2_LSR_REG_UART_ADDR_RCVD_Pos (8UL)                /*!< UART_ADDR_RCVD (Bit 8)                                */
-#define UART2_UART2_LSR_REG_UART_ADDR_RCVD_Msk (0x100UL)            /*!< UART_ADDR_RCVD (Bitfield-Mask: 0x01)                  */
-#define UART2_UART2_LSR_REG_UART_RFE_Pos  (7UL)                     /*!< UART_RFE (Bit 7)                                      */
-#define UART2_UART2_LSR_REG_UART_RFE_Msk  (0x80UL)                  /*!< UART_RFE (Bitfield-Mask: 0x01)                        */
-#define UART2_UART2_LSR_REG_UART_TEMT_Pos (6UL)                     /*!< UART_TEMT (Bit 6)                                     */
-#define UART2_UART2_LSR_REG_UART_TEMT_Msk (0x40UL)                  /*!< UART_TEMT (Bitfield-Mask: 0x01)                       */
-#define UART2_UART2_LSR_REG_UART_THRE_Pos (5UL)                     /*!< UART_THRE (Bit 5)                                     */
-#define UART2_UART2_LSR_REG_UART_THRE_Msk (0x20UL)                  /*!< UART_THRE (Bitfield-Mask: 0x01)                       */
-#define UART2_UART2_LSR_REG_UART_BI_Pos   (4UL)                     /*!< UART_BI (Bit 4)                                       */
-#define UART2_UART2_LSR_REG_UART_BI_Msk   (0x10UL)                  /*!< UART_BI (Bitfield-Mask: 0x01)                         */
-#define UART2_UART2_LSR_REG_UART_FE_Pos   (3UL)                     /*!< UART_FE (Bit 3)                                       */
-#define UART2_UART2_LSR_REG_UART_FE_Msk   (0x8UL)                   /*!< UART_FE (Bitfield-Mask: 0x01)                         */
-#define UART2_UART2_LSR_REG_UART_PE_Pos   (2UL)                     /*!< UART_PE (Bit 2)                                       */
-#define UART2_UART2_LSR_REG_UART_PE_Msk   (0x4UL)                   /*!< UART_PE (Bitfield-Mask: 0x01)                         */
-#define UART2_UART2_LSR_REG_UART_OE_Pos   (1UL)                     /*!< UART_OE (Bit 1)                                       */
-#define UART2_UART2_LSR_REG_UART_OE_Msk   (0x2UL)                   /*!< UART_OE (Bitfield-Mask: 0x01)                         */
-#define UART2_UART2_LSR_REG_UART_DR_Pos   (0UL)                     /*!< UART_DR (Bit 0)                                       */
-#define UART2_UART2_LSR_REG_UART_DR_Msk   (0x1UL)                   /*!< UART_DR (Bitfield-Mask: 0x01)                         */
-/* =====================================================  UART2_MCR_REG  ===================================================== */
-#define UART2_UART2_MCR_REG_UART_AFCE_Pos (5UL)                     /*!< UART_AFCE (Bit 5)                                     */
-#define UART2_UART2_MCR_REG_UART_AFCE_Msk (0x20UL)                  /*!< UART_AFCE (Bitfield-Mask: 0x01)                       */
-#define UART2_UART2_MCR_REG_UART_LB_Pos   (4UL)                     /*!< UART_LB (Bit 4)                                       */
-#define UART2_UART2_MCR_REG_UART_LB_Msk   (0x10UL)                  /*!< UART_LB (Bitfield-Mask: 0x01)                         */
-#define UART2_UART2_MCR_REG_UART_RTS_Pos  (1UL)                     /*!< UART_RTS (Bit 1)                                      */
-#define UART2_UART2_MCR_REG_UART_RTS_Msk  (0x2UL)                   /*!< UART_RTS (Bitfield-Mask: 0x01)                        */
-/* =====================================================  UART2_MSR_REG  ===================================================== */
-#define UART2_UART2_MSR_REG_UART_CTS_Pos  (4UL)                     /*!< UART_CTS (Bit 4)                                      */
-#define UART2_UART2_MSR_REG_UART_CTS_Msk  (0x10UL)                  /*!< UART_CTS (Bitfield-Mask: 0x01)                        */
-#define UART2_UART2_MSR_REG_UART_DCTS_Pos (0UL)                     /*!< UART_DCTS (Bit 0)                                     */
-#define UART2_UART2_MSR_REG_UART_DCTS_Msk (0x1UL)                   /*!< UART_DCTS (Bitfield-Mask: 0x01)                       */
-/* =====================================================  UART2_RAR_REG  ===================================================== */
-#define UART2_UART2_RAR_REG_UART_RAR_Pos  (0UL)                     /*!< UART_RAR (Bit 0)                                      */
-#define UART2_UART2_RAR_REG_UART_RAR_Msk  (0xffUL)                  /*!< UART_RAR (Bitfield-Mask: 0xff)                        */
-/* =================================================  UART2_RBR_THR_DLL_REG  ================================================= */
-#define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_9BIT_Pos (8UL)          /*!< RBR_THR_9BIT (Bit 8)                                  */
-#define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_9BIT_Msk (0x100UL)      /*!< RBR_THR_9BIT (Bitfield-Mask: 0x01)                    */
-#define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_DLL_Pos (0UL)           /*!< RBR_THR_DLL (Bit 0)                                   */
-#define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_DLL_Msk (0xffUL)        /*!< RBR_THR_DLL (Bitfield-Mask: 0xff)                     */
-/* =====================================================  UART2_RFL_REG  ===================================================== */
-#define UART2_UART2_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Pos (0UL)       /*!< UART_RECEIVE_FIFO_LEVEL (Bit 0)                       */
-#define UART2_UART2_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Msk (0x1fUL)    /*!< UART_RECEIVE_FIFO_LEVEL (Bitfield-Mask: 0x1f)         */
-/* ====================================================  UART2_SBCR_REG  ===================================================== */
-#define UART2_UART2_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Pos (0UL)    /*!< UART_SHADOW_BREAK_CONTROL (Bit 0)                     */
-#define UART2_UART2_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Msk (0x1UL)  /*!< UART_SHADOW_BREAK_CONTROL (Bitfield-Mask: 0x01)       */
-/* =====================================================  UART2_SCR_REG  ===================================================== */
-#define UART2_UART2_SCR_REG_UART_SCRATCH_PAD_Pos (0UL)              /*!< UART_SCRATCH_PAD (Bit 0)                              */
-#define UART2_UART2_SCR_REG_UART_SCRATCH_PAD_Msk (0xffUL)           /*!< UART_SCRATCH_PAD (Bitfield-Mask: 0xff)                */
-/* ====================================================  UART2_SDMAM_REG  ==================================================== */
-#define UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Pos (0UL)        /*!< UART_SHADOW_DMA_MODE (Bit 0)                          */
-#define UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Msk (0x1UL)      /*!< UART_SHADOW_DMA_MODE (Bitfield-Mask: 0x01)            */
-/* =====================================================  UART2_SFE_REG  ===================================================== */
-#define UART2_UART2_SFE_REG_UART_SHADOW_FIFO_ENABLE_Pos (0UL)       /*!< UART_SHADOW_FIFO_ENABLE (Bit 0)                       */
-#define UART2_UART2_SFE_REG_UART_SHADOW_FIFO_ENABLE_Msk (0x1UL)     /*!< UART_SHADOW_FIFO_ENABLE (Bitfield-Mask: 0x01)         */
-/* =================================================  UART2_SRBR_STHR0_REG  ================================================== */
-#define UART2_UART2_SRBR_STHR0_REG_SRBR_STHRx_Pos (0UL)             /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART2_UART2_SRBR_STHR0_REG_SRBR_STHRx_Msk (0xffUL)          /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART2_SRBR_STHR10_REG  ================================================= */
-#define UART2_UART2_SRBR_STHR10_REG_SRBR_STHRx_Pos (0UL)            /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART2_UART2_SRBR_STHR10_REG_SRBR_STHRx_Msk (0xffUL)         /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART2_SRBR_STHR11_REG  ================================================= */
-#define UART2_UART2_SRBR_STHR11_REG_SRBR_STHRx_Pos (0UL)            /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART2_UART2_SRBR_STHR11_REG_SRBR_STHRx_Msk (0xffUL)         /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART2_SRBR_STHR12_REG  ================================================= */
-#define UART2_UART2_SRBR_STHR12_REG_SRBR_STHRx_Pos (0UL)            /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART2_UART2_SRBR_STHR12_REG_SRBR_STHRx_Msk (0xffUL)         /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART2_SRBR_STHR13_REG  ================================================= */
-#define UART2_UART2_SRBR_STHR13_REG_SRBR_STHRx_Pos (0UL)            /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART2_UART2_SRBR_STHR13_REG_SRBR_STHRx_Msk (0xffUL)         /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART2_SRBR_STHR14_REG  ================================================= */
-#define UART2_UART2_SRBR_STHR14_REG_SRBR_STHRx_Pos (0UL)            /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART2_UART2_SRBR_STHR14_REG_SRBR_STHRx_Msk (0xffUL)         /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART2_SRBR_STHR15_REG  ================================================= */
-#define UART2_UART2_SRBR_STHR15_REG_SRBR_STHRx_Pos (0UL)            /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART2_UART2_SRBR_STHR15_REG_SRBR_STHRx_Msk (0xffUL)         /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART2_SRBR_STHR1_REG  ================================================== */
-#define UART2_UART2_SRBR_STHR1_REG_SRBR_STHRx_Pos (0UL)             /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART2_UART2_SRBR_STHR1_REG_SRBR_STHRx_Msk (0xffUL)          /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART2_SRBR_STHR2_REG  ================================================== */
-#define UART2_UART2_SRBR_STHR2_REG_SRBR_STHRx_Pos (0UL)             /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART2_UART2_SRBR_STHR2_REG_SRBR_STHRx_Msk (0xffUL)          /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART2_SRBR_STHR3_REG  ================================================== */
-#define UART2_UART2_SRBR_STHR3_REG_SRBR_STHRx_Pos (0UL)             /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART2_UART2_SRBR_STHR3_REG_SRBR_STHRx_Msk (0xffUL)          /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART2_SRBR_STHR4_REG  ================================================== */
-#define UART2_UART2_SRBR_STHR4_REG_SRBR_STHRx_Pos (0UL)             /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART2_UART2_SRBR_STHR4_REG_SRBR_STHRx_Msk (0xffUL)          /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART2_SRBR_STHR5_REG  ================================================== */
-#define UART2_UART2_SRBR_STHR5_REG_SRBR_STHRx_Pos (0UL)             /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART2_UART2_SRBR_STHR5_REG_SRBR_STHRx_Msk (0xffUL)          /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART2_SRBR_STHR6_REG  ================================================== */
-#define UART2_UART2_SRBR_STHR6_REG_SRBR_STHRx_Pos (0UL)             /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART2_UART2_SRBR_STHR6_REG_SRBR_STHRx_Msk (0xffUL)          /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART2_SRBR_STHR7_REG  ================================================== */
-#define UART2_UART2_SRBR_STHR7_REG_SRBR_STHRx_Pos (0UL)             /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART2_UART2_SRBR_STHR7_REG_SRBR_STHRx_Msk (0xffUL)          /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART2_SRBR_STHR8_REG  ================================================== */
-#define UART2_UART2_SRBR_STHR8_REG_SRBR_STHRx_Pos (0UL)             /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART2_UART2_SRBR_STHR8_REG_SRBR_STHRx_Msk (0xffUL)          /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART2_SRBR_STHR9_REG  ================================================== */
-#define UART2_UART2_SRBR_STHR9_REG_SRBR_STHRx_Pos (0UL)             /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART2_UART2_SRBR_STHR9_REG_SRBR_STHRx_Msk (0xffUL)          /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =====================================================  UART2_SRR_REG  ===================================================== */
-#define UART2_UART2_SRR_REG_UART_XFR_Pos  (2UL)                     /*!< UART_XFR (Bit 2)                                      */
-#define UART2_UART2_SRR_REG_UART_XFR_Msk  (0x4UL)                   /*!< UART_XFR (Bitfield-Mask: 0x01)                        */
-#define UART2_UART2_SRR_REG_UART_RFR_Pos  (1UL)                     /*!< UART_RFR (Bit 1)                                      */
-#define UART2_UART2_SRR_REG_UART_RFR_Msk  (0x2UL)                   /*!< UART_RFR (Bitfield-Mask: 0x01)                        */
-#define UART2_UART2_SRR_REG_UART_UR_Pos   (0UL)                     /*!< UART_UR (Bit 0)                                       */
-#define UART2_UART2_SRR_REG_UART_UR_Msk   (0x1UL)                   /*!< UART_UR (Bitfield-Mask: 0x01)                         */
-/* ====================================================  UART2_SRTS_REG  ===================================================== */
-#define UART2_UART2_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Pos (0UL)  /*!< UART_SHADOW_REQUEST_TO_SEND (Bit 0)                   */
-#define UART2_UART2_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Msk (0x1UL) /*!< UART_SHADOW_REQUEST_TO_SEND (Bitfield-Mask: 0x01)    */
-/* =====================================================  UART2_SRT_REG  ===================================================== */
-#define UART2_UART2_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Pos (0UL)      /*!< UART_SHADOW_RCVR_TRIGGER (Bit 0)                      */
-#define UART2_UART2_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Msk (0x3UL)    /*!< UART_SHADOW_RCVR_TRIGGER (Bitfield-Mask: 0x03)        */
-/* ====================================================  UART2_STET_REG  ===================================================== */
-#define UART2_UART2_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Pos (0UL) /*!< UART_SHADOW_TX_EMPTY_TRIGGER (Bit 0)                  */
-#define UART2_UART2_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Msk (0x3UL) /*!< UART_SHADOW_TX_EMPTY_TRIGGER (Bitfield-Mask: 0x03)  */
-/* =====================================================  UART2_TAR_REG  ===================================================== */
-#define UART2_UART2_TAR_REG_UART_TAR_Pos  (0UL)                     /*!< UART_TAR (Bit 0)                                      */
-#define UART2_UART2_TAR_REG_UART_TAR_Msk  (0xffUL)                  /*!< UART_TAR (Bitfield-Mask: 0xff)                        */
-/* =====================================================  UART2_TFL_REG  ===================================================== */
-#define UART2_UART2_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Pos (0UL)      /*!< UART_TRANSMIT_FIFO_LEVEL (Bit 0)                      */
-#define UART2_UART2_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Msk (0x1fUL)   /*!< UART_TRANSMIT_FIFO_LEVEL (Bitfield-Mask: 0x1f)        */
-/* =====================================================  UART2_UCV_REG  ===================================================== */
-#define UART2_UART2_UCV_REG_UART_UCV_Pos  (0UL)                     /*!< UART_UCV (Bit 0)                                      */
-#define UART2_UART2_UCV_REG_UART_UCV_Msk  (0xffffffffUL)            /*!< UART_UCV (Bitfield-Mask: 0xffffffff)                  */
-/* =====================================================  UART2_USR_REG  ===================================================== */
-#define UART2_UART2_USR_REG_UART_RFF_Pos  (4UL)                     /*!< UART_RFF (Bit 4)                                      */
-#define UART2_UART2_USR_REG_UART_RFF_Msk  (0x10UL)                  /*!< UART_RFF (Bitfield-Mask: 0x01)                        */
-#define UART2_UART2_USR_REG_UART_RFNE_Pos (3UL)                     /*!< UART_RFNE (Bit 3)                                     */
-#define UART2_UART2_USR_REG_UART_RFNE_Msk (0x8UL)                   /*!< UART_RFNE (Bitfield-Mask: 0x01)                       */
-#define UART2_UART2_USR_REG_UART_TFE_Pos  (2UL)                     /*!< UART_TFE (Bit 2)                                      */
-#define UART2_UART2_USR_REG_UART_TFE_Msk  (0x4UL)                   /*!< UART_TFE (Bitfield-Mask: 0x01)                        */
-#define UART2_UART2_USR_REG_UART_TFNF_Pos (1UL)                     /*!< UART_TFNF (Bit 1)                                     */
-#define UART2_UART2_USR_REG_UART_TFNF_Msk (0x2UL)                   /*!< UART_TFNF (Bitfield-Mask: 0x01)                       */
-#define UART2_UART2_USR_REG_UART_BUSY_Pos (0UL)                     /*!< UART_BUSY (Bit 0)                                     */
-#define UART2_UART2_USR_REG_UART_BUSY_Msk (0x1UL)                   /*!< UART_BUSY (Bitfield-Mask: 0x01)                       */
-
-
-/* =========================================================================================================================== */
-/* ================                                           UART3                                           ================ */
-/* =========================================================================================================================== */
-
-/* ===================================================  UART3_CONFIG_REG  ==================================================== */
-#define UART3_UART3_CONFIG_REG_ISO7816_SCRATCH_PAD_Pos (3UL)        /*!< ISO7816_SCRATCH_PAD (Bit 3)                           */
-#define UART3_UART3_CONFIG_REG_ISO7816_SCRATCH_PAD_Msk (0xf8UL)     /*!< ISO7816_SCRATCH_PAD (Bitfield-Mask: 0x1f)             */
-#define UART3_UART3_CONFIG_REG_ISO7816_ENABLE_Pos (2UL)             /*!< ISO7816_ENABLE (Bit 2)                                */
-#define UART3_UART3_CONFIG_REG_ISO7816_ENABLE_Msk (0x4UL)           /*!< ISO7816_ENABLE (Bitfield-Mask: 0x01)                  */
-#define UART3_UART3_CONFIG_REG_ISO7816_ERR_SIG_EN_Pos (1UL)         /*!< ISO7816_ERR_SIG_EN (Bit 1)                            */
-#define UART3_UART3_CONFIG_REG_ISO7816_ERR_SIG_EN_Msk (0x2UL)       /*!< ISO7816_ERR_SIG_EN (Bitfield-Mask: 0x01)              */
-#define UART3_UART3_CONFIG_REG_ISO7816_CONVENTION_Pos (0UL)         /*!< ISO7816_CONVENTION (Bit 0)                            */
-#define UART3_UART3_CONFIG_REG_ISO7816_CONVENTION_Msk (0x1UL)       /*!< ISO7816_CONVENTION (Bitfield-Mask: 0x01)              */
-/* ====================================================  UART3_CTRL_REG  ===================================================== */
-#define UART3_UART3_CTRL_REG_ISO7816_AUTO_GT_Pos (11UL)             /*!< ISO7816_AUTO_GT (Bit 11)                              */
-#define UART3_UART3_CTRL_REG_ISO7816_AUTO_GT_Msk (0x800UL)          /*!< ISO7816_AUTO_GT (Bitfield-Mask: 0x01)                 */
-#define UART3_UART3_CTRL_REG_ISO7816_ERR_TX_VALUE_IRQMASK_Pos (10UL) /*!< ISO7816_ERR_TX_VALUE_IRQMASK (Bit 10)                */
-#define UART3_UART3_CTRL_REG_ISO7816_ERR_TX_VALUE_IRQMASK_Msk (0x400UL) /*!< ISO7816_ERR_TX_VALUE_IRQMASK (Bitfield-Mask: 0x01) */
-#define UART3_UART3_CTRL_REG_ISO7816_ERR_TX_TIME_IRQMASK_Pos (9UL)  /*!< ISO7816_ERR_TX_TIME_IRQMASK (Bit 9)                   */
-#define UART3_UART3_CTRL_REG_ISO7816_ERR_TX_TIME_IRQMASK_Msk (0x200UL) /*!< ISO7816_ERR_TX_TIME_IRQMASK (Bitfield-Mask: 0x01)  */
-#define UART3_UART3_CTRL_REG_ISO7816_TIM_EXPIRED_IRQMASK_Pos (8UL)  /*!< ISO7816_TIM_EXPIRED_IRQMASK (Bit 8)                   */
-#define UART3_UART3_CTRL_REG_ISO7816_TIM_EXPIRED_IRQMASK_Msk (0x100UL) /*!< ISO7816_TIM_EXPIRED_IRQMASK (Bitfield-Mask: 0x01)  */
-#define UART3_UART3_CTRL_REG_ISO7816_CLK_STATUS_Pos (7UL)           /*!< ISO7816_CLK_STATUS (Bit 7)                            */
-#define UART3_UART3_CTRL_REG_ISO7816_CLK_STATUS_Msk (0x80UL)        /*!< ISO7816_CLK_STATUS (Bitfield-Mask: 0x01)              */
-#define UART3_UART3_CTRL_REG_ISO7816_CLK_LEVEL_Pos (6UL)            /*!< ISO7816_CLK_LEVEL (Bit 6)                             */
-#define UART3_UART3_CTRL_REG_ISO7816_CLK_LEVEL_Msk (0x40UL)         /*!< ISO7816_CLK_LEVEL (Bitfield-Mask: 0x01)               */
-#define UART3_UART3_CTRL_REG_ISO7816_CLK_EN_Pos (5UL)               /*!< ISO7816_CLK_EN (Bit 5)                                */
-#define UART3_UART3_CTRL_REG_ISO7816_CLK_EN_Msk (0x20UL)            /*!< ISO7816_CLK_EN (Bitfield-Mask: 0x01)                  */
-#define UART3_UART3_CTRL_REG_ISO7816_CLK_DIV_Pos (0UL)              /*!< ISO7816_CLK_DIV (Bit 0)                               */
-#define UART3_UART3_CTRL_REG_ISO7816_CLK_DIV_Msk (0x1fUL)           /*!< ISO7816_CLK_DIV (Bitfield-Mask: 0x1f)                 */
-/* =====================================================  UART3_CTR_REG  ===================================================== */
-#define UART3_UART3_CTR_REG_UART_CTR_Pos  (0UL)                     /*!< UART_CTR (Bit 0)                                      */
-#define UART3_UART3_CTR_REG_UART_CTR_Msk  (0xffffffffUL)            /*!< UART_CTR (Bitfield-Mask: 0xffffffff)                  */
-/* =====================================================  UART3_DLF_REG  ===================================================== */
-#define UART3_UART3_DLF_REG_UART_DLF_Pos  (0UL)                     /*!< UART_DLF (Bit 0)                                      */
-#define UART3_UART3_DLF_REG_UART_DLF_Msk  (0xfUL)                   /*!< UART_DLF (Bitfield-Mask: 0x0f)                        */
-/* ====================================================  UART3_DMASA_REG  ==================================================== */
-#define UART3_UART3_DMASA_REG_UART_DMASA_Pos (0UL)                  /*!< UART_DMASA (Bit 0)                                    */
-#define UART3_UART3_DMASA_REG_UART_DMASA_Msk (0x1UL)                /*!< UART_DMASA (Bitfield-Mask: 0x01)                      */
-/* ==================================================  UART3_ERR_CTRL_REG  =================================================== */
-#define UART3_UART3_ERR_CTRL_REG_ISO7816_ERR_PULSE_WIDTH_Pos (4UL)  /*!< ISO7816_ERR_PULSE_WIDTH (Bit 4)                       */
-#define UART3_UART3_ERR_CTRL_REG_ISO7816_ERR_PULSE_WIDTH_Msk (0x1f0UL) /*!< ISO7816_ERR_PULSE_WIDTH (Bitfield-Mask: 0x1f)      */
-#define UART3_UART3_ERR_CTRL_REG_ISO7816_ERR_PULSE_OFFSET_Pos (0UL) /*!< ISO7816_ERR_PULSE_OFFSET (Bit 0)                      */
-#define UART3_UART3_ERR_CTRL_REG_ISO7816_ERR_PULSE_OFFSET_Msk (0xfUL) /*!< ISO7816_ERR_PULSE_OFFSET (Bitfield-Mask: 0x0f)      */
-/* =====================================================  UART3_HTX_REG  ===================================================== */
-#define UART3_UART3_HTX_REG_UART_HALT_TX_Pos (0UL)                  /*!< UART_HALT_TX (Bit 0)                                  */
-#define UART3_UART3_HTX_REG_UART_HALT_TX_Msk (0x1UL)                /*!< UART_HALT_TX (Bitfield-Mask: 0x01)                    */
-/* ===================================================  UART3_IER_DLH_REG  =================================================== */
-#define UART3_UART3_IER_DLH_REG_PTIME_DLH7_Pos (7UL)                /*!< PTIME_DLH7 (Bit 7)                                    */
-#define UART3_UART3_IER_DLH_REG_PTIME_DLH7_Msk (0x80UL)             /*!< PTIME_DLH7 (Bitfield-Mask: 0x01)                      */
-#define UART3_UART3_IER_DLH_REG_DLH6_5_Pos (5UL)                    /*!< DLH6_5 (Bit 5)                                        */
-#define UART3_UART3_IER_DLH_REG_DLH6_5_Msk (0x60UL)                 /*!< DLH6_5 (Bitfield-Mask: 0x03)                          */
-#define UART3_UART3_IER_DLH_REG_ELCOLR_DLH4_Pos (4UL)               /*!< ELCOLR_DLH4 (Bit 4)                                   */
-#define UART3_UART3_IER_DLH_REG_ELCOLR_DLH4_Msk (0x10UL)            /*!< ELCOLR_DLH4 (Bitfield-Mask: 0x01)                     */
-#define UART3_UART3_IER_DLH_REG_EDSSI_DLH3_Pos (3UL)                /*!< EDSSI_DLH3 (Bit 3)                                    */
-#define UART3_UART3_IER_DLH_REG_EDSSI_DLH3_Msk (0x8UL)              /*!< EDSSI_DLH3 (Bitfield-Mask: 0x01)                      */
-#define UART3_UART3_IER_DLH_REG_ELSI_DLH2_Pos (2UL)                 /*!< ELSI_DLH2 (Bit 2)                                     */
-#define UART3_UART3_IER_DLH_REG_ELSI_DLH2_Msk (0x4UL)               /*!< ELSI_DLH2 (Bitfield-Mask: 0x01)                       */
-#define UART3_UART3_IER_DLH_REG_ETBEI_DLH1_Pos (1UL)                /*!< ETBEI_DLH1 (Bit 1)                                    */
-#define UART3_UART3_IER_DLH_REG_ETBEI_DLH1_Msk (0x2UL)              /*!< ETBEI_DLH1 (Bitfield-Mask: 0x01)                      */
-#define UART3_UART3_IER_DLH_REG_ERBFI_DLH0_Pos (0UL)                /*!< ERBFI_DLH0 (Bit 0)                                    */
-#define UART3_UART3_IER_DLH_REG_ERBFI_DLH0_Msk (0x1UL)              /*!< ERBFI_DLH0 (Bitfield-Mask: 0x01)                      */
-/* ===================================================  UART3_IIR_FCR_REG  =================================================== */
-#define UART3_UART3_IIR_FCR_REG_IIR_FCR_Pos (0UL)                   /*!< IIR_FCR (Bit 0)                                       */
-#define UART3_UART3_IIR_FCR_REG_IIR_FCR_Msk (0xffUL)                /*!< IIR_FCR (Bitfield-Mask: 0xff)                         */
-/* =================================================  UART3_IRQ_STATUS_REG  ================================================== */
-#define UART3_UART3_IRQ_STATUS_REG_ISO7816_ERR_TX_VALUE_IRQ_Pos (2UL) /*!< ISO7816_ERR_TX_VALUE_IRQ (Bit 2)                    */
-#define UART3_UART3_IRQ_STATUS_REG_ISO7816_ERR_TX_VALUE_IRQ_Msk (0x4UL) /*!< ISO7816_ERR_TX_VALUE_IRQ (Bitfield-Mask: 0x01)    */
-#define UART3_UART3_IRQ_STATUS_REG_ISO7816_ERR_TX_TIME_IRQ_Pos (1UL) /*!< ISO7816_ERR_TX_TIME_IRQ (Bit 1)                      */
-#define UART3_UART3_IRQ_STATUS_REG_ISO7816_ERR_TX_TIME_IRQ_Msk (0x2UL) /*!< ISO7816_ERR_TX_TIME_IRQ (Bitfield-Mask: 0x01)      */
-#define UART3_UART3_IRQ_STATUS_REG_ISO7816_TIM_EXPIRED_IRQ_Pos (0UL) /*!< ISO7816_TIM_EXPIRED_IRQ (Bit 0)                      */
-#define UART3_UART3_IRQ_STATUS_REG_ISO7816_TIM_EXPIRED_IRQ_Msk (0x1UL) /*!< ISO7816_TIM_EXPIRED_IRQ (Bitfield-Mask: 0x01)      */
-/* =====================================================  UART3_LCR_EXT  ===================================================== */
-#define UART3_UART3_LCR_EXT_UART_TRANSMIT_MODE_Pos (3UL)            /*!< UART_TRANSMIT_MODE (Bit 3)                            */
-#define UART3_UART3_LCR_EXT_UART_TRANSMIT_MODE_Msk (0x8UL)          /*!< UART_TRANSMIT_MODE (Bitfield-Mask: 0x01)              */
-#define UART3_UART3_LCR_EXT_UART_SEND_ADDR_Pos (2UL)                /*!< UART_SEND_ADDR (Bit 2)                                */
-#define UART3_UART3_LCR_EXT_UART_SEND_ADDR_Msk (0x4UL)              /*!< UART_SEND_ADDR (Bitfield-Mask: 0x01)                  */
-#define UART3_UART3_LCR_EXT_UART_ADDR_MATCH_Pos (1UL)               /*!< UART_ADDR_MATCH (Bit 1)                               */
-#define UART3_UART3_LCR_EXT_UART_ADDR_MATCH_Msk (0x2UL)             /*!< UART_ADDR_MATCH (Bitfield-Mask: 0x01)                 */
-#define UART3_UART3_LCR_EXT_UART_DLS_E_Pos (0UL)                    /*!< UART_DLS_E (Bit 0)                                    */
-#define UART3_UART3_LCR_EXT_UART_DLS_E_Msk (0x1UL)                  /*!< UART_DLS_E (Bitfield-Mask: 0x01)                      */
-/* =====================================================  UART3_LCR_REG  ===================================================== */
-#define UART3_UART3_LCR_REG_UART_DLAB_Pos (7UL)                     /*!< UART_DLAB (Bit 7)                                     */
-#define UART3_UART3_LCR_REG_UART_DLAB_Msk (0x80UL)                  /*!< UART_DLAB (Bitfield-Mask: 0x01)                       */
-#define UART3_UART3_LCR_REG_UART_BC_Pos   (6UL)                     /*!< UART_BC (Bit 6)                                       */
-#define UART3_UART3_LCR_REG_UART_BC_Msk   (0x40UL)                  /*!< UART_BC (Bitfield-Mask: 0x01)                         */
-#define UART3_UART3_LCR_REG_UART_SP_Pos   (5UL)                     /*!< UART_SP (Bit 5)                                       */
-#define UART3_UART3_LCR_REG_UART_SP_Msk   (0x20UL)                  /*!< UART_SP (Bitfield-Mask: 0x01)                         */
-#define UART3_UART3_LCR_REG_UART_EPS_Pos  (4UL)                     /*!< UART_EPS (Bit 4)                                      */
-#define UART3_UART3_LCR_REG_UART_EPS_Msk  (0x10UL)                  /*!< UART_EPS (Bitfield-Mask: 0x01)                        */
-#define UART3_UART3_LCR_REG_UART_PEN_Pos  (3UL)                     /*!< UART_PEN (Bit 3)                                      */
-#define UART3_UART3_LCR_REG_UART_PEN_Msk  (0x8UL)                   /*!< UART_PEN (Bitfield-Mask: 0x01)                        */
-#define UART3_UART3_LCR_REG_UART_STOP_Pos (2UL)                     /*!< UART_STOP (Bit 2)                                     */
-#define UART3_UART3_LCR_REG_UART_STOP_Msk (0x4UL)                   /*!< UART_STOP (Bitfield-Mask: 0x01)                       */
-#define UART3_UART3_LCR_REG_UART_DLS_Pos  (0UL)                     /*!< UART_DLS (Bit 0)                                      */
-#define UART3_UART3_LCR_REG_UART_DLS_Msk  (0x3UL)                   /*!< UART_DLS (Bitfield-Mask: 0x03)                        */
-/* =====================================================  UART3_LSR_REG  ===================================================== */
-#define UART3_UART3_LSR_REG_UART_ADDR_RCVD_Pos (8UL)                /*!< UART_ADDR_RCVD (Bit 8)                                */
-#define UART3_UART3_LSR_REG_UART_ADDR_RCVD_Msk (0x100UL)            /*!< UART_ADDR_RCVD (Bitfield-Mask: 0x01)                  */
-#define UART3_UART3_LSR_REG_UART_RFE_Pos  (7UL)                     /*!< UART_RFE (Bit 7)                                      */
-#define UART3_UART3_LSR_REG_UART_RFE_Msk  (0x80UL)                  /*!< UART_RFE (Bitfield-Mask: 0x01)                        */
-#define UART3_UART3_LSR_REG_UART_TEMT_Pos (6UL)                     /*!< UART_TEMT (Bit 6)                                     */
-#define UART3_UART3_LSR_REG_UART_TEMT_Msk (0x40UL)                  /*!< UART_TEMT (Bitfield-Mask: 0x01)                       */
-#define UART3_UART3_LSR_REG_UART_THRE_Pos (5UL)                     /*!< UART_THRE (Bit 5)                                     */
-#define UART3_UART3_LSR_REG_UART_THRE_Msk (0x20UL)                  /*!< UART_THRE (Bitfield-Mask: 0x01)                       */
-#define UART3_UART3_LSR_REG_UART_BI_Pos   (4UL)                     /*!< UART_BI (Bit 4)                                       */
-#define UART3_UART3_LSR_REG_UART_BI_Msk   (0x10UL)                  /*!< UART_BI (Bitfield-Mask: 0x01)                         */
-#define UART3_UART3_LSR_REG_UART_FE_Pos   (3UL)                     /*!< UART_FE (Bit 3)                                       */
-#define UART3_UART3_LSR_REG_UART_FE_Msk   (0x8UL)                   /*!< UART_FE (Bitfield-Mask: 0x01)                         */
-#define UART3_UART3_LSR_REG_UART_PE_Pos   (2UL)                     /*!< UART_PE (Bit 2)                                       */
-#define UART3_UART3_LSR_REG_UART_PE_Msk   (0x4UL)                   /*!< UART_PE (Bitfield-Mask: 0x01)                         */
-#define UART3_UART3_LSR_REG_UART_OE_Pos   (1UL)                     /*!< UART_OE (Bit 1)                                       */
-#define UART3_UART3_LSR_REG_UART_OE_Msk   (0x2UL)                   /*!< UART_OE (Bitfield-Mask: 0x01)                         */
-#define UART3_UART3_LSR_REG_UART_DR_Pos   (0UL)                     /*!< UART_DR (Bit 0)                                       */
-#define UART3_UART3_LSR_REG_UART_DR_Msk   (0x1UL)                   /*!< UART_DR (Bitfield-Mask: 0x01)                         */
-/* =====================================================  UART3_MCR_REG  ===================================================== */
-#define UART3_UART3_MCR_REG_UART_AFCE_Pos (5UL)                     /*!< UART_AFCE (Bit 5)                                     */
-#define UART3_UART3_MCR_REG_UART_AFCE_Msk (0x20UL)                  /*!< UART_AFCE (Bitfield-Mask: 0x01)                       */
-#define UART3_UART3_MCR_REG_UART_LB_Pos   (4UL)                     /*!< UART_LB (Bit 4)                                       */
-#define UART3_UART3_MCR_REG_UART_LB_Msk   (0x10UL)                  /*!< UART_LB (Bitfield-Mask: 0x01)                         */
-#define UART3_UART3_MCR_REG_UART_RTS_Pos  (1UL)                     /*!< UART_RTS (Bit 1)                                      */
-#define UART3_UART3_MCR_REG_UART_RTS_Msk  (0x2UL)                   /*!< UART_RTS (Bitfield-Mask: 0x01)                        */
-/* =====================================================  UART3_MSR_REG  ===================================================== */
-#define UART3_UART3_MSR_REG_UART_CTS_Pos  (4UL)                     /*!< UART_CTS (Bit 4)                                      */
-#define UART3_UART3_MSR_REG_UART_CTS_Msk  (0x10UL)                  /*!< UART_CTS (Bitfield-Mask: 0x01)                        */
-#define UART3_UART3_MSR_REG_UART_DCTS_Pos (0UL)                     /*!< UART_DCTS (Bit 0)                                     */
-#define UART3_UART3_MSR_REG_UART_DCTS_Msk (0x1UL)                   /*!< UART_DCTS (Bitfield-Mask: 0x01)                       */
-/* =====================================================  UART3_RAR_REG  ===================================================== */
-#define UART3_UART3_RAR_REG_UART_RAR_Pos  (0UL)                     /*!< UART_RAR (Bit 0)                                      */
-#define UART3_UART3_RAR_REG_UART_RAR_Msk  (0xffUL)                  /*!< UART_RAR (Bitfield-Mask: 0xff)                        */
-/* =================================================  UART3_RBR_THR_DLL_REG  ================================================= */
-#define UART3_UART3_RBR_THR_DLL_REG_RBR_THR_9BIT_Pos (8UL)          /*!< RBR_THR_9BIT (Bit 8)                                  */
-#define UART3_UART3_RBR_THR_DLL_REG_RBR_THR_9BIT_Msk (0x100UL)      /*!< RBR_THR_9BIT (Bitfield-Mask: 0x01)                    */
-#define UART3_UART3_RBR_THR_DLL_REG_RBR_THR_DLL_Pos (0UL)           /*!< RBR_THR_DLL (Bit 0)                                   */
-#define UART3_UART3_RBR_THR_DLL_REG_RBR_THR_DLL_Msk (0xffUL)        /*!< RBR_THR_DLL (Bitfield-Mask: 0xff)                     */
-/* =====================================================  UART3_RFL_REG  ===================================================== */
-#define UART3_UART3_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Pos (0UL)       /*!< UART_RECEIVE_FIFO_LEVEL (Bit 0)                       */
-#define UART3_UART3_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Msk (0x1fUL)    /*!< UART_RECEIVE_FIFO_LEVEL (Bitfield-Mask: 0x1f)         */
-/* ====================================================  UART3_SBCR_REG  ===================================================== */
-#define UART3_UART3_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Pos (0UL)    /*!< UART_SHADOW_BREAK_CONTROL (Bit 0)                     */
-#define UART3_UART3_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Msk (0x1UL)  /*!< UART_SHADOW_BREAK_CONTROL (Bitfield-Mask: 0x01)       */
-/* ====================================================  UART3_SDMAM_REG  ==================================================== */
-#define UART3_UART3_SDMAM_REG_UART_SHADOW_DMA_MODE_Pos (0UL)        /*!< UART_SHADOW_DMA_MODE (Bit 0)                          */
-#define UART3_UART3_SDMAM_REG_UART_SHADOW_DMA_MODE_Msk (0x1UL)      /*!< UART_SHADOW_DMA_MODE (Bitfield-Mask: 0x01)            */
-/* =====================================================  UART3_SFE_REG  ===================================================== */
-#define UART3_UART3_SFE_REG_UART_SHADOW_FIFO_ENABLE_Pos (0UL)       /*!< UART_SHADOW_FIFO_ENABLE (Bit 0)                       */
-#define UART3_UART3_SFE_REG_UART_SHADOW_FIFO_ENABLE_Msk (0x1UL)     /*!< UART_SHADOW_FIFO_ENABLE (Bitfield-Mask: 0x01)         */
-/* =================================================  UART3_SRBR_STHR0_REG  ================================================== */
-#define UART3_UART3_SRBR_STHR0_REG_SRBR_STHRx_Pos (0UL)             /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART3_UART3_SRBR_STHR0_REG_SRBR_STHRx_Msk (0xffUL)          /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART3_SRBR_STHR10_REG  ================================================= */
-#define UART3_UART3_SRBR_STHR10_REG_SRBR_STHRx_Pos (0UL)            /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART3_UART3_SRBR_STHR10_REG_SRBR_STHRx_Msk (0xffUL)         /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART3_SRBR_STHR11_REG  ================================================= */
-#define UART3_UART3_SRBR_STHR11_REG_SRBR_STHRx_Pos (0UL)            /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART3_UART3_SRBR_STHR11_REG_SRBR_STHRx_Msk (0xffUL)         /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART3_SRBR_STHR12_REG  ================================================= */
-#define UART3_UART3_SRBR_STHR12_REG_SRBR_STHRx_Pos (0UL)            /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART3_UART3_SRBR_STHR12_REG_SRBR_STHRx_Msk (0xffUL)         /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART3_SRBR_STHR13_REG  ================================================= */
-#define UART3_UART3_SRBR_STHR13_REG_SRBR_STHRx_Pos (0UL)            /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART3_UART3_SRBR_STHR13_REG_SRBR_STHRx_Msk (0xffUL)         /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART3_SRBR_STHR14_REG  ================================================= */
-#define UART3_UART3_SRBR_STHR14_REG_SRBR_STHRx_Pos (0UL)            /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART3_UART3_SRBR_STHR14_REG_SRBR_STHRx_Msk (0xffUL)         /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART3_SRBR_STHR15_REG  ================================================= */
-#define UART3_UART3_SRBR_STHR15_REG_SRBR_STHRx_Pos (0UL)            /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART3_UART3_SRBR_STHR15_REG_SRBR_STHRx_Msk (0xffUL)         /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART3_SRBR_STHR1_REG  ================================================== */
-#define UART3_UART3_SRBR_STHR1_REG_SRBR_STHRx_Pos (0UL)             /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART3_UART3_SRBR_STHR1_REG_SRBR_STHRx_Msk (0xffUL)          /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART3_SRBR_STHR2_REG  ================================================== */
-#define UART3_UART3_SRBR_STHR2_REG_SRBR_STHRx_Pos (0UL)             /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART3_UART3_SRBR_STHR2_REG_SRBR_STHRx_Msk (0xffUL)          /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART3_SRBR_STHR3_REG  ================================================== */
-#define UART3_UART3_SRBR_STHR3_REG_SRBR_STHRx_Pos (0UL)             /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART3_UART3_SRBR_STHR3_REG_SRBR_STHRx_Msk (0xffUL)          /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART3_SRBR_STHR4_REG  ================================================== */
-#define UART3_UART3_SRBR_STHR4_REG_SRBR_STHRx_Pos (0UL)             /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART3_UART3_SRBR_STHR4_REG_SRBR_STHRx_Msk (0xffUL)          /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART3_SRBR_STHR5_REG  ================================================== */
-#define UART3_UART3_SRBR_STHR5_REG_SRBR_STHRx_Pos (0UL)             /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART3_UART3_SRBR_STHR5_REG_SRBR_STHRx_Msk (0xffUL)          /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART3_SRBR_STHR6_REG  ================================================== */
-#define UART3_UART3_SRBR_STHR6_REG_SRBR_STHRx_Pos (0UL)             /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART3_UART3_SRBR_STHR6_REG_SRBR_STHRx_Msk (0xffUL)          /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART3_SRBR_STHR7_REG  ================================================== */
-#define UART3_UART3_SRBR_STHR7_REG_SRBR_STHRx_Pos (0UL)             /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART3_UART3_SRBR_STHR7_REG_SRBR_STHRx_Msk (0xffUL)          /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART3_SRBR_STHR8_REG  ================================================== */
-#define UART3_UART3_SRBR_STHR8_REG_SRBR_STHRx_Pos (0UL)             /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART3_UART3_SRBR_STHR8_REG_SRBR_STHRx_Msk (0xffUL)          /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =================================================  UART3_SRBR_STHR9_REG  ================================================== */
-#define UART3_UART3_SRBR_STHR9_REG_SRBR_STHRx_Pos (0UL)             /*!< SRBR_STHRx (Bit 0)                                    */
-#define UART3_UART3_SRBR_STHR9_REG_SRBR_STHRx_Msk (0xffUL)          /*!< SRBR_STHRx (Bitfield-Mask: 0xff)                      */
-/* =====================================================  UART3_SRR_REG  ===================================================== */
-#define UART3_UART3_SRR_REG_UART_XFR_Pos  (2UL)                     /*!< UART_XFR (Bit 2)                                      */
-#define UART3_UART3_SRR_REG_UART_XFR_Msk  (0x4UL)                   /*!< UART_XFR (Bitfield-Mask: 0x01)                        */
-#define UART3_UART3_SRR_REG_UART_RFR_Pos  (1UL)                     /*!< UART_RFR (Bit 1)                                      */
-#define UART3_UART3_SRR_REG_UART_RFR_Msk  (0x2UL)                   /*!< UART_RFR (Bitfield-Mask: 0x01)                        */
-#define UART3_UART3_SRR_REG_UART_UR_Pos   (0UL)                     /*!< UART_UR (Bit 0)                                       */
-#define UART3_UART3_SRR_REG_UART_UR_Msk   (0x1UL)                   /*!< UART_UR (Bitfield-Mask: 0x01)                         */
-/* ====================================================  UART3_SRTS_REG  ===================================================== */
-#define UART3_UART3_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Pos (0UL)  /*!< UART_SHADOW_REQUEST_TO_SEND (Bit 0)                   */
-#define UART3_UART3_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Msk (0x1UL) /*!< UART_SHADOW_REQUEST_TO_SEND (Bitfield-Mask: 0x01)    */
-/* =====================================================  UART3_SRT_REG  ===================================================== */
-#define UART3_UART3_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Pos (0UL)      /*!< UART_SHADOW_RCVR_TRIGGER (Bit 0)                      */
-#define UART3_UART3_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Msk (0x3UL)    /*!< UART_SHADOW_RCVR_TRIGGER (Bitfield-Mask: 0x03)        */
-/* ====================================================  UART3_STET_REG  ===================================================== */
-#define UART3_UART3_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Pos (0UL) /*!< UART_SHADOW_TX_EMPTY_TRIGGER (Bit 0)                  */
-#define UART3_UART3_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Msk (0x3UL) /*!< UART_SHADOW_TX_EMPTY_TRIGGER (Bitfield-Mask: 0x03)  */
-/* =====================================================  UART3_TAR_REG  ===================================================== */
-#define UART3_UART3_TAR_REG_UART_TAR_Pos  (0UL)                     /*!< UART_TAR (Bit 0)                                      */
-#define UART3_UART3_TAR_REG_UART_TAR_Msk  (0xffUL)                  /*!< UART_TAR (Bitfield-Mask: 0xff)                        */
-/* =====================================================  UART3_TFL_REG  ===================================================== */
-#define UART3_UART3_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Pos (0UL)      /*!< UART_TRANSMIT_FIFO_LEVEL (Bit 0)                      */
-#define UART3_UART3_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Msk (0x1fUL)   /*!< UART_TRANSMIT_FIFO_LEVEL (Bitfield-Mask: 0x1f)        */
-/* ====================================================  UART3_TIMER_REG  ==================================================== */
-#define UART3_UART3_TIMER_REG_ISO7816_TIM_MODE_Pos (17UL)           /*!< ISO7816_TIM_MODE (Bit 17)                             */
-#define UART3_UART3_TIMER_REG_ISO7816_TIM_MODE_Msk (0x20000UL)      /*!< ISO7816_TIM_MODE (Bitfield-Mask: 0x01)                */
-#define UART3_UART3_TIMER_REG_ISO7816_TIM_EN_Pos (16UL)             /*!< ISO7816_TIM_EN (Bit 16)                               */
-#define UART3_UART3_TIMER_REG_ISO7816_TIM_EN_Msk (0x10000UL)        /*!< ISO7816_TIM_EN (Bitfield-Mask: 0x01)                  */
-#define UART3_UART3_TIMER_REG_ISO7816_TIM_MAX_Pos (0UL)             /*!< ISO7816_TIM_MAX (Bit 0)                               */
-#define UART3_UART3_TIMER_REG_ISO7816_TIM_MAX_Msk (0xffffUL)        /*!< ISO7816_TIM_MAX (Bitfield-Mask: 0xffff)               */
-/* =====================================================  UART3_UCV_REG  ===================================================== */
-#define UART3_UART3_UCV_REG_UART_UCV_Pos  (0UL)                     /*!< UART_UCV (Bit 0)                                      */
-#define UART3_UART3_UCV_REG_UART_UCV_Msk  (0xffffffffUL)            /*!< UART_UCV (Bitfield-Mask: 0xffffffff)                  */
-/* =====================================================  UART3_USR_REG  ===================================================== */
-#define UART3_UART3_USR_REG_UART_RFF_Pos  (4UL)                     /*!< UART_RFF (Bit 4)                                      */
-#define UART3_UART3_USR_REG_UART_RFF_Msk  (0x10UL)                  /*!< UART_RFF (Bitfield-Mask: 0x01)                        */
-#define UART3_UART3_USR_REG_UART_RFNE_Pos (3UL)                     /*!< UART_RFNE (Bit 3)                                     */
-#define UART3_UART3_USR_REG_UART_RFNE_Msk (0x8UL)                   /*!< UART_RFNE (Bitfield-Mask: 0x01)                       */
-#define UART3_UART3_USR_REG_UART_TFE_Pos  (2UL)                     /*!< UART_TFE (Bit 2)                                      */
-#define UART3_UART3_USR_REG_UART_TFE_Msk  (0x4UL)                   /*!< UART_TFE (Bitfield-Mask: 0x01)                        */
-#define UART3_UART3_USR_REG_UART_TFNF_Pos (1UL)                     /*!< UART_TFNF (Bit 1)                                     */
-#define UART3_UART3_USR_REG_UART_TFNF_Msk (0x2UL)                   /*!< UART_TFNF (Bitfield-Mask: 0x01)                       */
-#define UART3_UART3_USR_REG_UART_BUSY_Pos (0UL)                     /*!< UART_BUSY (Bit 0)                                     */
-#define UART3_UART3_USR_REG_UART_BUSY_Msk (0x1UL)                   /*!< UART_BUSY (Bitfield-Mask: 0x01)                       */
-
-
-/* =========================================================================================================================== */
-/* ================                                            USB                                            ================ */
-/* =========================================================================================================================== */
-
-/* =====================================================  USB_ALTEV_REG  ===================================================== */
-#define USB_USB_ALTEV_REG_USB_RESUME_Pos  (7UL)                     /*!< USB_RESUME (Bit 7)                                    */
-#define USB_USB_ALTEV_REG_USB_RESUME_Msk  (0x80UL)                  /*!< USB_RESUME (Bitfield-Mask: 0x01)                      */
-#define USB_USB_ALTEV_REG_USB_RESET_Pos   (6UL)                     /*!< USB_RESET (Bit 6)                                     */
-#define USB_USB_ALTEV_REG_USB_RESET_Msk   (0x40UL)                  /*!< USB_RESET (Bitfield-Mask: 0x01)                       */
-#define USB_USB_ALTEV_REG_USB_SD5_Pos     (5UL)                     /*!< USB_SD5 (Bit 5)                                       */
-#define USB_USB_ALTEV_REG_USB_SD5_Msk     (0x20UL)                  /*!< USB_SD5 (Bitfield-Mask: 0x01)                         */
-#define USB_USB_ALTEV_REG_USB_SD3_Pos     (4UL)                     /*!< USB_SD3 (Bit 4)                                       */
-#define USB_USB_ALTEV_REG_USB_SD3_Msk     (0x10UL)                  /*!< USB_SD3 (Bitfield-Mask: 0x01)                         */
-#define USB_USB_ALTEV_REG_USB_EOP_Pos     (3UL)                     /*!< USB_EOP (Bit 3)                                       */
-#define USB_USB_ALTEV_REG_USB_EOP_Msk     (0x8UL)                   /*!< USB_EOP (Bitfield-Mask: 0x01)                         */
-/* ====================================================  USB_ALTMSK_REG  ===================================================== */
-#define USB_USB_ALTMSK_REG_USB_M_RESUME_Pos (7UL)                   /*!< USB_M_RESUME (Bit 7)                                  */
-#define USB_USB_ALTMSK_REG_USB_M_RESUME_Msk (0x80UL)                /*!< USB_M_RESUME (Bitfield-Mask: 0x01)                    */
-#define USB_USB_ALTMSK_REG_USB_M_RESET_Pos (6UL)                    /*!< USB_M_RESET (Bit 6)                                   */
-#define USB_USB_ALTMSK_REG_USB_M_RESET_Msk (0x40UL)                 /*!< USB_M_RESET (Bitfield-Mask: 0x01)                     */
-#define USB_USB_ALTMSK_REG_USB_M_SD5_Pos  (5UL)                     /*!< USB_M_SD5 (Bit 5)                                     */
-#define USB_USB_ALTMSK_REG_USB_M_SD5_Msk  (0x20UL)                  /*!< USB_M_SD5 (Bitfield-Mask: 0x01)                       */
-#define USB_USB_ALTMSK_REG_USB_M_SD3_Pos  (4UL)                     /*!< USB_M_SD3 (Bit 4)                                     */
-#define USB_USB_ALTMSK_REG_USB_M_SD3_Msk  (0x10UL)                  /*!< USB_M_SD3 (Bitfield-Mask: 0x01)                       */
-#define USB_USB_ALTMSK_REG_USB_M_EOP_Pos  (3UL)                     /*!< USB_M_EOP (Bit 3)                                     */
-#define USB_USB_ALTMSK_REG_USB_M_EOP_Msk  (0x8UL)                   /*!< USB_M_EOP (Bitfield-Mask: 0x01)                       */
-/* =================================================  USB_CHARGER_CTRL_REG  ================================================== */
-#define USB_USB_CHARGER_CTRL_REG_IDM_SINK_ON_Pos (5UL)              /*!< IDM_SINK_ON (Bit 5)                                   */
-#define USB_USB_CHARGER_CTRL_REG_IDM_SINK_ON_Msk (0x20UL)           /*!< IDM_SINK_ON (Bitfield-Mask: 0x01)                     */
-#define USB_USB_CHARGER_CTRL_REG_IDP_SINK_ON_Pos (4UL)              /*!< IDP_SINK_ON (Bit 4)                                   */
-#define USB_USB_CHARGER_CTRL_REG_IDP_SINK_ON_Msk (0x10UL)           /*!< IDP_SINK_ON (Bitfield-Mask: 0x01)                     */
-#define USB_USB_CHARGER_CTRL_REG_VDM_SRC_ON_Pos (3UL)               /*!< VDM_SRC_ON (Bit 3)                                    */
-#define USB_USB_CHARGER_CTRL_REG_VDM_SRC_ON_Msk (0x8UL)             /*!< VDM_SRC_ON (Bitfield-Mask: 0x01)                      */
-#define USB_USB_CHARGER_CTRL_REG_VDP_SRC_ON_Pos (2UL)               /*!< VDP_SRC_ON (Bit 2)                                    */
-#define USB_USB_CHARGER_CTRL_REG_VDP_SRC_ON_Msk (0x4UL)             /*!< VDP_SRC_ON (Bitfield-Mask: 0x01)                      */
-#define USB_USB_CHARGER_CTRL_REG_IDP_SRC_ON_Pos (1UL)               /*!< IDP_SRC_ON (Bit 1)                                    */
-#define USB_USB_CHARGER_CTRL_REG_IDP_SRC_ON_Msk (0x2UL)             /*!< IDP_SRC_ON (Bitfield-Mask: 0x01)                      */
-#define USB_USB_CHARGER_CTRL_REG_USB_CHARGE_ON_Pos (0UL)            /*!< USB_CHARGE_ON (Bit 0)                                 */
-#define USB_USB_CHARGER_CTRL_REG_USB_CHARGE_ON_Msk (0x1UL)          /*!< USB_CHARGE_ON (Bitfield-Mask: 0x01)                   */
-/* =================================================  USB_CHARGER_STAT_REG  ================================================== */
-#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL2_Pos (5UL)              /*!< USB_DM_VAL2 (Bit 5)                                   */
-#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL2_Msk (0x20UL)           /*!< USB_DM_VAL2 (Bitfield-Mask: 0x01)                     */
-#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL2_Pos (4UL)              /*!< USB_DP_VAL2 (Bit 4)                                   */
-#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL2_Msk (0x10UL)           /*!< USB_DP_VAL2 (Bitfield-Mask: 0x01)                     */
-#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL_Pos (3UL)               /*!< USB_DM_VAL (Bit 3)                                    */
-#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL_Msk (0x8UL)             /*!< USB_DM_VAL (Bitfield-Mask: 0x01)                      */
-#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL_Pos (2UL)               /*!< USB_DP_VAL (Bit 2)                                    */
-#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL_Msk (0x4UL)             /*!< USB_DP_VAL (Bitfield-Mask: 0x01)                      */
-#define USB_USB_CHARGER_STAT_REG_USB_CHG_DET_Pos (1UL)              /*!< USB_CHG_DET (Bit 1)                                   */
-#define USB_USB_CHARGER_STAT_REG_USB_CHG_DET_Msk (0x2UL)            /*!< USB_CHG_DET (Bitfield-Mask: 0x01)                     */
-#define USB_USB_CHARGER_STAT_REG_USB_DCP_DET_Pos (0UL)              /*!< USB_DCP_DET (Bit 0)                                   */
-#define USB_USB_CHARGER_STAT_REG_USB_DCP_DET_Msk (0x1UL)            /*!< USB_DCP_DET (Bitfield-Mask: 0x01)                     */
-/* ===================================================  USB_DMA_CTRL_REG  ==================================================== */
-#define USB_USB_DMA_CTRL_REG_USB_DMA_EN_Pos (6UL)                   /*!< USB_DMA_EN (Bit 6)                                    */
-#define USB_USB_DMA_CTRL_REG_USB_DMA_EN_Msk (0x40UL)                /*!< USB_DMA_EN (Bitfield-Mask: 0x01)                      */
-#define USB_USB_DMA_CTRL_REG_USB_DMA_TX_Pos (3UL)                   /*!< USB_DMA_TX (Bit 3)                                    */
-#define USB_USB_DMA_CTRL_REG_USB_DMA_TX_Msk (0x38UL)                /*!< USB_DMA_TX (Bitfield-Mask: 0x07)                      */
-#define USB_USB_DMA_CTRL_REG_USB_DMA_RX_Pos (0UL)                   /*!< USB_DMA_RX (Bit 0)                                    */
-#define USB_USB_DMA_CTRL_REG_USB_DMA_RX_Msk (0x7UL)                 /*!< USB_DMA_RX (Bitfield-Mask: 0x07)                      */
-/* ====================================================  USB_EP0_NAK_REG  ==================================================== */
-#define USB_USB_EP0_NAK_REG_USB_EP0_OUTNAK_Pos (1UL)                /*!< USB_EP0_OUTNAK (Bit 1)                                */
-#define USB_USB_EP0_NAK_REG_USB_EP0_OUTNAK_Msk (0x2UL)              /*!< USB_EP0_OUTNAK (Bitfield-Mask: 0x01)                  */
-#define USB_USB_EP0_NAK_REG_USB_EP0_INNAK_Pos (0UL)                 /*!< USB_EP0_INNAK (Bit 0)                                 */
-#define USB_USB_EP0_NAK_REG_USB_EP0_INNAK_Msk (0x1UL)               /*!< USB_EP0_INNAK (Bitfield-Mask: 0x01)                   */
-/* =====================================================  USB_EPC0_REG  ====================================================== */
-#define USB_USB_EPC0_REG_USB_STALL_Pos    (7UL)                     /*!< USB_STALL (Bit 7)                                     */
-#define USB_USB_EPC0_REG_USB_STALL_Msk    (0x80UL)                  /*!< USB_STALL (Bitfield-Mask: 0x01)                       */
-#define USB_USB_EPC0_REG_USB_DEF_Pos      (6UL)                     /*!< USB_DEF (Bit 6)                                       */
-#define USB_USB_EPC0_REG_USB_DEF_Msk      (0x40UL)                  /*!< USB_DEF (Bitfield-Mask: 0x01)                         */
-#define USB_USB_EPC0_REG_USB_EP_Pos       (0UL)                     /*!< USB_EP (Bit 0)                                        */
-#define USB_USB_EPC0_REG_USB_EP_Msk       (0xfUL)                   /*!< USB_EP (Bitfield-Mask: 0x0f)                          */
-/* =====================================================  USB_EPC1_REG  ====================================================== */
-#define USB_USB_EPC1_REG_USB_STALL_Pos    (7UL)                     /*!< USB_STALL (Bit 7)                                     */
-#define USB_USB_EPC1_REG_USB_STALL_Msk    (0x80UL)                  /*!< USB_STALL (Bitfield-Mask: 0x01)                       */
-#define USB_USB_EPC1_REG_USB_ISO_Pos      (5UL)                     /*!< USB_ISO (Bit 5)                                       */
-#define USB_USB_EPC1_REG_USB_ISO_Msk      (0x20UL)                  /*!< USB_ISO (Bitfield-Mask: 0x01)                         */
-#define USB_USB_EPC1_REG_USB_EP_EN_Pos    (4UL)                     /*!< USB_EP_EN (Bit 4)                                     */
-#define USB_USB_EPC1_REG_USB_EP_EN_Msk    (0x10UL)                  /*!< USB_EP_EN (Bitfield-Mask: 0x01)                       */
-#define USB_USB_EPC1_REG_USB_EP_Pos       (0UL)                     /*!< USB_EP (Bit 0)                                        */
-#define USB_USB_EPC1_REG_USB_EP_Msk       (0xfUL)                   /*!< USB_EP (Bitfield-Mask: 0x0f)                          */
-/* =====================================================  USB_EPC2_REG  ====================================================== */
-#define USB_USB_EPC2_REG_USB_STALL_Pos    (7UL)                     /*!< USB_STALL (Bit 7)                                     */
-#define USB_USB_EPC2_REG_USB_STALL_Msk    (0x80UL)                  /*!< USB_STALL (Bitfield-Mask: 0x01)                       */
-#define USB_USB_EPC2_REG_USB_ISO_Pos      (5UL)                     /*!< USB_ISO (Bit 5)                                       */
-#define USB_USB_EPC2_REG_USB_ISO_Msk      (0x20UL)                  /*!< USB_ISO (Bitfield-Mask: 0x01)                         */
-#define USB_USB_EPC2_REG_USB_EP_EN_Pos    (4UL)                     /*!< USB_EP_EN (Bit 4)                                     */
-#define USB_USB_EPC2_REG_USB_EP_EN_Msk    (0x10UL)                  /*!< USB_EP_EN (Bitfield-Mask: 0x01)                       */
-#define USB_USB_EPC2_REG_USB_EP_Pos       (0UL)                     /*!< USB_EP (Bit 0)                                        */
-#define USB_USB_EPC2_REG_USB_EP_Msk       (0xfUL)                   /*!< USB_EP (Bitfield-Mask: 0x0f)                          */
-/* =====================================================  USB_EPC3_REG  ====================================================== */
-#define USB_USB_EPC3_REG_USB_STALL_Pos    (7UL)                     /*!< USB_STALL (Bit 7)                                     */
-#define USB_USB_EPC3_REG_USB_STALL_Msk    (0x80UL)                  /*!< USB_STALL (Bitfield-Mask: 0x01)                       */
-#define USB_USB_EPC3_REG_USB_ISO_Pos      (5UL)                     /*!< USB_ISO (Bit 5)                                       */
-#define USB_USB_EPC3_REG_USB_ISO_Msk      (0x20UL)                  /*!< USB_ISO (Bitfield-Mask: 0x01)                         */
-#define USB_USB_EPC3_REG_USB_EP_EN_Pos    (4UL)                     /*!< USB_EP_EN (Bit 4)                                     */
-#define USB_USB_EPC3_REG_USB_EP_EN_Msk    (0x10UL)                  /*!< USB_EP_EN (Bitfield-Mask: 0x01)                       */
-#define USB_USB_EPC3_REG_USB_EP_Pos       (0UL)                     /*!< USB_EP (Bit 0)                                        */
-#define USB_USB_EPC3_REG_USB_EP_Msk       (0xfUL)                   /*!< USB_EP (Bitfield-Mask: 0x0f)                          */
-/* =====================================================  USB_EPC4_REG  ====================================================== */
-#define USB_USB_EPC4_REG_USB_STALL_Pos    (7UL)                     /*!< USB_STALL (Bit 7)                                     */
-#define USB_USB_EPC4_REG_USB_STALL_Msk    (0x80UL)                  /*!< USB_STALL (Bitfield-Mask: 0x01)                       */
-#define USB_USB_EPC4_REG_USB_ISO_Pos      (5UL)                     /*!< USB_ISO (Bit 5)                                       */
-#define USB_USB_EPC4_REG_USB_ISO_Msk      (0x20UL)                  /*!< USB_ISO (Bitfield-Mask: 0x01)                         */
-#define USB_USB_EPC4_REG_USB_EP_EN_Pos    (4UL)                     /*!< USB_EP_EN (Bit 4)                                     */
-#define USB_USB_EPC4_REG_USB_EP_EN_Msk    (0x10UL)                  /*!< USB_EP_EN (Bitfield-Mask: 0x01)                       */
-#define USB_USB_EPC4_REG_USB_EP_Pos       (0UL)                     /*!< USB_EP (Bit 0)                                        */
-#define USB_USB_EPC4_REG_USB_EP_Msk       (0xfUL)                   /*!< USB_EP (Bitfield-Mask: 0x0f)                          */
-/* =====================================================  USB_EPC5_REG  ====================================================== */
-#define USB_USB_EPC5_REG_USB_STALL_Pos    (7UL)                     /*!< USB_STALL (Bit 7)                                     */
-#define USB_USB_EPC5_REG_USB_STALL_Msk    (0x80UL)                  /*!< USB_STALL (Bitfield-Mask: 0x01)                       */
-#define USB_USB_EPC5_REG_USB_ISO_Pos      (5UL)                     /*!< USB_ISO (Bit 5)                                       */
-#define USB_USB_EPC5_REG_USB_ISO_Msk      (0x20UL)                  /*!< USB_ISO (Bitfield-Mask: 0x01)                         */
-#define USB_USB_EPC5_REG_USB_EP_EN_Pos    (4UL)                     /*!< USB_EP_EN (Bit 4)                                     */
-#define USB_USB_EPC5_REG_USB_EP_EN_Msk    (0x10UL)                  /*!< USB_EP_EN (Bitfield-Mask: 0x01)                       */
-#define USB_USB_EPC5_REG_USB_EP_Pos       (0UL)                     /*!< USB_EP (Bit 0)                                        */
-#define USB_USB_EPC5_REG_USB_EP_Msk       (0xfUL)                   /*!< USB_EP (Bitfield-Mask: 0x0f)                          */
-/* =====================================================  USB_EPC6_REG  ====================================================== */
-#define USB_USB_EPC6_REG_USB_STALL_Pos    (7UL)                     /*!< USB_STALL (Bit 7)                                     */
-#define USB_USB_EPC6_REG_USB_STALL_Msk    (0x80UL)                  /*!< USB_STALL (Bitfield-Mask: 0x01)                       */
-#define USB_USB_EPC6_REG_USB_ISO_Pos      (5UL)                     /*!< USB_ISO (Bit 5)                                       */
-#define USB_USB_EPC6_REG_USB_ISO_Msk      (0x20UL)                  /*!< USB_ISO (Bitfield-Mask: 0x01)                         */
-#define USB_USB_EPC6_REG_USB_EP_EN_Pos    (4UL)                     /*!< USB_EP_EN (Bit 4)                                     */
-#define USB_USB_EPC6_REG_USB_EP_EN_Msk    (0x10UL)                  /*!< USB_EP_EN (Bitfield-Mask: 0x01)                       */
-#define USB_USB_EPC6_REG_USB_EP_Pos       (0UL)                     /*!< USB_EP (Bit 0)                                        */
-#define USB_USB_EPC6_REG_USB_EP_Msk       (0xfUL)                   /*!< USB_EP (Bitfield-Mask: 0x0f)                          */
-/* ======================================================  USB_FAR_REG  ====================================================== */
-#define USB_USB_FAR_REG_USB_AD_EN_Pos     (7UL)                     /*!< USB_AD_EN (Bit 7)                                     */
-#define USB_USB_FAR_REG_USB_AD_EN_Msk     (0x80UL)                  /*!< USB_AD_EN (Bitfield-Mask: 0x01)                       */
-#define USB_USB_FAR_REG_USB_AD_Pos        (0UL)                     /*!< USB_AD (Bit 0)                                        */
-#define USB_USB_FAR_REG_USB_AD_Msk        (0x7fUL)                  /*!< USB_AD (Bitfield-Mask: 0x7f)                          */
-/* ======================================================  USB_FNH_REG  ====================================================== */
-#define USB_USB_FNH_REG_USB_MF_Pos        (7UL)                     /*!< USB_MF (Bit 7)                                        */
-#define USB_USB_FNH_REG_USB_MF_Msk        (0x80UL)                  /*!< USB_MF (Bitfield-Mask: 0x01)                          */
-#define USB_USB_FNH_REG_USB_UL_Pos        (6UL)                     /*!< USB_UL (Bit 6)                                        */
-#define USB_USB_FNH_REG_USB_UL_Msk        (0x40UL)                  /*!< USB_UL (Bitfield-Mask: 0x01)                          */
-#define USB_USB_FNH_REG_USB_RFC_Pos       (5UL)                     /*!< USB_RFC (Bit 5)                                       */
-#define USB_USB_FNH_REG_USB_RFC_Msk       (0x20UL)                  /*!< USB_RFC (Bitfield-Mask: 0x01)                         */
-#define USB_USB_FNH_REG_USB_FN_10_8_Pos   (0UL)                     /*!< USB_FN_10_8 (Bit 0)                                   */
-#define USB_USB_FNH_REG_USB_FN_10_8_Msk   (0x7UL)                   /*!< USB_FN_10_8 (Bitfield-Mask: 0x07)                     */
-/* ======================================================  USB_FNL_REG  ====================================================== */
-#define USB_USB_FNL_REG_USB_FN_Pos        (0UL)                     /*!< USB_FN (Bit 0)                                        */
-#define USB_USB_FNL_REG_USB_FN_Msk        (0xffUL)                  /*!< USB_FN (Bitfield-Mask: 0xff)                          */
-/* =====================================================  USB_FWEV_REG  ====================================================== */
-#define USB_USB_FWEV_REG_USB_RXWARN31_Pos (4UL)                     /*!< USB_RXWARN31 (Bit 4)                                  */
-#define USB_USB_FWEV_REG_USB_RXWARN31_Msk (0x70UL)                  /*!< USB_RXWARN31 (Bitfield-Mask: 0x07)                    */
-#define USB_USB_FWEV_REG_USB_TXWARN31_Pos (0UL)                     /*!< USB_TXWARN31 (Bit 0)                                  */
-#define USB_USB_FWEV_REG_USB_TXWARN31_Msk (0x7UL)                   /*!< USB_TXWARN31 (Bitfield-Mask: 0x07)                    */
-/* =====================================================  USB_FWMSK_REG  ===================================================== */
-#define USB_USB_FWMSK_REG_USB_M_RXWARN31_Pos (4UL)                  /*!< USB_M_RXWARN31 (Bit 4)                                */
-#define USB_USB_FWMSK_REG_USB_M_RXWARN31_Msk (0x70UL)               /*!< USB_M_RXWARN31 (Bitfield-Mask: 0x07)                  */
-#define USB_USB_FWMSK_REG_USB_M_TXWARN31_Pos (0UL)                  /*!< USB_M_TXWARN31 (Bit 0)                                */
-#define USB_USB_FWMSK_REG_USB_M_TXWARN31_Msk (0x7UL)                /*!< USB_M_TXWARN31 (Bitfield-Mask: 0x07)                  */
-/* =====================================================  USB_MAEV_REG  ====================================================== */
-#define USB_USB_MAEV_REG_USB_CH_EV_Pos    (11UL)                    /*!< USB_CH_EV (Bit 11)                                    */
-#define USB_USB_MAEV_REG_USB_CH_EV_Msk    (0x800UL)                 /*!< USB_CH_EV (Bitfield-Mask: 0x01)                       */
-#define USB_USB_MAEV_REG_USB_EP0_NAK_Pos  (10UL)                    /*!< USB_EP0_NAK (Bit 10)                                  */
-#define USB_USB_MAEV_REG_USB_EP0_NAK_Msk  (0x400UL)                 /*!< USB_EP0_NAK (Bitfield-Mask: 0x01)                     */
-#define USB_USB_MAEV_REG_USB_EP0_RX_Pos   (9UL)                     /*!< USB_EP0_RX (Bit 9)                                    */
-#define USB_USB_MAEV_REG_USB_EP0_RX_Msk   (0x200UL)                 /*!< USB_EP0_RX (Bitfield-Mask: 0x01)                      */
-#define USB_USB_MAEV_REG_USB_EP0_TX_Pos   (8UL)                     /*!< USB_EP0_TX (Bit 8)                                    */
-#define USB_USB_MAEV_REG_USB_EP0_TX_Msk   (0x100UL)                 /*!< USB_EP0_TX (Bitfield-Mask: 0x01)                      */
-#define USB_USB_MAEV_REG_USB_INTR_Pos     (7UL)                     /*!< USB_INTR (Bit 7)                                      */
-#define USB_USB_MAEV_REG_USB_INTR_Msk     (0x80UL)                  /*!< USB_INTR (Bitfield-Mask: 0x01)                        */
-#define USB_USB_MAEV_REG_USB_RX_EV_Pos    (6UL)                     /*!< USB_RX_EV (Bit 6)                                     */
-#define USB_USB_MAEV_REG_USB_RX_EV_Msk    (0x40UL)                  /*!< USB_RX_EV (Bitfield-Mask: 0x01)                       */
-#define USB_USB_MAEV_REG_USB_ULD_Pos      (5UL)                     /*!< USB_ULD (Bit 5)                                       */
-#define USB_USB_MAEV_REG_USB_ULD_Msk      (0x20UL)                  /*!< USB_ULD (Bitfield-Mask: 0x01)                         */
-#define USB_USB_MAEV_REG_USB_NAK_Pos      (4UL)                     /*!< USB_NAK (Bit 4)                                       */
-#define USB_USB_MAEV_REG_USB_NAK_Msk      (0x10UL)                  /*!< USB_NAK (Bitfield-Mask: 0x01)                         */
-#define USB_USB_MAEV_REG_USB_FRAME_Pos    (3UL)                     /*!< USB_FRAME (Bit 3)                                     */
-#define USB_USB_MAEV_REG_USB_FRAME_Msk    (0x8UL)                   /*!< USB_FRAME (Bitfield-Mask: 0x01)                       */
-#define USB_USB_MAEV_REG_USB_TX_EV_Pos    (2UL)                     /*!< USB_TX_EV (Bit 2)                                     */
-#define USB_USB_MAEV_REG_USB_TX_EV_Msk    (0x4UL)                   /*!< USB_TX_EV (Bitfield-Mask: 0x01)                       */
-#define USB_USB_MAEV_REG_USB_ALT_Pos      (1UL)                     /*!< USB_ALT (Bit 1)                                       */
-#define USB_USB_MAEV_REG_USB_ALT_Msk      (0x2UL)                   /*!< USB_ALT (Bitfield-Mask: 0x01)                         */
-#define USB_USB_MAEV_REG_USB_WARN_Pos     (0UL)                     /*!< USB_WARN (Bit 0)                                      */
-#define USB_USB_MAEV_REG_USB_WARN_Msk     (0x1UL)                   /*!< USB_WARN (Bitfield-Mask: 0x01)                        */
-/* =====================================================  USB_MAMSK_REG  ===================================================== */
-#define USB_USB_MAMSK_REG_USB_M_CH_EV_Pos (11UL)                    /*!< USB_M_CH_EV (Bit 11)                                  */
-#define USB_USB_MAMSK_REG_USB_M_CH_EV_Msk (0x800UL)                 /*!< USB_M_CH_EV (Bitfield-Mask: 0x01)                     */
-#define USB_USB_MAMSK_REG_USB_M_EP0_NAK_Pos (10UL)                  /*!< USB_M_EP0_NAK (Bit 10)                                */
-#define USB_USB_MAMSK_REG_USB_M_EP0_NAK_Msk (0x400UL)               /*!< USB_M_EP0_NAK (Bitfield-Mask: 0x01)                   */
-#define USB_USB_MAMSK_REG_USB_M_EP0_RX_Pos (9UL)                    /*!< USB_M_EP0_RX (Bit 9)                                  */
-#define USB_USB_MAMSK_REG_USB_M_EP0_RX_Msk (0x200UL)                /*!< USB_M_EP0_RX (Bitfield-Mask: 0x01)                    */
-#define USB_USB_MAMSK_REG_USB_M_EP0_TX_Pos (8UL)                    /*!< USB_M_EP0_TX (Bit 8)                                  */
-#define USB_USB_MAMSK_REG_USB_M_EP0_TX_Msk (0x100UL)                /*!< USB_M_EP0_TX (Bitfield-Mask: 0x01)                    */
-#define USB_USB_MAMSK_REG_USB_M_INTR_Pos  (7UL)                     /*!< USB_M_INTR (Bit 7)                                    */
-#define USB_USB_MAMSK_REG_USB_M_INTR_Msk  (0x80UL)                  /*!< USB_M_INTR (Bitfield-Mask: 0x01)                      */
-#define USB_USB_MAMSK_REG_USB_M_RX_EV_Pos (6UL)                     /*!< USB_M_RX_EV (Bit 6)                                   */
-#define USB_USB_MAMSK_REG_USB_M_RX_EV_Msk (0x40UL)                  /*!< USB_M_RX_EV (Bitfield-Mask: 0x01)                     */
-#define USB_USB_MAMSK_REG_USB_M_ULD_Pos   (5UL)                     /*!< USB_M_ULD (Bit 5)                                     */
-#define USB_USB_MAMSK_REG_USB_M_ULD_Msk   (0x20UL)                  /*!< USB_M_ULD (Bitfield-Mask: 0x01)                       */
-#define USB_USB_MAMSK_REG_USB_M_NAK_Pos   (4UL)                     /*!< USB_M_NAK (Bit 4)                                     */
-#define USB_USB_MAMSK_REG_USB_M_NAK_Msk   (0x10UL)                  /*!< USB_M_NAK (Bitfield-Mask: 0x01)                       */
-#define USB_USB_MAMSK_REG_USB_M_FRAME_Pos (3UL)                     /*!< USB_M_FRAME (Bit 3)                                   */
-#define USB_USB_MAMSK_REG_USB_M_FRAME_Msk (0x8UL)                   /*!< USB_M_FRAME (Bitfield-Mask: 0x01)                     */
-#define USB_USB_MAMSK_REG_USB_M_TX_EV_Pos (2UL)                     /*!< USB_M_TX_EV (Bit 2)                                   */
-#define USB_USB_MAMSK_REG_USB_M_TX_EV_Msk (0x4UL)                   /*!< USB_M_TX_EV (Bitfield-Mask: 0x01)                     */
-#define USB_USB_MAMSK_REG_USB_M_ALT_Pos   (1UL)                     /*!< USB_M_ALT (Bit 1)                                     */
-#define USB_USB_MAMSK_REG_USB_M_ALT_Msk   (0x2UL)                   /*!< USB_M_ALT (Bitfield-Mask: 0x01)                       */
-#define USB_USB_MAMSK_REG_USB_M_WARN_Pos  (0UL)                     /*!< USB_M_WARN (Bit 0)                                    */
-#define USB_USB_MAMSK_REG_USB_M_WARN_Msk  (0x1UL)                   /*!< USB_M_WARN (Bitfield-Mask: 0x01)                      */
-/* =====================================================  USB_MCTRL_REG  ===================================================== */
-#define USB_USB_MCTRL_REG_LSMODE_Pos      (4UL)                     /*!< LSMODE (Bit 4)                                        */
-#define USB_USB_MCTRL_REG_LSMODE_Msk      (0x10UL)                  /*!< LSMODE (Bitfield-Mask: 0x01)                          */
-#define USB_USB_MCTRL_REG_USB_NAT_Pos     (3UL)                     /*!< USB_NAT (Bit 3)                                       */
-#define USB_USB_MCTRL_REG_USB_NAT_Msk     (0x8UL)                   /*!< USB_NAT (Bitfield-Mask: 0x01)                         */
-#define USB_USB_MCTRL_REG_USB_DBG_Pos     (1UL)                     /*!< USB_DBG (Bit 1)                                       */
-#define USB_USB_MCTRL_REG_USB_DBG_Msk     (0x2UL)                   /*!< USB_DBG (Bitfield-Mask: 0x01)                         */
-#define USB_USB_MCTRL_REG_USBEN_Pos       (0UL)                     /*!< USBEN (Bit 0)                                         */
-#define USB_USB_MCTRL_REG_USBEN_Msk       (0x1UL)                   /*!< USBEN (Bitfield-Mask: 0x01)                           */
-/* =====================================================  USB_NAKEV_REG  ===================================================== */
-#define USB_USB_NAKEV_REG_USB_OUT31_Pos   (4UL)                     /*!< USB_OUT31 (Bit 4)                                     */
-#define USB_USB_NAKEV_REG_USB_OUT31_Msk   (0x70UL)                  /*!< USB_OUT31 (Bitfield-Mask: 0x07)                       */
-#define USB_USB_NAKEV_REG_USB_IN31_Pos    (0UL)                     /*!< USB_IN31 (Bit 0)                                      */
-#define USB_USB_NAKEV_REG_USB_IN31_Msk    (0x7UL)                   /*!< USB_IN31 (Bitfield-Mask: 0x07)                        */
-/* ====================================================  USB_NAKMSK_REG  ===================================================== */
-#define USB_USB_NAKMSK_REG_USB_M_OUT31_Pos (4UL)                    /*!< USB_M_OUT31 (Bit 4)                                   */
-#define USB_USB_NAKMSK_REG_USB_M_OUT31_Msk (0x70UL)                 /*!< USB_M_OUT31 (Bitfield-Mask: 0x07)                     */
-#define USB_USB_NAKMSK_REG_USB_M_IN31_Pos (0UL)                     /*!< USB_M_IN31 (Bit 0)                                    */
-#define USB_USB_NAKMSK_REG_USB_M_IN31_Msk (0x7UL)                   /*!< USB_M_IN31 (Bitfield-Mask: 0x07)                      */
-/* =====================================================  USB_NFSR_REG  ====================================================== */
-#define USB_USB_NFSR_REG_USB_NFS_Pos      (0UL)                     /*!< USB_NFS (Bit 0)                                       */
-#define USB_USB_NFSR_REG_USB_NFS_Msk      (0x3UL)                   /*!< USB_NFS (Bitfield-Mask: 0x03)                         */
-/* =====================================================  USB_RXC0_REG  ====================================================== */
-#define USB_USB_RXC0_REG_USB_FLUSH_Pos    (3UL)                     /*!< USB_FLUSH (Bit 3)                                     */
-#define USB_USB_RXC0_REG_USB_FLUSH_Msk    (0x8UL)                   /*!< USB_FLUSH (Bitfield-Mask: 0x01)                       */
-#define USB_USB_RXC0_REG_USB_IGN_SETUP_Pos (2UL)                    /*!< USB_IGN_SETUP (Bit 2)                                 */
-#define USB_USB_RXC0_REG_USB_IGN_SETUP_Msk (0x4UL)                  /*!< USB_IGN_SETUP (Bitfield-Mask: 0x01)                   */
-#define USB_USB_RXC0_REG_USB_IGN_OUT_Pos  (1UL)                     /*!< USB_IGN_OUT (Bit 1)                                   */
-#define USB_USB_RXC0_REG_USB_IGN_OUT_Msk  (0x2UL)                   /*!< USB_IGN_OUT (Bitfield-Mask: 0x01)                     */
-#define USB_USB_RXC0_REG_USB_RX_EN_Pos    (0UL)                     /*!< USB_RX_EN (Bit 0)                                     */
-#define USB_USB_RXC0_REG_USB_RX_EN_Msk    (0x1UL)                   /*!< USB_RX_EN (Bitfield-Mask: 0x01)                       */
-/* =====================================================  USB_RXC1_REG  ====================================================== */
-#define USB_USB_RXC1_REG_USB_RFWL_Pos     (5UL)                     /*!< USB_RFWL (Bit 5)                                      */
-#define USB_USB_RXC1_REG_USB_RFWL_Msk     (0x60UL)                  /*!< USB_RFWL (Bitfield-Mask: 0x03)                        */
-#define USB_USB_RXC1_REG_USB_FLUSH_Pos    (3UL)                     /*!< USB_FLUSH (Bit 3)                                     */
-#define USB_USB_RXC1_REG_USB_FLUSH_Msk    (0x8UL)                   /*!< USB_FLUSH (Bitfield-Mask: 0x01)                       */
-#define USB_USB_RXC1_REG_USB_IGN_SETUP_Pos (2UL)                    /*!< USB_IGN_SETUP (Bit 2)                                 */
-#define USB_USB_RXC1_REG_USB_IGN_SETUP_Msk (0x4UL)                  /*!< USB_IGN_SETUP (Bitfield-Mask: 0x01)                   */
-#define USB_USB_RXC1_REG_USB_RX_EN_Pos    (0UL)                     /*!< USB_RX_EN (Bit 0)                                     */
-#define USB_USB_RXC1_REG_USB_RX_EN_Msk    (0x1UL)                   /*!< USB_RX_EN (Bitfield-Mask: 0x01)                       */
-/* =====================================================  USB_RXC2_REG  ====================================================== */
-#define USB_USB_RXC2_REG_USB_RFWL_Pos     (5UL)                     /*!< USB_RFWL (Bit 5)                                      */
-#define USB_USB_RXC2_REG_USB_RFWL_Msk     (0x60UL)                  /*!< USB_RFWL (Bitfield-Mask: 0x03)                        */
-#define USB_USB_RXC2_REG_USB_FLUSH_Pos    (3UL)                     /*!< USB_FLUSH (Bit 3)                                     */
-#define USB_USB_RXC2_REG_USB_FLUSH_Msk    (0x8UL)                   /*!< USB_FLUSH (Bitfield-Mask: 0x01)                       */
-#define USB_USB_RXC2_REG_USB_IGN_SETUP_Pos (2UL)                    /*!< USB_IGN_SETUP (Bit 2)                                 */
-#define USB_USB_RXC2_REG_USB_IGN_SETUP_Msk (0x4UL)                  /*!< USB_IGN_SETUP (Bitfield-Mask: 0x01)                   */
-#define USB_USB_RXC2_REG_USB_RX_EN_Pos    (0UL)                     /*!< USB_RX_EN (Bit 0)                                     */
-#define USB_USB_RXC2_REG_USB_RX_EN_Msk    (0x1UL)                   /*!< USB_RX_EN (Bitfield-Mask: 0x01)                       */
-/* =====================================================  USB_RXC3_REG  ====================================================== */
-#define USB_USB_RXC3_REG_USB_RFWL_Pos     (5UL)                     /*!< USB_RFWL (Bit 5)                                      */
-#define USB_USB_RXC3_REG_USB_RFWL_Msk     (0x60UL)                  /*!< USB_RFWL (Bitfield-Mask: 0x03)                        */
-#define USB_USB_RXC3_REG_USB_FLUSH_Pos    (3UL)                     /*!< USB_FLUSH (Bit 3)                                     */
-#define USB_USB_RXC3_REG_USB_FLUSH_Msk    (0x8UL)                   /*!< USB_FLUSH (Bitfield-Mask: 0x01)                       */
-#define USB_USB_RXC3_REG_USB_IGN_SETUP_Pos (2UL)                    /*!< USB_IGN_SETUP (Bit 2)                                 */
-#define USB_USB_RXC3_REG_USB_IGN_SETUP_Msk (0x4UL)                  /*!< USB_IGN_SETUP (Bitfield-Mask: 0x01)                   */
-#define USB_USB_RXC3_REG_USB_RX_EN_Pos    (0UL)                     /*!< USB_RX_EN (Bit 0)                                     */
-#define USB_USB_RXC3_REG_USB_RX_EN_Msk    (0x1UL)                   /*!< USB_RX_EN (Bitfield-Mask: 0x01)                       */
-/* =====================================================  USB_RXD0_REG  ====================================================== */
-#define USB_USB_RXD0_REG_USB_RXFD_Pos     (0UL)                     /*!< USB_RXFD (Bit 0)                                      */
-#define USB_USB_RXD0_REG_USB_RXFD_Msk     (0xffUL)                  /*!< USB_RXFD (Bitfield-Mask: 0xff)                        */
-/* =====================================================  USB_RXD1_REG  ====================================================== */
-#define USB_USB_RXD1_REG_USB_RXFD_Pos     (0UL)                     /*!< USB_RXFD (Bit 0)                                      */
-#define USB_USB_RXD1_REG_USB_RXFD_Msk     (0xffUL)                  /*!< USB_RXFD (Bitfield-Mask: 0xff)                        */
-/* =====================================================  USB_RXD2_REG  ====================================================== */
-#define USB_USB_RXD2_REG_USB_RXFD_Pos     (0UL)                     /*!< USB_RXFD (Bit 0)                                      */
-#define USB_USB_RXD2_REG_USB_RXFD_Msk     (0xffUL)                  /*!< USB_RXFD (Bitfield-Mask: 0xff)                        */
-/* =====================================================  USB_RXD3_REG  ====================================================== */
-#define USB_USB_RXD3_REG_USB_RXFD_Pos     (0UL)                     /*!< USB_RXFD (Bit 0)                                      */
-#define USB_USB_RXD3_REG_USB_RXFD_Msk     (0xffUL)                  /*!< USB_RXFD (Bitfield-Mask: 0xff)                        */
-/* =====================================================  USB_RXEV_REG  ====================================================== */
-#define USB_USB_RXEV_REG_USB_RXOVRRN31_Pos (4UL)                    /*!< USB_RXOVRRN31 (Bit 4)                                 */
-#define USB_USB_RXEV_REG_USB_RXOVRRN31_Msk (0x70UL)                 /*!< USB_RXOVRRN31 (Bitfield-Mask: 0x07)                   */
-#define USB_USB_RXEV_REG_USB_RXFIFO31_Pos (0UL)                     /*!< USB_RXFIFO31 (Bit 0)                                  */
-#define USB_USB_RXEV_REG_USB_RXFIFO31_Msk (0x7UL)                   /*!< USB_RXFIFO31 (Bitfield-Mask: 0x07)                    */
-/* =====================================================  USB_RXMSK_REG  ===================================================== */
-#define USB_USB_RXMSK_REG_USB_M_RXOVRRN31_Pos (4UL)                 /*!< USB_M_RXOVRRN31 (Bit 4)                               */
-#define USB_USB_RXMSK_REG_USB_M_RXOVRRN31_Msk (0x70UL)              /*!< USB_M_RXOVRRN31 (Bitfield-Mask: 0x07)                 */
-#define USB_USB_RXMSK_REG_USB_M_RXFIFO31_Pos (0UL)                  /*!< USB_M_RXFIFO31 (Bit 0)                                */
-#define USB_USB_RXMSK_REG_USB_M_RXFIFO31_Msk (0x7UL)                /*!< USB_M_RXFIFO31 (Bitfield-Mask: 0x07)                  */
-/* =====================================================  USB_RXS0_REG  ====================================================== */
-#define USB_USB_RXS0_REG_USB_SETUP_Pos    (6UL)                     /*!< USB_SETUP (Bit 6)                                     */
-#define USB_USB_RXS0_REG_USB_SETUP_Msk    (0x40UL)                  /*!< USB_SETUP (Bitfield-Mask: 0x01)                       */
-#define USB_USB_RXS0_REG_USB_TOGGLE_RX0_Pos (5UL)                   /*!< USB_TOGGLE_RX0 (Bit 5)                                */
-#define USB_USB_RXS0_REG_USB_TOGGLE_RX0_Msk (0x20UL)                /*!< USB_TOGGLE_RX0 (Bitfield-Mask: 0x01)                  */
-#define USB_USB_RXS0_REG_USB_RX_LAST_Pos  (4UL)                     /*!< USB_RX_LAST (Bit 4)                                   */
-#define USB_USB_RXS0_REG_USB_RX_LAST_Msk  (0x10UL)                  /*!< USB_RX_LAST (Bitfield-Mask: 0x01)                     */
-#define USB_USB_RXS0_REG_USB_RCOUNT_Pos   (0UL)                     /*!< USB_RCOUNT (Bit 0)                                    */
-#define USB_USB_RXS0_REG_USB_RCOUNT_Msk   (0xfUL)                   /*!< USB_RCOUNT (Bitfield-Mask: 0x0f)                      */
-/* =====================================================  USB_RXS1_REG  ====================================================== */
-#define USB_USB_RXS1_REG_USB_RXCOUNT_Pos  (8UL)                     /*!< USB_RXCOUNT (Bit 8)                                   */
-#define USB_USB_RXS1_REG_USB_RXCOUNT_Msk  (0x7f00UL)                /*!< USB_RXCOUNT (Bitfield-Mask: 0x7f)                     */
-#define USB_USB_RXS1_REG_USB_RX_ERR_Pos   (7UL)                     /*!< USB_RX_ERR (Bit 7)                                    */
-#define USB_USB_RXS1_REG_USB_RX_ERR_Msk   (0x80UL)                  /*!< USB_RX_ERR (Bitfield-Mask: 0x01)                      */
-#define USB_USB_RXS1_REG_USB_SETUP_Pos    (6UL)                     /*!< USB_SETUP (Bit 6)                                     */
-#define USB_USB_RXS1_REG_USB_SETUP_Msk    (0x40UL)                  /*!< USB_SETUP (Bitfield-Mask: 0x01)                       */
-#define USB_USB_RXS1_REG_USB_TOGGLE_RX_Pos (5UL)                    /*!< USB_TOGGLE_RX (Bit 5)                                 */
-#define USB_USB_RXS1_REG_USB_TOGGLE_RX_Msk (0x20UL)                 /*!< USB_TOGGLE_RX (Bitfield-Mask: 0x01)                   */
-#define USB_USB_RXS1_REG_USB_RX_LAST_Pos  (4UL)                     /*!< USB_RX_LAST (Bit 4)                                   */
-#define USB_USB_RXS1_REG_USB_RX_LAST_Msk  (0x10UL)                  /*!< USB_RX_LAST (Bitfield-Mask: 0x01)                     */
-#define USB_USB_RXS1_REG_USB_RCOUNT_Pos   (0UL)                     /*!< USB_RCOUNT (Bit 0)                                    */
-#define USB_USB_RXS1_REG_USB_RCOUNT_Msk   (0xfUL)                   /*!< USB_RCOUNT (Bitfield-Mask: 0x0f)                      */
-/* =====================================================  USB_RXS2_REG  ====================================================== */
-#define USB_USB_RXS2_REG_USB_RXCOUNT_Pos  (8UL)                     /*!< USB_RXCOUNT (Bit 8)                                   */
-#define USB_USB_RXS2_REG_USB_RXCOUNT_Msk  (0x7f00UL)                /*!< USB_RXCOUNT (Bitfield-Mask: 0x7f)                     */
-#define USB_USB_RXS2_REG_USB_RX_ERR_Pos   (7UL)                     /*!< USB_RX_ERR (Bit 7)                                    */
-#define USB_USB_RXS2_REG_USB_RX_ERR_Msk   (0x80UL)                  /*!< USB_RX_ERR (Bitfield-Mask: 0x01)                      */
-#define USB_USB_RXS2_REG_USB_SETUP_Pos    (6UL)                     /*!< USB_SETUP (Bit 6)                                     */
-#define USB_USB_RXS2_REG_USB_SETUP_Msk    (0x40UL)                  /*!< USB_SETUP (Bitfield-Mask: 0x01)                       */
-#define USB_USB_RXS2_REG_USB_TOGGLE_RX_Pos (5UL)                    /*!< USB_TOGGLE_RX (Bit 5)                                 */
-#define USB_USB_RXS2_REG_USB_TOGGLE_RX_Msk (0x20UL)                 /*!< USB_TOGGLE_RX (Bitfield-Mask: 0x01)                   */
-#define USB_USB_RXS2_REG_USB_RX_LAST_Pos  (4UL)                     /*!< USB_RX_LAST (Bit 4)                                   */
-#define USB_USB_RXS2_REG_USB_RX_LAST_Msk  (0x10UL)                  /*!< USB_RX_LAST (Bitfield-Mask: 0x01)                     */
-#define USB_USB_RXS2_REG_USB_RCOUNT_Pos   (0UL)                     /*!< USB_RCOUNT (Bit 0)                                    */
-#define USB_USB_RXS2_REG_USB_RCOUNT_Msk   (0xfUL)                   /*!< USB_RCOUNT (Bitfield-Mask: 0x0f)                      */
-/* =====================================================  USB_RXS3_REG  ====================================================== */
-#define USB_USB_RXS3_REG_USB_RXCOUNT_Pos  (8UL)                     /*!< USB_RXCOUNT (Bit 8)                                   */
-#define USB_USB_RXS3_REG_USB_RXCOUNT_Msk  (0x7f00UL)                /*!< USB_RXCOUNT (Bitfield-Mask: 0x7f)                     */
-#define USB_USB_RXS3_REG_USB_RX_ERR_Pos   (7UL)                     /*!< USB_RX_ERR (Bit 7)                                    */
-#define USB_USB_RXS3_REG_USB_RX_ERR_Msk   (0x80UL)                  /*!< USB_RX_ERR (Bitfield-Mask: 0x01)                      */
-#define USB_USB_RXS3_REG_USB_SETUP_Pos    (6UL)                     /*!< USB_SETUP (Bit 6)                                     */
-#define USB_USB_RXS3_REG_USB_SETUP_Msk    (0x40UL)                  /*!< USB_SETUP (Bitfield-Mask: 0x01)                       */
-#define USB_USB_RXS3_REG_USB_TOGGLE_RX_Pos (5UL)                    /*!< USB_TOGGLE_RX (Bit 5)                                 */
-#define USB_USB_RXS3_REG_USB_TOGGLE_RX_Msk (0x20UL)                 /*!< USB_TOGGLE_RX (Bitfield-Mask: 0x01)                   */
-#define USB_USB_RXS3_REG_USB_RX_LAST_Pos  (4UL)                     /*!< USB_RX_LAST (Bit 4)                                   */
-#define USB_USB_RXS3_REG_USB_RX_LAST_Msk  (0x10UL)                  /*!< USB_RX_LAST (Bitfield-Mask: 0x01)                     */
-#define USB_USB_RXS3_REG_USB_RCOUNT_Pos   (0UL)                     /*!< USB_RCOUNT (Bit 0)                                    */
-#define USB_USB_RXS3_REG_USB_RCOUNT_Msk   (0xfUL)                   /*!< USB_RCOUNT (Bitfield-Mask: 0x0f)                      */
-/* ======================================================  USB_TCR_REG  ====================================================== */
-#define USB_USB_TCR_REG_USB_VADJ_Pos      (5UL)                     /*!< USB_VADJ (Bit 5)                                      */
-#define USB_USB_TCR_REG_USB_VADJ_Msk      (0xe0UL)                  /*!< USB_VADJ (Bitfield-Mask: 0x07)                        */
-#define USB_USB_TCR_REG_USB_CADJ_Pos      (0UL)                     /*!< USB_CADJ (Bit 0)                                      */
-#define USB_USB_TCR_REG_USB_CADJ_Msk      (0x1fUL)                  /*!< USB_CADJ (Bitfield-Mask: 0x1f)                        */
-/* =====================================================  USB_TXC0_REG  ====================================================== */
-#define USB_USB_TXC0_REG_USB_IGN_IN_Pos   (4UL)                     /*!< USB_IGN_IN (Bit 4)                                    */
-#define USB_USB_TXC0_REG_USB_IGN_IN_Msk   (0x10UL)                  /*!< USB_IGN_IN (Bitfield-Mask: 0x01)                      */
-#define USB_USB_TXC0_REG_USB_FLUSH_Pos    (3UL)                     /*!< USB_FLUSH (Bit 3)                                     */
-#define USB_USB_TXC0_REG_USB_FLUSH_Msk    (0x8UL)                   /*!< USB_FLUSH (Bitfield-Mask: 0x01)                       */
-#define USB_USB_TXC0_REG_USB_TOGGLE_TX0_Pos (2UL)                   /*!< USB_TOGGLE_TX0 (Bit 2)                                */
-#define USB_USB_TXC0_REG_USB_TOGGLE_TX0_Msk (0x4UL)                 /*!< USB_TOGGLE_TX0 (Bitfield-Mask: 0x01)                  */
-#define USB_USB_TXC0_REG_USB_TX_EN_Pos    (0UL)                     /*!< USB_TX_EN (Bit 0)                                     */
-#define USB_USB_TXC0_REG_USB_TX_EN_Msk    (0x1UL)                   /*!< USB_TX_EN (Bitfield-Mask: 0x01)                       */
-/* =====================================================  USB_TXC1_REG  ====================================================== */
-#define USB_USB_TXC1_REG_USB_IGN_ISOMSK_Pos (7UL)                   /*!< USB_IGN_ISOMSK (Bit 7)                                */
-#define USB_USB_TXC1_REG_USB_IGN_ISOMSK_Msk (0x80UL)                /*!< USB_IGN_ISOMSK (Bitfield-Mask: 0x01)                  */
-#define USB_USB_TXC1_REG_USB_TFWL_Pos     (5UL)                     /*!< USB_TFWL (Bit 5)                                      */
-#define USB_USB_TXC1_REG_USB_TFWL_Msk     (0x60UL)                  /*!< USB_TFWL (Bitfield-Mask: 0x03)                        */
-#define USB_USB_TXC1_REG_USB_RFF_Pos      (4UL)                     /*!< USB_RFF (Bit 4)                                       */
-#define USB_USB_TXC1_REG_USB_RFF_Msk      (0x10UL)                  /*!< USB_RFF (Bitfield-Mask: 0x01)                         */
-#define USB_USB_TXC1_REG_USB_FLUSH_Pos    (3UL)                     /*!< USB_FLUSH (Bit 3)                                     */
-#define USB_USB_TXC1_REG_USB_FLUSH_Msk    (0x8UL)                   /*!< USB_FLUSH (Bitfield-Mask: 0x01)                       */
-#define USB_USB_TXC1_REG_USB_TOGGLE_TX_Pos (2UL)                    /*!< USB_TOGGLE_TX (Bit 2)                                 */
-#define USB_USB_TXC1_REG_USB_TOGGLE_TX_Msk (0x4UL)                  /*!< USB_TOGGLE_TX (Bitfield-Mask: 0x01)                   */
-#define USB_USB_TXC1_REG_USB_LAST_Pos     (1UL)                     /*!< USB_LAST (Bit 1)                                      */
-#define USB_USB_TXC1_REG_USB_LAST_Msk     (0x2UL)                   /*!< USB_LAST (Bitfield-Mask: 0x01)                        */
-#define USB_USB_TXC1_REG_USB_TX_EN_Pos    (0UL)                     /*!< USB_TX_EN (Bit 0)                                     */
-#define USB_USB_TXC1_REG_USB_TX_EN_Msk    (0x1UL)                   /*!< USB_TX_EN (Bitfield-Mask: 0x01)                       */
-/* =====================================================  USB_TXC2_REG  ====================================================== */
-#define USB_USB_TXC2_REG_USB_IGN_ISOMSK_Pos (7UL)                   /*!< USB_IGN_ISOMSK (Bit 7)                                */
-#define USB_USB_TXC2_REG_USB_IGN_ISOMSK_Msk (0x80UL)                /*!< USB_IGN_ISOMSK (Bitfield-Mask: 0x01)                  */
-#define USB_USB_TXC2_REG_USB_TFWL_Pos     (5UL)                     /*!< USB_TFWL (Bit 5)                                      */
-#define USB_USB_TXC2_REG_USB_TFWL_Msk     (0x60UL)                  /*!< USB_TFWL (Bitfield-Mask: 0x03)                        */
-#define USB_USB_TXC2_REG_USB_RFF_Pos      (4UL)                     /*!< USB_RFF (Bit 4)                                       */
-#define USB_USB_TXC2_REG_USB_RFF_Msk      (0x10UL)                  /*!< USB_RFF (Bitfield-Mask: 0x01)                         */
-#define USB_USB_TXC2_REG_USB_FLUSH_Pos    (3UL)                     /*!< USB_FLUSH (Bit 3)                                     */
-#define USB_USB_TXC2_REG_USB_FLUSH_Msk    (0x8UL)                   /*!< USB_FLUSH (Bitfield-Mask: 0x01)                       */
-#define USB_USB_TXC2_REG_USB_TOGGLE_TX_Pos (2UL)                    /*!< USB_TOGGLE_TX (Bit 2)                                 */
-#define USB_USB_TXC2_REG_USB_TOGGLE_TX_Msk (0x4UL)                  /*!< USB_TOGGLE_TX (Bitfield-Mask: 0x01)                   */
-#define USB_USB_TXC2_REG_USB_LAST_Pos     (1UL)                     /*!< USB_LAST (Bit 1)                                      */
-#define USB_USB_TXC2_REG_USB_LAST_Msk     (0x2UL)                   /*!< USB_LAST (Bitfield-Mask: 0x01)                        */
-#define USB_USB_TXC2_REG_USB_TX_EN_Pos    (0UL)                     /*!< USB_TX_EN (Bit 0)                                     */
-#define USB_USB_TXC2_REG_USB_TX_EN_Msk    (0x1UL)                   /*!< USB_TX_EN (Bitfield-Mask: 0x01)                       */
-/* =====================================================  USB_TXC3_REG  ====================================================== */
-#define USB_USB_TXC3_REG_USB_IGN_ISOMSK_Pos (7UL)                   /*!< USB_IGN_ISOMSK (Bit 7)                                */
-#define USB_USB_TXC3_REG_USB_IGN_ISOMSK_Msk (0x80UL)                /*!< USB_IGN_ISOMSK (Bitfield-Mask: 0x01)                  */
-#define USB_USB_TXC3_REG_USB_TFWL_Pos     (5UL)                     /*!< USB_TFWL (Bit 5)                                      */
-#define USB_USB_TXC3_REG_USB_TFWL_Msk     (0x60UL)                  /*!< USB_TFWL (Bitfield-Mask: 0x03)                        */
-#define USB_USB_TXC3_REG_USB_RFF_Pos      (4UL)                     /*!< USB_RFF (Bit 4)                                       */
-#define USB_USB_TXC3_REG_USB_RFF_Msk      (0x10UL)                  /*!< USB_RFF (Bitfield-Mask: 0x01)                         */
-#define USB_USB_TXC3_REG_USB_FLUSH_Pos    (3UL)                     /*!< USB_FLUSH (Bit 3)                                     */
-#define USB_USB_TXC3_REG_USB_FLUSH_Msk    (0x8UL)                   /*!< USB_FLUSH (Bitfield-Mask: 0x01)                       */
-#define USB_USB_TXC3_REG_USB_TOGGLE_TX_Pos (2UL)                    /*!< USB_TOGGLE_TX (Bit 2)                                 */
-#define USB_USB_TXC3_REG_USB_TOGGLE_TX_Msk (0x4UL)                  /*!< USB_TOGGLE_TX (Bitfield-Mask: 0x01)                   */
-#define USB_USB_TXC3_REG_USB_LAST_Pos     (1UL)                     /*!< USB_LAST (Bit 1)                                      */
-#define USB_USB_TXC3_REG_USB_LAST_Msk     (0x2UL)                   /*!< USB_LAST (Bitfield-Mask: 0x01)                        */
-#define USB_USB_TXC3_REG_USB_TX_EN_Pos    (0UL)                     /*!< USB_TX_EN (Bit 0)                                     */
-#define USB_USB_TXC3_REG_USB_TX_EN_Msk    (0x1UL)                   /*!< USB_TX_EN (Bitfield-Mask: 0x01)                       */
-/* =====================================================  USB_TXD0_REG  ====================================================== */
-#define USB_USB_TXD0_REG_USB_TXFD_Pos     (0UL)                     /*!< USB_TXFD (Bit 0)                                      */
-#define USB_USB_TXD0_REG_USB_TXFD_Msk     (0xffUL)                  /*!< USB_TXFD (Bitfield-Mask: 0xff)                        */
-/* =====================================================  USB_TXD1_REG  ====================================================== */
-#define USB_USB_TXD1_REG_USB_TXFD_Pos     (0UL)                     /*!< USB_TXFD (Bit 0)                                      */
-#define USB_USB_TXD1_REG_USB_TXFD_Msk     (0xffUL)                  /*!< USB_TXFD (Bitfield-Mask: 0xff)                        */
-/* =====================================================  USB_TXD2_REG  ====================================================== */
-#define USB_USB_TXD2_REG_USB_TXFD_Pos     (0UL)                     /*!< USB_TXFD (Bit 0)                                      */
-#define USB_USB_TXD2_REG_USB_TXFD_Msk     (0xffUL)                  /*!< USB_TXFD (Bitfield-Mask: 0xff)                        */
-/* =====================================================  USB_TXD3_REG  ====================================================== */
-#define USB_USB_TXD3_REG_USB_TXFD_Pos     (0UL)                     /*!< USB_TXFD (Bit 0)                                      */
-#define USB_USB_TXD3_REG_USB_TXFD_Msk     (0xffUL)                  /*!< USB_TXFD (Bitfield-Mask: 0xff)                        */
-/* =====================================================  USB_TXEV_REG  ====================================================== */
-#define USB_USB_TXEV_REG_USB_TXUDRRN31_Pos (4UL)                    /*!< USB_TXUDRRN31 (Bit 4)                                 */
-#define USB_USB_TXEV_REG_USB_TXUDRRN31_Msk (0x70UL)                 /*!< USB_TXUDRRN31 (Bitfield-Mask: 0x07)                   */
-#define USB_USB_TXEV_REG_USB_TXFIFO31_Pos (0UL)                     /*!< USB_TXFIFO31 (Bit 0)                                  */
-#define USB_USB_TXEV_REG_USB_TXFIFO31_Msk (0x7UL)                   /*!< USB_TXFIFO31 (Bitfield-Mask: 0x07)                    */
-/* =====================================================  USB_TXMSK_REG  ===================================================== */
-#define USB_USB_TXMSK_REG_USB_M_TXUDRRN31_Pos (4UL)                 /*!< USB_M_TXUDRRN31 (Bit 4)                               */
-#define USB_USB_TXMSK_REG_USB_M_TXUDRRN31_Msk (0x70UL)              /*!< USB_M_TXUDRRN31 (Bitfield-Mask: 0x07)                 */
-#define USB_USB_TXMSK_REG_USB_M_TXFIFO31_Pos (0UL)                  /*!< USB_M_TXFIFO31 (Bit 0)                                */
-#define USB_USB_TXMSK_REG_USB_M_TXFIFO31_Msk (0x7UL)                /*!< USB_M_TXFIFO31 (Bitfield-Mask: 0x07)                  */
-/* =====================================================  USB_TXS0_REG  ====================================================== */
-#define USB_USB_TXS0_REG_USB_ACK_STAT_Pos (6UL)                     /*!< USB_ACK_STAT (Bit 6)                                  */
-#define USB_USB_TXS0_REG_USB_ACK_STAT_Msk (0x40UL)                  /*!< USB_ACK_STAT (Bitfield-Mask: 0x01)                    */
-#define USB_USB_TXS0_REG_USB_TX_DONE_Pos  (5UL)                     /*!< USB_TX_DONE (Bit 5)                                   */
-#define USB_USB_TXS0_REG_USB_TX_DONE_Msk  (0x20UL)                  /*!< USB_TX_DONE (Bitfield-Mask: 0x01)                     */
-#define USB_USB_TXS0_REG_USB_TCOUNT_Pos   (0UL)                     /*!< USB_TCOUNT (Bit 0)                                    */
-#define USB_USB_TXS0_REG_USB_TCOUNT_Msk   (0x1fUL)                  /*!< USB_TCOUNT (Bitfield-Mask: 0x1f)                      */
-/* =====================================================  USB_TXS1_REG  ====================================================== */
-#define USB_USB_TXS1_REG_USB_TX_URUN_Pos  (7UL)                     /*!< USB_TX_URUN (Bit 7)                                   */
-#define USB_USB_TXS1_REG_USB_TX_URUN_Msk  (0x80UL)                  /*!< USB_TX_URUN (Bitfield-Mask: 0x01)                     */
-#define USB_USB_TXS1_REG_USB_ACK_STAT_Pos (6UL)                     /*!< USB_ACK_STAT (Bit 6)                                  */
-#define USB_USB_TXS1_REG_USB_ACK_STAT_Msk (0x40UL)                  /*!< USB_ACK_STAT (Bitfield-Mask: 0x01)                    */
-#define USB_USB_TXS1_REG_USB_TX_DONE_Pos  (5UL)                     /*!< USB_TX_DONE (Bit 5)                                   */
-#define USB_USB_TXS1_REG_USB_TX_DONE_Msk  (0x20UL)                  /*!< USB_TX_DONE (Bitfield-Mask: 0x01)                     */
-#define USB_USB_TXS1_REG_USB_TCOUNT_Pos   (0UL)                     /*!< USB_TCOUNT (Bit 0)                                    */
-#define USB_USB_TXS1_REG_USB_TCOUNT_Msk   (0x1fUL)                  /*!< USB_TCOUNT (Bitfield-Mask: 0x1f)                      */
-/* =====================================================  USB_TXS2_REG  ====================================================== */
-#define USB_USB_TXS2_REG_USB_TX_URUN_Pos  (7UL)                     /*!< USB_TX_URUN (Bit 7)                                   */
-#define USB_USB_TXS2_REG_USB_TX_URUN_Msk  (0x80UL)                  /*!< USB_TX_URUN (Bitfield-Mask: 0x01)                     */
-#define USB_USB_TXS2_REG_USB_ACK_STAT_Pos (6UL)                     /*!< USB_ACK_STAT (Bit 6)                                  */
-#define USB_USB_TXS2_REG_USB_ACK_STAT_Msk (0x40UL)                  /*!< USB_ACK_STAT (Bitfield-Mask: 0x01)                    */
-#define USB_USB_TXS2_REG_USB_TX_DONE_Pos  (5UL)                     /*!< USB_TX_DONE (Bit 5)                                   */
-#define USB_USB_TXS2_REG_USB_TX_DONE_Msk  (0x20UL)                  /*!< USB_TX_DONE (Bitfield-Mask: 0x01)                     */
-#define USB_USB_TXS2_REG_USB_TCOUNT_Pos   (0UL)                     /*!< USB_TCOUNT (Bit 0)                                    */
-#define USB_USB_TXS2_REG_USB_TCOUNT_Msk   (0x1fUL)                  /*!< USB_TCOUNT (Bitfield-Mask: 0x1f)                      */
-/* =====================================================  USB_TXS3_REG  ====================================================== */
-#define USB_USB_TXS3_REG_USB_TX_URUN_Pos  (7UL)                     /*!< USB_TX_URUN (Bit 7)                                   */
-#define USB_USB_TXS3_REG_USB_TX_URUN_Msk  (0x80UL)                  /*!< USB_TX_URUN (Bitfield-Mask: 0x01)                     */
-#define USB_USB_TXS3_REG_USB_ACK_STAT_Pos (6UL)                     /*!< USB_ACK_STAT (Bit 6)                                  */
-#define USB_USB_TXS3_REG_USB_ACK_STAT_Msk (0x40UL)                  /*!< USB_ACK_STAT (Bitfield-Mask: 0x01)                    */
-#define USB_USB_TXS3_REG_USB_TX_DONE_Pos  (5UL)                     /*!< USB_TX_DONE (Bit 5)                                   */
-#define USB_USB_TXS3_REG_USB_TX_DONE_Msk  (0x20UL)                  /*!< USB_TX_DONE (Bitfield-Mask: 0x01)                     */
-#define USB_USB_TXS3_REG_USB_TCOUNT_Pos   (0UL)                     /*!< USB_TCOUNT (Bit 0)                                    */
-#define USB_USB_TXS3_REG_USB_TCOUNT_Msk   (0x1fUL)                  /*!< USB_TCOUNT (Bitfield-Mask: 0x1f)                      */
-/* ======================================================  USB_UTR_REG  ====================================================== */
-#define USB_USB_UTR_REG_USB_DIAG_Pos      (7UL)                     /*!< USB_DIAG (Bit 7)                                      */
-#define USB_USB_UTR_REG_USB_DIAG_Msk      (0x80UL)                  /*!< USB_DIAG (Bitfield-Mask: 0x01)                        */
-#define USB_USB_UTR_REG_USB_NCRC_Pos      (6UL)                     /*!< USB_NCRC (Bit 6)                                      */
-#define USB_USB_UTR_REG_USB_NCRC_Msk      (0x40UL)                  /*!< USB_NCRC (Bitfield-Mask: 0x01)                        */
-#define USB_USB_UTR_REG_USB_SF_Pos        (5UL)                     /*!< USB_SF (Bit 5)                                        */
-#define USB_USB_UTR_REG_USB_SF_Msk        (0x20UL)                  /*!< USB_SF (Bitfield-Mask: 0x01)                          */
-#define USB_USB_UTR_REG_USB_UTR_RES_Pos   (0UL)                     /*!< USB_UTR_RES (Bit 0)                                   */
-#define USB_USB_UTR_REG_USB_UTR_RES_Msk   (0x1fUL)                  /*!< USB_UTR_RES (Bitfield-Mask: 0x1f)                     */
-/* ====================================================  USB_UX20CDR_REG  ==================================================== */
-#define USB_USB_UX20CDR_REG_RPU_TEST7_Pos (7UL)                     /*!< RPU_TEST7 (Bit 7)                                     */
-#define USB_USB_UX20CDR_REG_RPU_TEST7_Msk (0x80UL)                  /*!< RPU_TEST7 (Bitfield-Mask: 0x01)                       */
-#define USB_USB_UX20CDR_REG_RPU_TEST_SW2_Pos (6UL)                  /*!< RPU_TEST_SW2 (Bit 6)                                  */
-#define USB_USB_UX20CDR_REG_RPU_TEST_SW2_Msk (0x40UL)               /*!< RPU_TEST_SW2 (Bitfield-Mask: 0x01)                    */
-#define USB_USB_UX20CDR_REG_RPU_TEST_SW1_Pos (5UL)                  /*!< RPU_TEST_SW1 (Bit 5)                                  */
-#define USB_USB_UX20CDR_REG_RPU_TEST_SW1_Msk (0x20UL)               /*!< RPU_TEST_SW1 (Bitfield-Mask: 0x01)                    */
-#define USB_USB_UX20CDR_REG_RPU_TEST_EN_Pos (4UL)                   /*!< RPU_TEST_EN (Bit 4)                                   */
-#define USB_USB_UX20CDR_REG_RPU_TEST_EN_Msk (0x10UL)                /*!< RPU_TEST_EN (Bitfield-Mask: 0x01)                     */
-#define USB_USB_UX20CDR_REG_RPU_TEST_SW1DM_Pos (2UL)                /*!< RPU_TEST_SW1DM (Bit 2)                                */
-#define USB_USB_UX20CDR_REG_RPU_TEST_SW1DM_Msk (0x4UL)              /*!< RPU_TEST_SW1DM (Bitfield-Mask: 0x01)                  */
-#define USB_USB_UX20CDR_REG_RPU_RCDELAY_Pos (1UL)                   /*!< RPU_RCDELAY (Bit 1)                                   */
-#define USB_USB_UX20CDR_REG_RPU_RCDELAY_Msk (0x2UL)                 /*!< RPU_RCDELAY (Bitfield-Mask: 0x01)                     */
-#define USB_USB_UX20CDR_REG_RPU_SSPROTEN_Pos (0UL)                  /*!< RPU_SSPROTEN (Bit 0)                                  */
-#define USB_USB_UX20CDR_REG_RPU_SSPROTEN_Msk (0x1UL)                /*!< RPU_SSPROTEN (Bitfield-Mask: 0x01)                    */
-/* ====================================================  USB_XCVDIAG_REG  ==================================================== */
-#define USB_USB_XCVDIAG_REG_USB_VPIN_Pos  (7UL)                     /*!< USB_VPIN (Bit 7)                                      */
-#define USB_USB_XCVDIAG_REG_USB_VPIN_Msk  (0x80UL)                  /*!< USB_VPIN (Bitfield-Mask: 0x01)                        */
-#define USB_USB_XCVDIAG_REG_USB_VMIN_Pos  (6UL)                     /*!< USB_VMIN (Bit 6)                                      */
-#define USB_USB_XCVDIAG_REG_USB_VMIN_Msk  (0x40UL)                  /*!< USB_VMIN (Bitfield-Mask: 0x01)                        */
-#define USB_USB_XCVDIAG_REG_USB_RCV_Pos   (5UL)                     /*!< USB_RCV (Bit 5)                                       */
-#define USB_USB_XCVDIAG_REG_USB_RCV_Msk   (0x20UL)                  /*!< USB_RCV (Bitfield-Mask: 0x01)                         */
-#define USB_USB_XCVDIAG_REG_USB_XCV_TXEN_Pos (3UL)                  /*!< USB_XCV_TXEN (Bit 3)                                  */
-#define USB_USB_XCVDIAG_REG_USB_XCV_TXEN_Msk (0x8UL)                /*!< USB_XCV_TXEN (Bitfield-Mask: 0x01)                    */
-#define USB_USB_XCVDIAG_REG_USB_XCV_TXn_Pos (2UL)                   /*!< USB_XCV_TXn (Bit 2)                                   */
-#define USB_USB_XCVDIAG_REG_USB_XCV_TXn_Msk (0x4UL)                 /*!< USB_XCV_TXn (Bitfield-Mask: 0x01)                     */
-#define USB_USB_XCVDIAG_REG_USB_XCV_TXp_Pos (1UL)                   /*!< USB_XCV_TXp (Bit 1)                                   */
-#define USB_USB_XCVDIAG_REG_USB_XCV_TXp_Msk (0x2UL)                 /*!< USB_XCV_TXp (Bitfield-Mask: 0x01)                     */
-#define USB_USB_XCVDIAG_REG_USB_XCV_TEST_Pos (0UL)                  /*!< USB_XCV_TEST (Bit 0)                                  */
-#define USB_USB_XCVDIAG_REG_USB_XCV_TEST_Msk (0x1UL)                /*!< USB_XCV_TEST (Bitfield-Mask: 0x01)                    */
-
-
-/* =========================================================================================================================== */
-/* ================                                          WAKEUP                                           ================ */
-/* =========================================================================================================================== */
-
-/* ===================================================  WKUP_CLEAR_P0_REG  =================================================== */
-#define WAKEUP_WKUP_CLEAR_P0_REG_WKUP_CLEAR_P0_Pos (0UL)            /*!< WKUP_CLEAR_P0 (Bit 0)                                 */
-#define WAKEUP_WKUP_CLEAR_P0_REG_WKUP_CLEAR_P0_Msk (0xffffffffUL)   /*!< WKUP_CLEAR_P0 (Bitfield-Mask: 0xffffffff)             */
-/* ===================================================  WKUP_CLEAR_P1_REG  =================================================== */
-#define WAKEUP_WKUP_CLEAR_P1_REG_WKUP_CLEAR_P1_Pos (0UL)            /*!< WKUP_CLEAR_P1 (Bit 0)                                 */
-#define WAKEUP_WKUP_CLEAR_P1_REG_WKUP_CLEAR_P1_Msk (0x7fffffUL)     /*!< WKUP_CLEAR_P1 (Bitfield-Mask: 0x7fffff)               */
-/* =====================================================  WKUP_CTRL_REG  ===================================================== */
-#define WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Pos (7UL)              /*!< WKUP_ENABLE_IRQ (Bit 7)                               */
-#define WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Msk (0x80UL)           /*!< WKUP_ENABLE_IRQ (Bitfield-Mask: 0x01)                 */
-#define WAKEUP_WKUP_CTRL_REG_WKUP_SFT_KEYHIT_Pos (6UL)              /*!< WKUP_SFT_KEYHIT (Bit 6)                               */
-#define WAKEUP_WKUP_CTRL_REG_WKUP_SFT_KEYHIT_Msk (0x40UL)           /*!< WKUP_SFT_KEYHIT (Bitfield-Mask: 0x01)                 */
-#define WAKEUP_WKUP_CTRL_REG_WKUP_DEB_VALUE_Pos (0UL)               /*!< WKUP_DEB_VALUE (Bit 0)                                */
-#define WAKEUP_WKUP_CTRL_REG_WKUP_DEB_VALUE_Msk (0x3fUL)            /*!< WKUP_DEB_VALUE (Bitfield-Mask: 0x3f)                  */
-/* ====================================================  WKUP_POL_P0_REG  ==================================================== */
-#define WAKEUP_WKUP_POL_P0_REG_WKUP_POL_P0_Pos (0UL)                /*!< WKUP_POL_P0 (Bit 0)                                   */
-#define WAKEUP_WKUP_POL_P0_REG_WKUP_POL_P0_Msk (0xffffffffUL)       /*!< WKUP_POL_P0 (Bitfield-Mask: 0xffffffff)               */
-/* ====================================================  WKUP_POL_P1_REG  ==================================================== */
-#define WAKEUP_WKUP_POL_P1_REG_WKUP_POL_P1_Pos (0UL)                /*!< WKUP_POL_P1 (Bit 0)                                   */
-#define WAKEUP_WKUP_POL_P1_REG_WKUP_POL_P1_Msk (0x7fffffUL)         /*!< WKUP_POL_P1 (Bitfield-Mask: 0x7fffff)                 */
-/* ==================================================  WKUP_RESET_IRQ_REG  =================================================== */
-#define WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Pos (0UL)            /*!< WKUP_IRQ_RST (Bit 0)                                  */
-#define WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Msk (0xffffUL)       /*!< WKUP_IRQ_RST (Bitfield-Mask: 0xffff)                  */
-/* ==================================================  WKUP_SELECT_P0_REG  =================================================== */
-#define WAKEUP_WKUP_SELECT_P0_REG_WKUP_SELECT_P0_Pos (0UL)          /*!< WKUP_SELECT_P0 (Bit 0)                                */
-#define WAKEUP_WKUP_SELECT_P0_REG_WKUP_SELECT_P0_Msk (0xffffffffUL) /*!< WKUP_SELECT_P0 (Bitfield-Mask: 0xffffffff)            */
-/* ==================================================  WKUP_SELECT_P1_REG  =================================================== */
-#define WAKEUP_WKUP_SELECT_P1_REG_WKUP_SELECT_P1_Pos (0UL)          /*!< WKUP_SELECT_P1 (Bit 0)                                */
-#define WAKEUP_WKUP_SELECT_P1_REG_WKUP_SELECT_P1_Msk (0x7fffffUL)   /*!< WKUP_SELECT_P1 (Bitfield-Mask: 0x7fffff)              */
-/* =================================================  WKUP_SEL_GPIO_P0_REG  ================================================== */
-#define WAKEUP_WKUP_SEL_GPIO_P0_REG_WKUP_SEL_GPIO_P0_Pos (0UL)      /*!< WKUP_SEL_GPIO_P0 (Bit 0)                              */
-#define WAKEUP_WKUP_SEL_GPIO_P0_REG_WKUP_SEL_GPIO_P0_Msk (0xffffffffUL) /*!< WKUP_SEL_GPIO_P0 (Bitfield-Mask: 0xffffffff)      */
-/* =================================================  WKUP_SEL_GPIO_P1_REG  ================================================== */
-#define WAKEUP_WKUP_SEL_GPIO_P1_REG_WKUP_SEL_GPIO_P1_Pos (0UL)      /*!< WKUP_SEL_GPIO_P1 (Bit 0)                              */
-#define WAKEUP_WKUP_SEL_GPIO_P1_REG_WKUP_SEL_GPIO_P1_Msk (0x7fffffUL) /*!< WKUP_SEL_GPIO_P1 (Bitfield-Mask: 0x7fffff)          */
-/* ==================================================  WKUP_STATUS_P0_REG  =================================================== */
-#define WAKEUP_WKUP_STATUS_P0_REG_WKUP_STAT_P0_Pos (0UL)            /*!< WKUP_STAT_P0 (Bit 0)                                  */
-#define WAKEUP_WKUP_STATUS_P0_REG_WKUP_STAT_P0_Msk (0xffffffffUL)   /*!< WKUP_STAT_P0 (Bitfield-Mask: 0xffffffff)              */
-/* ==================================================  WKUP_STATUS_P1_REG  =================================================== */
-#define WAKEUP_WKUP_STATUS_P1_REG_WKUP_STAT_P1_Pos (0UL)            /*!< WKUP_STAT_P1 (Bit 0)                                  */
-#define WAKEUP_WKUP_STATUS_P1_REG_WKUP_STAT_P1_Msk (0x7fffffUL)     /*!< WKUP_STAT_P1 (Bitfield-Mask: 0x7fffff)                */
-
-/** @} */ /* End of group PosMask_peripherals */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* DA1469X_H */
-
-
-/** @} */ /* End of group DA1469x */
-
-/** @} */ /* End of group PLA_BSP_REGISTERS */
diff --git a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_compiler.h b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_compiler.h
deleted file mode 100755
index fdb1a971..00000000
--- a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_compiler.h
+++ /dev/null
@@ -1,271 +0,0 @@
-/**************************************************************************//**
- * @file     cmsis_compiler.h
- * @brief    CMSIS compiler generic header file
- * @version  V5.1.0
- * @date     09. October 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_COMPILER_H
-#define __CMSIS_COMPILER_H
-
-#include <stdint.h>
-
-/*
- * Arm Compiler 4/5
- */
-#if   defined ( __CC_ARM )
-  #include "cmsis_armcc.h"
-
-
-/*
- * Arm Compiler 6.6 LTM (armclang)
- */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
-  #include "cmsis_armclang_ltm.h"
-
-  /*
- * Arm Compiler above 6.10.1 (armclang)
- */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
-  #include "cmsis_armclang.h"
-
-
-/*
- * GNU Compiler
- */
-#elif defined ( __GNUC__ )
-  #include "cmsis_gcc.h"
-
-
-/*
- * IAR Compiler
- */
-#elif defined ( __ICCARM__ )
-  #include <cmsis_iccarm.h>
-
-
-/*
- * TI Arm Compiler
- */
-#elif defined ( __TI_ARM__ )
-  #include <cmsis_ccs.h>
-
-  #ifndef   __ASM
-    #define __ASM                                  __asm
-  #endif
-  #ifndef   __INLINE
-    #define __INLINE                               inline
-  #endif
-  #ifndef   __STATIC_INLINE
-    #define __STATIC_INLINE                        static inline
-  #endif
-  #ifndef   __STATIC_FORCEINLINE
-    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
-  #endif
-  #ifndef   __NO_RETURN
-    #define __NO_RETURN                            __attribute__((noreturn))
-  #endif
-  #ifndef   __USED
-    #define __USED                                 __attribute__((used))
-  #endif
-  #ifndef   __WEAK
-    #define __WEAK                                 __attribute__((weak))
-  #endif
-  #ifndef   __PACKED
-    #define __PACKED                               __attribute__((packed))
-  #endif
-  #ifndef   __PACKED_STRUCT
-    #define __PACKED_STRUCT                        struct __attribute__((packed))
-  #endif
-  #ifndef   __PACKED_UNION
-    #define __PACKED_UNION                         union __attribute__((packed))
-  #endif
-  #ifndef   __UNALIGNED_UINT32        /* deprecated */
-    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
-    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT16_WRITE
-    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT16_READ
-    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT32_WRITE
-    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT32_READ
-    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __ALIGNED
-    #define __ALIGNED(x)                           __attribute__((aligned(x)))
-  #endif
-  #ifndef   __RESTRICT
-    #define __RESTRICT                             __restrict
-  #endif
-
-
-/*
- * TASKING Compiler
- */
-#elif defined ( __TASKING__ )
-  /*
-   * The CMSIS functions have been implemented as intrinsics in the compiler.
-   * Please use "carm -?i" to get an up to date list of all intrinsics,
-   * Including the CMSIS ones.
-   */
-
-  #ifndef   __ASM
-    #define __ASM                                  __asm
-  #endif
-  #ifndef   __INLINE
-    #define __INLINE                               inline
-  #endif
-  #ifndef   __STATIC_INLINE
-    #define __STATIC_INLINE                        static inline
-  #endif
-  #ifndef   __STATIC_FORCEINLINE
-    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
-  #endif
-  #ifndef   __NO_RETURN
-    #define __NO_RETURN                            __attribute__((noreturn))
-  #endif
-  #ifndef   __USED
-    #define __USED                                 __attribute__((used))
-  #endif
-  #ifndef   __WEAK
-    #define __WEAK                                 __attribute__((weak))
-  #endif
-  #ifndef   __PACKED
-    #define __PACKED                               __packed__
-  #endif
-  #ifndef   __PACKED_STRUCT
-    #define __PACKED_STRUCT                        struct __packed__
-  #endif
-  #ifndef   __PACKED_UNION
-    #define __PACKED_UNION                         union __packed__
-  #endif
-  #ifndef   __UNALIGNED_UINT32        /* deprecated */
-    struct __packed__ T_UINT32 { uint32_t v; };
-    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT16_WRITE
-    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT16_READ
-    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT32_WRITE
-    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT32_READ
-    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __ALIGNED
-    #define __ALIGNED(x)              __align(x)
-  #endif
-  #ifndef   __RESTRICT
-    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
-    #define __RESTRICT
-  #endif
-
-
-/*
- * COSMIC Compiler
- */
-#elif defined ( __CSMC__ )
-   #include <cmsis_csm.h>
-
- #ifndef   __ASM
-    #define __ASM                                  _asm
-  #endif
-  #ifndef   __INLINE
-    #define __INLINE                               inline
-  #endif
-  #ifndef   __STATIC_INLINE
-    #define __STATIC_INLINE                        static inline
-  #endif
-  #ifndef   __STATIC_FORCEINLINE
-    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
-  #endif
-  #ifndef   __NO_RETURN
-    // NO RETURN is automatically detected hence no warning here
-    #define __NO_RETURN
-  #endif
-  #ifndef   __USED
-    #warning No compiler specific solution for __USED. __USED is ignored.
-    #define __USED
-  #endif
-  #ifndef   __WEAK
-    #define __WEAK                                 __weak
-  #endif
-  #ifndef   __PACKED
-    #define __PACKED                               @packed
-  #endif
-  #ifndef   __PACKED_STRUCT
-    #define __PACKED_STRUCT                        @packed struct
-  #endif
-  #ifndef   __PACKED_UNION
-    #define __PACKED_UNION                         @packed union
-  #endif
-  #ifndef   __UNALIGNED_UINT32        /* deprecated */
-    @packed struct T_UINT32 { uint32_t v; };
-    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT16_WRITE
-    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT16_READ
-    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT32_WRITE
-    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT32_READ
-    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __ALIGNED
-    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
-    #define __ALIGNED(x)
-  #endif
-  #ifndef   __RESTRICT
-    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
-    #define __RESTRICT
-  #endif
-
-
-#else
-  #error Unknown compiler.
-#endif
-
-
-#endif /* __CMSIS_COMPILER_H */
-
diff --git a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_gcc.h b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_gcc.h
deleted file mode 100755
index 47a4b59d..00000000
--- a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_gcc.h
+++ /dev/null
@@ -1,2102 +0,0 @@
-/**************************************************************************//**
- * @file     cmsis_gcc.h
- * @brief    CMSIS compiler GCC header file
- * @version  V5.1.0
- * @date     20. December 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
- /* Copyright (c) 2019 Modified by Dialog Semiconductor */
-
-#ifndef __CMSIS_GCC_H
-#define __CMSIS_GCC_H
-
-/* ignore some GCC warnings */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wsign-conversion"
-#pragma GCC diagnostic ignored "-Wconversion"
-#pragma GCC diagnostic ignored "-Wunused-parameter"
-
-/* Fallback for __has_builtin */
-#ifndef __has_builtin
-  #define __has_builtin(x) (0)
-#endif
-
-/* CMSIS compiler specific defines */
-#ifndef   __ASM
-  #define __ASM                                  __asm
-#endif
-#ifndef   __INLINE
-  #define __INLINE                               inline
-#endif
-#ifndef   __STATIC_INLINE
-  #define __STATIC_INLINE                        static inline
-#endif
-#ifndef   __STATIC_FORCEINLINE                 
-  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
-#endif                                           
-#ifndef   __NO_RETURN
-  #define __NO_RETURN                            __attribute__((__noreturn__))
-#endif
-#ifndef   __USED
-  #define __USED                                 __attribute__((used))
-#endif
-#ifndef   __WEAK
-  #define __WEAK                                 __attribute__((weak))
-#endif
-#ifndef   __PACKED
-  #define __PACKED                               __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __PACKED_STRUCT
-  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __PACKED_UNION
-  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __UNALIGNED_UINT32        /* deprecated */
-  #pragma GCC diagnostic push
-  #pragma GCC diagnostic ignored "-Wpacked"
-  #pragma GCC diagnostic ignored "-Wattributes"
-  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
-  #pragma GCC diagnostic pop
-  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef   __UNALIGNED_UINT16_WRITE
-  #pragma GCC diagnostic push
-  #pragma GCC diagnostic ignored "-Wpacked"
-  #pragma GCC diagnostic ignored "-Wattributes"
-  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-  #pragma GCC diagnostic pop
-  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT16_READ
-  #pragma GCC diagnostic push
-  #pragma GCC diagnostic ignored "-Wpacked"
-  #pragma GCC diagnostic ignored "-Wattributes"
-  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-  #pragma GCC diagnostic pop
-  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-#endif
-#ifndef   __UNALIGNED_UINT32_WRITE
-  #pragma GCC diagnostic push
-  #pragma GCC diagnostic ignored "-Wpacked"
-  #pragma GCC diagnostic ignored "-Wattributes"
-  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-  #pragma GCC diagnostic pop
-  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT32_READ
-  #pragma GCC diagnostic push
-  #pragma GCC diagnostic ignored "-Wpacked"
-  #pragma GCC diagnostic ignored "-Wattributes"
-  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-  #pragma GCC diagnostic pop
-  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-#endif
-#ifndef   __ALIGNED
-  #define __ALIGNED(x)                           __attribute__((aligned(x)))
-#endif
-#ifndef   __RESTRICT
-  #define __RESTRICT                             __restrict
-#endif
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-/**
-  \brief   Enable IRQ Interrupts
-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __enable_irq(void)
-{
-  __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/**
-  \brief   Disable IRQ Interrupts
-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __disable_irq(void)
-{
-  __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/**
-  \brief   Get Control Register
-  \details Returns the content of the Control Register.
-  \return               Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Control Register (non-secure)
-  \details Returns the content of the non-secure Control Register when in secure mode.
-  \return               non-secure Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Control Register
-  \details Writes the given value to the Control Register.
-  \param [in]    control  Control Register value to set
- */
-__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Control Register (non-secure)
-  \details Writes the given value to the non-secure Control Register when in secure state.
-  \param [in]    control  Control Register value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
-{
-  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Get IPSR Register
-  \details Returns the content of the IPSR Register.
-  \return               IPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get APSR Register
-  \details Returns the content of the APSR Register.
-  \return               APSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_APSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get xPSR Register
-  \details Returns the content of the xPSR Register.
-  \return               xPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get Process Stack Pointer
-  \details Returns the current value of the Process Stack Pointer (PSP).
-  \return               PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSP(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Process Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
-  \return               PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer
-  \details Assigns the given value to the Process Stack Pointer (PSP).
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer
-  \details Returns the current value of the Main Stack Pointer (MSP).
-  \return               MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSP(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, msp" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Main Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
-  \return               MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer
-  \details Assigns the given value to the Main Stack Pointer (MSP).
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Main Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
-}
-#endif
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
-  \return               SP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Set Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
-  \param [in]    topOfStack  Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
-{
-  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Priority Mask
-  \details Returns the current state of the priority mask bit from the Priority Mask Register.
-  \return               Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Priority Mask (non-secure)
-  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
-  \return               Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Priority Mask
-  \details Assigns the given value to the Priority Mask Register.
-  \param [in]    priMask  Priority Mask
- */
-__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Priority Mask (non-secure)
-  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
-  \param [in]    priMask  Priority Mask
- */
-__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
-}
-#endif
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Enable FIQ
-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __enable_fault_irq(void)
-{
-  __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/**
-  \brief   Disable FIQ
-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __disable_fault_irq(void)
-{
-  __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/**
-  \brief   Get Base Priority
-  \details Returns the current value of the Base Priority register.
-  \return               Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Base Priority (non-secure)
-  \details Returns the current value of the non-secure Base Priority register when in secure state.
-  \return               Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority
-  \details Assigns the given value to the Base Priority register.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Base Priority (non-secure)
-  \details Assigns the given value to the non-secure Base Priority register when in secure state.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority with condition
-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-           or the new value increases the BASEPRI priority level.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
-}
-
-
-/**
-  \brief   Get Fault Mask
-  \details Returns the current value of the Fault Mask register.
-  \return               Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Fault Mask (non-secure)
-  \details Returns the current value of the non-secure Fault Mask register when in secure state.
-  \return               Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Fault Mask
-  \details Assigns the given value to the Fault Mask register.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Fault Mask (non-secure)
-  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-
-/**
-  \brief   Get Process Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always in non-secure
-  mode.
-  
-  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
-  \return               PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-    // without main extensions, the non-secure PSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
-  return result;
-#endif
-}
-
-#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Process Stack Pointer Limit (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always.
-
-  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \return               PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure PSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
-  return result;
-#endif
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored in non-secure
-  mode.
-  
-  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-  // without main extensions, the non-secure PSPLIM is RAZ/WI
-  (void)ProcStackPtrLimit;
-#else
-  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored.
-
-  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure PSPLIM is RAZ/WI
-  (void)ProcStackPtrLimit;
-#else
-  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
-#endif
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always in non-secure
-  mode.
-
-  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
-  \return               MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
-  return result;
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
-/**
-  \brief   Get Main Stack Pointer Limit (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always.
-
-  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
-  \return               MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
-  return result;
-#endif
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored in non-secure
-  mode.
-
-  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
-  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  (void)MainStackPtrLimit;
-#else
-  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
-/**
-  \brief   Set Main Stack Pointer Limit (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored.
-
-  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
-  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  (void)MainStackPtrLimit;
-#else
-  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
-#endif
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-
-/**
-  \brief   Get FPSCR
-  \details Returns the current value of the Floating Point Status/Control register.
-  \return               Floating Point Status/Control register value
- */
-__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-#if __has_builtin(__builtin_arm_get_fpscr) 
-// Re-enable using built-in when GCC has been fixed
-// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
-  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
-  return __builtin_arm_get_fpscr();
-#else
-  uint32_t result;
-
-  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
-  return(result);
-#endif
-#else
-  return(0U);
-#endif
-}
-
-
-/**
-  \brief   Set FPSCR
-  \details Assigns the given value to the Floating Point Status/Control register.
-  \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-#if __has_builtin(__builtin_arm_set_fpscr)
-// Re-enable using built-in when GCC has been fixed
-// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
-  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
-  __builtin_arm_set_fpscr(fpscr);
-#else
-  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
-#endif
-#else
-  (void)fpscr;
-#endif
-}
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constraint "l"
- * Otherwise, use general registers, specified by constraint "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_RW_REG(r) "+l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_RW_REG(r) "+r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/**
-  \brief   No Operation
-  \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP()                             __ASM volatile ("nop")
-
-/**
-  \brief   Wait For Interrupt
-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-#define __WFI()                             __ASM volatile ("wfi")
-
-
-/**
-  \brief   Wait For Event
-  \details Wait For Event is a hint instruction that permits the processor to enter
-           a low-power state until one of a number of events occurs.
- */
-#define __WFE()                             __ASM volatile ("wfe")
-
-
-/**
-  \brief   Send Event
-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV()                             __ASM volatile ("sev")
-
-
-/**
-  \brief   Instruction Synchronization Barrier
-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
-           so that all instructions following the ISB are fetched from cache or memory,
-           after the instruction has been completed.
- */
-__STATIC_FORCEINLINE void __ISB(void)
-{
-  __ASM volatile ("isb 0xF":::"memory");
-}
-
-
-/**
-  \brief   Data Synchronization Barrier
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
- */
-__STATIC_FORCEINLINE void __DSB(void)
-{
-  __ASM volatile ("dsb 0xF":::"memory");
-}
-
-
-/**
-  \brief   Data Memory Barrier
-  \details Ensures the apparent order of the explicit memory operations before
-           and after the instruction, without ensuring their completion.
- */
-__STATIC_FORCEINLINE void __DMB(void)
-{
-  __ASM volatile ("dmb 0xF":::"memory");
-}
-
-
-/**
-  \brief   Reverse byte order (32 bit)
-  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
-  return __builtin_bswap32(value);
-#else
-  uint32_t result;
-
-  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return result;
-#endif
-}
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return result;
-}
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-  return (int16_t)__builtin_bswap16(value);
-#else
-  int16_t result;
-
-  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return result;
-#endif
-}
-
-
-/**
-  \brief   Rotate Right in unsigned value (32 bit)
-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-  \param [in]    op1  Value to rotate
-  \param [in]    op2  Number of Bits to rotate
-  \return               Rotated value
- */
-__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-  op2 %= 32U;
-  if (op2 == 0U)
-  {
-    return op1;
-  }
-  return (op1 >> op2) | (op1 << (32U - op2));
-}
-
-
-/**
-  \brief   Breakpoint
-  \details Causes the processor to enter Debug state.
-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-  \param [in]    value  is ignored by the processor.
-                 If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
-
-
-/**
-  \brief   Reverse bit order of value
-  \details Reverses the bit order of the given value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-#else
-  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
-
-  result = value;                      /* r will be reversed bits of v; first get LSB of v */
-  for (value >>= 1U; value != 0U; value >>= 1U)
-  {
-    result <<= 1U;
-    result |= value & 1U;
-    s--;
-  }
-  result <<= s;                        /* shift when v's highest bits are zero */
-#endif
-  return result;
-}
-
-
-/**
-  \brief   Count leading zeros
-  \details Counts the number of leading zeros of a data value.
-  \param [in]  value  Value to count the leading zeros
-  \return             number of leading zeros in value
- */
-__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
-{
-  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
-     __builtin_clz(0) is undefined behaviour, so handle this case specially.
-     This guarantees ARM-compatible results if happening to compile on a non-ARM
-     target, and ensures the compiler doesn't decide to activate any
-     optimisations using the logic "value was passed to __builtin_clz, so it
-     is non-zero".
-     ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
-     single CLZ instruction.
-   */
-  if (value == 0U)
-  {
-    return 32U;
-  }
-  return __builtin_clz(value);
-}
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   LDR Exclusive (8 bit)
-  \details Executes a exclusive LDR instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDR Exclusive (16 bit)
-  \details Executes a exclusive LDR instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDR Exclusive (32 bit)
-  \details Executes a exclusive LDR instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
-   return(result);
-}
-
-
-/**
-  \brief   STR Exclusive (8 bit)
-  \details Executes a exclusive STR instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/**
-  \brief   STR Exclusive (16 bit)
-  \details Executes a exclusive STR instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/**
-  \brief   STR Exclusive (32 bit)
-  \details Executes a exclusive STR instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
-   return(result);
-}
-
-
-/**
-  \brief   Remove the exclusive lock
-  \details Removes the exclusive lock which is created by LDREX.
- */
-__STATIC_FORCEINLINE void __CLREX(void)
-{
-  __ASM volatile ("clrex" ::: "memory");
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  ARG1  Value to be saturated
-  \param [in]  ARG2  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-__extension__ \
-({                          \
-  int32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  ARG1  Value to be saturated
-  \param [in]  ARG2  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-#define __USAT(ARG1,ARG2) \
- __extension__ \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/**
-  \brief   Rotate Right with Extend (32 bit)
-  \details Moves each bit of a bitstring right by one bit.
-           The carry input is shifted in at the left end of the bitstring.
-  \param [in]    value  Value to rotate
-  \return               Rotated value
- */
-__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-
-
-/**
-  \brief   LDRT Unprivileged (8 bit)
-  \details Executes a Unprivileged LDRT instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
-#endif
-   return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (16 bit)
-  \details Executes a Unprivileged LDRT instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
-#endif
-   return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (32 bit)
-  \details Executes a Unprivileged LDRT instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return(result);
-}
-
-
-/**
-  \brief   STRT Unprivileged (8 bit)
-  \details Executes a Unprivileged STRT instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
-{
-   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (16 bit)
-  \details Executes a Unprivileged STRT instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
-{
-   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (32 bit)
-  \details Executes a Unprivileged STRT instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
-{
-   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
-}
-
-#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]    val  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
-{
-  if ((sat >= 1U) && (sat <= 32U))
-  {
-    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
-    const int32_t min = -1 - max ;
-    if (val > max)
-    {
-      return max;
-    }
-    else if (val < min)
-    {
-      return min;
-    }
-  }
-  return val;
-}
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]    val  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
-{
-  if (sat <= 31U)
-  {
-    const uint32_t max = ((1U << sat) - 1U);
-    if (val > (int32_t)max)
-    {
-      return max;
-    }
-    else if (val < 0)
-    {
-      return 0U;
-    }
-  }
-  return (uint32_t)val;
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   Load-Acquire (8 bit)
-  \details Executes a LDAB instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return ((uint8_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (16 bit)
-  \details Executes a LDAH instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return ((uint16_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (32 bit)
-  \details Executes a LDA instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return(result);
-}
-
-
-/**
-  \brief   Store-Release (8 bit)
-  \details Executes a STLB instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
-{
-   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Store-Release (16 bit)
-  \details Executes a STLH instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
-{
-   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Store-Release (32 bit)
-  \details Executes a STL instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
-{
-   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (8 bit)
-  \details Executes a LDAB exclusive instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return ((uint8_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (16 bit)
-  \details Executes a LDAH exclusive instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return ((uint16_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (32 bit)
-  \details Executes a LDA exclusive instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return(result);
-}
-
-
-/**
-  \brief   Store-Release Exclusive (8 bit)
-  \details Executes a STLB exclusive instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
-{
-   uint32_t result;
-
-   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/**
-  \brief   Store-Release Exclusive (16 bit)
-  \details Executes a STLH exclusive instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
-{
-   uint32_t result;
-
-   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/**
-  \brief   Store-Release Exclusive (32 bit)
-  \details Executes a STL exclusive instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
-{
-   uint32_t result;
-
-   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
-
-__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({                          \
-  int32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
-{
-  int32_t result;
-
-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
-{
-  int32_t result;
-
-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-#if 0
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  if (ARG3 == 0) \
-    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
-  else \
-    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-#endif
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
- int32_t result;
-
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#endif /* (__ARM_FEATURE_DSP == 1) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#pragma GCC diagnostic pop
-
-#endif /* __CMSIS_GCC_H */
diff --git a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_version.h b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_version.h
deleted file mode 100755
index 660f612a..00000000
--- a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_version.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/**************************************************************************//**
- * @file     cmsis_version.h
- * @brief    CMSIS Core(M) Version definitions
- * @version  V5.0.2
- * @date     19. April 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CMSIS_VERSION_H
-#define __CMSIS_VERSION_H
-
-/*  CMSIS Version definitions */
-#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
-#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
-#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
-                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
-#endif
diff --git a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm0.h b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm0.h
deleted file mode 100755
index e2cf6b96..00000000
--- a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm0.h
+++ /dev/null
@@ -1,950 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm0.h
- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version  V5.0.6
- * @date     13. March 2019
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
- /* Copyright (c) 2019 Modified by Dialog Semiconductor */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM0_H_GENERIC
-#define __CORE_CM0_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M0
-  @{
- */
-
-#include "cmsis_version.h"
- 
-/*  CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
-                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_FP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0_H_DEPENDANT
-#define __CORE_CM0_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM0_REV
-    #define __CM0_REV               0x0000U
-    #warning "__CM0_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M0 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[31U];
-  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RESERVED1[31U];
-  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[31U];
-  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[31U];
-        uint32_t RESERVED4[64U];
-  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-        uint32_t RESERVED0;
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-        uint32_t RESERVED1;
-  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
-            Therefore they are not covered by the Cortex-M0 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* The following EXC_RETURN values are saved the LR on exception entry */
-#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
-#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
-#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
-
-
-/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-#define __NVIC_SetPriorityGrouping(X) (void)(X)
-#define __NVIC_GetPriorityGrouping()  (0U)
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref __NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]          Priority  Priority value, which can be retrieved with the function \ref __NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           Address 0 must be mapped to SRAM.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-  uint32_t vectors = 0x0U;
-  (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-  uint32_t vectors = 0x0U;
-  return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm33.h b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm33.h
deleted file mode 100755
index 7249e133..00000000
--- a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm33.h
+++ /dev/null
@@ -1,2908 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm33.h
- * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File
- * @version  V5.1.0
- * @date     12. November 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
- /* Copyright (c) 2019 Modified by Dialog Semiconductor */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM33_H_GENERIC
-#define __CORE_CM33_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M33
-  @{
- */
-
-#include "cmsis_version.h"
-
-/*  CMSIS CM33 definitions */
-#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
-#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
-                                     __CM33_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_M                 (33U)                                       /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-  #if defined (__TARGET_FPU_VFP)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
-    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
-      #define __DSP_USED       1U
-    #else
-      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
-      #define __DSP_USED         0U
-    #endif
-  #else
-    #define __DSP_USED         0U
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined (__ARM_FP)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
-    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
-      #define __DSP_USED       1U
-    #else
-      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
-      #define __DSP_USED         0U
-    #endif
-  #else
-    #define __DSP_USED         0U
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
-    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
-      #define __DSP_USED       1U
-    #else
-      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
-      #define __DSP_USED         0U
-    #endif
-  #else
-    #define __DSP_USED         0U
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined (__ARMVFP__)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
-    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
-      #define __DSP_USED       1U
-    #else
-      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
-      #define __DSP_USED         0U
-    #endif
-  #else
-    #define __DSP_USED         0U
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined (__TI_VFP_SUPPORT__)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined (__FPU_VFP__)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM33_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM33_H_DEPENDANT
-#define __CORE_CM33_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM33_REV
-    #define __CM33_REV                0x0000U
-    #warning "__CM33_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0U
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __SAUREGION_PRESENT
-    #define __SAUREGION_PRESENT       0U
-    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __DSP_PRESENT
-    #define __DSP_PRESENT             0U
-    #warning "__DSP_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          3U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M33 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core SAU Register
-  - Core FPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
-    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
-    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
-    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
-#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
-
-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[16U];
-  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[16U];
-  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[16U];
-  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[16U];
-  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-        uint32_t RESERVED4[16U];
-  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
-        uint32_t RESERVED5[16U];
-  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-        uint32_t RESERVED6[580U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
-  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
-  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
-  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
-        uint32_t RESERVED3[92U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
-        uint32_t RESERVED4[15U];
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
-  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
-        uint32_t RESERVED5[1U];
-  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
-        uint32_t RESERVED6[1U];
-  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
-  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
-  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
-  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
-  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
-  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
-  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
-  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
-#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
-
-#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
-#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
-#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
-
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
-#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
-#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/* SCB Non-Secure Access Control Register Definitions */
-#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
-#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
-
-#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
-#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
-
-#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
-#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
-
-/* SCB Cache Level ID Register Definitions */
-#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
-
-/* SCB Cache Type Register Definitions */
-#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
-
-/* SCB Cache Size ID Register Definitions */
-#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
-
-/* SCB Cache Size Selection Register Definitions */
-#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register Definitions */
-#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
-
-/* SCB D-Cache Invalidate by Set-way Register Definitions */
-#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
-#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
-
-#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
-#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
-
-/* SCB D-Cache Clean by Set-way Register Definitions */
-#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
-#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
-
-#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
-#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
-
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
-#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
-#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
-
-#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
-#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __OM  union
-  {
-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-        uint32_t RESERVED0[864U];
-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-        uint32_t RESERVED1[15U];
-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-        uint32_t RESERVED2[15U];
-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-        uint32_t RESERVED3[32U];
-        uint32_t RESERVED4[43U];
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-        uint32_t RESERVED5[1U];
-  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
-        uint32_t RESERVED6[4U];
-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Stimulus Port Register Definitions */
-#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
-#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
-
-#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
-#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
-#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
-
-#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
-#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-        uint32_t RESERVED1[1U];
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-        uint32_t RESERVED2[1U];
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-        uint32_t RESERVED3[1U];
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-        uint32_t RESERVED4[1U];
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-        uint32_t RESERVED5[1U];
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-        uint32_t RESERVED6[1U];
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-        uint32_t RESERVED7[1U];
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-        uint32_t RESERVED8[1U];
-  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
-        uint32_t RESERVED9[1U];
-  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
-        uint32_t RESERVED10[1U];
-  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
-        uint32_t RESERVED11[1U];
-  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
-        uint32_t RESERVED12[1U];
-  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
-        uint32_t RESERVED13[1U];
-  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
-        uint32_t RESERVED14[1U];
-  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
-        uint32_t RESERVED15[1U];
-  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
-        uint32_t RESERVED16[1U];
-  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
-        uint32_t RESERVED17[1U];
-  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
-        uint32_t RESERVED18[1U];
-  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
-        uint32_t RESERVED19[1U];
-  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
-        uint32_t RESERVED20[1U];
-  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
-        uint32_t RESERVED21[1U];
-  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
-        uint32_t RESERVED22[1U];
-  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
-        uint32_t RESERVED23[1U];
-  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
-        uint32_t RESERVED24[1U];
-  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
-        uint32_t RESERVED25[1U];
-  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
-        uint32_t RESERVED26[1U];
-  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
-        uint32_t RESERVED27[1U];
-  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
-        uint32_t RESERVED28[1U];
-  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
-        uint32_t RESERVED29[1U];
-  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
-        uint32_t RESERVED30[1U];
-  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
-        uint32_t RESERVED31[1U];
-  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
-        uint32_t RESERVED32[934U];
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
-        uint32_t RESERVED33[1U];
-  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
-#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-        uint32_t RESERVED1[55U];
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-        uint32_t RESERVED2[131U];
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
-        uint32_t RESERVED3[759U];
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
-  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */
-  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */
-        uint32_t RESERVED4[1U];
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */
-  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-        uint32_t RESERVED5[39U];
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-        uint32_t RESERVED7[8U];
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
-#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration Test FIFO Test Data 0 Register Definitions */
-#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
-#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
-
-#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
-#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
-
-#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
-#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
-
-#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
-#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
-
-#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
-#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
-
-#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
-#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
-
-#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
-#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
-
-/* TPI Integration Test ATB Control Register 2 Register Definitions */
-#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */
-#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */
-
-#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */
-#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */
-
-#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */
-#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */
-
-#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */
-#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */
-
-/* TPI Integration Test FIFO Test Data 1 Register Definitions */
-#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
-#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
-
-#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
-#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
-
-#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
-#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
-
-#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
-#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
-
-#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
-#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
-
-#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
-#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
-
-#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
-#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
-
-/* TPI Integration Test ATB Control Register 0 Definitions */
-#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */
-#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */
-
-#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */
-#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */
-
-#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */
-#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */
-
-#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */
-#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */
-#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
-  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
-  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
-  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
-        uint32_t RESERVED0[1];
-  union {
-  __IOM uint32_t MAIR[2];
-  struct {
-  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
-  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
-  };
-  };
-} MPU_Type;
-
-#define MPU_TYPE_RALIASES                  4U
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
-#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
-
-#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
-#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
-  \brief    Type definitions for the Security Attribution Unit (SAU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
-#else
-        uint32_t RESERVED0[3];
-#endif
-  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
-  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/* Secure Fault Status Register Definitions */
-#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
-#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
-
-#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
-#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
-
-#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
-#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
-
-#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
-#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
-
-#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
-#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
-
-#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
-#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
-
-#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
-#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
-
-#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
-#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-  \brief    Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
-  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
-  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
-#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
-
-#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
-#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
-
-#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
-#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
-
-#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
-#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
-
-#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
-#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
-
-#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
-#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
-#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
-#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-        uint32_t RESERVED4[1U];
-  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
-  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
-  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
-  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
-  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
-  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
-  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
-  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
-  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
-
-  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
-  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
-  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
-  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
-  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
-  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
-  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
-  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
-
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
-    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
-  #endif
-
-  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
-    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
-  #endif
-
-  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
-  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
-  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
-  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
-  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
-  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
-
-  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
-  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
-  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
-  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
-  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
-
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
-    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
-  #endif
-
-  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
-  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-  #define NVIC_GetActive              __NVIC_GetActive
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
-
-/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
-#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
-
-/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
-#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
-#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
-#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
-#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
-#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
-#define EXC_RETURN_SPSEL           (0x00000004UL)     /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP           */
-#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
-
-/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
-#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
-#else 
-#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
-#endif
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Get Interrupt Target State
-  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-  \return             1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Target State
-  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Clear Interrupt Target State
-  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else
-  {
-    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref __NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with \ref __NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Set Priority Grouping (non-secure)
-  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB_NS->AIRCR;                                                /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
-  SCB_NS->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping (non-secure)
-  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
-{
-  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt (non-secure)
-  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status (non-secure)
-  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt (non-secure)
-  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt (non-secure)
-  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt (non-secure)
-  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt (non-secure)
-  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt (non-secure)
-  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority (non-secure)
-  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else
-  {
-    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority (non-secure)
-  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-/* ##########################  MPU functions  #################################### */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-
-#include "mpu_armv8.h"
-
-#endif
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-  uint32_t mvfr0;
-
-  mvfr0 = FPU->MVFR0;
-  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
-  {
-    return 2U;           /* Double + Single precision FPU */
-  }
-  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
-  {
-    return 1U;           /* Single precision FPU */
-  }
-  else
-  {
-    return 0U;           /* No FPU */
-  }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##########################   SAU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SAUFunctions SAU Functions
-  \brief    Functions that configure the SAU.
-  @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
-  \brief   Enable SAU
-  \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
-    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
-  \brief   Disable SAU
-  \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
-    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   System Tick Configuration (non-secure)
-  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                         /* Reload value impossible */
-  }
-
-  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
-  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
-  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                      SysTick_CTRL_TICKINT_Msk   |
-                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                           /* Function successful */
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0U].u32 == 0UL)
-    {
-      __NOP();
-    }
-    ITM->PORT[0U].u8 = (uint8_t)ch;
-  }
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
-  {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
-  {
-    return (0);                              /* no character available */
-  }
-  else
-  {
-    return (1);                              /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM33_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/mpu_armv8.h b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/mpu_armv8.h
deleted file mode 100755
index bc3b0510..00000000
--- a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/mpu_armv8.h
+++ /dev/null
@@ -1,347 +0,0 @@
-/******************************************************************************
- * @file     mpu_armv8.h
- * @brief    CMSIS MPU API for Armv8-M and Armv8.1-M MPU
- * @version  V5.1.0
- * @date     08. March 2019
- ******************************************************************************/
-/*
- * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
- /* Copyright (c) 2019 Modified by Dialog Semiconductor */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header    /* treat file as system include file */
-#endif
-
-#ifndef ARM_MPU_ARMV8_H
-#define ARM_MPU_ARMV8_H
-
-/** \brief Attribute for device memory (outer only) */
-#define ARM_MPU_ATTR_DEVICE                           ( 0U )
-
-/** \brief Attribute for non-cacheable, normal memory */
-#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
-
-/** \brief Attribute for normal memory (outer and inner)
-* \param NT Non-Transient: Set to 1 for non-transient data.
-* \param WB Write-Back: Set to 1 to use write-back update policy.
-* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
-* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
-*/
-#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
-  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
-
-/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
-#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
-
-/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
-#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
-
-/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
-#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
-
-/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
-#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
-
-/** \brief Memory Attribute
-* \param O Outer memory attributes
-* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
-*/
-#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
-
-/** \brief Normal memory non-shareable  */
-#define ARM_MPU_SH_NON   (0U)
-
-/** \brief Normal memory outer shareable  */
-#define ARM_MPU_SH_OUTER (2U)
-
-/** \brief Normal memory inner shareable  */
-#define ARM_MPU_SH_INNER (3U)
-
-/** \brief Memory access permissions
-* \param RO Read-Only: Set to 1 for read-only memory.
-* \param NP Non-Privileged: Set to 1 for non-privileged memory.
-*/
-#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
-
-/** \brief Region Base Address Register value
-* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
-* \param SH Defines the Shareability domain for this memory region.
-* \param RO Read-Only: Set to 1 for a read-only memory region.
-* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
-* \param XN eXecute Never: Set to 1 for a non-executable memory region.
-*/
-#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
-  ((BASE & MPU_RBAR_BASE_Msk) | \
-  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
-  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
-  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
-
-/** \brief Region Limit Address Register value
-* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
-* \param IDX The attribute index to be associated with this memory region.
-*/
-#define ARM_MPU_RLAR(LIMIT, IDX) \
-  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
-  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
-  (MPU_RLAR_EN_Msk))
-
-#if defined(MPU_RLAR_PXN_Pos)
-  
-/** \brief Region Limit Address Register with PXN value
-* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
-* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
-* \param IDX The attribute index to be associated with this memory region.
-*/
-#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
-  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
-  ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
-  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
-  (MPU_RLAR_EN_Msk))
-  
-#endif
-
-/**
-* Struct for a single MPU Region
-*/
-typedef struct {
-  uint32_t RBAR;                   /*!< Region Base Address Register value */
-  uint32_t RLAR;                   /*!< Region Limit Address Register value */
-} ARM_MPU_Region_t;
-    
-/** Enable the MPU.
-* \param MPU_Control Default access permissions for unconfigured regions.
-*/
-__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
-{
-  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk
-  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-#endif
-  __DSB();
-  __ISB();
-}
-
-/** Disable the MPU.
-*/
-__STATIC_INLINE void ARM_MPU_Disable(void)
-{
-  __DMB();
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk
-  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-#endif
-  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
-}
-
-#ifdef MPU_NS
-/** Enable the Non-secure MPU.
-* \param MPU_Control Default access permissions for unconfigured regions.
-*/
-__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
-{
-  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk
-  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-#endif
-  __DSB();
-  __ISB();
-}
-
-/** Disable the Non-secure MPU.
-*/
-__STATIC_INLINE void ARM_MPU_Disable_NS(void)
-{
-  __DMB();
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk
-  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-#endif
-  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
-}
-#endif
-
-/** Set the memory attribute encoding to the given MPU.
-* \param mpu Pointer to the MPU to be configured.
-* \param idx The attribute index to be set [0-7]
-* \param attr The attribute value to be set.
-*/
-__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
-{
-  const uint8_t reg = idx / 4U;
-  const uint32_t pos = ((idx % 4U) * 8U);
-  const uint32_t mask = 0xFFU << pos;
-  
-  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
-    return; // invalid index
-  }
-  
-  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
-}
-
-/** Set the memory attribute encoding.
-* \param idx The attribute index to be set [0-7]
-* \param attr The attribute value to be set.
-*/
-__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
-{
-  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
-}
-
-#ifdef MPU_NS
-/** Set the memory attribute encoding to the Non-secure MPU.
-* \param idx The attribute index to be set [0-7]
-* \param attr The attribute value to be set.
-*/
-__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
-{
-  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
-}
-#endif
-
-/** Clear and disable the given MPU region of the given MPU.
-* \param mpu Pointer to MPU to be used.
-* \param rnr Region number to be cleared.
-*/
-__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
-{
-  mpu->RNR = rnr;
-  mpu->RLAR = 0U;
-}
-
-/** Clear and disable the given MPU region.
-* \param rnr Region number to be cleared.
-*/
-__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
-{
-  ARM_MPU_ClrRegionEx(MPU, rnr);
-}
-
-#ifdef MPU_NS
-/** Clear and disable the given Non-secure MPU region.
-* \param rnr Region number to be cleared.
-*/
-__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
-{  
-  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
-}
-#endif
-
-/** Configure the given MPU region of the given MPU.
-* \param mpu Pointer to MPU to be used.
-* \param rnr Region number to be configured.
-* \param rbar Value for RBAR register.
-* \param rlar Value for RLAR register.
-*/   
-__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
-{
-  mpu->RNR = rnr;
-  mpu->RBAR = rbar;
-  mpu->RLAR = rlar;
-}
-
-/** Configure the given MPU region.
-* \param rnr Region number to be configured.
-* \param rbar Value for RBAR register.
-* \param rlar Value for RLAR register.
-*/   
-__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
-{
-  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
-}
-
-#ifdef MPU_NS
-/** Configure the given Non-secure MPU region.
-* \param rnr Region number to be configured.
-* \param rbar Value for RBAR register.
-* \param rlar Value for RLAR register.
-*/   
-__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
-{
-  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
-}
-#endif
-
-/** Memcopy with strictly ordered memory access, e.g. for register targets.
-* \param dst Destination data is copied to.
-* \param src Source data is copied from.
-* \param len Amount of data words to be copied.
-*/
-__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
-{
-  uint32_t i;
-  for (i = 0U; i < len; ++i) 
-  {
-    dst[i] = src[i];
-  }
-}
-
-/** Load the given number of MPU regions from a table to the given MPU.
-* \param mpu Pointer to the MPU registers to be used.
-* \param rnr First region number to be configured.
-* \param table Pointer to the MPU configuration table.
-* \param cnt Amount of regions to be configured.
-*/
-__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
-{
-  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
-  if (cnt == 1U) {
-    mpu->RNR = rnr;
-    ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
-  } else {
-    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
-    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
-    
-    mpu->RNR = rnrBase;
-    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
-      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
-      ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
-      table += c;
-      cnt -= c;
-      rnrOffset = 0U;
-      rnrBase += MPU_TYPE_RALIASES;
-      mpu->RNR = rnrBase;
-    }
-    
-    ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
-  }
-}
-
-/** Load the given number of MPU regions from a table.
-* \param rnr First region number to be configured.
-* \param table Pointer to the MPU configuration table.
-* \param cnt Amount of regions to be configured.
-*/
-__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
-{
-  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
-}
-
-#ifdef MPU_NS
-/** Load the given number of MPU regions from a table to the Non-secure MPU.
-* \param rnr First region number to be configured.
-* \param table Pointer to the MPU configuration table.
-* \param cnt Amount of regions to be configured.
-*/
-__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
-{
-  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
-}
-#endif
-
-#endif
-
diff --git a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/system_ARMCM0.h b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/system_ARMCM0.h
deleted file mode 100755
index 7fe7e914..00000000
--- a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/system_ARMCM0.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/**************************************************************************//**
- * @file     system_ARMCM0.h
- * @brief    CMSIS Device System Header File for
- *           ARMCM0 Device
- * @version  V5.3.1
- * @date     09. July 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef SYSTEM_ARMCM0_H
-#define SYSTEM_ARMCM0_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock) */
-
-
-/**
-  \brief Setup the microcontroller system.
-
-   Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-
-/**
-  \brief  Update SystemCoreClock variable.
-
-   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SYSTEM_ARMCM0_H */
diff --git a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/system_DA1469x.h b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/system_DA1469x.h
deleted file mode 100755
index 6c53ee9a..00000000
--- a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/system_DA1469x.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/**************************************************************************//**
- * @file     system_DA1469x.h
- * @brief    CMSIS Device System Header File for DA1469x Device
- * @version  V5.3.1
- * @date     17. May 2019
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-/* Copyright (c) 2017 Modified by Dialog Semiconductor */
-
-
-#ifndef SYSTEM_DA1469x_H
-#define SYSTEM_DA1469x_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-#include <stdbool.h>
-
-extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock) */
-
-
-/**
-  \brief Setup the microcontroller system.
-
-   Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-
-/**
-  \brief  Update SystemCoreClock variable.
-   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-/**
- * \brief Convert a CPU address to a physical address
- *
- * To calculate the physical address, the current remapping (SYS_CTRL_REG.REMAP_ADR0)
- * is used.
- *
- * \param [in] addr address seen by CPU
- *
- * \return physical address (for DMA, AES/HASH etc.) -- can be same or different as addr
- *
- */
-extern uint32_t black_orca_phy_addr(uint32_t addr);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SYSTEM_DA1469x_H */
diff --git a/tinyusb/hw/mcu/dialog/da1469x/da1469x.ld b/tinyusb/hw/mcu/dialog/da1469x/da1469x.ld
deleted file mode 100755
index c91dea84..00000000
--- a/tinyusb/hw/mcu/dialog/da1469x/da1469x.ld
+++ /dev/null
@@ -1,228 +0,0 @@
-/* Linker script for Dialog DA1469x devices
- *
- * Version: Sourcery G++ 4.5-1
- * Support: https://support.codesourcery.com/GNUToolchain/
- *
- * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.
- *
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions.  No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __HeapBase
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   __bssnz_start__
- *   __bssnz_end__
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
-    .imghdr (NOLOAD):
-    {
-        . = . + _imghdr_size;
-    } > FLASH
-
-    __text = .;
-
-    .text :
-    {
-        __isr_vector_start = .;
-        KEEP(*(.isr_vector))
-        /* ISR vector shall have exactly 512 bytes */
-        . = __isr_vector_start + 0x200;
-        __isr_vector_end = .;
-
-        *(.text)
-        *(.text.*)
-
-        KEEP(*(.init))
-        KEEP(*(.fini))
-
-        /* .ctors */
-        *crtbegin.o(.ctors)
-        *crtbegin?.o(.ctors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-        *(SORT(.ctors.*))
-        *(.ctors)
-
-        /* .dtors */
-        *crtbegin.o(.dtors)
-        *crtbegin?.o(.dtors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
-        *(SORT(.dtors.*))
-        *(.dtors)
-
-        *(.rodata*)
-
-        *(.eh_frame*)
-        . = ALIGN(4);
-    } > FLASH
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-        . = ALIGN(4);
-    } > FLASH
-
-    __exidx_start = .;
-    .ARM.exidx :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        . = ALIGN(4);
-    } > FLASH
-    __exidx_end = .;
-
-    .intvect :
-    {
-        . = ALIGN(4);
-        __intvect_start__ = .;
-        . = . + (__isr_vector_end - __isr_vector_start);
-        . = ALIGN(4);
-    } > RAM
-
-    .sleep_state (NOLOAD) :
-    {
-        . = ALIGN(4);
-        *(sleep_state)
-    } > RAM
-
-    /* This section will be zeroed by RTT package init */
-    .rtt (NOLOAD):
-    {
-        . = ALIGN(4);
-        *(.rtt)
-        . = ALIGN(4);
-    } > RAM
-
-    __text_ram_addr = LOADADDR(.text_ram);
-
-    .text_ram :
-    {
-        . = ALIGN(4);
-        __text_ram_start__ = .;
-        *(.text_ram*)
-        . = ALIGN(4);
-        __text_ram_end__ = .;
-    } > RAM AT > FLASH
-
-    __etext = LOADADDR(.data);
-
-    .data :
-    {
-        __data_start__ = .;
-        *(vtable)
-        *(.data*)
-
-        . = ALIGN(4);
-        /* preinit data */
-        PROVIDE_HIDDEN (__preinit_array_start = .);
-        *(.preinit_array)
-        PROVIDE_HIDDEN (__preinit_array_end = .);
-
-        . = ALIGN(4);
-        /* init data */
-        PROVIDE_HIDDEN (__init_array_start = .);
-        *(SORT(.init_array.*))
-        *(.init_array)
-        PROVIDE_HIDDEN (__init_array_end = .);
-
-
-        . = ALIGN(4);
-        /* finit data */
-        PROVIDE_HIDDEN (__fini_array_start = .);
-        *(SORT(.fini_array.*))
-        *(.fini_array)
-        PROVIDE_HIDDEN (__fini_array_end = .);
-
-        *(.jcr)
-        . = ALIGN(4);
-        /* All data end */
-        __data_end__ = .;
-    } > RAM AT > FLASH
-
-    .bssnz :
-    {
-        . = ALIGN(4);
-        __bssnz_start__ = .;
-        *(.bss.core.nz*)
-        . = ALIGN(4);
-        __bssnz_end__ = .;
-    } > RAM
-
-    .bss :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > RAM
-
-    .cmac (NOLOAD) :
-    {
-        . = ALIGN(0x400);
-        *(.libcmac.ram)
-    } > RAM
-
-    /* Heap starts after BSS */
-    . = ALIGN(8);
-    __HeapBase = .;
-
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (COPY):
-    {
-        *(.stack*)
-    } > RAM
-
-    _ram_start = ORIGIN(RAM);
-
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    PROVIDE(__stack = __StackTop);
-
-    /* Top of head is the bottom of the stack */
-    __HeapLimit = __StackLimit;
-
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__HeapBase <= __HeapLimit, "region RAM overflowed with stack")
-
-    /* Check that intvect is at the beginning of RAM */
-    ASSERT(__intvect_start__ == ORIGIN(RAM), "intvect is not at beginning of RAM")
-}
-
diff --git a/tinyusb/hw/mcu/dialog/da1469x/include/hal/hal_gpio.h b/tinyusb/hw/mcu/dialog/da1469x/include/hal/hal_gpio.h
deleted file mode 100755
index 67fc3c14..00000000
--- a/tinyusb/hw/mcu/dialog/da1469x/include/hal/hal_gpio.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements.  See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership.  The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License.  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied.  See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-
-/**
- * @addtogroup HAL
- * @{
- *   @defgroup HALGpio HAL GPIO
- *   @{
- */
-
-#ifndef H_HAL_GPIO_
-#define H_HAL_GPIO_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * The "mode" of the gpio. The gpio is either an input, output, or it is
- * "not connected" (the pin specified is not functioning as a gpio)
- */
-enum hal_gpio_mode_e {
-    /** Not connected */
-    HAL_GPIO_MODE_NC = -1,
-    /** Input */
-    HAL_GPIO_MODE_IN = 0,
-    /** Output */
-    HAL_GPIO_MODE_OUT = 1
-};
-typedef enum hal_gpio_mode_e hal_gpio_mode_t;
-
-/*
- * The "pull" of the gpio. This is either an input or an output.
- */
-enum hal_gpio_pull {
-    /** Pull-up/down not enabled */
-    HAL_GPIO_PULL_NONE = 0,
-    /** Pull-up enabled */
-    HAL_GPIO_PULL_UP = 1,
-    /** Pull-down enabled */
-    HAL_GPIO_PULL_DOWN = 2
-};
-typedef enum hal_gpio_pull hal_gpio_pull_t;
-
-/*
- * IRQ trigger type.
- */
-enum hal_gpio_irq_trigger {
-    HAL_GPIO_TRIG_NONE = 0,
-    /** IRQ occurs on rising edge */
-    HAL_GPIO_TRIG_RISING = 1,
-    /** IRQ occurs on falling edge */
-    HAL_GPIO_TRIG_FALLING = 2,
-    /** IRQ occurs on either edge */
-    HAL_GPIO_TRIG_BOTH = 3,
-    /** IRQ occurs when line is low */
-    HAL_GPIO_TRIG_LOW = 4,
-    /** IRQ occurs when line is high */
-    HAL_GPIO_TRIG_HIGH = 5
-};
-typedef enum hal_gpio_irq_trigger hal_gpio_irq_trig_t;
-
-/* Function proto for GPIO irq handler functions */
-typedef void (*hal_gpio_irq_handler_t)(void *arg);
-
-/**
- * Initializes the specified pin as an input
- *
- * @param pin   Pin number to set as input
- * @param pull  pull type
- *
- * @return int  0: no error; -1 otherwise.
- */
-int hal_gpio_init_in(int pin, hal_gpio_pull_t pull);
-
-/**
- * Initialize the specified pin as an output, setting the pin to the specified
- * value.
- *
- * @param pin Pin number to set as output
- * @param val Value to set pin
- *
- * @return int  0: no error; -1 otherwise.
- */
-int hal_gpio_init_out(int pin, int val);
-
-/**
- * Deinitialize the specified pin to revert the previous initialization
- *
- * @param pin Pin number to unset
- *
- * @return int  0: no error; -1 otherwise.
- */
-int hal_gpio_deinit(int pin);
-
-/**
- * Write a value (either high or low) to the specified pin.
- *
- * @param pin Pin to set
- * @param val Value to set pin (0:low 1:high)
- */
-void hal_gpio_write(int pin, int val);
-
-/**
- * Reads the specified pin.
- *
- * @param pin Pin number to read
- *
- * @return int 0: low, 1: high
- */
-int hal_gpio_read(int pin);
-
-/**
- * Toggles the specified pin
- *
- * @param pin Pin number to toggle
- *
- * @return current gpio state int 0: low, 1: high
- */
-int hal_gpio_toggle(int pin);
-
-/**
- * Initialize a given pin to trigger a GPIO IRQ callback.
- *
- * @param pin     The pin to trigger GPIO interrupt on
- * @param handler The handler function to call
- * @param arg     The argument to provide to the IRQ handler
- * @param trig    The trigger mode (e.g. rising, falling)
- * @param pull    The mode of the pin (e.g. pullup, pulldown)
- *
- * @return 0 on success, non-zero error code on failure.
- */
-int hal_gpio_irq_init(int pin, hal_gpio_irq_handler_t handler, void *arg,
-                      hal_gpio_irq_trig_t trig, hal_gpio_pull_t pull);
-
-/**
- * Release a pin from being configured to trigger IRQ on state change.
- *
- * @param pin The pin to release
- */
-void hal_gpio_irq_release(int pin);
-
-/**
- * Enable IRQs on the passed pin
- *
- * @param pin The pin to enable IRQs on
- */
-void hal_gpio_irq_enable(int pin);
-
-/**
- * Disable IRQs on the passed pin
- *
- * @param pin The pin to disable IRQs on
- */
-void hal_gpio_irq_disable(int pin);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* H_HAL_GPIO_ */
-
-/**
- *   @} HALGpio
- * @} HAL
- */
diff --git a/tinyusb/hw/mcu/dialog/da1469x/include/mcu/da1469x_clock.h b/tinyusb/hw/mcu/dialog/da1469x/include/mcu/da1469x_clock.h
deleted file mode 100755
index 3c697747..00000000
--- a/tinyusb/hw/mcu/dialog/da1469x/include/mcu/da1469x_clock.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements.  See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership.  The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License.  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied.  See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#ifndef __MCU_DA1469X_CLOCK_H_
-#define __MCU_DA1469X_CLOCK_H_
-
-#include <stdint.h>
-#include "mcu/da1469x_hal.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * Initialize XTAL32M
- */
-void da1469x_clock_sys_xtal32m_init(void);
-
-/**
- * Enable XTAL32M
- */
-void da1469x_clock_sys_xtal32m_enable(void);
-
-/**
- * Wait for XTAL32M to settle
- */
-void da1469x_clock_sys_xtal32m_wait_to_settle(void);
-
-/**
- * Switch sys_clk to XTAL32M
- *
- * Caller shall ensure that XTAL32M is already settled.
- */
-void da1469x_clock_sys_xtal32m_switch(void);
-
-/**
- * Switch sys_clk to XTAL32M
- *
- * Waits for XTAL32M to settle before switching.
- */
-void da1469x_clock_sys_xtal32m_switch_safe(void);
-
-/**
- * Disable RC32M
- */
-void da1469x_clock_sys_rc32m_disable(void);
-
-/**
- * Enable AMBA clock(s)
- *
- * @param mask
- */
-static inline void
-da1469x_clock_amba_enable(uint32_t mask)
-{
-    uint32_t primask;
-
-    __HAL_DISABLE_INTERRUPTS(primask);
-    CRG_TOP->CLK_AMBA_REG |= mask;
-    __HAL_ENABLE_INTERRUPTS(primask);
-}
-
-/**
- * Disable AMBA clock(s)
- *
- * @param uint32_t mask
- */
-static inline void
-da1469x_clock_amba_disable(uint32_t mask)
-{
-    uint32_t primask;
-
-    __HAL_DISABLE_INTERRUPTS(primask);
-    CRG_TOP->CLK_AMBA_REG &= ~mask;
-    __HAL_ENABLE_INTERRUPTS(primask);
-}
-
-/**
- * Enable PLL96
- */
-static inline void
-da1469x_clock_sys_pll_enable(void)
-{
-    CRG_XTAL->PLL_SYS_CTRL1_REG |= CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_EN_Msk |
-                                   CRG_XTAL_PLL_SYS_CTRL1_REG_LDO_PLL_ENABLE_Msk;
-}
-
-/**
- * Disable PLL96
- *
- * If PLL was used as SYS_CLOCK switches to XTAL32M.
- */
-void da1469x_clock_sys_pll_disable(void);
-
-/**
- * Checks whether PLL96 is locked and can be use as system clock or USB clock
- *
- * @return 0 if PLL is off, non-0 it its running
- */
-static inline int
-da1469x_clock_is_pll_locked(void)
-{
-    return 0 != (CRG_XTAL->PLL_SYS_STATUS_REG & CRG_XTAL_PLL_SYS_STATUS_REG_PLL_LOCK_FINE_Msk);
-}
-
-/**
- * Waits for PLL96 to lock.
- */
-void da1469x_clock_pll_wait_to_lock(void);
-
-/**
- * Switches system clock to PLL96
- *
- * Caller shall ensure that PLL is already locked.
- */
-void da1469x_clock_sys_pll_switch(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __MCU_DA1469X_CLOCK_H_ */
diff --git a/tinyusb/hw/mcu/dialog/da1469x/include/mcu/da1469x_hal.h b/tinyusb/hw/mcu/dialog/da1469x/include/mcu/da1469x_hal.h
deleted file mode 100755
index 28fa1aa8..00000000
--- a/tinyusb/hw/mcu/dialog/da1469x/include/mcu/da1469x_hal.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements.  See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership.  The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License.  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied.  See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#ifndef __MCU_DA1469X_HAL_H_
-#define __MCU_DA1469X_HAL_H_
-
-#include <assert.h>
-#include "mcu/mcu.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Helper functions to enable/disable interrupts. */
-#define __HAL_DISABLE_INTERRUPTS(x)                     \
-    do {                                                \
-        x = __get_PRIMASK();                            \
-        __disable_irq();                                \
-    } while (0)
-
-#define __HAL_ENABLE_INTERRUPTS(x)                      \
-    do {                                                \
-        if (!x) {                                       \
-            __enable_irq();                             \
-        }                                               \
-    } while (0)
-
-#define __HAL_ASSERT_CRITICAL()                         \
-    do {                                                \
-        assert(__get_PRIMASK() & 1);                    \
-    } while (0)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* __MCU_DA1469X_HAL_H_ */
diff --git a/tinyusb/hw/mcu/dialog/da1469x/include/mcu/mcu.h b/tinyusb/hw/mcu/dialog/da1469x/include/mcu/mcu.h
deleted file mode 100755
index 1e673678..00000000
--- a/tinyusb/hw/mcu/dialog/da1469x/include/mcu/mcu.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements.  See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership.  The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License.  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied.  See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#ifndef __MCU_MCU_H_
-#define __MCU_MCU_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "DA1469xAB.h"
-
-#define sec_text_ram_core   __attribute__((section(".text_ram"))) __attribute__((noinline))
-
-#define MCU_SYSVIEW_INTERRUPTS \
-    "I#1=Reset,I#2=MNI,I#3=HardFault,I#4=MemoryMgmt,I#5=BusFault,I#6=UsageFault," \
-    "I#7=SecureFault,I#11=SVCall,I#12=DebugMonitor,I#14=PendSV,I#15=SysTick," \
-    "I#16=SENSOR_NODE,I#17=DMA,I#18=CHARGER_STATE,I#19=CHARGER_ERROR," \
-    "I#20=CMAC2SYS,I#21=UART,I#22=UART2,I#23=UART3,I#24=I2C,I#25=I2C2,I#26=SPI," \
-    "I#27=SPI2,I#28=PCM,I#29=SRC_IN,I#30=SRC_OUT,I#31=USB,I#32=TIMER," \
-    "I#33=TIMER2,I#34=RTC,I#35=KEY_WKUP_GPIO,I#36=PDC,I#37=VBUS,I#38=MRM," \
-    "I#39=MOTOR_CONTROLLER,I#40=TRNG,I#41=DCDC,I#42=XTAL32M_RDY,I#43=ADC," \
-    "I#44=ADC2,I#45=CRYPTO,I#46=CAPTIMER1,I#47=RFDIAG,I#48=LCD_CONTROLLER," \
-    "I#49=PLL_LOCK,I#50=TIMER3,I#51=TIMER4,I#52=LRA,I#53=RTC_EVENT," \
-    "I#54=GPIO_P0,I#55=GPIO_P1"
-
-/**
-* \brief GPIO function
-*
-*/
-typedef enum {
-    MCU_GPIO_FUNC_GPIO = 0,                  /**< GPIO */
-    MCU_GPIO_FUNC_UART_RX = 1,               /**< GPIO as UART RX */
-    MCU_GPIO_FUNC_UART_TX = 2,               /**< GPIO as UART TX */
-    MCU_GPIO_FUNC_UART2_RX = 3,              /**< GPIO as UART2 RX */
-    MCU_GPIO_FUNC_UART2_TX = 4,              /**< GPIO as UART2 TX */
-    MCU_GPIO_FUNC_UART2_CTSN = 5,            /**< GPIO as UART2 CTSN */
-    MCU_GPIO_FUNC_UART2_RTSN = 6,            /**< GPIO as UART2 RTSN */
-    MCU_GPIO_FUNC_UART3_RX = 7,              /**< GPIO as UART3 RX */
-    MCU_GPIO_FUNC_UART3_TX = 8,              /**< GPIO as UART3 TX */
-    MCU_GPIO_FUNC_UART3_CTSN = 9,            /**< GPIO as UART3 CTSN */
-    MCU_GPIO_FUNC_UART3_RTSN = 10,           /**< GPIO as UART3 RTSN */
-    MCU_GPIO_FUNC_ISO_CLK = 11,              /**< GPIO as ISO CLK */
-    MCU_GPIO_FUNC_ISO_DATA = 12,             /**< GPIO as ISO DATA */
-    MCU_GPIO_FUNC_SPI_DI = 13,               /**< GPIO as SPI DI */
-    MCU_GPIO_FUNC_SPI_DO = 14,               /**< GPIO as SPI DO */
-    MCU_GPIO_FUNC_SPI_CLK = 15,              /**< GPIO as SPI CLK */
-    MCU_GPIO_FUNC_SPI_EN = 16,               /**< GPIO as SPI EN */
-    MCU_GPIO_FUNC_SPI2_DI = 17,              /**< GPIO as SPI2 DI */
-    MCU_GPIO_FUNC_SPI2_DO = 18,              /**< GPIO as SPI2 DO */
-    MCU_GPIO_FUNC_SPI2_CLK = 19,             /**< GPIO as SPI2 CLK */
-    MCU_GPIO_FUNC_SPI2_EN = 20,              /**< GPIO as SPI2 EN */
-    MCU_GPIO_FUNC_I2C_SCL = 21,              /**< GPIO as I2C SCL */
-    MCU_GPIO_FUNC_I2C_SDA = 22,              /**< GPIO as I2C SDA */
-    MCU_GPIO_FUNC_I2C2_SCL = 23,             /**< GPIO as I2C2 SCL */
-    MCU_GPIO_FUNC_I2C2_SDA = 24,             /**< GPIO as I2C2 SDA */
-    MCU_GPIO_FUNC_USB_SOF = 25,              /**< GPIO as USB SOF */
-    MCU_GPIO_FUNC_ADC = 26,                  /**< GPIO as ADC (dedicated pin) */
-    MCU_GPIO_FUNC_USB = 27,                  /**< GPIO as USB */
-    MCU_GPIO_FUNC_PCM_DI = 28,               /**< GPIO as PCM DI */
-    MCU_GPIO_FUNC_PCM_DO = 29,               /**< GPIO as PCM DO */
-    MCU_GPIO_FUNC_PCM_FSC = 30,              /**< GPIO as PCM FSC */
-    MCU_GPIO_FUNC_PCM_CLK = 31,              /**< GPIO as PCM CLK */
-    MCU_GPIO_FUNC_PDM_DATA = 32,             /**< GPIO as PDM DATA */
-    MCU_GPIO_FUNC_PDM_CLK = 33,              /**< GPIO as PDM CLK */
-    MCU_GPIO_FUNC_COEX_EXT_ACT = 34,         /**< GPIO as COEX EXT ACT0 */
-    MCU_GPIO_FUNC_COEX_SMART_ACT = 35,       /**< GPIO as COEX SMART ACT */
-    MCU_GPIO_FUNC_COEX_SMART_PRI = 36,       /**< GPIO as COEX SMART PRI */
-    MCU_GPIO_FUNC_PORT0_DCF = 37,            /**< GPIO as PORT0 DCF */
-    MCU_GPIO_FUNC_PORT1_DCF = 38,            /**< GPIO as PORT1 DCF */
-    MCU_GPIO_FUNC_PORT2_DCF = 39,            /**< GPIO as PORT2 DCF */
-    MCU_GPIO_FUNC_PORT3_DCF = 40,            /**< GPIO as PORT3 DCF */
-    MCU_GPIO_FUNC_PORT4_DCF = 41,            /**< GPIO as PORT4 DCF */
-    MCU_GPIO_FUNC_CLOCK = 42,                /**< GPIO as CLOCK */
-    MCU_GPIO_FUNC_PG = 43,                   /**< GPIO as PG */
-    MCU_GPIO_FUNC_LCD = 44,                  /**< GPIO as LCD */
-    MCU_GPIO_FUNC_LCD_SPI_DC = 45,           /**< GPIO as LCD SPI DC */
-    MCU_GPIO_FUNC_LCD_SPI_DO = 46,           /**< GPIO as LCD SPI DO */
-    MCU_GPIO_FUNC_LCD_SPI_CLK = 47,          /**< GPIO as LCD SPI CLK */
-    MCU_GPIO_FUNC_LCD_SPI_EN = 48,           /**< GPIO as LCD SPI EN */
-    MCU_GPIO_FUNC_TIM_PWM = 49,              /**< GPIO as TIM PWM */
-    MCU_GPIO_FUNC_TIM2_PWM = 50,             /**< GPIO as TIM2 PWM */
-    MCU_GPIO_FUNC_TIM_1SHOT = 51,            /**< GPIO as TIM 1SHOT */
-    MCU_GPIO_FUNC_TIM2_1SHOT = 52,           /**< GPIO as TIM2 1SHOT */
-    MCU_GPIO_FUNC_TIM3_PWM = 53,             /**< GPIO as TIM3 PWM */
-    MCU_GPIO_FUNC_TIM4_PWM = 54,             /**< GPIO as TIM4 PWM */
-    MCU_GPIO_FUNC_AGC_EXT = 55,              /**< GPIO as AGC EXT */
-    MCU_GPIO_FUNC_CMAC_DIAG0 = 56,           /**< GPIO as CMAC DIAG0 */
-    MCU_GPIO_FUNC_CMAC_DIAG1 = 57,           /**< GPIO as CMAC DIAG1 */
-    MCU_GPIO_FUNC_CMAC_DIAG2 = 58,           /**< GPIO as CMAC DIAG2 */
-    MCU_GPIO_FUNC_CMAC_DIAGX = 59,           /**< GPIO as CMAC DIAGX */
-    MCU_GPIO_FUNC_LAST,
-} mcu_gpio_func;
-
-#define MCU_GPIO_MODE_INPUT                 0x000    /**< GPIO as an input */
-#define MCU_GPIO_MODE_INPUT_PULLUP          0x100    /**< GPIO as an input with pull-up */
-#define MCU_GPIO_MODE_INPUT_PULLDOWN        0x200    /**< GPIO as an input with pull-down */
-#define MCU_GPIO_MODE_OUTPUT                0x300    /**< GPIO as an output */
-#define MCU_GPIO_MODE_OUTPUT_OPEN_DRAIN     0x700    /**< GPIO as an open-drain output */
-
-#define MCU_GPIO_PORT0_PIN_COUNT            32
-#define MCU_GPIO_PORT0(pin)		((0 * 32) + (pin))
-#define MCU_GPIO_PORT1(pin)		((1 * 32) + (pin))
-#define MCU_DMA_CHAN_MAX                    8
-
-#define MCU_PIN_GPADC_SEL0               MCU_GPIO_PORT1(9)
-#define MCU_PIN_GPADC_SEL1               MCU_GPIO_PORT0(25)
-#define MCU_PIN_GPADC_SEL2               MCU_GPIO_PORT0(8)
-#define MCU_PIN_GPADC_SEL3               MCU_GPIO_PORT0(9)
-#define MCU_PIN_GPADC_SEL16              MCU_GPIO_PORT1(13)
-#define MCU_PIN_GPADC_SEL17              MCU_GPIO_PORT1(12)
-#define MCU_PIN_GPADC_SEL18              MCU_GPIO_PORT1(18)
-#define MCU_PIN_GPADC_SEL19              MCU_GPIO_PORT1(19)
-#define MCU_PIN_GPADC_DIFF0_P0           MCU_GPIO_PORT1(9)
-#define MCU_PIN_GPADC_DIFF0_P1           MCU_GPIO_PORT0(25)
-#define MCU_PIN_GPADC_DIFF1_P0           MCU_GPIO_PORT0(8)
-#define MCU_PIN_GPADC_DIFF1_P1           MCU_GPIO_PORT0(9)
-
-#define MCU_PIN_SDADC0               MCU_GPIO_PORT1(9)
-#define MCU_PIN_SDADC1               MCU_GPIO_PORT0(25)
-#define MCU_PIN_SDADC2               MCU_GPIO_PORT0(8)
-#define MCU_PIN_SDADC3               MCU_GPIO_PORT0(9)
-#define MCU_PIN_SDADC4               MCU_GPIO_PORT1(14)
-#define MCU_PIN_SDADC5               MCU_GPIO_PORT1(20)
-#define MCU_PIN_SDADC6               MCU_GPIO_PORT1(21)
-#define MCU_PIN_SDADC7               MCU_GPIO_PORT1(22)
-
-void mcu_gpio_set_pin_function(int pin, int mode, mcu_gpio_func func);
-void mcu_gpio_enter_sleep(void);
-void mcu_gpio_exit_sleep(void);
-
-#define MCU_MEM_QSPIF_M_END_REMAP_ADDRESS (0x800000)
-#define MCU_MEM_QSPIF_M_START_ADDRESS   (0x16000000)
-#define MCU_MEM_QSPIF_M_END_ADDRESS     (0x18000000)
-#define MCU_MEM_SYSRAM_START_ADDRESS    (0x20000000)
-#define MCU_MEM_SYSRAM_END_ADDRESS      (0x20080000)
-
-#define MCU_OTPM_BASE 0x30080000UL
-#define MCU_OTPM_SIZE 4096
-
-/* Largest group id seen on a DA14699 was 18 so far */
-#define MCU_TRIMV_GROUP_ID_MAX          (18)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __MCU_MCU_H_ */
-
diff --git a/tinyusb/hw/mcu/dialog/da1469x/src/da1469x_clock.c b/tinyusb/hw/mcu/dialog/da1469x/src/da1469x_clock.c
deleted file mode 100755
index 6b4f0e6c..00000000
--- a/tinyusb/hw/mcu/dialog/da1469x/src/da1469x_clock.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements.  See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership.  The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License.  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied.  See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#include <assert.h>
-#include <stdbool.h>
-#include <stdint.h>
-#include "syscfg/syscfg.h"
-#include "mcu/da1469x_hal.h"
-#include "mcu/da1469x_clock.h"
-
-static inline bool
-da1469x_clock_is_xtal32m_settled(void)
-{
-    return ((*(uint32_t *)0x5001001c & 0xff00) == 0) &&
-           ((*(uint32_t *)0x50010054 & 0x000f) != 0xb);
-}
-
-void
-da1469x_clock_sys_xtal32m_init(void)
-{
-    uint32_t reg;
-    int xtalrdy_cnt;
-
-    /* Number of lp_clk cycles (~30.5us) */
-    xtalrdy_cnt = MYNEWT_VAL(MCU_CLOCK_XTAL32M_SETTLE_TIME_US) * 10 / 305;
-
-    reg = CRG_XTAL->XTALRDY_CTRL_REG;
-    reg &= ~(CRG_XTAL_XTALRDY_CTRL_REG_XTALRDY_CLK_SEL_Msk |
-             CRG_XTAL_XTALRDY_CTRL_REG_XTALRDY_CNT_Msk);
-    reg |= xtalrdy_cnt;
-    CRG_XTAL->XTALRDY_CTRL_REG = reg;
-}
-
-void
-da1469x_clock_sys_xtal32m_enable(void)
-{
-  PDC->PDC_CTRL0_REG = (2 << PDC_PDC_CTRL0_REG_TRIG_SELECT_Pos) |
-                       (15 << PDC_PDC_CTRL0_REG_TRIG_ID_Pos) |
-                       (1 << PDC_PDC_CTRL0_REG_PDC_MASTER_Pos) |
-                       (1 << PDC_PDC_CTRL0_REG_EN_XTAL_Pos);
-
-  PDC->PDC_SET_PENDING_REG = 0;
-  PDC->PDC_ACKNOWLEDGE_REG = 0;
-}
-
-void
-da1469x_clock_sys_xtal32m_switch(void)
-{
-    if (CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC32M_Msk) {
-        CRG_TOP->CLK_SWITCH2XTAL_REG = CRG_TOP_CLK_SWITCH2XTAL_REG_SWITCH2XTAL_Msk;
-    } else {
-        CRG_TOP->CLK_CTRL_REG &= ~CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk;
-    }
-
-    while (!(CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL32M_Msk));
-}
-
-void
-da1469x_clock_sys_xtal32m_wait_to_settle(void)
-{
-    uint32_t primask;
-
-    __HAL_DISABLE_INTERRUPTS(primask);
-
-    NVIC_ClearPendingIRQ(XTAL32M_RDY_IRQn);
-
-    if (!da1469x_clock_is_xtal32m_settled()) {
-        NVIC_EnableIRQ(XTAL32M_RDY_IRQn);
-        while (!NVIC_GetPendingIRQ(XTAL32M_RDY_IRQn)) {
-            __WFI();
-        }
-        NVIC_DisableIRQ(XTAL32M_RDY_IRQn);
-    }
-
-    __HAL_ENABLE_INTERRUPTS(primask);
-}
-
-void
-da1469x_clock_sys_xtal32m_switch_safe(void)
-{
-    da1469x_clock_sys_xtal32m_wait_to_settle();
-
-    da1469x_clock_sys_xtal32m_switch();
-}
-
-void
-da1469x_clock_sys_rc32m_disable(void)
-{
-    CRG_TOP->CLK_RC32M_REG &= ~CRG_TOP_CLK_RC32M_REG_RC32M_ENABLE_Msk;
-}
-
-void
-da1469x_clock_lp_xtal32k_enable(void)
-{
-    CRG_TOP->CLK_XTAL32K_REG |= CRG_TOP_CLK_XTAL32K_REG_XTAL32K_ENABLE_Msk;
-}
-
-void
-da1469x_clock_lp_xtal32k_switch(void)
-{
-    CRG_TOP->CLK_CTRL_REG = (CRG_TOP->CLK_CTRL_REG &
-                             ~CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk) |
-                            (2 << CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos);
-}
-
-void
-da1469x_clock_pll_disable(void)
-{
-    while (CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Msk) {
-        CRG_TOP->CLK_SWITCH2XTAL_REG = CRG_TOP_CLK_SWITCH2XTAL_REG_SWITCH2XTAL_Msk;
-    }
-
-    CRG_XTAL->PLL_SYS_CTRL1_REG &= ~CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_EN_Msk;
-}
-
-void
-da1469x_clock_pll_wait_to_lock(void)
-{
-    uint32_t primask;
-
-    __HAL_DISABLE_INTERRUPTS(primask);
-
-    NVIC_ClearPendingIRQ(PLL_LOCK_IRQn);
-
-    if (!da1469x_clock_is_pll_locked()) {
-        NVIC_EnableIRQ(PLL_LOCK_IRQn);
-        while (!NVIC_GetPendingIRQ(PLL_LOCK_IRQn)) {
-            __WFI();
-        }
-        NVIC_DisableIRQ(PLL_LOCK_IRQn);
-    }
-
-    __HAL_ENABLE_INTERRUPTS(primask);
-}
-
-void
-da1469x_clock_sys_pll_switch(void)
-{
-    /* CLK_SEL_Msk == 3 means PLL */
-    CRG_TOP->CLK_CTRL_REG |= CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk;
-
-    while (!(CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Msk));
-}
diff --git a/tinyusb/hw/mcu/dialog/da1469x/src/hal_gpio.c b/tinyusb/hw/mcu/dialog/da1469x/src/hal_gpio.c
deleted file mode 100755
index e105cf2b..00000000
--- a/tinyusb/hw/mcu/dialog/da1469x/src/hal_gpio.c
+++ /dev/null
@@ -1,478 +0,0 @@
-
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements.  See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership.  The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License.  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied.  See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#include <assert.h>
-#include <stddef.h>
-#include "syscfg/syscfg.h"
-#include "mcu/da1469x_hal.h"
-#include <mcu/mcu.h>
-#include "hal/hal_gpio.h"
-
-/* GPIO interrupts */
-#define HAL_GPIO_MAX_IRQ        MYNEWT_VAL(MCU_GPIO_MAX_IRQ)
-
-#define GPIO_REG(name) ((__IO uint32_t *)(GPIO_BASE + offsetof(GPIO_Type, name)))
-#define WAKEUP_REG(name) ((__IO uint32_t *)(WAKEUP_BASE + offsetof(WAKEUP_Type, name)))
-#define CRG_TOP_REG(name) ((__IO uint32_t *)(CRG_TOP_BASE + offsetof(CRG_TOP_Type, name)))
-
-#ifndef MCU_GPIO_PORT0_PIN_COUNT
-#define MCU_GPIO_PORT0_PIN_COUNT 32
-#endif
-
-#if (MCU_GPIO_PORT0_PIN_COUNT) == 32
-#define GPIO_PORT(pin)          (((unsigned)(pin)) >> 5U)
-#define GPIO_PORT_PIN(pin)      (((unsigned)(pin)) & 31U)
-#else
-#define GPIO_PORT(pin)          (((unsigned)(pin)) < MCU_GPIO_PORT0_PIN_COUNT ? 0 : 1)
-#define GPIO_PORT_PIN(pin)      ((unsigned)(pin) < MCU_GPIO_PORT0_PIN_COUNT ? \
-                                (pin) : (pin) - MCU_GPIO_PORT0_PIN_COUNT)
-#endif
-
-#define GPIO_PIN_BIT(pin)       (1 << GPIO_PORT_PIN(pin))
-
-#define GPIO_PIN_DATA_REG_ADDR(pin)        (GPIO_REG(P0_DATA_REG) + GPIO_PORT(pin))
-#define GPIO_PIN_DATA_REG(pin)             *GPIO_PIN_DATA_REG_ADDR(pin)
-#define GPIO_PIN_SET_DATA_REG_ADDR(pin)    (GPIO_REG(P0_SET_DATA_REG) + GPIO_PORT(pin))
-#define GPIO_PIN_SET_DATA_REG(pin)         *GPIO_PIN_SET_DATA_REG_ADDR(pin)
-#define GPIO_PIN_RESET_DATA_REG_ADDR(pin)  (GPIO_REG(P0_RESET_DATA_REG) + GPIO_PORT(pin))
-#define GPIO_PIN_RESET_DATA_REG(pin)       *GPIO_PIN_RESET_DATA_REG_ADDR(pin)
-#define GPIO_PIN_MODE_REG_ADDR(pin)        (GPIO_REG(P0_00_MODE_REG) + (pin))
-#define GPIO_PIN_MODE_REG(pin)             *GPIO_PIN_MODE_REG_ADDR(pin)
-#define GPIO_PIN_PADPWR_CTRL_REG_ADDR(pin) (GPIO_REG(P0_PADPWR_CTRL_REG) + GPIO_PORT(pin))
-#define GPIO_PIN_PADPWR_CTRL_REG(pin)      *GPIO_PIN_PADPWR_CTRL_REG_ADDR(pin)
-#define GPIO_PIN_UNLATCH_ADDR(pin)         (CRG_TOP_REG(P0_SET_PAD_LATCH_REG) + GPIO_PORT(pin) * 3)
-#define GPIO_PIN_LATCH_ADDR(pin)           (CRG_TOP_REG(P0_RESET_PAD_LATCH_REG) + GPIO_PORT(pin) * 3)
-
-#define WKUP_CTRL_REG_ADDR              (WAKEUP_REG(WKUP_CTRL_REG))
-#define WKUP_RESET_IRQ_REG_ADDR         (WAKEUP_REG(WKUP_RESET_IRQ_REG))
-#define WKUP_SELECT_PX_REG_ADDR(pin)    (WAKEUP_REG(WKUP_SELECT_P0_REG) + GPIO_PORT(pin))
-#define WKUP_SELECT_PX_REG(pin)         *(WKUP_SELECT_PX_REG_ADDR(pin))
-#define WKUP_POL_PX_REG_ADDR(pin)       (WAKEUP_REG(WKUP_POL_P0_REG) + GPIO_PORT(pin))
-#define WKUP_POL_PX_SET_FALLING(pin)    do { *(WKUP_POL_PX_REG_ADDR(pin)) |= GPIO_PIN_BIT(pin); } while (0)
-#define WKUP_POL_PX_SET_RISING(pin)     do { *(WKUP_POL_PX_REG_ADDR(pin)) &= ~GPIO_PIN_BIT(pin); } while (0)
-#define WKUP_STAT_PX_REG_ADDR(pin)      (WAKEUP_REG(WKUP_STATUS_P0_REG) + GPIO_PORT(pin))
-#define WKUP_STAT(pin)                  ((*(WKUP_STAT_PX_REG_ADDR(pin)) >> GPIO_PORT_PIN(pin)) & 1)
-#define WKUP_CLEAR_PX_REG_ADDR(pin)     (WAKEUP_REG(WKUP_CLEAR_P0_REG) + GPIO_PORT(pin))
-#define WKUP_CLEAR_PX(pin)              do { (*(WKUP_CLEAR_PX_REG_ADDR(pin)) = GPIO_PIN_BIT(pin)); } while (0)
-#define WKUP_SEL_GPIO_PX_REG_ADDR(pin)  (WAKEUP_REG(WKUP_SEL_GPIO_P0_REG) + GPIO_PORT(pin))
-#define WKUP_SEL_GPIO_PX_REG(pin)       *(WKUP_SEL_GPIO_PX_REG_ADDR(pin))
-
-/* Storage for GPIO callbacks. */
-struct hal_gpio_irq {
-    int pin;
-    hal_gpio_irq_handler_t func;
-    void *arg;
-};
-
-static struct hal_gpio_irq hal_gpio_irqs[HAL_GPIO_MAX_IRQ];
-
-#if MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM) >= 0
-static uint32_t g_mcu_gpio_latch_state[2];
-static uint8_t g_mcu_gpio_retained_num;
-static struct da1469x_retreg g_mcu_gpio_retained[MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM)];
-#endif
-
-/*
- * We assume that any latched pin has default configuration, i.e. was either
- * not configured or was deinited. Any unlatched pin is considered to be used
- * by someone.
- *
- * By default, all pins are assumed to have default configuration and are
- * latched. This allows PD_COM to be disabled (if no other peripheral needs
- * it) since we do not need GPIO mux to be active.
- *
- * Configuration of any pin shall be done as follows, with interrupts disabled:
- * 1. call mcu_gpio_unlatch_prepare() to enable PD_COM if needed
- * 2. configure pin
- * 3. call mcu_gpio_unlatch() to actually unlatch pin
- *
- * Once pin is restored to default configuration it shall be latched again by
- * calling mcu_gpio_latch().
- */
-
-#if MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM) >= 0
-static void
-mcu_gpio_retained_add_port(uint32_t latch_val, volatile uint32_t *base_reg)
-{
-    struct da1469x_retreg *retreg;
-    int pin;
-
-    retreg = &g_mcu_gpio_retained[g_mcu_gpio_retained_num];
-
-    while (latch_val) {
-        assert(g_mcu_gpio_retained_num < MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM));
-
-        pin = __builtin_ctz(latch_val);
-        latch_val &= ~(1 << pin);
-
-        da1469x_retreg_assign(retreg, &base_reg[pin]);
-
-        g_mcu_gpio_retained_num++;
-        retreg++;
-    }
-}
-#endif
-
-static void
-mcu_gpio_retained_refresh(void)
-{
-#if MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM) >= 0
-    g_mcu_gpio_retained_num = 0;
-
-    mcu_gpio_retained_add_port(CRG_TOP->P0_PAD_LATCH_REG, &GPIO->P0_00_MODE_REG);
-    mcu_gpio_retained_add_port(CRG_TOP->P1_PAD_LATCH_REG, &GPIO->P1_00_MODE_REG);
-#endif
-}
-
-static inline void
-mcu_gpio_unlatch_prepare(int pin)
-{
-    __HAL_ASSERT_CRITICAL();
-    (void)pin;
-
-    /* Acquire PD_COM if first pin will be unlatched */
-//    if ((CRG_TOP->P0_PAD_LATCH_REG | CRG_TOP->P1_PAD_LATCH_REG) == 0) {
-//        da1469x_pd_acquire(MCU_PD_DOMAIN_COM);
-//    }
-}
-
-static inline void
-mcu_gpio_unlatch(int pin)
-{
-    __HAL_ASSERT_CRITICAL();
-
-    *GPIO_PIN_UNLATCH_ADDR(pin) = GPIO_PIN_BIT(pin);
-    mcu_gpio_retained_refresh();
-}
-
-static inline void
-mcu_gpio_latch(int pin)
-{
-    (void)pin;
-//    uint32_t primask;
-//    uint32_t latch_pre;
-//    uint32_t latch_post;
-//
-//    __HAL_DISABLE_INTERRUPTS(primask);
-//
-//    latch_pre = CRG_TOP->P0_PAD_LATCH_REG | CRG_TOP->P1_PAD_LATCH_REG;
-//
-//    *GPIO_PIN_LATCH_ADDR(pin) = GPIO_PIN_BIT(pin);
-//    mcu_gpio_retained_refresh();
-//
-//    latch_post = CRG_TOP->P0_PAD_LATCH_REG | CRG_TOP->P1_PAD_LATCH_REG;
-//
-//    /* Release PD_COM if last pin was latched */
-//    if (latch_pre && !latch_post) {
-//        da1469x_pd_release(MCU_PD_DOMAIN_COM);
-//    }
-//
-//    __HAL_ENABLE_INTERRUPTS(primask);
-}
-
-int
-hal_gpio_init_in(int pin, hal_gpio_pull_t pull)
-{
-    volatile uint32_t *px_xx_mod_reg = GPIO_PIN_MODE_REG_ADDR(pin);
-    uint32_t regval;
-    uint32_t primask;
-
-    switch (pull) {
-    case HAL_GPIO_PULL_UP:
-        regval = MCU_GPIO_FUNC_GPIO | MCU_GPIO_MODE_INPUT_PULLUP;
-        break;
-    case HAL_GPIO_PULL_DOWN:
-        regval = MCU_GPIO_FUNC_GPIO | MCU_GPIO_MODE_INPUT_PULLDOWN;
-        break;
-    case HAL_GPIO_PULL_NONE:
-        regval = MCU_GPIO_FUNC_GPIO | MCU_GPIO_MODE_INPUT;
-        break;
-    default:
-        return -1;
-    }
-
-    __HAL_DISABLE_INTERRUPTS(primask);
-
-    mcu_gpio_unlatch_prepare(pin);
-
-    *px_xx_mod_reg = regval;
-
-    mcu_gpio_unlatch(pin);
-
-    __HAL_ENABLE_INTERRUPTS(primask);
-
-    return 0;
-}
-
-int
-hal_gpio_init_out(int pin, int val)
-{
-    uint32_t primask;
-
-    __HAL_DISABLE_INTERRUPTS(primask);
-
-    mcu_gpio_unlatch_prepare(pin);
-
-    GPIO_PIN_MODE_REG(pin) = MCU_GPIO_MODE_OUTPUT;
-
-    if (val) {
-        GPIO_PIN_SET_DATA_REG(pin) = GPIO_PIN_BIT(pin);
-    } else {
-        GPIO_PIN_RESET_DATA_REG(pin) = GPIO_PIN_BIT(pin);
-    }
-
-    mcu_gpio_unlatch(pin);
-
-    __HAL_ENABLE_INTERRUPTS(primask);
-
-    return 0;
-}
-
-int
-hal_gpio_deinit(int pin)
-{
-    /* Reset mode to default value and latch pin */
-    GPIO_PIN_MODE_REG(pin) = 0x200;
-    GPIO_PIN_RESET_DATA_REG(pin) = GPIO_PIN_BIT(pin);
-
-    mcu_gpio_latch(pin);
-
-    return 0;
-}
-
-void
-hal_gpio_write(int pin, int val)
-{
-    if (val) {
-        GPIO_PIN_SET_DATA_REG(pin) = GPIO_PIN_BIT(pin);
-    } else {
-        GPIO_PIN_RESET_DATA_REG(pin) = GPIO_PIN_BIT(pin);
-    }
-}
-
-int
-hal_gpio_read(int pin)
-{
-    return (GPIO_PIN_DATA_REG(pin) >> GPIO_PORT_PIN(pin)) & 1;
-}
-
-int
-hal_gpio_toggle(int pin)
-{
-    int new_value = hal_gpio_read(pin) == 0;
-
-    hal_gpio_write(pin, new_value);
-
-    return new_value;
-}
-
-static void
-hal_gpio_irq_handler(void)
-{
-    struct hal_gpio_irq *irq;
-    uint32_t stat;
-    int i;
-
-    *WKUP_RESET_IRQ_REG_ADDR = 1;
-    NVIC_ClearPendingIRQ(KEY_WKUP_GPIO_IRQn);
-
-    for (i = 0; i < HAL_GPIO_MAX_IRQ; i++) {
-        irq = &hal_gpio_irqs[i];
-
-        /* Read latched status value from relevant GPIO port */
-        stat = WKUP_STAT(irq->pin);
-
-        if (irq->func && stat) {
-            irq->func(irq->arg);
-        }
-
-        WKUP_CLEAR_PX(irq->pin);
-    }
-}
-
-static void
-hal_gpio_irq_setup(void)
-{
-    static uint8_t irq_setup;
-    int sr;
-
-    if (!irq_setup) {
-        __HAL_DISABLE_INTERRUPTS(sr);
-
-        irq_setup = 1;
-
-        NVIC_ClearPendingIRQ(GPIO_P0_IRQn);
-        NVIC_ClearPendingIRQ(GPIO_P1_IRQn);
-        NVIC_SetVector(GPIO_P0_IRQn, (uint32_t)hal_gpio_irq_handler);
-        NVIC_SetVector(GPIO_P1_IRQn, (uint32_t)hal_gpio_irq_handler);
-        WAKEUP->WKUP_CTRL_REG = 0;
-        WAKEUP->WKUP_CLEAR_P0_REG = 0xFFFFFFFF;
-        WAKEUP->WKUP_CLEAR_P1_REG = 0x007FFFFF;
-        WAKEUP->WKUP_SELECT_P0_REG = 0;
-        WAKEUP->WKUP_SELECT_P1_REG = 0;
-        WAKEUP->WKUP_SEL_GPIO_P0_REG = 0;
-        WAKEUP->WKUP_SEL_GPIO_P1_REG = 0;
-        WAKEUP->WKUP_RESET_IRQ_REG = 0;
-
-        CRG_TOP->CLK_TMR_REG |= CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Msk;
-
-        __HAL_ENABLE_INTERRUPTS(sr);
-        NVIC_EnableIRQ(GPIO_P0_IRQn);
-        NVIC_EnableIRQ(GPIO_P1_IRQn);
-    }
-}
-
-static int
-hal_gpio_find_empty_slot(void)
-{
-    int i;
-
-    for (i = 0; i < HAL_GPIO_MAX_IRQ; i++) {
-        if (hal_gpio_irqs[i].func == NULL) {
-            return i;
-        }
-    }
-
-    return -1;
-}
-
-int
-hal_gpio_irq_init(int pin, hal_gpio_irq_handler_t handler, void *arg,
-                  hal_gpio_irq_trig_t trig, hal_gpio_pull_t pull)
-{
-    int i;
-
-    hal_gpio_irq_setup();
-
-    i = hal_gpio_find_empty_slot();
-    /* If assert failed increase syscfg value MCU_GPIO_MAX_IRQ */
-    assert(i >= 0);
-    if (i < 0) {
-        return -1;
-    }
-
-    hal_gpio_init_in(pin, pull);
-
-    switch (trig) {
-    case HAL_GPIO_TRIG_RISING:
-        WKUP_POL_PX_SET_RISING(pin);
-        break;
-    case HAL_GPIO_TRIG_FALLING:
-        WKUP_POL_PX_SET_FALLING(pin);
-        break;
-    case HAL_GPIO_TRIG_BOTH:
-        /* Not supported */
-    default:
-        return -1;
-    }
-
-    hal_gpio_irqs[i].pin = pin;
-    hal_gpio_irqs[i].func = handler;
-    hal_gpio_irqs[i].arg = arg;
-
-    return 0;
-}
-
-void
-hal_gpio_irq_release(int pin)
-{
-    int i;
-
-    hal_gpio_irq_disable(pin);
-
-    for (i = 0; i < HAL_GPIO_MAX_IRQ; i++) {
-        if (hal_gpio_irqs[i].pin == pin && hal_gpio_irqs[i].func) {
-            hal_gpio_irqs[i].pin = -1;
-            hal_gpio_irqs[i].arg = NULL;
-            hal_gpio_irqs[i].func = NULL;
-        }
-    }
-}
-
-void
-hal_gpio_irq_enable(int pin)
-{
-    WKUP_SEL_GPIO_PX_REG(pin) |= GPIO_PIN_BIT(pin);
-}
-
-void
-hal_gpio_irq_disable(int pin)
-{
-    WKUP_SEL_GPIO_PX_REG(pin) &= ~GPIO_PIN_BIT(pin);
-    WKUP_CLEAR_PX(pin);
-}
-
-void
-mcu_gpio_set_pin_function(int pin, int mode, mcu_gpio_func func)
-{
-    uint32_t primask;
-
-    __HAL_DISABLE_INTERRUPTS(primask);
-
-    mcu_gpio_unlatch_prepare(pin);
-
-    GPIO_PIN_MODE_REG(pin) = (func & GPIO_P0_00_MODE_REG_PID_Msk) |
-        (mode & (GPIO_P0_00_MODE_REG_PUPD_Msk | GPIO_P0_00_MODE_REG_PPOD_Msk));
-
-    mcu_gpio_unlatch(pin);
-
-    __HAL_ENABLE_INTERRUPTS(primask);
-}
-
-void
-mcu_gpio_enter_sleep(void)
-{
-#if MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM) >= 0
-    if (g_mcu_gpio_retained_num == 0) {
-        return;
-    }
-
-    g_mcu_gpio_latch_state[0] = CRG_TOP->P0_PAD_LATCH_REG;
-    g_mcu_gpio_latch_state[1] = CRG_TOP->P1_PAD_LATCH_REG;
-
-    da1469x_retreg_update(g_mcu_gpio_retained, g_mcu_gpio_retained_num);
-
-    CRG_TOP->P0_RESET_PAD_LATCH_REG = CRG_TOP_P0_PAD_LATCH_REG_P0_LATCH_EN_Msk;
-    CRG_TOP->P1_RESET_PAD_LATCH_REG = CRG_TOP_P1_PAD_LATCH_REG_P1_LATCH_EN_Msk;
-
-    da1469x_pd_release(MCU_PD_DOMAIN_COM);
-#endif
-}
-
-void
-mcu_gpio_exit_sleep(void)
-{
-#if MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM) >= 0
-    if (g_mcu_gpio_retained_num == 0) {
-        return;
-    }
-
-    da1469x_pd_acquire(MCU_PD_DOMAIN_COM);
-
-    da1469x_retreg_restore(g_mcu_gpio_retained, g_mcu_gpio_retained_num);
-
-    /* Set pins states to their latched values */
-    GPIO->P0_DATA_REG = GPIO->P0_DATA_REG;
-    GPIO->P1_DATA_REG = GPIO->P1_DATA_REG;
-
-    CRG_TOP->P0_PAD_LATCH_REG = g_mcu_gpio_latch_state[0];
-    CRG_TOP->P1_PAD_LATCH_REG = g_mcu_gpio_latch_state[1];
-#endif
-}
diff --git a/tinyusb/hw/mcu/dialog/da1469x/src/hal_system.c b/tinyusb/hw/mcu/dialog/da1469x/src/hal_system.c
deleted file mode 100755
index 2841979f..00000000
--- a/tinyusb/hw/mcu/dialog/da1469x/src/hal_system.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements.  See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership.  The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License.  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied.  See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#include <assert.h>
-#include "syscfg/syscfg.h"
-#include "mcu/da1469x_clock.h"
-#include "mcu/da1469x_lpclk.h"
-#include "mcu/da1469x_pd.h"
-#include "mcu/da1469x_pdc.h"
-#include "mcu/da1469x_prail.h"
-#include "hal/hal_system.h"
-#include "os/os_cputime.h"
-
-#if !MYNEWT_VAL(BOOT_LOADER)
-static enum hal_reset_reason g_hal_reset_reason;
-#endif
-
-void
-hal_system_init(void)
-{
-#if MYNEWT_VAL(MCU_DCDC_ENABLE)
-    da1469x_prail_dcdc_enable();
-#endif
-
-    /*
-     * RESET_STAT_REG has to be cleared to allow HW set bits during next reset
-     * so we should read it now and keep result for application to check at any
-     * time. This does not happen for bootloader since reading reset reason in
-     * bootloader would prevent application from reading it.
-     */
-
-#if !MYNEWT_VAL(BOOT_LOADER)
-    uint32_t reg;
-
-    reg = CRG_TOP->RESET_STAT_REG;
-    CRG_TOP->RESET_STAT_REG = 0;
-
-    if (reg & CRG_TOP_RESET_STAT_REG_PORESET_STAT_Msk) {
-        g_hal_reset_reason = HAL_RESET_POR;
-    } else if (reg & CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Msk) {
-        g_hal_reset_reason = HAL_RESET_WATCHDOG;
-    } else if (reg & CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Msk) {
-        g_hal_reset_reason = HAL_RESET_SOFT;
-    } else if (reg & CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Msk) {
-        g_hal_reset_reason = HAL_RESET_PIN;
-    } else {
-        g_hal_reset_reason = 0;
-    }
-#endif
-}
-
-void
-hal_system_reset(void)
-{
-
-#if MYNEWT_VAL(HAL_SYSTEM_RESET_CB)
-    hal_system_reset_cb();
-#endif
-
-    while (1) {
-        HAL_DEBUG_BREAK();
-        CRG_TOP->SYS_CTRL_REG = 0x20;
-        NVIC_SystemReset();
-    }
-}
-
-int
-hal_debugger_connected(void)
-{
-    return CRG_TOP->SYS_STAT_REG & CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Msk;
-}
-
-void
-hal_system_clock_start(void)
-{
-    /* Reset clock dividers to 0 */
-    CRG_TOP->CLK_AMBA_REG &= ~(CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk | CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk);
-
-    /* PD_TIM is already started in SystemInit */
-
-    da1469x_clock_sys_xtal32m_init();
-    da1469x_clock_sys_xtal32m_enable();
-#if MYNEWT_VAL(MCU_PLL_ENABLE)
-    da1469x_clock_sys_pll_enable();
-#endif
-#if MYNEWT_VAL_CHOICE(MCU_SYSCLK_SOURCE, PLL96)
-    da1469x_clock_pll_wait_to_lock();
-    da1469x_clock_sys_pll_switch();
-#endif
-#if MYNEWT_VAL_CHOICE(MCU_SYSCLK_SOURCE, XTAL32M)
-    /* Switch to XTAL32M and disable RC32M */
-    da1469x_clock_sys_xtal32m_switch_safe();
-#endif
-    da1469x_clock_sys_rc32m_disable();
-
-#if MYNEWT_VAL_CHOICE(MCU_LPCLK_SOURCE, RCX)
-    /* Switch to RCX and calibrate it */
-    da1469x_clock_lp_rcx_enable();
-    da1469x_clock_lp_rcx_switch();
-    da1469x_clock_lp_rcx_calibrate();
-    da1469x_lpclk_enabled();
-#else
-    /*
-     * We cannot switch lp_clk to XTAL32K here since it needs some time to
-     * settle, so we just disable RCX (we don't need it) and then we'll handle
-     * switch to XTAL32K from sysinit since we need os_cputime for this.
-     */
-    da1469x_clock_lp_rcx_disable();
-#endif
-}
-
-enum hal_reset_reason
-hal_reset_cause(void)
-{
-#if MYNEWT_VAL(BOOT_LOADER)
-    return 0;
-#else
-    return g_hal_reset_reason;
-#endif
-}
diff --git a/tinyusb/hw/mcu/dialog/da1469x/src/hal_system_start.c b/tinyusb/hw/mcu/dialog/da1469x/src/hal_system_start.c
deleted file mode 100755
index bd246504..00000000
--- a/tinyusb/hw/mcu/dialog/da1469x/src/hal_system_start.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements.  See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership.  The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License.  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied.  See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#include <assert.h>
-#include <stdint.h>
-#include "mcu/mcu.h"
-#include "mcu/da1469x_hal.h"
-#include <flash_map/flash_map.h>
-#include <mcu/da1469x_clock.h>
-#if MCUBOOT_MYNEWT
-#include "bootutil/bootutil.h"
-#include "bootutil/image.h"
-#include "bootutil/bootutil_log.h"
-#include "mcu/da1469x_dma.h"
-#include "mcu/da1469x_otp.h"
-#endif
-
-#if MYNEWT_VAL(BOOT_CUSTOM_START) && MCUBOOT_MYNEWT
-sec_text_ram_core
-#endif
-void __attribute__((naked))
-hal_system_start(void *img_start)
-{
-    uint32_t img_data_addr;
-    uint32_t *img_data;
-
-    img_data_addr = MCU_MEM_QSPIF_M_START_ADDRESS + (uint32_t)img_start;
-
-    assert(img_data_addr < MCU_MEM_QSPIF_M_END_ADDRESS);
-
-    img_data = (uint32_t *)img_data_addr;
-
-    asm volatile (".syntax unified        \n"
-                  /* 1st word is stack pointer */
-                  "    msr  msp, %0       \n"
-                  /* 2nd word is a reset handler (image entry) */
-                  "    bx   %1            \n"
-                  : /* no output */
-                  : "r" (img_data[0]), "r" (img_data[1]));
-}
-
-void
-hal_system_restart(void *img_start)
-{
-    uint32_t primask __attribute__((unused));
-    int i;
-
-    /*
-     * Disable interrupts, and leave them disabled.
-     * They get re-enabled when system starts coming back again.
-     */
-    __HAL_DISABLE_INTERRUPTS(primask);
-
-    for (i = 0; i < sizeof(NVIC->ICER) / sizeof(NVIC->ICER[0]); i++) {
-        NVIC->ICER[i] = 0xffffffff;
-    }
-
-    hal_system_start(img_start);
-}
-
-#if MYNEWT_VAL(BOOT_CUSTOM_START) && MCUBOOT_MYNEWT
-#define IMAGE_TLV_AES_NONCE   0x50
-#define IMAGE_TLV_SECRET_ID   0x60
-
-sec_text_ram_core void
-boot_custom_start(uintptr_t flash_base, struct boot_rsp *rsp)
-{
-    int rc;
-    struct image_tlv_iter it;
-    const struct flash_area *fap;
-    uint32_t off;
-    uint16_t len;
-    uint16_t type;
-    uint8_t buf[8];
-    uint8_t key;
-    uint32_t nonce[2];
-    bool has_aes_nonce;
-    bool has_secret_id;
-    DMA_Type *dma_regs = DMA;
-    uint32_t  jump_offset = rsp->br_image_off + rsp->br_hdr->ih_hdr_size;
-
-    BOOT_LOG_INF("Custom initialization");
-
-    /* skip to booting if we are running nonsecure mode */
-    if (!(CRG_TOP->SECURE_BOOT_REG & 0x1)) {
-        hal_system_start((void *)(flash_base + jump_offset));
-    }
-
-    rc = flash_area_open(flash_area_id_from_image_slot(0), &fap);
-    assert(rc == 0);
-
-    rc = bootutil_tlv_iter_begin(&it, rsp->br_hdr, fap, IMAGE_TLV_ANY, true);
-    assert(rc == 0);
-
-    has_aes_nonce = has_secret_id = false;
-    while (true) {
-        rc = bootutil_tlv_iter_next(&it, &off, &len, &type);
-        assert(rc >= 0);
-
-        if (rc > 0) {
-            break;
-        }
-
-        if (type == IMAGE_TLV_AES_NONCE) {
-            assert(len == 8);
-
-            rc = flash_area_read(fap, off, buf, len);
-            assert(rc == 0);
-
-            nonce[0] = __builtin_bswap32(*(uint32_t *)buf);
-            nonce[1] = __builtin_bswap32(*(uint32_t *)(buf + 4));
-            has_aes_nonce = true;
-        } else if (type == IMAGE_TLV_SECRET_ID) {
-            assert(len == 4);
-
-            rc = flash_area_read(fap, off, buf, len);
-            assert(rc == 0);
-
-            key = buf[0];
-            has_secret_id = true;
-        }
-    }
-
-    assert(has_aes_nonce && has_secret_id && key <= 7);
-
-    /* enable OTP clock and set in read mode */
-    da1469x_clock_amba_enable(CRG_TOP_CLK_AMBA_REG_OTP_ENABLE_Msk);
-    da1469x_otp_set_mode(OTPC_MODE_READ);
-
-    /* disable decrypt on the fly and program start and end addresses */
-    QSPIC->QSPIC_CTR_CTRL_REG = 0;
-    QSPIC->QSPIC_CTR_SADDR_REG = jump_offset;
-    QSPIC->QSPIC_CTR_EADDR_REG = QSPIC->QSPIC_CTR_SADDR_REG +
-                                 rsp->br_hdr->ih_img_size - 1;
-
-    /* securely DMA hardware key from secret storage to QSPI decrypt engine */
-    dma_regs->DMA_REQ_MUX_REG |= 0xf000;
-    dma_regs->DMA7_LEN_REG = 8;
-    dma_regs->DMA7_A_START_REG = MCU_OTPM_BASE + OTP_SEGMENT_QSPI_FW_KEYS +
-                                 (32 * key);
-    dma_regs->DMA7_B_START_REG = (uint32_t)&QSPIC->QSPIC_CTR_KEY_0_3_REG;
-    dma_regs->DMA7_CTRL_REG = DMA_DMA7_CTRL_REG_AINC_Msk |
-                              DMA_DMA7_CTRL_REG_BINC_Msk |
-                              (MCU_DMA_BUS_WIDTH_4B << DMA_DMA7_CTRL_REG_BW_Pos) |
-                              DMA_DMA7_CTRL_REG_DMA_ON_Msk;
-    while (dma_regs->DMA7_IDX_REG != 8);
-
-    /* program NONCE */
-    QSPIC->QSPIC_CTR_NONCE_0_3_REG = nonce[0];
-    QSPIC->QSPIC_CTR_NONCE_4_7_REG = nonce[1];
-
-    /* turn back on decrypt on the fly */
-    QSPIC->QSPIC_CTR_CTRL_REG = 1;
-
-    /* set OTP to standby and turn off clock */
-    da1469x_otp_set_mode(OTPC_MODE_STBY);
-    da1469x_clock_amba_disable(CRG_TOP_CLK_AMBA_REG_OTP_ENABLE_Msk);
-
-    hal_system_start((void *)(flash_base + jump_offset));
-}
-#endif
diff --git a/tinyusb/hw/mcu/dialog/da1469x/src/system_da1469x.c b/tinyusb/hw/mcu/dialog/da1469x/src/system_da1469x.c
deleted file mode 100755
index 538bac79..00000000
--- a/tinyusb/hw/mcu/dialog/da1469x/src/system_da1469x.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements.  See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership.  The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License.  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied.  See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#include "mcu/mcu.h"
-#include <mcu/da1469x_clock.h>
-
-extern uint8_t __StackLimit;
-
-uint32_t SystemCoreClock = 32000000;
-
-void
-SystemInit(void)
-{
-  /* Enable FPU when using hard-float */
-#if (__FPU_USED == 1)
-  SCB->CPACR |= (3UL << 20) | (3UL << 22);
-  __DSB();
-  __ISB();
-#endif
-
-  /* Freez watchdog */
-  GPREG->SET_FREEZE_REG |= GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Msk;
-  /* Initialize power domains (disable radio only) */
-  CRG_TOP->PMU_CTRL_REG = CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Msk;
-
-  CRG_TOP->P0_SET_PAD_LATCH_REG = CRG_TOP_P0_PAD_LATCH_REG_P0_LATCH_EN_Msk;
-  CRG_TOP->P1_SET_PAD_LATCH_REG = CRG_TOP_P1_PAD_LATCH_REG_P1_LATCH_EN_Msk;
-
-  /* Reset clock dividers to 0 */
-  CRG_TOP->CLK_AMBA_REG &= ~(CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk | CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk);
-
-  /* PD_TIM is already started in SystemInit */
-
-  da1469x_clock_sys_xtal32m_init();
-  da1469x_clock_sys_xtal32m_enable();
-  da1469x_clock_sys_pll_enable();
-  da1469x_clock_pll_wait_to_lock();
-  /* Switch to XTAL32M and disable RC32M */
-  da1469x_clock_sys_xtal32m_switch_safe();
-  da1469x_clock_sys_rc32m_disable();
-}
-
-void _init(void)
-{
-}
diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble.h
deleted file mode 100755
index 76a432bf..00000000
--- a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble.h
+++ /dev/null
@@ -1,685 +0,0 @@
-/*
- * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- *    list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form, except as embedded into a Nordic
- *    Semiconductor ASA integrated circuit in a product or a software update for
- *    such product, must reproduce the above copyright notice, this list of
- *    conditions and the following disclaimer in the documentation and/or other
- *    materials provided with the distribution.
- *
- * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
- *    contributors may be used to endorse or promote products derived from this
- *    software without specific prior written permission.
- *
- * 4. This software, with or without modification, must only be used with a
- *    Nordic Semiconductor ASA integrated circuit.
- *
- * 5. Any software provided in binary form under this license must not be reverse
- *    engineered, decompiled, modified and/or disassembled.
- *
- * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
-  @addtogroup BLE_COMMON BLE SoftDevice Common
-  @{
-  @defgroup ble_api Events, type definitions and API calls
-  @{
-
-  @brief Module independent events, type definitions and API calls for the BLE SoftDevice.
-
- */
-
-#ifndef BLE_H__
-#define BLE_H__
-
-#include <stdint.h>
-#include "nrf_svc.h"
-#include "nrf_error.h"
-#include "ble_err.h"
-#include "ble_gap.h"
-#include "ble_l2cap.h"
-#include "ble_gatt.h"
-#include "ble_gattc.h"
-#include "ble_gatts.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @addtogroup BLE_COMMON_ENUMERATIONS Enumerations
- * @{ */
-
-/**
- * @brief Common API SVC numbers.
- */
-enum BLE_COMMON_SVCS
-{
-  SD_BLE_ENABLE = BLE_SVC_BASE,         /**< Enable and initialize the BLE stack */
-  SD_BLE_EVT_GET,                       /**< Get an event from the pending events queue. */
-  SD_BLE_UUID_VS_ADD,                   /**< Add a Vendor Specific base UUID. */
-  SD_BLE_UUID_DECODE,                   /**< Decode UUID bytes. */
-  SD_BLE_UUID_ENCODE,                   /**< Encode UUID bytes. */
-  SD_BLE_VERSION_GET,                   /**< Get the local version information (company ID, Link Layer Version, Link Layer Subversion). */
-  SD_BLE_USER_MEM_REPLY,                /**< User Memory Reply. */
-  SD_BLE_OPT_SET,                       /**< Set a BLE option. */
-  SD_BLE_OPT_GET,                       /**< Get a BLE option. */
-  SD_BLE_CFG_SET,                       /**< Add a configuration to the BLE stack. */
-  SD_BLE_UUID_VS_REMOVE,                /**< Remove a Vendor Specific base UUID. */
-};
-
-/**
- * @brief BLE Module Independent Event IDs.
- */
-enum BLE_COMMON_EVTS
-{
-  BLE_EVT_USER_MEM_REQUEST = BLE_EVT_BASE + 0,   /**< User Memory request. @ref ble_evt_user_mem_request_t */
-  BLE_EVT_USER_MEM_RELEASE = BLE_EVT_BASE + 1,   /**< User Memory release. @ref ble_evt_user_mem_release_t */
-};
-
-/**@brief BLE Connection Configuration IDs.
- *
- * IDs that uniquely identify a connection configuration.
- */
-enum BLE_CONN_CFGS
-{
-    BLE_CONN_CFG_GAP   = BLE_CONN_CFG_BASE + 0, /**< BLE GAP specific connection configuration. */
-    BLE_CONN_CFG_GATTC = BLE_CONN_CFG_BASE + 1, /**< BLE GATTC specific connection configuration. */
-    BLE_CONN_CFG_GATTS = BLE_CONN_CFG_BASE + 2, /**< BLE GATTS specific connection configuration. */
-    BLE_CONN_CFG_GATT  = BLE_CONN_CFG_BASE + 3, /**< BLE GATT specific connection configuration. */
-    BLE_CONN_CFG_L2CAP = BLE_CONN_CFG_BASE + 4, /**< BLE L2CAP specific connection configuration. */
-};
-
-/**@brief BLE Common Configuration IDs.
- *
- * IDs that uniquely identify a common configuration.
- */
-enum BLE_COMMON_CFGS
-{
-  BLE_COMMON_CFG_VS_UUID = BLE_CFG_BASE, /**< Vendor specific base UUID configuration */
-};
-
-/**@brief Common Option IDs.
- * IDs that uniquely identify a common option.
- */
-enum BLE_COMMON_OPTS
-{
-  BLE_COMMON_OPT_PA_LNA          = BLE_OPT_BASE + 0, /**< PA and LNA options */
-  BLE_COMMON_OPT_CONN_EVT_EXT    = BLE_OPT_BASE + 1, /**< Extended connection events option */
-  BLE_COMMON_OPT_EXTENDED_RC_CAL = BLE_OPT_BASE + 2, /**< Extended RC calibration option */
-  BLE_COMMON_OPT_ADV_SCHED_CFG   = BLE_OPT_BASE + 3, /**< Advertiser role scheduling configuration option */
-};
-
-/** @} */
-
-/** @addtogroup BLE_COMMON_DEFINES Defines
- * @{ */
-
-/** @brief  Required pointer alignment for BLE Events.
-*/
-#define BLE_EVT_PTR_ALIGNMENT    4
-
-/** @brief  Leaves the maximum of the two arguments.
-*/
-#define BLE_MAX(a, b) ((a) < (b) ? (b) : (a))
-
-/** @brief  Maximum possible length for BLE Events.
- * @note The highest value used for @ref ble_gatt_conn_cfg_t::att_mtu in any connection configuration shall be used as a parameter.
- * If that value has not been configured for any connections then @ref BLE_GATT_ATT_MTU_DEFAULT must be used instead.
-*/
-#define BLE_EVT_LEN_MAX(ATT_MTU) ( \
-    offsetof(ble_evt_t, evt.gattc_evt.params.prim_srvc_disc_rsp.services) + ((ATT_MTU) - 1) / 4 * sizeof(ble_gattc_service_t) \
-)
-
-/** @defgroup ADV_SCHED_CFG Advertiser Role Scheduling Configuration
- * @{ */
-#define ADV_SCHED_CFG_DEFAULT  0  /**< Default advertiser role scheduling configuration. */
-#define ADV_SCHED_CFG_IMPROVED 1  /**< Improved advertiser role scheduling configuration in which the housekeeping time is reduced. */
-/** @} */
-
-/** @defgroup BLE_USER_MEM_TYPES User Memory Types
- * @{ */
-#define BLE_USER_MEM_TYPE_INVALID               0x00  /**< Invalid User Memory Types. */
-#define BLE_USER_MEM_TYPE_GATTS_QUEUED_WRITES   0x01  /**< User Memory for GATTS queued writes. */
-/** @} */
-
-/** @defgroup BLE_UUID_VS_COUNTS Vendor Specific base UUID counts
- * @{
- */
-#define BLE_UUID_VS_COUNT_DEFAULT 10  /**< Default VS UUID count. */
-#define BLE_UUID_VS_COUNT_MAX     254 /**< Maximum VS UUID count. */
-/** @} */
-
-/** @defgroup BLE_COMMON_CFG_DEFAULTS Configuration defaults.
- * @{
- */
-#define BLE_CONN_CFG_TAG_DEFAULT  0    /**< Default configuration tag, SoftDevice default connection configuration. */
-
-/** @} */
-
-/** @} */
-
-/** @addtogroup BLE_COMMON_STRUCTURES Structures
- * @{ */
-
-/**@brief User Memory Block. */
-typedef struct
-{
-  uint8_t          *p_mem;      /**< Pointer to the start of the user memory block. */
-  uint16_t          len;        /**< Length in bytes of the user memory block. */
-} ble_user_mem_block_t;
-
-/**@brief Event structure for @ref BLE_EVT_USER_MEM_REQUEST. */
-typedef struct
-{
-  uint8_t                     type;     /**< User memory type, see @ref BLE_USER_MEM_TYPES. */
-} ble_evt_user_mem_request_t;
-
-/**@brief Event structure for @ref BLE_EVT_USER_MEM_RELEASE. */
-typedef struct
-{
-  uint8_t                     type;       /**< User memory type, see @ref BLE_USER_MEM_TYPES. */
-  ble_user_mem_block_t        mem_block;  /**< User memory block */
-} ble_evt_user_mem_release_t;
-
-/**@brief Event structure for events not associated with a specific function module. */
-typedef struct
-{
-  uint16_t conn_handle;                                 /**< Connection Handle on which this event occurred. */
-  union
-  {
-    ble_evt_user_mem_request_t      user_mem_request;    /**< User Memory Request Event Parameters. */
-    ble_evt_user_mem_release_t      user_mem_release;    /**< User Memory Release Event Parameters. */
-  } params;                                              /**< Event parameter union. */
-} ble_common_evt_t;
-
-/**@brief BLE Event header. */
-typedef struct
-{
-  uint16_t evt_id;                /**< Value from a BLE_<module>_EVT series. */
-  uint16_t evt_len;               /**< Length in octets including this header. */
-} ble_evt_hdr_t;
-
-/**@brief Common BLE Event type, wrapping the module specific event reports. */
-typedef struct
-{
-  ble_evt_hdr_t header;           /**< Event header. */
-  union
-  {
-    ble_common_evt_t  common_evt; /**< Common Event, evt_id in BLE_EVT_* series. */
-    ble_gap_evt_t     gap_evt;    /**< GAP originated event, evt_id in BLE_GAP_EVT_* series. */
-    ble_gattc_evt_t   gattc_evt;  /**< GATT client originated event, evt_id in BLE_GATTC_EVT* series. */
-    ble_gatts_evt_t   gatts_evt;  /**< GATT server originated event, evt_id in BLE_GATTS_EVT* series. */
-    ble_l2cap_evt_t   l2cap_evt;  /**< L2CAP originated event, evt_id in BLE_L2CAP_EVT* series. */
-  } evt;                          /**< Event union. */
-} ble_evt_t;
-
-
-/**
- * @brief Version Information.
- */
-typedef struct
-{
-  uint8_t   version_number;    /**< Link Layer Version number. See https://www.bluetooth.org/en-us/specification/assigned-numbers/link-layer for assigned values. */
-  uint16_t  company_id;        /**< Company ID, Nordic Semiconductor's company ID is 89 (0x0059) (https://www.bluetooth.org/apps/content/Default.aspx?doc_id=49708). */
-  uint16_t  subversion_number; /**< Link Layer Sub Version number, corresponds to the SoftDevice Config ID or Firmware ID (FWID). */
-} ble_version_t;
-
-/**
- * @brief Configuration parameters for the PA and LNA.
- */
-typedef struct
-{
-     uint8_t enable :1;      /**< Enable toggling for this amplifier */
-     uint8_t active_high :1; /**< Set the pin to be active high */
-     uint8_t gpio_pin :6;    /**< The GPIO pin to toggle for this amplifier */
-} ble_pa_lna_cfg_t;
-
-/**
- * @brief PA & LNA GPIO toggle configuration
- *
- * This option configures the SoftDevice to toggle pins when the radio is active for use with a power amplifier and/or
- * a low noise amplifier.
- *
- * Toggling the pins is achieved by using two PPI channels and a GPIOTE channel. The hardware channel IDs are provided
- * by the application and should be regarded as reserved as long as any PA/LNA toggling is enabled.
- *
- * @note  @ref sd_ble_opt_get is not supported for this option.
- * @note  Setting this option while the radio is in use (i.e. any of the roles are active) may have undefined consequences
- * and must be avoided by the application.
- */
-typedef struct
-{
-   ble_pa_lna_cfg_t pa_cfg;   /**< Power Amplifier configuration */
-   ble_pa_lna_cfg_t lna_cfg;  /**< Low Noise Amplifier configuration */
-
-   uint8_t ppi_ch_id_set;     /**< PPI channel used for radio pin setting */
-   uint8_t ppi_ch_id_clr;     /**< PPI channel used for radio pin clearing */
-   uint8_t gpiote_ch_id;      /**< GPIOTE channel used for radio pin toggling */
-} ble_common_opt_pa_lna_t;
-
-/**
- * @brief Configuration of extended BLE connection events.
- *
- * When enabled the SoftDevice will dynamically extend the connection event when possible.
- *
- * The connection event length is controlled by the connection configuration as set by @ref ble_gap_conn_cfg_t::event_length.
- * The connection event can be extended if there is time to send another packet pair before the start of the next connection interval,
- * and if there are no conflicts with other BLE roles requesting radio time.
- *
- * @note @ref sd_ble_opt_get is not supported for this option.
- */
-typedef struct
-{
-   uint8_t enable : 1; /**< Enable extended BLE connection events, disabled by default. */
-} ble_common_opt_conn_evt_ext_t;
-
-/**
- * @brief Enable/disable extended RC calibration.
- *
- * If extended RC calibration is enabled and the internal RC oscillator (@ref NRF_CLOCK_LF_SRC_RC) is used as the SoftDevice
- * LFCLK source, the SoftDevice as a peripheral will by default try to increase the receive window if two consecutive packets
- * are not received. If it turns out that the packets were not received due to clock drift, the RC calibration is started.
- * This calibration comes in addition to the periodic calibration that is configured by @ref sd_softdevice_enable(). When
- * using only peripheral connections, the periodic calibration can therefore be configured with a much longer interval as the
- * peripheral will be able to detect and adjust automatically to clock drift, and calibrate on demand.
- *
- * If extended RC calibration is disabled and the internal RC oscillator is used as the SoftDevice LFCLK source, the
- * RC oscillator is calibrated periodically as configured by @ref sd_softdevice_enable().
- *
- * @note @ref sd_ble_opt_get is not supported for this option.
- */
-typedef struct
-{
-   uint8_t enable : 1; /**< Enable extended RC calibration, enabled by default. */
-} ble_common_opt_extended_rc_cal_t;
-
-/**
- * @brief Configuration of BLE advertiser role scheduling.
- *
- * @note @ref sd_ble_opt_get is not supported for this option.
- */
-typedef struct
-{
-  uint8_t sched_cfg;  /**< See @ref ADV_SCHED_CFG. */
-} ble_common_opt_adv_sched_cfg_t;
-
-/**@brief Option structure for common options. */
-typedef union
-{
-  ble_common_opt_pa_lna_t          pa_lna;          /**< Parameters for controlling PA and LNA pin toggling. */
-  ble_common_opt_conn_evt_ext_t    conn_evt_ext;    /**< Parameters for enabling extended connection events. */
-  ble_common_opt_extended_rc_cal_t extended_rc_cal; /**< Parameters for enabling extended RC calibration. */
-  ble_common_opt_adv_sched_cfg_t   adv_sched_cfg;   /**< Parameters for configuring advertiser role scheduling. */
-} ble_common_opt_t;
-
-/**@brief Common BLE Option type, wrapping the module specific options. */
-typedef union
-{
-  ble_common_opt_t  common_opt;         /**< COMMON options, opt_id in @ref BLE_COMMON_OPTS series. */
-  ble_gap_opt_t     gap_opt;            /**< GAP option, opt_id in @ref BLE_GAP_OPTS series. */
-} ble_opt_t;
-
-/**@brief BLE connection configuration type, wrapping the module specific configurations, set with
- * @ref sd_ble_cfg_set.
- *
- * @note Connection configurations don't have to be set.
- * In the case that no configurations has been set, or fewer connection configurations has been set than enabled connections,
- * the default connection configuration will be automatically added for the remaining connections.
- * When creating connections with the default configuration, @ref BLE_CONN_CFG_TAG_DEFAULT should be used in
- * place of @ref ble_conn_cfg_t::conn_cfg_tag.
- *
- * @sa sd_ble_gap_adv_start()
- * @sa sd_ble_gap_connect()
- *
- * @mscs
- * @mmsc{@ref BLE_CONN_CFG}
- * @endmscs
-
- */
-typedef struct
-{
-  uint8_t              conn_cfg_tag;        /**< The application chosen tag it can use with the
-                                                 @ref sd_ble_gap_adv_start() and @ref sd_ble_gap_connect() calls
-                                                 to select this configuration when creating a connection.
-                                                 Must be different for all connection configurations added and not @ref BLE_CONN_CFG_TAG_DEFAULT. */
-  union {
-    ble_gap_conn_cfg_t   gap_conn_cfg;      /**< GAP connection configuration, cfg_id is @ref BLE_CONN_CFG_GAP. */
-    ble_gattc_conn_cfg_t gattc_conn_cfg;    /**< GATTC connection configuration, cfg_id is @ref BLE_CONN_CFG_GATTC. */
-    ble_gatts_conn_cfg_t gatts_conn_cfg;    /**< GATTS connection configuration, cfg_id is @ref BLE_CONN_CFG_GATTS. */
-    ble_gatt_conn_cfg_t  gatt_conn_cfg;     /**< GATT connection configuration, cfg_id is @ref BLE_CONN_CFG_GATT. */
-    ble_l2cap_conn_cfg_t l2cap_conn_cfg;    /**< L2CAP connection configuration, cfg_id is @ref BLE_CONN_CFG_L2CAP. */
-  } params;                                 /**< Connection configuration union. */
-} ble_conn_cfg_t;
-
-/**
- * @brief Configuration of Vendor Specific base UUIDs, set with @ref sd_ble_cfg_set.
- *
- * @retval ::NRF_ERROR_INVALID_PARAM Too many UUIDs configured.
- */
-typedef struct
-{
-  uint8_t vs_uuid_count; /**< Number of 128-bit Vendor Specific base UUID bases to allocate memory for.
-                              Default value is @ref BLE_UUID_VS_COUNT_DEFAULT. Maximum value is
-                              @ref BLE_UUID_VS_COUNT_MAX. */
-} ble_common_cfg_vs_uuid_t;
-
-/**@brief Common BLE Configuration type, wrapping the common configurations. */
-typedef union
-{
-  ble_common_cfg_vs_uuid_t  vs_uuid_cfg;  /**< Vendor Specific base UUID configuration, cfg_id is @ref BLE_COMMON_CFG_VS_UUID. */
-} ble_common_cfg_t;
-
-/**@brief BLE Configuration type, wrapping the module specific configurations. */
-typedef union
-{
-  ble_conn_cfg_t    conn_cfg;   /**< Connection specific configurations, cfg_id in @ref BLE_CONN_CFGS series. */
-  ble_common_cfg_t  common_cfg; /**< Global common configurations, cfg_id in @ref BLE_COMMON_CFGS series. */
-  ble_gap_cfg_t     gap_cfg;    /**< Global GAP configurations, cfg_id in @ref BLE_GAP_CFGS series. */
-  ble_gatts_cfg_t   gatts_cfg;  /**< Global GATTS configuration, cfg_id in @ref BLE_GATTS_CFGS series. */
-} ble_cfg_t;
-
-/** @} */
-
-/** @addtogroup BLE_COMMON_FUNCTIONS Functions
- * @{ */
-
-/**@brief Enable the BLE stack
- *
- * @param[in, out] p_app_ram_base   Pointer to a variable containing the start address of the
- *                                  application RAM region (APP_RAM_BASE). On return, this will
- *                                  contain the minimum start address of the application RAM region
- *                                  required by the SoftDevice for this configuration.
- *
- * @note The memory requirement for a specific configuration will not increase between SoftDevices
- *       with the same major version number.
- *
- * @note At runtime the IC's RAM is split into 2 regions: The SoftDevice RAM region is located
- *       between 0x20000000 and APP_RAM_BASE-1 and the application's RAM region is located between
- *       APP_RAM_BASE and the start of the call stack.
- *
- * @details This call initializes the BLE stack, no BLE related function other than @ref
- *          sd_ble_cfg_set can be called before this one.
- *
- * @mscs
- * @mmsc{@ref BLE_COMMON_ENABLE}
- * @endmscs
- *
- * @retval ::NRF_SUCCESS              The BLE stack has been initialized successfully.
- * @retval ::NRF_ERROR_INVALID_STATE  The BLE stack had already been initialized and cannot be reinitialized.
- * @retval ::NRF_ERROR_INVALID_ADDR   Invalid or not sufficiently aligned pointer supplied.
- * @retval ::NRF_ERROR_NO_MEM         One or more of the following is true:
- *                                    - The amount of memory assigned to the SoftDevice by *p_app_ram_base is not
- *                                      large enough to fit this configuration's memory requirement. Check *p_app_ram_base
- *                                      and set the start address of the application RAM region accordingly.
- *                                    - Dynamic part of the SoftDevice RAM region is larger then 64 kB which
- *                                      is currently not supported.
- * @retval ::NRF_ERROR_RESOURCES      The total number of L2CAP Channels configured using @ref sd_ble_cfg_set is too large.
- */
-SVCALL(SD_BLE_ENABLE, uint32_t, sd_ble_enable(uint32_t * p_app_ram_base));
-
-/**@brief Add configurations for the BLE stack
- *
- * @param[in] cfg_id              Config ID, see @ref BLE_CONN_CFGS, @ref BLE_COMMON_CFGS, @ref
- *                                BLE_GAP_CFGS or @ref BLE_GATTS_CFGS.
- * @param[in] p_cfg               Pointer to a ble_cfg_t structure containing the configuration value.
- * @param[in] app_ram_base        The start address of the application RAM region (APP_RAM_BASE).
- *                                See @ref sd_ble_enable for details about APP_RAM_BASE.
- *
- * @note The memory requirement for a specific configuration will not increase between SoftDevices
- *       with the same major version number.
- *
- * @note If a configuration is set more than once, the last one set is the one that takes effect on
- *       @ref sd_ble_enable.
- *
- * @note Any part of the BLE stack that is NOT configured with @ref sd_ble_cfg_set will have default
- *       configuration.
- *
- * @note @ref sd_ble_cfg_set may be called at any time when the SoftDevice is enabled (see @ref
- *       sd_softdevice_enable) while the BLE part of the SoftDevice is not enabled (see @ref
- *       sd_ble_enable).
- *
- * @note Error codes for the configurations are described in the configuration structs.
- *
- * @mscs
- * @mmsc{@ref BLE_COMMON_ENABLE}
- * @endmscs
- *
- * @retval ::NRF_SUCCESS              The configuration has been added successfully.
- * @retval ::NRF_ERROR_INVALID_STATE  The BLE stack had already been initialized.
- * @retval ::NRF_ERROR_INVALID_ADDR   Invalid or not sufficiently aligned pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM  Invalid cfg_id supplied.
- * @retval ::NRF_ERROR_NO_MEM         The amount of memory assigned to the SoftDevice by app_ram_base is not
- *                                    large enough to fit this configuration's memory requirement.
- */
-SVCALL(SD_BLE_CFG_SET, uint32_t, sd_ble_cfg_set(uint32_t cfg_id, ble_cfg_t const * p_cfg, uint32_t app_ram_base));
-
-/**@brief Get an event from the pending events queue.
- *
- * @param[out] p_dest Pointer to buffer to be filled in with an event, or NULL to retrieve the event length.
- *                    This buffer <b>must be aligned to the extend defined by @ref BLE_EVT_PTR_ALIGNMENT</b>.
- *                    The buffer should be interpreted as a @ref ble_evt_t struct.
- * @param[in, out] p_len Pointer the length of the buffer, on return it is filled with the event length.
- *
- * @details This call allows the application to pull a BLE event from the BLE stack. The application is signaled that
- * an event is available from the BLE stack by the triggering of the SD_EVT_IRQn interrupt.
- * The application is free to choose whether to call this function from thread mode (main context) or directly from the
- * Interrupt Service Routine that maps to SD_EVT_IRQn. In any case however, and because the BLE stack runs at a higher
- * priority than the application, this function should be called in a loop (until @ref NRF_ERROR_NOT_FOUND is returned)
- * every time SD_EVT_IRQn is raised to ensure that all available events are pulled from the BLE stack. Failure to do so
- * could potentially leave events in the internal queue without the application being aware of this fact.
- *
- * Sizing the p_dest buffer is equally important, since the application needs to provide all the memory necessary for the event to
- * be copied into application memory. If the buffer provided is not large enough to fit the entire contents of the event,
- * @ref NRF_ERROR_DATA_SIZE will be returned and the application can then call again with a larger buffer size.
- * The maximum possible event length is defined by @ref BLE_EVT_LEN_MAX. The application may also "peek" the event length
- * by providing p_dest as a NULL pointer and inspecting the value of *p_len upon return:
- *
- *     \code
- *     uint16_t len;
- *     errcode = sd_ble_evt_get(NULL, &len);
- *     \endcode
- *
- * @mscs
- * @mmsc{@ref BLE_COMMON_IRQ_EVT_MSC}
- * @mmsc{@ref BLE_COMMON_THREAD_EVT_MSC}
- * @endmscs
- *
- * @retval ::NRF_SUCCESS Event pulled and stored into the supplied buffer.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid or not sufficiently aligned pointer supplied.
- * @retval ::NRF_ERROR_NOT_FOUND No events ready to be pulled.
- * @retval ::NRF_ERROR_DATA_SIZE Event ready but could not fit into the supplied buffer.
- */
-SVCALL(SD_BLE_EVT_GET, uint32_t, sd_ble_evt_get(uint8_t *p_dest, uint16_t *p_len));
-
-
-/**@brief Add a Vendor Specific base UUID.
- *
- * @details This call enables the application to add a Vendor Specific base UUID to the BLE stack's table, for later
- * use with all other modules and APIs. This then allows the application to use the shorter, 24-bit @ref ble_uuid_t
- * format when dealing with both 16-bit and 128-bit UUIDs without having to check for lengths and having split code
- * paths. This is accomplished by extending the grouping mechanism that the Bluetooth SIG standard base UUID uses
- * for all other 128-bit UUIDs. The type field in the @ref ble_uuid_t structure is an index (relative to
- * @ref BLE_UUID_TYPE_VENDOR_BEGIN) to the table populated by multiple calls to this function, and the UUID field
- * in the same structure contains the 2 bytes at indexes 12 and 13. The number of possible 128-bit UUIDs available to
- * the application is therefore the number of Vendor Specific UUIDs added with the help of this function times 65536,
- * although restricted to modifying bytes 12 and 13 for each of the entries in the supplied array.
- *
- * @note Bytes 12 and 13 of the provided UUID will not be used internally, since those are always replaced by
- * the 16-bit uuid field in @ref ble_uuid_t.
- *
- * @note If a UUID is already present in the BLE stack's internal table, the corresponding index will be returned in
- * p_uuid_type along with an @ref NRF_SUCCESS error code.
- *
- * @param[in]  p_vs_uuid    Pointer to a 16-octet (128-bit) little endian Vendor Specific base UUID disregarding
- *                          bytes 12 and 13.
- * @param[out] p_uuid_type  Pointer to a uint8_t where the type field in @ref ble_uuid_t corresponding to this UUID will be stored.
- *
- * @retval ::NRF_SUCCESS Successfully added the Vendor Specific base UUID.
- * @retval ::NRF_ERROR_INVALID_ADDR If p_vs_uuid or p_uuid_type is NULL or invalid.
- * @retval ::NRF_ERROR_NO_MEM If there are no more free slots for VS UUIDs.
- */
-SVCALL(SD_BLE_UUID_VS_ADD, uint32_t, sd_ble_uuid_vs_add(ble_uuid128_t const *p_vs_uuid, uint8_t *p_uuid_type));
-
-
-/**@brief Remove a Vendor Specific base UUID.
- * 
- * @details This call removes a Vendor Specific base UUID that has been added with @ref sd_ble_uuid_vs_add. This function allows
- * the application to reuse memory allocated for Vendor Specific base UUIDs.
- *
- * @note Currently this function can only be called with a p_uuid_type set to @ref BLE_UUID_TYPE_UNKNOWN or the last added UUID type.
- *
- * @param[in]  p_uuid_type  Pointer to a uint8_t where the type field in @ref ble_uuid_t::type corresponds to the UUID type that
- *                          shall be removed. If the type is set to @ref BLE_UUID_TYPE_UNKNOWN, or the pointer is NULL, the last
- *                          Vendor Specific base UUID will be removed.
- * @param[out] p_uuid_type  Pointer to a uint8_t where the type field in @ref ble_uuid_t corresponds to the UUID type that was
- *                          removed. If function returns with a failure, it contains the last type that is in use by the ATT Server.
- *
- * @retval ::NRF_SUCCESS Successfully removed the Vendor Specific base UUID.
- * @retval ::NRF_ERROR_INVALID_ADDR If p_uuid_type is invalid.
- * @retval ::NRF_ERROR_INVALID_PARAM If p_uuid_type points to a non-valid UUID type.
- * @retval ::NRF_ERROR_FORBIDDEN If the Vendor Specific base UUID is in use by the ATT Server.
- */
-
-SVCALL(SD_BLE_UUID_VS_REMOVE, uint32_t, sd_ble_uuid_vs_remove(uint8_t *p_uuid_type));
-
-
-/** @brief Decode little endian raw UUID bytes (16-bit or 128-bit) into a 24 bit @ref ble_uuid_t structure.
- *
- * @details The raw UUID bytes excluding bytes 12 and 13 (i.e. bytes 0-11 and 14-15) of p_uuid_le are compared
- * to the corresponding ones in each entry of the table of Vendor Specific base UUIDs populated with @ref sd_ble_uuid_vs_add
- * to look for a match. If there is such a match, bytes 12 and 13 are returned as p_uuid->uuid and the index
- * relative to @ref BLE_UUID_TYPE_VENDOR_BEGIN as p_uuid->type.
- *
- * @note If the UUID length supplied is 2, then the type set by this call will always be @ref BLE_UUID_TYPE_BLE.
- *
- * @param[in]   uuid_le_len Length in bytes of the buffer pointed to by p_uuid_le (must be 2 or 16 bytes).
- * @param[in]   p_uuid_le   Pointer pointing to little endian raw UUID bytes.
- * @param[out]  p_uuid      Pointer to a @ref ble_uuid_t structure to be filled in.
- *
- * @retval ::NRF_SUCCESS Successfully decoded into the @ref ble_uuid_t structure.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_LENGTH Invalid UUID length.
- * @retval ::NRF_ERROR_NOT_FOUND For a 128-bit UUID, no match in the populated table of UUIDs.
- */
-SVCALL(SD_BLE_UUID_DECODE, uint32_t, sd_ble_uuid_decode(uint8_t uuid_le_len, uint8_t const *p_uuid_le, ble_uuid_t *p_uuid));
-
-
-/** @brief Encode a @ref ble_uuid_t structure into little endian raw UUID bytes (16-bit or 128-bit).
- *
- * @note The pointer to the destination buffer p_uuid_le may be NULL, in which case only the validity and size of p_uuid is computed.
- *
- * @param[in]   p_uuid        Pointer to a @ref ble_uuid_t structure that will be encoded into bytes.
- * @param[out]  p_uuid_le_len Pointer to a uint8_t that will be filled with the encoded length (2 or 16 bytes).
- * @param[out]  p_uuid_le     Pointer to a buffer where the little endian raw UUID bytes (2 or 16) will be stored.
- *
- * @retval ::NRF_SUCCESS Successfully encoded into the buffer.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid UUID type.
- */
-SVCALL(SD_BLE_UUID_ENCODE, uint32_t, sd_ble_uuid_encode(ble_uuid_t const *p_uuid, uint8_t *p_uuid_le_len, uint8_t *p_uuid_le));
-
-
-/**@brief Get Version Information.
- *
- * @details This call allows the application to get the BLE stack version information.
- *
- * @param[out] p_version Pointer to a ble_version_t structure to be filled in.
- *
- * @retval ::NRF_SUCCESS  Version information stored successfully.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_BUSY The BLE stack is busy (typically doing a locally-initiated disconnection procedure).
- */
-SVCALL(SD_BLE_VERSION_GET, uint32_t, sd_ble_version_get(ble_version_t *p_version));
-
-
-/**@brief Provide a user memory block.
- *
- * @note This call can only be used as a response to a @ref BLE_EVT_USER_MEM_REQUEST event issued to the application.
- *
- * @param[in] conn_handle Connection handle.
- * @param[in] p_block Pointer to a user memory block structure or NULL if memory is managed by the application.
- *
- * @mscs
- * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_PEER_CANCEL_MSC}
- * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_AUTH_MSC}
- * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_NOAUTH_MSC}
- * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_BUF_AUTH_MSC}
- * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_BUF_NOAUTH_MSC}
- * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_QUEUE_FULL_MSC}
- * @endmscs
- *
- * @retval ::NRF_SUCCESS Successfully queued a response to the peer.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_LENGTH Invalid user memory block length supplied.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection state or no user memory request pending.
- */
-SVCALL(SD_BLE_USER_MEM_REPLY, uint32_t, sd_ble_user_mem_reply(uint16_t conn_handle, ble_user_mem_block_t const *p_block));
-
-/**@brief Set a BLE option.
- *
- * @details This call allows the application to set the value of an option.
- *
- * @mscs
- * @mmsc{@ref BLE_GAP_PERIPH_BONDING_STATIC_PK_MSC}
- * @endmscs
- *
- * @param[in] opt_id Option ID, see @ref BLE_COMMON_OPTS and @ref BLE_GAP_OPTS.
- * @param[in] p_opt Pointer to a ble_opt_t structure containing the option value.
- *
- * @retval ::NRF_SUCCESS  Option set successfully.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints.
- * @retval ::NRF_ERROR_INVALID_STATE Unable to set the parameter at this time.
- * @retval ::NRF_ERROR_BUSY The BLE stack is busy or the previous procedure has not completed.
- */
-SVCALL(SD_BLE_OPT_SET, uint32_t, sd_ble_opt_set(uint32_t opt_id, ble_opt_t const *p_opt));
-
-
-/**@brief Get a BLE option.
- *
- * @details This call allows the application to retrieve the value of an option.
- *
- * @param[in] opt_id Option ID, see @ref BLE_COMMON_OPTS and @ref BLE_GAP_OPTS.
- * @param[out] p_opt Pointer to a ble_opt_t structure to be filled in.
- *
- * @retval ::NRF_SUCCESS  Option retrieved successfully.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints.
- * @retval ::NRF_ERROR_INVALID_STATE Unable to retrieve the parameter at this time.
- * @retval ::NRF_ERROR_BUSY The BLE stack is busy or the previous procedure has not completed.
- * @retval ::NRF_ERROR_NOT_SUPPORTED This option is not supported.
- *
- */
-SVCALL(SD_BLE_OPT_GET, uint32_t, sd_ble_opt_get(uint32_t opt_id, ble_opt_t *p_opt));
-
-/** @} */
-#ifdef __cplusplus
-}
-#endif
-#endif /* BLE_H__ */
-
-/**
-  @}
-  @}
-*/
diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_err.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_err.h
deleted file mode 100755
index 1b4820dc..00000000
--- a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_err.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- *    list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form, except as embedded into a Nordic
- *    Semiconductor ASA integrated circuit in a product or a software update for
- *    such product, must reproduce the above copyright notice, this list of
- *    conditions and the following disclaimer in the documentation and/or other
- *    materials provided with the distribution.
- *
- * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
- *    contributors may be used to endorse or promote products derived from this
- *    software without specific prior written permission.
- *
- * 4. This software, with or without modification, must only be used with a
- *    Nordic Semiconductor ASA integrated circuit.
- *
- * 5. Any software provided in binary form under this license must not be reverse
- *    engineered, decompiled, modified and/or disassembled.
- *
- * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
-  @addtogroup BLE_COMMON
-  @{
-  @addtogroup  nrf_error
-  @{
-    @ingroup BLE_COMMON
-  @}
-
-  @defgroup ble_err General error codes
-  @{
-
-  @brief General error code definitions for the BLE API.
-
-  @ingroup BLE_COMMON
-*/
-#ifndef NRF_BLE_ERR_H__
-#define NRF_BLE_ERR_H__
-
-#include "nrf_error.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* @defgroup BLE_ERRORS Error Codes
- * @{ */
-#define BLE_ERROR_NOT_ENABLED            (NRF_ERROR_STK_BASE_NUM+0x001) /**< @ref sd_ble_enable has not been called. */
-#define BLE_ERROR_INVALID_CONN_HANDLE    (NRF_ERROR_STK_BASE_NUM+0x002) /**< Invalid connection handle. */
-#define BLE_ERROR_INVALID_ATTR_HANDLE    (NRF_ERROR_STK_BASE_NUM+0x003) /**< Invalid attribute handle. */
-#define BLE_ERROR_INVALID_ADV_HANDLE     (NRF_ERROR_STK_BASE_NUM+0x004) /**< Invalid advertising handle. */
-#define BLE_ERROR_INVALID_ROLE           (NRF_ERROR_STK_BASE_NUM+0x005) /**< Invalid role. */
-#define BLE_ERROR_BLOCKED_BY_OTHER_LINKS (NRF_ERROR_STK_BASE_NUM+0x006) /**< The attempt to change link settings failed due to the scheduling of other links. */
-/** @} */
-
-
-/** @defgroup BLE_ERROR_SUBRANGES Module specific error code subranges
- *  @brief Assignment of subranges for module specific error codes.
- *  @note For specific error codes, see ble_<module>.h or ble_error_<module>.h.
- * @{ */
-#define NRF_L2CAP_ERR_BASE             (NRF_ERROR_STK_BASE_NUM+0x100) /**< L2CAP specific errors. */
-#define NRF_GAP_ERR_BASE               (NRF_ERROR_STK_BASE_NUM+0x200) /**< GAP specific errors. */
-#define NRF_GATTC_ERR_BASE             (NRF_ERROR_STK_BASE_NUM+0x300) /**< GATT client specific errors. */
-#define NRF_GATTS_ERR_BASE             (NRF_ERROR_STK_BASE_NUM+0x400) /**< GATT server specific errors. */
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif
-#endif
-
-
-/**
-  @}
-  @}
-*/
diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gap.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gap.h
deleted file mode 100755
index c434fefb..00000000
--- a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gap.h
+++ /dev/null
@@ -1,2696 +0,0 @@
-/*
- * Copyright (c) 2011 - 2018, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- *    list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form, except as embedded into a Nordic
- *    Semiconductor ASA integrated circuit in a product or a software update for
- *    such product, must reproduce the above copyright notice, this list of
- *    conditions and the following disclaimer in the documentation and/or other
- *    materials provided with the distribution.
- *
- * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
- *    contributors may be used to endorse or promote products derived from this
- *    software without specific prior written permission.
- *
- * 4. This software, with or without modification, must only be used with a
- *    Nordic Semiconductor ASA integrated circuit.
- *
- * 5. Any software provided in binary form under this license must not be reverse
- *    engineered, decompiled, modified and/or disassembled.
- *
- * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
-  @addtogroup BLE_GAP Generic Access Profile (GAP)
-  @{
-  @brief Definitions and prototypes for the GAP interface.
- */
-
-#ifndef BLE_GAP_H__
-#define BLE_GAP_H__
-
-#include <stdint.h>
-#include "nrf_svc.h"
-#include "nrf_error.h"
-#include "ble_hci.h"
-#include "ble_ranges.h"
-#include "ble_types.h"
-#include "ble_err.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**@addtogroup BLE_GAP_ENUMERATIONS Enumerations
- * @{ */
-
-/**@brief GAP API SVC numbers.
- */
-enum BLE_GAP_SVCS
-{
-  SD_BLE_GAP_ADDR_SET              = BLE_GAP_SVC_BASE,       /**< Set own Bluetooth Address. */
-  SD_BLE_GAP_ADDR_GET              = BLE_GAP_SVC_BASE + 1,   /**< Get own Bluetooth Address. */
-  SD_BLE_GAP_WHITELIST_SET         = BLE_GAP_SVC_BASE + 2,   /**< Set active whitelist. */
-  SD_BLE_GAP_DEVICE_IDENTITIES_SET = BLE_GAP_SVC_BASE + 3,   /**< Set device identity list. */
-  SD_BLE_GAP_PRIVACY_SET           = BLE_GAP_SVC_BASE + 4,   /**< Set Privacy settings*/
-  SD_BLE_GAP_PRIVACY_GET           = BLE_GAP_SVC_BASE + 5,   /**< Get Privacy settings*/
-  SD_BLE_GAP_ADV_SET_CONFIGURE     = BLE_GAP_SVC_BASE + 6,   /**< Configure an advertising set. */
-  SD_BLE_GAP_ADV_START             = BLE_GAP_SVC_BASE + 7,   /**< Start Advertising. */
-  SD_BLE_GAP_ADV_STOP              = BLE_GAP_SVC_BASE + 8,   /**< Stop Advertising. */
-  SD_BLE_GAP_CONN_PARAM_UPDATE     = BLE_GAP_SVC_BASE + 9,   /**< Connection Parameter Update. */
-  SD_BLE_GAP_DISCONNECT            = BLE_GAP_SVC_BASE + 10,  /**< Disconnect. */
-  SD_BLE_GAP_TX_POWER_SET          = BLE_GAP_SVC_BASE + 11,  /**< Set TX Power. */
-  SD_BLE_GAP_APPEARANCE_SET        = BLE_GAP_SVC_BASE + 12,  /**< Set Appearance. */
-  SD_BLE_GAP_APPEARANCE_GET        = BLE_GAP_SVC_BASE + 13,  /**< Get Appearance. */
-  SD_BLE_GAP_PPCP_SET              = BLE_GAP_SVC_BASE + 14,  /**< Set PPCP. */
-  SD_BLE_GAP_PPCP_GET              = BLE_GAP_SVC_BASE + 15,  /**< Get PPCP. */
-  SD_BLE_GAP_DEVICE_NAME_SET       = BLE_GAP_SVC_BASE + 16,  /**< Set Device Name. */
-  SD_BLE_GAP_DEVICE_NAME_GET       = BLE_GAP_SVC_BASE + 17,  /**< Get Device Name. */
-  SD_BLE_GAP_AUTHENTICATE          = BLE_GAP_SVC_BASE + 18,  /**< Initiate Pairing/Bonding. */
-  SD_BLE_GAP_SEC_PARAMS_REPLY      = BLE_GAP_SVC_BASE + 19,  /**< Reply with Security Parameters. */
-  SD_BLE_GAP_AUTH_KEY_REPLY        = BLE_GAP_SVC_BASE + 20,  /**< Reply with an authentication key. */
-  SD_BLE_GAP_LESC_DHKEY_REPLY      = BLE_GAP_SVC_BASE + 21,  /**< Reply with an LE Secure Connections DHKey. */
-  SD_BLE_GAP_KEYPRESS_NOTIFY       = BLE_GAP_SVC_BASE + 22,  /**< Notify of a keypress during an authentication procedure. */
-  SD_BLE_GAP_LESC_OOB_DATA_GET     = BLE_GAP_SVC_BASE + 23,  /**< Get the local LE Secure Connections OOB data. */
-  SD_BLE_GAP_LESC_OOB_DATA_SET     = BLE_GAP_SVC_BASE + 24,  /**< Set the remote LE Secure Connections OOB data. */
-  SD_BLE_GAP_ENCRYPT               = BLE_GAP_SVC_BASE + 25,  /**< Initiate encryption procedure. */
-  SD_BLE_GAP_SEC_INFO_REPLY        = BLE_GAP_SVC_BASE + 26,  /**< Reply with Security Information. */
-  SD_BLE_GAP_CONN_SEC_GET          = BLE_GAP_SVC_BASE + 27,  /**< Obtain connection security level. */
-  SD_BLE_GAP_RSSI_START            = BLE_GAP_SVC_BASE + 28,  /**< Start reporting of changes in RSSI. */
-  SD_BLE_GAP_RSSI_STOP             = BLE_GAP_SVC_BASE + 29,  /**< Stop reporting of changes in RSSI. */
-  SD_BLE_GAP_SCAN_START            = BLE_GAP_SVC_BASE + 30,  /**< Start Scanning. */
-  SD_BLE_GAP_SCAN_STOP             = BLE_GAP_SVC_BASE + 31,  /**< Stop Scanning. */
-  SD_BLE_GAP_CONNECT               = BLE_GAP_SVC_BASE + 32,  /**< Connect. */
-  SD_BLE_GAP_CONNECT_CANCEL        = BLE_GAP_SVC_BASE + 33,  /**< Cancel ongoing connection procedure. */
-  SD_BLE_GAP_RSSI_GET              = BLE_GAP_SVC_BASE + 34,  /**< Get the last RSSI sample. */
-  SD_BLE_GAP_PHY_UPDATE            = BLE_GAP_SVC_BASE + 35,  /**< Initiate or respond to a PHY Update Procedure. */
-  SD_BLE_GAP_DATA_LENGTH_UPDATE    = BLE_GAP_SVC_BASE + 36,  /**< Initiate or respond to a Data Length Update Procedure. */
-  SD_BLE_GAP_QOS_CHANNEL_SURVEY_START  = BLE_GAP_SVC_BASE + 37, /**< Start Quality of Service (QoS) channel survey module. */
-  SD_BLE_GAP_QOS_CHANNEL_SURVEY_STOP   = BLE_GAP_SVC_BASE + 38, /**< Stop Quality of Service (QoS) channel survey module. */
-  SD_BLE_GAP_ADV_ADDR_GET          = BLE_GAP_SVC_BASE + 39, /**< Get the Address used on air while Advertising. */
-};
-
-/**@brief GAP Event IDs.
- * IDs that uniquely identify an event coming from the stack to the application.
- */
-enum BLE_GAP_EVTS
-{
-  BLE_GAP_EVT_CONNECTED                   = BLE_GAP_EVT_BASE,       /**< Connected to peer.                              \n See @ref ble_gap_evt_connected_t             */
-  BLE_GAP_EVT_DISCONNECTED                = BLE_GAP_EVT_BASE + 1,   /**< Disconnected from peer.                         \n See @ref ble_gap_evt_disconnected_t.         */
-  BLE_GAP_EVT_CONN_PARAM_UPDATE           = BLE_GAP_EVT_BASE + 2,   /**< Connection Parameters updated.                  \n See @ref ble_gap_evt_conn_param_update_t.    */
-  BLE_GAP_EVT_SEC_PARAMS_REQUEST          = BLE_GAP_EVT_BASE + 3,   /**< Request to provide security parameters.         \n Reply with @ref sd_ble_gap_sec_params_reply.  \n See @ref ble_gap_evt_sec_params_request_t. */
-  BLE_GAP_EVT_SEC_INFO_REQUEST            = BLE_GAP_EVT_BASE + 4,   /**< Request to provide security information.        \n Reply with @ref sd_ble_gap_sec_info_reply.    \n See @ref ble_gap_evt_sec_info_request_t.   */
-  BLE_GAP_EVT_PASSKEY_DISPLAY             = BLE_GAP_EVT_BASE + 5,   /**< Request to display a passkey to the user.       \n In LESC Numeric Comparison, reply with @ref sd_ble_gap_auth_key_reply. \n See @ref ble_gap_evt_passkey_display_t. */
-  BLE_GAP_EVT_KEY_PRESSED                 = BLE_GAP_EVT_BASE + 6,   /**< Notification of a keypress on the remote device.\n See @ref ble_gap_evt_key_pressed_t           */
-  BLE_GAP_EVT_AUTH_KEY_REQUEST            = BLE_GAP_EVT_BASE + 7,   /**< Request to provide an authentication key.       \n Reply with @ref sd_ble_gap_auth_key_reply.    \n See @ref ble_gap_evt_auth_key_request_t.   */
-  BLE_GAP_EVT_LESC_DHKEY_REQUEST          = BLE_GAP_EVT_BASE + 8,   /**< Request to calculate an LE Secure Connections DHKey. \n Reply with @ref sd_ble_gap_lesc_dhkey_reply.  \n See @ref ble_gap_evt_lesc_dhkey_request_t */
-  BLE_GAP_EVT_AUTH_STATUS                 = BLE_GAP_EVT_BASE + 9,   /**< Authentication procedure completed with status. \n See @ref ble_gap_evt_auth_status_t.          */
-  BLE_GAP_EVT_CONN_SEC_UPDATE             = BLE_GAP_EVT_BASE + 10,  /**< Connection security updated.                    \n See @ref ble_gap_evt_conn_sec_update_t.      */
-  BLE_GAP_EVT_TIMEOUT                     = BLE_GAP_EVT_BASE + 11,  /**< Timeout expired.                                \n See @ref ble_gap_evt_timeout_t.              */
-  BLE_GAP_EVT_RSSI_CHANGED                = BLE_GAP_EVT_BASE + 12,  /**< RSSI report.                                    \n See @ref ble_gap_evt_rssi_changed_t.         */
-  BLE_GAP_EVT_ADV_REPORT                  = BLE_GAP_EVT_BASE + 13,  /**< Advertising report.                             \n See @ref ble_gap_evt_adv_report_t.           */
-  BLE_GAP_EVT_SEC_REQUEST                 = BLE_GAP_EVT_BASE + 14,  /**< Security Request.                               \n See @ref ble_gap_evt_sec_request_t.          */
-  BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST   = BLE_GAP_EVT_BASE + 15,  /**< Connection Parameter Update Request.            \n Reply with @ref sd_ble_gap_conn_param_update. \n See @ref ble_gap_evt_conn_param_update_request_t. */
-  BLE_GAP_EVT_SCAN_REQ_REPORT             = BLE_GAP_EVT_BASE + 16,  /**< Scan request report.                            \n See @ref ble_gap_evt_scan_req_report_t. */
-  BLE_GAP_EVT_PHY_UPDATE_REQUEST          = BLE_GAP_EVT_BASE + 17,  /**< PHY Update Request.                             \n Reply with @ref sd_ble_gap_phy_update. \n See @ref ble_gap_evt_phy_update_request_t. */
-  BLE_GAP_EVT_PHY_UPDATE                  = BLE_GAP_EVT_BASE + 18,  /**< PHY Update Procedure is complete.               \n See @ref ble_gap_evt_phy_update_t.           */
-  BLE_GAP_EVT_DATA_LENGTH_UPDATE_REQUEST = BLE_GAP_EVT_BASE + 19,   /**< Data Length Update Request.                     \n Reply with @ref sd_ble_gap_data_length_update.\n See @ref ble_gap_evt_data_length_update_request_t. */
-  BLE_GAP_EVT_DATA_LENGTH_UPDATE         = BLE_GAP_EVT_BASE + 20,   /**< LL Data Channel PDU payload length updated.     \n See @ref ble_gap_evt_data_length_update_t. */
-  BLE_GAP_EVT_QOS_CHANNEL_SURVEY_REPORT  = BLE_GAP_EVT_BASE + 21,   /**< Channel survey report.                          \n See @ref ble_gap_evt_qos_channel_survey_report_t. */
-  BLE_GAP_EVT_ADV_SET_TERMINATED         = BLE_GAP_EVT_BASE + 22,   /**< Advertising set terminated.                     \n See @ref ble_gap_evt_adv_set_terminated_t. */
-};
-
-/**@brief GAP Option IDs.
- * IDs that uniquely identify a GAP option.
- */
-enum BLE_GAP_OPTS
-{
-  BLE_GAP_OPT_CH_MAP                 = BLE_GAP_OPT_BASE,       /**< Channel Map. @ref ble_gap_opt_ch_map_t  */
-  BLE_GAP_OPT_LOCAL_CONN_LATENCY     = BLE_GAP_OPT_BASE + 1,   /**< Local connection latency. @ref ble_gap_opt_local_conn_latency_t */
-  BLE_GAP_OPT_PASSKEY                = BLE_GAP_OPT_BASE + 2,   /**< Set passkey. @ref ble_gap_opt_passkey_t */
-  BLE_GAP_OPT_COMPAT_MODE_1          = BLE_GAP_OPT_BASE + 3,   /**< Compatibility mode. @ref ble_gap_opt_compat_mode_1_t */
-  BLE_GAP_OPT_AUTH_PAYLOAD_TIMEOUT   = BLE_GAP_OPT_BASE + 4,   /**< Set Authenticated payload timeout. @ref ble_gap_opt_auth_payload_timeout_t */
-  BLE_GAP_OPT_SLAVE_LATENCY_DISABLE  = BLE_GAP_OPT_BASE + 5,   /**< Disable slave latency. @ref ble_gap_opt_slave_latency_disable_t */
-};
-
-/**@brief GAP Configuration IDs.
- *
- * IDs that uniquely identify a GAP configuration.
- */
-enum BLE_GAP_CFGS
-{
-  BLE_GAP_CFG_ROLE_COUNT    = BLE_GAP_CFG_BASE,     /**< Role count configuration.  */
-  BLE_GAP_CFG_DEVICE_NAME   = BLE_GAP_CFG_BASE + 1, /**< Device name configuration. */
-};
-
-/**@brief GAP TX Power roles.
- */
-enum BLE_GAP_TX_POWER_ROLES
-{
-  BLE_GAP_TX_POWER_ROLE_ADV       = 1,           /**< Advertiser role. */
-  BLE_GAP_TX_POWER_ROLE_SCAN_INIT = 2,           /**< Scanner and initiator role. */
-  BLE_GAP_TX_POWER_ROLE_CONN      = 3,           /**< Connection role. */
-};
-
-/** @} */
-
-/**@addtogroup BLE_GAP_DEFINES Defines
- * @{ */
-
-/**@defgroup BLE_ERRORS_GAP SVC return values specific to GAP
- * @{ */
-#define BLE_ERROR_GAP_UUID_LIST_MISMATCH            (NRF_GAP_ERR_BASE + 0x000)  /**< UUID list does not contain an integral number of UUIDs. */
-#define BLE_ERROR_GAP_DISCOVERABLE_WITH_WHITELIST   (NRF_GAP_ERR_BASE + 0x001)  /**< Use of Whitelist not permitted with discoverable advertising. */
-#define BLE_ERROR_GAP_INVALID_BLE_ADDR              (NRF_GAP_ERR_BASE + 0x002)  /**< The upper two bits of the address do not correspond to the specified address type. */
-#define BLE_ERROR_GAP_WHITELIST_IN_USE              (NRF_GAP_ERR_BASE + 0x003)  /**< Attempt to modify the whitelist while already in use by another operation. */
-#define BLE_ERROR_GAP_DEVICE_IDENTITIES_IN_USE      (NRF_GAP_ERR_BASE + 0x004)  /**< Attempt to modify the device identity list while already in use by another operation. */
-#define BLE_ERROR_GAP_DEVICE_IDENTITIES_DUPLICATE   (NRF_GAP_ERR_BASE + 0x005)  /**< The device identity list contains entries with duplicate identity addresses. */
-/**@} */
-
-
-/**@defgroup BLE_GAP_ROLES GAP Roles
- * @{ */
-#define BLE_GAP_ROLE_INVALID     0x0            /**< Invalid Role. */
-#define BLE_GAP_ROLE_PERIPH      0x1            /**< Peripheral Role. */
-#define BLE_GAP_ROLE_CENTRAL     0x2            /**< Central Role. */
-/**@} */
-
-
-/**@defgroup BLE_GAP_TIMEOUT_SOURCES GAP Timeout sources
- * @{ */
-#define BLE_GAP_TIMEOUT_SRC_SCAN                       0x01 /**< Scanning timeout. */
-#define BLE_GAP_TIMEOUT_SRC_CONN                       0x02 /**< Connection timeout. */
-#define BLE_GAP_TIMEOUT_SRC_AUTH_PAYLOAD               0x03 /**< Authenticated payload timeout. */
-/**@} */
-
-
-/**@defgroup BLE_GAP_ADDR_TYPES GAP Address types
- * @{ */
-#define BLE_GAP_ADDR_TYPE_PUBLIC                        0x00 /**< Public (identity) address.*/
-#define BLE_GAP_ADDR_TYPE_RANDOM_STATIC                 0x01 /**< Random static (identity) address. */
-#define BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE     0x02 /**< Random private resolvable address. */
-#define BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE 0x03 /**< Random private non-resolvable address. */
-#define BLE_GAP_ADDR_TYPE_ANONYMOUS                     0x7F /**< An advertiser may advertise without its address.
-                                                                  This type of advertising is called anonymous. */
-/**@} */
-
-
-/**@brief The default interval in seconds at which a private address is refreshed.  */
-#define BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S (900) /* 15 minutes. */
-/**@brief The maximum interval in seconds at which a private address can be refreshed.  */
-#define BLE_GAP_MAX_PRIVATE_ADDR_CYCLE_INTERVAL_S     (41400) /* 11 hours 30 minutes. */
-
-
-/** @brief BLE address length. */
-#define BLE_GAP_ADDR_LEN (6)
-
-/**@defgroup BLE_GAP_PRIVACY_MODES Privacy modes
- * @{ */
-#define BLE_GAP_PRIVACY_MODE_OFF                       0x00 /**< Device will send and accept its identity address for its own address. */
-#define BLE_GAP_PRIVACY_MODE_DEVICE_PRIVACY            0x01 /**< Device will send and accept only private addresses for its own address. */
-#define BLE_GAP_PRIVACY_MODE_NETWORK_PRIVACY           0x02 /**< Device will send and accept only private addresses for its own address,
-                                                                 and will not accept a peer using identity address as sender address when
-                                                                 the peer IRK is exchanged, non-zero and added to the identity list. */
-/**@} */
-
-/** @brief Invalid power level. */
-#define BLE_GAP_POWER_LEVEL_INVALID     127
-
-/** @brief Advertising set handle not set. */
-#define BLE_GAP_ADV_SET_HANDLE_NOT_SET (0xFF)
-
-/** @brief The default number of advertising sets. */
-#define BLE_GAP_ADV_SET_COUNT_DEFAULT   (1)
-
-/** @brief The maximum number of advertising sets supported by this SoftDevice. */
-#define BLE_GAP_ADV_SET_COUNT_MAX       (1)
-
-/**@defgroup BLE_GAP_ADV_SET_DATA_SIZES Advertising data sizes.
- * @{ */
-#define BLE_GAP_ADV_SET_DATA_SIZE_MAX                    (31)   /**< Maximum data length for an advertising set.
-                                                                     If more advertising data is required, use extended advertising instead. */
-#define BLE_GAP_ADV_SET_DATA_SIZE_EXTENDED_MAX_SUPPORTED (255)  /**< Maximum supported data length for an extended advertising set. */
-
-#define BLE_GAP_ADV_SET_DATA_SIZE_EXTENDED_CONNECTABLE_MAX_SUPPORTED (238) /**< Maximum supported data length for an extended connectable advertising set. */
-/**@}. */
-
-/** @brief Set ID not available in advertising report. */
-#define BLE_GAP_ADV_REPORT_SET_ID_NOT_AVAILABLE                    0xFF
-
-/**@defgroup BLE_GAP_EVT_ADV_SET_TERMINATED_REASON GAP Advertising Set Terminated reasons
- * @{ */
-#define BLE_GAP_EVT_ADV_SET_TERMINATED_REASON_TIMEOUT              0x01  /**< Timeout value reached. */
-#define BLE_GAP_EVT_ADV_SET_TERMINATED_REASON_LIMIT_REACHED        0x02  /**< @ref ble_gap_adv_params_t::max_adv_evts was reached. */
-/**@} */
-
-/**@defgroup BLE_GAP_AD_TYPE_DEFINITIONS GAP Advertising and Scan Response Data format
- * @note Found at https://www.bluetooth.org/Technical/AssignedNumbers/generic_access_profile.htm
- * @{ */
-#define BLE_GAP_AD_TYPE_FLAGS                               0x01 /**< Flags for discoverability. */
-#define BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_MORE_AVAILABLE   0x02 /**< Partial list of 16 bit service UUIDs. */
-#define BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_COMPLETE         0x03 /**< Complete list of 16 bit service UUIDs. */
-#define BLE_GAP_AD_TYPE_32BIT_SERVICE_UUID_MORE_AVAILABLE   0x04 /**< Partial list of 32 bit service UUIDs. */
-#define BLE_GAP_AD_TYPE_32BIT_SERVICE_UUID_COMPLETE         0x05 /**< Complete list of 32 bit service UUIDs. */
-#define BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_MORE_AVAILABLE  0x06 /**< Partial list of 128 bit service UUIDs. */
-#define BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_COMPLETE        0x07 /**< Complete list of 128 bit service UUIDs. */
-#define BLE_GAP_AD_TYPE_SHORT_LOCAL_NAME                    0x08 /**< Short local device name. */
-#define BLE_GAP_AD_TYPE_COMPLETE_LOCAL_NAME                 0x09 /**< Complete local device name. */
-#define BLE_GAP_AD_TYPE_TX_POWER_LEVEL                      0x0A /**< Transmit power level. */
-#define BLE_GAP_AD_TYPE_CLASS_OF_DEVICE                     0x0D /**< Class of device. */
-#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_HASH_C               0x0E /**< Simple Pairing Hash C. */
-#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_RANDOMIZER_R         0x0F /**< Simple Pairing Randomizer R. */
-#define BLE_GAP_AD_TYPE_SECURITY_MANAGER_TK_VALUE           0x10 /**< Security Manager TK Value. */
-#define BLE_GAP_AD_TYPE_SECURITY_MANAGER_OOB_FLAGS          0x11 /**< Security Manager Out Of Band Flags. */
-#define BLE_GAP_AD_TYPE_SLAVE_CONNECTION_INTERVAL_RANGE     0x12 /**< Slave Connection Interval Range. */
-#define BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_16BIT       0x14 /**< List of 16-bit Service Solicitation UUIDs. */
-#define BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_128BIT      0x15 /**< List of 128-bit Service Solicitation UUIDs. */
-#define BLE_GAP_AD_TYPE_SERVICE_DATA                        0x16 /**< Service Data - 16-bit UUID. */
-#define BLE_GAP_AD_TYPE_PUBLIC_TARGET_ADDRESS               0x17 /**< Public Target Address. */
-#define BLE_GAP_AD_TYPE_RANDOM_TARGET_ADDRESS               0x18 /**< Random Target Address. */
-#define BLE_GAP_AD_TYPE_APPEARANCE                          0x19 /**< Appearance. */
-#define BLE_GAP_AD_TYPE_ADVERTISING_INTERVAL                0x1A /**< Advertising Interval. */
-#define BLE_GAP_AD_TYPE_LE_BLUETOOTH_DEVICE_ADDRESS         0x1B /**< LE Bluetooth Device Address. */
-#define BLE_GAP_AD_TYPE_LE_ROLE                             0x1C /**< LE Role. */
-#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_HASH_C256            0x1D /**< Simple Pairing Hash C-256. */
-#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_RANDOMIZER_R256      0x1E /**< Simple Pairing Randomizer R-256. */
-#define BLE_GAP_AD_TYPE_SERVICE_DATA_32BIT_UUID             0x20 /**< Service Data - 32-bit UUID. */
-#define BLE_GAP_AD_TYPE_SERVICE_DATA_128BIT_UUID            0x21 /**< Service Data - 128-bit UUID. */
-#define BLE_GAP_AD_TYPE_LESC_CONFIRMATION_VALUE             0x22 /**< LE Secure Connections Confirmation Value */
-#define BLE_GAP_AD_TYPE_LESC_RANDOM_VALUE                   0x23 /**< LE Secure Connections Random Value */
-#define BLE_GAP_AD_TYPE_URI                                 0x24 /**< URI */
-#define BLE_GAP_AD_TYPE_3D_INFORMATION_DATA                 0x3D /**< 3D Information Data. */
-#define BLE_GAP_AD_TYPE_MANUFACTURER_SPECIFIC_DATA          0xFF /**< Manufacturer Specific Data. */
-/**@} */
-
-
-/**@defgroup BLE_GAP_ADV_FLAGS GAP Advertisement Flags
- * @{ */
-#define BLE_GAP_ADV_FLAG_LE_LIMITED_DISC_MODE         (0x01)   /**< LE Limited Discoverable Mode. */
-#define BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE         (0x02)   /**< LE General Discoverable Mode. */
-#define BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED         (0x04)   /**< BR/EDR not supported. */
-#define BLE_GAP_ADV_FLAG_LE_BR_EDR_CONTROLLER         (0x08)   /**< Simultaneous LE and BR/EDR, Controller. */
-#define BLE_GAP_ADV_FLAG_LE_BR_EDR_HOST               (0x10)   /**< Simultaneous LE and BR/EDR, Host. */
-#define BLE_GAP_ADV_FLAGS_LE_ONLY_LIMITED_DISC_MODE   (BLE_GAP_ADV_FLAG_LE_LIMITED_DISC_MODE | BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED)   /**< LE Limited Discoverable Mode, BR/EDR not supported. */
-#define BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE   (BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE | BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED)   /**< LE General Discoverable Mode, BR/EDR not supported. */
-/**@} */
-
-
-/**@defgroup BLE_GAP_ADV_INTERVALS GAP Advertising interval max and min
- * @{ */
-#define BLE_GAP_ADV_INTERVAL_MIN        0x000020 /**< Minimum Advertising interval in 625 us units, i.e. 20 ms. */
-#define BLE_GAP_ADV_INTERVAL_MAX        0x004000 /**< Maximum Advertising interval in 625 us units, i.e. 10.24 s. */
- /**@}  */
-
-
-/**@defgroup BLE_GAP_SCAN_INTERVALS GAP Scan interval max and min
- * @{ */
-#define BLE_GAP_SCAN_INTERVAL_MIN       0x0004 /**< Minimum Scan interval in 625 us units, i.e. 2.5 ms. */
-#define BLE_GAP_SCAN_INTERVAL_MAX       0xFFFF /**< Maximum Scan interval in 625 us units, i.e. 40,959.375 s. */
- /** @}  */
-
-
-/**@defgroup BLE_GAP_SCAN_WINDOW GAP Scan window max and min
- * @{ */
-#define BLE_GAP_SCAN_WINDOW_MIN         0x0004 /**< Minimum Scan window in 625 us units, i.e. 2.5 ms. */
-#define BLE_GAP_SCAN_WINDOW_MAX         0xFFFF /**< Maximum Scan window in 625 us units, i.e. 40,959.375 s. */
- /** @}  */
-
-
-/**@defgroup BLE_GAP_SCAN_TIMEOUT GAP Scan timeout max and min
- * @{ */
-#define BLE_GAP_SCAN_TIMEOUT_MIN        0x0001 /**< Minimum Scan timeout in 10 ms units, i.e 10 ms. */
-#define BLE_GAP_SCAN_TIMEOUT_UNLIMITED  0x0000 /**< Continue to scan forever. */
- /** @}  */
-
-/**@defgroup BLE_GAP_SCAN_BUFFER_SIZE GAP Minimum scanner buffer size
- *
- * Scan buffers are used for storing advertising data received from an advertiser.
- * If ble_gap_scan_params_t::extended is set to 0, @ref BLE_GAP_SCAN_BUFFER_MIN is the minimum scan buffer length.
- * else the minimum scan buffer size is @ref BLE_GAP_SCAN_BUFFER_EXTENDED_MIN.
- * @{ */
-#define BLE_GAP_SCAN_BUFFER_MIN                    (31)                             /**< Minimum data length for an
-                                                                                         advertising set. */
-#define BLE_GAP_SCAN_BUFFER_MAX                    (31)                             /**< Maximum data length for an
-                                                                                         advertising set. */
-#define BLE_GAP_SCAN_BUFFER_EXTENDED_MIN           (255)                            /**< Minimum data length for an
-                                                                                         extended advertising set. */
-#define BLE_GAP_SCAN_BUFFER_EXTENDED_MAX           (1650)                           /**< Maximum data length for an
-                                                                                         extended advertising set. */
-#define BLE_GAP_SCAN_BUFFER_EXTENDED_MAX_SUPPORTED (255)                            /**< Maximum supported data length for
-                                                                                         an extended advertising set. */
-/** @}  */
-
-/**@defgroup BLE_GAP_ADV_TYPES GAP Advertising types
- *
- * Advertising types defined in Bluetooth Core Specification v5.0, Vol 6, Part B, Section 4.4.2.
- *
- * The maximum advertising data length is defined by @ref BLE_GAP_ADV_SET_DATA_SIZE_MAX.
- * The maximum supported data length for an extended advertiser is defined by
- * @ref BLE_GAP_ADV_SET_DATA_SIZE_EXTENDED_MAX_SUPPORTED
- * Note that some of the advertising types do not support advertising data. Non-scannable types do not support
- * scan response data.
- *
- * @{ */
-#define BLE_GAP_ADV_TYPE_CONNECTABLE_SCANNABLE_UNDIRECTED                   0x01   /**< Connectable and scannable undirected
-                                                                                        advertising events. */
-#define BLE_GAP_ADV_TYPE_CONNECTABLE_NONSCANNABLE_DIRECTED_HIGH_DUTY_CYCLE  0x02   /**< Connectable non-scannable directed advertising
-                                                                                        events. Advertising interval is less that 3.75 ms.
-                                                                                        Use this type for fast reconnections.
-                                                                                        @note Advertising data is not supported. */
-#define BLE_GAP_ADV_TYPE_CONNECTABLE_NONSCANNABLE_DIRECTED                  0x03   /**< Connectable non-scannable directed advertising
-                                                                                        events.
-                                                                                        @note Advertising data is not supported. */
-#define BLE_GAP_ADV_TYPE_NONCONNECTABLE_SCANNABLE_UNDIRECTED                0x04   /**< Non-connectable scannable undirected
-                                                                                        advertising events. */
-#define BLE_GAP_ADV_TYPE_NONCONNECTABLE_NONSCANNABLE_UNDIRECTED             0x05   /**< Non-connectable non-scannable undirected
-                                                                                        advertising events. */
-#define BLE_GAP_ADV_TYPE_EXTENDED_CONNECTABLE_NONSCANNABLE_UNDIRECTED       0x06   /**< Connectable non-scannable undirected advertising
-                                                                                        events using extended advertising PDUs. */
-#define BLE_GAP_ADV_TYPE_EXTENDED_CONNECTABLE_NONSCANNABLE_DIRECTED         0x07   /**< Connectable non-scannable directed advertising
-                                                                                        events using extended advertising PDUs. */
-#define BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_SCANNABLE_UNDIRECTED       0x08   /**< Non-connectable scannable undirected advertising
-                                                                                        events using extended advertising PDUs.
-                                                                                        @note Only scan response data is supported. */
-#define BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_SCANNABLE_DIRECTED         0x09   /**< Non-connectable scannable directed advertising
-                                                                                        events using extended advertising PDUs.
-                                                                                        @note Only scan response data is supported. */
-#define BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_NONSCANNABLE_UNDIRECTED    0x0A   /**< Non-connectable non-scannable undirected advertising
-                                                                                        events using extended advertising PDUs. */
-#define BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_NONSCANNABLE_DIRECTED      0x0B   /**< Non-connectable non-scannable directed advertising
-                                                                                        events using extended advertising PDUs. */
-/**@} */
-
-/**@defgroup BLE_GAP_ADV_FILTER_POLICIES GAP Advertising filter policies
- * @{ */
-#define BLE_GAP_ADV_FP_ANY                0x00   /**< Allow scan requests and connect requests from any device. */
-#define BLE_GAP_ADV_FP_FILTER_SCANREQ     0x01   /**< Filter scan requests with whitelist. */
-#define BLE_GAP_ADV_FP_FILTER_CONNREQ     0x02   /**< Filter connect requests with whitelist. */
-#define BLE_GAP_ADV_FP_FILTER_BOTH        0x03   /**< Filter both scan and connect requests with whitelist. */
-/**@} */
-
-/**@defgroup BLE_GAP_ADV_DATA_STATUS GAP Advertising data status
- * @{ */
-#define BLE_GAP_ADV_DATA_STATUS_COMPLETE             0x00 /**< All data in the advertising event have been received. */
-#define BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA 0x01 /**< More data to be received.
-                                                               @note This value will only be used if
-                                                               @ref ble_gap_scan_params_t::report_incomplete_evts and
-                                                               @ref ble_gap_adv_report_type_t::extended_pdu are set to true. */
-#define BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_TRUNCATED 0x02 /**< Incomplete data. Buffer size insufficient to receive more.
-                                                               @note This value will only be used if
-                                                               @ref ble_gap_adv_report_type_t::extended_pdu is set to true. */
-#define BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MISSED    0x03 /**< Failed to receive the remaining data.
-                                                               @note This value will only be used if
-                                                               @ref ble_gap_adv_report_type_t::extended_pdu is set to true. */
-/**@} */
-
-/**@defgroup BLE_GAP_SCAN_FILTER_POLICIES GAP Scanner filter policies
- * @{ */
-#define BLE_GAP_SCAN_FP_ACCEPT_ALL                      0x00  /**< Accept all advertising packets except directed advertising packets
-                                                                   not addressed to this device. */
-#define BLE_GAP_SCAN_FP_WHITELIST                       0x01  /**< Accept advertising packets from devices in the whitelist except directed
-                                                                   packets not addressed to this device. */
-#define BLE_GAP_SCAN_FP_ALL_NOT_RESOLVED_DIRECTED       0x02  /**< Accept all advertising packets specified in @ref BLE_GAP_SCAN_FP_ACCEPT_ALL.
-                                                                   In addition, accept directed advertising packets, where the advertiser's
-                                                                   address is a resolvable private address that cannot be resolved. */
-#define BLE_GAP_SCAN_FP_WHITELIST_NOT_RESOLVED_DIRECTED 0x03  /**< Accept all advertising packets specified in @ref BLE_GAP_SCAN_FP_WHITELIST.
-                                                                   In addition, accept directed advertising packets, where the advertiser's
-                                                                   address is a resolvable private address that cannot be resolved. */
-/**@} */
-
-/**@defgroup BLE_GAP_ADV_TIMEOUT_VALUES GAP Advertising timeout values in 10 ms units
- * @{ */
-#define BLE_GAP_ADV_TIMEOUT_HIGH_DUTY_MAX     (128)   /**< Maximum high duty advertising time in 10 ms units. Corresponds to 1.28 s. */
-#define BLE_GAP_ADV_TIMEOUT_LIMITED_MAX       (18000) /**< Maximum advertising time in 10 ms units corresponding to TGAP(lim_adv_timeout) = 180 s in limited discoverable mode. */
-#define BLE_GAP_ADV_TIMEOUT_GENERAL_UNLIMITED (0)     /**< Unlimited advertising in general discoverable mode.
-                                                           For high duty cycle advertising, this corresponds to @ref BLE_GAP_ADV_TIMEOUT_HIGH_DUTY_MAX. */
-/**@} */
-
-
-/**@defgroup BLE_GAP_DISC_MODES GAP Discovery modes
- * @{ */
-#define BLE_GAP_DISC_MODE_NOT_DISCOVERABLE  0x00   /**< Not discoverable discovery Mode. */
-#define BLE_GAP_DISC_MODE_LIMITED           0x01   /**< Limited Discovery Mode. */
-#define BLE_GAP_DISC_MODE_GENERAL           0x02   /**< General Discovery Mode. */
-/**@} */
-
-
-/**@defgroup BLE_GAP_IO_CAPS GAP IO Capabilities
- * @{ */
-#define BLE_GAP_IO_CAPS_DISPLAY_ONLY      0x00   /**< Display Only. */
-#define BLE_GAP_IO_CAPS_DISPLAY_YESNO     0x01   /**< Display and Yes/No entry. */
-#define BLE_GAP_IO_CAPS_KEYBOARD_ONLY     0x02   /**< Keyboard Only. */
-#define BLE_GAP_IO_CAPS_NONE              0x03   /**< No I/O capabilities. */
-#define BLE_GAP_IO_CAPS_KEYBOARD_DISPLAY  0x04   /**< Keyboard and Display. */
-/**@} */
-
-
-/**@defgroup BLE_GAP_AUTH_KEY_TYPES GAP Authentication Key Types
- * @{ */
-#define BLE_GAP_AUTH_KEY_TYPE_NONE        0x00   /**< No key (may be used to reject). */
-#define BLE_GAP_AUTH_KEY_TYPE_PASSKEY     0x01   /**< 6-digit Passkey. */
-#define BLE_GAP_AUTH_KEY_TYPE_OOB         0x02   /**< Out Of Band data. */
-/**@} */
-
-
-/**@defgroup BLE_GAP_KP_NOT_TYPES GAP Keypress Notification Types
- * @{ */
-#define BLE_GAP_KP_NOT_TYPE_PASSKEY_START       0x00   /**< Passkey entry started. */
-#define BLE_GAP_KP_NOT_TYPE_PASSKEY_DIGIT_IN    0x01   /**< Passkey digit entered. */
-#define BLE_GAP_KP_NOT_TYPE_PASSKEY_DIGIT_OUT   0x02   /**< Passkey digit erased. */
-#define BLE_GAP_KP_NOT_TYPE_PASSKEY_CLEAR       0x03   /**< Passkey cleared. */
-#define BLE_GAP_KP_NOT_TYPE_PASSKEY_END         0x04   /**< Passkey entry completed. */
-/**@} */
-
-
-/**@defgroup BLE_GAP_SEC_STATUS GAP Security status
- * @{ */
-#define BLE_GAP_SEC_STATUS_SUCCESS                0x00  /**< Procedure completed with success. */
-#define BLE_GAP_SEC_STATUS_TIMEOUT                0x01  /**< Procedure timed out. */
-#define BLE_GAP_SEC_STATUS_PDU_INVALID            0x02  /**< Invalid PDU received. */
-#define BLE_GAP_SEC_STATUS_RFU_RANGE1_BEGIN       0x03  /**< Reserved for Future Use range #1 begin. */
-#define BLE_GAP_SEC_STATUS_RFU_RANGE1_END         0x80  /**< Reserved for Future Use range #1 end. */
-#define BLE_GAP_SEC_STATUS_PASSKEY_ENTRY_FAILED   0x81  /**< Passkey entry failed (user canceled or other). */
-#define BLE_GAP_SEC_STATUS_OOB_NOT_AVAILABLE      0x82  /**< Out of Band Key not available. */
-#define BLE_GAP_SEC_STATUS_AUTH_REQ               0x83  /**< Authentication requirements not met. */
-#define BLE_GAP_SEC_STATUS_CONFIRM_VALUE          0x84  /**< Confirm value failed. */
-#define BLE_GAP_SEC_STATUS_PAIRING_NOT_SUPP       0x85  /**< Pairing not supported.  */
-#define BLE_GAP_SEC_STATUS_ENC_KEY_SIZE           0x86  /**< Encryption key size. */
-#define BLE_GAP_SEC_STATUS_SMP_CMD_UNSUPPORTED    0x87  /**< Unsupported SMP command. */
-#define BLE_GAP_SEC_STATUS_UNSPECIFIED            0x88  /**< Unspecified reason. */
-#define BLE_GAP_SEC_STATUS_REPEATED_ATTEMPTS      0x89  /**< Too little time elapsed since last attempt. */
-#define BLE_GAP_SEC_STATUS_INVALID_PARAMS         0x8A  /**< Invalid parameters. */
-#define BLE_GAP_SEC_STATUS_DHKEY_FAILURE          0x8B  /**< DHKey check failure. */
-#define BLE_GAP_SEC_STATUS_NUM_COMP_FAILURE       0x8C  /**< Numeric Comparison failure. */
-#define BLE_GAP_SEC_STATUS_BR_EDR_IN_PROG         0x8D  /**< BR/EDR pairing in progress. */
-#define BLE_GAP_SEC_STATUS_X_TRANS_KEY_DISALLOWED 0x8E  /**< BR/EDR Link Key cannot be used for LE keys. */
-#define BLE_GAP_SEC_STATUS_RFU_RANGE2_BEGIN       0x8F  /**< Reserved for Future Use range #2 begin. */
-#define BLE_GAP_SEC_STATUS_RFU_RANGE2_END         0xFF  /**< Reserved for Future Use range #2 end. */
-/**@} */
-
-
-/**@defgroup BLE_GAP_SEC_STATUS_SOURCES GAP Security status sources
- * @{ */
-#define BLE_GAP_SEC_STATUS_SOURCE_LOCAL           0x00  /**< Local failure. */
-#define BLE_GAP_SEC_STATUS_SOURCE_REMOTE          0x01  /**< Remote failure. */
-/**@} */
-
-
-/**@defgroup BLE_GAP_CP_LIMITS GAP Connection Parameters Limits
- * @{ */
-#define BLE_GAP_CP_MIN_CONN_INTVL_NONE           0xFFFF  /**< No new minimum connection interval specified in connect parameters. */
-#define BLE_GAP_CP_MIN_CONN_INTVL_MIN            0x0006  /**< Lowest minimum connection interval permitted, in units of 1.25 ms, i.e. 7.5 ms. */
-#define BLE_GAP_CP_MIN_CONN_INTVL_MAX            0x0C80  /**< Highest minimum connection interval permitted, in units of 1.25 ms, i.e. 4 s. */
-#define BLE_GAP_CP_MAX_CONN_INTVL_NONE           0xFFFF  /**< No new maximum connection interval specified in connect parameters. */
-#define BLE_GAP_CP_MAX_CONN_INTVL_MIN            0x0006  /**< Lowest maximum connection interval permitted, in units of 1.25 ms, i.e. 7.5 ms. */
-#define BLE_GAP_CP_MAX_CONN_INTVL_MAX            0x0C80  /**< Highest maximum connection interval permitted, in units of 1.25 ms, i.e. 4 s. */
-#define BLE_GAP_CP_SLAVE_LATENCY_MAX             0x01F3  /**< Highest slave latency permitted, in connection events. */
-#define BLE_GAP_CP_CONN_SUP_TIMEOUT_NONE         0xFFFF  /**< No new supervision timeout specified in connect parameters. */
-#define BLE_GAP_CP_CONN_SUP_TIMEOUT_MIN          0x000A  /**< Lowest supervision timeout permitted, in units of 10 ms, i.e. 100 ms. */
-#define BLE_GAP_CP_CONN_SUP_TIMEOUT_MAX          0x0C80  /**< Highest supervision timeout permitted, in units of 10 ms, i.e. 32 s. */
-/**@} */
-
-
-/**@defgroup BLE_GAP_DEVNAME GAP device name defines.
- * @{ */
-#define BLE_GAP_DEVNAME_DEFAULT                  "nRF5x" /**< Default device name value. */
-#define BLE_GAP_DEVNAME_DEFAULT_LEN              31      /**< Default number of octets in device name. */
-#define BLE_GAP_DEVNAME_MAX_LEN                  248     /**< Maximum number of octets in device name. */
-/**@} */
-
-
-/**@brief Disable RSSI events for connections */
-#define BLE_GAP_RSSI_THRESHOLD_INVALID 0xFF
-
-/**@defgroup BLE_GAP_PHYS GAP PHYs
- * @{ */
-#define BLE_GAP_PHY_AUTO                         0x00    /**< Automatic PHY selection. Refer @ref sd_ble_gap_phy_update for more information.*/
-#define BLE_GAP_PHY_1MBPS                        0x01    /**< 1 Mbps PHY. */
-#define BLE_GAP_PHY_2MBPS                        0x02    /**< 2 Mbps PHY. */
-#define BLE_GAP_PHY_CODED                        0x04    /**< Coded PHY. */
-#define BLE_GAP_PHY_NOT_SET                      0xFF    /**< PHY is not configured. */
-
-/**@brief Supported PHYs in connections, for scanning, and for advertising. */
-#define BLE_GAP_PHYS_SUPPORTED  (BLE_GAP_PHY_1MBPS | BLE_GAP_PHY_2MBPS | BLE_GAP_PHY_CODED) /**< All PHYs are supported. */
-
-/**@} */
-
-/**@defgroup BLE_GAP_CONN_SEC_MODE_SET_MACROS GAP attribute security requirement setters
- *
- * See @ref ble_gap_conn_sec_mode_t.
- * @{ */
-/**@brief Set sec_mode pointed to by ptr to have no access rights.*/
-#define BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(ptr)          do {(ptr)->sm = 0; (ptr)->lv = 0;} while(0)
-/**@brief Set sec_mode pointed to by ptr to require no protection, open link.*/
-#define BLE_GAP_CONN_SEC_MODE_SET_OPEN(ptr)               do {(ptr)->sm = 1; (ptr)->lv = 1;} while(0)
-/**@brief Set sec_mode pointed to by ptr to require encryption, but no MITM protection.*/
-#define BLE_GAP_CONN_SEC_MODE_SET_ENC_NO_MITM(ptr)        do {(ptr)->sm = 1; (ptr)->lv = 2;} while(0)
-/**@brief Set sec_mode pointed to by ptr to require encryption and MITM protection.*/
-#define BLE_GAP_CONN_SEC_MODE_SET_ENC_WITH_MITM(ptr)      do {(ptr)->sm = 1; (ptr)->lv = 3;} while(0)
-/**@brief Set sec_mode pointed to by ptr to require LESC encryption and MITM protection.*/
-#define BLE_GAP_CONN_SEC_MODE_SET_LESC_ENC_WITH_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 4;} while(0)
-/**@brief Set sec_mode pointed to by ptr to require signing or encryption, no MITM protection needed.*/
-#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_NO_MITM(ptr)     do {(ptr)->sm = 2; (ptr)->lv = 1;} while(0)
-/**@brief Set sec_mode pointed to by ptr to require signing or encryption with MITM protection.*/
-#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_WITH_MITM(ptr)   do {(ptr)->sm = 2; (ptr)->lv = 2;} while(0)
-/**@} */
-
-
-/**@brief GAP Security Random Number Length. */
-#define BLE_GAP_SEC_RAND_LEN 8
-
-
-/**@brief GAP Security Key Length. */
-#define BLE_GAP_SEC_KEY_LEN 16
-
-
-/**@brief GAP LE Secure Connections Elliptic Curve Diffie-Hellman P-256 Public Key Length. */
-#define BLE_GAP_LESC_P256_PK_LEN 64
-
-
-/**@brief GAP LE Secure Connections Elliptic Curve Diffie-Hellman DHKey Length. */
-#define BLE_GAP_LESC_DHKEY_LEN   32
-
-
-/**@brief GAP Passkey Length. */
-#define BLE_GAP_PASSKEY_LEN 6
-
-
-/**@brief Maximum amount of addresses in the whitelist. */
-#define BLE_GAP_WHITELIST_ADDR_MAX_COUNT (8)
-
-
-/**@brief Maximum amount of identities in the device identities list. */
-#define BLE_GAP_DEVICE_IDENTITIES_MAX_COUNT (8)
-
-
-/**@brief Default connection count for a configuration. */
-#define BLE_GAP_CONN_COUNT_DEFAULT (1)
-
-
-/**@defgroup BLE_GAP_EVENT_LENGTH GAP event length defines.
- * @{ */
-#define BLE_GAP_EVENT_LENGTH_MIN            (2)  /**< Minimum event length, in 1.25 ms units. */
-#define BLE_GAP_EVENT_LENGTH_CODED_PHY_MIN  (6)  /**< The shortest event length in 1.25 ms units supporting LE Coded PHY. */
-#define BLE_GAP_EVENT_LENGTH_DEFAULT        (3)  /**< Default event length, in 1.25 ms units. */
-/**@} */
-
-
-/**@defgroup BLE_GAP_ROLE_COUNT GAP concurrent connection count defines.
- * @{ */
-#define BLE_GAP_ROLE_COUNT_PERIPH_DEFAULT      (1)   /**< Default maximum number of connections concurrently acting as peripherals. */
-#define BLE_GAP_ROLE_COUNT_CENTRAL_DEFAULT     (3)   /**< Default maximum number of connections concurrently acting as centrals. */
-#define BLE_GAP_ROLE_COUNT_CENTRAL_SEC_DEFAULT (1)   /**< Default number of SMP instances shared between all connections acting as centrals. */
-#define BLE_GAP_ROLE_COUNT_COMBINED_MAX        (20)  /**< Maximum supported number of concurrent connections in the peripheral and central roles combined. */
-
-/**@} */
-
-/**@brief Automatic data length parameter. */
-#define BLE_GAP_DATA_LENGTH_AUTO 0
-
-/**@defgroup BLE_GAP_AUTH_PAYLOAD_TIMEOUT Authenticated payload timeout defines.
-  * @{ */
-#define BLE_GAP_AUTH_PAYLOAD_TIMEOUT_MAX (48000) /**< Maximum authenticated payload timeout in 10 ms units, i.e. 8 minutes. */
-#define BLE_GAP_AUTH_PAYLOAD_TIMEOUT_MIN (1)     /**< Minimum authenticated payload timeout in 10 ms units, i.e. 10 ms. */
-/**@} */
-
-/**@defgroup GAP_SEC_MODES GAP Security Modes
- * @{ */
-#define BLE_GAP_SEC_MODE 0x00 /**< No key (may be used to reject). */
-/**@} */
-
-/**@brief The total number of channels in Bluetooth Low Energy. */
-#define BLE_GAP_CHANNEL_COUNT      (40)
-
-/**@defgroup BLE_GAP_QOS_CHANNEL_SURVEY_INTERVALS Quality of Service (QoS) Channel survey interval defines
- * @{ */
-#define BLE_GAP_QOS_CHANNEL_SURVEY_INTERVAL_CONTINUOUS  (0)       /**< Continuous channel survey. */
-#define BLE_GAP_QOS_CHANNEL_SURVEY_INTERVAL_MIN_US      (7500)    /**< Minimum channel survey interval in microseconds (7.5 ms). */
-#define BLE_GAP_QOS_CHANNEL_SURVEY_INTERVAL_MAX_US      (4000000) /**< Maximum channel survey interval in microseconds (4 s). */
- /**@}  */
-
-/** @} */
-
-
-/**@addtogroup BLE_GAP_STRUCTURES Structures
- * @{ */
-
-/**@brief Advertising event properties. */
-typedef struct
-{
-  uint8_t type;                 /**< Advertising type. See @ref BLE_GAP_ADV_TYPES. */
-  uint8_t anonymous        : 1; /**< Omit advertiser's address from all PDUs.
-                                     @note Anonymous advertising is only available for
-                                     @ref BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_NONSCANNABLE_UNDIRECTED and
-                                     @ref BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_NONSCANNABLE_DIRECTED. */
-  uint8_t include_tx_power : 1; /**< This feature is not supported on this SoftDevice. */
-} ble_gap_adv_properties_t;
-
-
-/**@brief Advertising report type. */
-typedef struct
-{
-  uint16_t connectable   : 1; /**< Connectable advertising event type. */
-  uint16_t scannable     : 1; /**< Scannable advertising event type. */
-  uint16_t directed      : 1; /**< Directed advertising event type. */
-  uint16_t scan_response : 1; /**< Received a scan response. */
-  uint16_t extended_pdu  : 1; /**< Received an extended advertising set. */
-  uint16_t status        : 2; /**< Data status. See @ref BLE_GAP_ADV_DATA_STATUS. */
-  uint16_t reserved      : 9; /**< Reserved for future use. */
-} ble_gap_adv_report_type_t;
-
-/**@brief Advertising Auxiliary Pointer. */
-typedef struct
-{
-  uint16_t  aux_offset;   /**< Time offset from the beginning of advertising packet to the auxiliary packet in 100 us units. */
-  uint8_t   aux_phy;      /**< Indicates the PHY on which the auxiliary advertising packet is sent. See @ref BLE_GAP_PHYS. */
-} ble_gap_aux_pointer_t;
-
-/**@brief Bluetooth Low Energy address. */
-typedef struct
-{
-  uint8_t addr_id_peer : 1;       /**< Only valid for peer addresses.
-                                       This bit is set by the SoftDevice to indicate whether the address has been resolved from
-                                       a Resolvable Private Address (when the peer is using privacy).
-                                       If set to 1, @ref addr and @ref addr_type refer to the identity address of the resolved address.
-
-                                       This bit is ignored when a variable of type @ref ble_gap_addr_t is used as input to API functions. */
-  uint8_t addr_type    : 7;       /**< See @ref BLE_GAP_ADDR_TYPES. */
-  uint8_t addr[BLE_GAP_ADDR_LEN]; /**< 48-bit address, LSB format.
-                                       @ref addr is not used if @ref addr_type is @ref BLE_GAP_ADDR_TYPE_ANONYMOUS. */
-} ble_gap_addr_t;
-
-
-/**@brief GAP connection parameters.
- *
- * @note  When ble_conn_params_t is received in an event, both min_conn_interval and
- *        max_conn_interval will be equal to the connection interval set by the central.
- *
- * @note  If both conn_sup_timeout and max_conn_interval are specified, then the following constraint applies:
- *        conn_sup_timeout * 4 > (1 + slave_latency) * max_conn_interval
- *        that corresponds to the following Bluetooth Spec requirement:
- *        The Supervision_Timeout in milliseconds shall be larger than
- *        (1 + Conn_Latency) * Conn_Interval_Max * 2, where Conn_Interval_Max is given in milliseconds.
- */
-typedef struct
-{
-  uint16_t min_conn_interval;         /**< Minimum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/
-  uint16_t max_conn_interval;         /**< Maximum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/
-  uint16_t slave_latency;             /**< Slave Latency in number of connection events, see @ref BLE_GAP_CP_LIMITS.*/
-  uint16_t conn_sup_timeout;          /**< Connection Supervision Timeout in 10 ms units, see @ref BLE_GAP_CP_LIMITS.*/
-} ble_gap_conn_params_t;
-
-
-/**@brief GAP connection security modes.
- *
- * Security Mode 0 Level 0: No access permissions at all (this level is not defined by the Bluetooth Core specification).\n
- * Security Mode 1 Level 1: No security is needed (aka open link).\n
- * Security Mode 1 Level 2: Encrypted link required, MITM protection not necessary.\n
- * Security Mode 1 Level 3: MITM protected encrypted link required.\n
- * Security Mode 1 Level 4: LESC MITM protected encrypted link using a 128-bit strength encryption key required.\n
- * Security Mode 2 Level 1: Signing or encryption required, MITM protection not necessary.\n
- * Security Mode 2 Level 2: MITM protected signing required, unless link is MITM protected encrypted.\n
- */
-typedef struct
-{
-  uint8_t sm : 4;                     /**< Security Mode (1 or 2), 0 for no permissions at all. */
-  uint8_t lv : 4;                     /**< Level (1, 2, 3 or 4), 0 for no permissions at all. */
-
-} ble_gap_conn_sec_mode_t;
-
-
-/**@brief GAP connection security status.*/
-typedef struct
-{
-  ble_gap_conn_sec_mode_t sec_mode;           /**< Currently active security mode for this connection.*/
-  uint8_t                 encr_key_size;      /**< Length of currently active encryption key, 7 to 16 octets (only applicable for bonding procedures). */
-} ble_gap_conn_sec_t;
-
-/**@brief Identity Resolving Key. */
-typedef struct
-{
-  uint8_t irk[BLE_GAP_SEC_KEY_LEN];   /**< Array containing IRK. */
-} ble_gap_irk_t;
-
-
-/**@brief Channel mask (40 bits).
- * Every channel is represented with a bit positioned as per channel index defined in Bluetooth Core Specification v5.0,
- * Vol 6, Part B, Section 1.4.1. The LSB contained in array element 0 represents channel index 0, and bit 39 represents
- * channel index 39. If a bit is set to 1, the channel is not used.
- */
-typedef uint8_t ble_gap_ch_mask_t[5];
-
-
-/**@brief GAP advertising parameters. */
-typedef struct
-{
-  ble_gap_adv_properties_t properties;              /**< The properties of the advertising events. */
-  ble_gap_addr_t const    *p_peer_addr;             /**< Address of a known peer.
-                                                         @note ble_gap_addr_t::addr_type cannot be
-                                                               @ref BLE_GAP_ADDR_TYPE_ANONYMOUS.
-                                                         - When privacy is enabled and the local device uses
-                                                           @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE addresses,
-                                                           the device identity list is searched for a matching entry. If
-                                                           the local IRK for that device identity is set, the local IRK
-                                                           for that device will be used to generate the advertiser address
-                                                           field in the advertising packet.
-                                                         - If @ref ble_gap_adv_properties_t::type is directed, this must be
-                                                           set to the targeted scanner or initiator. If the peer address is
-                                                           in the device identity list, the peer IRK for that device will be
-                                                           used to generate @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE
-                                                           target addresses used in the advertising event PDUs. */
-  uint32_t                 interval;                /**< Advertising interval in 625 us units. @sa BLE_GAP_ADV_INTERVALS.
-                                                         @note If @ref ble_gap_adv_properties_t::type is set to
-                                                               @ref BLE_GAP_ADV_TYPE_CONNECTABLE_NONSCANNABLE_DIRECTED_HIGH_DUTY_CYCLE
-                                                               advertising, this parameter is ignored. */
-  uint16_t                 duration;                /**< Advertising duration in 10 ms units. When timeout is reached,
-                                                         an event of type @ref BLE_GAP_EVT_ADV_SET_TERMINATED is raised.
-                                                         @sa BLE_GAP_ADV_TIMEOUT_VALUES.
-                                                         @note The SoftDevice will always complete at least one advertising
-                                                               event even if the duration is set too low. */
-  uint8_t                  max_adv_evts;            /**< Maximum advertising events that shall be sent prior to disabling
-                                                         advertising. Setting the value to 0 disables the limitation. When
-                                                         the count of advertising events specified by this parameter
-                                                         (if not 0) is reached, advertising will be automatically stopped
-                                                         and an event of type @ref BLE_GAP_EVT_ADV_SET_TERMINATED is raised
-                                                         @note If @ref ble_gap_adv_properties_t::type is set to
-                                                               @ref BLE_GAP_ADV_TYPE_CONNECTABLE_NONSCANNABLE_DIRECTED_HIGH_DUTY_CYCLE,
-                                                               this parameter is ignored. */
-  ble_gap_ch_mask_t        channel_mask;            /**< Channel mask for primary and secondary advertising channels.
-                                                         At least one of the primary channels, that is channel index 37-39, must be used.
-                                                         Masking away secondary advertising channels is not supported. */
-  uint8_t                  filter_policy;           /**< Filter Policy. @sa BLE_GAP_ADV_FILTER_POLICIES. */
-  uint8_t                  primary_phy;             /**< Indicates the PHY on which the primary advertising channel packets
-                                                         are transmitted. If set to @ref BLE_GAP_PHY_AUTO, @ref BLE_GAP_PHY_1MBPS
-                                                         will be used.
-                                                         Valid values are @ref BLE_GAP_PHY_1MBPS and @ref BLE_GAP_PHY_CODED.
-                                                         @note The primary_phy shall indicate @ref BLE_GAP_PHY_1MBPS if
-                                                               @ref ble_gap_adv_properties_t::type is not an extended advertising type. */
-  uint8_t                  secondary_phy;           /**< Indicates the PHY on which the secondary advertising channel packets
-                                                         are transmitted.
-                                                         If set to @ref BLE_GAP_PHY_AUTO, @ref BLE_GAP_PHY_1MBPS will be used.
-                                                         Valid values are
-                                                         @ref BLE_GAP_PHY_1MBPS, @ref BLE_GAP_PHY_2MBPS, and @ref BLE_GAP_PHY_CODED.
-                                                         If @ref ble_gap_adv_properties_t::type is an extended advertising type
-                                                         and connectable, this is the PHY that will be used to establish a
-                                                         connection and send AUX_ADV_IND packets on.
-                                                         @note This parameter will be ignored when
-                                                               @ref ble_gap_adv_properties_t::type is not an extended advertising type. */
-  uint8_t                  set_id:4;                /**< The advertising set identifier distinguishes this advertising set from other
-                                                         advertising sets transmitted by this and other devices.
-                                                         @note This parameter will be ignored when
-                                                               @ref ble_gap_adv_properties_t::type is not an extended advertising type. */
-  uint8_t                  scan_req_notification:1; /**< Enable scan request notifications for this advertising set. When a
-                                                         scan request is received and the scanner address is allowed
-                                                         by the filter policy, @ref BLE_GAP_EVT_SCAN_REQ_REPORT is raised.
-                                                         @note This parameter will be ignored when
-                                                               @ref ble_gap_adv_properties_t::type is a non-scannable
-                                                               advertising type. */
-} ble_gap_adv_params_t;
-
-
-/**@brief GAP advertising data buffers.
- *
- * The application must provide the buffers for advertisement. The memory shall reside in application RAM, and
- * shall never be modified while advertising. The data shall be kept alive until either:
- *  - @ref BLE_GAP_EVT_ADV_SET_TERMINATED is raised.
- *  - @ref BLE_GAP_EVT_CONNECTED is raised with @ref ble_gap_evt_connected_t::adv_handle set to the corresponding
- *    advertising handle.
- *  - Advertising is stopped.
- *  - Advertising data is changed.
- * To update advertising data while advertising, provide new buffers to @ref sd_ble_gap_adv_set_configure. */
-typedef struct
-{
-  ble_data_t       adv_data;                     /**< Advertising data.
-                                                      @note
-                                                      Advertising data can only be specified for a @ref ble_gap_adv_properties_t::type
-                                                      that is allowed to contain advertising data. */
-  ble_data_t       scan_rsp_data;                /**< Scan response data.
-                                                      @note
-                                                      Scan response data can only be specified for a @ref ble_gap_adv_properties_t::type
-                                                      that is scannable. */
-} ble_gap_adv_data_t;
-
-
-/**@brief GAP scanning parameters. */
-typedef struct
-{
-  uint8_t               extended               : 1; /**< If 1, the scanner will accept extended advertising packets.
-                                                         If set to 0, the scanner will not receive advertising packets
-                                                         on secondary advertising channels, and will not be able
-                                                         to receive long advertising PDUs. */
-  uint8_t               report_incomplete_evts : 1; /**< If 1, events of type @ref ble_gap_evt_adv_report_t may have
-                                                         @ref ble_gap_adv_report_type_t::status set to
-                                                         @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA.
-                                                         This parameter is ignored when used with @ref sd_ble_gap_connect
-                                                         @note This may be used to abort receiving more packets from an extended
-                                                               advertising event, and is only available for extended
-                                                               scanning, see @ref sd_ble_gap_scan_start.
-                                                         @note This feature is not supported by this SoftDevice. */
-  uint8_t               active                 : 1; /**< If 1, perform active scanning by sending scan requests.
-                                                         This parameter is ignored when used with @ref sd_ble_gap_connect. */
-  uint8_t               filter_policy          : 2; /**< Scanning filter policy. @sa BLE_GAP_SCAN_FILTER_POLICIES.
-                                                         @note Only @ref BLE_GAP_SCAN_FP_ACCEPT_ALL and
-                                                               @ref BLE_GAP_SCAN_FP_WHITELIST are valid when used with
-                                                               @ref sd_ble_gap_connect */
-  uint8_t               scan_phys;                  /**< Bitfield of PHYs to scan on. If set to @ref BLE_GAP_PHY_AUTO,
-                                                         scan_phys will default to @ref BLE_GAP_PHY_1MBPS.
-                                                         - If @ref ble_gap_scan_params_t::extended is set to 0, the only
-                                                           supported PHY is @ref BLE_GAP_PHY_1MBPS.
-                                                         - When used with @ref sd_ble_gap_scan_start,
-                                                           the bitfield indicates the PHYs the scanner will use for scanning
-                                                           on primary advertising channels. The scanner will accept
-                                                           @ref BLE_GAP_PHYS_SUPPORTED as secondary advertising channel PHYs.
-                                                         - When used with @ref sd_ble_gap_connect, the bitfield indicates
-                                                           the PHYs the initiator will use for scanning on primary advertising
-                                                           channels. The initiator will accept connections initiated on either
-                                                           of the @ref BLE_GAP_PHYS_SUPPORTED PHYs.
-                                                           If scan_phys contains @ref BLE_GAP_PHY_1MBPS and/or @ref BLE_GAP_PHY_2MBPS,
-                                                           the primary scan PHY is @ref BLE_GAP_PHY_1MBPS.
-                                                           If scan_phys also contains @ref BLE_GAP_PHY_CODED, the primary scan
-                                                           PHY will also contain @ref BLE_GAP_PHY_CODED. If the only scan PHY is
-                                                           @ref BLE_GAP_PHY_CODED, the primary scan PHY is
-                                                           @ref BLE_GAP_PHY_CODED only. */
-  uint16_t              interval;                   /**< Scan interval in 625 us units. @sa BLE_GAP_SCAN_INTERVALS. */
-  uint16_t              window;                     /**< Scan window in 625 us units. @sa BLE_GAP_SCAN_WINDOW.
-                                                         If scan_phys contains both @ref BLE_GAP_PHY_1MBPS and
-                                                         @ref BLE_GAP_PHY_CODED interval shall be larger than or
-                                                         equal to twice the scan window. */
-  uint16_t              timeout;                    /**< Scan timeout in 10 ms units. @sa BLE_GAP_SCAN_TIMEOUT. */
-  ble_gap_ch_mask_t     channel_mask;               /**< Channel mask for primary and secondary advertising channels.
-                                                         At least one of the primary channels, that is channel index 37-39, must be
-                                                         set to 0.
-                                                         Masking away secondary channels is not supported. */
-} ble_gap_scan_params_t;
-
-
-/**@brief Privacy.
- *
- *        The privacy feature provides a way for the device to avoid being tracked over a period of time.
- *        The privacy feature, when enabled, hides the local device identity and replaces it with a private address
- *        that is automatically refreshed at a specified interval.
- *
- *        If a device still wants to be recognized by other peers, it needs to share it's Identity Resolving Key (IRK).
- *        With this key, a device can generate a random private address that can only be recognized by peers in possession of that key,
- *        and devices can establish connections without revealing their real identities.
- *
- *        Both network privacy (@ref BLE_GAP_PRIVACY_MODE_NETWORK_PRIVACY) and device privacy (@ref BLE_GAP_PRIVACY_MODE_DEVICE_PRIVACY)
- *        are supported.
- *
- * @note  If the device IRK is updated, the new IRK becomes the one to be distributed in all
- *        bonding procedures performed after @ref sd_ble_gap_privacy_set returns.
- *        The IRK distributed during bonding procedure is the device IRK that is active when @ref sd_ble_gap_sec_params_reply is called.
- */
-typedef struct
-{
-  uint8_t        privacy_mode;         /**< Privacy mode, see @ref BLE_GAP_PRIVACY_MODES. Default is @ref BLE_GAP_PRIVACY_MODE_OFF. */
-  uint8_t        private_addr_type;    /**< The private address type must be either @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE or @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE. */
-  uint16_t       private_addr_cycle_s; /**< Private address cycle interval in seconds. Providing an address cycle value of 0 will use the default value defined by @ref BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S. */
-  ble_gap_irk_t *p_device_irk;         /**< When used as input, pointer to IRK structure that will be used as the default IRK. If NULL, the device default IRK will be used.
-                                            When used as output, pointer to IRK structure where the current default IRK will be written to. If NULL, this argument is ignored.
-                                            By default, the default IRK is used to generate random private resolvable addresses for the local device unless instructed otherwise. */
-} ble_gap_privacy_params_t;
-
-
-/**@brief PHY preferences for TX and RX
- * @note  tx_phys and rx_phys are bit fields. Multiple bits can be set in them to indicate multiple preferred PHYs for each direction.
- * @code
- * p_gap_phys->tx_phys = BLE_GAP_PHY_1MBPS | BLE_GAP_PHY_2MBPS;
- * p_gap_phys->rx_phys = BLE_GAP_PHY_1MBPS | BLE_GAP_PHY_2MBPS;
- * @endcode
- *
- */
-typedef struct
-{
-  uint8_t tx_phys;     /**< Preferred transmit PHYs, see @ref BLE_GAP_PHYS. */
-  uint8_t rx_phys;     /**< Preferred receive PHYs, see @ref BLE_GAP_PHYS. */
-} ble_gap_phys_t;
-
-/** @brief Keys that can be exchanged during a bonding procedure. */
-typedef struct
-{
-  uint8_t enc     : 1;                        /**< Long Term Key and Master Identification. */
-  uint8_t id      : 1;                        /**< Identity Resolving Key and Identity Address Information. */
-  uint8_t sign    : 1;                        /**< Connection Signature Resolving Key. */
-  uint8_t link    : 1;                        /**< Derive the Link Key from the LTK. */
-} ble_gap_sec_kdist_t;
-
-
-/**@brief GAP security parameters. */
-typedef struct
-{
-  uint8_t               bond      : 1;             /**< Perform bonding. */
-  uint8_t               mitm      : 1;             /**< Enable Man In The Middle protection. */
-  uint8_t               lesc      : 1;             /**< Enable LE Secure Connection pairing. */
-  uint8_t               keypress  : 1;             /**< Enable generation of keypress notifications. */
-  uint8_t               io_caps   : 3;             /**< IO capabilities, see @ref BLE_GAP_IO_CAPS. */
-  uint8_t               oob       : 1;             /**< The OOB data flag.
-                                                        - In LE legacy pairing, this flag is set if a device has out of band authentication data.
-                                                          The OOB method is used if both of the devices have out of band authentication data.
-                                                        - In LE Secure Connections pairing, this flag is set if a device has the peer device's out of band authentication data.
-                                                          The OOB method is used if at least one device has the peer device's OOB data available. */
-  uint8_t               min_key_size;              /**< Minimum encryption key size in octets between 7 and 16. If 0 then not applicable in this instance. */
-  uint8_t               max_key_size;              /**< Maximum encryption key size in octets between min_key_size and 16. */
-  ble_gap_sec_kdist_t   kdist_own;                 /**< Key distribution bitmap: keys that the local device will distribute. */
-  ble_gap_sec_kdist_t   kdist_peer;                /**< Key distribution bitmap: keys that the remote device will distribute. */
-} ble_gap_sec_params_t;
-
-
-/**@brief GAP Encryption Information. */
-typedef struct
-{
-  uint8_t   ltk[BLE_GAP_SEC_KEY_LEN];   /**< Long Term Key. */
-  uint8_t   lesc : 1;                   /**< Key generated using LE Secure Connections. */
-  uint8_t   auth : 1;                   /**< Authenticated Key. */
-  uint8_t   ltk_len : 6;                /**< LTK length in octets. */
-} ble_gap_enc_info_t;
-
-
-/**@brief GAP Master Identification. */
-typedef struct
-{
-  uint16_t  ediv;                       /**< Encrypted Diversifier. */
-  uint8_t   rand[BLE_GAP_SEC_RAND_LEN]; /**< Random Number. */
-} ble_gap_master_id_t;
-
-
-/**@brief GAP Signing Information. */
-typedef struct
-{
-  uint8_t   csrk[BLE_GAP_SEC_KEY_LEN];        /**< Connection Signature Resolving Key. */
-} ble_gap_sign_info_t;
-
-
-/**@brief GAP LE Secure Connections P-256 Public Key. */
-typedef struct
-{
-  uint8_t   pk[BLE_GAP_LESC_P256_PK_LEN];        /**< LE Secure Connections Elliptic Curve Diffie-Hellman P-256 Public Key. Stored in the standard SMP protocol format: {X,Y} both in little-endian. */
-} ble_gap_lesc_p256_pk_t;
-
-
-/**@brief GAP LE Secure Connections DHKey. */
-typedef struct
-{
-  uint8_t   key[BLE_GAP_LESC_DHKEY_LEN];        /**< LE Secure Connections Elliptic Curve Diffie-Hellman Key. Stored in little-endian. */
-} ble_gap_lesc_dhkey_t;
-
-
-/**@brief GAP LE Secure Connections OOB data. */
-typedef struct
-{
-  ble_gap_addr_t  addr;                          /**< Bluetooth address of the device. */
-  uint8_t         r[BLE_GAP_SEC_KEY_LEN];        /**< Random Number. */
-  uint8_t         c[BLE_GAP_SEC_KEY_LEN];        /**< Confirm Value. */
-} ble_gap_lesc_oob_data_t;
-
-
-/**@brief Event structure for @ref BLE_GAP_EVT_CONNECTED. */
-typedef struct
-{
-  ble_gap_addr_t        peer_addr;              /**< Bluetooth address of the peer device. If the peer_addr resolved: @ref ble_gap_addr_t::addr_id_peer is set to 1
-                                                     and the address is the device's identity address. */
-  uint8_t               role;                   /**< BLE role for this connection, see @ref BLE_GAP_ROLES */
-  ble_gap_conn_params_t conn_params;            /**< GAP Connection Parameters. */
-  uint8_t               adv_handle;             /**< Advertising handle in which advertising has ended.
-                                                     This variable is only set if role is set to @ref BLE_GAP_ROLE_PERIPH. */
-  ble_gap_adv_data_t    adv_data;               /**< Advertising buffers corresponding to the terminated
-                                                     advertising set. The advertising buffers provided in
-                                                     @ref sd_ble_gap_adv_set_configure are now released.
-                                                     This variable is only set if role is set to @ref BLE_GAP_ROLE_PERIPH. */
-} ble_gap_evt_connected_t;
-
-
-/**@brief Event structure for @ref BLE_GAP_EVT_DISCONNECTED. */
-typedef struct
-{
-  uint8_t reason;                               /**< HCI error code, see @ref BLE_HCI_STATUS_CODES. */
-} ble_gap_evt_disconnected_t;
-
-
-/**@brief Event structure for @ref BLE_GAP_EVT_CONN_PARAM_UPDATE. */
-typedef struct
-{
-  ble_gap_conn_params_t conn_params;            /**<  GAP Connection Parameters. */
-} ble_gap_evt_conn_param_update_t;
-
-/**@brief Event structure for @ref BLE_GAP_EVT_PHY_UPDATE_REQUEST. */
-typedef struct
-{
-  ble_gap_phys_t peer_preferred_phys;            /**< The PHYs the peer prefers to use. */
-} ble_gap_evt_phy_update_request_t;
-
-/**@brief Event Structure for @ref BLE_GAP_EVT_PHY_UPDATE. */
-typedef struct
-{
-  uint8_t status;                               /**< Status of the procedure, see @ref BLE_HCI_STATUS_CODES.*/
-  uint8_t tx_phy;                               /**< TX PHY for this connection, see @ref BLE_GAP_PHYS. */
-  uint8_t rx_phy;                               /**< RX PHY for this connection, see @ref BLE_GAP_PHYS. */
-} ble_gap_evt_phy_update_t;
-
-/**@brief Event structure for @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST. */
-typedef struct
-{
-  ble_gap_sec_params_t peer_params;             /**< Initiator Security Parameters. */
-} ble_gap_evt_sec_params_request_t;
-
-
-/**@brief Event structure for @ref BLE_GAP_EVT_SEC_INFO_REQUEST. */
-typedef struct
-{
-  ble_gap_addr_t      peer_addr;                     /**< Bluetooth address of the peer device. */
-  ble_gap_master_id_t master_id;                     /**< Master Identification for LTK lookup. */
-  uint8_t             enc_info  : 1;                 /**< If 1, Encryption Information required. */
-  uint8_t             id_info   : 1;                 /**< If 1, Identity Information required. */
-  uint8_t             sign_info : 1;                 /**< If 1, Signing Information required. */
-} ble_gap_evt_sec_info_request_t;
-
-
-/**@brief Event structure for @ref BLE_GAP_EVT_PASSKEY_DISPLAY. */
-typedef struct
-{
-  uint8_t passkey[BLE_GAP_PASSKEY_LEN];         /**< 6-digit passkey in ASCII ('0'-'9' digits only). */
-  uint8_t match_request : 1;                    /**< If 1 requires the application to report the match using @ref sd_ble_gap_auth_key_reply
-                                                     with either @ref BLE_GAP_AUTH_KEY_TYPE_NONE if there is no match or
-                                                     @ref BLE_GAP_AUTH_KEY_TYPE_PASSKEY if there is a match. */
-} ble_gap_evt_passkey_display_t;
-
-/**@brief Event structure for @ref BLE_GAP_EVT_KEY_PRESSED. */
-typedef struct
-{
-  uint8_t kp_not;         /**< Keypress notification type, see @ref BLE_GAP_KP_NOT_TYPES. */
-} ble_gap_evt_key_pressed_t;
-
-
-/**@brief Event structure for @ref BLE_GAP_EVT_AUTH_KEY_REQUEST. */
-typedef struct
-{
-  uint8_t key_type;                             /**< See @ref BLE_GAP_AUTH_KEY_TYPES. */
-} ble_gap_evt_auth_key_request_t;
-
-/**@brief Event structure for @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST. */
-typedef struct
-{
-  ble_gap_lesc_p256_pk_t *p_pk_peer;  /**< LE Secure Connections remote P-256 Public Key. This will point to the application-supplied memory
-                                           inside the keyset during the call to @ref sd_ble_gap_sec_params_reply. */
-  uint8_t oobd_req       :1;          /**< LESC OOB data required. A call to @ref sd_ble_gap_lesc_oob_data_set is required to complete the procedure. */
-} ble_gap_evt_lesc_dhkey_request_t;
-
-
-/**@brief Security levels supported.
- * @note  See Bluetooth Specification Version 4.2 Volume 3, Part C, Chapter 10, Section 10.2.1.
-*/
-typedef struct
-{
-  uint8_t lv1 : 1;                              /**< If 1: Level 1 is supported. */
-  uint8_t lv2 : 1;                              /**< If 1: Level 2 is supported. */
-  uint8_t lv3 : 1;                              /**< If 1: Level 3 is supported. */
-  uint8_t lv4 : 1;                              /**< If 1: Level 4 is supported. */
-} ble_gap_sec_levels_t;
-
-
-/**@brief Encryption Key. */
-typedef struct
-{
-  ble_gap_enc_info_t    enc_info;             /**< Encryption Information. */
-  ble_gap_master_id_t   master_id;            /**< Master Identification. */
-} ble_gap_enc_key_t;
-
-
-/**@brief Identity Key. */
-typedef struct
-{
-  ble_gap_irk_t         id_info;              /**< Identity Resolving Key. */
-  ble_gap_addr_t        id_addr_info;         /**< Identity Address. */
-} ble_gap_id_key_t;
-
-
-/**@brief Security Keys. */
-typedef struct
-{
-  ble_gap_enc_key_t      *p_enc_key;           /**< Encryption Key, or NULL. */
-  ble_gap_id_key_t       *p_id_key;            /**< Identity Key, or NULL. */
-  ble_gap_sign_info_t    *p_sign_key;          /**< Signing Key, or NULL. */
-  ble_gap_lesc_p256_pk_t *p_pk;                /**< LE Secure Connections P-256 Public Key. When in debug mode the application must use the value defined
-                                                    in the Core Bluetooth Specification v4.2 Vol.3, Part H, Section 2.3.5.6.1 */
-} ble_gap_sec_keys_t;
-
-
-/**@brief Security key set for both local and peer keys. */
-typedef struct
-{
-  ble_gap_sec_keys_t            keys_own;     /**< Keys distributed by the local device. For LE Secure Connections the encryption key will be generated locally and will always be stored if bonding. */
-  ble_gap_sec_keys_t            keys_peer;    /**< Keys distributed by the remote device. For LE Secure Connections, p_enc_key must always be NULL. */
-} ble_gap_sec_keyset_t;
-
-
-/**@brief Data Length Update Procedure parameters. */
-typedef struct
-{
-  uint16_t max_tx_octets;   /**< Maximum number of payload octets that a Controller supports for transmission of a single Link Layer Data Channel PDU. */
-  uint16_t max_rx_octets;   /**< Maximum number of payload octets that a Controller supports for reception of a single Link Layer Data Channel PDU. */
-  uint16_t max_tx_time_us;  /**< Maximum time, in microseconds, that a Controller supports for transmission of a single Link Layer Data Channel PDU. */
-  uint16_t max_rx_time_us;  /**< Maximum time, in microseconds, that a Controller supports for reception of a single Link Layer Data Channel PDU. */
-} ble_gap_data_length_params_t;
-
-
-/**@brief Data Length Update Procedure local limitation. */
-typedef struct
-{
-  uint16_t tx_payload_limited_octets; /**< If > 0, the requested TX packet length is too long by this many octets. */
-  uint16_t rx_payload_limited_octets; /**< If > 0, the requested RX packet length is too long by this many octets. */
-  uint16_t tx_rx_time_limited_us;     /**< If > 0, the requested combination of TX and RX packet lengths is too long by this many microseconds. */
-} ble_gap_data_length_limitation_t;
-
-
-/**@brief Event structure for @ref BLE_GAP_EVT_AUTH_STATUS. */
-typedef struct
-{
-  uint8_t               auth_status;            /**< Authentication status, see @ref BLE_GAP_SEC_STATUS. */
-  uint8_t               error_src : 2;          /**< On error, source that caused the failure, see @ref BLE_GAP_SEC_STATUS_SOURCES. */
-  uint8_t               bonded : 1;             /**< Procedure resulted in a bond. */
-  uint8_t               lesc : 1;               /**< Procedure resulted in a LE Secure Connection. */
-  ble_gap_sec_levels_t  sm1_levels;             /**< Levels supported in Security Mode 1. */
-  ble_gap_sec_levels_t  sm2_levels;             /**< Levels supported in Security Mode 2. */
-  ble_gap_sec_kdist_t   kdist_own;              /**< Bitmap stating which keys were exchanged (distributed) by the local device. If bonding with LE Secure Connections, the enc bit will be always set. */
-  ble_gap_sec_kdist_t   kdist_peer;             /**< Bitmap stating which keys were exchanged (distributed) by the remote device. If bonding with LE Secure Connections, the enc bit will never be set. */
-} ble_gap_evt_auth_status_t;
-
-
-/**@brief Event structure for @ref BLE_GAP_EVT_CONN_SEC_UPDATE. */
-typedef struct
-{
-  ble_gap_conn_sec_t conn_sec;                  /**< Connection security level. */
-} ble_gap_evt_conn_sec_update_t;
-
-
-/**@brief Event structure for @ref BLE_GAP_EVT_TIMEOUT. */
-typedef struct
-{
-  uint8_t src;                                  /**< Source of timeout event, see @ref BLE_GAP_TIMEOUT_SOURCES. */
-  union
-  {
-    ble_data_t adv_report_buffer;               /**< If source is set to @ref BLE_GAP_TIMEOUT_SRC_SCAN, the released
-                                                     scan buffer is contained in this field. */
-  } params;                                     /**< Event Parameters. */
-} ble_gap_evt_timeout_t;
-
-
-/**@brief Event structure for @ref BLE_GAP_EVT_RSSI_CHANGED. */
-typedef struct
-{
-  int8_t  rssi;                                 /**< Received Signal Strength Indication in dBm.
-                                                     @note ERRATA-153 requires the rssi sample to be compensated based on a temperature measurement. */
-  uint8_t ch_index;                             /**< Data Channel Index on which the Signal Strength is measured (0-36). */
-} ble_gap_evt_rssi_changed_t;
-
-/**@brief Event structure for @ref BLE_GAP_EVT_ADV_SET_TERMINATED */
-typedef struct
-{
-  uint8_t             reason;                         /**< Reason for why the advertising set terminated. See
-                                                           @ref BLE_GAP_EVT_ADV_SET_TERMINATED_REASON. */
-  uint8_t             adv_handle;                     /**< Advertising handle in which advertising has ended. */
-  uint8_t             num_completed_adv_events;       /**< If @ref ble_gap_adv_params_t::max_adv_evts was not set to 0,
-                                                           this field indicates the number of completed advertising events. */
-  ble_gap_adv_data_t  adv_data;                       /**< Advertising buffers corresponding to the terminated
-                                                           advertising set. The advertising buffers provided in
-                                                           @ref sd_ble_gap_adv_set_configure are now released. */
-} ble_gap_evt_adv_set_terminated_t;
-
-/**@brief Event structure for @ref BLE_GAP_EVT_ADV_REPORT.
- *
- * @note If @ref ble_gap_adv_report_type_t::status is set to @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA,
- *       not all fields in the advertising report may be available.
- *
- * @note When ble_gap_adv_report_type_t::status is not set to @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA,
- *       scanning will be paused. To continue scanning, call @ref sd_ble_gap_scan_start.
- */
-typedef struct
-{
-  ble_gap_adv_report_type_t type;                  /**< Advertising report type. See @ref ble_gap_adv_report_type_t. */
-  ble_gap_addr_t            peer_addr;             /**< Bluetooth address of the peer device. If the peer_addr is resolved:
-                                                        @ref ble_gap_addr_t::addr_id_peer is set to 1 and the address is the
-                                                        peer's identity address. */
-  ble_gap_addr_t            direct_addr;           /**< Contains the target address of the advertising event if
-                                                        @ref ble_gap_adv_report_type_t::directed is set to 1. If the
-                                                        SoftDevice was able to resolve the address,
-                                                        @ref ble_gap_addr_t::addr_id_peer is set to 1 and the direct_addr
-                                                        contains the local identity address. If the target address of the
-                                                        advertising event is @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE,
-                                                        and the SoftDevice was unable to resolve it, the application may try
-                                                        to resolve this address to find out if the advertising event was
-                                                        directed to us. */
-  uint8_t                   primary_phy;           /**< Indicates the PHY on which the primary advertising packet was received.
-                                                        See @ref BLE_GAP_PHYS. */
-  uint8_t                   secondary_phy;         /**< Indicates the PHY on which the secondary advertising packet was received.
-                                                        See @ref BLE_GAP_PHYS. This field is set to @ref BLE_GAP_PHY_NOT_SET if no packets
-                                                        were received on a secondary advertising channel. */
-  int8_t                    tx_power;              /**< TX Power reported by the advertiser in the last packet header received.
-                                                        This field is set to @ref BLE_GAP_POWER_LEVEL_INVALID if the
-                                                        last received packet did not contain the Tx Power field.
-                                                        @note TX Power is only included in extended advertising packets. */
-  int8_t                    rssi;                  /**< Received Signal Strength Indication in dBm of the last packet received.
-                                                        @note ERRATA-153 requires the rssi sample to be compensated based on a temperature measurement. */
-  uint8_t                   ch_index;              /**< Channel Index on which the last advertising packet is received (0-39). */
-  uint8_t                   set_id;                /**< Set ID of the received advertising data. Set ID is not present
-                                                        if set to @ref BLE_GAP_ADV_REPORT_SET_ID_NOT_AVAILABLE. */
-  uint16_t                  data_id:12;            /**< The advertising data ID of the received advertising data. Data ID
-                                                        is not present if @ref ble_gap_evt_adv_report_t::set_id is set to
-                                                        @ref BLE_GAP_ADV_REPORT_SET_ID_NOT_AVAILABLE. */
-  ble_data_t                data;                  /**< Received advertising or scan response data. If
-                                                        @ref ble_gap_adv_report_type_t::status is not set to
-                                                        @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA, the data buffer provided
-                                                        in @ref sd_ble_gap_scan_start is now released. */
-  ble_gap_aux_pointer_t     aux_pointer;           /**< The offset and PHY of the next advertising packet in this extended advertising
-                                                        event. @note This field is only set if @ref ble_gap_adv_report_type_t::status
-                                                        is set to @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA. */
-} ble_gap_evt_adv_report_t;
-
-
-/**@brief Event structure for @ref BLE_GAP_EVT_SEC_REQUEST. */
-typedef struct
-{
-  uint8_t    bond       : 1;                       /**< Perform bonding. */
-  uint8_t    mitm       : 1;                       /**< Man In The Middle protection requested. */
-  uint8_t    lesc       : 1;                       /**< LE Secure Connections requested. */
-  uint8_t    keypress   : 1;                       /**< Generation of keypress notifications requested. */
-} ble_gap_evt_sec_request_t;
-
-
-/**@brief Event structure for @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST. */
-typedef struct
-{
-  ble_gap_conn_params_t conn_params;            /**<  GAP Connection Parameters. */
-} ble_gap_evt_conn_param_update_request_t;
-
-
-/**@brief Event structure for @ref BLE_GAP_EVT_SCAN_REQ_REPORT. */
-typedef struct
-{
-  uint8_t                 adv_handle;        /**< Advertising handle for the advertising set which received the Scan Request */
-  int8_t                  rssi;              /**< Received Signal Strength Indication in dBm.
-                                                  @note ERRATA-153 requires the rssi sample to be compensated based on a temperature measurement. */
-  ble_gap_addr_t          peer_addr;         /**< Bluetooth address of the peer device. If the peer_addr resolved: @ref ble_gap_addr_t::addr_id_peer is set to 1
-                                                  and the address is the device's identity address. */
-} ble_gap_evt_scan_req_report_t;
-
-
-/**@brief Event structure for @ref BLE_GAP_EVT_DATA_LENGTH_UPDATE_REQUEST. */
-typedef struct
-{
-  ble_gap_data_length_params_t peer_params; /**< Peer data length parameters. */
-} ble_gap_evt_data_length_update_request_t;
-
-/**@brief Event structure for @ref BLE_GAP_EVT_DATA_LENGTH_UPDATE. */
-typedef struct
-{
-  ble_gap_data_length_params_t effective_params;  /**< The effective data length parameters. */
-} ble_gap_evt_data_length_update_t;
-
-
-/**@brief Event structure for @ref BLE_GAP_EVT_QOS_CHANNEL_SURVEY_REPORT. */
-typedef struct
-{
-  int8_t channel_energy[BLE_GAP_CHANNEL_COUNT]; /**< The measured energy on the Bluetooth Low Energy
-                                                     channels, in dBm, indexed by Channel Index.
-                                                     If no measurement is available for the given channel, channel_energy is set to
-                                                     @ref BLE_GAP_POWER_LEVEL_INVALID. */
-} ble_gap_evt_qos_channel_survey_report_t;
-
-/**@brief GAP event structure. */
-typedef struct
-{
-  uint16_t conn_handle;                                     /**< Connection Handle on which event occurred. */
-  union                                                     /**< union alternative identified by evt_id in enclosing struct. */
-  {
-    ble_gap_evt_connected_t                   connected;                    /**< Connected Event Parameters. */
-    ble_gap_evt_disconnected_t                disconnected;                 /**< Disconnected Event Parameters. */
-    ble_gap_evt_conn_param_update_t           conn_param_update;            /**< Connection Parameter Update Parameters. */
-    ble_gap_evt_sec_params_request_t          sec_params_request;           /**< Security Parameters Request Event Parameters. */
-    ble_gap_evt_sec_info_request_t            sec_info_request;             /**< Security Information Request Event Parameters. */
-    ble_gap_evt_passkey_display_t             passkey_display;              /**< Passkey Display Event Parameters. */
-    ble_gap_evt_key_pressed_t                 key_pressed;                  /**< Key Pressed Event Parameters. */
-    ble_gap_evt_auth_key_request_t            auth_key_request;             /**< Authentication Key Request Event Parameters. */
-    ble_gap_evt_lesc_dhkey_request_t          lesc_dhkey_request;           /**< LE Secure Connections DHKey calculation request. */
-    ble_gap_evt_auth_status_t                 auth_status;                  /**< Authentication Status Event Parameters. */
-    ble_gap_evt_conn_sec_update_t             conn_sec_update;              /**< Connection Security Update Event Parameters. */
-    ble_gap_evt_timeout_t                     timeout;                      /**< Timeout Event Parameters. */
-    ble_gap_evt_rssi_changed_t                rssi_changed;                 /**< RSSI Event Parameters. */
-    ble_gap_evt_adv_report_t                  adv_report;                   /**< Advertising Report Event Parameters. */
-    ble_gap_evt_adv_set_terminated_t          adv_set_terminated;           /**< Advertising Set Terminated Event Parameters. */
-    ble_gap_evt_sec_request_t                 sec_request;                  /**< Security Request Event Parameters. */
-    ble_gap_evt_conn_param_update_request_t   conn_param_update_request;    /**< Connection Parameter Update Parameters. */
-    ble_gap_evt_scan_req_report_t             scan_req_report;              /**< Scan Request Report Parameters. */
-    ble_gap_evt_phy_update_request_t          phy_update_request;           /**< PHY Update Request Event Parameters. */
-    ble_gap_evt_phy_update_t                  phy_update;                   /**< PHY Update Parameters. */
-    ble_gap_evt_data_length_update_request_t  data_length_update_request;   /**< Data Length Update Request Event Parameters. */
-    ble_gap_evt_data_length_update_t          data_length_update;           /**< Data Length Update Event Parameters. */
-    ble_gap_evt_qos_channel_survey_report_t   qos_channel_survey_report;    /**< Quality of Service (QoS) Channel Survey Report Parameters. */
-  } params;                                                                 /**< Event Parameters. */
-} ble_gap_evt_t;
-
-
-/**
- * @brief BLE GAP connection configuration parameters, set with @ref sd_ble_cfg_set.
- *
- * @retval ::NRF_ERROR_CONN_COUNT     The connection count for the connection configurations is zero.
- * @retval ::NRF_ERROR_INVALID_PARAM  One or more of the following is true:
- *                                    - The sum of conn_count for all connection configurations combined exceeds UINT8_MAX.
- *                                    - The event length is smaller than @ref BLE_GAP_EVENT_LENGTH_MIN.
- */
-typedef struct
-{
-  uint8_t  conn_count;     /**< The number of concurrent connections the application can create with this configuration.
-                                The default and minimum value is @ref BLE_GAP_CONN_COUNT_DEFAULT. */
-  uint16_t event_length;   /**< The time set aside for this connection on every connection interval in 1.25 ms units.
-                                The default value is @ref BLE_GAP_EVENT_LENGTH_DEFAULT, the minimum value is @ref BLE_GAP_EVENT_LENGTH_MIN.
-                                The event length and the connection interval are the primary parameters
-                                for setting the throughput of a connection.
-                                See the SoftDevice Specification for details on throughput. */
-} ble_gap_conn_cfg_t;
-
-
-/**
- * @brief Configuration of maximum concurrent connections in the different connected roles, set with
- * @ref sd_ble_cfg_set.
- *
- * @retval ::NRF_ERROR_CONN_COUNT     The sum of periph_role_count and central_role_count is too
- *                                    large. The maximum supported sum of concurrent connections is
- *                                    @ref BLE_GAP_ROLE_COUNT_COMBINED_MAX.
- * @retval ::NRF_ERROR_INVALID_PARAM  central_sec_count is larger than central_role_count.
- * @retval ::NRF_ERROR_RESOURCES      The adv_set_count is too large. The maximum
- *                                    supported advertising handles is
- *                                    @ref BLE_GAP_ADV_SET_COUNT_MAX.
- */
-typedef struct
-{
-  uint8_t adv_set_count;      /**< Maximum number of advertising sets. Default value is @ref BLE_GAP_ADV_SET_COUNT_DEFAULT. */
-  uint8_t periph_role_count;  /**< Maximum number of connections concurrently acting as a peripheral. Default value is @ref BLE_GAP_ROLE_COUNT_PERIPH_DEFAULT. */
-  uint8_t central_role_count; /**< Maximum number of connections concurrently acting as a central. Default value is @ref BLE_GAP_ROLE_COUNT_CENTRAL_DEFAULT. */
-  uint8_t central_sec_count;  /**< Number of SMP instances shared between all connections acting as a central. Default value is @ref BLE_GAP_ROLE_COUNT_CENTRAL_SEC_DEFAULT. */
-  uint8_t qos_channel_survey_role_available:1; /**< If set, the Quality of Service (QoS) channel survey module is available to the
-                                                    application using @ref sd_ble_gap_qos_channel_survey_start. */
-} ble_gap_cfg_role_count_t;
-
-
-/**
- * @brief Device name and its properties, set with @ref sd_ble_cfg_set.
- *
- * @note  If the device name is not configured, the default device name will be
- *        @ref BLE_GAP_DEVNAME_DEFAULT, the maximum device name length will be
- *        @ref BLE_GAP_DEVNAME_DEFAULT_LEN, vloc will be set to @ref BLE_GATTS_VLOC_STACK and the device name
- *        will have no write access.
- *
- * @note  If @ref max_len is more than @ref BLE_GAP_DEVNAME_DEFAULT_LEN and vloc is set to @ref BLE_GATTS_VLOC_STACK,
- *        the attribute table size must be increased to have room for the longer device name (see
- *        @ref sd_ble_cfg_set and @ref ble_gatts_cfg_attr_tab_size_t).
- *
- * @note  If vloc is @ref BLE_GATTS_VLOC_STACK :
- *        - p_value must point to non-volatile memory (flash) or be NULL.
- *        - If p_value is NULL, the device name will initially be empty.
- *
- * @note  If vloc is @ref BLE_GATTS_VLOC_USER :
- *        - p_value cannot be NULL.
- *        - If the device name is writable, p_value must point to volatile memory (RAM).
- *
- * @retval ::NRF_ERROR_INVALID_PARAM  One or more of the following is true:
- *                                    - Invalid device name location (vloc).
- *                                    - Invalid device name security mode.
- * @retval ::NRF_ERROR_INVALID_LENGTH One or more of the following is true:
- *                                    - The device name length is invalid (must be between 0 and @ref BLE_GAP_DEVNAME_MAX_LEN).
- *                                    - The device name length is too long for the given Attribute Table.
- * @retval ::NRF_ERROR_NOT_SUPPORTED  Device name security mode is not supported.
- */
-typedef struct
-{
-  ble_gap_conn_sec_mode_t  write_perm;   /**< Write permissions. */
-  uint8_t                  vloc:2;       /**< Value location, see @ref BLE_GATTS_VLOCS.*/
-  uint8_t                 *p_value;      /**< Pointer to where the value (device name) is stored or will be stored. */
-  uint16_t                 current_len;  /**< Current length in bytes of the memory pointed to by p_value.*/
-  uint16_t                 max_len;      /**< Maximum length in bytes of the memory pointed to by p_value.*/
-} ble_gap_cfg_device_name_t;
-
-
-/**@brief Configuration structure for GAP configurations. */
-typedef union
-{
-  ble_gap_cfg_role_count_t  role_count_cfg;  /**< Role count configuration, cfg_id is @ref BLE_GAP_CFG_ROLE_COUNT. */
-  ble_gap_cfg_device_name_t device_name_cfg; /**< Device name configuration, cfg_id is @ref BLE_GAP_CFG_DEVICE_NAME. */
-} ble_gap_cfg_t;
-
-
-/**@brief Channel Map option.
- *
- * @details Used with @ref sd_ble_opt_get to get the current channel map
- *          or @ref sd_ble_opt_set to set a new channel map. When setting the
- *          channel map, it applies to all current and future connections. When getting the
- *          current channel map, it applies to a single connection and the connection handle
- *          must be supplied.
- *
- * @note Setting the channel map may take some time, depending on connection parameters.
- *       The time taken may be different for each connection and the get operation will
- *       return the previous channel map until the new one has taken effect.
- *
- * @note After setting the channel map, by spec it can not be set again until at least 1 s has passed.
- *       See Bluetooth Specification Version 4.1 Volume 2, Part E, Section 7.3.46.
- *
- * @retval ::NRF_SUCCESS Get or set successful.
- * @retval ::NRF_ERROR_INVALID_PARAM One or more of the following is true:
- *                                   - Less then two bits in @ref ch_map are set.
- *                                   - Bits for primary advertising channels (37-39) are set.
- * @retval ::NRF_ERROR_BUSY Channel map was set again before enough time had passed.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied for get.
- *
- */
-typedef struct
-{
-  uint16_t conn_handle;                   /**< Connection Handle (only applicable for get) */
-  uint8_t ch_map[5];                      /**< Channel Map (37-bit). */
-} ble_gap_opt_ch_map_t;
-
-
-/**@brief Local connection latency option.
- *
- * @details Local connection latency is a feature which enables the slave to improve
- *          current consumption by ignoring the slave latency set by the peer. The
- *          local connection latency can only be set to a multiple of the slave latency,
- *          and cannot be longer than half of the supervision timeout.
- *
- * @details Used with @ref sd_ble_opt_set to set the local connection latency. The
- *          @ref sd_ble_opt_get is not supported for this option, but the actual
- *          local connection latency (unless set to NULL) is set as a return parameter
- *          when setting the option.
- *
- * @note The latency set will be truncated down to the closest slave latency event
- *       multiple, or the nearest multiple before half of the supervision timeout.
- *
- * @note The local connection latency is disabled by default, and needs to be enabled for new
- *       connections and whenever the connection is updated.
- *
- * @retval ::NRF_SUCCESS Set successfully.
- * @retval ::NRF_ERROR_NOT_SUPPORTED Get is not supported.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle parameter.
- */
-typedef struct
-{
-  uint16_t   conn_handle;                       /**< Connection Handle */
-  uint16_t   requested_latency;                 /**< Requested local connection latency. */
-  uint16_t * p_actual_latency;                  /**< Pointer to storage for the actual local connection latency (can be set to NULL to skip return value). */
-} ble_gap_opt_local_conn_latency_t;
-
-/**@brief Disable slave latency
- *
- * @details Used with @ref sd_ble_opt_set to temporarily disable slave latency of a peripheral connection
- *          (see @ref ble_gap_conn_params_t::slave_latency). And to re-enable it again. When disabled, the
- *          peripheral will ignore the slave_latency set by the central.
- *
- * @note  Shall only be called on peripheral links.
- *
- * @retval ::NRF_SUCCESS Set successfully.
- * @retval ::NRF_ERROR_NOT_SUPPORTED Get is not supported.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle parameter.
- */
-typedef struct
-{
-  uint16_t   conn_handle;    /**< Connection Handle */
-  uint8_t    disable : 1;    /**< Set to 1 to disable slave latency. Set to 0 enable it again.*/
-} ble_gap_opt_slave_latency_disable_t;
-
-/**@brief Passkey Option.
- *
- * @details Structure containing the passkey to be used during pairing. This can be used with @ref
- *          sd_ble_opt_set to make the SoftDevice use a preprogrammed passkey for authentication
- *          instead of generating a random one.
- *
- * @note Repeated pairing attempts using the same preprogrammed passkey makes pairing vulnerable to MITM attacks.
- *
- * @note @ref sd_ble_opt_get is not supported for this option.
- *
- */
-typedef struct
-{
-  uint8_t const * p_passkey;                    /**< Pointer to 6-digit ASCII string (digit 0..9 only, no NULL termination) passkey to be used during pairing. If this is NULL, the SoftDevice will generate a random passkey if required.*/
-} ble_gap_opt_passkey_t;
-
-
-/**@brief Compatibility mode 1 option.
- *
- * @details This can be used with @ref sd_ble_opt_set to enable and disable
- *          compatibility mode 1. Compatibility mode 1 is disabled by default.
- *
- * @note Compatibility mode 1 enables interoperability with devices that do not support a value of
- *       0 for the WinOffset parameter in the Link Layer CONNECT_IND packet. This applies to a
- *       limited set of legacy peripheral devices from another vendor. Enabling this compatibility
- *       mode will only have an effect if the local device will act as a central device and
- *       initiate a connection to a peripheral device. In that case it may lead to the connection
- *       creation taking up to one connection interval longer to complete for all connections.
- *
- *  @retval ::NRF_SUCCESS Set successfully.
- *  @retval ::NRF_ERROR_INVALID_STATE When connection creation is ongoing while mode 1 is set.
- */
-typedef struct
-{
-   uint8_t enable : 1;                           /**< Enable compatibility mode 1.*/
-} ble_gap_opt_compat_mode_1_t;
-
-
-/**@brief Authenticated payload timeout option.
- *
- * @details This can be used with @ref sd_ble_opt_set to change the Authenticated payload timeout to a value other
- *          than the default of @ref BLE_GAP_AUTH_PAYLOAD_TIMEOUT_MAX.
- *
- * @note The authenticated payload timeout event ::BLE_GAP_TIMEOUT_SRC_AUTH_PAYLOAD will be generated
- *       if auth_payload_timeout time has elapsed without receiving a packet with a valid MIC on an encrypted
- *       link.
- *
- * @note The LE ping procedure will be initiated before the timer expires to give the peer a chance
- *       to reset the timer. In addition the stack will try to prioritize running of LE ping over other
- *       activities to increase chances of finishing LE ping before timer expires. To avoid side-effects
- *       on other activities, it is recommended to use high timeout values.
- *       Recommended timeout > 2*(connInterval * (6 + connSlaveLatency)).
- *
- * @retval ::NRF_SUCCESS Set successfully.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. auth_payload_timeout was outside of allowed range.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle parameter.
- */
-typedef struct
-{
-  uint16_t   conn_handle;                       /**< Connection Handle */
-  uint16_t   auth_payload_timeout;              /**< Requested timeout in 10 ms unit, see @ref BLE_GAP_AUTH_PAYLOAD_TIMEOUT. */
-} ble_gap_opt_auth_payload_timeout_t;
-
-/**@brief Option structure for GAP options. */
-typedef union
-{
-  ble_gap_opt_ch_map_t                  ch_map;                    /**< Parameters for the Channel Map option. */
-  ble_gap_opt_local_conn_latency_t      local_conn_latency;        /**< Parameters for the Local connection latency option */
-  ble_gap_opt_passkey_t                 passkey;                   /**< Parameters for the Passkey option.*/
-  ble_gap_opt_compat_mode_1_t           compat_mode_1;             /**< Parameters for the compatibility mode 1 option.*/
-  ble_gap_opt_auth_payload_timeout_t    auth_payload_timeout;      /**< Parameters for the authenticated payload timeout option.*/
-  ble_gap_opt_slave_latency_disable_t   slave_latency_disable;     /**< Parameters for the Disable slave latency option */
-} ble_gap_opt_t;
-/**@} */
-
-
-/**@addtogroup BLE_GAP_FUNCTIONS Functions
- * @{ */
-
-/**@brief Set the local Bluetooth identity address.
- *
- *        The local Bluetooth identity address is the address that identifies this device to other peers.
- *        The address type must be either @ref BLE_GAP_ADDR_TYPE_PUBLIC or @ref BLE_GAP_ADDR_TYPE_RANDOM_STATIC.
- *
- * @note  The identity address cannot be changed while advertising, scanning or creating a connection.
- *
- * @note  This address will be distributed to the peer during bonding.
- *        If the address changes, the address stored in the peer device will not be valid and the ability to
- *        reconnect using the old address will be lost.
- *
- * @note  By default the SoftDevice will set an address of type @ref BLE_GAP_ADDR_TYPE_RANDOM_STATIC upon being
- *        enabled. The address is a random number populated during the IC manufacturing process and remains unchanged
- *        for the lifetime of each IC.
- *
- * @mscs
- * @mmsc{@ref BLE_GAP_ADV_MSC}
- * @endmscs
- *
- * @param[in] p_addr Pointer to address structure.
- *
- * @retval ::NRF_SUCCESS Address successfully set.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid address.
- * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry.
- * @retval ::NRF_ERROR_INVALID_STATE The identity address cannot be changed while advertising,
- *                                   scanning or creating a connection.
- */
-SVCALL(SD_BLE_GAP_ADDR_SET, uint32_t, sd_ble_gap_addr_set(ble_gap_addr_t const *p_addr));
-
-
-/**@brief Get local Bluetooth identity address.
- *
- * @note  This will always return the identity address irrespective of the privacy settings,
- *        i.e. the address type will always be either @ref BLE_GAP_ADDR_TYPE_PUBLIC or @ref BLE_GAP_ADDR_TYPE_RANDOM_STATIC.
- *
- * @param[out] p_addr Pointer to address structure to be filled in.
- *
- * @retval ::NRF_SUCCESS Address successfully retrieved.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid or NULL pointer supplied.
- */
-SVCALL(SD_BLE_GAP_ADDR_GET, uint32_t, sd_ble_gap_addr_get(ble_gap_addr_t *p_addr));
-
-
-/**@brief Get the Bluetooth device address used by the advertiser.
- *
- * @note  This function will return the local Bluetooth address used in advertising PDUs. When
- *        using privacy, the SoftDevice will generate a new private address every
- *        @ref ble_gap_privacy_params_t::private_addr_cycle_s configured using
- *        @ref sd_ble_gap_privacy_set. Hence depending on when the application calls this API, the
- *        address returned may not be the latest address that is used in the advertising PDUs.
- *
- * @param[in]  adv_handle The advertising handle to get the address from.
- * @param[out] p_addr     Pointer to address structure to be filled in.
- *
- * @retval ::NRF_SUCCESS                  Address successfully retrieved.
- * @retval ::NRF_ERROR_INVALID_ADDR       Invalid or NULL pointer supplied.
- * @retval ::BLE_ERROR_INVALID_ADV_HANDLE The provided advertising handle was not found. 
- * @retval ::NRF_ERROR_INVALID_STATE      The advertising set is currently not advertising.
- */
-SVCALL(SD_BLE_GAP_ADV_ADDR_GET, uint32_t, sd_ble_gap_adv_addr_get(uint8_t adv_handle, ble_gap_addr_t *p_addr));
-
-
-/**@brief Set the active whitelist in the SoftDevice.
- *
- * @note  Only one whitelist can be used at a time and the whitelist is shared between the BLE roles.
- *        The whitelist cannot be set if a BLE role is using the whitelist.
- *
- * @note  If an address is resolved using the information in the device identity list, then the whitelist
- *        filter policy applies to the peer identity address and not the resolvable address sent on air.
- *
- * @mscs
- * @mmsc{@ref BLE_GAP_WL_SHARE_MSC}
- * @mmsc{@ref BLE_GAP_PRIVACY_SCAN_PRIVATE_SCAN_MSC}
- * @endmscs
- *
- * @param[in] pp_wl_addrs Pointer to a whitelist of peer addresses, if NULL the whitelist will be cleared.
- * @param[in] len         Length of the whitelist, maximum @ref BLE_GAP_WHITELIST_ADDR_MAX_COUNT.
- *
- * @retval ::NRF_SUCCESS The whitelist is successfully set/cleared.
- * @retval ::NRF_ERROR_INVALID_ADDR The whitelist (or one of its entries) provided is invalid.
- * @retval ::BLE_ERROR_GAP_WHITELIST_IN_USE The whitelist is in use by a BLE role and cannot be set or cleared.
- * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid address type is supplied.
- * @retval ::NRF_ERROR_DATA_SIZE The given whitelist size is invalid (zero or too large); this can only return when
- *                               pp_wl_addrs is not NULL.
- */
-SVCALL(SD_BLE_GAP_WHITELIST_SET, uint32_t, sd_ble_gap_whitelist_set(ble_gap_addr_t const * const * pp_wl_addrs, uint8_t len));
-
-
-/**@brief Set device identity list.
- *
- * @note  Only one device identity list can be used at a time and the list is shared between the BLE roles.
- *        The device identity list cannot be set if a BLE role is using the list.
- *
- * @param[in] pp_id_keys     Pointer to an array of peer identity addresses and peer IRKs, if NULL the device identity list will be cleared.
- * @param[in] pp_local_irks  Pointer to an array of local IRKs. Each entry in the array maps to the entry in pp_id_keys at the same index.
- *                           To fill in the list with the currently set device IRK for all peers, set to NULL.
- * @param[in] len            Length of the device identity list, maximum @ref BLE_GAP_DEVICE_IDENTITIES_MAX_COUNT.
- *
- * @mscs
- * @mmsc{@ref BLE_GAP_PRIVACY_ADV_MSC}
- * @mmsc{@ref BLE_GAP_PRIVACY_SCAN_MSC}
- * @mmsc{@ref BLE_GAP_PRIVACY_SCAN_PRIVATE_SCAN_MSC}
- * @mmsc{@ref BLE_GAP_PRIVACY_ADV_DIR_PRIV_MSC}
- * @mmsc{@ref BLE_GAP_PERIPH_CONN_PRIV_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_CONN_PRIV_MSC}
- * @endmscs
- *
- * @retval ::NRF_SUCCESS The device identity list successfully set/cleared.
- * @retval ::NRF_ERROR_INVALID_ADDR The device identity list (or one of its entries) provided is invalid.
- *                                  This code may be returned if the local IRK list also has an invalid entry.
- * @retval ::BLE_ERROR_GAP_DEVICE_IDENTITIES_IN_USE The device identity list is in use and cannot be set or cleared.
- * @retval ::BLE_ERROR_GAP_DEVICE_IDENTITIES_DUPLICATE The device identity list contains multiple entries with the same identity address.
- * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid address type is supplied.
- * @retval ::NRF_ERROR_DATA_SIZE The given device identity list size invalid (zero or too large); this can
- *                               only return when pp_id_keys is not NULL.
- */
-SVCALL(SD_BLE_GAP_DEVICE_IDENTITIES_SET, uint32_t, sd_ble_gap_device_identities_set(ble_gap_id_key_t const * const * pp_id_keys, ble_gap_irk_t const * const * pp_local_irks, uint8_t len));
-
-
-/**@brief Set privacy settings.
- *
- * @note  Privacy settings cannot be changed while advertising, scanning or creating a connection.
- *
- * @param[in] p_privacy_params Privacy settings.
- *
- * @mscs
- * @mmsc{@ref BLE_GAP_PRIVACY_ADV_MSC}
- * @mmsc{@ref BLE_GAP_PRIVACY_SCAN_MSC}
- * @mmsc{@ref BLE_GAP_PRIVACY_ADV_DIR_PRIV_MSC}
- * @endmscs
- *
- * @retval ::NRF_SUCCESS Set successfully.
- * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry.
- * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid address type is supplied.
- * @retval ::NRF_ERROR_INVALID_ADDR The pointer to privacy settings is NULL or invalid.
- *                                  Otherwise, the p_device_irk pointer in privacy parameter is an invalid pointer.
- * @retval ::NRF_ERROR_INVALID_PARAM Out of range parameters are provided.
- * @retval ::NRF_ERROR_INVALID_STATE Privacy settings cannot be changed while advertising, scanning
- *                                   or creating a connection.
- */
-SVCALL(SD_BLE_GAP_PRIVACY_SET, uint32_t, sd_ble_gap_privacy_set(ble_gap_privacy_params_t const *p_privacy_params));
-
-
-/**@brief Get privacy settings.
- *
- * @note ::ble_gap_privacy_params_t::p_device_irk must be initialized to NULL or a valid address before this function is called.
- *       If it is initialized to a valid address, the address pointed to will contain the current device IRK on return.
- *
- * @param[in,out] p_privacy_params Privacy settings.
- *
- * @retval ::NRF_SUCCESS            Privacy settings read.
- * @retval ::NRF_ERROR_INVALID_ADDR The pointer given for returning the privacy settings may be NULL or invalid.
- *                                  Otherwise, the p_device_irk pointer in privacy parameter is an invalid pointer.
- */
-SVCALL(SD_BLE_GAP_PRIVACY_GET, uint32_t, sd_ble_gap_privacy_get(ble_gap_privacy_params_t *p_privacy_params));
-
-
-/**@brief Configure an advertising set. Set, clear or update advertising and scan response data.
- *
- * @note  The format of the advertising data will be checked by this call to ensure interoperability.
- *        Limitations imposed by this API call to the data provided include having a flags data type in the scan response data and
- *        duplicating the local name in the advertising data and scan response data.
- *
- * @note In order to update advertising data while advertising, new advertising buffers must be provided.
- *
- * @mscs
- * @mmsc{@ref BLE_GAP_ADV_MSC}
- * @mmsc{@ref BLE_GAP_WL_SHARE_MSC}
- * @endmscs
- *
- * @param[in,out] p_adv_handle                         Provide a pointer to a handle containing @ref BLE_GAP_ADV_SET_HANDLE_NOT_SET to configure
- *                                                     a new advertising set. On success, a new handle is then returned through the pointer.
- *                                                     Provide a pointer to an existing advertising handle to configure an existing advertising set.
- * @param[in]     p_adv_data                           Advertising data. If set to NULL, no advertising data will be used. See @ref ble_gap_adv_data_t.
- * @param[in]     p_adv_params                         Advertising parameters. When this function is used to update advertising data while advertising,
- *                                                     this parameter must be NULL. See @ref ble_gap_adv_params_t.
- *
- * @retval ::NRF_SUCCESS                               Advertising set successfully configured.
- * @retval ::NRF_ERROR_INVALID_PARAM                   Invalid parameter(s) supplied:
- *                                                      - Invalid advertising data configuration specified. See @ref ble_gap_adv_data_t.
- *                                                      - Invalid configuration of p_adv_params. See @ref ble_gap_adv_params_t.
- *                                                      - Use of whitelist requested but whitelist has not been set,
- *                                                        see @ref sd_ble_gap_whitelist_set.
- * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR            ble_gap_adv_params_t::p_peer_addr is invalid.
- * @retval ::NRF_ERROR_INVALID_STATE                   Invalid state to perform operation. Either:
- *                                                     - It is invalid to provide non-NULL advertising set parameters while advertising.
- *                                                     - It is invalid to provide the same data buffers while advertising. To update
- *                                                       advertising data, provide new advertising buffers.
- * @retval ::BLE_ERROR_GAP_DISCOVERABLE_WITH_WHITELIST Discoverable mode and whitelist incompatible.
- * @retval ::BLE_ERROR_INVALID_ADV_HANDLE              The provided advertising handle was not found. Use @ref BLE_GAP_ADV_SET_HANDLE_NOT_SET to
- *                                                     configure a new advertising handle.
- * @retval ::NRF_ERROR_INVALID_ADDR                    Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_FLAGS                   Invalid combination of advertising flags supplied.
- * @retval ::NRF_ERROR_INVALID_DATA                    Invalid data type(s) supplied. Check the advertising data format specification
- *                                                     given in Bluetooth Specification Version 5.0, Volume 3, Part C, Chapter 11.
- * @retval ::NRF_ERROR_INVALID_LENGTH                  Invalid data length(s) supplied.
- * @retval ::NRF_ERROR_NOT_SUPPORTED                   Unsupported data length or advertising parameter configuration.
- * @retval ::NRF_ERROR_NO_MEM                          Not enough memory to configure a new advertising handle. Update an
- *                                                     existing advertising handle instead.
- * @retval ::BLE_ERROR_GAP_UUID_LIST_MISMATCH Invalid UUID list supplied.
- */
-SVCALL(SD_BLE_GAP_ADV_SET_CONFIGURE, uint32_t, sd_ble_gap_adv_set_configure(uint8_t *p_adv_handle, ble_gap_adv_data_t const *p_adv_data, ble_gap_adv_params_t const *p_adv_params));
-
-
-/**@brief Start advertising (GAP Discoverable, Connectable modes, Broadcast Procedure).
- *
- * @note Only one advertiser may be active at any time.
- *
- * @events
- * @event{@ref BLE_GAP_EVT_CONNECTED, Generated after connection has been established through connectable advertising.}
- * @event{@ref BLE_GAP_EVT_ADV_SET_TERMINATED, Advertising set has terminated.}
- * @event{@ref BLE_GAP_EVT_SCAN_REQ_REPORT, A scan request was received.}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_GAP_ADV_MSC}
- * @mmsc{@ref BLE_GAP_PERIPH_CONN_PRIV_MSC}
- * @mmsc{@ref BLE_GAP_PRIVACY_ADV_DIR_PRIV_MSC}
- * @mmsc{@ref BLE_GAP_WL_SHARE_MSC}
- * @endmscs
- *
- * @param[in] adv_handle   Advertising handle to advertise on, received from @ref sd_ble_gap_adv_set_configure.
- * @param[in] conn_cfg_tag Tag identifying a configuration set by @ref sd_ble_cfg_set or
- *                         @ref BLE_CONN_CFG_TAG_DEFAULT to use the default connection configuration. For non-connectable
- *                         advertising, this is ignored.
- *
- * @retval ::NRF_SUCCESS                  The BLE stack has started advertising.
- * @retval ::NRF_ERROR_INVALID_STATE      adv_handle is not configured or already advertising.
- * @retval ::NRF_ERROR_CONN_COUNT         The limit of available connections has been reached; connectable advertiser cannot be started.
- * @retval ::BLE_ERROR_INVALID_ADV_HANDLE Advertising handle not found. Configure a new adveriting handle with @ref sd_ble_gap_adv_set_configure.
- * @retval ::NRF_ERROR_NOT_FOUND          conn_cfg_tag not found.
- * @retval ::NRF_ERROR_INVALID_PARAM      Invalid parameter(s) supplied:
- *                                        - Invalid configuration of p_adv_params. See @ref ble_gap_adv_params_t.
- *                                        - Use of whitelist requested but whitelist has not been set, see @ref sd_ble_gap_whitelist_set.
- * @retval ::NRF_ERROR_RESOURCES          Either:
- *                                        - adv_handle is configured with connectable advertising, but the event_length parameter
- *                                          associated with conn_cfg_tag is too small to be able to establish a connection on
- *                                          the selected advertising phys. Use @ref sd_ble_cfg_set to increase the event length.
- *                                        - Not enough BLE role slots available.
-                                            Stop one or more currently active roles (Central, Peripheral, Broadcaster or Observer) and try again.
- *                                        - p_adv_params is configured with connectable advertising, but the event_length parameter
- *                                          associated with conn_cfg_tag is too small to be able to establish a connection on
- *                                          the selected advertising phys. Use @ref sd_ble_cfg_set to increase the event length.
- */
-SVCALL(SD_BLE_GAP_ADV_START, uint32_t, sd_ble_gap_adv_start(uint8_t adv_handle, uint8_t conn_cfg_tag));
-
-
-/**@brief Stop advertising (GAP Discoverable, Connectable modes, Broadcast Procedure).
- *
- * @mscs
- * @mmsc{@ref BLE_GAP_ADV_MSC}
- * @mmsc{@ref BLE_GAP_WL_SHARE_MSC}
- * @endmscs
- *
- * @param[in] adv_handle The advertising handle that should stop advertising.
- *
- * @retval ::NRF_SUCCESS The BLE stack has stopped advertising.
- * @retval ::BLE_ERROR_INVALID_ADV_HANDLE Invalid advertising handle.
- * @retval ::NRF_ERROR_INVALID_STATE The advertising handle is not advertising.
- */
-SVCALL(SD_BLE_GAP_ADV_STOP, uint32_t, sd_ble_gap_adv_stop(uint8_t adv_handle));
-
-
-
-/**@brief Update connection parameters.
- *
- * @details In the central role this will initiate a Link Layer connection parameter update procedure,
- *          otherwise in the peripheral role, this will send the corresponding L2CAP request and wait for
- *          the central to perform the procedure. In both cases, and regardless of success or failure, the application
- *          will be informed of the result with a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE event.
- *
- * @details This function can be used as a central both to reply to a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST or to start the procedure unrequested.
- *
- * @events
- * @event{@ref BLE_GAP_EVT_CONN_PARAM_UPDATE, Result of the connection parameter update procedure.}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_GAP_CPU_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_ENC_AUTH_MUTEX_MSC}
- * @mmsc{@ref BLE_GAP_MULTILINK_CPU_MSC}
- * @mmsc{@ref BLE_GAP_MULTILINK_CTRL_PROC_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_CPU_MSC}
- * @endmscs
- *
- * @param[in] conn_handle Connection handle.
- * @param[in] p_conn_params  Pointer to desired connection parameters. If NULL is provided on a peripheral role,
- *                           the parameters in the PPCP characteristic of the GAP service will be used instead.
- *                           If NULL is provided on a central role and in response to a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST, the peripheral request will be rejected
- *
- * @retval ::NRF_SUCCESS The Connection Update procedure has been started successfully.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints.
- * @retval ::NRF_ERROR_INVALID_STATE Disconnection in progress or link has not been established.
- * @retval ::NRF_ERROR_BUSY Procedure already in progress, wait for pending procedures to complete and retry.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
- * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
- */
-SVCALL(SD_BLE_GAP_CONN_PARAM_UPDATE, uint32_t, sd_ble_gap_conn_param_update(uint16_t conn_handle, ble_gap_conn_params_t const *p_conn_params));
-
-
-/**@brief Disconnect (GAP Link Termination).
- *
- * @details This call initiates the disconnection procedure, and its completion will be communicated to the application
- *          with a @ref BLE_GAP_EVT_DISCONNECTED event.
- *
- * @events
- * @event{@ref BLE_GAP_EVT_DISCONNECTED, Generated when disconnection procedure is complete.}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_GAP_CONN_MSC}
- * @endmscs
- *
- * @param[in] conn_handle Connection handle.
- * @param[in] hci_status_code HCI status code, see @ref BLE_HCI_STATUS_CODES (accepted values are @ref BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION and @ref BLE_HCI_CONN_INTERVAL_UNACCEPTABLE).
- *
- * @retval ::NRF_SUCCESS The disconnection procedure has been started successfully.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
- * @retval ::NRF_ERROR_INVALID_STATE Disconnection in progress or link has not been established.
- */
-SVCALL(SD_BLE_GAP_DISCONNECT, uint32_t, sd_ble_gap_disconnect(uint16_t conn_handle, uint8_t hci_status_code));
-
-
-/**@brief Set the radio's transmit power.
- *
- * @param[in] role The role to set the transmit power for, see @ref BLE_GAP_TX_POWER_ROLES for
- *                 possible roles.
- * @param[in] handle   The handle parameter is interpreted depending on role:
- *                     - If role is @ref BLE_GAP_TX_POWER_ROLE_CONN, this value is the specific connection handle.
- *                     - If role is @ref BLE_GAP_TX_POWER_ROLE_ADV, the advertising set identified with the advertising handle,
- *                       will use the specified transmit power, and include it in the advertising packet headers if
- *                       @ref ble_gap_adv_properties_t::include_tx_power set.
- *                     - For all other roles handle is ignored.
- * @param[in] tx_power Radio transmit power in dBm (see note for accepted values).
- *
-  * @note Supported tx_power values: -40dBm, -20dBm, -16dBm, -12dBm, -8dBm, -4dBm, 0dBm, +2dBm, +3dBm, +4dBm, +5dBm, +6dBm, +7dBm and +8dBm.
-  * @note The initiator will have the same transmit power as the scanner.
- * @note When a connection is created it will inherit the transmit power from the initiator or
- *       advertiser leading to the connection.
- *
- * @retval ::NRF_SUCCESS Successfully changed the transmit power.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::BLE_ERROR_INVALID_ADV_HANDLE Advertising handle not found.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
- */
-SVCALL(SD_BLE_GAP_TX_POWER_SET, uint32_t, sd_ble_gap_tx_power_set(uint8_t role, uint16_t handle, int8_t tx_power));
-
-
-/**@brief Set GAP Appearance value.
- *
- * @param[in] appearance Appearance (16-bit), see @ref BLE_APPEARANCES.
- *
- * @retval ::NRF_SUCCESS  Appearance value set successfully.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- */
-SVCALL(SD_BLE_GAP_APPEARANCE_SET, uint32_t, sd_ble_gap_appearance_set(uint16_t appearance));
-
-
-/**@brief Get GAP Appearance value.
- *
- * @param[out] p_appearance Pointer to appearance (16-bit) to be filled in, see @ref BLE_APPEARANCES.
- *
- * @retval ::NRF_SUCCESS Appearance value retrieved successfully.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- */
-SVCALL(SD_BLE_GAP_APPEARANCE_GET, uint32_t, sd_ble_gap_appearance_get(uint16_t *p_appearance));
-
-
-/**@brief Set GAP Peripheral Preferred Connection Parameters.
- *
- * @param[in] p_conn_params Pointer to a @ref ble_gap_conn_params_t structure with the desired parameters.
- *
- * @retval ::NRF_SUCCESS Peripheral Preferred Connection Parameters set successfully.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- */
-SVCALL(SD_BLE_GAP_PPCP_SET, uint32_t, sd_ble_gap_ppcp_set(ble_gap_conn_params_t const *p_conn_params));
-
-
-/**@brief Get GAP Peripheral Preferred Connection Parameters.
- *
- * @param[out] p_conn_params Pointer to a @ref ble_gap_conn_params_t structure where the parameters will be stored.
- *
- * @retval ::NRF_SUCCESS Peripheral Preferred Connection Parameters retrieved successfully.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- */
-SVCALL(SD_BLE_GAP_PPCP_GET, uint32_t, sd_ble_gap_ppcp_get(ble_gap_conn_params_t *p_conn_params));
-
-
-/**@brief Set GAP device name.
- *
- * @note  If the device name is located in application flash memory (see @ref ble_gap_cfg_device_name_t),
- *        it cannot be changed. Then @ref NRF_ERROR_FORBIDDEN will be returned.
- *
- * @param[in] p_write_perm Write permissions for the Device Name characteristic, see @ref ble_gap_conn_sec_mode_t.
- * @param[in] p_dev_name Pointer to a UTF-8 encoded, <b>non NULL-terminated</b> string.
- * @param[in] len Length of the UTF-8, <b>non NULL-terminated</b> string pointed to by p_dev_name in octets (must be smaller or equal than @ref BLE_GAP_DEVNAME_MAX_LEN).
- *
- * @retval ::NRF_SUCCESS GAP device name and permissions set successfully.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied.
- * @retval ::NRF_ERROR_FORBIDDEN Device name is not writable.
- */
-SVCALL(SD_BLE_GAP_DEVICE_NAME_SET, uint32_t, sd_ble_gap_device_name_set(ble_gap_conn_sec_mode_t const *p_write_perm, uint8_t const *p_dev_name, uint16_t len));
-
-
-/**@brief Get GAP device name.
- *
- * @note  If the device name is longer than the size of the supplied buffer,
- *        p_len will return the complete device name length,
- *        and not the number of bytes actually returned in p_dev_name.
- *        The application may use this information to allocate a suitable buffer size.
- *
- * @param[out]    p_dev_name Pointer to an empty buffer where the UTF-8 <b>non NULL-terminated</b> string will be placed. Set to NULL to obtain the complete device name length.
- * @param[in,out] p_len      Length of the buffer pointed by p_dev_name, complete device name length on output.
- *
- * @retval ::NRF_SUCCESS GAP device name retrieved successfully.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied.
- */
-SVCALL(SD_BLE_GAP_DEVICE_NAME_GET, uint32_t, sd_ble_gap_device_name_get(uint8_t *p_dev_name, uint16_t *p_len));
-
-
-/**@brief Initiate the GAP Authentication procedure.
- *
- * @details In the central role, this function will send an SMP Pairing Request (or an SMP Pairing Failed if rejected),
- *          otherwise in the peripheral role, an SMP Security Request will be sent.
- *
- * @events
- * @event{Depending on the security parameters set and the packet exchanges with the peer\, the following events may be generated:}
- * @event{@ref BLE_GAP_EVT_SEC_PARAMS_REQUEST}
- * @event{@ref BLE_GAP_EVT_SEC_INFO_REQUEST}
- * @event{@ref BLE_GAP_EVT_PASSKEY_DISPLAY}
- * @event{@ref BLE_GAP_EVT_KEY_PRESSED}
- * @event{@ref BLE_GAP_EVT_AUTH_KEY_REQUEST}
- * @event{@ref BLE_GAP_EVT_LESC_DHKEY_REQUEST}
- * @event{@ref BLE_GAP_EVT_CONN_SEC_UPDATE}
- * @event{@ref BLE_GAP_EVT_AUTH_STATUS}
- * @event{@ref BLE_GAP_EVT_TIMEOUT}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_GAP_PERIPH_SEC_REQ_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_SEC_REQ_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_ENC_AUTH_MUTEX_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_PAIRING_JW_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_JW_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_OOB_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_LESC_PAIRING_JW_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_PD_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC}
- * @endmscs
- *
- * @param[in] conn_handle Connection handle.
- * @param[in] p_sec_params Pointer to the @ref ble_gap_sec_params_t structure with the security parameters to be used during the pairing or bonding procedure.
- *                         In the peripheral role, only the bond, mitm, lesc and keypress fields of this structure are used.
- *                         In the central role, this pointer may be NULL to reject a Security Request.
- *
- * @retval ::NRF_SUCCESS Successfully initiated authentication procedure.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either:
- *                                   - No link has been established.
- *                                   - An encryption is already executing or queued.
- * @retval ::NRF_ERROR_NO_MEM The maximum number of authentication procedures that can run in parallel for the given role is reached.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
- * @retval ::NRF_ERROR_NOT_SUPPORTED Setting of sign or link fields in @ref ble_gap_sec_kdist_t not supported.
- * @retval ::NRF_ERROR_TIMEOUT A SMP timeout has occurred, and further SMP operations on this link is prohibited.
- */
-SVCALL(SD_BLE_GAP_AUTHENTICATE, uint32_t, sd_ble_gap_authenticate(uint16_t conn_handle, ble_gap_sec_params_t const *p_sec_params));
-
-
-/**@brief Reply with GAP security parameters.
- *
- * @details This function is only used to reply to a @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST, calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE.
- * @note    If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters.
- *
- * @events
- * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_JW_MSC}
- * @mmsc{@ref BLE_GAP_PERIPH_BONDING_JW_MSC}
- * @mmsc{@ref BLE_GAP_PERIPH_BONDING_PK_PERIPH_MSC}
- * @mmsc{@ref BLE_GAP_PERIPH_BONDING_PK_CENTRAL_OOB_MSC}
- * @mmsc{@ref BLE_GAP_PERIPH_BONDING_STATIC_PK_MSC}
- * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_CONFIRM_FAIL_MSC}
- * @mmsc{@ref BLE_GAP_PERIPH_LESC_PAIRING_JW_MSC}
- * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_NC_MSC}
- * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_PD_MSC}
- * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC}
- * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC}
- * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_KS_TOO_SMALL_MSC}
- * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_APP_ERROR_MSC}
- * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_REMOTE_PAIRING_FAIL_MSC}
- * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_TIMEOUT_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_PAIRING_JW_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_JW_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_OOB_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_LESC_PAIRING_JW_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_PD_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC}
- * @endmscs
- *
- * @param[in] conn_handle Connection handle.
- * @param[in] sec_status Security status, see @ref BLE_GAP_SEC_STATUS.
- * @param[in] p_sec_params Pointer to a @ref ble_gap_sec_params_t security parameters structure. In the central role this must be set to NULL, as the parameters have
- *                         already been provided during a previous call to @ref sd_ble_gap_authenticate.
- * @param[in,out] p_sec_keyset Pointer to a @ref ble_gap_sec_keyset_t security keyset structure. Any keys generated and/or distributed as a result of the ongoing security procedure
- *                         will be stored into the memory referenced by the pointers inside this structure. The keys will be stored and available to the application
- *                         upon reception of a @ref BLE_GAP_EVT_AUTH_STATUS event.
- *                         Note that the SoftDevice expects the application to provide memory for storing the
- *                         peer's keys. So it must be ensured that the relevant pointers inside this structure are not NULL. The pointers to the local key
- *                         can, however, be NULL, in which case, the local key data will not be available to the application upon reception of the
- *                         @ref BLE_GAP_EVT_AUTH_STATUS event.
- *
- * @retval ::NRF_SUCCESS Successfully accepted security parameter from the application.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::NRF_ERROR_INVALID_STATE Security parameters has not been requested.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
- * @retval ::NRF_ERROR_NOT_SUPPORTED Setting of sign or link fields in @ref ble_gap_sec_kdist_t not supported.
- */
-SVCALL(SD_BLE_GAP_SEC_PARAMS_REPLY, uint32_t, sd_ble_gap_sec_params_reply(uint16_t conn_handle, uint8_t sec_status, ble_gap_sec_params_t const *p_sec_params, ble_gap_sec_keyset_t const *p_sec_keyset));
-
-
-/**@brief Reply with an authentication key.
- *
- * @details This function is only used to reply to a @ref BLE_GAP_EVT_AUTH_KEY_REQUEST or a @ref BLE_GAP_EVT_PASSKEY_DISPLAY, calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE.
- * @note    If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters.
- *
- * @events
- * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_GAP_PERIPH_BONDING_PK_CENTRAL_OOB_MSC}
- * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_NC_MSC}
- * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_OOB_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC}
- * @endmscs
- *
- * @param[in] conn_handle Connection handle.
- * @param[in] key_type See @ref BLE_GAP_AUTH_KEY_TYPES.
- * @param[in] p_key If key type is @ref BLE_GAP_AUTH_KEY_TYPE_NONE, then NULL.
- *                  If key type is @ref BLE_GAP_AUTH_KEY_TYPE_PASSKEY, then a 6-byte ASCII string (digit 0..9 only, no NULL termination)
- *                     or NULL when confirming LE Secure Connections Numeric Comparison.
- *                  If key type is @ref BLE_GAP_AUTH_KEY_TYPE_OOB, then a 16-byte OOB key value in little-endian format.
- *
- * @retval ::NRF_SUCCESS Authentication key successfully set.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::NRF_ERROR_INVALID_STATE Authentication key has not been requested.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
- */
-SVCALL(SD_BLE_GAP_AUTH_KEY_REPLY, uint32_t, sd_ble_gap_auth_key_reply(uint16_t conn_handle, uint8_t key_type, uint8_t const *p_key));
-
-
-/**@brief Reply with an LE Secure connections DHKey.
- *
- * @details This function is only used to reply to a @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST, calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE.
- * @note    If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters.
- *
- * @events
- * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_GAP_PERIPH_LESC_PAIRING_JW_MSC}
- * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_NC_MSC}
- * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_PD_MSC}
- * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC}
- * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_LESC_PAIRING_JW_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_PD_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC}
- * @endmscs
- *
- * @param[in] conn_handle Connection handle.
- * @param[in] p_dhkey LE Secure Connections DHKey.
- *
- * @retval ::NRF_SUCCESS DHKey successfully set.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either:
- *                                   - The peer is not authenticated.
- *                                   - The application has not pulled a @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST event.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
- */
-SVCALL(SD_BLE_GAP_LESC_DHKEY_REPLY, uint32_t, sd_ble_gap_lesc_dhkey_reply(uint16_t conn_handle, ble_gap_lesc_dhkey_t const *p_dhkey));
-
-
-/**@brief Notify the peer of a local keypress.
- *
- * @mscs
- * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC}
- * @endmscs
- *
- * @param[in] conn_handle Connection handle.
- * @param[in] kp_not See @ref BLE_GAP_KP_NOT_TYPES.
- *
- * @retval ::NRF_SUCCESS Keypress notification successfully queued for transmission.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either:
- *                                   - Authentication key not requested.
- *                                   - Passkey has not been entered.
- *                                   - Keypresses have not been enabled by both peers.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
- * @retval ::NRF_ERROR_BUSY The BLE stack is busy. Retry at later time.
- */
-SVCALL(SD_BLE_GAP_KEYPRESS_NOTIFY, uint32_t, sd_ble_gap_keypress_notify(uint16_t conn_handle, uint8_t kp_not));
-
-
-/**@brief Generate a set of OOB data to send to a peer out of band.
- *
- * @note  The @ref ble_gap_addr_t included in the OOB data returned will be the currently active one (or, if a connection has already been established,
- *        the one used during connection setup). The application may manually overwrite it with an updated value.
- *
- * @mscs
- * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC}
- * @endmscs
- *
- * @param[in] conn_handle Connection handle. Can be @ref BLE_CONN_HANDLE_INVALID if a BLE connection has not been established yet.
- * @param[in] p_pk_own LE Secure Connections local P-256 Public Key.
- * @param[out] p_oobd_own The OOB data to be sent out of band to a peer.
- *
- * @retval ::NRF_SUCCESS OOB data successfully generated.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
- */
-SVCALL(SD_BLE_GAP_LESC_OOB_DATA_GET, uint32_t, sd_ble_gap_lesc_oob_data_get(uint16_t conn_handle, ble_gap_lesc_p256_pk_t const *p_pk_own, ble_gap_lesc_oob_data_t *p_oobd_own));
-
-/**@brief Provide the OOB data sent/received out of band.
- *
- * @note  An authentication procedure with OOB selected as an algorithm must be in progress when calling this function.
- * @note  A @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST event with the oobd_req set to 1 must have been received prior to calling this function.
- *
- * @events
- * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC}
- * @endmscs
- *
- * @param[in] conn_handle Connection handle.
- * @param[in] p_oobd_own The OOB data sent out of band to a peer or NULL if the peer has not received OOB data.
- *                       Must correspond to @ref ble_gap_sec_params_t::oob flag in @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST.
- * @param[in] p_oobd_peer The OOB data received out of band from a peer or NULL if none received.
- *                        Must correspond to @ref ble_gap_sec_params_t::oob flag
- *                        in @ref sd_ble_gap_authenticate in the central role or
- *                        in @ref sd_ble_gap_sec_params_reply in the peripheral role.
- *
- * @retval ::NRF_SUCCESS OOB data accepted.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either:
- *                                   - Authentication key not requested
- *                                   - Not expecting LESC OOB data
- *                                   - Have not actually exchanged passkeys.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
- */
-SVCALL(SD_BLE_GAP_LESC_OOB_DATA_SET, uint32_t, sd_ble_gap_lesc_oob_data_set(uint16_t conn_handle, ble_gap_lesc_oob_data_t const *p_oobd_own, ble_gap_lesc_oob_data_t const *p_oobd_peer));
-
-
-/**@brief Initiate GAP Encryption procedure.
- *
- * @details In the central role, this function will initiate the encryption procedure using the encryption information provided.
- *
- * @events
- * @event{@ref BLE_GAP_EVT_CONN_SEC_UPDATE, The connection security has been updated.}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_GAP_CENTRAL_ENC_AUTH_MUTEX_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_ENC_MSC}
- * @mmsc{@ref BLE_GAP_MULTILINK_CTRL_PROC_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_SEC_REQ_MSC}
- * @endmscs
- *
- * @param[in] conn_handle Connection handle.
- * @param[in] p_master_id Pointer to a @ref ble_gap_master_id_t master identification structure.
- * @param[in] p_enc_info  Pointer to a @ref ble_gap_enc_info_t encryption information structure.
- *
- * @retval ::NRF_SUCCESS Successfully initiated authentication procedure.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_STATE No link has been established.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
- * @retval ::BLE_ERROR_INVALID_ROLE Operation is not supported in the Peripheral role.
- * @retval ::NRF_ERROR_BUSY Procedure already in progress or not allowed at this time, wait for pending procedures to complete and retry.
- */
-SVCALL(SD_BLE_GAP_ENCRYPT, uint32_t, sd_ble_gap_encrypt(uint16_t conn_handle, ble_gap_master_id_t const *p_master_id, ble_gap_enc_info_t const *p_enc_info));
-
-
-/**@brief Reply with GAP security information.
- *
- * @details This function is only used to reply to a @ref BLE_GAP_EVT_SEC_INFO_REQUEST, calling it at other times will result in @ref NRF_ERROR_INVALID_STATE.
- * @note    If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters.
- * @note    Data signing is not yet supported, and p_sign_info must therefore be NULL.
- *
- * @mscs
- * @mmsc{@ref BLE_GAP_PERIPH_ENC_MSC}
- * @endmscs
- *
- * @param[in] conn_handle Connection handle.
- * @param[in] p_enc_info Pointer to a @ref ble_gap_enc_info_t encryption information structure. May be NULL to signal none is available.
- * @param[in] p_id_info Pointer to a @ref ble_gap_irk_t identity information structure. May be NULL to signal none is available.
- * @param[in] p_sign_info Pointer to a @ref ble_gap_sign_info_t signing information structure. May be NULL to signal none is available.
- *
- * @retval ::NRF_SUCCESS Successfully accepted security information.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either:
- *                                   - No link has been established.
- *                                   - No @ref BLE_GAP_EVT_SEC_REQUEST pending.
- *                                   - LE long term key requested command not allowed.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
- */
-SVCALL(SD_BLE_GAP_SEC_INFO_REPLY, uint32_t, sd_ble_gap_sec_info_reply(uint16_t conn_handle, ble_gap_enc_info_t const *p_enc_info, ble_gap_irk_t const *p_id_info, ble_gap_sign_info_t const *p_sign_info));
-
-
-/**@brief Get the current connection security.
- *
- * @param[in]  conn_handle Connection handle.
- * @param[out] p_conn_sec  Pointer to a @ref ble_gap_conn_sec_t structure to be filled in.
- *
- * @retval ::NRF_SUCCESS Current connection security successfully retrieved.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
- */
-SVCALL(SD_BLE_GAP_CONN_SEC_GET, uint32_t, sd_ble_gap_conn_sec_get(uint16_t conn_handle, ble_gap_conn_sec_t *p_conn_sec));
-
-
-/**@brief Start reporting the received signal strength to the application.
- *
- *        A new event is reported whenever the RSSI value changes, until @ref sd_ble_gap_rssi_stop is called.
- *
- * @events
- * @event{@ref BLE_GAP_EVT_RSSI_CHANGED, New RSSI data available. How often the event is generated is
- *                                       dependent on the settings of the <code>threshold_dbm</code>
- *                                       and <code>skip_count</code> input parameters.}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_GAP_CENTRAL_RSSI_READ_MSC}
- * @mmsc{@ref BLE_GAP_RSSI_FILT_MSC}
- * @endmscs
- *
- * @param[in] conn_handle        Connection handle.
- * @param[in] threshold_dbm      Minimum change in dBm before triggering the @ref BLE_GAP_EVT_RSSI_CHANGED event. Events are disabled if threshold_dbm equals @ref BLE_GAP_RSSI_THRESHOLD_INVALID.
- * @param[in] skip_count         Number of RSSI samples with a change of threshold_dbm or more before sending a new @ref BLE_GAP_EVT_RSSI_CHANGED event.
- *
- * @retval ::NRF_SUCCESS                   Successfully activated RSSI reporting.
- * @retval ::NRF_ERROR_INVALID_STATE       RSSI reporting is already ongoing.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
- */
-SVCALL(SD_BLE_GAP_RSSI_START, uint32_t, sd_ble_gap_rssi_start(uint16_t conn_handle, uint8_t threshold_dbm, uint8_t skip_count));
-
-
-/**@brief Stop reporting the received signal strength.
- *
- * @note  An RSSI change detected before the call but not yet received by the application
- *        may be reported after @ref sd_ble_gap_rssi_stop has been called.
- *
- * @mscs
- * @mmsc{@ref BLE_GAP_CENTRAL_RSSI_READ_MSC}
- * @mmsc{@ref BLE_GAP_RSSI_FILT_MSC}
- * @endmscs
- *
- * @param[in] conn_handle Connection handle.
- *
- * @retval ::NRF_SUCCESS                   Successfully deactivated RSSI reporting.
- * @retval ::NRF_ERROR_INVALID_STATE       RSSI reporting is not ongoing.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
- */
-SVCALL(SD_BLE_GAP_RSSI_STOP, uint32_t, sd_ble_gap_rssi_stop(uint16_t conn_handle));
-
-
-/**@brief Get the received signal strength for the last connection event.
- *
- *        @ref sd_ble_gap_rssi_start must be called to start reporting RSSI before using this function. @ref NRF_ERROR_NOT_FOUND
- *        will be returned until RSSI was sampled for the first time after calling @ref sd_ble_gap_rssi_start.
- * @note ERRATA-153 requires the rssi sample to be compensated based on a temperature measurement.
- * @mscs
- * @mmsc{@ref BLE_GAP_CENTRAL_RSSI_READ_MSC}
- * @endmscs
- *
- * @param[in]  conn_handle Connection handle.
- * @param[out] p_rssi      Pointer to the location where the RSSI measurement shall be stored.
- * @param[out] p_ch_index  Pointer to the location where Channel Index for the RSSI measurement shall be stored.
- *
- * @retval ::NRF_SUCCESS                   Successfully read the RSSI.
- * @retval ::NRF_ERROR_NOT_FOUND           No sample is available.
- * @retval ::NRF_ERROR_INVALID_ADDR        Invalid pointer supplied.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
- * @retval ::NRF_ERROR_INVALID_STATE       RSSI reporting is not ongoing.
- */
-SVCALL(SD_BLE_GAP_RSSI_GET, uint32_t, sd_ble_gap_rssi_get(uint16_t conn_handle, int8_t *p_rssi, uint8_t *p_ch_index));
-
-
-/**@brief Start or continue scanning (GAP Discovery procedure, Observer Procedure).
- *
- * @note    A call to this function will require the application to keep the memory pointed by
- *          p_adv_report_buffer alive until the buffer is released. The buffer is released when the scanner is stopped
- *          or when this function is called with another buffer.
- *
- * @note    The scanner will automatically stop in the following cases:
- *           - @ref sd_ble_gap_scan_stop is called.
- *           - @ref sd_ble_gap_connect is called.
- *           - A @ref BLE_GAP_EVT_TIMEOUT with source set to @ref BLE_GAP_TIMEOUT_SRC_SCAN is received.
- *           - When a @ref BLE_GAP_EVT_ADV_REPORT event is received and @ref ble_gap_adv_report_type_t::status is not set to
- *             @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA. In this case scanning is only paused to let the application
- *             access received data. The application must call this function to continue scanning, or call @ref sd_ble_gap_scan_stop
- *             to stop scanning.
- *
- * @note    If a @ref BLE_GAP_EVT_ADV_REPORT event is received with @ref ble_gap_adv_report_type_t::status set to
- *          @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA, the scanner will continue scanning, and the application will
- *          receive more reports from this advertising event. The following reports will include the old and new received data.
- *
- * @events
- * @event{@ref BLE_GAP_EVT_ADV_REPORT, An advertising or scan response packet has been received.}
- * @event{@ref BLE_GAP_EVT_TIMEOUT, Scanner has timed out.}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_GAP_SCAN_MSC}
- * @mmsc{@ref BLE_GAP_WL_SHARE_MSC}
- * @endmscs
- *
- * @param[in] p_scan_params       Pointer to scan parameters structure. When this function is used to continue
- *                                scanning, this parameter must be NULL.
- * @param[in] p_adv_report_buffer Pointer to buffer used to store incoming advertising data.
- *                                The memory pointed to should be kept alive until the scanning is stopped.
- *                                See @ref BLE_GAP_SCAN_BUFFER_SIZE for minimum and maximum buffer size.
- *                                If the scanner receives advertising data larger than can be stored in the buffer,
- *                                a @ref BLE_GAP_EVT_ADV_REPORT will be raised with @ref ble_gap_adv_report_type_t::status
- *                                set to @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_TRUNCATED.
- *
- * @retval ::NRF_SUCCESS Successfully initiated scanning procedure.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either:
- *                                   - Scanning is already ongoing and p_scan_params was not NULL
- *                                   - Scanning is not running and p_scan_params was NULL.
- *                                   - The scanner has timed out when this function is called to continue scanning.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. See @ref ble_gap_scan_params_t.
- * @retval ::NRF_ERROR_NOT_SUPPORTED Unsupported parameters supplied. See @ref ble_gap_scan_params_t.
- * @retval ::NRF_ERROR_INVALID_LENGTH The provided buffer length is invalid. See @ref BLE_GAP_SCAN_BUFFER_MIN.
- * @retval ::NRF_ERROR_RESOURCES Not enough BLE role slots available.
- *                               Stop one or more currently active roles (Central, Peripheral or Broadcaster) and try again
- */
-SVCALL(SD_BLE_GAP_SCAN_START, uint32_t, sd_ble_gap_scan_start(ble_gap_scan_params_t const *p_scan_params, ble_data_t const * p_adv_report_buffer));
-
-
-/**@brief Stop scanning (GAP Discovery procedure, Observer Procedure).
- *
- * @note The buffer provided in @ref sd_ble_gap_scan_start is released.
- *
- * @mscs
- * @mmsc{@ref BLE_GAP_SCAN_MSC}
- * @mmsc{@ref BLE_GAP_WL_SHARE_MSC}
- * @endmscs
- *
- * @retval ::NRF_SUCCESS Successfully stopped scanning procedure.
- * @retval ::NRF_ERROR_INVALID_STATE Not in the scanning state.
- */
-SVCALL(SD_BLE_GAP_SCAN_STOP, uint32_t, sd_ble_gap_scan_stop(void));
-
-
-/**@brief Create a connection (GAP Link Establishment).
- *
- * @note If a scanning procedure is currently in progress it will be automatically stopped when calling this function.
- *       The scanning procedure will be stopped even if the function returns an error.
- *
- * @events
- * @event{@ref BLE_GAP_EVT_CONNECTED, A connection was established.}
- * @event{@ref BLE_GAP_EVT_TIMEOUT, Failed to establish a connection.}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_GAP_WL_SHARE_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_CONN_PRIV_MSC}
- * @mmsc{@ref BLE_GAP_CENTRAL_CONN_MSC}
- * @endmscs
- *
- * @param[in] p_peer_addr   Pointer to peer identity address. If @ref ble_gap_scan_params_t::filter_policy is set to use
- *                          whitelist, then p_peer_addr is ignored.
- * @param[in] p_scan_params Pointer to scan parameters structure.
- * @param[in] p_conn_params Pointer to desired connection parameters.
- * @param[in] conn_cfg_tag  Tag identifying a configuration set by @ref sd_ble_cfg_set or
- *                          @ref BLE_CONN_CFG_TAG_DEFAULT to use the default connection configuration.
- *
- * @retval ::NRF_SUCCESS Successfully initiated connection procedure.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid parameter(s) pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- *                                   - Invalid parameter(s) in p_scan_params or p_conn_params.
- *                                   - Use of whitelist requested but whitelist has not been set, see @ref sd_ble_gap_whitelist_set.
- *                                   - Peer address was not present in the device identity list, see @ref sd_ble_gap_device_identities_set.
- * @retval ::NRF_ERROR_NOT_FOUND conn_cfg_tag not found.
- * @retval ::NRF_ERROR_INVALID_STATE The SoftDevice is in an invalid state to perform this operation. This may be due to an
- *                                   existing locally initiated connect procedure, which must complete before initiating again.
- * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid Peer address.
- * @retval ::NRF_ERROR_CONN_COUNT The limit of available connections has been reached.
- * @retval ::NRF_ERROR_RESOURCES Either:
- *                                 - Not enough BLE role slots available.
- *                                   Stop one or more currently active roles (Central, Peripheral or Observer) and try again.
- *                                 - The event_length parameter associated with conn_cfg_tag is too small to be able to
- *                                   establish a connection on the selected @ref ble_gap_scan_params_t::scan_phys.
- *                                   Use @ref sd_ble_cfg_set to increase the event length.
- */
-SVCALL(SD_BLE_GAP_CONNECT, uint32_t, sd_ble_gap_connect(ble_gap_addr_t const *p_peer_addr, ble_gap_scan_params_t const *p_scan_params, ble_gap_conn_params_t const *p_conn_params, uint8_t conn_cfg_tag));
-
-
-/**@brief Cancel a connection establishment.
- *
- * @mscs
- * @mmsc{@ref BLE_GAP_CENTRAL_CONN_MSC}
- * @endmscs
- *
- * @retval ::NRF_SUCCESS Successfully canceled an ongoing connection procedure.
- * @retval ::NRF_ERROR_INVALID_STATE No locally initiated connect procedure started or connection
- *                                   completed occurred.
- */
-SVCALL(SD_BLE_GAP_CONNECT_CANCEL, uint32_t, sd_ble_gap_connect_cancel(void));
-
-
-/**@brief Initiate or respond to a PHY Update Procedure
- *
- * @details   This function is used to initiate or respond to a PHY Update Procedure. It will always
- *            generate a @ref BLE_GAP_EVT_PHY_UPDATE event if successfully executed.
- *            If this function is used to initiate a PHY Update procedure and the only option
- *            provided in @ref ble_gap_phys_t::tx_phys and @ref ble_gap_phys_t::rx_phys is the
- *            currently active PHYs in the respective directions, the SoftDevice will generate a
- *            @ref BLE_GAP_EVT_PHY_UPDATE with the current PHYs set and will not initiate the
- *            procedure in the Link Layer.
- *
- *            If @ref ble_gap_phys_t::tx_phys or @ref ble_gap_phys_t::rx_phys is @ref BLE_GAP_PHY_AUTO,
- *            then the stack will select PHYs based on the peer's PHY preferences and the local link
- *            configuration. The PHY Update procedure will for this case result in a PHY combination
- *            that respects the time constraints configured with @ref sd_ble_cfg_set and the current
- *            link layer data length.
- *
- *            When acting as a central, the SoftDevice will select the fastest common PHY in each direction.
- *
- *            If the peer does not support the PHY Update Procedure, then the resulting
- *            @ref BLE_GAP_EVT_PHY_UPDATE event will have a status set to
- *            @ref BLE_HCI_UNSUPPORTED_REMOTE_FEATURE.
- *
- *            If the PHY procedure was rejected by the peer due to a procedure collision, the status
- *            will be @ref BLE_HCI_STATUS_CODE_LMP_ERROR_TRANSACTION_COLLISION or
- *            @ref BLE_HCI_DIFFERENT_TRANSACTION_COLLISION.
- *            If the peer responds to the PHY Update procedure with invalid parameters, the status
- *            will be @ref BLE_HCI_STATUS_CODE_INVALID_LMP_PARAMETERS.
- *            If the PHY procedure was rejected by the peer for a different reason, the status will
- *            contain the reason as specified by the peer.
- *
- * @events
- * @event{@ref BLE_GAP_EVT_PHY_UPDATE, Result of the PHY Update Procedure.}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_GAP_CENTRAL_PHY_UPDATE}
- * @mmsc{@ref BLE_GAP_PERIPHERAL_PHY_UPDATE}
- * @endmscs
- *
- * @param[in] conn_handle   Connection handle to indicate the connection for which the PHY Update is requested.
- * @param[in] p_gap_phys    Pointer to PHY structure.
- *
- * @retval ::NRF_SUCCESS Successfully requested a PHY Update.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::NRF_ERROR_INVALID_STATE No link has been established.
- * @retval ::NRF_ERROR_RESOURCES The connection event length configured for this link is not sufficient for the combination of
- *                               @ref ble_gap_phys_t::tx_phys, @ref ble_gap_phys_t::rx_phys, and @ref ble_gap_data_length_params_t.
- *                               The connection event length is configured with @ref BLE_CONN_CFG_GAP using @ref sd_ble_cfg_set.
- * @retval ::NRF_ERROR_BUSY Procedure is already in progress or not allowed at this time. Process pending events and wait for the pending procedure to complete and retry.
- *
- */
-SVCALL(SD_BLE_GAP_PHY_UPDATE, uint32_t, sd_ble_gap_phy_update(uint16_t conn_handle, ble_gap_phys_t const *p_gap_phys));
-
-
-/**@brief Initiate or respond to a Data Length Update Procedure.
- *
- * @note If the application uses @ref BLE_GAP_DATA_LENGTH_AUTO for one or more members of
- *       p_dl_params, the SoftDevice will choose the highest value supported in current
- *       configuration and connection parameters.
- * @note  If the link PHY is Coded, the SoftDevice will ensure that the MaxTxTime and/or MaxRxTime
- *        used in the Data Length Update procedure is at least 2704 us. Otherwise, MaxTxTime and
- *        MaxRxTime will be limited to maximum 2120 us.
- *
- * @param[in]   conn_handle       Connection handle.
- * @param[in]   p_dl_params       Pointer to local parameters to be used in Data Length Update
- *                                Procedure. Set any member to @ref BLE_GAP_DATA_LENGTH_AUTO to let
- *                                the SoftDevice automatically decide the value for that member.
- *                                Set to NULL to use automatic values for all members.
- * @param[out]  p_dl_limitation   Pointer to limitation to be written when local device does not
- *                                have enough resources or does not support the requested Data Length
- *                                Update parameters. Ignored if NULL.
- *
- * @mscs
- * @mmsc{@ref BLE_GAP_DATA_LENGTH_UPDATE_PROCEDURE_MSC}
- * @endmscs
- *
- * @retval ::NRF_SUCCESS Successfully set Data Length Extension initiation/response parameters.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle parameter supplied.
- * @retval ::NRF_ERROR_INVALID_STATE No link has been established.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameters supplied.
- * @retval ::NRF_ERROR_NOT_SUPPORTED The requested parameters are not supported by the SoftDevice. Inspect
- *                                   p_dl_limitation to see which parameter is not supported.
- * @retval ::NRF_ERROR_RESOURCES The connection event length configured for this link is not sufficient for the requested parameters.
- *                               Use @ref sd_ble_cfg_set with @ref BLE_CONN_CFG_GAP to increase the connection event length.
- *                               Inspect p_dl_limitation to see where the limitation is.
- * @retval ::NRF_ERROR_BUSY Peer has already initiated a Data Length Update Procedure. Process the
- *                          pending @ref BLE_GAP_EVT_DATA_LENGTH_UPDATE_REQUEST event to respond.
- */
-SVCALL(SD_BLE_GAP_DATA_LENGTH_UPDATE, uint32_t, sd_ble_gap_data_length_update(uint16_t conn_handle, ble_gap_data_length_params_t const *p_dl_params, ble_gap_data_length_limitation_t *p_dl_limitation));
-
-/**@brief   Start the Quality of Service (QoS) channel survey module.
- *
- * @details The channel survey module provides measurements of the energy levels on
- *          the Bluetooth Low Energy channels. When the module is enabled, @ref BLE_GAP_EVT_QOS_CHANNEL_SURVEY_REPORT
- *          events will periodically report the measured energy levels for each channel.
- *
- * @note    The measurements are scheduled with lower priority than other Bluetooth Low Energy roles,
- *          Radio Timeslot API events and Flash API events.
- *
- * @note    The channel survey module will attempt to do measurements so that the average interval
- *          between measurements will be interval_us. However due to the channel survey module
- *          having the lowest priority of all roles and modules, this may not be possible. In that
- *          case fewer than expected channel survey reports may be given.
- *
- * @note    In order to use the channel survey module, @ref ble_gap_cfg_role_count_t::qos_channel_survey_role_available
- *          must be set. This is done using @ref sd_ble_cfg_set.
- *
- * @param[in]   interval_us      Requested average interval for the measurements and reports. See
- *                               @ref BLE_GAP_QOS_CHANNEL_SURVEY_INTERVALS for valid ranges. If set
- *                               to @ref BLE_GAP_QOS_CHANNEL_SURVEY_INTERVAL_CONTINUOUS, the channel
- *                               survey role will be scheduled at every available opportunity.
- *
- * @retval ::NRF_SUCCESS             The module is successfully started.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter supplied. interval_us is out of the
- *                                   allowed range.
- * @retval ::NRF_ERROR_INVALID_STATE Trying to start the module when already running.
- * @retval ::NRF_ERROR_RESOURCES     The channel survey module is not available to the application.
- *                                   Set @ref ble_gap_cfg_role_count_t::qos_channel_survey_role_available using
- *                                   @ref sd_ble_cfg_set.
- */
-SVCALL(SD_BLE_GAP_QOS_CHANNEL_SURVEY_START, uint32_t, sd_ble_gap_qos_channel_survey_start(uint32_t interval_us));
-
-/**@brief   Stop the Quality of Service (QoS) channel survey module.
- *
- * @retval ::NRF_SUCCESS             The module is successfully stopped.
- * @retval ::NRF_ERROR_INVALID_STATE Trying to stop the module when it is not running.
- */
-SVCALL(SD_BLE_GAP_QOS_CHANNEL_SURVEY_STOP, uint32_t, sd_ble_gap_qos_channel_survey_stop(void));
-
-
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif
-#endif // BLE_GAP_H__
-
-/**
-  @}
-*/
diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gatt.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gatt.h
deleted file mode 100755
index 9cb577cc..00000000
--- a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gatt.h
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- * Copyright (c) 2013 - 2018, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- *    list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form, except as embedded into a Nordic
- *    Semiconductor ASA integrated circuit in a product or a software update for
- *    such product, must reproduce the above copyright notice, this list of
- *    conditions and the following disclaimer in the documentation and/or other
- *    materials provided with the distribution.
- *
- * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
- *    contributors may be used to endorse or promote products derived from this
- *    software without specific prior written permission.
- *
- * 4. This software, with or without modification, must only be used with a
- *    Nordic Semiconductor ASA integrated circuit.
- *
- * 5. Any software provided in binary form under this license must not be reverse
- *    engineered, decompiled, modified and/or disassembled.
- *
- * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
-  @addtogroup BLE_GATT Generic Attribute Profile (GATT) Common
-  @{
-  @brief  Common definitions and prototypes for the GATT interfaces.
- */
-
-#ifndef BLE_GATT_H__
-#define BLE_GATT_H__
-
-#include <stdint.h>
-#include "nrf_svc.h"
-#include "nrf_error.h"
-#include "ble_hci.h"
-#include "ble_ranges.h"
-#include "ble_types.h"
-#include "ble_err.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @addtogroup BLE_GATT_DEFINES Defines
- * @{ */
-
-/** @brief Default ATT MTU, in bytes. */
-#define BLE_GATT_ATT_MTU_DEFAULT          23
-
-/**@brief Invalid Attribute Handle. */
-#define BLE_GATT_HANDLE_INVALID            0x0000
-
-/**@brief First Attribute Handle. */
-#define BLE_GATT_HANDLE_START              0x0001
-
-/**@brief Last Attribute Handle. */
-#define BLE_GATT_HANDLE_END                0xFFFF
-
-/** @defgroup BLE_GATT_TIMEOUT_SOURCES GATT Timeout sources
- * @{ */
-#define BLE_GATT_TIMEOUT_SRC_PROTOCOL      0x00  /**< ATT Protocol timeout. */
-/** @} */
-
-/** @defgroup BLE_GATT_WRITE_OPS GATT Write operations
- * @{ */
-#define BLE_GATT_OP_INVALID                0x00  /**< Invalid Operation. */
-#define BLE_GATT_OP_WRITE_REQ              0x01  /**< Write Request. */
-#define BLE_GATT_OP_WRITE_CMD              0x02  /**< Write Command. */
-#define BLE_GATT_OP_SIGN_WRITE_CMD         0x03  /**< Signed Write Command. */
-#define BLE_GATT_OP_PREP_WRITE_REQ         0x04  /**< Prepare Write Request. */
-#define BLE_GATT_OP_EXEC_WRITE_REQ         0x05  /**< Execute Write Request. */
-/** @} */
-
-/** @defgroup BLE_GATT_EXEC_WRITE_FLAGS GATT Execute Write flags
- * @{ */
-#define BLE_GATT_EXEC_WRITE_FLAG_PREPARED_CANCEL 0x00   /**< Cancel prepared write. */
-#define BLE_GATT_EXEC_WRITE_FLAG_PREPARED_WRITE  0x01   /**< Execute prepared write. */
-/** @} */
-
-/** @defgroup BLE_GATT_HVX_TYPES GATT Handle Value operations
- * @{ */
-#define BLE_GATT_HVX_INVALID               0x00  /**< Invalid Operation. */
-#define BLE_GATT_HVX_NOTIFICATION          0x01  /**< Handle Value Notification. */
-#define BLE_GATT_HVX_INDICATION            0x02  /**< Handle Value Indication. */
-/** @} */
-
-/** @defgroup BLE_GATT_STATUS_CODES GATT Status Codes
- * @{ */
-#define BLE_GATT_STATUS_SUCCESS                           0x0000  /**< Success. */
-#define BLE_GATT_STATUS_UNKNOWN                           0x0001  /**< Unknown or not applicable status. */
-#define BLE_GATT_STATUS_ATTERR_INVALID                    0x0100  /**< ATT Error: Invalid Error Code. */
-#define BLE_GATT_STATUS_ATTERR_INVALID_HANDLE             0x0101  /**< ATT Error: Invalid Attribute Handle. */
-#define BLE_GATT_STATUS_ATTERR_READ_NOT_PERMITTED         0x0102  /**< ATT Error: Read not permitted. */
-#define BLE_GATT_STATUS_ATTERR_WRITE_NOT_PERMITTED        0x0103  /**< ATT Error: Write not permitted. */
-#define BLE_GATT_STATUS_ATTERR_INVALID_PDU                0x0104  /**< ATT Error: Used in ATT as Invalid PDU. */
-#define BLE_GATT_STATUS_ATTERR_INSUF_AUTHENTICATION       0x0105  /**< ATT Error: Authenticated link required. */
-#define BLE_GATT_STATUS_ATTERR_REQUEST_NOT_SUPPORTED      0x0106  /**< ATT Error: Used in ATT as Request Not Supported. */
-#define BLE_GATT_STATUS_ATTERR_INVALID_OFFSET             0x0107  /**< ATT Error: Offset specified was past the end of the attribute. */
-#define BLE_GATT_STATUS_ATTERR_INSUF_AUTHORIZATION        0x0108  /**< ATT Error: Used in ATT as Insufficient Authorization. */
-#define BLE_GATT_STATUS_ATTERR_PREPARE_QUEUE_FULL         0x0109  /**< ATT Error: Used in ATT as Prepare Queue Full. */
-#define BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_FOUND        0x010A  /**< ATT Error: Used in ATT as Attribute not found. */
-#define BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_LONG         0x010B  /**< ATT Error: Attribute cannot be read or written using read/write blob requests. */
-#define BLE_GATT_STATUS_ATTERR_INSUF_ENC_KEY_SIZE         0x010C  /**< ATT Error: Encryption key size used is insufficient. */
-#define BLE_GATT_STATUS_ATTERR_INVALID_ATT_VAL_LENGTH     0x010D  /**< ATT Error: Invalid value size. */
-#define BLE_GATT_STATUS_ATTERR_UNLIKELY_ERROR             0x010E  /**< ATT Error: Very unlikely error. */
-#define BLE_GATT_STATUS_ATTERR_INSUF_ENCRYPTION           0x010F  /**< ATT Error: Encrypted link required. */
-#define BLE_GATT_STATUS_ATTERR_UNSUPPORTED_GROUP_TYPE     0x0110  /**< ATT Error: Attribute type is not a supported grouping attribute. */
-#define BLE_GATT_STATUS_ATTERR_INSUF_RESOURCES            0x0111  /**< ATT Error: Encrypted link required. */
-#define BLE_GATT_STATUS_ATTERR_RFU_RANGE1_BEGIN           0x0112  /**< ATT Error: Reserved for Future Use range #1 begin. */
-#define BLE_GATT_STATUS_ATTERR_RFU_RANGE1_END             0x017F  /**< ATT Error: Reserved for Future Use range #1 end. */
-#define BLE_GATT_STATUS_ATTERR_APP_BEGIN                  0x0180  /**< ATT Error: Application range begin. */
-#define BLE_GATT_STATUS_ATTERR_APP_END                    0x019F  /**< ATT Error: Application range end. */
-#define BLE_GATT_STATUS_ATTERR_RFU_RANGE2_BEGIN           0x01A0  /**< ATT Error: Reserved for Future Use range #2 begin. */
-#define BLE_GATT_STATUS_ATTERR_RFU_RANGE2_END             0x01DF  /**< ATT Error: Reserved for Future Use range #2 end. */
-#define BLE_GATT_STATUS_ATTERR_RFU_RANGE3_BEGIN           0x01E0  /**< ATT Error: Reserved for Future Use range #3 begin. */
-#define BLE_GATT_STATUS_ATTERR_RFU_RANGE3_END             0x01FC  /**< ATT Error: Reserved for Future Use range #3 end. */
-#define BLE_GATT_STATUS_ATTERR_CPS_WRITE_REQ_REJECTED     0x01FC  /**< ATT Common Profile and Service Error: Write request rejected. */
-#define BLE_GATT_STATUS_ATTERR_CPS_CCCD_CONFIG_ERROR      0x01FD  /**< ATT Common Profile and Service Error: Client Characteristic Configuration Descriptor improperly configured. */
-#define BLE_GATT_STATUS_ATTERR_CPS_PROC_ALR_IN_PROG       0x01FE  /**< ATT Common Profile and Service Error: Procedure Already in Progress. */
-#define BLE_GATT_STATUS_ATTERR_CPS_OUT_OF_RANGE           0x01FF  /**< ATT Common Profile and Service Error: Out Of Range. */
-/** @} */
-
-
-/** @defgroup BLE_GATT_CPF_FORMATS Characteristic Presentation Formats
- *  @note Found at http://developer.bluetooth.org/gatt/descriptors/Pages/DescriptorViewer.aspx?u=org.bluetooth.descriptor.gatt.characteristic_presentation_format.xml
- * @{ */
-#define BLE_GATT_CPF_FORMAT_RFU                 0x00 /**< Reserved For Future Use. */
-#define BLE_GATT_CPF_FORMAT_BOOLEAN             0x01 /**< Boolean. */
-#define BLE_GATT_CPF_FORMAT_2BIT                0x02 /**< Unsigned 2-bit integer. */
-#define BLE_GATT_CPF_FORMAT_NIBBLE              0x03 /**< Unsigned 4-bit integer. */
-#define BLE_GATT_CPF_FORMAT_UINT8               0x04 /**< Unsigned 8-bit integer. */
-#define BLE_GATT_CPF_FORMAT_UINT12              0x05 /**< Unsigned 12-bit integer. */
-#define BLE_GATT_CPF_FORMAT_UINT16              0x06 /**< Unsigned 16-bit integer. */
-#define BLE_GATT_CPF_FORMAT_UINT24              0x07 /**< Unsigned 24-bit integer. */
-#define BLE_GATT_CPF_FORMAT_UINT32              0x08 /**< Unsigned 32-bit integer. */
-#define BLE_GATT_CPF_FORMAT_UINT48              0x09 /**< Unsigned 48-bit integer. */
-#define BLE_GATT_CPF_FORMAT_UINT64              0x0A /**< Unsigned 64-bit integer. */
-#define BLE_GATT_CPF_FORMAT_UINT128             0x0B /**< Unsigned 128-bit integer. */
-#define BLE_GATT_CPF_FORMAT_SINT8               0x0C /**< Signed 2-bit integer. */
-#define BLE_GATT_CPF_FORMAT_SINT12              0x0D /**< Signed 12-bit integer. */
-#define BLE_GATT_CPF_FORMAT_SINT16              0x0E /**< Signed 16-bit integer. */
-#define BLE_GATT_CPF_FORMAT_SINT24              0x0F /**< Signed 24-bit integer. */
-#define BLE_GATT_CPF_FORMAT_SINT32              0x10 /**< Signed 32-bit integer. */
-#define BLE_GATT_CPF_FORMAT_SINT48              0x11 /**< Signed 48-bit integer. */
-#define BLE_GATT_CPF_FORMAT_SINT64              0x12 /**< Signed 64-bit integer. */
-#define BLE_GATT_CPF_FORMAT_SINT128             0x13 /**< Signed 128-bit integer. */
-#define BLE_GATT_CPF_FORMAT_FLOAT32             0x14 /**< IEEE-754 32-bit floating point. */
-#define BLE_GATT_CPF_FORMAT_FLOAT64             0x15 /**< IEEE-754 64-bit floating point. */
-#define BLE_GATT_CPF_FORMAT_SFLOAT              0x16 /**< IEEE-11073 16-bit SFLOAT. */
-#define BLE_GATT_CPF_FORMAT_FLOAT               0x17 /**< IEEE-11073 32-bit FLOAT. */
-#define BLE_GATT_CPF_FORMAT_DUINT16             0x18 /**< IEEE-20601 format. */
-#define BLE_GATT_CPF_FORMAT_UTF8S               0x19 /**< UTF-8 string. */
-#define BLE_GATT_CPF_FORMAT_UTF16S              0x1A /**< UTF-16 string. */
-#define BLE_GATT_CPF_FORMAT_STRUCT              0x1B /**< Opaque Structure. */
-/** @} */
-
-/** @defgroup BLE_GATT_CPF_NAMESPACES GATT Bluetooth Namespaces
- * @{
- */
-#define BLE_GATT_CPF_NAMESPACE_BTSIG            0x01 /**< Bluetooth SIG defined Namespace. */
-#define BLE_GATT_CPF_NAMESPACE_DESCRIPTION_UNKNOWN 0x0000 /**< Namespace Description Unknown. */
-/** @} */
-
-/** @} */
-
-/** @addtogroup BLE_GATT_STRUCTURES Structures
- * @{ */
-
-/**
- * @brief BLE GATT connection configuration parameters, set with @ref sd_ble_cfg_set.
- *
- * @retval ::NRF_ERROR_INVALID_PARAM att_mtu is smaller than @ref BLE_GATT_ATT_MTU_DEFAULT.
- */
-typedef struct
-{
-  uint16_t  att_mtu;          /**< Maximum size of ATT packet the SoftDevice can send or receive.
-                                   The default and minimum value is @ref BLE_GATT_ATT_MTU_DEFAULT.
-                                   @mscs
-                                   @mmsc{@ref BLE_GATTC_MTU_EXCHANGE}
-                                   @mmsc{@ref BLE_GATTS_MTU_EXCHANGE}
-                                   @endmscs
-                              */
-} ble_gatt_conn_cfg_t;
-
-/**@brief GATT Characteristic Properties. */
-typedef struct
-{
-  /* Standard properties */
-  uint8_t broadcast       :1; /**< Broadcasting of the value permitted. */
-  uint8_t read            :1; /**< Reading the value permitted. */
-  uint8_t write_wo_resp   :1; /**< Writing the value with Write Command permitted. */
-  uint8_t write           :1; /**< Writing the value with Write Request permitted. */
-  uint8_t notify          :1; /**< Notification of the value permitted. */
-  uint8_t indicate        :1; /**< Indications of the value permitted. */
-  uint8_t auth_signed_wr  :1; /**< Writing the value with Signed Write Command permitted. */
-} ble_gatt_char_props_t;
-
-/**@brief GATT Characteristic Extended Properties. */
-typedef struct
-{
-  /* Extended properties */
-  uint8_t reliable_wr     :1; /**< Writing the value with Queued Write operations permitted. */
-  uint8_t wr_aux          :1; /**< Writing the Characteristic User Description descriptor permitted. */
-} ble_gatt_char_ext_props_t;
-
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif
-#endif // BLE_GATT_H__
-
-/** @} */
diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gattc.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gattc.h
deleted file mode 100755
index 7fb39202..00000000
--- a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gattc.h
+++ /dev/null
@@ -1,715 +0,0 @@
-/*
- * Copyright (c) 2011 - 2017, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- *    list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form, except as embedded into a Nordic
- *    Semiconductor ASA integrated circuit in a product or a software update for
- *    such product, must reproduce the above copyright notice, this list of
- *    conditions and the following disclaimer in the documentation and/or other
- *    materials provided with the distribution.
- *
- * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
- *    contributors may be used to endorse or promote products derived from this
- *    software without specific prior written permission.
- *
- * 4. This software, with or without modification, must only be used with a
- *    Nordic Semiconductor ASA integrated circuit.
- *
- * 5. Any software provided in binary form under this license must not be reverse
- *    engineered, decompiled, modified and/or disassembled.
- *
- * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
-  @addtogroup BLE_GATTC Generic Attribute Profile (GATT) Client
-  @{
-  @brief  Definitions and prototypes for the GATT Client interface.
- */
-
-#ifndef BLE_GATTC_H__
-#define BLE_GATTC_H__
-
-#include <stdint.h>
-#include "nrf.h"
-#include "nrf_svc.h"
-#include "nrf_error.h"
-#include "ble_ranges.h"
-#include "ble_types.h"
-#include "ble_err.h"
-#include "ble_gatt.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @addtogroup BLE_GATTC_ENUMERATIONS Enumerations
- * @{ */
-
-/**@brief GATTC API SVC numbers. */
-enum BLE_GATTC_SVCS
-{
-  SD_BLE_GATTC_PRIMARY_SERVICES_DISCOVER = BLE_GATTC_SVC_BASE, /**< Primary Service Discovery. */
-  SD_BLE_GATTC_RELATIONSHIPS_DISCOVER,                         /**< Relationship Discovery. */
-  SD_BLE_GATTC_CHARACTERISTICS_DISCOVER,                       /**< Characteristic Discovery. */
-  SD_BLE_GATTC_DESCRIPTORS_DISCOVER,                           /**< Characteristic Descriptor Discovery. */
-  SD_BLE_GATTC_ATTR_INFO_DISCOVER,                             /**< Attribute Information Discovery. */
-  SD_BLE_GATTC_CHAR_VALUE_BY_UUID_READ,                        /**< Read Characteristic Value by UUID. */
-  SD_BLE_GATTC_READ,                                           /**< Generic read. */
-  SD_BLE_GATTC_CHAR_VALUES_READ,                               /**< Read multiple Characteristic Values. */
-  SD_BLE_GATTC_WRITE,                                          /**< Generic write. */
-  SD_BLE_GATTC_HV_CONFIRM,                                     /**< Handle Value Confirmation. */
-  SD_BLE_GATTC_EXCHANGE_MTU_REQUEST,                           /**< Exchange MTU Request. */
-};
-
-/**
- * @brief GATT Client Event IDs.
- */
-enum BLE_GATTC_EVTS
-{
-  BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP = BLE_GATTC_EVT_BASE,  /**< Primary Service Discovery Response event.          \n See @ref ble_gattc_evt_prim_srvc_disc_rsp_t.          */
-  BLE_GATTC_EVT_REL_DISC_RSP,                             /**< Relationship Discovery Response event.             \n See @ref ble_gattc_evt_rel_disc_rsp_t.                */
-  BLE_GATTC_EVT_CHAR_DISC_RSP,                            /**< Characteristic Discovery Response event.           \n See @ref ble_gattc_evt_char_disc_rsp_t.               */
-  BLE_GATTC_EVT_DESC_DISC_RSP,                            /**< Descriptor Discovery Response event.               \n See @ref ble_gattc_evt_desc_disc_rsp_t.               */
-  BLE_GATTC_EVT_ATTR_INFO_DISC_RSP,                       /**< Attribute Information Response event.              \n See @ref ble_gattc_evt_attr_info_disc_rsp_t. */
-  BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP,                /**< Read By UUID Response event.                       \n See @ref ble_gattc_evt_char_val_by_uuid_read_rsp_t.   */
-  BLE_GATTC_EVT_READ_RSP,                                 /**< Read Response event.                               \n See @ref ble_gattc_evt_read_rsp_t.                    */
-  BLE_GATTC_EVT_CHAR_VALS_READ_RSP,                       /**< Read multiple Response event.                      \n See @ref ble_gattc_evt_char_vals_read_rsp_t.          */
-  BLE_GATTC_EVT_WRITE_RSP,                                /**< Write Response event.                              \n See @ref ble_gattc_evt_write_rsp_t.                   */
-  BLE_GATTC_EVT_HVX,                                      /**< Handle Value Notification or Indication event.     \n Confirm indication with @ref sd_ble_gattc_hv_confirm.  \n See @ref ble_gattc_evt_hvx_t. */
-  BLE_GATTC_EVT_EXCHANGE_MTU_RSP,                         /**< Exchange MTU Response event.                       \n See @ref ble_gattc_evt_exchange_mtu_rsp_t.            */
-  BLE_GATTC_EVT_TIMEOUT,                                  /**< Timeout event.                                     \n See @ref ble_gattc_evt_timeout_t.                     */
-  BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE                     /**< Write without Response transmission complete.      \n See @ref ble_gattc_evt_write_cmd_tx_complete_t.       */
-};
-
-/** @} */
-
-/** @addtogroup BLE_GATTC_DEFINES Defines
- * @{ */
-
-/** @defgroup BLE_ERRORS_GATTC SVC return values specific to GATTC
- * @{ */
-#define BLE_ERROR_GATTC_PROC_NOT_PERMITTED    (NRF_GATTC_ERR_BASE + 0x000) /**< Procedure not Permitted. */
-/** @} */
-
-/** @defgroup BLE_GATTC_ATTR_INFO_FORMAT Attribute Information Formats
- * @{ */
-#define BLE_GATTC_ATTR_INFO_FORMAT_16BIT    1 /**< 16-bit Attribute Information Format. */
-#define BLE_GATTC_ATTR_INFO_FORMAT_128BIT   2 /**< 128-bit Attribute Information Format. */
-/** @} */
-
-/** @defgroup BLE_GATTC_DEFAULTS GATT Client defaults
- * @{ */
-#define BLE_GATTC_WRITE_CMD_TX_QUEUE_SIZE_DEFAULT  1 /**< Default number of Write without Response that can be queued for transmission. */
-/** @} */
-
-/** @} */
-
-/** @addtogroup BLE_GATTC_STRUCTURES Structures
- * @{ */
-
-/**
- * @brief BLE GATTC connection configuration parameters, set with @ref sd_ble_cfg_set.
- */
-typedef struct
-{
-  uint8_t  write_cmd_tx_queue_size; /**< The guaranteed minimum number of Write without Response that can be queued for transmission.
-                                          The default value is @ref BLE_GATTC_WRITE_CMD_TX_QUEUE_SIZE_DEFAULT */
-} ble_gattc_conn_cfg_t;
-
-/**@brief Operation Handle Range. */
-typedef struct
-{
-  uint16_t          start_handle; /**< Start Handle. */
-  uint16_t          end_handle;   /**< End Handle. */
-} ble_gattc_handle_range_t;
-
-
-/**@brief GATT service. */
-typedef struct
-{
-  ble_uuid_t               uuid;          /**< Service UUID. */
-  ble_gattc_handle_range_t handle_range;  /**< Service Handle Range. */
-} ble_gattc_service_t;
-
-
-/**@brief  GATT include. */
-typedef struct
-{
-  uint16_t            handle;           /**< Include Handle. */
-  ble_gattc_service_t included_srvc;    /**< Handle of the included service. */
-} ble_gattc_include_t;
-
-
-/**@brief GATT characteristic. */
-typedef struct
-{
-  ble_uuid_t              uuid;                 /**< Characteristic UUID. */
-  ble_gatt_char_props_t   char_props;           /**< Characteristic Properties. */
-  uint8_t                 char_ext_props : 1;   /**< Extended properties present. */
-  uint16_t                handle_decl;          /**< Handle of the Characteristic Declaration. */
-  uint16_t                handle_value;         /**< Handle of the Characteristic Value. */
-} ble_gattc_char_t;
-
-
-/**@brief GATT descriptor. */
-typedef struct
-{
-  uint16_t          handle;         /**< Descriptor Handle. */
-  ble_uuid_t        uuid;           /**< Descriptor UUID. */
-} ble_gattc_desc_t;
-
-
-/**@brief Write Parameters. */
-typedef struct
-{
-  uint8_t        write_op;             /**< Write Operation to be performed, see @ref BLE_GATT_WRITE_OPS. */
-  uint8_t        flags;                /**< Flags, see @ref BLE_GATT_EXEC_WRITE_FLAGS. */
-  uint16_t       handle;               /**< Handle to the attribute to be written. */
-  uint16_t       offset;               /**< Offset in bytes. @note For WRITE_CMD and WRITE_REQ, offset must be 0. */
-  uint16_t       len;                  /**< Length of data in bytes. */
-  uint8_t const *p_value;              /**< Pointer to the value data. */
-} ble_gattc_write_params_t;
-
-/**@brief Attribute Information for 16-bit Attribute UUID. */
-typedef struct
-{
-  uint16_t       handle;               /**< Attribute handle. */
-  ble_uuid_t     uuid;                 /**< 16-bit Attribute UUID. */
-} ble_gattc_attr_info16_t;
-
-/**@brief Attribute Information for 128-bit Attribute UUID. */
-typedef struct
-{
-  uint16_t       handle;               /**< Attribute handle. */
-  ble_uuid128_t  uuid;                 /**< 128-bit Attribute UUID. */
-} ble_gattc_attr_info128_t;
-
-/**@brief Event structure for @ref BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP. */
-typedef struct
-{
-  uint16_t             count;           /**< Service count. */
-  ble_gattc_service_t services[1];      /**< Service data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
-                                             See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
-} ble_gattc_evt_prim_srvc_disc_rsp_t;
-
-/**@brief Event structure for @ref BLE_GATTC_EVT_REL_DISC_RSP. */
-typedef struct
-{
-  uint16_t             count;           /**< Include count. */
-  ble_gattc_include_t includes[1];      /**< Include data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
-                                             See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
-} ble_gattc_evt_rel_disc_rsp_t;
-
-/**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_DISC_RSP. */
-typedef struct
-{
-  uint16_t            count;          /**< Characteristic count. */
-  ble_gattc_char_t    chars[1];       /**< Characteristic data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
-                                           See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
-} ble_gattc_evt_char_disc_rsp_t;
-
-/**@brief Event structure for @ref BLE_GATTC_EVT_DESC_DISC_RSP. */
-typedef struct
-{
-  uint16_t            count;          /**< Descriptor count. */
-  ble_gattc_desc_t    descs[1];       /**< Descriptor data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
-                                           See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
-} ble_gattc_evt_desc_disc_rsp_t;
-
-/**@brief Event structure for @ref BLE_GATTC_EVT_ATTR_INFO_DISC_RSP. */
-typedef struct
-{
-  uint16_t                     count;            /**< Attribute count. */
-  uint8_t                      format;           /**< Attribute information format, see @ref BLE_GATTC_ATTR_INFO_FORMAT. */
-  union {
-    ble_gattc_attr_info16_t  attr_info16[1];     /**< Attribute information for 16-bit Attribute UUID.
-                                                      @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
-                                                      See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
-    ble_gattc_attr_info128_t attr_info128[1];    /**< Attribute information for 128-bit Attribute UUID.
-                                                      @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
-                                                      See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
-  } info;                                        /**< Attribute information union. */
-} ble_gattc_evt_attr_info_disc_rsp_t;
-
-/**@brief GATT read by UUID handle value pair. */
-typedef struct
-{
-  uint16_t            handle;          /**< Attribute Handle. */
-  uint8_t            *p_value;         /**< Pointer to the Attribute Value, length is available in @ref ble_gattc_evt_char_val_by_uuid_read_rsp_t::value_len. */
-} ble_gattc_handle_value_t;
-
-/**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP. */
-typedef struct
-{
-  uint16_t                  count;            /**< Handle-Value Pair Count. */
-  uint16_t                  value_len;        /**< Length of the value in Handle-Value(s) list. */
-  uint8_t                   handle_value[1];  /**< Handle-Value(s) list. To iterate through the list use @ref sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter.
-                                                   @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
-                                                   See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
-} ble_gattc_evt_char_val_by_uuid_read_rsp_t;
-
-/**@brief Event structure for @ref BLE_GATTC_EVT_READ_RSP. */
-typedef struct
-{
-  uint16_t            handle;         /**< Attribute Handle. */
-  uint16_t            offset;         /**< Offset of the attribute data. */
-  uint16_t            len;            /**< Attribute data length. */
-  uint8_t             data[1];        /**< Attribute data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
-                                           See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
-} ble_gattc_evt_read_rsp_t;
-
-/**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_VALS_READ_RSP. */
-typedef struct
-{
-  uint16_t            len;            /**< Concatenated Attribute values length. */
-  uint8_t             values[1];      /**< Attribute values. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
-                                           See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
-} ble_gattc_evt_char_vals_read_rsp_t;
-
-/**@brief Event structure for @ref BLE_GATTC_EVT_WRITE_RSP. */
-typedef struct
-{
-  uint16_t            handle;           /**< Attribute Handle. */
-  uint8_t             write_op;         /**< Type of write operation, see @ref BLE_GATT_WRITE_OPS. */
-  uint16_t            offset;           /**< Data offset. */
-  uint16_t            len;              /**< Data length. */
-  uint8_t             data[1];          /**< Data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
-                                             See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
-} ble_gattc_evt_write_rsp_t;
-
-/**@brief Event structure for @ref BLE_GATTC_EVT_HVX. */
-typedef struct
-{
-  uint16_t            handle;         /**< Handle to which the HVx operation applies. */
-  uint8_t             type;           /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */
-  uint16_t            len;            /**< Attribute data length. */
-  uint8_t             data[1];        /**< Attribute data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
-                                           See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
-} ble_gattc_evt_hvx_t;
-
-/**@brief Event structure for @ref BLE_GATTC_EVT_EXCHANGE_MTU_RSP. */
-typedef struct
-{
-  uint16_t          server_rx_mtu;            /**< Server RX MTU size. */
-} ble_gattc_evt_exchange_mtu_rsp_t;
-
-/**@brief Event structure for @ref BLE_GATTC_EVT_TIMEOUT. */
-typedef struct
-{
-  uint8_t          src;                       /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */
-} ble_gattc_evt_timeout_t;
-
-/**@brief Event structure for @ref BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE. */
-typedef struct
-{
-  uint8_t             count;            /**< Number of write without response transmissions completed. */
-} ble_gattc_evt_write_cmd_tx_complete_t;
-
-/**@brief GATTC event structure. */
-typedef struct
-{
-  uint16_t            conn_handle;                /**< Connection Handle on which event occurred. */
-  uint16_t            gatt_status;                /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */
-  uint16_t            error_handle;               /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */
-  union
-  {
-    ble_gattc_evt_prim_srvc_disc_rsp_t          prim_srvc_disc_rsp;         /**< Primary Service Discovery Response Event Parameters. */
-    ble_gattc_evt_rel_disc_rsp_t                rel_disc_rsp;               /**< Relationship Discovery Response Event Parameters. */
-    ble_gattc_evt_char_disc_rsp_t               char_disc_rsp;              /**< Characteristic Discovery Response Event Parameters. */
-    ble_gattc_evt_desc_disc_rsp_t               desc_disc_rsp;              /**< Descriptor Discovery Response Event Parameters. */
-    ble_gattc_evt_char_val_by_uuid_read_rsp_t   char_val_by_uuid_read_rsp;  /**< Characteristic Value Read by UUID Response Event Parameters. */
-    ble_gattc_evt_read_rsp_t                    read_rsp;                   /**< Read Response Event Parameters. */
-    ble_gattc_evt_char_vals_read_rsp_t          char_vals_read_rsp;         /**< Characteristic Values Read Response Event Parameters. */
-    ble_gattc_evt_write_rsp_t                   write_rsp;                  /**< Write Response Event Parameters. */
-    ble_gattc_evt_hvx_t                         hvx;                        /**< Handle Value Notification/Indication Event Parameters. */
-    ble_gattc_evt_exchange_mtu_rsp_t            exchange_mtu_rsp;           /**< Exchange MTU Response Event Parameters. */
-    ble_gattc_evt_timeout_t                     timeout;                    /**< Timeout Event Parameters. */
-    ble_gattc_evt_attr_info_disc_rsp_t          attr_info_disc_rsp;         /**< Attribute Information Discovery Event Parameters. */
-    ble_gattc_evt_write_cmd_tx_complete_t       write_cmd_tx_complete;      /**< Write without Response transmission complete Event Parameters. */
-  } params;                                                                 /**< Event Parameters. @note Only valid if @ref gatt_status == @ref BLE_GATT_STATUS_SUCCESS. */
-} ble_gattc_evt_t;
-/** @} */
-
-/** @addtogroup BLE_GATTC_FUNCTIONS Functions
- * @{ */
-
-/**@brief Initiate or continue a GATT Primary Service Discovery procedure.
- *
- * @details This function initiates or resumes a Primary Service discovery procedure, starting from the supplied handle.
- *          If the last service has not been reached, this function must be called again with an updated start handle value to continue the search.
- *
- * @note If any of the discovered services have 128-bit UUIDs which are not present in the table provided to ble_vs_uuids_assign, a UUID structure with
- *       type @ref BLE_UUID_TYPE_UNKNOWN will be received in the corresponding event.
- *
- * @events
- * @event{@ref BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_GATTC_PRIM_SRVC_DISC_MSC}
- * @endmscs
- *
- * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
- * @param[in] start_handle Handle to start searching from.
- * @param[in] p_srvc_uuid Pointer to the service UUID to be found. If it is NULL, all primary services will be returned.
- *
- * @retval ::NRF_SUCCESS Successfully started or resumed the Primary Service Discovery procedure.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
- * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection.
- */
-SVCALL(SD_BLE_GATTC_PRIMARY_SERVICES_DISCOVER, uint32_t, sd_ble_gattc_primary_services_discover(uint16_t conn_handle, uint16_t start_handle, ble_uuid_t const *p_srvc_uuid));
-
-
-/**@brief Initiate or continue a GATT Relationship Discovery procedure.
- *
- * @details This function initiates or resumes the Find Included Services sub-procedure. If the last included service has not been reached,
- *          this must be called again with an updated handle range to continue the search.
- *
- * @events
- * @event{@ref BLE_GATTC_EVT_REL_DISC_RSP}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_GATTC_REL_DISC_MSC}
- * @endmscs
- *
- * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
- * @param[in] p_handle_range A pointer to the range of handles of the Service to perform this procedure on.
- *
- * @retval ::NRF_SUCCESS Successfully started or resumed the Relationship Discovery procedure.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
- * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection.
- */
-SVCALL(SD_BLE_GATTC_RELATIONSHIPS_DISCOVER, uint32_t, sd_ble_gattc_relationships_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range));
-
-
-/**@brief Initiate or continue a GATT Characteristic Discovery procedure.
- *
- * @details This function initiates or resumes a Characteristic discovery procedure. If the last Characteristic has not been reached,
- *          this must be called again with an updated handle range to continue the discovery.
- *
- * @note If any of the discovered characteristics have 128-bit UUIDs which are not present in the table provided to ble_vs_uuids_assign, a UUID structure with
- *       type @ref BLE_UUID_TYPE_UNKNOWN will be received in the corresponding event.
- *
- * @events
- * @event{@ref BLE_GATTC_EVT_CHAR_DISC_RSP}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_GATTC_CHAR_DISC_MSC}
- * @endmscs
- *
- * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
- * @param[in] p_handle_range A pointer to the range of handles of the Service to perform this procedure on.
- *
- * @retval ::NRF_SUCCESS Successfully started or resumed the Characteristic Discovery procedure.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
- * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection.
- */
-SVCALL(SD_BLE_GATTC_CHARACTERISTICS_DISCOVER, uint32_t, sd_ble_gattc_characteristics_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range));
-
-
-/**@brief Initiate or continue a GATT Characteristic Descriptor Discovery procedure.
- *
- * @details This function initiates or resumes a Characteristic Descriptor discovery procedure. If the last Descriptor has not been reached,
- *          this must be called again with an updated handle range to continue the discovery.
- *
- * @events
- * @event{@ref BLE_GATTC_EVT_DESC_DISC_RSP}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_GATTC_DESC_DISC_MSC}
- * @endmscs
- *
- * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
- * @param[in] p_handle_range A pointer to the range of handles of the Characteristic to perform this procedure on.
- *
- * @retval ::NRF_SUCCESS Successfully started or resumed the Descriptor Discovery procedure.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
- * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection.
- */
-SVCALL(SD_BLE_GATTC_DESCRIPTORS_DISCOVER, uint32_t, sd_ble_gattc_descriptors_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range));
-
-
-/**@brief Initiate or continue a GATT Read using Characteristic UUID procedure.
- *
- * @details This function initiates or resumes a Read using Characteristic UUID procedure. If the last Characteristic has not been reached,
- *          this must be called again with an updated handle range to continue the discovery.
- *
- * @events
- * @event{@ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_GATTC_READ_UUID_MSC}
- * @endmscs
- *
- * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
- * @param[in] p_uuid Pointer to a Characteristic value UUID to read.
- * @param[in] p_handle_range A pointer to the range of handles to perform this procedure on.
- *
- * @retval ::NRF_SUCCESS Successfully started or resumed the Read using Characteristic UUID procedure.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
- * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection.
- */
-SVCALL(SD_BLE_GATTC_CHAR_VALUE_BY_UUID_READ, uint32_t, sd_ble_gattc_char_value_by_uuid_read(uint16_t conn_handle, ble_uuid_t const *p_uuid, ble_gattc_handle_range_t const *p_handle_range));
-
-
-/**@brief Initiate or continue a GATT Read (Long) Characteristic or Descriptor procedure.
- *
- * @details This function initiates or resumes a GATT Read (Long) Characteristic or Descriptor procedure. If the Characteristic or Descriptor
- *          to be read is longer than ATT_MTU - 1, this function must be called multiple times with appropriate offset to read the
- *          complete value.
- *
- * @events
- * @event{@ref BLE_GATTC_EVT_READ_RSP}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_GATTC_VALUE_READ_MSC}
- * @endmscs
- *
- * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
- * @param[in] handle The handle of the attribute to be read.
- * @param[in] offset Offset into the attribute value to be read.
- *
- * @retval ::NRF_SUCCESS Successfully started or resumed the Read (Long) procedure.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
- * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
- * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection.
- */
-SVCALL(SD_BLE_GATTC_READ, uint32_t, sd_ble_gattc_read(uint16_t conn_handle, uint16_t handle, uint16_t offset));
-
-
-/**@brief Initiate a GATT Read Multiple Characteristic Values procedure.
- *
- * @details This function initiates a GATT Read Multiple Characteristic Values procedure.
- *
- * @events
- * @event{@ref BLE_GATTC_EVT_CHAR_VALS_READ_RSP}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_GATTC_READ_MULT_MSC}
- * @endmscs
- *
- * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
- * @param[in] p_handles A pointer to the handle(s) of the attribute(s) to be read.
- * @param[in] handle_count The number of handles in p_handles.
- *
- * @retval ::NRF_SUCCESS Successfully started the Read Multiple Characteristic Values procedure.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
- * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection.
- */
-SVCALL(SD_BLE_GATTC_CHAR_VALUES_READ, uint32_t, sd_ble_gattc_char_values_read(uint16_t conn_handle, uint16_t const *p_handles, uint16_t handle_count));
-
-
-/**@brief Perform a Write (Characteristic Value or Descriptor, with or without response, signed or not, long or reliable) procedure.
- *
- * @details This function can perform all write procedures described in GATT.
- *
- * @note    Only one write with response procedure can be ongoing per connection at a time.
- *          If the application tries to write with response while another write with response procedure is ongoing,
- *          the function call will return @ref NRF_ERROR_BUSY.
- *          A @ref BLE_GATTC_EVT_WRITE_RSP event will be issued as soon as the write response arrives from the peer.
- *
- * @note    The number of Write without Response that can be queued is configured by @ref ble_gattc_conn_cfg_t::write_cmd_tx_queue_size
- *          When the queue is full, the function call will return @ref NRF_ERROR_RESOURCES.
- *          A @ref BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE event will be issued as soon as the transmission of the write without response is complete.
- *
- * @note    The application can keep track of the available queue element count for writes without responses by following the procedure below:
- *          - Store initial queue element count in a variable.
- *          - Decrement the variable, which stores the currently available queue element count, by one when a call to this function returns @ref NRF_SUCCESS.
- *          - Increment the variable, which stores the current available queue element count, by the count variable in @ref BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE event.
- *
- * @events
- * @event{@ref BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE, Write without response transmission complete.}
- * @event{@ref BLE_GATTC_EVT_WRITE_RSP, Write response received from the peer.}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_GATTC_VALUE_WRITE_WITHOUT_RESP_MSC}
- * @mmsc{@ref BLE_GATTC_VALUE_WRITE_MSC}
- * @mmsc{@ref BLE_GATTC_VALUE_LONG_WRITE_MSC}
- * @mmsc{@ref BLE_GATTC_VALUE_RELIABLE_WRITE_MSC}
- * @endmscs
- *
- * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
- * @param[in] p_write_params A pointer to a write parameters structure.
- *
- * @retval ::NRF_SUCCESS Successfully started the Write procedure.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied.
- * @retval ::NRF_ERROR_BUSY For write with response, procedure already in progress. Wait for a @ref BLE_GATTC_EVT_WRITE_RSP event and retry.
- * @retval ::NRF_ERROR_RESOURCES Too many writes without responses queued.
- *                               Wait for a @ref BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE event and retry.
- * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection.
- */
-SVCALL(SD_BLE_GATTC_WRITE, uint32_t, sd_ble_gattc_write(uint16_t conn_handle, ble_gattc_write_params_t const *p_write_params));
-
-
-/**@brief Send a Handle Value Confirmation to the GATT Server.
- *
- * @mscs
- * @mmsc{@ref BLE_GATTC_HVI_MSC}
- * @endmscs
- *
- * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
- * @param[in] handle The handle of the attribute in the indication.
- *
- * @retval ::NRF_SUCCESS Successfully queued the Handle Value Confirmation for transmission.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State or no Indication pending to be confirmed.
- * @retval ::BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle.
- * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection.
- */
-SVCALL(SD_BLE_GATTC_HV_CONFIRM, uint32_t, sd_ble_gattc_hv_confirm(uint16_t conn_handle, uint16_t handle));
-
-/**@brief Discovers information about a range of attributes on a GATT server.
- *
- * @events
- * @event{@ref BLE_GATTC_EVT_ATTR_INFO_DISC_RSP, Generated when information about a range of attributes has been received.}
- * @endevents
- *
- * @param[in] conn_handle    The connection handle identifying the connection to perform this procedure on.
- * @param[in] p_handle_range The range of handles to request information about.
- *
- * @retval ::NRF_SUCCESS Successfully started an attribute information discovery procedure.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid connection state
- * @retval ::NRF_ERROR_INVALID_ADDR  Invalid pointer supplied.
- * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
- * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection.
- */
-SVCALL(SD_BLE_GATTC_ATTR_INFO_DISCOVER, uint32_t, sd_ble_gattc_attr_info_discover(uint16_t conn_handle, ble_gattc_handle_range_t const * p_handle_range));
-
-/**@brief Start an ATT_MTU exchange by sending an Exchange MTU Request to the server.
- *
- * @details The SoftDevice sets ATT_MTU to the minimum of:
- *          - The Client RX MTU value, and
- *          - The Server RX MTU value from @ref BLE_GATTC_EVT_EXCHANGE_MTU_RSP.
- *
- *          However, the SoftDevice never sets ATT_MTU lower than @ref BLE_GATT_ATT_MTU_DEFAULT.
- *
- * @events
- * @event{@ref BLE_GATTC_EVT_EXCHANGE_MTU_RSP}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_GATTC_MTU_EXCHANGE}
- * @endmscs
- *
- * @param[in] conn_handle    The connection handle identifying the connection to perform this procedure on.
- * @param[in] client_rx_mtu  Client RX MTU size.
- *                           - The minimum value is @ref BLE_GATT_ATT_MTU_DEFAULT.
- *                           - The maximum value is @ref ble_gatt_conn_cfg_t::att_mtu in the connection configuration
-                               used for this connection.
- *                           - The value must be equal to Server RX MTU size given in @ref sd_ble_gatts_exchange_mtu_reply
- *                             if an ATT_MTU exchange has already been performed in the other direction.
- *
- * @retval ::NRF_SUCCESS Successfully sent request to the server.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid connection state or an ATT_MTU exchange was already requested once.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid Client RX MTU size supplied.
- * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
- * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection.
- */
-SVCALL(SD_BLE_GATTC_EXCHANGE_MTU_REQUEST, uint32_t, sd_ble_gattc_exchange_mtu_request(uint16_t conn_handle, uint16_t client_rx_mtu));
-
-/**@brief Iterate through Handle-Value(s) list in @ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP event.
- *
- * @param[in] p_gattc_evt  Pointer to event buffer containing @ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP event.
- *                         @note If the buffer contains different event, behavior is undefined.
- * @param[in,out] p_iter   Iterator, points to @ref ble_gattc_handle_value_t structure that will be filled in with
- *                         the next Handle-Value pair in each iteration. If the function returns other than
- *                         @ref NRF_SUCCESS, it will not be changed.
- *                         - To start iteration, initialize the structure to zero.
- *                         - To continue, pass the value from previous iteration.
- *
- * \code
- * ble_gattc_handle_value_t iter;
- * memset(&iter, 0, sizeof(ble_gattc_handle_value_t));
- * while (sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter(&ble_evt.evt.gattc_evt, &iter) == NRF_SUCCESS)
- * {
- *   app_handle = iter.handle;
- *   memcpy(app_value, iter.p_value, ble_evt.evt.gattc_evt.params.char_val_by_uuid_read_rsp.value_len);
- * }
- * \endcode
- *
- * @retval ::NRF_SUCCESS Successfully retrieved the next Handle-Value pair.
- * @retval ::NRF_ERROR_NOT_FOUND No more Handle-Value pairs available in the list.
- */
-__STATIC_INLINE uint32_t sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter(ble_gattc_evt_t *p_gattc_evt, ble_gattc_handle_value_t *p_iter);
-
-/** @} */
-
-#ifndef SUPPRESS_INLINE_IMPLEMENTATION
-
-__STATIC_INLINE uint32_t sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter(ble_gattc_evt_t *p_gattc_evt, ble_gattc_handle_value_t *p_iter)
-{
-  uint32_t value_len = p_gattc_evt->params.char_val_by_uuid_read_rsp.value_len;
-  uint8_t *p_first = p_gattc_evt->params.char_val_by_uuid_read_rsp.handle_value;
-  uint8_t *p_next = p_iter->p_value ? p_iter->p_value + value_len : p_first;
-
-  if ((p_next - p_first) / (sizeof(uint16_t) + value_len) < p_gattc_evt->params.char_val_by_uuid_read_rsp.count)
-  {
-    p_iter->handle = (uint16_t)p_next[1] << 8 | p_next[0];
-    p_iter->p_value = p_next + sizeof(uint16_t);
-    return NRF_SUCCESS;
-  }
-  else
-  {
-    return NRF_ERROR_NOT_FOUND;
-  }
-}
-
-#endif /* SUPPRESS_INLINE_IMPLEMENTATION */
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* BLE_GATTC_H__ */
-
-/**
-  @}
-*/
diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gatts.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gatts.h
deleted file mode 100755
index 394d8d18..00000000
--- a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gatts.h
+++ /dev/null
@@ -1,845 +0,0 @@
-/*
- * Copyright (c) 2011 - 2018, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- *    list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form, except as embedded into a Nordic
- *    Semiconductor ASA integrated circuit in a product or a software update for
- *    such product, must reproduce the above copyright notice, this list of
- *    conditions and the following disclaimer in the documentation and/or other
- *    materials provided with the distribution.
- *
- * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
- *    contributors may be used to endorse or promote products derived from this
- *    software without specific prior written permission.
- *
- * 4. This software, with or without modification, must only be used with a
- *    Nordic Semiconductor ASA integrated circuit.
- *
- * 5. Any software provided in binary form under this license must not be reverse
- *    engineered, decompiled, modified and/or disassembled.
- *
- * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
-  @addtogroup BLE_GATTS Generic Attribute Profile (GATT) Server
-  @{
-  @brief  Definitions and prototypes for the GATTS interface.
- */
-
-#ifndef BLE_GATTS_H__
-#define BLE_GATTS_H__
-
-#include <stdint.h>
-#include "nrf_svc.h"
-#include "nrf_error.h"
-#include "ble_hci.h"
-#include "ble_ranges.h"
-#include "ble_types.h"
-#include "ble_err.h"
-#include "ble_gatt.h"
-#include "ble_gap.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @addtogroup BLE_GATTS_ENUMERATIONS Enumerations
- * @{ */
-
-/**
- * @brief GATTS API SVC numbers.
- */
-enum BLE_GATTS_SVCS
-{
-  SD_BLE_GATTS_SERVICE_ADD = BLE_GATTS_SVC_BASE, /**< Add a service. */
-  SD_BLE_GATTS_INCLUDE_ADD,                      /**< Add an included service. */
-  SD_BLE_GATTS_CHARACTERISTIC_ADD,               /**< Add a characteristic. */
-  SD_BLE_GATTS_DESCRIPTOR_ADD,                   /**< Add a generic attribute. */
-  SD_BLE_GATTS_VALUE_SET,                        /**< Set an attribute value. */
-  SD_BLE_GATTS_VALUE_GET,                        /**< Get an attribute value. */
-  SD_BLE_GATTS_HVX,                              /**< Handle Value Notification or Indication. */
-  SD_BLE_GATTS_SERVICE_CHANGED,                  /**< Perform a Service Changed Indication to one or more peers. */
-  SD_BLE_GATTS_RW_AUTHORIZE_REPLY,               /**< Reply to an authorization request for a read or write operation on one or more attributes. */
-  SD_BLE_GATTS_SYS_ATTR_SET,                     /**< Set the persistent system attributes for a connection. */
-  SD_BLE_GATTS_SYS_ATTR_GET,                     /**< Retrieve the persistent system attributes. */
-  SD_BLE_GATTS_INITIAL_USER_HANDLE_GET,          /**< Retrieve the first valid user handle. */
-  SD_BLE_GATTS_ATTR_GET,                         /**< Retrieve the UUID and/or metadata of an attribute. */
-  SD_BLE_GATTS_EXCHANGE_MTU_REPLY                /**< Reply to Exchange MTU Request. */
-};
-
-/**
- * @brief GATT Server Event IDs.
- */
-enum BLE_GATTS_EVTS
-{
-  BLE_GATTS_EVT_WRITE = BLE_GATTS_EVT_BASE,       /**< Write operation performed.                                           \n See @ref ble_gatts_evt_write_t.                 */
-  BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST,             /**< Read/Write Authorization request.                                    \n Reply with @ref sd_ble_gatts_rw_authorize_reply. \n See @ref ble_gatts_evt_rw_authorize_request_t. */
-  BLE_GATTS_EVT_SYS_ATTR_MISSING,                 /**< A persistent system attribute access is pending.                     \n Respond with @ref sd_ble_gatts_sys_attr_set.     \n See @ref ble_gatts_evt_sys_attr_missing_t.     */
-  BLE_GATTS_EVT_HVC,                              /**< Handle Value Confirmation.                                           \n See @ref ble_gatts_evt_hvc_t.                   */
-  BLE_GATTS_EVT_SC_CONFIRM,                       /**< Service Changed Confirmation.                                        \n No additional event structure applies.          */
-  BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST,             /**< Exchange MTU Request.                                                \n Reply with @ref sd_ble_gatts_exchange_mtu_reply. \n See @ref ble_gatts_evt_exchange_mtu_request_t. */
-  BLE_GATTS_EVT_TIMEOUT,                          /**< Peer failed to respond to an ATT request in time.                    \n See @ref ble_gatts_evt_timeout_t.               */
-  BLE_GATTS_EVT_HVN_TX_COMPLETE                   /**< Handle Value Notification transmission complete.                     \n See @ref ble_gatts_evt_hvn_tx_complete_t.       */
-};
-
-/**@brief GATTS Configuration IDs.
- *
- * IDs that uniquely identify a GATTS configuration.
- */
-enum BLE_GATTS_CFGS
-{
-  BLE_GATTS_CFG_SERVICE_CHANGED = BLE_GATTS_CFG_BASE, /**< Service changed configuration. */
-  BLE_GATTS_CFG_ATTR_TAB_SIZE,                        /**< Attribute table size configuration. */
-};
-
-/** @} */
-
-/** @addtogroup BLE_GATTS_DEFINES Defines
- * @{ */
-
-/** @defgroup BLE_ERRORS_GATTS SVC return values specific to GATTS
- * @{ */
-#define BLE_ERROR_GATTS_INVALID_ATTR_TYPE   (NRF_GATTS_ERR_BASE + 0x000) /**< Invalid attribute type. */
-#define BLE_ERROR_GATTS_SYS_ATTR_MISSING    (NRF_GATTS_ERR_BASE + 0x001) /**< System Attributes missing. */
-/** @} */
-
-/** @defgroup BLE_GATTS_ATTR_LENS_MAX Maximum attribute lengths
- * @{ */
-#define BLE_GATTS_FIX_ATTR_LEN_MAX (510)  /**< Maximum length for fixed length Attribute Values. */
-#define BLE_GATTS_VAR_ATTR_LEN_MAX (512)  /**< Maximum length for variable length Attribute Values. */
-/** @} */
-
-/** @defgroup BLE_GATTS_SRVC_TYPES GATT Server Service Types
- * @{ */
-#define BLE_GATTS_SRVC_TYPE_INVALID          0x00  /**< Invalid Service Type. */
-#define BLE_GATTS_SRVC_TYPE_PRIMARY          0x01  /**< Primary Service. */
-#define BLE_GATTS_SRVC_TYPE_SECONDARY        0x02  /**< Secondary Type. */
-/** @} */
-
-
-/** @defgroup BLE_GATTS_ATTR_TYPES GATT Server Attribute Types
- * @{ */
-#define BLE_GATTS_ATTR_TYPE_INVALID         0x00  /**< Invalid Attribute Type. */
-#define BLE_GATTS_ATTR_TYPE_PRIM_SRVC_DECL  0x01  /**< Primary Service Declaration. */
-#define BLE_GATTS_ATTR_TYPE_SEC_SRVC_DECL   0x02  /**< Secondary Service Declaration. */
-#define BLE_GATTS_ATTR_TYPE_INC_DECL        0x03  /**< Include Declaration. */
-#define BLE_GATTS_ATTR_TYPE_CHAR_DECL       0x04  /**< Characteristic Declaration. */
-#define BLE_GATTS_ATTR_TYPE_CHAR_VAL        0x05  /**< Characteristic Value. */
-#define BLE_GATTS_ATTR_TYPE_DESC            0x06  /**< Descriptor. */
-#define BLE_GATTS_ATTR_TYPE_OTHER           0x07  /**< Other, non-GATT specific type. */
-/** @} */
-
-
-/** @defgroup BLE_GATTS_OPS GATT Server Operations
- * @{ */
-#define BLE_GATTS_OP_INVALID                0x00  /**< Invalid Operation. */
-#define BLE_GATTS_OP_WRITE_REQ              0x01  /**< Write Request. */
-#define BLE_GATTS_OP_WRITE_CMD              0x02  /**< Write Command. */
-#define BLE_GATTS_OP_SIGN_WRITE_CMD         0x03  /**< Signed Write Command. */
-#define BLE_GATTS_OP_PREP_WRITE_REQ         0x04  /**< Prepare Write Request. */
-#define BLE_GATTS_OP_EXEC_WRITE_REQ_CANCEL  0x05  /**< Execute Write Request: Cancel all prepared writes. */
-#define BLE_GATTS_OP_EXEC_WRITE_REQ_NOW     0x06  /**< Execute Write Request: Immediately execute all prepared writes. */
-/** @} */
-
-/** @defgroup BLE_GATTS_VLOCS GATT Value Locations
- * @{ */
-#define BLE_GATTS_VLOC_INVALID       0x00  /**< Invalid Location. */
-#define BLE_GATTS_VLOC_STACK         0x01  /**< Attribute Value is located in stack memory, no user memory is required. */
-#define BLE_GATTS_VLOC_USER          0x02  /**< Attribute Value is located in user memory. This requires the user to maintain a valid buffer through the lifetime of the attribute, since the stack
-                                                will read and write directly to the memory using the pointer provided in the APIs. There are no alignment requirements for the buffer. */
-/** @} */
-
-/** @defgroup BLE_GATTS_AUTHORIZE_TYPES GATT Server Authorization Types
- * @{ */
-#define BLE_GATTS_AUTHORIZE_TYPE_INVALID    0x00  /**< Invalid Type. */
-#define BLE_GATTS_AUTHORIZE_TYPE_READ       0x01  /**< Authorize a Read Operation. */
-#define BLE_GATTS_AUTHORIZE_TYPE_WRITE      0x02  /**< Authorize a Write Request Operation. */
-/** @} */
-
-/** @defgroup BLE_GATTS_SYS_ATTR_FLAGS System Attribute Flags
- * @{ */
-#define BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS (1 << 0)  /**< Restrict system attributes to system services only. */
-#define BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS (1 << 1)  /**< Restrict system attributes to user services only. */
-/** @} */
-
-/** @defgroup BLE_GATTS_SERVICE_CHANGED Service Changed Inclusion Values
- * @{
- */
-#define BLE_GATTS_SERVICE_CHANGED_DEFAULT   (1)   /**< Default is to include the Service Changed characteristic in the Attribute Table. */
-/** @} */
-
-/** @defgroup BLE_GATTS_ATTR_TAB_SIZE Attribute Table size
- * @{
- */
-#define BLE_GATTS_ATTR_TAB_SIZE_MIN         (248)  /**< Minimum Attribute Table size */
-#define BLE_GATTS_ATTR_TAB_SIZE_DEFAULT     (1408) /**< Default Attribute Table size. */
-/** @} */
-
-/** @defgroup BLE_GATTS_DEFAULTS GATT Server defaults
- * @{
- */
-#define BLE_GATTS_HVN_TX_QUEUE_SIZE_DEFAULT  1 /**< Default number of Handle Value Notifications that can be queued for transmission. */
-/** @} */
-
-/** @} */
-
-/** @addtogroup BLE_GATTS_STRUCTURES Structures
- * @{ */
-
-/**
- * @brief BLE GATTS connection configuration parameters, set with @ref sd_ble_cfg_set.
- */
-typedef struct
-{
-  uint8_t  hvn_tx_queue_size; /**< Minimum guaranteed number of Handle Value Notifications that can be queued for transmission.
-                                    The default value is @ref BLE_GATTS_HVN_TX_QUEUE_SIZE_DEFAULT */
-} ble_gatts_conn_cfg_t;
-
-/**@brief Attribute metadata. */
-typedef struct
-{
-  ble_gap_conn_sec_mode_t read_perm;       /**< Read permissions. */
-  ble_gap_conn_sec_mode_t write_perm;      /**< Write permissions. */
-  uint8_t                 vlen       :1;   /**< Variable length attribute. */
-  uint8_t                 vloc       :2;   /**< Value location, see @ref BLE_GATTS_VLOCS.*/
-  uint8_t                 rd_auth    :1;   /**< Read authorization and value will be requested from the application on every read operation. */
-  uint8_t                 wr_auth    :1;   /**< Write authorization will be requested from the application on every Write Request operation (but not Write Command). */
-} ble_gatts_attr_md_t;
-
-
-/**@brief GATT Attribute. */
-typedef struct
-{
-  ble_uuid_t const          *p_uuid;        /**< Pointer to the attribute UUID. */
-  ble_gatts_attr_md_t const *p_attr_md;     /**< Pointer to the attribute metadata structure. */
-  uint16_t                   init_len;      /**< Initial attribute value length in bytes. */
-  uint16_t                   init_offs;     /**< Initial attribute value offset in bytes. If different from zero, the first init_offs bytes of the attribute value will be left uninitialized. */
-  uint16_t                   max_len;       /**< Maximum attribute value length in bytes, see @ref BLE_GATTS_ATTR_LENS_MAX for maximum values. */
-  uint8_t                   *p_value;       /**< Pointer to the attribute data. Please note that if the @ref BLE_GATTS_VLOC_USER value location is selected in the attribute metadata, this will have to point to a buffer
-                                                 that remains valid through the lifetime of the attribute. This excludes usage of automatic variables that may go out of scope or any other temporary location.
-                                                 The stack may access that memory directly without the application's knowledge. For writable characteristics, this value must not be a location in flash memory.*/
-} ble_gatts_attr_t;
-
-/**@brief GATT Attribute Value. */
-typedef struct
-{
-  uint16_t  len;        /**< Length in bytes to be written or read. Length in bytes written or read after successful return.*/
-  uint16_t  offset;     /**< Attribute value offset. */
-  uint8_t  *p_value;    /**< Pointer to where value is stored or will be stored.
-                             If value is stored in user memory, only the attribute length is updated when p_value == NULL.
-                             Set to NULL when reading to obtain the complete length of the attribute value */
-} ble_gatts_value_t;
-
-
-/**@brief GATT Characteristic Presentation Format. */
-typedef struct
-{
-  uint8_t          format;      /**< Format of the value, see @ref BLE_GATT_CPF_FORMATS. */
-  int8_t           exponent;    /**< Exponent for integer data types. */
-  uint16_t         unit;        /**< Unit from Bluetooth Assigned Numbers. */
-  uint8_t          name_space;  /**< Namespace from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */
-  uint16_t         desc;        /**< Namespace description from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */
-} ble_gatts_char_pf_t;
-
-
-/**@brief GATT Characteristic metadata. */
-typedef struct
-{
-  ble_gatt_char_props_t       char_props;               /**< Characteristic Properties. */
-  ble_gatt_char_ext_props_t   char_ext_props;           /**< Characteristic Extended Properties. */
-  uint8_t const              *p_char_user_desc;         /**< Pointer to a UTF-8 encoded string (non-NULL terminated), NULL if the descriptor is not required. */
-  uint16_t                    char_user_desc_max_size;  /**< The maximum size in bytes of the user description descriptor. */
-  uint16_t                    char_user_desc_size;      /**< The size of the user description, must be smaller or equal to char_user_desc_max_size. */
-  ble_gatts_char_pf_t const  *p_char_pf;                /**< Pointer to a presentation format structure or NULL if the CPF descriptor is not required. */
-  ble_gatts_attr_md_t const  *p_user_desc_md;           /**< Attribute metadata for the User Description descriptor, or NULL for default values. */
-  ble_gatts_attr_md_t const  *p_cccd_md;                /**< Attribute metadata for the Client Characteristic Configuration Descriptor, or NULL for default values. */
-  ble_gatts_attr_md_t const  *p_sccd_md;                /**< Attribute metadata for the Server Characteristic Configuration Descriptor, or NULL for default values. */
-} ble_gatts_char_md_t;
-
-
-/**@brief GATT Characteristic Definition Handles. */
-typedef struct
-{
-  uint16_t          value_handle;       /**< Handle to the characteristic value. */
-  uint16_t          user_desc_handle;   /**< Handle to the User Description descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */
-  uint16_t          cccd_handle;        /**< Handle to the Client Characteristic Configuration Descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */
-  uint16_t          sccd_handle;        /**< Handle to the Server Characteristic Configuration Descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */
-} ble_gatts_char_handles_t;
-
-
-/**@brief GATT HVx parameters. */
-typedef struct
-{
-  uint16_t          handle;             /**< Characteristic Value Handle. */
-  uint8_t           type;               /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */
-  uint16_t          offset;             /**< Offset within the attribute value. */
-  uint16_t         *p_len;              /**< Length in bytes to be written, length in bytes written after return. */
-  uint8_t const    *p_data;             /**< Actual data content, use NULL to use the current attribute value. */
-} ble_gatts_hvx_params_t;
-
-/**@brief GATT Authorization parameters. */
-typedef struct
-{
-  uint16_t          gatt_status;        /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */
-  uint8_t           update : 1;         /**< If set, data supplied in p_data will be used to update the attribute value.
-                                             Please note that for @ref BLE_GATTS_AUTHORIZE_TYPE_WRITE operations this bit must always be set,
-                                             as the data to be written needs to be stored and later provided by the application. */
-  uint16_t          offset;             /**< Offset of the attribute value being updated. */
-  uint16_t          len;                /**< Length in bytes of the value in p_data pointer, see @ref BLE_GATTS_ATTR_LENS_MAX. */
-  uint8_t const    *p_data;             /**< Pointer to new value used to update the attribute value. */
-} ble_gatts_authorize_params_t;
-
-/**@brief GATT Read or Write Authorize Reply parameters. */
-typedef struct
-{
-  uint8_t                               type;   /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */
-  union {
-    ble_gatts_authorize_params_t        read;   /**< Read authorization parameters. */
-    ble_gatts_authorize_params_t        write;  /**< Write authorization parameters. */
-  } params;                                     /**< Reply Parameters. */
-} ble_gatts_rw_authorize_reply_params_t;
-
-/**@brief Service Changed Inclusion configuration parameters, set with @ref sd_ble_cfg_set. */
-typedef struct
-{
-  uint8_t service_changed : 1;       /**< If 1, include the Service Changed characteristic in the Attribute Table. Default is @ref BLE_GATTS_SERVICE_CHANGED_DEFAULT. */
-} ble_gatts_cfg_service_changed_t;
-
-/**@brief Attribute table size configuration parameters, set with @ref sd_ble_cfg_set.
- *
- * @retval ::NRF_ERROR_INVALID_LENGTH One or more of the following is true:
- *                                    - The specified Attribute Table size is too small.
- *                                      The minimum acceptable size is defined by @ref BLE_GATTS_ATTR_TAB_SIZE_MIN.
- *                                    - The specified Attribute Table size is not a multiple of 4.
- */
-typedef struct
-{
-  uint32_t attr_tab_size; /**< Attribute table size. Default is @ref BLE_GATTS_ATTR_TAB_SIZE_DEFAULT, minimum is @ref BLE_GATTS_ATTR_TAB_SIZE_MIN. */
-} ble_gatts_cfg_attr_tab_size_t;
-
-/**@brief Config structure for GATTS configurations. */
-typedef union
-{
-  ble_gatts_cfg_service_changed_t service_changed;  /**< Include service changed characteristic, cfg_id is @ref BLE_GATTS_CFG_SERVICE_CHANGED. */
-  ble_gatts_cfg_attr_tab_size_t attr_tab_size;      /**< Attribute table size, cfg_id is @ref BLE_GATTS_CFG_ATTR_TAB_SIZE. */
-} ble_gatts_cfg_t;
-
-
-/**@brief Event structure for @ref BLE_GATTS_EVT_WRITE. */
-typedef struct
-{
-  uint16_t                    handle;             /**< Attribute Handle. */
-  ble_uuid_t                  uuid;               /**< Attribute UUID. */
-  uint8_t                     op;                 /**< Type of write operation, see @ref BLE_GATTS_OPS. */
-  uint8_t                     auth_required;      /**< Writing operation deferred due to authorization requirement. Application may use @ref sd_ble_gatts_value_set to finalize the writing operation. */
-  uint16_t                    offset;             /**< Offset for the write operation. */
-  uint16_t                    len;                /**< Length of the received data. */
-  uint8_t                     data[1];            /**< Received data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
-                                                       See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
-} ble_gatts_evt_write_t;
-
-/**@brief Event substructure for authorized read requests, see @ref ble_gatts_evt_rw_authorize_request_t. */
-typedef struct
-{
-  uint16_t                    handle;             /**< Attribute Handle. */
-  ble_uuid_t                  uuid;               /**< Attribute UUID. */
-  uint16_t                    offset;             /**< Offset for the read operation. */
-} ble_gatts_evt_read_t;
-
-/**@brief Event structure for @ref BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST. */
-typedef struct
-{
-  uint8_t                     type;             /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */
-  union {
-    ble_gatts_evt_read_t      read;             /**< Attribute Read Parameters. */
-    ble_gatts_evt_write_t     write;            /**< Attribute Write Parameters. */
-  } request;                                    /**< Request Parameters. */
-} ble_gatts_evt_rw_authorize_request_t;
-
-/**@brief Event structure for @ref BLE_GATTS_EVT_SYS_ATTR_MISSING. */
-typedef struct
-{
-  uint8_t hint;                                 /**< Hint (currently unused). */
-} ble_gatts_evt_sys_attr_missing_t;
-
-
-/**@brief Event structure for @ref BLE_GATTS_EVT_HVC. */
-typedef struct
-{
-  uint16_t          handle;                       /**< Attribute Handle. */
-} ble_gatts_evt_hvc_t;
-
-/**@brief Event structure for @ref BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST. */
-typedef struct
-{
-  uint16_t          client_rx_mtu;              /**< Client RX MTU size. */
-} ble_gatts_evt_exchange_mtu_request_t;
-
-/**@brief Event structure for @ref BLE_GATTS_EVT_TIMEOUT. */
-typedef struct
-{
-  uint8_t          src;                       /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */
-} ble_gatts_evt_timeout_t;
-
-/**@brief Event structure for @ref BLE_GATTS_EVT_HVN_TX_COMPLETE. */
-typedef struct
-{
-  uint8_t          count;                     /**< Number of notification transmissions completed. */
-} ble_gatts_evt_hvn_tx_complete_t;
-
-/**@brief GATTS event structure. */
-typedef struct
-{
-  uint16_t conn_handle;                                       /**< Connection Handle on which the event occurred. */
-  union
-  {
-    ble_gatts_evt_write_t                 write;                 /**< Write Event Parameters. */
-    ble_gatts_evt_rw_authorize_request_t  authorize_request;     /**< Read or Write Authorize Request Parameters. */
-    ble_gatts_evt_sys_attr_missing_t      sys_attr_missing;      /**< System attributes missing. */
-    ble_gatts_evt_hvc_t                   hvc;                   /**< Handle Value Confirmation Event Parameters. */
-    ble_gatts_evt_exchange_mtu_request_t  exchange_mtu_request;  /**< Exchange MTU Request Event Parameters. */
-    ble_gatts_evt_timeout_t               timeout;               /**< Timeout Event. */
-    ble_gatts_evt_hvn_tx_complete_t       hvn_tx_complete;       /**< Handle Value Notification transmission complete Event Parameters. */
-  } params;                                                      /**< Event Parameters. */
-} ble_gatts_evt_t;
-
-/** @} */
-
-/** @addtogroup BLE_GATTS_FUNCTIONS Functions
- * @{ */
-
-/**@brief Add a service declaration to the Attribute Table.
- *
- * @note Secondary Services are only relevant in the context of the entity that references them, it is therefore forbidden to
- *       add a secondary service declaration that is not referenced by another service later in the Attribute Table.
- *
- * @mscs
- * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC}
- * @endmscs
- *
- * @param[in] type      Toggles between primary and secondary services, see @ref BLE_GATTS_SRVC_TYPES.
- * @param[in] p_uuid    Pointer to service UUID.
- * @param[out] p_handle Pointer to a 16-bit word where the assigned handle will be stored.
- *
- * @retval ::NRF_SUCCESS Successfully added a service declaration.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, Vendor Specific UUIDs need to be present in the table.
- * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack.
- * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
- */
-SVCALL(SD_BLE_GATTS_SERVICE_ADD, uint32_t, sd_ble_gatts_service_add(uint8_t type, ble_uuid_t const *p_uuid, uint16_t *p_handle));
-
-
-/**@brief Add an include declaration to the Attribute Table.
- *
- * @note It is currently only possible to add an include declaration to the last added service (i.e. only sequential population is supported at this time).
- *
- * @note The included service must already be present in the Attribute Table prior to this call.
- *
- * @mscs
- * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC}
- * @endmscs
- *
- * @param[in] service_handle    Handle of the service where the included service is to be placed, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially.
- * @param[in] inc_srvc_handle   Handle of the included service.
- * @param[out] p_include_handle Pointer to a 16-bit word where the assigned handle will be stored.
- *
- * @retval ::NRF_SUCCESS Successfully added an include declaration.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, handle values need to match previously added services.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation, a service context is required.
- * @retval ::NRF_ERROR_NOT_SUPPORTED Feature is not supported, service_handle must be that of the last added service.
- * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, self inclusions are not allowed.
- * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
- * @retval ::NRF_ERROR_NOT_FOUND Attribute not found.
- */
-SVCALL(SD_BLE_GATTS_INCLUDE_ADD, uint32_t, sd_ble_gatts_include_add(uint16_t service_handle, uint16_t inc_srvc_handle, uint16_t *p_include_handle));
-
-
-/**@brief Add a characteristic declaration, a characteristic value declaration and optional characteristic descriptor declarations to the Attribute Table.
- *
- * @note It is currently only possible to add a characteristic to the last added service (i.e. only sequential population is supported at this time).
- *
- * @note Several restrictions apply to the parameters, such as matching permissions between the user description descriptor and the writable auxiliaries bits,
- *       readable (no security) and writable (selectable) CCCDs and SCCDs and valid presentation format values.
- *
- * @note If no metadata is provided for the optional descriptors, their permissions will be derived from the characteristic permissions.
- *
- * @mscs
- * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC}
- * @endmscs
- *
- * @param[in] service_handle    Handle of the service where the characteristic is to be placed, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially.
- * @param[in] p_char_md         Characteristic metadata.
- * @param[in] p_attr_char_value Pointer to the attribute structure corresponding to the characteristic value.
- * @param[out] p_handles        Pointer to the structure where the assigned handles will be stored.
- *
- * @retval ::NRF_SUCCESS Successfully added a characteristic.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, service handle, Vendor Specific UUIDs, lengths, and permissions need to adhere to the constraints.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation, a service context is required.
- * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack.
- * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
- * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX.
- */
-SVCALL(SD_BLE_GATTS_CHARACTERISTIC_ADD, uint32_t, sd_ble_gatts_characteristic_add(uint16_t service_handle, ble_gatts_char_md_t const *p_char_md, ble_gatts_attr_t const *p_attr_char_value, ble_gatts_char_handles_t *p_handles));
-
-
-/**@brief Add a descriptor to the Attribute Table.
- *
- * @note It is currently only possible to add a descriptor to the last added characteristic (i.e. only sequential population is supported at this time).
- *
- * @mscs
- * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC}
- * @endmscs
- *
- * @param[in] char_handle   Handle of the characteristic where the descriptor is to be placed, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially.
- * @param[in] p_attr        Pointer to the attribute structure.
- * @param[out] p_handle     Pointer to a 16-bit word where the assigned handle will be stored.
- *
- * @retval ::NRF_SUCCESS Successfully added a descriptor.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, characteristic handle, Vendor Specific UUIDs, lengths, and permissions need to adhere to the constraints.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation, a characteristic context is required.
- * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack.
- * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
- * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX.
- */
-SVCALL(SD_BLE_GATTS_DESCRIPTOR_ADD, uint32_t, sd_ble_gatts_descriptor_add(uint16_t char_handle, ble_gatts_attr_t const *p_attr, uint16_t *p_handle));
-
-/**@brief Set the value of a given attribute.
- *
- * @note Values other than system attributes can be set at any time, regardless of whether any active connections exist.
- *
- * @mscs
- * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_QUEUE_FULL_MSC}
- * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_NOAUTH_MSC}
- * @endmscs
- *
- * @param[in] conn_handle  Connection handle. Ignored if the value does not belong to a system attribute.
- * @param[in] handle       Attribute handle.
- * @param[in,out] p_value  Attribute value information.
- *
- * @retval ::NRF_SUCCESS Successfully set the value of the attribute.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::NRF_ERROR_NOT_FOUND Attribute not found.
- * @retval ::NRF_ERROR_FORBIDDEN Forbidden handle supplied, certain attributes are not modifiable by the application.
- * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied on a system attribute.
- */
-SVCALL(SD_BLE_GATTS_VALUE_SET, uint32_t, sd_ble_gatts_value_set(uint16_t conn_handle, uint16_t handle, ble_gatts_value_t *p_value));
-
-/**@brief Get the value of a given attribute.
- *
- * @note                 If the attribute value is longer than the size of the supplied buffer,
- *                       @ref ble_gatts_value_t::len will return the total attribute value length (excluding offset),
- *                       and not the number of bytes actually returned in @ref ble_gatts_value_t::p_value.
- *                       The application may use this information to allocate a suitable buffer size.
- *
- * @note                 When retrieving system attribute values with this function, the connection handle
- *                       may refer to an already disconnected connection. Refer to the documentation of
- *                       @ref sd_ble_gatts_sys_attr_get for further information.
- *
- * @param[in] conn_handle  Connection handle. Ignored if the value does not belong to a system attribute.
- * @param[in] handle       Attribute handle.
- * @param[in,out] p_value  Attribute value information.
- *
- * @retval ::NRF_SUCCESS Successfully retrieved the value of the attribute.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_NOT_FOUND Attribute not found.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid attribute offset supplied.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied on a system attribute.
- * @retval ::BLE_ERROR_GATTS_SYS_ATTR_MISSING System attributes missing, use @ref sd_ble_gatts_sys_attr_set to set them to a known value.
- */
-SVCALL(SD_BLE_GATTS_VALUE_GET, uint32_t, sd_ble_gatts_value_get(uint16_t conn_handle, uint16_t handle, ble_gatts_value_t *p_value));
-
-/**@brief Notify or Indicate an attribute value.
- *
- * @details This function checks for the relevant Client Characteristic Configuration descriptor value to verify that the relevant operation
- *          (notification or indication) has been enabled by the client. It is also able to update the attribute value before issuing the PDU, so that
- *          the application can atomically perform a value update and a server initiated transaction with a single API call.
- *
- * @note    The local attribute value may be updated even if an outgoing packet is not sent to the peer due to an error during execution.
- *          The Attribute Table has been updated if one of the following error codes is returned: @ref NRF_ERROR_INVALID_STATE, @ref NRF_ERROR_BUSY,
- *          @ref NRF_ERROR_FORBIDDEN, @ref BLE_ERROR_GATTS_SYS_ATTR_MISSING and @ref NRF_ERROR_RESOURCES.
- *          The caller can check whether the value has been updated by looking at the contents of *(@ref ble_gatts_hvx_params_t::p_len).
- *
- * @note    Only one indication procedure can be ongoing per connection at a time.
- *          If the application tries to indicate an attribute value while another indication procedure is ongoing,
- *          the function call will return @ref NRF_ERROR_BUSY.
- *          A @ref BLE_GATTS_EVT_HVC event will be issued as soon as the confirmation arrives from the peer.
- *
- * @note    The number of Handle Value Notifications that can be queued is configured by @ref ble_gatts_conn_cfg_t::hvn_tx_queue_size
- *          When the queue is full, the function call will return @ref NRF_ERROR_RESOURCES.
- *          A @ref BLE_GATTS_EVT_HVN_TX_COMPLETE event will be issued as soon as the transmission of the notification is complete.
- *
- * @note    The application can keep track of the available queue element count for notifications by following the procedure below:
- *          - Store initial queue element count in a variable.
- *          - Decrement the variable, which stores the currently available queue element count, by one when a call to this function returns @ref NRF_SUCCESS.
- *          - Increment the variable, which stores the current available queue element count, by the count variable in @ref BLE_GATTS_EVT_HVN_TX_COMPLETE event.
- *
- * @events
- * @event{@ref BLE_GATTS_EVT_HVN_TX_COMPLETE, Notification transmission complete.}
- * @event{@ref BLE_GATTS_EVT_HVC, Confirmation received from the peer.}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_GATTS_HVX_SYS_ATTRS_MISSING_MSC}
- * @mmsc{@ref BLE_GATTS_HVN_MSC}
- * @mmsc{@ref BLE_GATTS_HVI_MSC}
- * @mmsc{@ref BLE_GATTS_HVX_DISABLED_MSC}
- * @endmscs
- *
- * @param[in] conn_handle      Connection handle.
- * @param[in,out] p_hvx_params Pointer to an HVx parameters structure. If @ref ble_gatts_hvx_params_t::p_data
- *                             contains a non-NULL pointer the attribute value will be updated with the contents
- *                             pointed by it before sending the notification or indication. If the attribute value
- *                             is updated, @ref ble_gatts_hvx_params_t::p_len is updated by the SoftDevice to
- *                             contain the number of actual bytes written, else it will be set to 0.
- *
- * @retval ::NRF_SUCCESS Successfully queued a notification or indication for transmission, and optionally updated the attribute value.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_STATE One or more of the following is true:
- *                                   - Invalid Connection State
- *                                   - Notifications and/or indications not enabled in the CCCD
- *                                   - An ATT_MTU exchange is ongoing
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle(s) supplied. Only attributes added directly by the application are available to notify and indicate.
- * @retval ::BLE_ERROR_GATTS_INVALID_ATTR_TYPE Invalid attribute type(s) supplied, only characteristic values may be notified and indicated.
- * @retval ::NRF_ERROR_NOT_FOUND Attribute not found.
- * @retval ::NRF_ERROR_FORBIDDEN The connection's current security level is lower than the one required by the write permissions of the CCCD associated with this characteristic.
- * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied.
- * @retval ::NRF_ERROR_BUSY For @ref BLE_GATT_HVX_INDICATION Procedure already in progress. Wait for a @ref BLE_GATTS_EVT_HVC event and retry.
- * @retval ::BLE_ERROR_GATTS_SYS_ATTR_MISSING System attributes missing, use @ref sd_ble_gatts_sys_attr_set to set them to a known value.
- * @retval ::NRF_ERROR_RESOURCES Too many notifications queued.
- *                               Wait for a @ref BLE_GATTS_EVT_HVN_TX_COMPLETE event and retry.
- * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection.
- */
-SVCALL(SD_BLE_GATTS_HVX, uint32_t, sd_ble_gatts_hvx(uint16_t conn_handle, ble_gatts_hvx_params_t const *p_hvx_params));
-
-/**@brief Indicate the Service Changed attribute value.
- *
- * @details This call will send a Handle Value Indication to one or more peers connected to inform them that the Attribute
- *          Table layout has changed. As soon as the peer has confirmed the indication, a @ref BLE_GATTS_EVT_SC_CONFIRM event will
- *          be issued.
- *
- * @note    Some of the restrictions and limitations that apply to @ref sd_ble_gatts_hvx also apply here.
- *
- * @events
- * @event{@ref BLE_GATTS_EVT_SC_CONFIRM, Confirmation of attribute table change received from peer.}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_GATTS_SC_MSC}
- * @endmscs
- *
- * @param[in] conn_handle  Connection handle.
- * @param[in] start_handle Start of affected attribute handle range.
- * @param[in] end_handle   End of affected attribute handle range.
- *
- * @retval ::NRF_SUCCESS Successfully queued the Service Changed indication for transmission.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_NOT_SUPPORTED Service Changed not enabled at initialization. See @ref
- *                                   sd_ble_cfg_set and @ref ble_gatts_cfg_service_changed_t.
- * @retval ::NRF_ERROR_INVALID_STATE One or more of the following is true:
- *                                   - Invalid Connection State
- *                                   - Notifications and/or indications not enabled in the CCCD
- *                                   - An ATT_MTU exchange is ongoing
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
- * @retval ::BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle(s) supplied, handles must be in the range populated by the application.
- * @retval ::NRF_ERROR_BUSY Procedure already in progress.
- * @retval ::BLE_ERROR_GATTS_SYS_ATTR_MISSING System attributes missing, use @ref sd_ble_gatts_sys_attr_set to set them to a known value.
- * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection.
- */
-SVCALL(SD_BLE_GATTS_SERVICE_CHANGED, uint32_t, sd_ble_gatts_service_changed(uint16_t conn_handle, uint16_t start_handle, uint16_t end_handle));
-
-/**@brief Respond to a Read/Write authorization request.
- *
- * @note This call should only be used as a response to a @ref BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST event issued to the application.
- *
- * @mscs
- * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_AUTH_MSC}
- * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_BUF_AUTH_MSC}
- * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_NOAUTH_MSC}
- * @mmsc{@ref BLE_GATTS_READ_REQ_AUTH_MSC}
- * @mmsc{@ref BLE_GATTS_WRITE_REQ_AUTH_MSC}
- * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_QUEUE_FULL_MSC}
- * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_PEER_CANCEL_MSC}
- * @endmscs
- *
- * @param[in] conn_handle                 Connection handle.
- * @param[in] p_rw_authorize_reply_params Pointer to a structure with the attribute provided by the application.
- *
- * @note @ref ble_gatts_authorize_params_t::p_data is ignored when this function is used to respond
- *       to a @ref BLE_GATTS_AUTHORIZE_TYPE_READ event if @ref ble_gatts_authorize_params_t::update
- *       is set to 0.
- *
- * @retval ::NRF_SUCCESS               Successfully queued a response to the peer, and in the case of a write operation, Attribute Table updated.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_BUSY            The stack is busy, process pending events and retry.
- * @retval ::NRF_ERROR_INVALID_ADDR    Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_STATE   Invalid Connection State or no authorization request pending.
- * @retval ::NRF_ERROR_INVALID_PARAM   Authorization op invalid,
- *                                         handle supplied does not match requested handle,
- *                                         or invalid data to be written provided by the application.
- * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection.
- */
-SVCALL(SD_BLE_GATTS_RW_AUTHORIZE_REPLY, uint32_t, sd_ble_gatts_rw_authorize_reply(uint16_t conn_handle, ble_gatts_rw_authorize_reply_params_t const *p_rw_authorize_reply_params));
-
-
-/**@brief Update persistent system attribute information.
- *
- * @details Supply information about persistent system attributes to the stack,
- *          previously obtained using @ref sd_ble_gatts_sys_attr_get.
- *          This call is only allowed for active connections, and is usually
- *          made immediately after a connection is established with an known bonded device,
- *          often as a response to a @ref BLE_GATTS_EVT_SYS_ATTR_MISSING.
- *
- *          p_sysattrs may point directly to the application's stored copy of the system attributes
- *          obtained using @ref sd_ble_gatts_sys_attr_get.
- *          If the pointer is NULL, the system attribute info is initialized, assuming that
- *          the application does not have any previously saved system attribute data for this device.
- *
- * @note The state of persistent system attributes is reset upon connection establishment and then remembered for its duration.
- *
- * @note If this call returns with an error code different from @ref NRF_SUCCESS, the storage of persistent system attributes may have been completed only partially.
- *       This means that the state of the attribute table is undefined, and the application should either provide a new set of attributes using this same call or
- *       reset the SoftDevice to return to a known state.
- *
- * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS is used with this function, only the system attributes included in system services will be modified.
- * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS is used with this function, only the system attributes included in user services will be modified.
- *
- * @mscs
- * @mmsc{@ref BLE_GATTS_HVX_SYS_ATTRS_MISSING_MSC}
- * @mmsc{@ref BLE_GATTS_SYS_ATTRS_UNK_PEER_MSC}
- * @mmsc{@ref BLE_GATTS_SYS_ATTRS_BONDED_PEER_MSC}
- * @endmscs
- *
- * @param[in]  conn_handle        Connection handle.
- * @param[in]  p_sys_attr_data    Pointer to a saved copy of system attributes supplied to the stack, or NULL.
- * @param[in]  len                Size of data pointed by p_sys_attr_data, in octets.
- * @param[in]  flags              Optional additional flags, see @ref BLE_GATTS_SYS_ATTR_FLAGS
- *
- * @retval ::NRF_SUCCESS Successfully set the system attribute information.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid flags supplied.
- * @retval ::NRF_ERROR_INVALID_DATA Invalid data supplied, the data should be exactly the same as retrieved with @ref sd_ble_gatts_sys_attr_get.
- * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
- */
-SVCALL(SD_BLE_GATTS_SYS_ATTR_SET, uint32_t, sd_ble_gatts_sys_attr_set(uint16_t conn_handle, uint8_t const *p_sys_attr_data, uint16_t len, uint32_t flags));
-
-
-/**@brief Retrieve persistent system attribute information from the stack.
- *
- * @details This call is used to retrieve information about values to be stored persistently by the application
- *          during the lifetime of a connection or after it has been terminated. When a new connection is established with the same bonded device,
- *          the system attribute information retrieved with this function should be restored using using @ref sd_ble_gatts_sys_attr_set.
- *          If retrieved after disconnection, the data should be read before a new connection established. The connection handle for
- *          the previous, now disconnected, connection will remain valid until a new one is created to allow this API call to refer to it.
- *          Connection handles belonging to active connections can be used as well, but care should be taken since the system attributes
- *          may be written to at any time by the peer during a connection's lifetime.
- *
- * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS is used with this function, only the system attributes included in system services will be returned.
- * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS is used with this function, only the system attributes included in user services will be returned.
- *
- * @mscs
- * @mmsc{@ref BLE_GATTS_SYS_ATTRS_BONDED_PEER_MSC}
- * @endmscs
- *
- * @param[in]     conn_handle       Connection handle of the recently terminated connection.
- * @param[out]    p_sys_attr_data   Pointer to a buffer where updated information about system attributes will be filled in. The format of the data is described
- *                                  in @ref BLE_GATTS_SYS_ATTRS_FORMAT. NULL can be provided to obtain the length of the data.
- * @param[in,out] p_len             Size of application buffer if p_sys_attr_data is not NULL. Unconditionally updated to actual length of system attribute data.
- * @param[in]     flags             Optional additional flags, see @ref BLE_GATTS_SYS_ATTR_FLAGS
- *
- * @retval ::NRF_SUCCESS Successfully retrieved the system attribute information.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid flags supplied.
- * @retval ::NRF_ERROR_DATA_SIZE The system attribute information did not fit into the provided buffer.
- * @retval ::NRF_ERROR_NOT_FOUND No system attributes found.
- */
-SVCALL(SD_BLE_GATTS_SYS_ATTR_GET, uint32_t, sd_ble_gatts_sys_attr_get(uint16_t conn_handle, uint8_t *p_sys_attr_data, uint16_t *p_len, uint32_t flags));
-
-
-/**@brief Retrieve the first valid user attribute handle.
- *
- * @param[out] p_handle   Pointer to an integer where the handle will be stored.
- *
- * @retval ::NRF_SUCCESS Successfully retrieved the handle.
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- */
-SVCALL(SD_BLE_GATTS_INITIAL_USER_HANDLE_GET, uint32_t, sd_ble_gatts_initial_user_handle_get(uint16_t *p_handle));
-
-/**@brief Retrieve the attribute UUID and/or metadata.
- *
- * @param[in]  handle Attribute handle
- * @param[out] p_uuid UUID of the attribute. Use NULL to omit this field.
- * @param[out] p_md Metadata of the attribute. Use NULL to omit this field.
- *
- * @retval ::NRF_SUCCESS Successfully retrieved the attribute metadata,
- * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameters supplied. Returned when both @c p_uuid and @c p_md are NULL.
- * @retval ::NRF_ERROR_NOT_FOUND Attribute was not found.
- */
-SVCALL(SD_BLE_GATTS_ATTR_GET, uint32_t, sd_ble_gatts_attr_get(uint16_t handle, ble_uuid_t * p_uuid, ble_gatts_attr_md_t * p_md));
-
-/**@brief Reply to an ATT_MTU exchange request by sending an Exchange MTU Response to the client.
- *
- * @details This function is only used to reply to a @ref BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST event.
- *
- * @details The SoftDevice sets ATT_MTU to the minimum of:
- *          - The Client RX MTU value from @ref BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST, and
- *          - The Server RX MTU value.
- *
- *          However, the SoftDevice never sets ATT_MTU lower than @ref BLE_GATT_ATT_MTU_DEFAULT.
- *
- * @mscs
- * @mmsc{@ref BLE_GATTS_MTU_EXCHANGE}
- * @endmscs
- *
- * @param[in] conn_handle    The connection handle identifying the connection to perform this procedure on.
- * @param[in] server_rx_mtu  Server RX MTU size.
- *                           - The minimum value is @ref BLE_GATT_ATT_MTU_DEFAULT.
- *                           - The maximum value is @ref ble_gatt_conn_cfg_t::att_mtu in the connection configuration
- *                             used for this connection.
- *                           - The value must be equal to Client RX MTU size given in @ref sd_ble_gattc_exchange_mtu_request
- *                             if an ATT_MTU exchange has already been performed in the other direction.
- *
- * @retval ::NRF_SUCCESS Successfully sent response to the client.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State or no ATT_MTU exchange request pending.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid Server RX MTU size supplied.
- * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection.
- */
-SVCALL(SD_BLE_GATTS_EXCHANGE_MTU_REPLY, uint32_t, sd_ble_gatts_exchange_mtu_reply(uint16_t conn_handle, uint16_t server_rx_mtu));
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif
-#endif // BLE_GATTS_H__
-
-/**
-  @}
-*/
diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_hci.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_hci.h
deleted file mode 100755
index f0dde9a0..00000000
--- a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_hci.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * Copyright (c) 2012 - 2017, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- *    list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form, except as embedded into a Nordic
- *    Semiconductor ASA integrated circuit in a product or a software update for
- *    such product, must reproduce the above copyright notice, this list of
- *    conditions and the following disclaimer in the documentation and/or other
- *    materials provided with the distribution.
- *
- * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
- *    contributors may be used to endorse or promote products derived from this
- *    software without specific prior written permission.
- *
- * 4. This software, with or without modification, must only be used with a
- *    Nordic Semiconductor ASA integrated circuit.
- *
- * 5. Any software provided in binary form under this license must not be reverse
- *    engineered, decompiled, modified and/or disassembled.
- *
- * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
-  @addtogroup BLE_COMMON
-  @{
-*/
-
-
-#ifndef BLE_HCI_H__
-#define BLE_HCI_H__
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup BLE_HCI_STATUS_CODES Bluetooth status codes
- * @{ */
-
-#define BLE_HCI_STATUS_CODE_SUCCESS                        0x00   /**< Success. */
-#define BLE_HCI_STATUS_CODE_UNKNOWN_BTLE_COMMAND           0x01   /**< Unknown BLE Command. */
-#define BLE_HCI_STATUS_CODE_UNKNOWN_CONNECTION_IDENTIFIER  0x02   /**< Unknown Connection Identifier. */
-/*0x03 Hardware Failure
-0x04 Page Timeout
-*/
-#define BLE_HCI_AUTHENTICATION_FAILURE                     0x05   /**< Authentication Failure. */
-#define BLE_HCI_STATUS_CODE_PIN_OR_KEY_MISSING             0x06   /**< Pin or Key missing. */
-#define BLE_HCI_MEMORY_CAPACITY_EXCEEDED                   0x07   /**< Memory Capacity Exceeded. */
-#define BLE_HCI_CONNECTION_TIMEOUT                         0x08   /**< Connection Timeout. */
-/*0x09 Connection Limit Exceeded
-0x0A Synchronous Connection Limit To A Device Exceeded
-0x0B ACL Connection Already Exists*/
-#define BLE_HCI_STATUS_CODE_COMMAND_DISALLOWED             0x0C   /**< Command Disallowed. */
-/*0x0D Connection Rejected due to Limited Resources
-0x0E Connection Rejected Due To Security Reasons
-0x0F Connection Rejected due to Unacceptable BD_ADDR
-0x10 Connection Accept Timeout Exceeded
-0x11 Unsupported Feature or Parameter Value*/
-#define BLE_HCI_STATUS_CODE_INVALID_BTLE_COMMAND_PARAMETERS 0x12  /**< Invalid BLE Command Parameters. */
-#define BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION           0x13  /**< Remote User Terminated Connection. */
-#define BLE_HCI_REMOTE_DEV_TERMINATION_DUE_TO_LOW_RESOURCES 0x14  /**< Remote Device Terminated Connection due to low resources.*/
-#define BLE_HCI_REMOTE_DEV_TERMINATION_DUE_TO_POWER_OFF     0x15  /**< Remote Device Terminated Connection due to power off. */
-#define BLE_HCI_LOCAL_HOST_TERMINATED_CONNECTION            0x16  /**< Local Host Terminated Connection. */
-/*
-0x17 Repeated Attempts
-0x18 Pairing Not Allowed
-0x19 Unknown LMP PDU
-*/
-#define BLE_HCI_UNSUPPORTED_REMOTE_FEATURE 0x1A                   /**< Unsupported Remote Feature. */
-/*
-0x1B SCO Offset Rejected
-0x1C SCO Interval Rejected
-0x1D SCO Air Mode Rejected*/
-#define BLE_HCI_STATUS_CODE_INVALID_LMP_PARAMETERS     0x1E       /**< Invalid LMP Parameters. */
-#define BLE_HCI_STATUS_CODE_UNSPECIFIED_ERROR          0x1F       /**< Unspecified Error. */
-/*0x20 Unsupported LMP Parameter Value
-0x21 Role Change Not Allowed
-*/
-#define BLE_HCI_STATUS_CODE_LMP_RESPONSE_TIMEOUT            0x22       /**< LMP Response Timeout. */
-#define BLE_HCI_STATUS_CODE_LMP_ERROR_TRANSACTION_COLLISION 0x23  /**< LMP Error Transaction Collision/LL Procedure Collision. */
-#define BLE_HCI_STATUS_CODE_LMP_PDU_NOT_ALLOWED             0x24       /**< LMP PDU Not Allowed. */
-/*0x25 Encryption Mode Not Acceptable
-0x26 Link Key Can Not be Changed
-0x27 Requested QoS Not Supported
-*/
-#define BLE_HCI_INSTANT_PASSED                         0x28       /**< Instant Passed. */
-#define BLE_HCI_PAIRING_WITH_UNIT_KEY_UNSUPPORTED      0x29       /**< Pairing with Unit Key Unsupported. */
-#define BLE_HCI_DIFFERENT_TRANSACTION_COLLISION        0x2A       /**< Different Transaction Collision. */
-/*
-0x2B Reserved
-0x2C QoS Unacceptable Parameter
-0x2D QoS Rejected
-0x2E Channel Classification Not Supported
-0x2F Insufficient Security
-*/
-#define BLE_HCI_PARAMETER_OUT_OF_MANDATORY_RANGE       0x30            /**< Parameter Out Of Mandatory Range. */
-/*
-0x31 Reserved
-0x32 Role Switch Pending
-0x33 Reserved
-0x34 Reserved Slot Violation
-0x35 Role Switch Failed
-0x36 Extended Inquiry Response Too Large
-0x37 Secure Simple Pairing Not Supported By Host.
-0x38 Host Busy - Pairing
-0x39 Connection Rejected due to No Suitable Channel Found*/
-#define BLE_HCI_CONTROLLER_BUSY                        0x3A       /**< Controller Busy. */
-#define BLE_HCI_CONN_INTERVAL_UNACCEPTABLE             0x3B       /**< Connection Interval Unacceptable. */
-#define BLE_HCI_DIRECTED_ADVERTISER_TIMEOUT            0x3C       /**< Directed Advertisement Timeout. */
-#define BLE_HCI_CONN_TERMINATED_DUE_TO_MIC_FAILURE     0x3D       /**< Connection Terminated due to MIC Failure. */
-#define BLE_HCI_CONN_FAILED_TO_BE_ESTABLISHED          0x3E       /**< Connection Failed to be Established. */
-
-/** @} */
-
-
-#ifdef __cplusplus
-}
-#endif
-#endif // BLE_HCI_H__
-
-/** @} */
diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_l2cap.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_l2cap.h
deleted file mode 100755
index edaf6641..00000000
--- a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_l2cap.h
+++ /dev/null
@@ -1,506 +0,0 @@
-/*
- * Copyright (c) 2011 - 2018, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- *    list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form, except as embedded into a Nordic
- *    Semiconductor ASA integrated circuit in a product or a software update for
- *    such product, must reproduce the above copyright notice, this list of
- *    conditions and the following disclaimer in the documentation and/or other
- *    materials provided with the distribution.
- *
- * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
- *    contributors may be used to endorse or promote products derived from this
- *    software without specific prior written permission.
- *
- * 4. This software, with or without modification, must only be used with a
- *    Nordic Semiconductor ASA integrated circuit.
- *
- * 5. Any software provided in binary form under this license must not be reverse
- *    engineered, decompiled, modified and/or disassembled.
- *
- * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
-  @addtogroup BLE_L2CAP Logical Link Control and Adaptation Protocol (L2CAP)
-  @{
-  @brief Definitions and prototypes for the L2CAP interface.
- */
-
-#ifndef BLE_L2CAP_H__
-#define BLE_L2CAP_H__
-
-#include <stdint.h>
-#include "nrf_svc.h"
-#include "nrf_error.h"
-#include "ble_ranges.h"
-#include "ble_types.h"
-#include "ble_err.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**@addtogroup BLE_L2CAP_TERMINOLOGY Terminology
- * @{
- * @details
- *
- * L2CAP SDU
- * - A data unit that the application can send/receive to/from a peer.
- *
- * L2CAP PDU
- * - A data unit that is exchanged between local and remote L2CAP entities.
- *   It consists of L2CAP protocol control information and payload fields.
- *   The payload field can contain an L2CAP SDU or a part of an L2CAP SDU.
- *
- * L2CAP MTU
- * - The maximum length of an L2CAP SDU.
- *
- * L2CAP MPS
- * - The maximum length of an L2CAP PDU payload field.
- *
- * Credits
- * - A value indicating the number of L2CAP PDUs that the receiver of the credit can send to the peer.
- * @} */
-
-/**@addtogroup BLE_L2CAP_ENUMERATIONS Enumerations
- * @{ */
-
-/**@brief L2CAP API SVC numbers. */
-enum BLE_L2CAP_SVCS
-{
-  SD_BLE_L2CAP_CH_SETUP        = BLE_L2CAP_SVC_BASE + 0, /**< Set up an L2CAP channel. */
-  SD_BLE_L2CAP_CH_RELEASE      = BLE_L2CAP_SVC_BASE + 1, /**< Release an L2CAP channel. */
-  SD_BLE_L2CAP_CH_RX           = BLE_L2CAP_SVC_BASE + 2, /**< Receive an SDU on an L2CAP channel. */
-  SD_BLE_L2CAP_CH_TX           = BLE_L2CAP_SVC_BASE + 3, /**< Transmit an SDU on an L2CAP channel. */
-  SD_BLE_L2CAP_CH_FLOW_CONTROL = BLE_L2CAP_SVC_BASE + 4, /**< Advanced SDU reception flow control. */
-};
-
-/**@brief L2CAP Event IDs. */
-enum BLE_L2CAP_EVTS
-{
-  BLE_L2CAP_EVT_CH_SETUP_REQUEST    = BLE_L2CAP_EVT_BASE + 0,    /**< L2CAP Channel Setup Request event.
-                                                                   \n See @ref ble_l2cap_evt_ch_setup_request_t. */
-  BLE_L2CAP_EVT_CH_SETUP_REFUSED    = BLE_L2CAP_EVT_BASE + 1,    /**< L2CAP Channel Setup Refused event.
-                                                                   \n See @ref ble_l2cap_evt_ch_setup_refused_t. */
-  BLE_L2CAP_EVT_CH_SETUP            = BLE_L2CAP_EVT_BASE + 2,    /**< L2CAP Channel Setup Completed event.
-                                                                   \n See @ref ble_l2cap_evt_ch_setup_t. */
-  BLE_L2CAP_EVT_CH_RELEASED         = BLE_L2CAP_EVT_BASE + 3,    /**< L2CAP Channel Released event.
-                                                                   \n No additional event structure applies. */
-  BLE_L2CAP_EVT_CH_SDU_BUF_RELEASED = BLE_L2CAP_EVT_BASE + 4,    /**< L2CAP Channel SDU data buffer released event.
-                                                                   \n See @ref ble_l2cap_evt_ch_sdu_buf_released_t. */
-  BLE_L2CAP_EVT_CH_CREDIT           = BLE_L2CAP_EVT_BASE + 5,    /**< L2CAP Channel Credit received.
-                                                                   \n See @ref ble_l2cap_evt_ch_credit_t. */
-  BLE_L2CAP_EVT_CH_RX               = BLE_L2CAP_EVT_BASE + 6,    /**< L2CAP Channel SDU received.
-                                                                   \n See @ref ble_l2cap_evt_ch_rx_t. */
-  BLE_L2CAP_EVT_CH_TX               = BLE_L2CAP_EVT_BASE + 7,   /**< L2CAP Channel SDU transmitted.
-                                                                   \n See @ref ble_l2cap_evt_ch_tx_t. */
-};
-
-/** @} */
-
-/**@addtogroup BLE_L2CAP_DEFINES Defines
- * @{ */
-
-/**@brief Maximum number of L2CAP channels per connection. */
-#define BLE_L2CAP_CH_COUNT_MAX    (64)
-
-/**@brief Minimum L2CAP MTU, in bytes. */
-#define BLE_L2CAP_MTU_MIN         (23)
-
-/**@brief Minimum L2CAP MPS, in bytes. */
-#define BLE_L2CAP_MPS_MIN         (23)
-
-/**@brief Invalid CID. */
-#define BLE_L2CAP_CID_INVALID     (0x0000)
-
-/**@brief Default number of credits for @ref sd_ble_l2cap_ch_flow_control. */
-#define BLE_L2CAP_CREDITS_DEFAULT (1)
-
-/**@defgroup BLE_L2CAP_CH_SETUP_REFUSED_SRCS L2CAP channel setup refused sources
- * @{ */
-#define BLE_L2CAP_CH_SETUP_REFUSED_SRC_LOCAL            (0x01)    /**< Local. */
-#define BLE_L2CAP_CH_SETUP_REFUSED_SRC_REMOTE           (0x02)    /**< Remote. */
- /** @}  */
-
- /** @defgroup BLE_L2CAP_CH_STATUS_CODES L2CAP channel status codes
- * @{ */
-#define BLE_L2CAP_CH_STATUS_CODE_SUCCESS                (0x0000)  /**< Success. */
-#define BLE_L2CAP_CH_STATUS_CODE_LE_PSM_NOT_SUPPORTED   (0x0002)  /**< LE_PSM not supported. */
-#define BLE_L2CAP_CH_STATUS_CODE_NO_RESOURCES           (0x0004)  /**< No resources available. */
-#define BLE_L2CAP_CH_STATUS_CODE_INSUFF_AUTHENTICATION  (0x0005)  /**< Insufficient authentication. */
-#define BLE_L2CAP_CH_STATUS_CODE_INSUFF_AUTHORIZATION   (0x0006)  /**< Insufficient authorization. */
-#define BLE_L2CAP_CH_STATUS_CODE_INSUFF_ENC_KEY_SIZE    (0x0007)  /**< Insufficient encryption key size. */
-#define BLE_L2CAP_CH_STATUS_CODE_INSUFF_ENC             (0x0008)  /**< Insufficient encryption. */
-#define BLE_L2CAP_CH_STATUS_CODE_INVALID_SCID           (0x0009)  /**< Invalid Source CID. */
-#define BLE_L2CAP_CH_STATUS_CODE_SCID_ALLOCATED         (0x000A)  /**< Source CID already allocated. */
-#define BLE_L2CAP_CH_STATUS_CODE_UNACCEPTABLE_PARAMS    (0x000B)  /**< Unacceptable parameters. */
-#define BLE_L2CAP_CH_STATUS_CODE_NOT_UNDERSTOOD         (0x8000)  /**< Command Reject received instead of LE Credit Based Connection Response. */
-#define BLE_L2CAP_CH_STATUS_CODE_TIMEOUT                (0xC000)  /**< Operation timed out. */
-/** @} */
-
-/** @} */
-
-/**@addtogroup BLE_L2CAP_STRUCTURES Structures
- * @{ */
-
-/**
- * @brief BLE L2CAP connection configuration parameters, set with @ref sd_ble_cfg_set.
- *
- * @note  These parameters are set per connection, so all L2CAP channels created on this connection
- *        will have the same parameters.
- *
- * @retval ::NRF_ERROR_INVALID_PARAM  One or more of the following is true:
- *                                    - rx_mps is smaller than @ref BLE_L2CAP_MPS_MIN.
- *                                    - tx_mps is smaller than @ref BLE_L2CAP_MPS_MIN.
- *                                    - ch_count is greater than @ref BLE_L2CAP_CH_COUNT_MAX.
- * @retval ::NRF_ERROR_NO_MEM         rx_mps or tx_mps is set too high.
- */
-typedef struct
-{
-  uint16_t    rx_mps;        /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP shall
-                                  be able to receive on L2CAP channels on connections with this
-                                  configuration. The minimum value is @ref BLE_L2CAP_MPS_MIN. */
-  uint16_t    tx_mps;        /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP shall
-                                  be able to transmit on L2CAP channels on connections with this
-                                  configuration. The minimum value is @ref BLE_L2CAP_MPS_MIN. */
-  uint8_t     rx_queue_size; /**< Number of SDU data buffers that can be queued for reception per
-                                  L2CAP channel. The minimum value is one. */
-  uint8_t     tx_queue_size; /**< Number of SDU data buffers that can be queued for transmission
-                                  per L2CAP channel. The minimum value is one. */
-  uint8_t     ch_count;      /**< Number of L2CAP channels the application can create per connection
-                                  with this configuration. The default value is zero, the maximum
-                                  value is @ref BLE_L2CAP_CH_COUNT_MAX.
-                                  @note if this parameter is set to zero, all other parameters in
-                                  @ref ble_l2cap_conn_cfg_t are ignored. */
-} ble_l2cap_conn_cfg_t;
-
-/**@brief L2CAP channel RX parameters. */
-typedef struct
-{
-  uint16_t    rx_mtu;        /**< The maximum L2CAP SDU size, in bytes, that L2CAP shall be able to
-                                  receive on this L2CAP channel.
-                                  - Must be equal to or greater than @ref BLE_L2CAP_MTU_MIN. */
-  uint16_t    rx_mps;        /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP shall be
-                                  able to receive on this L2CAP channel.
-                                  - Must be equal to or greater than @ref BLE_L2CAP_MPS_MIN.
-                                  - Must be equal to or less than @ref ble_l2cap_conn_cfg_t::rx_mps. */
-  ble_data_t  sdu_buf;       /**< SDU data buffer for reception.
-                                  - If @ref ble_data_t::p_data is non-NULL, initial credits are
-                                    issued to the peer.
-                                  - If @ref ble_data_t::p_data is NULL, no initial credits are
-                                    issued to the peer. */
-} ble_l2cap_ch_rx_params_t;
-
-/**@brief L2CAP channel setup parameters. */
-typedef struct
-{
-  ble_l2cap_ch_rx_params_t      rx_params;  /**< L2CAP channel RX parameters. */
-  uint16_t                      le_psm;     /**< LE Protocol/Service Multiplexer. Used when requesting
-                                                 setup of an L2CAP channel, ignored otherwise. */
-  uint16_t                      status;     /**< Status code, see @ref BLE_L2CAP_CH_STATUS_CODES.
-                                                 Used when replying to a setup request of an L2CAP
-                                                 channel, ignored otherwise. */
-} ble_l2cap_ch_setup_params_t;
-
-/**@brief L2CAP channel TX parameters. */
-typedef struct
-{
-  uint16_t    tx_mtu;        /**< The maximum L2CAP SDU size, in bytes, that L2CAP is able to
-                                  transmit on this L2CAP channel. */
-  uint16_t    peer_mps;      /**< The maximum L2CAP PDU payload size, in bytes, that the peer is
-                                  able to receive on this L2CAP channel. */
-  uint16_t    tx_mps;        /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP is able
-                                  to transmit on this L2CAP channel. This is effective tx_mps,
-                                  selected by the SoftDevice as
-                                  MIN( @ref ble_l2cap_ch_tx_params_t::peer_mps, @ref ble_l2cap_conn_cfg_t::tx_mps ) */
-  uint16_t    credits;       /**< Initial credits given by the peer. */
-} ble_l2cap_ch_tx_params_t;
-
-/**@brief L2CAP Channel Setup Request event. */
-typedef struct
-{
-  ble_l2cap_ch_tx_params_t  tx_params;  /**< L2CAP channel TX parameters. */
-  uint16_t                  le_psm;     /**< LE Protocol/Service Multiplexer. */
-} ble_l2cap_evt_ch_setup_request_t;
-
-/**@brief L2CAP Channel Setup Refused event. */
-typedef struct
-{
-  uint8_t  source;           /**< Source, see @ref BLE_L2CAP_CH_SETUP_REFUSED_SRCS */
-  uint16_t status;           /**< Status code, see @ref BLE_L2CAP_CH_STATUS_CODES */
-} ble_l2cap_evt_ch_setup_refused_t;
-
-/**@brief L2CAP Channel Setup Completed event. */
-typedef struct
-{
-  ble_l2cap_ch_tx_params_t tx_params;  /**< L2CAP channel TX parameters. */
-} ble_l2cap_evt_ch_setup_t;
-
-/**@brief L2CAP Channel SDU Data Buffer Released event. */
-typedef struct
-{
-  ble_data_t  sdu_buf;       /**< Returned reception or transmission SDU data buffer. The SoftDevice
-                                  returns SDU data buffers supplied by the application, which have
-                                  not yet been returned previously via a @ref BLE_L2CAP_EVT_CH_RX or
-                                  @ref BLE_L2CAP_EVT_CH_TX event. */
-} ble_l2cap_evt_ch_sdu_buf_released_t;
-
-/**@brief L2CAP Channel Credit received event. */
-typedef struct
-{
-  uint16_t  credits;         /**< Additional credits given by the peer. */
-} ble_l2cap_evt_ch_credit_t;
-
-/**@brief L2CAP Channel received SDU event. */
-typedef struct
-{
-  uint16_t    sdu_len;       /**< Total SDU length, in bytes. */
-  ble_data_t  sdu_buf;       /**< SDU data buffer.
-                                  @note If there is not enough space in the buffer
-                                        (sdu_buf.len < sdu_len) then the rest of the SDU will be
-                                        silently discarded by the SoftDevice. */
-} ble_l2cap_evt_ch_rx_t;
-
-/**@brief L2CAP Channel transmitted SDU event. */
-typedef struct
-{
-  ble_data_t  sdu_buf;       /**< SDU data buffer. */
-} ble_l2cap_evt_ch_tx_t;
-
-/**@brief L2CAP event structure. */
-typedef struct
-{
-  uint16_t conn_handle;                                     /**< Connection Handle on which the event occured. */
-  uint16_t local_cid;                                       /**< Local Channel ID of the L2CAP channel, or
-                                                                 @ref BLE_L2CAP_CID_INVALID if not present. */
-  union
-  {
-    ble_l2cap_evt_ch_setup_request_t    ch_setup_request;   /**< L2CAP Channel Setup Request Event Parameters. */
-    ble_l2cap_evt_ch_setup_refused_t    ch_setup_refused;   /**< L2CAP Channel Setup Refused Event Parameters. */
-    ble_l2cap_evt_ch_setup_t            ch_setup;           /**< L2CAP Channel Setup Completed Event Parameters. */
-    ble_l2cap_evt_ch_sdu_buf_released_t ch_sdu_buf_released;/**< L2CAP Channel SDU Data Buffer Released Event Parameters. */
-    ble_l2cap_evt_ch_credit_t           credit;             /**< L2CAP Channel Credit Received Event Parameters. */
-    ble_l2cap_evt_ch_rx_t               rx;                 /**< L2CAP Channel SDU Received Event Parameters. */
-    ble_l2cap_evt_ch_tx_t               tx;                 /**< L2CAP Channel SDU Transmitted Event Parameters. */
-  } params;                                                 /**< Event Parameters. */
-} ble_l2cap_evt_t;
-
-/** @} */
-
-/**@addtogroup BLE_L2CAP_FUNCTIONS Functions
- * @{ */
-
-/**@brief Set up an L2CAP channel.
- *
- * @details This function is used to:
- *          - Request setup of an L2CAP channel: sends an LE Credit Based Connection Request packet to a peer.
- *          - Reply to a setup request of an L2CAP channel (if called in response to a
- *            @ref BLE_L2CAP_EVT_CH_SETUP_REQUEST event): sends an LE Credit Based Connection
- *            Response packet to a peer.
- *
- * @note    A call to this function will require the application to keep the SDU data buffer alive
- *          until the SDU data buffer is returned in @ref BLE_L2CAP_EVT_CH_RX or
- *          @ref BLE_L2CAP_EVT_CH_SDU_BUF_RELEASED event.
- *
- * @events
- * @event{@ref BLE_L2CAP_EVT_CH_SETUP, Setup successful.}
- * @event{@ref BLE_L2CAP_EVT_CH_SETUP_REFUSED, Setup failed.}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_L2CAP_CH_SETUP_MSC}
- * @endmscs
- *
- * @param[in] conn_handle      Connection Handle.
- * @param[in,out] p_local_cid  Pointer to a uint16_t containing Local Channel ID of the L2CAP channel:
- *                             - As input: @ref BLE_L2CAP_CID_INVALID when requesting setup of an L2CAP
- *                               channel or local_cid provided in the @ref BLE_L2CAP_EVT_CH_SETUP_REQUEST
- *                               event when replying to a setup request of an L2CAP channel.
- *                             - As output: local_cid for this channel.
- * @param[in] p_params         L2CAP channel parameters.
- *
- * @retval ::NRF_SUCCESS                    Successfully queued request or response for transmission.
- * @retval ::NRF_ERROR_BUSY                 The stack is busy, process pending events and retry.
- * @retval ::NRF_ERROR_INVALID_ADDR         Invalid pointer supplied.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE  Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_PARAM        Invalid parameter(s) supplied.
- * @retval ::NRF_ERROR_INVALID_LENGTH       Supplied higher rx_mps than has been configured on this link.
- * @retval ::NRF_ERROR_INVALID_STATE        Invalid State to perform operation (L2CAP channel already set up).
- * @retval ::NRF_ERROR_NOT_FOUND            CID not found.
- * @retval ::NRF_ERROR_RESOURCES            The limit has been reached for available L2CAP channels,
- *                                          see @ref ble_l2cap_conn_cfg_t::ch_count.
- */
-SVCALL(SD_BLE_L2CAP_CH_SETUP, uint32_t, sd_ble_l2cap_ch_setup(uint16_t conn_handle, uint16_t *p_local_cid, ble_l2cap_ch_setup_params_t const *p_params));
-
-/**@brief Release an L2CAP channel.
- *
- * @details This sends a Disconnection Request packet to a peer.
- *
- * @events
- * @event{@ref BLE_L2CAP_EVT_CH_RELEASED, Release complete.}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_L2CAP_CH_RELEASE_MSC}
- * @endmscs
- *
- * @param[in] conn_handle   Connection Handle.
- * @param[in] local_cid     Local Channel ID of the L2CAP channel.
- *
- * @retval ::NRF_SUCCESS                    Successfully queued request for transmission.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE  Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_STATE        Invalid State to perform operation (Setup or release is
- *                                          in progress for the L2CAP channel).
- * @retval ::NRF_ERROR_NOT_FOUND            CID not found.
- */
-SVCALL(SD_BLE_L2CAP_CH_RELEASE, uint32_t, sd_ble_l2cap_ch_release(uint16_t conn_handle, uint16_t local_cid));
-
-/**@brief Receive an SDU on an L2CAP channel.
- *
- * @details This may issue additional credits to the peer using an LE Flow Control Credit packet.
- *
- * @note    A call to this function will require the application to keep the memory pointed by
- *          @ref ble_data_t::p_data alive until the SDU data buffer is returned in @ref BLE_L2CAP_EVT_CH_RX
- *          or @ref BLE_L2CAP_EVT_CH_SDU_BUF_RELEASED event.
- *
- * @note    The SoftDevice can queue up to @ref ble_l2cap_conn_cfg_t::rx_queue_size SDU data buffers
- *          for reception per L2CAP channel.
- *
- * @events
- * @event{@ref BLE_L2CAP_EVT_CH_RX, The SDU is received.}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_L2CAP_CH_RX_MSC}
- * @endmscs
- *
- * @param[in] conn_handle Connection Handle.
- * @param[in] local_cid   Local Channel ID of the L2CAP channel.
- * @param[in] p_sdu_buf   Pointer to the SDU data buffer.
- *
- * @retval ::NRF_SUCCESS                    Buffer accepted.
- * @retval ::NRF_ERROR_INVALID_ADDR         Invalid pointer supplied.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE  Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_STATE        Invalid State to perform operation (Setup or release is
- *                                          in progress for an L2CAP channel).
- * @retval ::NRF_ERROR_NOT_FOUND            CID not found.
- * @retval ::NRF_ERROR_RESOURCES            Too many SDU data buffers supplied. Wait for a
- *                                          @ref BLE_L2CAP_EVT_CH_RX event and retry.
- */
-SVCALL(SD_BLE_L2CAP_CH_RX, uint32_t, sd_ble_l2cap_ch_rx(uint16_t conn_handle, uint16_t local_cid, ble_data_t const *p_sdu_buf));
-
-/**@brief Transmit an SDU on an L2CAP channel.
- *
- * @note    A call to this function will require the application to keep the memory pointed by
- *          @ref ble_data_t::p_data alive until the SDU data buffer is returned in @ref BLE_L2CAP_EVT_CH_TX
- *          or @ref BLE_L2CAP_EVT_CH_SDU_BUF_RELEASED event.
- *
- * @note    The SoftDevice can queue up to @ref ble_l2cap_conn_cfg_t::tx_queue_size SDUs for
- *          transmission per L2CAP channel.
- *
- * @note    The application can keep track of the available credits for transmission by following
- *          the procedure below:
- *          - Store initial credits given by the peer in a variable.
- *            (Initial credits are provided in a @ref BLE_L2CAP_EVT_CH_SETUP event.)
- *          - Decrement the variable, which stores the currently available credits, by
- *            ceiling((@ref ble_data_t::len + 2) / tx_mps) when a call to this function returns
- *            @ref NRF_SUCCESS. (tx_mps is provided in a @ref BLE_L2CAP_EVT_CH_SETUP event.)
- *          - Increment the variable, which stores the currently available credits, by additional
- *            credits given by the peer in a @ref BLE_L2CAP_EVT_CH_CREDIT event.
- *
- * @events
- * @event{@ref BLE_L2CAP_EVT_CH_TX, The SDU is transmitted.}
- * @endevents
- *
- * @mscs
- * @mmsc{@ref BLE_L2CAP_CH_TX_MSC}
- * @endmscs
- *
- * @param[in] conn_handle Connection Handle.
- * @param[in] local_cid   Local Channel ID of the L2CAP channel.
- * @param[in] p_sdu_buf   Pointer to the SDU data buffer.
- *
- * @retval ::NRF_SUCCESS                    Successfully queued L2CAP SDU for transmission.
- * @retval ::NRF_ERROR_INVALID_ADDR         Invalid pointer supplied.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE  Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_STATE        Invalid State to perform operation (Setup or release is
- *                                          in progress for the L2CAP channel).
- * @retval ::NRF_ERROR_NOT_FOUND            CID not found.
- * @retval ::NRF_ERROR_DATA_SIZE            Invalid SDU length supplied, must not be more than
- *                                          @ref ble_l2cap_ch_tx_params_t::tx_mtu provided in
- *                                          @ref BLE_L2CAP_EVT_CH_SETUP event.
- * @retval ::NRF_ERROR_RESOURCES            Too many SDUs queued for transmission. Wait for a
- *                                          @ref BLE_L2CAP_EVT_CH_TX event and retry.
- */
-SVCALL(SD_BLE_L2CAP_CH_TX, uint32_t, sd_ble_l2cap_ch_tx(uint16_t conn_handle, uint16_t local_cid, ble_data_t const *p_sdu_buf));
-
-/**@brief Advanced SDU reception flow control.
- *
- * @details Adjust the way the SoftDevice issues credits to the peer.
- *          This may issue additional credits to the peer using an LE Flow Control Credit packet.
- *
- * @mscs
- * @mmsc{@ref BLE_L2CAP_CH_FLOW_CONTROL_MSC}
- * @endmscs
- *
- * @param[in] conn_handle Connection Handle.
- * @param[in] local_cid   Local Channel ID of the L2CAP channel or @ref BLE_L2CAP_CID_INVALID to set
- *                        the value that will be used for newly created channels.
- * @param[in] credits     Number of credits that the SoftDevice will make sure the peer has every
- *                        time it starts using a new reception buffer.
- *                        - @ref BLE_L2CAP_CREDITS_DEFAULT is the default value the SoftDevice will
- *                          use if this function is not called.
- *                        - If set to zero, the SoftDevice will stop issuing credits for new reception
- *                          buffers the application provides or has provided. SDU reception that is
- *                          currently ongoing will be allowed to complete.
- * @param[out] p_credits  NULL or pointer to a uint16_t. If a valid pointer is provided, it will be
- *                        written by the SoftDevice with the number of credits that is or will be
- *                        available to the peer. If the value written by the SoftDevice is 0 when
- *                        credits parameter was set to 0, the peer will not be able to send more
- *                        data until more credits are provided by calling this function again with
- *                        credits > 0. This parameter is ignored when local_cid is set to
- *                        @ref BLE_L2CAP_CID_INVALID.
- *
- * @note Application should take care when setting number of credits higher than default value. In
- *       this case the application must make sure that the SoftDevice always has reception buffers
- *       available (see @ref sd_ble_l2cap_ch_rx) for that channel. If the SoftDevice does not have
- *       such buffers available, packets may be NACKed on the Link Layer and all Bluetooth traffic
- *       on the connection handle may be stalled until the SoftDevice again has an available
- *       reception buffer. This applies even if the application has used this call to set the
- *       credits back to default, or zero.
- *
- * @retval ::NRF_SUCCESS                    Flow control parameters accepted.
- * @retval ::NRF_ERROR_INVALID_ADDR         Invalid pointer supplied.
- * @retval ::BLE_ERROR_INVALID_CONN_HANDLE  Invalid Connection Handle.
- * @retval ::NRF_ERROR_INVALID_STATE        Invalid State to perform operation (Setup or release is
- *                                          in progress for an L2CAP channel).
- * @retval ::NRF_ERROR_NOT_FOUND            CID not found.
- */
-SVCALL(SD_BLE_L2CAP_CH_FLOW_CONTROL, uint32_t, sd_ble_l2cap_ch_flow_control(uint16_t conn_handle, uint16_t local_cid, uint16_t credits, uint16_t *p_credits));
-
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif
-#endif // BLE_L2CAP_H__
-
-/**
-  @}
-*/
diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_ranges.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_ranges.h
deleted file mode 100755
index 0935bca0..00000000
--- a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_ranges.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- *    list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form, except as embedded into a Nordic
- *    Semiconductor ASA integrated circuit in a product or a software update for
- *    such product, must reproduce the above copyright notice, this list of
- *    conditions and the following disclaimer in the documentation and/or other
- *    materials provided with the distribution.
- *
- * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
- *    contributors may be used to endorse or promote products derived from this
- *    software without specific prior written permission.
- *
- * 4. This software, with or without modification, must only be used with a
- *    Nordic Semiconductor ASA integrated circuit.
- *
- * 5. Any software provided in binary form under this license must not be reverse
- *    engineered, decompiled, modified and/or disassembled.
- *
- * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
-  @addtogroup BLE_COMMON
-  @{
-  @defgroup ble_ranges Module specific SVC, event and option number subranges
-  @{
-
-  @brief Definition of SVC, event and option number subranges for each API module.
-
-  @note
-  SVCs, event and option numbers are split into subranges for each API module.
-  Each module receives its entire allocated range of SVC calls, whether implemented or not,
-  but return BLE_ERROR_NOT_SUPPORTED for unimplemented or undefined calls in its range.
-
-  Note that the symbols BLE_<module>_SVC_LAST is the end of the allocated SVC range,
-  rather than the last SVC function call actually defined and implemented.
-
-  Specific SVC, event and option values are defined in each module's ble_<module>.h file,
-  which defines names of each individual SVC code based on the range start value.
-*/
-
-#ifndef BLE_RANGES_H__
-#define BLE_RANGES_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define BLE_SVC_BASE           0x60       /**< Common BLE SVC base. */
-#define BLE_SVC_LAST           0x6B       /**< Common BLE SVC last. */
-
-#define BLE_GAP_SVC_BASE       0x6C       /**< GAP BLE SVC base. */
-#define BLE_GAP_SVC_LAST       0x9A       /**< GAP BLE SVC last. */
-
-#define BLE_GATTC_SVC_BASE     0x9B       /**< GATTC BLE SVC base. */
-#define BLE_GATTC_SVC_LAST     0xA7       /**< GATTC BLE SVC last. */
-
-#define BLE_GATTS_SVC_BASE     0xA8       /**< GATTS BLE SVC base. */
-#define BLE_GATTS_SVC_LAST     0xB7       /**< GATTS BLE SVC last. */
-
-#define BLE_L2CAP_SVC_BASE     0xB8       /**< L2CAP BLE SVC base. */
-#define BLE_L2CAP_SVC_LAST     0xBF       /**< L2CAP BLE SVC last. */
-
-
-#define BLE_EVT_INVALID        0x00       /**< Invalid BLE Event. */
-
-#define BLE_EVT_BASE           0x01       /**< Common BLE Event base. */
-#define BLE_EVT_LAST           0x0F       /**< Common BLE Event last. */
-
-#define BLE_GAP_EVT_BASE       0x10       /**< GAP BLE Event base. */
-#define BLE_GAP_EVT_LAST       0x2F       /**< GAP BLE Event last. */
-
-#define BLE_GATTC_EVT_BASE     0x30       /**< GATTC BLE Event base. */
-#define BLE_GATTC_EVT_LAST     0x4F       /**< GATTC BLE Event last. */
-
-#define BLE_GATTS_EVT_BASE     0x50       /**< GATTS BLE Event base. */
-#define BLE_GATTS_EVT_LAST     0x6F       /**< GATTS BLE Event last. */
-
-#define BLE_L2CAP_EVT_BASE     0x70       /**< L2CAP BLE Event base. */
-#define BLE_L2CAP_EVT_LAST     0x8F       /**< L2CAP BLE Event last. */
-
-
-#define BLE_OPT_INVALID        0x00       /**< Invalid BLE Option. */
-
-#define BLE_OPT_BASE           0x01       /**< Common BLE Option base. */
-#define BLE_OPT_LAST           0x1F       /**< Common BLE Option last. */
-
-#define BLE_GAP_OPT_BASE       0x20       /**< GAP BLE Option base. */
-#define BLE_GAP_OPT_LAST       0x3F       /**< GAP BLE Option last. */
-
-#define BLE_GATT_OPT_BASE      0x40       /**< GATT BLE Option base. */
-#define BLE_GATT_OPT_LAST      0x5F       /**< GATT BLE Option last. */
-
-#define BLE_GATTC_OPT_BASE     0x60       /**< GATTC BLE Option base. */
-#define BLE_GATTC_OPT_LAST     0x7F       /**< GATTC BLE Option last. */
-
-#define BLE_GATTS_OPT_BASE     0x80       /**< GATTS BLE Option base. */
-#define BLE_GATTS_OPT_LAST     0x9F       /**< GATTS BLE Option last. */
-
-#define BLE_L2CAP_OPT_BASE     0xA0       /**< L2CAP BLE Option base. */
-#define BLE_L2CAP_OPT_LAST     0xBF       /**< L2CAP BLE Option last. */
-
-
-#define BLE_CFG_INVALID        0x00       /**< Invalid BLE configuration. */
-
-#define BLE_CFG_BASE           0x01       /**< Common BLE configuration base. */
-#define BLE_CFG_LAST           0x1F       /**< Common BLE configuration last. */
-
-#define BLE_CONN_CFG_BASE      0x20       /**< BLE connection configuration base. */
-#define BLE_CONN_CFG_LAST      0x3F       /**< BLE connection configuration last. */
-
-#define BLE_GAP_CFG_BASE       0x40       /**< GAP BLE configuration base. */
-#define BLE_GAP_CFG_LAST       0x5F       /**< GAP BLE configuration last. */
-
-#define BLE_GATT_CFG_BASE      0x60       /**< GATT BLE configuration base. */
-#define BLE_GATT_CFG_LAST      0x7F       /**< GATT BLE configuration last. */
-
-#define BLE_GATTC_CFG_BASE     0x80       /**< GATTC BLE configuration base. */
-#define BLE_GATTC_CFG_LAST     0x9F       /**< GATTC BLE configuration last. */
-
-#define BLE_GATTS_CFG_BASE     0xA0       /**< GATTS BLE configuration base. */
-#define BLE_GATTS_CFG_LAST     0xBF       /**< GATTS BLE configuration last. */
-
-#define BLE_L2CAP_CFG_BASE     0xC0       /**< L2CAP BLE configuration base. */
-#define BLE_L2CAP_CFG_LAST     0xDF       /**< L2CAP BLE configuration last. */
-
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* BLE_RANGES_H__ */
-
-/**
-  @}
-  @}
-*/
diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_types.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_types.h
deleted file mode 100755
index 88c93180..00000000
--- a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_types.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * Copyright (c) 2012 - 2017, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- *    list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form, except as embedded into a Nordic
- *    Semiconductor ASA integrated circuit in a product or a software update for
- *    such product, must reproduce the above copyright notice, this list of
- *    conditions and the following disclaimer in the documentation and/or other
- *    materials provided with the distribution.
- *
- * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
- *    contributors may be used to endorse or promote products derived from this
- *    software without specific prior written permission.
- *
- * 4. This software, with or without modification, must only be used with a
- *    Nordic Semiconductor ASA integrated circuit.
- *
- * 5. Any software provided in binary form under this license must not be reverse
- *    engineered, decompiled, modified and/or disassembled.
- *
- * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
-  @addtogroup BLE_COMMON
-  @{
-  @defgroup ble_types Common types and macro definitions
-  @{
-
-  @brief Common types and macro definitions for the BLE SoftDevice.
- */
-
-#ifndef BLE_TYPES_H__
-#define BLE_TYPES_H__
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @addtogroup BLE_TYPES_DEFINES Defines
- * @{ */
-
-/** @defgroup BLE_CONN_HANDLES BLE Connection Handles
- * @{ */
-#define BLE_CONN_HANDLE_INVALID 0xFFFF  /**< Invalid Connection Handle. */
-#define BLE_CONN_HANDLE_ALL     0xFFFE  /**< Applies to all Connection Handles. */
-/** @} */
-
-
-/** @defgroup BLE_UUID_VALUES Assigned Values for BLE UUIDs
- * @{ */
-/* Generic UUIDs, applicable to all services */
-#define BLE_UUID_UNKNOWN                              0x0000 /**< Reserved UUID. */
-#define BLE_UUID_SERVICE_PRIMARY                      0x2800 /**< Primary Service. */
-#define BLE_UUID_SERVICE_SECONDARY                    0x2801 /**< Secondary Service. */
-#define BLE_UUID_SERVICE_INCLUDE                      0x2802 /**< Include. */
-#define BLE_UUID_CHARACTERISTIC                       0x2803 /**< Characteristic. */
-#define BLE_UUID_DESCRIPTOR_CHAR_EXT_PROP             0x2900 /**< Characteristic Extended Properties Descriptor. */
-#define BLE_UUID_DESCRIPTOR_CHAR_USER_DESC            0x2901 /**< Characteristic User Description Descriptor. */
-#define BLE_UUID_DESCRIPTOR_CLIENT_CHAR_CONFIG        0x2902 /**< Client Characteristic Configuration Descriptor. */
-#define BLE_UUID_DESCRIPTOR_SERVER_CHAR_CONFIG        0x2903 /**< Server Characteristic Configuration Descriptor. */
-#define BLE_UUID_DESCRIPTOR_CHAR_PRESENTATION_FORMAT  0x2904 /**< Characteristic Presentation Format Descriptor. */
-#define BLE_UUID_DESCRIPTOR_CHAR_AGGREGATE_FORMAT     0x2905 /**< Characteristic Aggregate Format Descriptor. */
-/* GATT specific UUIDs */
-#define BLE_UUID_GATT                                 0x1801 /**< Generic Attribute Profile. */
-#define BLE_UUID_GATT_CHARACTERISTIC_SERVICE_CHANGED  0x2A05 /**< Service Changed Characteristic. */
-/* GAP specific UUIDs */
-#define BLE_UUID_GAP                                  0x1800 /**< Generic Access Profile. */
-#define BLE_UUID_GAP_CHARACTERISTIC_DEVICE_NAME       0x2A00 /**< Device Name Characteristic. */
-#define BLE_UUID_GAP_CHARACTERISTIC_APPEARANCE        0x2A01 /**< Appearance Characteristic. */
-#define BLE_UUID_GAP_CHARACTERISTIC_RECONN_ADDR       0x2A03 /**< Reconnection Address Characteristic. */
-#define BLE_UUID_GAP_CHARACTERISTIC_PPCP              0x2A04 /**< Peripheral Preferred Connection Parameters Characteristic. */
-#define BLE_UUID_GAP_CHARACTERISTIC_CAR               0x2AA6 /**< Central Address Resolution Characteristic. */
-#define BLE_UUID_GAP_CHARACTERISTIC_RPA_ONLY          0x2AC9 /**< Resolvable Private Address Only Characteristic. */
-/** @} */
-
-
-/** @defgroup BLE_UUID_TYPES Types of UUID
- * @{ */
-#define BLE_UUID_TYPE_UNKNOWN       0x00 /**< Invalid UUID type. */
-#define BLE_UUID_TYPE_BLE           0x01 /**< Bluetooth SIG UUID (16-bit). */
-#define BLE_UUID_TYPE_VENDOR_BEGIN  0x02 /**< Vendor UUID types start at this index (128-bit). */
-/** @} */
-
-
-/** @defgroup BLE_APPEARANCES Bluetooth Appearance values
- *  @note Retrieved from http://developer.bluetooth.org/gatt/characteristics/Pages/CharacteristicViewer.aspx?u=org.bluetooth.characteristic.gap.appearance.xml
- * @{ */
-#define BLE_APPEARANCE_UNKNOWN                                0 /**< Unknown. */
-#define BLE_APPEARANCE_GENERIC_PHONE                         64 /**< Generic Phone. */
-#define BLE_APPEARANCE_GENERIC_COMPUTER                     128 /**< Generic Computer. */
-#define BLE_APPEARANCE_GENERIC_WATCH                        192 /**< Generic Watch. */
-#define BLE_APPEARANCE_WATCH_SPORTS_WATCH                   193 /**< Watch: Sports Watch. */
-#define BLE_APPEARANCE_GENERIC_CLOCK                        256 /**< Generic Clock. */
-#define BLE_APPEARANCE_GENERIC_DISPLAY                      320 /**< Generic Display. */
-#define BLE_APPEARANCE_GENERIC_REMOTE_CONTROL               384 /**< Generic Remote Control. */
-#define BLE_APPEARANCE_GENERIC_EYE_GLASSES                  448 /**< Generic Eye-glasses. */
-#define BLE_APPEARANCE_GENERIC_TAG                          512 /**< Generic Tag. */
-#define BLE_APPEARANCE_GENERIC_KEYRING                      576 /**< Generic Keyring. */
-#define BLE_APPEARANCE_GENERIC_MEDIA_PLAYER                 640 /**< Generic Media Player. */
-#define BLE_APPEARANCE_GENERIC_BARCODE_SCANNER              704 /**< Generic Barcode Scanner. */
-#define BLE_APPEARANCE_GENERIC_THERMOMETER                  768 /**< Generic Thermometer. */
-#define BLE_APPEARANCE_THERMOMETER_EAR                      769 /**< Thermometer: Ear. */
-#define BLE_APPEARANCE_GENERIC_HEART_RATE_SENSOR            832 /**< Generic Heart rate Sensor. */
-#define BLE_APPEARANCE_HEART_RATE_SENSOR_HEART_RATE_BELT    833 /**< Heart Rate Sensor: Heart Rate Belt. */
-#define BLE_APPEARANCE_GENERIC_BLOOD_PRESSURE               896 /**< Generic Blood Pressure. */
-#define BLE_APPEARANCE_BLOOD_PRESSURE_ARM                   897 /**< Blood Pressure: Arm. */
-#define BLE_APPEARANCE_BLOOD_PRESSURE_WRIST                 898 /**< Blood Pressure: Wrist. */
-#define BLE_APPEARANCE_GENERIC_HID                          960 /**< Human Interface Device (HID). */
-#define BLE_APPEARANCE_HID_KEYBOARD                         961 /**< Keyboard (HID Subtype). */
-#define BLE_APPEARANCE_HID_MOUSE                            962 /**< Mouse (HID Subtype). */
-#define BLE_APPEARANCE_HID_JOYSTICK                         963 /**< Joystick (HID Subtype). */
-#define BLE_APPEARANCE_HID_GAMEPAD                          964 /**< Gamepad (HID Subtype). */
-#define BLE_APPEARANCE_HID_DIGITIZERSUBTYPE                 965 /**< Digitizer Tablet (HID Subtype). */
-#define BLE_APPEARANCE_HID_CARD_READER                      966 /**< Card Reader (HID Subtype). */
-#define BLE_APPEARANCE_HID_DIGITAL_PEN                      967 /**< Digital Pen (HID Subtype). */
-#define BLE_APPEARANCE_HID_BARCODE                          968 /**< Barcode Scanner (HID Subtype). */
-#define BLE_APPEARANCE_GENERIC_GLUCOSE_METER               1024 /**< Generic Glucose Meter. */
-#define BLE_APPEARANCE_GENERIC_RUNNING_WALKING_SENSOR      1088 /**< Generic Running Walking Sensor. */
-#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_IN_SHOE      1089 /**< Running Walking Sensor: In-Shoe. */
-#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_ON_SHOE      1090 /**< Running Walking Sensor: On-Shoe. */
-#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_ON_HIP       1091 /**< Running Walking Sensor: On-Hip. */
-#define BLE_APPEARANCE_GENERIC_CYCLING                     1152 /**< Generic Cycling. */
-#define BLE_APPEARANCE_CYCLING_CYCLING_COMPUTER            1153 /**< Cycling: Cycling Computer. */
-#define BLE_APPEARANCE_CYCLING_SPEED_SENSOR                1154 /**< Cycling: Speed Sensor. */
-#define BLE_APPEARANCE_CYCLING_CADENCE_SENSOR              1155 /**< Cycling: Cadence Sensor. */
-#define BLE_APPEARANCE_CYCLING_POWER_SENSOR                1156 /**< Cycling: Power Sensor. */
-#define BLE_APPEARANCE_CYCLING_SPEED_CADENCE_SENSOR        1157 /**< Cycling: Speed and Cadence Sensor. */
-#define BLE_APPEARANCE_GENERIC_PULSE_OXIMETER              3136 /**< Generic Pulse Oximeter. */
-#define BLE_APPEARANCE_PULSE_OXIMETER_FINGERTIP            3137 /**< Fingertip (Pulse Oximeter subtype). */
-#define BLE_APPEARANCE_PULSE_OXIMETER_WRIST_WORN           3138 /**< Wrist Worn(Pulse Oximeter subtype). */
-#define BLE_APPEARANCE_GENERIC_WEIGHT_SCALE                3200 /**< Generic Weight Scale. */
-#define BLE_APPEARANCE_GENERIC_OUTDOOR_SPORTS_ACT          5184 /**< Generic Outdoor Sports Activity. */
-#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_DISP         5185 /**< Location Display Device (Outdoor Sports Activity subtype). */
-#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_AND_NAV_DISP 5186 /**< Location and Navigation Display Device (Outdoor Sports Activity subtype). */
-#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_POD          5187 /**< Location Pod (Outdoor Sports Activity subtype). */
-#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_AND_NAV_POD  5188 /**< Location and Navigation Pod (Outdoor Sports Activity subtype). */
-/** @} */
-
-/** @brief Set .type and .uuid fields of ble_uuid_struct to specified UUID value. */
-#define BLE_UUID_BLE_ASSIGN(instance, value) do {\
-            instance.type = BLE_UUID_TYPE_BLE; \
-            instance.uuid = value;} while(0)
-
-/** @brief Copy type and uuid members from src to dst ble_uuid_t pointer. Both pointers must be valid/non-null. */
-#define BLE_UUID_COPY_PTR(dst, src) do {\
-            (dst)->type = (src)->type; \
-            (dst)->uuid = (src)->uuid;} while(0)
-
-/** @brief Copy type and uuid members from src to dst ble_uuid_t struct. */
-#define BLE_UUID_COPY_INST(dst, src) do {\
-            (dst).type = (src).type; \
-            (dst).uuid = (src).uuid;} while(0)
-
-/** @brief Compare for equality both type and uuid members of two (valid, non-null) ble_uuid_t pointers. */
-#define BLE_UUID_EQ(p_uuid1, p_uuid2) \
-            (((p_uuid1)->type == (p_uuid2)->type) && ((p_uuid1)->uuid == (p_uuid2)->uuid))
-
-/** @brief Compare for difference both type and uuid members of two (valid, non-null) ble_uuid_t pointers. */
-#define BLE_UUID_NEQ(p_uuid1, p_uuid2) \
-            (((p_uuid1)->type != (p_uuid2)->type) || ((p_uuid1)->uuid != (p_uuid2)->uuid))
-
-/** @} */
-
-/** @addtogroup BLE_TYPES_STRUCTURES Structures
- * @{ */
-
-/** @brief 128 bit UUID values. */
-typedef struct
-{
-  uint8_t uuid128[16]; /**< Little-Endian UUID bytes. */
-} ble_uuid128_t;
-
-/** @brief  Bluetooth Low Energy UUID type, encapsulates both 16-bit and 128-bit UUIDs. */
-typedef struct
-{
-  uint16_t    uuid; /**< 16-bit UUID value or octets 12-13 of 128-bit UUID. */
-  uint8_t     type; /**< UUID type, see @ref BLE_UUID_TYPES. If type is @ref BLE_UUID_TYPE_UNKNOWN, the value of uuid is undefined. */
-} ble_uuid_t;
-
-/**@brief Data structure. */
-typedef struct
-{
-  uint8_t     *p_data;  /**< Pointer to the data buffer provided to/from the application. */
-  uint16_t     len;     /**< Length of the data buffer, in bytes. */
-} ble_data_t;
-
-/** @} */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* BLE_TYPES_H__ */
-
-/**
-  @}
-  @}
-*/
diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf52/nrf_mbr.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf52/nrf_mbr.h
deleted file mode 100755
index 42e09fc8..00000000
--- a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf52/nrf_mbr.h
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * Copyright (c) 2014 - 2017, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- *    list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form, except as embedded into a Nordic
- *    Semiconductor ASA integrated circuit in a product or a software update for
- *    such product, must reproduce the above copyright notice, this list of
- *    conditions and the following disclaimer in the documentation and/or other
- *    materials provided with the distribution.
- *
- * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
- *    contributors may be used to endorse or promote products derived from this
- *    software without specific prior written permission.
- *
- * 4. This software, with or without modification, must only be used with a
- *    Nordic Semiconductor ASA integrated circuit.
- *
- * 5. Any software provided in binary form under this license must not be reverse
- *    engineered, decompiled, modified and/or disassembled.
- *
- * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
-  @defgroup nrf_mbr_api Master Boot Record API
-  @{
-
-  @brief APIs for updating SoftDevice and BootLoader
-
-*/
-
-#ifndef NRF_MBR_H__
-#define NRF_MBR_H__
-
-#include "nrf_svc.h"
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @addtogroup NRF_MBR_DEFINES Defines
- * @{ */
-
-/**@brief MBR SVC Base number. */
-#define MBR_SVC_BASE            (0x18)
-
-/**@brief Page size in words. */
-#define MBR_PAGE_SIZE_IN_WORDS  (1024)
-
-/** @brief The size that must be reserved for the MBR when a SoftDevice is written to flash.
-This is the offset where the first byte of the SoftDevice hex file is written. */
-#define MBR_SIZE                (0x1000)
-
-/** @brief Location (in the flash memory) of the bootloader address. */
-#define MBR_BOOTLOADER_ADDR      (0xFF8)
-
-/** @brief Location (in UICR) of the bootloader address. */
-#define MBR_UICR_BOOTLOADER_ADDR (&(NRF_UICR->NRFFW[0]))
-
-/** @brief Location (in the flash memory) of the address of the MBR parameter page. */
-#define MBR_PARAM_PAGE_ADDR      (0xFFC)
-
-/** @brief Location (in UICR) of the address of the MBR parameter page. */
-#define MBR_UICR_PARAM_PAGE_ADDR (&(NRF_UICR->NRFFW[1]))
-
-
-/** @} */
-
-/** @addtogroup NRF_MBR_ENUMS Enumerations
- * @{ */
-
-/**@brief nRF Master Boot Record API SVC numbers. */
-enum NRF_MBR_SVCS
-{
-  SD_MBR_COMMAND = MBR_SVC_BASE, /**< ::sd_mbr_command */
-};
-
-/**@brief Possible values for ::sd_mbr_command_t.command */
-enum NRF_MBR_COMMANDS
-{
-  SD_MBR_COMMAND_COPY_BL,                 /**< Copy a new BootLoader. @see ::sd_mbr_command_copy_bl_t*/
-  SD_MBR_COMMAND_COPY_SD,                 /**< Copy a new SoftDevice. @see ::sd_mbr_command_copy_sd_t*/
-  SD_MBR_COMMAND_INIT_SD,                 /**< Initialize forwarding interrupts to SD, and run reset function in SD. Does not require any parameters in ::sd_mbr_command_t params.*/
-  SD_MBR_COMMAND_COMPARE,                 /**< This command works like memcmp. @see ::sd_mbr_command_compare_t*/
-  SD_MBR_COMMAND_VECTOR_TABLE_BASE_SET,   /**< Change the address the MBR starts after a reset. @see ::sd_mbr_command_vector_table_base_set_t*/
-  SD_MBR_COMMAND_RESERVED,
-  SD_MBR_COMMAND_IRQ_FORWARD_ADDRESS_SET, /**< Start forwarding all interrupts to this address. @see ::sd_mbr_command_irq_forward_address_set_t*/
-};
-
-/** @} */
-
-/** @addtogroup NRF_MBR_TYPES Types
- * @{ */
-
-/**@brief This command copies part of a new SoftDevice
- *
- * The destination area is erased before copying.
- * If dst is in the middle of a flash page, that whole flash page will be erased.
- * If (dst+len) is in the middle of a flash page, that whole flash page will be erased.
- *
- * The user of this function is responsible for setting the BPROT registers.
- *
- * @retval ::NRF_SUCCESS indicates that the contents of the memory blocks where copied correctly.
- * @retval ::NRF_ERROR_INTERNAL indicates that the contents of the memory blocks where not verified correctly after copying.
- */
-typedef struct
-{
-  uint32_t *src;  /**< Pointer to the source of data to be copied.*/
-  uint32_t *dst;  /**< Pointer to the destination where the content is to be copied.*/
-  uint32_t len;   /**< Number of 32 bit words to copy. Must be a multiple of @ref MBR_PAGE_SIZE_IN_WORDS words.*/
-} sd_mbr_command_copy_sd_t;
-
-
-/**@brief This command works like memcmp, but takes the length in words.
- *
- * @retval ::NRF_SUCCESS indicates that the contents of both memory blocks are equal.
- * @retval ::NRF_ERROR_NULL indicates that the contents of the memory blocks are not equal.
- */
-typedef struct
-{
-  uint32_t *ptr1; /**< Pointer to block of memory. */
-  uint32_t *ptr2; /**< Pointer to block of memory. */
-  uint32_t len;   /**< Number of 32 bit words to compare.*/
-} sd_mbr_command_compare_t;
-
-
-/**@brief This command copies a new BootLoader.
- *
- * The MBR assumes that either @ref MBR_BOOTLOADER_ADDR or @ref MBR_UICR_BOOTLOADER_ADDR is set to
- * the address where the bootloader will be copied. If both addresses are set, the MBR will prioritize
- * @ref MBR_BOOTLOADER_ADDR.
- *
- * The bootloader destination is erased by this function.
- * If (destination+bl_len) is in the middle of a flash page, that whole flash page will be erased.
- *
- * This command requires that @ref MBR_PARAM_PAGE_ADDR or @ref MBR_UICR_PARAM_PAGE_ADDR is set,
- * see @ref sd_mbr_command.
- *
- * This command will use the flash protect peripheral (BPROT or ACL) to protect the flash that is
- * not intended to be written.
- *
- * On success, this function will not return. It will start the new bootloader from reset-vector as normal.
- *
- * @retval ::NRF_ERROR_INTERNAL indicates an internal error that should not happen.
- * @retval ::NRF_ERROR_FORBIDDEN if the bootloader address is not set.
- * @retval ::NRF_ERROR_INVALID_LENGTH if parameters attempts to read or write outside flash area.
- * @retval ::NRF_ERROR_NO_MEM No MBR parameter page is provided. See @ref sd_mbr_command.
- */
-typedef struct
-{
-  uint32_t *bl_src;  /**< Pointer to the source of the bootloader to be be copied.*/
-  uint32_t bl_len;   /**< Number of 32 bit words to copy for BootLoader. */
-} sd_mbr_command_copy_bl_t;
-
-/**@brief Change the address the MBR starts after a reset
- *
- * Once this function has been called, this address is where the MBR will start to forward
- * interrupts to after a reset.
- *
- * To restore default forwarding, this function should be called with @ref address set to 0. If a
- * bootloader is present, interrupts will be forwarded to the bootloader. If not, interrupts will
- * be forwarded to the SoftDevice.
- *
- * The location of a bootloader can be specified in @ref MBR_BOOTLOADER_ADDR or
- * @ref MBR_UICR_BOOTLOADER_ADDR. If both addresses are set, the MBR will prioritize
- * @ref MBR_BOOTLOADER_ADDR.
- *
- * This command requires that @ref MBR_PARAM_PAGE_ADDR or @ref MBR_UICR_PARAM_PAGE_ADDR is set,
- * see @ref sd_mbr_command.
- *
- * On success, this function will not return. It will reset the device.
- *
- * @retval ::NRF_ERROR_INTERNAL indicates an internal error that should not happen.
- * @retval ::NRF_ERROR_INVALID_ADDR if parameter address is outside of the flash size.
- * @retval ::NRF_ERROR_NO_MEM No MBR parameter page is provided. See @ref sd_mbr_command.
- */
-typedef struct
-{
-  uint32_t address; /**< The base address of the interrupt vector table for forwarded interrupts.*/
-} sd_mbr_command_vector_table_base_set_t;
-
-/**@brief Sets the base address of the interrupt vector table for interrupts forwarded from the MBR
- *
- * Unlike sd_mbr_command_vector_table_base_set_t, this function does not reset, and it does not
- * change where the MBR starts after reset.
- *
- * @retval ::NRF_SUCCESS
- */
-typedef struct
-{
-  uint32_t address; /**< The base address of the interrupt vector table for forwarded interrupts.*/
-} sd_mbr_command_irq_forward_address_set_t;
-
-/**@brief Input structure containing data used when calling ::sd_mbr_command
- *
- * Depending on what command value that is set, the corresponding params value type must also be
- * set. See @ref NRF_MBR_COMMANDS for command types and corresponding params value type. If command
- * @ref SD_MBR_COMMAND_INIT_SD is set, it is not necessary to set any values under params.
- */
-typedef struct
-{
-  uint32_t command;  /**< Type of command to be issued. See @ref NRF_MBR_COMMANDS. */
-  union
-  {
-    sd_mbr_command_copy_sd_t copy_sd;  /**< Parameters for copy SoftDevice.*/
-    sd_mbr_command_compare_t compare;  /**< Parameters for verify.*/
-    sd_mbr_command_copy_bl_t copy_bl;  /**< Parameters for copy BootLoader. Requires parameter page. */
-    sd_mbr_command_vector_table_base_set_t base_set; /**< Parameters for vector table base set. Requires parameter page.*/
-    sd_mbr_command_irq_forward_address_set_t irq_forward_address_set; /**< Parameters for irq forward address set*/
-  } params; /**< Command parameters. */
-} sd_mbr_command_t;
-
-/** @} */
-
-/** @addtogroup NRF_MBR_FUNCTIONS Functions
- * @{ */
-
-/**@brief Issue Master Boot Record commands
- *
- * Commands used when updating a SoftDevice and bootloader.
- *
- * The @ref SD_MBR_COMMAND_COPY_BL and @ref SD_MBR_COMMAND_VECTOR_TABLE_BASE_SET requires
- * parameters to be retained by the MBR when resetting the IC. This is done in a separate flash
- * page. The location of the flash page should be provided by the application in either
- * @ref MBR_PARAM_PAGE_ADDR or @ref MBR_UICR_PARAM_PAGE_ADDR. If both addresses are set, the MBR
- * will prioritize @ref MBR_PARAM_PAGE_ADDR. This page will be cleared by the MBR and is used to
- * store the command before reset. When an address is specified, the page it refers to must not be
- * used by the application. If no address is provided by the application, i.e. both
- * @ref MBR_PARAM_PAGE_ADDR and @ref MBR_UICR_PARAM_PAGE_ADDR is 0xFFFFFFFF, MBR commands which use
- * flash will be unavailable and return @ref NRF_ERROR_NO_MEM.
- *
- * @param[in]  param Pointer to a struct describing the command.
- *
- * @note For a complete set of return values, see ::sd_mbr_command_copy_sd_t,
- *       ::sd_mbr_command_copy_bl_t, ::sd_mbr_command_compare_t,
- *       ::sd_mbr_command_vector_table_base_set_t, ::sd_mbr_command_irq_forward_address_set_t
- *
- * @retval ::NRF_ERROR_NO_MEM No MBR parameter page provided
- * @retval ::NRF_ERROR_INVALID_PARAM if an invalid command is given.
-*/
-SVCALL(SD_MBR_COMMAND, uint32_t, sd_mbr_command(sd_mbr_command_t* param));
-
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif
-#endif // NRF_MBR_H__
-
-/**
-  @}
-*/
diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_error.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_error.h
deleted file mode 100755
index 6badee98..00000000
--- a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_error.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright (c) 2014 - 2017, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- *    list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form, except as embedded into a Nordic
- *    Semiconductor ASA integrated circuit in a product or a software update for
- *    such product, must reproduce the above copyright notice, this list of
- *    conditions and the following disclaimer in the documentation and/or other
- *    materials provided with the distribution.
- *
- * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
- *    contributors may be used to endorse or promote products derived from this
- *    software without specific prior written permission.
- *
- * 4. This software, with or without modification, must only be used with a
- *    Nordic Semiconductor ASA integrated circuit.
- *
- * 5. Any software provided in binary form under this license must not be reverse
- *    engineered, decompiled, modified and/or disassembled.
- *
- * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
- /**
-  @defgroup nrf_error SoftDevice Global Error Codes
-  @{
-
-  @brief Global Error definitions
-*/
-
-/* Header guard */
-#ifndef NRF_ERROR_H__
-#define NRF_ERROR_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup NRF_ERRORS_BASE Error Codes Base number definitions
- * @{ */
-#define NRF_ERROR_BASE_NUM      (0x0)       ///< Global error base
-#define NRF_ERROR_SDM_BASE_NUM  (0x1000)    ///< SDM error base
-#define NRF_ERROR_SOC_BASE_NUM  (0x2000)    ///< SoC error base
-#define NRF_ERROR_STK_BASE_NUM  (0x3000)    ///< STK error base
-/** @} */
-
-#define NRF_SUCCESS                           (NRF_ERROR_BASE_NUM + 0)  ///< Successful command
-#define NRF_ERROR_SVC_HANDLER_MISSING         (NRF_ERROR_BASE_NUM + 1)  ///< SVC handler is missing
-#define NRF_ERROR_SOFTDEVICE_NOT_ENABLED      (NRF_ERROR_BASE_NUM + 2)  ///< SoftDevice has not been enabled
-#define NRF_ERROR_INTERNAL                    (NRF_ERROR_BASE_NUM + 3)  ///< Internal Error
-#define NRF_ERROR_NO_MEM                      (NRF_ERROR_BASE_NUM + 4)  ///< No Memory for operation
-#define NRF_ERROR_NOT_FOUND                   (NRF_ERROR_BASE_NUM + 5)  ///< Not found
-#define NRF_ERROR_NOT_SUPPORTED               (NRF_ERROR_BASE_NUM + 6)  ///< Not supported
-#define NRF_ERROR_INVALID_PARAM               (NRF_ERROR_BASE_NUM + 7)  ///< Invalid Parameter
-#define NRF_ERROR_INVALID_STATE               (NRF_ERROR_BASE_NUM + 8)  ///< Invalid state, operation disallowed in this state
-#define NRF_ERROR_INVALID_LENGTH              (NRF_ERROR_BASE_NUM + 9)  ///< Invalid Length
-#define NRF_ERROR_INVALID_FLAGS               (NRF_ERROR_BASE_NUM + 10) ///< Invalid Flags
-#define NRF_ERROR_INVALID_DATA                (NRF_ERROR_BASE_NUM + 11) ///< Invalid Data
-#define NRF_ERROR_DATA_SIZE                   (NRF_ERROR_BASE_NUM + 12) ///< Invalid Data size
-#define NRF_ERROR_TIMEOUT                     (NRF_ERROR_BASE_NUM + 13) ///< Operation timed out
-#define NRF_ERROR_NULL                        (NRF_ERROR_BASE_NUM + 14) ///< Null Pointer
-#define NRF_ERROR_FORBIDDEN                   (NRF_ERROR_BASE_NUM + 15) ///< Forbidden Operation
-#define NRF_ERROR_INVALID_ADDR                (NRF_ERROR_BASE_NUM + 16) ///< Bad Memory Address
-#define NRF_ERROR_BUSY                        (NRF_ERROR_BASE_NUM + 17) ///< Busy
-#define NRF_ERROR_CONN_COUNT                  (NRF_ERROR_BASE_NUM + 18) ///< Maximum connection count exceeded.
-#define NRF_ERROR_RESOURCES                   (NRF_ERROR_BASE_NUM + 19) ///< Not enough resources for operation
-
-#ifdef __cplusplus
-}
-#endif
-#endif // NRF_ERROR_H__
-
-/**
-  @}
-*/
diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_error_sdm.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_error_sdm.h
deleted file mode 100755
index 530959b9..00000000
--- a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_error_sdm.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright (c) 2012 - 2017, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- *    list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form, except as embedded into a Nordic
- *    Semiconductor ASA integrated circuit in a product or a software update for
- *    such product, must reproduce the above copyright notice, this list of
- *    conditions and the following disclaimer in the documentation and/or other
- *    materials provided with the distribution.
- *
- * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
- *    contributors may be used to endorse or promote products derived from this
- *    software without specific prior written permission.
- *
- * 4. This software, with or without modification, must only be used with a
- *    Nordic Semiconductor ASA integrated circuit.
- *
- * 5. Any software provided in binary form under this license must not be reverse
- *    engineered, decompiled, modified and/or disassembled.
- *
- * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
- /**
-  @addtogroup nrf_sdm_api
-  @{
-  @defgroup nrf_sdm_error SoftDevice Manager Error Codes
-  @{
-
-  @brief Error definitions for the SDM API
-*/
-
-/* Header guard */
-#ifndef NRF_ERROR_SDM_H__
-#define NRF_ERROR_SDM_H__
-
-#include "nrf_error.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NRF_ERROR_SDM_LFCLK_SOURCE_UNKNOWN              (NRF_ERROR_SDM_BASE_NUM + 0)  ///< Unknown LFCLK source.
-#define NRF_ERROR_SDM_INCORRECT_INTERRUPT_CONFIGURATION (NRF_ERROR_SDM_BASE_NUM + 1)  ///< Incorrect interrupt configuration (can be caused by using illegal priority levels, or having enabled SoftDevice interrupts).
-#define NRF_ERROR_SDM_INCORRECT_CLENR0                  (NRF_ERROR_SDM_BASE_NUM + 2)  ///< Incorrect CLENR0 (can be caused by erroneous SoftDevice flashing).
-
-#ifdef __cplusplus
-}
-#endif
-#endif // NRF_ERROR_SDM_H__
-
-/**
-  @}
-  @}
-*/
diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_error_soc.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_error_soc.h
deleted file mode 100755
index 1e784b8d..00000000
--- a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_error_soc.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright (c) 2012 - 2017, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- *    list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form, except as embedded into a Nordic
- *    Semiconductor ASA integrated circuit in a product or a software update for
- *    such product, must reproduce the above copyright notice, this list of
- *    conditions and the following disclaimer in the documentation and/or other
- *    materials provided with the distribution.
- *
- * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
- *    contributors may be used to endorse or promote products derived from this
- *    software without specific prior written permission.
- *
- * 4. This software, with or without modification, must only be used with a
- *    Nordic Semiconductor ASA integrated circuit.
- *
- * 5. Any software provided in binary form under this license must not be reverse
- *    engineered, decompiled, modified and/or disassembled.
- *
- * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
-  @addtogroup nrf_soc_api
-  @{
-  @defgroup nrf_soc_error SoC Library Error Codes
-  @{
-
-  @brief Error definitions for the SoC library
-
-*/
-
-/* Header guard */
-#ifndef NRF_ERROR_SOC_H__
-#define NRF_ERROR_SOC_H__
-
-#include "nrf_error.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Mutex Errors */
-#define NRF_ERROR_SOC_MUTEX_ALREADY_TAKEN                 (NRF_ERROR_SOC_BASE_NUM + 0)  ///< Mutex already taken
-
-/* NVIC errors */
-#define NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE        (NRF_ERROR_SOC_BASE_NUM + 1)  ///< NVIC interrupt not available
-#define NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED (NRF_ERROR_SOC_BASE_NUM + 2)  ///< NVIC interrupt priority not allowed
-#define NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN              (NRF_ERROR_SOC_BASE_NUM + 3)  ///< NVIC should not return
-
-/* Power errors */
-#define NRF_ERROR_SOC_POWER_MODE_UNKNOWN                  (NRF_ERROR_SOC_BASE_NUM + 4)  ///< Power mode unknown
-#define NRF_ERROR_SOC_POWER_POF_THRESHOLD_UNKNOWN         (NRF_ERROR_SOC_BASE_NUM + 5)  ///< Power POF threshold unknown
-#define NRF_ERROR_SOC_POWER_OFF_SHOULD_NOT_RETURN         (NRF_ERROR_SOC_BASE_NUM + 6)  ///< Power off should not return
-
-/* Rand errors */
-#define NRF_ERROR_SOC_RAND_NOT_ENOUGH_VALUES              (NRF_ERROR_SOC_BASE_NUM + 7)  ///< RAND not enough values
-
-/* PPI errors */
-#define NRF_ERROR_SOC_PPI_INVALID_CHANNEL                 (NRF_ERROR_SOC_BASE_NUM + 8)  ///< Invalid PPI Channel
-#define NRF_ERROR_SOC_PPI_INVALID_GROUP                   (NRF_ERROR_SOC_BASE_NUM + 9)  ///< Invalid PPI Group
-
-#ifdef __cplusplus
-}
-#endif
-#endif // NRF_ERROR_SOC_H__
-/**
-  @}
-  @}
-*/
diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_nvic.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_nvic.h
deleted file mode 100755
index 1f79cc3c..00000000
--- a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_nvic.h
+++ /dev/null
@@ -1,491 +0,0 @@
-/*
- * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- *    list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form, except as embedded into a Nordic
- *    Semiconductor ASA integrated circuit in a product or a software update for
- *    such product, must reproduce the above copyright notice, this list of
- *    conditions and the following disclaimer in the documentation and/or other
- *    materials provided with the distribution.
- *
- * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
- *    contributors may be used to endorse or promote products derived from this
- *    software without specific prior written permission.
- *
- * 4. This software, with or without modification, must only be used with a
- *    Nordic Semiconductor ASA integrated circuit.
- *
- * 5. Any software provided in binary form under this license must not be reverse
- *    engineered, decompiled, modified and/or disassembled.
- *
- * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
- * @defgroup nrf_nvic_api SoftDevice NVIC API
- * @{
- *
- * @note In order to use this module, the following code has to be added to a .c file:
- *     \code
- *     nrf_nvic_state_t nrf_nvic_state = {0};
- *     \endcode
- *
- * @note Definitions and declarations starting with __ (double underscore) in this header file are
- * not intended for direct use by the application.
- *
- * @brief APIs for the accessing NVIC when using a SoftDevice.
- *
- */
-
-#ifndef NRF_NVIC_H__
-#define NRF_NVIC_H__
-
-#include <stdint.h>
-#include "nrf.h"
-#include "nrf_svc.h"
-#include "nrf_error.h"
-#include "nrf_error_soc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**@addtogroup NRF_NVIC_DEFINES Defines
- * @{ */
-
-/**@defgroup NRF_NVIC_ISER_DEFINES SoftDevice NVIC internal definitions
- * @{ */
-
-#define __NRF_NVIC_NVMC_IRQn (30) /**< The peripheral ID of the NVMC. IRQ numbers are used to identify peripherals, but the NVMC doesn't have an IRQ number in the MDK. */
-
-#define __NRF_NVIC_ISER_COUNT (2) /**< The number of ISER/ICER registers in the NVIC that are used. */
-
-/**@brief Interrupt priority levels used by the SoftDevice. */
-#define __NRF_NVIC_SD_IRQ_PRIOS ((uint8_t)( \
-      (1U << 0)  /**< Priority level high .*/   \
-    | (1U << 1)  /**< Priority level medium. */ \
-    | (1U << 4)  /**< Priority level low. */    \
-  ))
-
-/**@brief Interrupt priority levels available to the application. */
-#define __NRF_NVIC_APP_IRQ_PRIOS ((uint8_t)~__NRF_NVIC_SD_IRQ_PRIOS)
-
-/**@brief Interrupts used by the SoftDevice, with IRQn in the range 0-31. */
-#define __NRF_NVIC_SD_IRQS_0 ((uint32_t)( \
-      (1U << POWER_CLOCK_IRQn) \
-    | (1U << RADIO_IRQn) \
-    | (1U << RTC0_IRQn) \
-    | (1U << TIMER0_IRQn) \
-    | (1U << RNG_IRQn) \
-    | (1U << ECB_IRQn) \
-    | (1U << CCM_AAR_IRQn) \
-    | (1U << TEMP_IRQn) \
-    | (1U << __NRF_NVIC_NVMC_IRQn) \
-    | (1U << (uint32_t)SWI5_IRQn) \
-  ))
-
-/**@brief Interrupts used by the SoftDevice, with IRQn in the range 32-63. */
-#define __NRF_NVIC_SD_IRQS_1 ((uint32_t)0)
-
-/**@brief Interrupts available for to application, with IRQn in the range 0-31. */
-#define __NRF_NVIC_APP_IRQS_0 (~__NRF_NVIC_SD_IRQS_0)
-
-/**@brief Interrupts available for to application, with IRQn in the range 32-63. */
-#define __NRF_NVIC_APP_IRQS_1 (~__NRF_NVIC_SD_IRQS_1)
-
-/**@} */
-
-/**@} */
-
-/**@addtogroup NRF_NVIC_VARIABLES Variables
- * @{ */
-
-/**@brief Type representing the state struct for the SoftDevice NVIC module. */
-typedef struct
-{
-  uint32_t volatile __irq_masks[__NRF_NVIC_ISER_COUNT]; /**< IRQs enabled by the application in the NVIC. */
-  uint32_t volatile __cr_flag;                          /**< Non-zero if already in a critical region */
-} nrf_nvic_state_t;
-
-/**@brief Variable keeping the state for the SoftDevice NVIC module. This must be declared in an
- * application source file. */
-extern nrf_nvic_state_t nrf_nvic_state;
-
-/**@} */
-
-/**@addtogroup NRF_NVIC_INTERNAL_FUNCTIONS SoftDevice NVIC internal functions
- * @{ */
-
-/**@brief Disables IRQ interrupts globally, including the SoftDevice's interrupts.
- *
- * @retval  The value of PRIMASK prior to disabling the interrupts.
- */
-__STATIC_INLINE int __sd_nvic_irq_disable(void);
-
-/**@brief Enables IRQ interrupts globally, including the SoftDevice's interrupts.
- */
-__STATIC_INLINE void __sd_nvic_irq_enable(void);
-
-/**@brief Checks if IRQn is available to application
- * @param[in]  IRQn  IRQ to check
- *
- * @retval  1 (true) if the IRQ to check is available to the application
- */
-__STATIC_INLINE uint32_t __sd_nvic_app_accessible_irq(IRQn_Type IRQn);
-
-/**@brief Checks if priority is available to application
- * @param[in]  priority  priority to check
- *
- * @retval  1 (true) if the priority to check is available to the application
- */
-__STATIC_INLINE uint32_t __sd_nvic_is_app_accessible_priority(uint32_t priority);
-
-/**@} */
-
-/**@addtogroup NRF_NVIC_FUNCTIONS SoftDevice NVIC public functions
- * @{ */
-
-/**@brief Enable External Interrupt.
- * @note Corresponds to NVIC_EnableIRQ in CMSIS.
- *
- * @pre IRQn is valid and not reserved by the stack.
- *
- * @param[in] IRQn See the NVIC_EnableIRQ documentation in CMSIS.
- *
- * @retval ::NRF_SUCCESS The interrupt was enabled.
- * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE The interrupt is not available for the application.
- * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED The interrupt has a priority not available for the application.
- */
-__STATIC_INLINE uint32_t sd_nvic_EnableIRQ(IRQn_Type IRQn);
-
-/**@brief  Disable External Interrupt.
- * @note Corresponds to NVIC_DisableIRQ in CMSIS.
- *
- * @pre IRQn is valid and not reserved by the stack.
- *
- * @param[in] IRQn See the NVIC_DisableIRQ documentation in CMSIS.
- *
- * @retval ::NRF_SUCCESS The interrupt was disabled.
- * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE The interrupt is not available for the application.
- */
-__STATIC_INLINE uint32_t sd_nvic_DisableIRQ(IRQn_Type IRQn);
-
-/**@brief  Get Pending Interrupt.
- * @note Corresponds to NVIC_GetPendingIRQ in CMSIS.
- *
- * @pre IRQn is valid and not reserved by the stack.
- *
- * @param[in]   IRQn          See the NVIC_GetPendingIRQ documentation in CMSIS.
- * @param[out]  p_pending_irq Return value from NVIC_GetPendingIRQ.
- *
- * @retval ::NRF_SUCCESS The interrupt is available for the application.
- * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application.
- */
-__STATIC_INLINE uint32_t sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t * p_pending_irq);
-
-/**@brief  Set Pending Interrupt.
- * @note Corresponds to NVIC_SetPendingIRQ in CMSIS.
- *
- * @pre IRQn is valid and not reserved by the stack.
- *
- * @param[in] IRQn See the NVIC_SetPendingIRQ documentation in CMSIS.
- *
- * @retval ::NRF_SUCCESS The interrupt is set pending.
- * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application.
- */
-__STATIC_INLINE uint32_t sd_nvic_SetPendingIRQ(IRQn_Type IRQn);
-
-/**@brief  Clear Pending Interrupt.
- * @note Corresponds to NVIC_ClearPendingIRQ in CMSIS.
- *
- * @pre IRQn is valid and not reserved by the stack.
- *
- * @param[in] IRQn See the NVIC_ClearPendingIRQ documentation in CMSIS.
- *
- * @retval ::NRF_SUCCESS The interrupt pending flag is cleared.
- * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application.
- */
-__STATIC_INLINE uint32_t sd_nvic_ClearPendingIRQ(IRQn_Type IRQn);
-
-/**@brief Set Interrupt Priority.
- * @note Corresponds to NVIC_SetPriority in CMSIS.
- *
- * @pre IRQn is valid and not reserved by the stack.
- * @pre Priority is valid and not reserved by the stack.
- *
- * @param[in] IRQn      See the NVIC_SetPriority documentation in CMSIS.
- * @param[in] priority  A valid IRQ priority for use by the application.
- *
- * @retval ::NRF_SUCCESS The interrupt and priority level is available for the application.
- * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application.
- * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED The interrupt priority is not available for the application.
- */
-__STATIC_INLINE uint32_t sd_nvic_SetPriority(IRQn_Type IRQn, uint32_t priority);
-
-/**@brief Get Interrupt Priority.
- * @note Corresponds to NVIC_GetPriority in CMSIS.
- *
- * @pre IRQn is valid and not reserved by the stack.
- *
- * @param[in]  IRQn         See the NVIC_GetPriority documentation in CMSIS.
- * @param[out] p_priority   Return value from NVIC_GetPriority.
- *
- * @retval ::NRF_SUCCESS The interrupt priority is returned in p_priority.
- * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE - IRQn is not available for the application.
- */
-__STATIC_INLINE uint32_t sd_nvic_GetPriority(IRQn_Type IRQn, uint32_t * p_priority);
-
-/**@brief System Reset.
- * @note Corresponds to NVIC_SystemReset in CMSIS.
- *
- * @retval ::NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN
- */
-__STATIC_INLINE uint32_t sd_nvic_SystemReset(void);
-
-/**@brief Enter critical region.
- *
- * @post Application interrupts will be disabled.
- * @note sd_nvic_critical_region_enter() and ::sd_nvic_critical_region_exit() must be called in matching pairs inside each
- * execution context
- * @sa sd_nvic_critical_region_exit
- *
- * @param[out] p_is_nested_critical_region If 1, the application is now in a nested critical region.
- *
- * @retval ::NRF_SUCCESS
- */
-__STATIC_INLINE uint32_t sd_nvic_critical_region_enter(uint8_t * p_is_nested_critical_region);
-
-/**@brief Exit critical region.
- *
- * @pre Application has entered a critical region using ::sd_nvic_critical_region_enter.
- * @post If not in a nested critical region, the application interrupts will restored to the state before ::sd_nvic_critical_region_enter was called.
- *
- * @param[in] is_nested_critical_region If this is set to 1, the critical region won't be exited. @sa sd_nvic_critical_region_enter.
- *
- * @retval ::NRF_SUCCESS
- */
-__STATIC_INLINE uint32_t sd_nvic_critical_region_exit(uint8_t is_nested_critical_region);
-
-/**@} */
-
-#ifndef SUPPRESS_INLINE_IMPLEMENTATION
-
-__STATIC_INLINE int __sd_nvic_irq_disable(void)
-{
-  int pm = __get_PRIMASK();
-  __disable_irq();
-  return pm;
-}
-
-__STATIC_INLINE void __sd_nvic_irq_enable(void)
-{
-  __enable_irq();
-}
-
-__STATIC_INLINE uint32_t __sd_nvic_app_accessible_irq(IRQn_Type IRQn)
-{
-  if (IRQn < 32)
-  {
-    return ((1UL<<IRQn) & __NRF_NVIC_APP_IRQS_0) != 0;
-  }
-  else if (IRQn < 64)
-  {
-    return ((1UL<<(IRQn-32)) & __NRF_NVIC_APP_IRQS_1) != 0;
-  }
-  else
-  {
-    return 1;
-  }
-}
-
-__STATIC_INLINE uint32_t __sd_nvic_is_app_accessible_priority(uint32_t priority)
-{
-  if( (priority >= (1 << __NVIC_PRIO_BITS))
-   || (((1 << priority) & __NRF_NVIC_APP_IRQ_PRIOS) == 0)
-    )
-  {
-    return 0;
-  }
-  return 1;
-}
-
-
-__STATIC_INLINE uint32_t sd_nvic_EnableIRQ(IRQn_Type IRQn)
-{
-  if (!__sd_nvic_app_accessible_irq(IRQn))
-  {
-    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
-  }
-  if (!__sd_nvic_is_app_accessible_priority(NVIC_GetPriority(IRQn)))
-  {
-    return NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED;
-  }
-
-  if (nrf_nvic_state.__cr_flag)
-  {
-    nrf_nvic_state.__irq_masks[(uint32_t)((int32_t)IRQn) >> 5] |= (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F));
-  }
-  else
-  {
-    NVIC_EnableIRQ(IRQn);
-  }
-  return NRF_SUCCESS;
-}
-
-__STATIC_INLINE uint32_t sd_nvic_DisableIRQ(IRQn_Type IRQn)
-{
-  if (!__sd_nvic_app_accessible_irq(IRQn))
-  {
-    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
-  }
-
-  if (nrf_nvic_state.__cr_flag)
-  {
-    nrf_nvic_state.__irq_masks[(uint32_t)((int32_t)IRQn) >> 5] &= ~(1UL << ((uint32_t)(IRQn) & 0x1F));
-  }
-  else
-  {
-    NVIC_DisableIRQ(IRQn);
-  }
-
-  return NRF_SUCCESS;
-}
-
-__STATIC_INLINE uint32_t sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t * p_pending_irq)
-{
-  if (__sd_nvic_app_accessible_irq(IRQn))
-  {
-    *p_pending_irq = NVIC_GetPendingIRQ(IRQn);
-    return NRF_SUCCESS;
-  }
-  else
-  {
-    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
-  }
-}
-
-__STATIC_INLINE uint32_t sd_nvic_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if (__sd_nvic_app_accessible_irq(IRQn))
-  {
-    NVIC_SetPendingIRQ(IRQn);
-    return NRF_SUCCESS;
-  }
-  else
-  {
-    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
-  }
-}
-
-__STATIC_INLINE uint32_t sd_nvic_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if (__sd_nvic_app_accessible_irq(IRQn))
-  {
-    NVIC_ClearPendingIRQ(IRQn);
-    return NRF_SUCCESS;
-  }
-  else
-  {
-    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
-  }
-}
-
-__STATIC_INLINE uint32_t sd_nvic_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if (!__sd_nvic_app_accessible_irq(IRQn))
-  {
-    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
-  }
-
-  if (!__sd_nvic_is_app_accessible_priority(priority))
-  {
-    return NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED;
-  }
-
-  NVIC_SetPriority(IRQn, (uint32_t)priority);
-  return NRF_SUCCESS;
-}
-
-__STATIC_INLINE uint32_t sd_nvic_GetPriority(IRQn_Type IRQn, uint32_t * p_priority)
-{
-  if (__sd_nvic_app_accessible_irq(IRQn))
-  {
-    *p_priority = (NVIC_GetPriority(IRQn) & 0xFF);
-    return NRF_SUCCESS;
-  }
-  else
-  {
-    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
-  }
-}
-
-__STATIC_INLINE uint32_t sd_nvic_SystemReset(void)
-{
-  NVIC_SystemReset();
-  return NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN;
-}
-
-__STATIC_INLINE uint32_t sd_nvic_critical_region_enter(uint8_t * p_is_nested_critical_region)
-{
-  int was_masked = __sd_nvic_irq_disable();
-  if (!nrf_nvic_state.__cr_flag)
-  {
-    nrf_nvic_state.__cr_flag = 1;
-    nrf_nvic_state.__irq_masks[0] = ( NVIC->ICER[0] & __NRF_NVIC_APP_IRQS_0 );
-    NVIC->ICER[0] = __NRF_NVIC_APP_IRQS_0;
-    nrf_nvic_state.__irq_masks[1] = ( NVIC->ICER[1] & __NRF_NVIC_APP_IRQS_1 );
-    NVIC->ICER[1] = __NRF_NVIC_APP_IRQS_1;
-    *p_is_nested_critical_region = 0;
-  }
-  else
-  {
-    *p_is_nested_critical_region = 1;
-  }
-  if (!was_masked)
-  {
-    __sd_nvic_irq_enable();
-  }
-  return NRF_SUCCESS;
-}
-
-__STATIC_INLINE uint32_t sd_nvic_critical_region_exit(uint8_t is_nested_critical_region)
-{
-  if (nrf_nvic_state.__cr_flag && (is_nested_critical_region == 0))
-  {
-    int was_masked = __sd_nvic_irq_disable();
-    NVIC->ISER[0] = nrf_nvic_state.__irq_masks[0];
-    NVIC->ISER[1] = nrf_nvic_state.__irq_masks[1];
-    nrf_nvic_state.__cr_flag = 0;
-    if (!was_masked)
-    {
-      __sd_nvic_irq_enable();
-    }
-  }
-
-  return NRF_SUCCESS;
-}
-
-#endif /* SUPPRESS_INLINE_IMPLEMENTATION */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // NRF_NVIC_H__
-
-/**@} */
diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_sdm.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_sdm.h
deleted file mode 100755
index 5dfbb287..00000000
--- a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_sdm.h
+++ /dev/null
@@ -1,367 +0,0 @@
-/*
- * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- *    list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form, except as embedded into a Nordic
- *    Semiconductor ASA integrated circuit in a product or a software update for
- *    such product, must reproduce the above copyright notice, this list of
- *    conditions and the following disclaimer in the documentation and/or other
- *    materials provided with the distribution.
- *
- * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
- *    contributors may be used to endorse or promote products derived from this
- *    software without specific prior written permission.
- *
- * 4. This software, with or without modification, must only be used with a
- *    Nordic Semiconductor ASA integrated circuit.
- *
- * 5. Any software provided in binary form under this license must not be reverse
- *    engineered, decompiled, modified and/or disassembled.
- *
- * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
-  @defgroup nrf_sdm_api SoftDevice Manager API
-  @{
-
-  @brief APIs for SoftDevice management.
-
-*/
-
-#ifndef NRF_SDM_H__
-#define NRF_SDM_H__
-
-#include <stdint.h>
-#include "nrf.h"
-#include "nrf_svc.h"
-#include "nrf_error.h"
-#include "nrf_error_sdm.h"
-#include "nrf_soc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @addtogroup NRF_SDM_DEFINES Defines
- * @{ */
-#ifdef NRFSOC_DOXYGEN
-/// Declared in nrf_mbr.h
-#define MBR_SIZE 0
-#warning test
-#endif
-
-/** @brief The major version for the SoftDevice binary distributed with this header file. */
-#define SD_MAJOR_VERSION  (6)
-
-/** @brief The minor version for the SoftDevice binary distributed with this header file. */
-#define SD_MINOR_VERSION  (1)
-
-/** @brief The bugfix version for the SoftDevice binary distributed with this header file. */
-#define SD_BUGFIX_VERSION (1)
-
-/** @brief The SoftDevice variant of this firmware. */
-#define SD_VARIANT_ID 140
-
-/** @brief The full version number for the SoftDevice binary this header file was distributed
- *         with, as a decimal number in the form Mmmmbbb, where:
- *           - M is major version (one or more digits)
- *           - mmm is minor version (three digits)
- *           - bbb is bugfix version (three digits). */
-#define SD_VERSION (SD_MAJOR_VERSION * 1000000 + SD_MINOR_VERSION * 1000 + SD_BUGFIX_VERSION)
-
-/** @brief SoftDevice Manager SVC Base number. */
-#define SDM_SVC_BASE 0x10
-
-/** @brief SoftDevice unique string size in bytes. */
-#define SD_UNIQUE_STR_SIZE 20
-
-/** @brief Invalid info field. Returned when an info field does not exist. */
-#define SDM_INFO_FIELD_INVALID (0)
-
-/** @brief Defines the SoftDevice Information Structure location (address) as an offset from
-the start of the SoftDevice (without MBR)*/
-#define SOFTDEVICE_INFO_STRUCT_OFFSET (0x2000)
-
-/** @brief Defines the absolute SoftDevice Information Structure location (address) when the
- *         SoftDevice is installed just above the MBR (the usual case). */
-#define SOFTDEVICE_INFO_STRUCT_ADDRESS (SOFTDEVICE_INFO_STRUCT_OFFSET + MBR_SIZE)
-
-/** @brief Defines the offset for the SoftDevice Information Structure size value relative to the
- *         SoftDevice base address. The size value is of type uint8_t. */
-#define SD_INFO_STRUCT_SIZE_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET)
-
-/** @brief Defines the offset for the SoftDevice size value relative to the SoftDevice base address.
- *         The size value is of type uint32_t. */
-#define SD_SIZE_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x08)
-
-/** @brief Defines the offset for FWID value relative to the SoftDevice base address. The FWID value
- *         is of type uint16_t.  */
-#define SD_FWID_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x0C)
-
-/** @brief Defines the offset for the SoftDevice ID relative to the SoftDevice base address. The ID
- *         is of type uint32_t. */
-#define SD_ID_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x10)
-
-/** @brief Defines the offset for the SoftDevice version relative to the SoftDevice base address in
- *         the same format as @ref SD_VERSION, stored as an uint32_t. */
-#define SD_VERSION_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x14)
-
-/** @brief Defines the offset for the SoftDevice unique string relative to the SoftDevice base address.
- *         The SD_UNIQUE_STR is stored as an array of uint8_t. The size of array is @ref SD_UNIQUE_STR_SIZE.
- */
-#define SD_UNIQUE_STR_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x18)
-
-/** @brief Defines a macro for retrieving the actual SoftDevice Information Structure size value
- *         from a given base address. Use @ref MBR_SIZE as the argument when the SoftDevice is
- *         installed just above the MBR (the usual case). */
-#define SD_INFO_STRUCT_SIZE_GET(baseaddr) (*((uint8_t *) ((baseaddr) + SD_INFO_STRUCT_SIZE_OFFSET)))
-
-/** @brief Defines a macro for retrieving the actual SoftDevice size value from a given base
- *         address. Use @ref MBR_SIZE as the argument when the SoftDevice is installed just above
- *         the MBR (the usual case). */
-#define SD_SIZE_GET(baseaddr) (*((uint32_t *) ((baseaddr) + SD_SIZE_OFFSET)))
-
-/** @brief Defines the amount of flash that is used by the SoftDevice.
- *         Add @ref MBR_SIZE to find the first available flash address when the SoftDevice is installed
- *         just above the MBR (the usual case).
- */
-#define SD_FLASH_SIZE 0x25000
-
-/** @brief Defines a macro for retrieving the actual FWID value from a given base address. Use
- *         @ref MBR_SIZE as the argument when the SoftDevice is installed just above the MBR (the usual
- *         case). */
-#define SD_FWID_GET(baseaddr) (*((uint16_t *) ((baseaddr) + SD_FWID_OFFSET)))
-
-/** @brief Defines a macro for retrieving the actual SoftDevice ID from a given base address. Use
- *         @ref MBR_SIZE as the argument when the SoftDevice is installed just above the MBR (the
- *         usual case). */
-#define SD_ID_GET(baseaddr) ((SD_INFO_STRUCT_SIZE_GET(baseaddr) > (SD_ID_OFFSET - SOFTDEVICE_INFO_STRUCT_OFFSET)) \
-        ? (*((uint32_t *) ((baseaddr) + SD_ID_OFFSET))) : SDM_INFO_FIELD_INVALID)
-
-/** @brief Defines a macro for retrieving the actual SoftDevice version from a given base address.
- *         Use @ref MBR_SIZE as the argument when the SoftDevice is installed just above the MBR
- *         (the usual case). */
-#define SD_VERSION_GET(baseaddr) ((SD_INFO_STRUCT_SIZE_GET(baseaddr) > (SD_VERSION_OFFSET - SOFTDEVICE_INFO_STRUCT_OFFSET)) \
-        ? (*((uint32_t *) ((baseaddr) + SD_VERSION_OFFSET))) : SDM_INFO_FIELD_INVALID)
-
-/** @brief Defines a macro for retrieving the address of SoftDevice unique str based on a given base address.
- *         Use @ref MBR_SIZE as the argument when the SoftDevice is installed just above the MBR
- *         (the usual case). */
-#define SD_UNIQUE_STR_ADDR_GET(baseaddr) ((SD_INFO_STRUCT_SIZE_GET(baseaddr) > (SD_UNIQUE_STR_OFFSET - SOFTDEVICE_INFO_STRUCT_OFFSET)) \
-        ? (((uint8_t *) ((baseaddr) + SD_UNIQUE_STR_OFFSET))) : SDM_INFO_FIELD_INVALID)
-
-/**@defgroup NRF_FAULT_ID_RANGES Fault ID ranges
- * @{ */
-#define NRF_FAULT_ID_SD_RANGE_START     0x00000000            /**< SoftDevice ID range start. */
-#define NRF_FAULT_ID_APP_RANGE_START    0x00001000            /**< Application ID range start. */
-/**@} */
-
-/**@defgroup NRF_FAULT_IDS Fault ID types
- * @{ */
-#define NRF_FAULT_ID_SD_ASSERT    (NRF_FAULT_ID_SD_RANGE_START  + 1)          /**< SoftDevice assertion. The info parameter is reserved for future used. */
-#define NRF_FAULT_ID_APP_MEMACC   (NRF_FAULT_ID_APP_RANGE_START + 1)          /**< Application invalid memory access. The info parameter will contain 0x00000000,
-                                                                                   in case of SoftDevice RAM access violation. In case of SoftDevice peripheral
-                                                                                   register violation the info parameter will contain the sub-region number of
-                                                                                   PREGION[0], on whose address range the disallowed write access caused the
-                                                                                   memory access fault. */
-/**@} */
-
-/** @} */
-
-/** @addtogroup NRF_SDM_ENUMS Enumerations
- * @{ */
-
-/**@brief nRF SoftDevice Manager API SVC numbers. */
-enum NRF_SD_SVCS
-{
-  SD_SOFTDEVICE_ENABLE = SDM_SVC_BASE, /**< ::sd_softdevice_enable */
-  SD_SOFTDEVICE_DISABLE,               /**< ::sd_softdevice_disable */
-  SD_SOFTDEVICE_IS_ENABLED,            /**< ::sd_softdevice_is_enabled */
-  SD_SOFTDEVICE_VECTOR_TABLE_BASE_SET, /**< ::sd_softdevice_vector_table_base_set */
-  SVC_SDM_LAST                         /**< Placeholder for last SDM SVC */
-};
-
-/** @} */
-
-/** @addtogroup NRF_SDM_DEFINES Defines
- * @{ */
-
-/**@defgroup NRF_CLOCK_LF_ACCURACY Clock accuracy
- * @{ */
-
-#define NRF_CLOCK_LF_ACCURACY_250_PPM (0) /**< Default: 250 ppm */
-#define NRF_CLOCK_LF_ACCURACY_500_PPM (1) /**< 500 ppm */
-#define NRF_CLOCK_LF_ACCURACY_150_PPM (2) /**< 150 ppm */
-#define NRF_CLOCK_LF_ACCURACY_100_PPM (3) /**< 100 ppm */
-#define NRF_CLOCK_LF_ACCURACY_75_PPM  (4) /**< 75 ppm */
-#define NRF_CLOCK_LF_ACCURACY_50_PPM  (5) /**< 50 ppm */
-#define NRF_CLOCK_LF_ACCURACY_30_PPM  (6) /**< 30 ppm */
-#define NRF_CLOCK_LF_ACCURACY_20_PPM  (7) /**< 20 ppm */
-#define NRF_CLOCK_LF_ACCURACY_10_PPM  (8) /**< 10 ppm */
-#define NRF_CLOCK_LF_ACCURACY_5_PPM   (9) /**<  5 ppm */
-#define NRF_CLOCK_LF_ACCURACY_2_PPM  (10) /**<  2 ppm */
-#define NRF_CLOCK_LF_ACCURACY_1_PPM  (11) /**<  1 ppm */
-
-/** @} */
-
-/**@defgroup NRF_CLOCK_LF_SRC Possible LFCLK oscillator sources
- * @{ */
-
-#define NRF_CLOCK_LF_SRC_RC      (0)                        /**< LFCLK RC oscillator. */
-#define NRF_CLOCK_LF_SRC_XTAL    (1)                        /**< LFCLK crystal oscillator. */
-#define NRF_CLOCK_LF_SRC_SYNTH   (2)                        /**< LFCLK Synthesized from HFCLK. */
-
-/** @} */
-
-/** @} */
-
-/** @addtogroup NRF_SDM_TYPES Types
- * @{ */
-
-/**@brief Type representing LFCLK oscillator source. */
-typedef struct
-{
-  uint8_t source;         /**< LF oscillator clock source, see @ref NRF_CLOCK_LF_SRC. */
-  uint8_t rc_ctiv;        /**< Only for ::NRF_CLOCK_LF_SRC_RC: Calibration timer interval in 1/4 second
-                               units (nRF52: 1-32).
-                               @note To avoid excessive clock drift, 0.5 degrees Celsius is the
-                                     maximum temperature change allowed in one calibration timer
-                                     interval. The interval should be selected to ensure this.
-
-                                  @note Must be 0 if source is not ::NRF_CLOCK_LF_SRC_RC.  */
-  uint8_t rc_temp_ctiv;   /**<  Only for ::NRF_CLOCK_LF_SRC_RC: How often (in number of calibration
-                                intervals) the RC oscillator shall be calibrated if the temperature
-                                hasn't changed.
-                                     0: Always calibrate even if the temperature hasn't changed.
-                                     1: Only calibrate if the temperature has changed (legacy - nRF51 only).
-                                     2-33: Check the temperature and only calibrate if it has changed,
-                                           however calibration will take place every rc_temp_ctiv
-                                           intervals in any case.
-
-                                @note Must be 0 if source is not ::NRF_CLOCK_LF_SRC_RC.
-
-                                @note For nRF52, the application must ensure calibration at least once
-                                      every 8 seconds to ensure +/-500 ppm clock stability. The
-                                      recommended configuration for ::NRF_CLOCK_LF_SRC_RC on nRF52 is
-                                      rc_ctiv=16 and rc_temp_ctiv=2. This will ensure calibration at
-                                      least once every 8 seconds and for temperature changes of 0.5
-                                      degrees Celsius every 4 seconds. See the Product Specification
-                                      for the nRF52 device being used for more information.*/
-  uint8_t accuracy;       /**< External clock accuracy used in the LL to compute timing
-                               windows, see @ref NRF_CLOCK_LF_ACCURACY.*/
-} nrf_clock_lf_cfg_t;
-
-/**@brief Fault Handler type.
- *
- * When certain unrecoverable errors occur within the application or SoftDevice the fault handler will be called back.
- * The protocol stack will be in an undefined state when this happens and the only way to recover will be to
- * perform a reset, using e.g. CMSIS NVIC_SystemReset().
- * If the application returns from the fault handler the SoftDevice will call NVIC_SystemReset().
- *
- * @note This callback is executed in HardFault context, thus SVC functions cannot be called from the fault callback.
- *
- * @param[in] id Fault identifier. See @ref NRF_FAULT_IDS.
- * @param[in] pc The program counter of the instruction that triggered the fault.
- * @param[in] info Optional additional information regarding the fault. Refer to each Fault identifier for details.
- *
- * @note When id is set to @ref NRF_FAULT_ID_APP_MEMACC, pc will contain the address of the instruction being executed at the time when
- * the fault is detected by the CPU. The CPU program counter may have advanced up to 2 instructions (no branching) after the one that triggered the fault.
- */
-typedef void (*nrf_fault_handler_t)(uint32_t id, uint32_t pc, uint32_t info);
-
-/** @} */
-
-/** @addtogroup NRF_SDM_FUNCTIONS Functions
- * @{ */
-
-/**@brief Enables the SoftDevice and by extension the protocol stack.
- *
- * @note Some care must be taken if a low frequency clock source is already running when calling this function:
- *       If the LF clock has a different source then the one currently running, it will be stopped. Then, the new
- *       clock source will be started.
- *
- * @note This function has no effect when returning with an error.
- *
- * @post If return code is ::NRF_SUCCESS
- *       - SoC library and protocol stack APIs are made available.
- *       - A portion of RAM will be unavailable (see relevant SDS documentation).
- *       - Some peripherals will be unavailable or available only through the SoC API (see relevant SDS documentation).
- *       - Interrupts will not arrive from protected peripherals or interrupts.
- *       - nrf_nvic_ functions must be used instead of CMSIS NVIC_ functions for reliable usage of the SoftDevice.
- *       - Interrupt latency may be affected by the SoftDevice  (see relevant SDS documentation).
- *       - Chosen low frequency clock source will be running.
- *
- * @param p_clock_lf_cfg Low frequency clock source and accuracy.
-                         If NULL the clock will be configured as an RC source with rc_ctiv = 16 and .rc_temp_ctiv = 2
-                         In the case of XTAL source, the PPM accuracy of the chosen clock source must be greater than or equal to the actual characteristics of your XTAL clock.
- * @param fault_handler Callback to be invoked in case of fault, cannot be NULL.
- *
- * @retval ::NRF_SUCCESS
- * @retval ::NRF_ERROR_INVALID_ADDR  Invalid or NULL pointer supplied.
- * @retval ::NRF_ERROR_INVALID_STATE SoftDevice is already enabled, and the clock source and fault handler cannot be updated.
- * @retval ::NRF_ERROR_SDM_INCORRECT_INTERRUPT_CONFIGURATION SoftDevice interrupt is already enabled, or an enabled interrupt has an illegal priority level.
- * @retval ::NRF_ERROR_SDM_LFCLK_SOURCE_UNKNOWN Unknown low frequency clock source selected.
- * @retval ::NRF_ERROR_INVALID_PARAM Invalid clock source configuration supplied in p_clock_lf_cfg.
- */
-SVCALL(SD_SOFTDEVICE_ENABLE, uint32_t, sd_softdevice_enable(nrf_clock_lf_cfg_t const * p_clock_lf_cfg, nrf_fault_handler_t fault_handler));
-
-
-/**@brief Disables the SoftDevice and by extension the protocol stack.
- *
- * Idempotent function to disable the SoftDevice.
- *
- * @post SoC library and protocol stack APIs are made unavailable.
- * @post All interrupts that was protected by the SoftDevice will be disabled and initialized to priority 0 (highest).
- * @post All peripherals used by the SoftDevice will be reset to default values.
- * @post All of RAM become available.
- * @post All interrupts are forwarded to the application.
- * @post LFCLK source chosen in ::sd_softdevice_enable will be left running.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_SOFTDEVICE_DISABLE, uint32_t, sd_softdevice_disable(void));
-
-/**@brief Check if the SoftDevice is enabled.
- *
- * @param[out]  p_softdevice_enabled If the SoftDevice is enabled: 1 else 0.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_SOFTDEVICE_IS_ENABLED, uint32_t, sd_softdevice_is_enabled(uint8_t * p_softdevice_enabled));
-
-/**@brief Sets the base address of the interrupt vector table for interrupts forwarded from the SoftDevice
- *
- * This function is only intended to be called when a bootloader is enabled.
- *
- * @param[in] address The base address of the interrupt vector table for forwarded interrupts.
-
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_SOFTDEVICE_VECTOR_TABLE_BASE_SET, uint32_t, sd_softdevice_vector_table_base_set(uint32_t address));
-
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif
-#endif // NRF_SDM_H__
-
-/**
-  @}
-*/
diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_soc.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_soc.h
deleted file mode 100755
index beb4d3a5..00000000
--- a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_soc.h
+++ /dev/null
@@ -1,1079 +0,0 @@
-/*
- * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- *    list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form, except as embedded into a Nordic
- *    Semiconductor ASA integrated circuit in a product or a software update for
- *    such product, must reproduce the above copyright notice, this list of
- *    conditions and the following disclaimer in the documentation and/or other
- *    materials provided with the distribution.
- *
- * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
- *    contributors may be used to endorse or promote products derived from this
- *    software without specific prior written permission.
- *
- * 4. This software, with or without modification, must only be used with a
- *    Nordic Semiconductor ASA integrated circuit.
- *
- * 5. Any software provided in binary form under this license must not be reverse
- *    engineered, decompiled, modified and/or disassembled.
- *
- * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
- * @defgroup nrf_soc_api SoC Library API
- * @{
- *
- * @brief APIs for the SoC library.
- *
- */
-
-#ifndef NRF_SOC_H__
-#define NRF_SOC_H__
-
-#include <stdint.h>
-#include "nrf.h"
-#include "nrf_svc.h"
-#include "nrf_error.h"
-#include "nrf_error_soc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**@addtogroup NRF_SOC_DEFINES Defines
- * @{ */
-
-/**@brief The number of the lowest SVC number reserved for the SoC library. */
-#define SOC_SVC_BASE               (0x20)                   /**< Base value for SVCs that are available when the SoftDevice is disabled. */
-#define SOC_SVC_BASE_NOT_AVAILABLE (0x2C)                   /**< Base value for SVCs that are not available when the SoftDevice is disabled. */
-
-/**@brief Guaranteed time for application to process radio inactive notification. */
-#define NRF_RADIO_NOTIFICATION_INACTIVE_GUARANTEED_TIME_US  (62)
-
-/**@brief The minimum allowed timeslot extension time. */
-#define NRF_RADIO_MINIMUM_TIMESLOT_LENGTH_EXTENSION_TIME_US (200)
-
-/**@brief The maximum processing time to handle a timeslot extension. */
-#define NRF_RADIO_MAX_EXTENSION_PROCESSING_TIME_US           (17)
-
-/**@brief The latest time before the end of a timeslot the timeslot can be extended. */
-#define NRF_RADIO_MIN_EXTENSION_MARGIN_US                    (79)
-
-#define SOC_ECB_KEY_LENGTH                (16)                       /**< ECB key length. */
-#define SOC_ECB_CLEARTEXT_LENGTH          (16)                       /**< ECB cleartext length. */
-#define SOC_ECB_CIPHERTEXT_LENGTH         (SOC_ECB_CLEARTEXT_LENGTH) /**< ECB ciphertext length. */
-
-#define SD_EVT_IRQn                       (SWI2_IRQn)        /**< SoftDevice Event IRQ number. Used for both protocol events and SoC events. */
-#define SD_EVT_IRQHandler                 (SWI2_IRQHandler)  /**< SoftDevice Event IRQ handler. Used for both protocol events and SoC events.
-                                                                       The default interrupt priority for this handler is set to 6 */
-#define RADIO_NOTIFICATION_IRQn           (SWI1_IRQn)        /**< The radio notification IRQ number. */
-#define RADIO_NOTIFICATION_IRQHandler     (SWI1_IRQHandler)  /**< The radio notification IRQ handler.
-                                                                       The default interrupt priority for this handler is set to 6 */
-#define NRF_RADIO_LENGTH_MIN_US           (100)               /**< The shortest allowed radio timeslot, in microseconds. */
-#define NRF_RADIO_LENGTH_MAX_US           (100000)            /**< The longest allowed radio timeslot, in microseconds. */
-
-#define NRF_RADIO_DISTANCE_MAX_US         (128000000UL - 1UL) /**< The longest timeslot distance, in microseconds, allowed for the distance parameter (see @ref nrf_radio_request_normal_t) in the request. */
-
-#define NRF_RADIO_EARLIEST_TIMEOUT_MAX_US (128000000UL - 1UL) /**< The longest timeout, in microseconds, allowed when requesting the earliest possible timeslot. */
-
-#define NRF_RADIO_START_JITTER_US         (2)                 /**< The maximum jitter in @ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START relative to the requested start time. */
-
-/**@brief Mask of PPI channels reserved by the SoftDevice when the SoftDevice is disabled. */
-#define NRF_SOC_SD_PPI_CHANNELS_SD_DISABLED_MSK ((uint32_t)(0))
-
-/**@brief Mask of PPI channels reserved by the SoftDevice when the SoftDevice is enabled. */
-#define NRF_SOC_SD_PPI_CHANNELS_SD_ENABLED_MSK  ((uint32_t)( \
-      (1U << 17) \
-    | (1U << 18) \
-    | (1U << 19) \
-    | (1U << 20) \
-    | (1U << 21) \
-    | (1U << 22) \
-    | (1U << 23) \
-    | (1U << 24) \
-    | (1U << 25) \
-    | (1U << 26) \
-    | (1U << 27) \
-    | (1U << 28) \
-    | (1U << 29) \
-    | (1U << 30) \
-    | (1U << 31) \
-  ))
-
-/**@brief Mask of PPI channels available to the application when the SoftDevice is disabled. */
-#define NRF_SOC_APP_PPI_CHANNELS_SD_DISABLED_MSK (~NRF_SOC_SD_PPI_CHANNELS_SD_DISABLED_MSK)
-
-/**@brief Mask of PPI channels available to the application when the SoftDevice is enabled. */
-#define NRF_SOC_APP_PPI_CHANNELS_SD_ENABLED_MSK  (~NRF_SOC_SD_PPI_CHANNELS_SD_ENABLED_MSK)
-
-/**@brief Mask of PPI groups reserved by the SoftDevice when the SoftDevice is disabled. */
-#define NRF_SOC_SD_PPI_GROUPS_SD_DISABLED_MSK    ((uint32_t)(0))
-
-/**@brief Mask of PPI groups reserved by the SoftDevice when the SoftDevice is enabled. */
-#define NRF_SOC_SD_PPI_GROUPS_SD_ENABLED_MSK     ((uint32_t)( \
-      (1U << 4) \
-    | (1U << 5) \
-  ))
-
-/**@brief Mask of PPI groups available to the application when the SoftDevice is disabled. */
-#define NRF_SOC_APP_PPI_GROUPS_SD_DISABLED_MSK   (~NRF_SOC_SD_PPI_GROUPS_SD_DISABLED_MSK)
-
-/**@brief Mask of PPI groups available to the application when the SoftDevice is enabled. */
-#define NRF_SOC_APP_PPI_GROUPS_SD_ENABLED_MSK    (~NRF_SOC_SD_PPI_GROUPS_SD_ENABLED_MSK)
-
-/**@} */
-
-/**@addtogroup NRF_SOC_ENUMS Enumerations
- * @{ */
-
-/**@brief The SVC numbers used by the SVC functions in the SoC library. */
-enum NRF_SOC_SVCS
-{
-  SD_PPI_CHANNEL_ENABLE_GET   = SOC_SVC_BASE,
-  SD_PPI_CHANNEL_ENABLE_SET   = SOC_SVC_BASE + 1,
-  SD_PPI_CHANNEL_ENABLE_CLR   = SOC_SVC_BASE + 2,
-  SD_PPI_CHANNEL_ASSIGN       = SOC_SVC_BASE + 3,
-  SD_PPI_GROUP_TASK_ENABLE    = SOC_SVC_BASE + 4,
-  SD_PPI_GROUP_TASK_DISABLE   = SOC_SVC_BASE + 5,
-  SD_PPI_GROUP_ASSIGN         = SOC_SVC_BASE + 6,
-  SD_PPI_GROUP_GET            = SOC_SVC_BASE + 7,
-  SD_FLASH_PAGE_ERASE         = SOC_SVC_BASE + 8,
-  SD_FLASH_WRITE              = SOC_SVC_BASE + 9,
-  SD_PROTECTED_REGISTER_WRITE = SOC_SVC_BASE + 11,
-  SD_MUTEX_NEW                            = SOC_SVC_BASE_NOT_AVAILABLE,
-  SD_MUTEX_ACQUIRE                        = SOC_SVC_BASE_NOT_AVAILABLE + 1,
-  SD_MUTEX_RELEASE                        = SOC_SVC_BASE_NOT_AVAILABLE + 2,
-  SD_RAND_APPLICATION_POOL_CAPACITY_GET   = SOC_SVC_BASE_NOT_AVAILABLE + 3,
-  SD_RAND_APPLICATION_BYTES_AVAILABLE_GET = SOC_SVC_BASE_NOT_AVAILABLE + 4,
-  SD_RAND_APPLICATION_VECTOR_GET          = SOC_SVC_BASE_NOT_AVAILABLE + 5,
-  SD_POWER_MODE_SET                       = SOC_SVC_BASE_NOT_AVAILABLE + 6,
-  SD_POWER_SYSTEM_OFF                     = SOC_SVC_BASE_NOT_AVAILABLE + 7,
-  SD_POWER_RESET_REASON_GET               = SOC_SVC_BASE_NOT_AVAILABLE + 8,
-  SD_POWER_RESET_REASON_CLR               = SOC_SVC_BASE_NOT_AVAILABLE + 9,
-  SD_POWER_POF_ENABLE                     = SOC_SVC_BASE_NOT_AVAILABLE + 10,
-  SD_POWER_POF_THRESHOLD_SET              = SOC_SVC_BASE_NOT_AVAILABLE + 11,
-  SD_POWER_POF_THRESHOLDVDDH_SET          = SOC_SVC_BASE_NOT_AVAILABLE + 12,
-  SD_POWER_RAM_POWER_SET                  = SOC_SVC_BASE_NOT_AVAILABLE + 13,
-  SD_POWER_RAM_POWER_CLR                  = SOC_SVC_BASE_NOT_AVAILABLE + 14,
-  SD_POWER_RAM_POWER_GET                  = SOC_SVC_BASE_NOT_AVAILABLE + 15,
-  SD_POWER_GPREGRET_SET                   = SOC_SVC_BASE_NOT_AVAILABLE + 16,
-  SD_POWER_GPREGRET_CLR                   = SOC_SVC_BASE_NOT_AVAILABLE + 17,
-  SD_POWER_GPREGRET_GET                   = SOC_SVC_BASE_NOT_AVAILABLE + 18,
-  SD_POWER_DCDC_MODE_SET                  = SOC_SVC_BASE_NOT_AVAILABLE + 19,
-  SD_POWER_DCDC0_MODE_SET                 = SOC_SVC_BASE_NOT_AVAILABLE + 20,
-  SD_APP_EVT_WAIT                         = SOC_SVC_BASE_NOT_AVAILABLE + 21,
-  SD_CLOCK_HFCLK_REQUEST                  = SOC_SVC_BASE_NOT_AVAILABLE + 22,
-  SD_CLOCK_HFCLK_RELEASE                  = SOC_SVC_BASE_NOT_AVAILABLE + 23,
-  SD_CLOCK_HFCLK_IS_RUNNING               = SOC_SVC_BASE_NOT_AVAILABLE + 24,
-  SD_RADIO_NOTIFICATION_CFG_SET           = SOC_SVC_BASE_NOT_AVAILABLE + 25,
-  SD_ECB_BLOCK_ENCRYPT                    = SOC_SVC_BASE_NOT_AVAILABLE + 26,
-  SD_ECB_BLOCKS_ENCRYPT                   = SOC_SVC_BASE_NOT_AVAILABLE + 27,
-  SD_RADIO_SESSION_OPEN                   = SOC_SVC_BASE_NOT_AVAILABLE + 28,
-  SD_RADIO_SESSION_CLOSE                  = SOC_SVC_BASE_NOT_AVAILABLE + 29,
-  SD_RADIO_REQUEST                        = SOC_SVC_BASE_NOT_AVAILABLE + 30,
-  SD_EVT_GET                              = SOC_SVC_BASE_NOT_AVAILABLE + 31,
-  SD_TEMP_GET                             = SOC_SVC_BASE_NOT_AVAILABLE + 32,
-  SD_POWER_USBPWRRDY_ENABLE               = SOC_SVC_BASE_NOT_AVAILABLE + 33,
-  SD_POWER_USBDETECTED_ENABLE             = SOC_SVC_BASE_NOT_AVAILABLE + 34,
-  SD_POWER_USBREMOVED_ENABLE              = SOC_SVC_BASE_NOT_AVAILABLE + 35,
-  SD_POWER_USBREGSTATUS_GET               = SOC_SVC_BASE_NOT_AVAILABLE + 36,
-  SVC_SOC_LAST                            = SOC_SVC_BASE_NOT_AVAILABLE + 37
-};
-
-/**@brief Possible values of a ::nrf_mutex_t. */
-enum NRF_MUTEX_VALUES
-{
-  NRF_MUTEX_FREE,
-  NRF_MUTEX_TAKEN
-};
-
-/**@brief Power modes. */
-enum NRF_POWER_MODES
-{
-  NRF_POWER_MODE_CONSTLAT,  /**< Constant latency mode. See power management in the reference manual. */
-  NRF_POWER_MODE_LOWPWR     /**< Low power mode. See power management in the reference manual. */
-};
-
-
-/**@brief Power failure thresholds */
-enum NRF_POWER_THRESHOLDS
-{
-  NRF_POWER_THRESHOLD_V17 = 4UL, /**< 1.7 Volts power failure threshold. */
-  NRF_POWER_THRESHOLD_V18,       /**< 1.8 Volts power failure threshold. */
-  NRF_POWER_THRESHOLD_V19,       /**< 1.9 Volts power failure threshold. */
-  NRF_POWER_THRESHOLD_V20,       /**< 2.0 Volts power failure threshold. */
-  NRF_POWER_THRESHOLD_V21,       /**< 2.1 Volts power failure threshold. */
-  NRF_POWER_THRESHOLD_V22,       /**< 2.2 Volts power failure threshold. */
-  NRF_POWER_THRESHOLD_V23,       /**< 2.3 Volts power failure threshold. */
-  NRF_POWER_THRESHOLD_V24,       /**< 2.4 Volts power failure threshold. */
-  NRF_POWER_THRESHOLD_V25,       /**< 2.5 Volts power failure threshold. */
-  NRF_POWER_THRESHOLD_V26,       /**< 2.6 Volts power failure threshold. */
-  NRF_POWER_THRESHOLD_V27,       /**< 2.7 Volts power failure threshold. */
-  NRF_POWER_THRESHOLD_V28        /**< 2.8 Volts power failure threshold. */
-};
-
-/**@brief Power failure thresholds for high voltage */
-enum NRF_POWER_THRESHOLDVDDHS
-{
-  NRF_POWER_THRESHOLDVDDH_V27,       /**< 2.7 Volts power failure threshold. */
-  NRF_POWER_THRESHOLDVDDH_V28,       /**< 2.8 Volts power failure threshold. */
-  NRF_POWER_THRESHOLDVDDH_V29,       /**< 2.9 Volts power failure threshold. */
-  NRF_POWER_THRESHOLDVDDH_V30,       /**< 3.0 Volts power failure threshold. */
-  NRF_POWER_THRESHOLDVDDH_V31,       /**< 3.1 Volts power failure threshold. */
-  NRF_POWER_THRESHOLDVDDH_V32,       /**< 3.2 Volts power failure threshold. */
-  NRF_POWER_THRESHOLDVDDH_V33,       /**< 3.3 Volts power failure threshold. */
-  NRF_POWER_THRESHOLDVDDH_V34,       /**< 3.4 Volts power failure threshold. */
-  NRF_POWER_THRESHOLDVDDH_V35,       /**< 3.5 Volts power failure threshold. */
-  NRF_POWER_THRESHOLDVDDH_V36,       /**< 3.6 Volts power failure threshold. */
-  NRF_POWER_THRESHOLDVDDH_V37,       /**< 3.7 Volts power failure threshold. */
-  NRF_POWER_THRESHOLDVDDH_V38,       /**< 3.8 Volts power failure threshold. */
-  NRF_POWER_THRESHOLDVDDH_V39,       /**< 3.9 Volts power failure threshold. */
-  NRF_POWER_THRESHOLDVDDH_V40,       /**< 4.0 Volts power failure threshold. */
-  NRF_POWER_THRESHOLDVDDH_V41,       /**< 4.1 Volts power failure threshold. */
-  NRF_POWER_THRESHOLDVDDH_V42        /**< 4.2 Volts power failure threshold. */
-};
-
-
-/**@brief DC/DC converter modes. */
-enum NRF_POWER_DCDC_MODES
-{
-  NRF_POWER_DCDC_DISABLE,          /**< The DCDC is disabled. */
-  NRF_POWER_DCDC_ENABLE            /**< The DCDC is enabled.  */
-};
-
-/**@brief Radio notification distances. */
-enum NRF_RADIO_NOTIFICATION_DISTANCES
-{
-  NRF_RADIO_NOTIFICATION_DISTANCE_NONE = 0, /**< The event does not have a notification. */
-  NRF_RADIO_NOTIFICATION_DISTANCE_800US,    /**< The distance from the active notification to start of radio activity. */
-  NRF_RADIO_NOTIFICATION_DISTANCE_1740US,   /**< The distance from the active notification to start of radio activity. */
-  NRF_RADIO_NOTIFICATION_DISTANCE_2680US,   /**< The distance from the active notification to start of radio activity. */
-  NRF_RADIO_NOTIFICATION_DISTANCE_3620US,   /**< The distance from the active notification to start of radio activity. */
-  NRF_RADIO_NOTIFICATION_DISTANCE_4560US,   /**< The distance from the active notification to start of radio activity. */
-  NRF_RADIO_NOTIFICATION_DISTANCE_5500US    /**< The distance from the active notification to start of radio activity. */
-};
-
-
-/**@brief Radio notification types. */
-enum NRF_RADIO_NOTIFICATION_TYPES
-{
-  NRF_RADIO_NOTIFICATION_TYPE_NONE = 0,        /**< The event does not have a radio notification signal. */
-  NRF_RADIO_NOTIFICATION_TYPE_INT_ON_ACTIVE,   /**< Using interrupt for notification when the radio will be enabled. */
-  NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE, /**< Using interrupt for notification when the radio has been disabled. */
-  NRF_RADIO_NOTIFICATION_TYPE_INT_ON_BOTH,     /**< Using interrupt for notification both when the radio will be enabled and disabled. */
-};
-
-/**@brief The Radio signal callback types. */
-enum NRF_RADIO_CALLBACK_SIGNAL_TYPE
-{
-  NRF_RADIO_CALLBACK_SIGNAL_TYPE_START,             /**< This signal indicates the start of the radio timeslot. */
-  NRF_RADIO_CALLBACK_SIGNAL_TYPE_TIMER0,            /**< This signal indicates the NRF_TIMER0 interrupt. */
-  NRF_RADIO_CALLBACK_SIGNAL_TYPE_RADIO,             /**< This signal indicates the NRF_RADIO interrupt. */
-  NRF_RADIO_CALLBACK_SIGNAL_TYPE_EXTEND_FAILED,     /**< This signal indicates extend action failed. */
-  NRF_RADIO_CALLBACK_SIGNAL_TYPE_EXTEND_SUCCEEDED   /**< This signal indicates extend action succeeded. */
-};
-
-/**@brief The actions requested by the signal callback.
- *
- *  This code gives the SOC instructions about what action to take when the signal callback has
- *  returned.
- */
-enum NRF_RADIO_SIGNAL_CALLBACK_ACTION
-{
-  NRF_RADIO_SIGNAL_CALLBACK_ACTION_NONE,            /**< Return without action. */
-  NRF_RADIO_SIGNAL_CALLBACK_ACTION_EXTEND,          /**< Request an extension of the current
-                                                         timeslot. Maximum execution time for this action:
-                                                         @ref NRF_RADIO_MAX_EXTENSION_PROCESSING_TIME_US.
-                                                         This action must be started at least
-                                                         @ref NRF_RADIO_MIN_EXTENSION_MARGIN_US before
-                                                         the end of the timeslot. */
-  NRF_RADIO_SIGNAL_CALLBACK_ACTION_END,             /**< End the current radio timeslot. */
-  NRF_RADIO_SIGNAL_CALLBACK_ACTION_REQUEST_AND_END  /**< Request a new radio timeslot and end the current timeslot. */
-};
-
-/**@brief Radio timeslot high frequency clock source configuration. */
-enum NRF_RADIO_HFCLK_CFG
-{
-  NRF_RADIO_HFCLK_CFG_XTAL_GUARANTEED, /**< The SoftDevice will guarantee that the high frequency clock source is the
-                                           external crystal for the whole duration of the timeslot. This should be the
-                                           preferred option for events that use the radio or require high timing accuracy.
-                                           @note The SoftDevice will automatically turn on and off the external crystal,
-                                           at the beginning and end of the timeslot, respectively. The crystal may also
-                                           intentionally be left running after the timeslot, in cases where it is needed
-                                           by the SoftDevice shortly after the end of the timeslot. */
-  NRF_RADIO_HFCLK_CFG_NO_GUARANTEE    /**< This configuration allows for earlier and tighter scheduling of timeslots.
-                                           The RC oscillator may be the clock source in part or for the whole duration of the timeslot.
-                                           The RC oscillator's accuracy must therefore be taken into consideration.
-                                           @note If the application will use the radio peripheral in timeslots with this configuration,
-                                           it must make sure that the crystal is running and stable before starting the radio. */
-};
-
-/**@brief Radio timeslot priorities. */
-enum NRF_RADIO_PRIORITY
-{
-  NRF_RADIO_PRIORITY_HIGH,                          /**< High (equal priority as the normal connection priority of the SoftDevice stack(s)). */
-  NRF_RADIO_PRIORITY_NORMAL,                        /**< Normal (equal priority as the priority of secondary activities of the SoftDevice stack(s)). */
-};
-
-/**@brief Radio timeslot request type. */
-enum NRF_RADIO_REQUEST_TYPE
-{
-  NRF_RADIO_REQ_TYPE_EARLIEST,                      /**< Request radio timeslot as early as possible. This should always be used for the first request in a session. */
-  NRF_RADIO_REQ_TYPE_NORMAL                         /**< Normal radio timeslot request. */
-};
-
-/**@brief SoC Events. */
-enum NRF_SOC_EVTS
-{
-  NRF_EVT_HFCLKSTARTED,                         /**< Event indicating that the HFCLK has started. */
-  NRF_EVT_POWER_FAILURE_WARNING,                /**< Event indicating that a power failure warning has occurred. */
-  NRF_EVT_FLASH_OPERATION_SUCCESS,              /**< Event indicating that the ongoing flash operation has completed successfully. */
-  NRF_EVT_FLASH_OPERATION_ERROR,                /**< Event indicating that the ongoing flash operation has timed out with an error. */
-  NRF_EVT_RADIO_BLOCKED,                        /**< Event indicating that a radio timeslot was blocked. */
-  NRF_EVT_RADIO_CANCELED,                       /**< Event indicating that a radio timeslot was canceled by SoftDevice. */
-  NRF_EVT_RADIO_SIGNAL_CALLBACK_INVALID_RETURN, /**< Event indicating that a radio timeslot signal callback handler return was invalid. */
-  NRF_EVT_RADIO_SESSION_IDLE,                   /**< Event indicating that a radio timeslot session is idle. */
-  NRF_EVT_RADIO_SESSION_CLOSED,                 /**< Event indicating that a radio timeslot session is closed. */
-  NRF_EVT_POWER_USB_POWER_READY,                /**< Event indicating that a USB 3.3 V supply is ready. */
-  NRF_EVT_POWER_USB_DETECTED,                   /**< Event indicating that voltage supply is detected on VBUS. */
-  NRF_EVT_POWER_USB_REMOVED,                    /**< Event indicating that voltage supply is removed from VBUS. */
-  NRF_EVT_NUMBER_OF_EVTS
-};
-
-/**@} */
-
-
-/**@addtogroup NRF_SOC_STRUCTURES Structures
- * @{ */
-
-/**@brief Represents a mutex for use with the nrf_mutex functions.
- * @note Accessing the value directly is not safe, use the mutex functions!
- */
-typedef volatile uint8_t nrf_mutex_t;
-
-/**@brief Parameters for a request for a timeslot as early as possible. */
-typedef struct
-{
-  uint8_t       hfclk;                              /**< High frequency clock source, see @ref NRF_RADIO_HFCLK_CFG. */
-  uint8_t       priority;                           /**< The radio timeslot priority, see @ref NRF_RADIO_PRIORITY. */
-  uint32_t      length_us;                          /**< The radio timeslot length (in the range 100 to 100,000] microseconds). */
-  uint32_t      timeout_us;                         /**< Longest acceptable delay until the start of the requested timeslot (up to @ref NRF_RADIO_EARLIEST_TIMEOUT_MAX_US microseconds). */
-} nrf_radio_request_earliest_t;
-
-/**@brief Parameters for a normal radio timeslot request. */
-typedef struct
-{
-  uint8_t       hfclk;                              /**< High frequency clock source, see @ref NRF_RADIO_HFCLK_CFG. */
-  uint8_t       priority;                           /**< The radio timeslot priority, see @ref NRF_RADIO_PRIORITY. */
-  uint32_t      distance_us;                        /**< Distance from the start of the previous radio timeslot (up to @ref NRF_RADIO_DISTANCE_MAX_US microseconds). */
-  uint32_t      length_us;                          /**< The radio timeslot length (in the range [100..100,000] microseconds). */
-} nrf_radio_request_normal_t;
-
-/**@brief Radio timeslot request parameters. */
-typedef struct
-{
-  uint8_t                         request_type;     /**< Type of request, see @ref NRF_RADIO_REQUEST_TYPE. */
-  union
-  {
-    nrf_radio_request_earliest_t  earliest;         /**< Parameters for requesting a radio timeslot as early as possible. */
-    nrf_radio_request_normal_t    normal;           /**< Parameters for requesting a normal radio timeslot. */
-  } params;                                         /**< Parameter union. */
-} nrf_radio_request_t;
-
-/**@brief Return parameters of the radio timeslot signal callback. */
-typedef struct
-{
-  uint8_t               callback_action;            /**< The action requested by the application when returning from the signal callback, see @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION. */
-  union
-  {
-    struct
-    {
-      nrf_radio_request_t * p_next;                 /**< The request parameters for the next radio timeslot. */
-    } request;                                      /**< Additional parameters for return_code @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION_REQUEST_AND_END. */
-    struct
-    {
-      uint32_t              length_us;              /**< Requested extension of the radio timeslot duration (microseconds) (for minimum time see @ref NRF_RADIO_MINIMUM_TIMESLOT_LENGTH_EXTENSION_TIME_US). */
-    } extend;                                       /**< Additional parameters for return_code @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION_EXTEND. */
-  } params;                                         /**< Parameter union. */
-} nrf_radio_signal_callback_return_param_t;
-
-/**@brief The radio timeslot signal callback type.
- *
- * @note In case of invalid return parameters, the radio timeslot will automatically end
- *       immediately after returning from the signal callback and the
- *       @ref NRF_EVT_RADIO_SIGNAL_CALLBACK_INVALID_RETURN event will be sent.
- * @note The returned struct pointer must remain valid after the signal callback
- *       function returns. For instance, this means that it must not point to a stack variable.
- *
- * @param[in] signal_type Type of signal, see @ref NRF_RADIO_CALLBACK_SIGNAL_TYPE.
- *
- * @return Pointer to structure containing action requested by the application.
- */
-typedef nrf_radio_signal_callback_return_param_t * (*nrf_radio_signal_callback_t) (uint8_t signal_type);
-
-/**@brief AES ECB parameter typedefs */
-typedef uint8_t soc_ecb_key_t[SOC_ECB_KEY_LENGTH];                /**< Encryption key type. */
-typedef uint8_t soc_ecb_cleartext_t[SOC_ECB_CLEARTEXT_LENGTH];    /**< Cleartext data type. */
-typedef uint8_t soc_ecb_ciphertext_t[SOC_ECB_CIPHERTEXT_LENGTH];  /**< Ciphertext data type. */
-
-/**@brief AES ECB data structure */
-typedef struct
-{
-  soc_ecb_key_t        key;            /**< Encryption key. */
-  soc_ecb_cleartext_t  cleartext;      /**< Cleartext data. */
-  soc_ecb_ciphertext_t ciphertext;     /**< Ciphertext data. */
-} nrf_ecb_hal_data_t;
-
-/**@brief AES ECB block. Used to provide multiple blocks in a single call
-          to @ref sd_ecb_blocks_encrypt.*/
-typedef struct
-{
-  soc_ecb_key_t const *       p_key;           /**< Pointer to the Encryption key. */
-  soc_ecb_cleartext_t const * p_cleartext;     /**< Pointer to the Cleartext data. */
-  soc_ecb_ciphertext_t *      p_ciphertext;    /**< Pointer to the Ciphertext data. */
-} nrf_ecb_hal_data_block_t;
-
-/**@} */
-
-/**@addtogroup NRF_SOC_FUNCTIONS Functions
- * @{ */
-
-/**@brief Initialize a mutex.
- *
- * @param[in] p_mutex Pointer to the mutex to initialize.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_MUTEX_NEW, uint32_t, sd_mutex_new(nrf_mutex_t * p_mutex));
-
-/**@brief Attempt to acquire a mutex.
- *
- * @param[in] p_mutex Pointer to the mutex to acquire.
- *
- * @retval ::NRF_SUCCESS The mutex was successfully acquired.
- * @retval ::NRF_ERROR_SOC_MUTEX_ALREADY_TAKEN The mutex could not be acquired.
- */
-SVCALL(SD_MUTEX_ACQUIRE, uint32_t, sd_mutex_acquire(nrf_mutex_t * p_mutex));
-
-/**@brief Release a mutex.
- *
- * @param[in] p_mutex Pointer to the mutex to release.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_MUTEX_RELEASE, uint32_t, sd_mutex_release(nrf_mutex_t * p_mutex));
-
-/**@brief Query the capacity of the application random pool.
- *
- * @param[out] p_pool_capacity The capacity of the pool.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_RAND_APPLICATION_POOL_CAPACITY_GET, uint32_t, sd_rand_application_pool_capacity_get(uint8_t * p_pool_capacity));
-
-/**@brief Get number of random bytes available to the application.
- *
- * @param[out] p_bytes_available The number of bytes currently available in the pool.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_RAND_APPLICATION_BYTES_AVAILABLE_GET, uint32_t, sd_rand_application_bytes_available_get(uint8_t * p_bytes_available));
-
-/**@brief Get random bytes from the application pool.
- *
- * @param[out]  p_buff  Pointer to unit8_t buffer for storing the bytes.
- * @param[in]   length  Number of bytes to take from pool and place in p_buff.
- *
- * @retval ::NRF_SUCCESS The requested bytes were written to p_buff.
- * @retval ::NRF_ERROR_SOC_RAND_NOT_ENOUGH_VALUES No bytes were written to the buffer, because there were not enough bytes available.
-*/
-SVCALL(SD_RAND_APPLICATION_VECTOR_GET, uint32_t, sd_rand_application_vector_get(uint8_t * p_buff, uint8_t length));
-
-/**@brief Gets the reset reason register.
- *
- * @param[out]  p_reset_reason  Contents of the NRF_POWER->RESETREAS register.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_POWER_RESET_REASON_GET, uint32_t, sd_power_reset_reason_get(uint32_t * p_reset_reason));
-
-/**@brief Clears the bits of the reset reason register.
- *
- * @param[in] reset_reason_clr_msk Contains the bits to clear from the reset reason register.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_POWER_RESET_REASON_CLR, uint32_t, sd_power_reset_reason_clr(uint32_t reset_reason_clr_msk));
-
-/**@brief Sets the power mode when in CPU sleep.
- *
- * @param[in] power_mode The power mode to use when in CPU sleep, see @ref NRF_POWER_MODES. @sa sd_app_evt_wait
- *
- * @retval ::NRF_SUCCESS The power mode was set.
- * @retval ::NRF_ERROR_SOC_POWER_MODE_UNKNOWN The power mode was unknown.
- */
-SVCALL(SD_POWER_MODE_SET, uint32_t, sd_power_mode_set(uint8_t power_mode));
-
-/**@brief Puts the chip in System OFF mode.
- *
- * @retval ::NRF_ERROR_SOC_POWER_OFF_SHOULD_NOT_RETURN
- */
-SVCALL(SD_POWER_SYSTEM_OFF, uint32_t, sd_power_system_off(void));
-
-/**@brief Enables or disables the power-fail comparator.
- *
- * Enabling this will give a SoftDevice event (NRF_EVT_POWER_FAILURE_WARNING) when the power failure warning occurs.
- * The event can be retrieved with sd_evt_get();
- *
- * @param[in] pof_enable    True if the power-fail comparator should be enabled, false if it should be disabled.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_POWER_POF_ENABLE, uint32_t, sd_power_pof_enable(uint8_t pof_enable));
-
-/**@brief Enables or disables the USB power ready event.
- *
- * Enabling this will give a SoftDevice event (NRF_EVT_POWER_USB_POWER_READY) when a USB 3.3 V supply is ready.
- * The event can be retrieved with sd_evt_get();
- *
- * @param[in] usbpwrrdy_enable    True if the power ready event should be enabled, false if it should be disabled.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_POWER_USBPWRRDY_ENABLE, uint32_t, sd_power_usbpwrrdy_enable(uint8_t usbpwrrdy_enable));
-
-/**@brief Enables or disables the power USB-detected event.
- *
- * Enabling this will give a SoftDevice event (NRF_EVT_POWER_USB_DETECTED) when a voltage supply is detected on VBUS.
- * The event can be retrieved with sd_evt_get();
- *
- * @param[in] usbdetected_enable    True if the power ready event should be enabled, false if it should be disabled.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_POWER_USBDETECTED_ENABLE, uint32_t, sd_power_usbdetected_enable(uint8_t usbdetected_enable));
-
-/**@brief Enables or disables the power USB-removed event.
- *
- * Enabling this will give a SoftDevice event (NRF_EVT_POWER_USB_REMOVED) when a voltage supply is removed from VBUS.
- * The event can be retrieved with sd_evt_get();
- *
- * @param[in] usbremoved_enable    True if the power ready event should be enabled, false if it should be disabled.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_POWER_USBREMOVED_ENABLE, uint32_t, sd_power_usbremoved_enable(uint8_t usbremoved_enable));
-
-/**@brief Get USB supply status register content.
- *
- * @param[out] usbregstatus    The content of USBREGSTATUS register.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_POWER_USBREGSTATUS_GET, uint32_t, sd_power_usbregstatus_get(uint32_t * usbregstatus));
-
-/**@brief Sets the power failure comparator threshold value.
- *
- * @note: Power failure comparator threshold setting. This setting applies both for normal voltage
- *        mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to
- *        VDDH only).
- *
- * @param[in] threshold The power-fail threshold value to use, see @ref NRF_POWER_THRESHOLDS.
- *
- * @retval ::NRF_SUCCESS The power failure threshold was set.
- * @retval ::NRF_ERROR_SOC_POWER_POF_THRESHOLD_UNKNOWN The power failure threshold is unknown.
- */
-SVCALL(SD_POWER_POF_THRESHOLD_SET, uint32_t, sd_power_pof_threshold_set(uint8_t threshold));
-
-/**@brief Sets the power failure comparator threshold value for high voltage.
- *
- * @note: Power failure comparator threshold setting for high voltage mode (supply connected to
- *        VDDH only). This setting does not apply for normal voltage mode (supply connected to both
- *        VDD and VDDH).
- *
- * @param[in] threshold The power-fail threshold value to use, see @ref NRF_POWER_THRESHOLDVDDHS.
- *
- * @retval ::NRF_SUCCESS The power failure threshold was set.
- * @retval ::NRF_ERROR_SOC_POWER_POF_THRESHOLD_UNKNOWN The power failure threshold is unknown.
- */
-SVCALL(SD_POWER_POF_THRESHOLDVDDH_SET, uint32_t, sd_power_pof_thresholdvddh_set(uint8_t threshold));
-
-/**@brief Writes the NRF_POWER->RAM[index].POWERSET register.
- *
- * @param[in] index Contains the index in the NRF_POWER->RAM[index].POWERSET register to write to.
- * @param[in] ram_powerset Contains the word to write to the NRF_POWER->RAM[index].POWERSET register.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_POWER_RAM_POWER_SET, uint32_t, sd_power_ram_power_set(uint8_t index, uint32_t ram_powerset));
-
-/**@brief Writes the NRF_POWER->RAM[index].POWERCLR register.
- *
- * @param[in] index Contains the index in the NRF_POWER->RAM[index].POWERCLR register to write to.
- * @param[in] ram_powerclr Contains the word to write to the NRF_POWER->RAM[index].POWERCLR register.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_POWER_RAM_POWER_CLR, uint32_t, sd_power_ram_power_clr(uint8_t index, uint32_t ram_powerclr));
-
-/**@brief Get contents of NRF_POWER->RAM[index].POWER register, indicates power status of RAM[index] blocks.
- *
- * @param[in] index Contains the index in the NRF_POWER->RAM[index].POWER register to read from.
- * @param[out] p_ram_power Content of NRF_POWER->RAM[index].POWER register.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_POWER_RAM_POWER_GET, uint32_t, sd_power_ram_power_get(uint8_t index, uint32_t * p_ram_power));
-
-/**@brief Set bits in the general purpose retention registers (NRF_POWER->GPREGRET*).
- *
- * @param[in] gpregret_id 0 for GPREGRET, 1 for GPREGRET2.
- * @param[in] gpregret_msk Bits to be set in the GPREGRET register.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_POWER_GPREGRET_SET, uint32_t, sd_power_gpregret_set(uint32_t gpregret_id, uint32_t gpregret_msk));
-
-/**@brief Clear bits in the general purpose retention registers (NRF_POWER->GPREGRET*).
- *
- * @param[in] gpregret_id 0 for GPREGRET, 1 for GPREGRET2.
- * @param[in] gpregret_msk Bits to be clear in the GPREGRET register.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_POWER_GPREGRET_CLR, uint32_t, sd_power_gpregret_clr(uint32_t gpregret_id, uint32_t gpregret_msk));
-
-/**@brief Get contents of the general purpose retention registers (NRF_POWER->GPREGRET*).
- *
- * @param[in] gpregret_id 0 for GPREGRET, 1 for GPREGRET2.
- * @param[out] p_gpregret Contents of the GPREGRET register.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_POWER_GPREGRET_GET, uint32_t, sd_power_gpregret_get(uint32_t gpregret_id, uint32_t *p_gpregret));
-
-/**@brief Enable or disable the DC/DC regulator for the regulator stage 1 (REG1).
- *
- * @param[in] dcdc_mode The mode of the DCDC, see @ref NRF_POWER_DCDC_MODES.
- *
- * @retval ::NRF_SUCCESS
- * @retval ::NRF_ERROR_INVALID_PARAM The DCDC mode is invalid.
- */
-SVCALL(SD_POWER_DCDC_MODE_SET, uint32_t, sd_power_dcdc_mode_set(uint8_t dcdc_mode));
-
-/**@brief Enable or disable the DC/DC regulator for the regulator stage 0 (REG0).
- *
- * For more details on the REG0 stage, please see product specification.
- *
- * @param[in] dcdc_mode The mode of the DCDC0, see @ref NRF_POWER_DCDC_MODES.
- *
- * @retval ::NRF_SUCCESS
- * @retval ::NRF_ERROR_INVALID_PARAM The dcdc_mode is invalid.
- */
-SVCALL(SD_POWER_DCDC0_MODE_SET, uint32_t, sd_power_dcdc0_mode_set(uint8_t dcdc_mode));
-
-/**@brief Request the high frequency crystal oscillator.
- *
- * Will start the high frequency crystal oscillator, the startup time of the crystal varies
- * and the ::sd_clock_hfclk_is_running function can be polled to check if it has started.
- *
- * @see sd_clock_hfclk_is_running
- * @see sd_clock_hfclk_release
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_CLOCK_HFCLK_REQUEST, uint32_t, sd_clock_hfclk_request(void));
-
-/**@brief Releases the high frequency crystal oscillator.
- *
- * Will stop the high frequency crystal oscillator, this happens immediately.
- *
- * @see sd_clock_hfclk_is_running
- * @see sd_clock_hfclk_request
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_CLOCK_HFCLK_RELEASE, uint32_t, sd_clock_hfclk_release(void));
-
-/**@brief Checks if the high frequency crystal oscillator is running.
- *
- * @see sd_clock_hfclk_request
- * @see sd_clock_hfclk_release
- *
- * @param[out] p_is_running 1 if the external crystal oscillator is running, 0 if not.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_CLOCK_HFCLK_IS_RUNNING, uint32_t, sd_clock_hfclk_is_running(uint32_t * p_is_running));
-
-/**@brief Waits for an application event.
- *
- * An application event is either an application interrupt or a pended interrupt when the interrupt
- * is disabled.
- *
- * When the application waits for an application event by calling this function, an interrupt that
- * is enabled will be taken immediately on pending since this function will wait in thread mode,
- * then the execution will return in the application's main thread.
- *
- * In order to wake up from disabled interrupts, the SEVONPEND flag has to be set in the Cortex-M
- * MCU's System Control Register (SCR), CMSIS_SCB. In that case, when a disabled interrupt gets
- * pended, this function will return to the application's main thread.
- *
- * @note The application must ensure that the pended flag is cleared using ::sd_nvic_ClearPendingIRQ
- *       in order to sleep using this function. This is only necessary for disabled interrupts, as
- *       the interrupt handler will clear the pending flag automatically for enabled interrupts.
- *
- * @note If an application interrupt has happened since the last time sd_app_evt_wait was
- *       called this function will return immediately and not go to sleep. This is to avoid race
- *       conditions that can occur when a flag is updated in the interrupt handler and processed
- *       in the main loop.
- *
- * @post An application interrupt has happened or a interrupt pending flag is set.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_APP_EVT_WAIT, uint32_t, sd_app_evt_wait(void));
-
-/**@brief Get PPI channel enable register contents.
- *
- * @param[out] p_channel_enable The contents of the PPI CHEN register.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_PPI_CHANNEL_ENABLE_GET, uint32_t, sd_ppi_channel_enable_get(uint32_t * p_channel_enable));
-
-/**@brief Set PPI channel enable register.
- *
- * @param[in] channel_enable_set_msk Mask containing the bits to set in the PPI CHEN register.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_PPI_CHANNEL_ENABLE_SET, uint32_t, sd_ppi_channel_enable_set(uint32_t channel_enable_set_msk));
-
-/**@brief Clear PPI channel enable register.
- *
- * @param[in] channel_enable_clr_msk Mask containing the bits to clear in the PPI CHEN register.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_PPI_CHANNEL_ENABLE_CLR, uint32_t, sd_ppi_channel_enable_clr(uint32_t channel_enable_clr_msk));
-
-/**@brief Assign endpoints to a PPI channel.
- *
- * @param[in] channel_num Number of the PPI channel to assign.
- * @param[in] evt_endpoint Event endpoint of the PPI channel.
- * @param[in] task_endpoint Task endpoint of the PPI channel.
- *
- * @retval ::NRF_ERROR_SOC_PPI_INVALID_CHANNEL The channel number is invalid.
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_PPI_CHANNEL_ASSIGN, uint32_t, sd_ppi_channel_assign(uint8_t channel_num, const volatile void * evt_endpoint, const volatile void * task_endpoint));
-
-/**@brief Task to enable a channel group.
- *
- * @param[in] group_num Number of the channel group.
- *
- * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_PPI_GROUP_TASK_ENABLE, uint32_t, sd_ppi_group_task_enable(uint8_t group_num));
-
-/**@brief Task to disable a channel group.
- *
- * @param[in] group_num Number of the PPI group.
- *
- * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid.
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_PPI_GROUP_TASK_DISABLE, uint32_t, sd_ppi_group_task_disable(uint8_t group_num));
-
-/**@brief Assign PPI channels to a channel group.
- *
- * @param[in] group_num Number of the channel group.
- * @param[in] channel_msk Mask of the channels to assign to the group.
- *
- * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid.
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_PPI_GROUP_ASSIGN, uint32_t, sd_ppi_group_assign(uint8_t group_num, uint32_t channel_msk));
-
-/**@brief Gets the PPI channels of a channel group.
- *
- * @param[in]   group_num Number of the channel group.
- * @param[out]  p_channel_msk Mask of the channels assigned to the group.
- *
- * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid.
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_PPI_GROUP_GET, uint32_t, sd_ppi_group_get(uint8_t group_num, uint32_t * p_channel_msk));
-
-/**@brief Configures the Radio Notification signal.
- *
- * @note
- *      - The notification signal latency depends on the interrupt priority settings of SWI used
- *        for notification signal.
- *      - To ensure that the radio notification signal behaves in a consistent way, the radio
- *        notifications must be configured when there is no protocol stack or other SoftDevice
- *        activity in progress. It is recommended that the radio notification signal is
- *        configured directly after the SoftDevice has been enabled.
- *      - In the period between the ACTIVE signal and the start of the Radio Event, the SoftDevice
- *        will interrupt the application to do Radio Event preparation.
- *      - Using the Radio Notification feature may limit the bandwidth, as the SoftDevice may have
- *        to shorten the connection events to have time for the Radio Notification signals.
- *
- * @param[in]  type      Type of notification signal, see @ref NRF_RADIO_NOTIFICATION_TYPES.
- *                       @ref NRF_RADIO_NOTIFICATION_TYPE_NONE shall be used to turn off radio
- *                       notification. Using @ref NRF_RADIO_NOTIFICATION_DISTANCE_NONE is
- *                       recommended (but not required) to be used with
- *                       @ref NRF_RADIO_NOTIFICATION_TYPE_NONE.
- *
- * @param[in]  distance  Distance between the notification signal and start of radio activity, see @ref NRF_RADIO_NOTIFICATION_DISTANCES.
- *                       This parameter is ignored when @ref NRF_RADIO_NOTIFICATION_TYPE_NONE or
- *                       @ref NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE is used.
- *
- * @retval ::NRF_ERROR_INVALID_PARAM The group number is invalid.
- * @retval ::NRF_ERROR_INVALID_STATE A protocol stack or other SoftDevice is running. Stop all
- *                                   running activities and retry.
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_RADIO_NOTIFICATION_CFG_SET, uint32_t, sd_radio_notification_cfg_set(uint8_t type, uint8_t distance));
-
-/**@brief Encrypts a block according to the specified parameters.
- *
- * 128-bit AES encryption.
- *
- * @note:
- *    - The application may set the SEVONPEND bit in the SCR to 1 to make the SoftDevice sleep while
- *      the ECB is running. The SEVONPEND bit should only be cleared (set to 0) from application
- *      main or low interrupt level.
- *
- * @param[in, out] p_ecb_data Pointer to the ECB parameters' struct (two input
- *                            parameters and one output parameter).
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_ECB_BLOCK_ENCRYPT, uint32_t, sd_ecb_block_encrypt(nrf_ecb_hal_data_t * p_ecb_data));
-
-/**@brief Encrypts multiple data blocks provided as an array of data block structures.
- *
- * @details: Performs 128-bit AES encryption on multiple data blocks
- *
- * @note:
- *    - The application may set the SEVONPEND bit in the SCR to 1 to make the SoftDevice sleep while
- *      the ECB is running. The SEVONPEND bit should only be cleared (set to 0) from application
- *      main or low interrupt level.
- *
- * @param[in]     block_count     Count of blocks in the p_data_blocks array.
- * @param[in,out] p_data_blocks   Pointer to the first entry in a contiguous array of
- *                                @ref nrf_ecb_hal_data_block_t structures.
- *
- * @retval ::NRF_SUCCESS
- */
-SVCALL(SD_ECB_BLOCKS_ENCRYPT, uint32_t, sd_ecb_blocks_encrypt(uint8_t block_count, nrf_ecb_hal_data_block_t * p_data_blocks));
-
-/**@brief Gets any pending events generated by the SoC API.
- *
- * The application should keep calling this function to get events, until ::NRF_ERROR_NOT_FOUND is returned.
- *
- * @param[out] p_evt_id Set to one of the values in @ref NRF_SOC_EVTS, if any events are pending.
- *
- * @retval ::NRF_SUCCESS An event was pending. The event id is written in the p_evt_id parameter.
- * @retval ::NRF_ERROR_NOT_FOUND No pending events.
- */
-SVCALL(SD_EVT_GET, uint32_t, sd_evt_get(uint32_t * p_evt_id));
-
-/**@brief Get the temperature measured on the chip
- *
- * This function will block until the temperature measurement is done.
- * It takes around 50 us from call to return.
- *
- * @param[out] p_temp Result of temperature measurement. Die temperature in 0.25 degrees Celsius.
- *
- * @retval ::NRF_SUCCESS A temperature measurement was done, and the temperature was written to temp
- */
-SVCALL(SD_TEMP_GET, uint32_t, sd_temp_get(int32_t * p_temp));
-
-/**@brief Flash Write
-*
-* Commands to write a buffer to flash
-*
-* If the SoftDevice is enabled:
-*  This call initiates the flash access command, and its completion will be communicated to the
-*  application with exactly one of the following events:
-*      - @ref NRF_EVT_FLASH_OPERATION_SUCCESS - The command was successfully completed.
-*      - @ref NRF_EVT_FLASH_OPERATION_ERROR   - The command could not be started.
-*
-* If the SoftDevice is not enabled no event will be generated, and this call will return @ref NRF_SUCCESS when the
- * write has been completed
-*
-* @note
-*      - This call takes control over the radio and the CPU during flash erase and write to make sure that
-*        they will not interfere with the flash access. This means that all interrupts will be blocked
-*        for a predictable time (depending on the NVMC specification in the device's Product Specification
-*        and the command parameters).
-*      - The data in the p_src buffer should not be modified before the @ref NRF_EVT_FLASH_OPERATION_SUCCESS
-*        or the @ref NRF_EVT_FLASH_OPERATION_ERROR have been received if the SoftDevice is enabled.
-*      - This call will make the SoftDevice trigger a hardfault when the page is written, if it is
-*        protected.
-*
-*
-* @param[in]  p_dst Pointer to start of flash location to be written.
-* @param[in]  p_src Pointer to buffer with data to be written.
-* @param[in]  size  Number of 32-bit words to write. Maximum size is the number of words in one
-*                   flash page. See the device's Product Specification for details.
-*
-* @retval ::NRF_ERROR_INVALID_ADDR   Tried to write to a non existing flash address, or p_dst or p_src was unaligned.
-* @retval ::NRF_ERROR_BUSY           The previous command has not yet completed.
-* @retval ::NRF_ERROR_INVALID_LENGTH Size was 0, or higher than the maximum allowed size.
-* @retval ::NRF_ERROR_FORBIDDEN      Tried to write to an address outside the application flash area.
-* @retval ::NRF_SUCCESS              The command was accepted.
-*/
-SVCALL(SD_FLASH_WRITE, uint32_t, sd_flash_write(uint32_t * p_dst, uint32_t const * p_src, uint32_t size));
-
-
-/**@brief Flash Erase page
-*
-* Commands to erase a flash page
-* If the SoftDevice is enabled:
-*  This call initiates the flash access command, and its completion will be communicated to the
-*  application with exactly one of the following events:
-*      - @ref NRF_EVT_FLASH_OPERATION_SUCCESS - The command was successfully completed.
-*      - @ref NRF_EVT_FLASH_OPERATION_ERROR   - The command could not be started.
-*
-* If the SoftDevice is not enabled no event will be generated, and this call will return @ref NRF_SUCCESS when the
-* erase has been completed
-*
-* @note
-*      - This call takes control over the radio and the CPU during flash erase and write to make sure that
-*        they will not interfere with the flash access. This means that all interrupts will be blocked
-*        for a predictable time (depending on the NVMC specification in the device's Product Specification
-*        and the command parameters).
-*      - This call will make the SoftDevice trigger a hardfault when the page is erased, if it is
-*        protected.
-*
-*
-* @param[in]  page_number           Page number of the page to erase
-*
-* @retval ::NRF_ERROR_INTERNAL      If a new session could not be opened due to an internal error.
-* @retval ::NRF_ERROR_INVALID_ADDR  Tried to erase to a non existing flash page.
-* @retval ::NRF_ERROR_BUSY          The previous command has not yet completed.
-* @retval ::NRF_ERROR_FORBIDDEN     Tried to erase a page outside the application flash area.
-* @retval ::NRF_SUCCESS             The command was accepted.
-*/
-SVCALL(SD_FLASH_PAGE_ERASE, uint32_t, sd_flash_page_erase(uint32_t page_number));
-
-
-
-/**@brief Opens a session for radio timeslot requests.
- *
- * @note Only one session can be open at a time.
- * @note p_radio_signal_callback(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START) will be called when the radio timeslot
- *       starts. From this point the NRF_RADIO and NRF_TIMER0 peripherals can be freely accessed
- *       by the application.
- * @note p_radio_signal_callback(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_TIMER0) is called whenever the NRF_TIMER0
- *       interrupt occurs.
- * @note p_radio_signal_callback(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_RADIO) is called whenever the NRF_RADIO
- *       interrupt occurs.
- * @note p_radio_signal_callback() will be called at ARM interrupt priority level 0. This
- *       implies that none of the sd_* API calls can be used from p_radio_signal_callback().
- *
- * @param[in] p_radio_signal_callback The signal callback.
- *
- * @retval ::NRF_ERROR_INVALID_ADDR p_radio_signal_callback is an invalid function pointer.
- * @retval ::NRF_ERROR_BUSY If session cannot be opened.
- * @retval ::NRF_ERROR_INTERNAL If a new session could not be opened due to an internal error.
- * @retval ::NRF_SUCCESS Otherwise.
- */
- SVCALL(SD_RADIO_SESSION_OPEN, uint32_t, sd_radio_session_open(nrf_radio_signal_callback_t p_radio_signal_callback));
-
-/**@brief Closes a session for radio timeslot requests.
- *
- * @note Any current radio timeslot will be finished before the session is closed.
- * @note If a radio timeslot is scheduled when the session is closed, it will be canceled.
- * @note The application cannot consider the session closed until the @ref NRF_EVT_RADIO_SESSION_CLOSED
- *       event is received.
- *
- * @retval ::NRF_ERROR_FORBIDDEN If session not opened.
- * @retval ::NRF_ERROR_BUSY If session is currently being closed.
- * @retval ::NRF_SUCCESS Otherwise.
- */
- SVCALL(SD_RADIO_SESSION_CLOSE, uint32_t, sd_radio_session_close(void));
-
-/**@brief Requests a radio timeslot.
- *
- * @note The request type is determined by p_request->request_type, and can be one of @ref NRF_RADIO_REQ_TYPE_EARLIEST
- *       and @ref NRF_RADIO_REQ_TYPE_NORMAL. The first request in a session must always be of type @ref NRF_RADIO_REQ_TYPE_EARLIEST.
- * @note For a normal request (@ref NRF_RADIO_REQ_TYPE_NORMAL), the start time of a radio timeslot is specified by
- *       p_request->distance_us and is given relative to the start of the previous timeslot.
- * @note A too small p_request->distance_us will lead to a @ref NRF_EVT_RADIO_BLOCKED event.
- * @note Timeslots scheduled too close will lead to a @ref NRF_EVT_RADIO_BLOCKED event.
- * @note See the SoftDevice Specification for more on radio timeslot scheduling, distances and lengths.
- * @note If an opportunity for the first radio timeslot is not found before 100 ms after the call to this
- *       function, it is not scheduled, and instead a @ref NRF_EVT_RADIO_BLOCKED event is sent.
- *       The application may then try to schedule the first radio timeslot again.
- * @note Successful requests will result in nrf_radio_signal_callback_t(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START).
- *       Unsuccessful requests will result in a @ref NRF_EVT_RADIO_BLOCKED event, see @ref NRF_SOC_EVTS.
- * @note The jitter in the start time of the radio timeslots is +/- @ref NRF_RADIO_START_JITTER_US us.
- * @note The nrf_radio_signal_callback_t(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START) call has a latency relative to the
- *       specified radio timeslot start, but this does not affect the actual start time of the timeslot.
- * @note NRF_TIMER0 is reset at the start of the radio timeslot, and is clocked at 1MHz from the high frequency
- *       (16 MHz) clock source. If p_request->hfclk_force_xtal is true, the high frequency clock is
- *       guaranteed to be clocked from the external crystal.
- * @note The SoftDevice will neither access the NRF_RADIO peripheral nor the NRF_TIMER0 peripheral
- *       during the radio timeslot.
- *
- * @param[in] p_request Pointer to the request parameters.
- *
- * @retval ::NRF_ERROR_FORBIDDEN If session not opened or the session is not IDLE.
- * @retval ::NRF_ERROR_INVALID_ADDR If the p_request pointer is invalid.
- * @retval ::NRF_ERROR_INVALID_PARAM If the parameters of p_request are not valid.
- * @retval ::NRF_SUCCESS Otherwise.
- */
- SVCALL(SD_RADIO_REQUEST, uint32_t, sd_radio_request(nrf_radio_request_t const * p_request));
-
-/**@brief Write register protected by the SoftDevice
- *
- * This function writes to a register that is write-protected by the SoftDevice. Please refer to your
- * SoftDevice Specification for more details about which registers that are protected by SoftDevice.
- * This function can write to the following protected peripheral:
- *  - ACL
- *
- * @note Protected registers may be read directly.
- * @note Register that are write-once will return @ref NRF_SUCCESS on second set, even the value in
- *       the register has not changed. See the Product Specification for more details about register
- *       properties.
- *
- * @param[in]  p_register Pointer to register to be written.
- * @param[in]  value Value to be written to the register.
- *
- * @retval ::NRF_ERROR_INVALID_ADDR This function can not write to the reguested register.
- * @retval ::NRF_SUCCESS Value successfully written to register.
- *
- */
-SVCALL(SD_PROTECTED_REGISTER_WRITE, uint32_t, sd_protected_register_write(volatile uint32_t * p_register, uint32_t value));
-
-/**@} */
-
-#ifdef __cplusplus
-}
-#endif
-#endif // NRF_SOC_H__
-
-/**@} */
diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_svc.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_svc.h
deleted file mode 100755
index 292c6929..00000000
--- a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_svc.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright (c) 2012 - 2017, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- *    list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form, except as embedded into a Nordic
- *    Semiconductor ASA integrated circuit in a product or a software update for
- *    such product, must reproduce the above copyright notice, this list of
- *    conditions and the following disclaimer in the documentation and/or other
- *    materials provided with the distribution.
- *
- * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
- *    contributors may be used to endorse or promote products derived from this
- *    software without specific prior written permission.
- *
- * 4. This software, with or without modification, must only be used with a
- *    Nordic Semiconductor ASA integrated circuit.
- *
- * 5. Any software provided in binary form under this license must not be reverse
- *    engineered, decompiled, modified and/or disassembled.
- *
- * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef NRF_SVC__
-#define NRF_SVC__
-
-#include "stdint.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef SVCALL_AS_NORMAL_FUNCTION
-#define SVCALL(number, return_type, signature) return_type signature
-#else
-
-#ifndef SVCALL
-#if defined (__CC_ARM)
-#define SVCALL(number, return_type, signature) return_type __svc(number) signature
-#elif defined (__GNUC__)
-#ifdef __cplusplus
-#define GCC_CAST_CPP (uint16_t)
-#else
-#define GCC_CAST_CPP
-#endif
-#define SVCALL(number, return_type, signature)          \
-  _Pragma("GCC diagnostic push")                        \
-  _Pragma("GCC diagnostic ignored \"-Wreturn-type\"")   \
-  __attribute__((naked))                                \
-  __attribute__((unused))                               \
-  static return_type signature                          \
-  {                                                     \
-    __asm(                                              \
-        "svc %0\n"                                      \
-        "bx r14" : : "I" (GCC_CAST_CPP number) : "r0"   \
-    );                                                  \
-  }                                                     \
-  _Pragma("GCC diagnostic pop")
-
-#elif defined (__ICCARM__)
-#define PRAGMA(x) _Pragma(#x)
-#define SVCALL(number, return_type, signature)          \
-PRAGMA(swi_number = (number))                           \
- __swi return_type signature;
-#else
-#define SVCALL(number, return_type, signature) return_type signature
-#endif
-#endif  // SVCALL
-
-#endif  // SVCALL_AS_NORMAL_FUNCTION
-
-#ifdef __cplusplus
-}
-#endif
-#endif  // NRF_SVC__
diff --git a/tinyusb/hw/mcu/nordic/nrfx_config.h b/tinyusb/hw/mcu/nordic/nrfx_config.h
deleted file mode 100755
index 6a974ba7..00000000
--- a/tinyusb/hw/mcu/nordic/nrfx_config.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef NRFX_CONFIG_H__
-#define NRFX_CONFIG_H__
-
-#define NRFX_POWER_ENABLED   1
-#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY  7
-
-#define NRFX_CLOCK_ENABLED   0
-
-#define NRFX_UARTE_ENABLED   1
-#define NRFX_UARTE0_ENABLED  1
-
-#define NRFX_UARTE1_ENABLED  0
-#define NRFX_UARTE2_ENABLED  0
-#define NRFX_UARTE3_ENABLED  0
-
-#define NRFX_PRS_ENABLED     0
-
-#endif // NRFX_CONFIG_H__
diff --git a/tinyusb/hw/mcu/nordic/nrfx_glue.h b/tinyusb/hw/mcu/nordic/nrfx_glue.h
deleted file mode 100755
index cdf49b4a..00000000
--- a/tinyusb/hw/mcu/nordic/nrfx_glue.h
+++ /dev/null
@@ -1,227 +0,0 @@
-/*
- * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- *    list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- *    contributors may be used to endorse or promote products derived from this
- *    software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef NRFX_GLUE_H__
-#define NRFX_GLUE_H__
-
-// THIS IS A TEMPLATE FILE.
-// It should be copied to a suitable location within the host environment into
-// which nrfx is integrated, and the following macros should be provided with
-// appropriate implementations.
-// And this comment should be removed from the customized file.
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @defgroup nrfx_glue nrfx_glue.h
- * @{
- * @ingroup nrfx
- *
- * @brief This file contains macros that should be implemented according to
- *        the needs of the host environment into which @em nrfx is integrated.
- */
-
-// Uncomment this line to use the standard MDK way of binding IRQ handlers
-// at linking time.
-#include <soc/nrfx_irqs.h>
-
-//------------------------------------------------------------------------------
-
-/**
- * @brief Macro for placing a runtime assertion.
- *
- * @param expression  Expression to evaluate.
- */
-#define NRFX_ASSERT(expression)
-
-/**
- * @brief Macro for placing a compile time assertion.
- *
- * @param expression  Expression to evaluate.
- */
-#define NRFX_STATIC_ASSERT(expression)
-
-//------------------------------------------------------------------------------
-
-/**
- * @brief Macro for setting the priority of a specific IRQ.
- *
- * @param irq_number  IRQ number.
- * @param priority    Priority to set.
- */
-#define NRFX_IRQ_PRIORITY_SET(irq_number, priority) _NRFX_IRQ_PRIORITY_SET(irq_number, priority)
-static inline void _NRFX_IRQ_PRIORITY_SET(IRQn_Type irq_number,
-                                          uint8_t   priority)
-{
-    NRFX_ASSERT(INTERRUPT_PRIORITY_IS_VALID(priority));
-    NVIC_SetPriority(irq_number, priority);
-}
-
-/**
- * @brief Macro for enabling a specific IRQ.
- *
- * @param irq_number  IRQ number.
- */
-#define NRFX_IRQ_ENABLE(irq_number)  _NRFX_IRQ_ENABLE(irq_number)
-static inline void _NRFX_IRQ_ENABLE(IRQn_Type irq_number)
-{
-    NVIC_ClearPendingIRQ(irq_number);
-    NVIC_EnableIRQ(irq_number);
-}
-
-/**
- * @brief Macro for checking if a specific IRQ is enabled.
- *
- * @param irq_number  IRQ number.
- *
- * @retval true  If the IRQ is enabled.
- * @retval false Otherwise.
- */
-#define NRFX_IRQ_IS_ENABLED(irq_number)  _NRFX_IRQ_IS_ENABLED(irq_number)
-static inline bool _NRFX_IRQ_IS_ENABLED(IRQn_Type irq_number)
-{
-    return 0 != (NVIC->ISER[irq_number / 32] & (1UL << (irq_number % 32)));
-}
-
-/**
- * @brief Macro for disabling a specific IRQ.
- *
- * @param irq_number  IRQ number.
- */
-#define NRFX_IRQ_DISABLE(irq_number)  _NRFX_IRQ_DISABLE(irq_number)
-static inline void _NRFX_IRQ_DISABLE(IRQn_Type irq_number)
-{
-    NVIC_DisableIRQ(irq_number);
-}
-
-/**
- * @brief Macro for setting a specific IRQ as pending.
- *
- * @param irq_number  IRQ number.
- */
-#define NRFX_IRQ_PENDING_SET(irq_number) _NRFX_IRQ_PENDING_SET(irq_number)
-static inline void _NRFX_IRQ_PENDING_SET(IRQn_Type irq_number)
-{
-    NVIC_SetPendingIRQ(irq_number);
-}
-
-/**
- * @brief Macro for clearing the pending status of a specific IRQ.
- *
- * @param irq_number  IRQ number.
- */
-#define NRFX_IRQ_PENDING_CLEAR(irq_number) _NRFX_IRQ_PENDING_CLEAR(irq_number)
-static inline void _NRFX_IRQ_PENDING_CLEAR(IRQn_Type irq_number)
-{
-    NVIC_ClearPendingIRQ(irq_number);
-}
-
-/**
- * @brief Macro for checking the pending status of a specific IRQ.
- *
- * @retval true  If the IRQ is pending.
- * @retval false Otherwise.
- */
-#define NRFX_IRQ_IS_PENDING(irq_number) _NRFX_IRQ_IS_PENDING(irq_number)
-static inline bool _NRFX_IRQ_IS_PENDING(IRQn_Type irq_number)
-{
-    return (NVIC_GetPendingIRQ(irq_number) == 1);
-}
-
-/**
- * @brief Macro for entering into a critical section.
- */
-#define NRFX_CRITICAL_SECTION_ENTER()
-
-/**
- * @brief Macro for exiting from a critical section.
- */
-#define NRFX_CRITICAL_SECTION_EXIT()
-
-//------------------------------------------------------------------------------
-
-/**
- * @brief When set to a non-zero value, this macro specifies that
- *        @ref nrfx_coredep_delay_us uses a precise DWT-based solution.
- *        A compilation error is generated if the DWT unit is not present
- *        in the SoC used.
- */
-#define NRFX_DELAY_DWT_BASED    0
-
-/**
- * @brief Macro for delaying the code execution for at least the specified time.
- *
- * @param us_time Number of microseconds to wait.
- */
-#include <soc/nrfx_coredep.h>
-#define NRFX_DELAY_US(us_time) nrfx_coredep_delay_us(us_time)
-
-//------------------------------------------------------------------------------
-
-/**
- * @brief When set to a non-zero value, this macro specifies that the
- *        @ref nrfx_error_codes and the @ref nrfx_err_t type itself are defined
- *        in a customized way and the default definitions from @c <nrfx_error.h>
- *        should not be used.
- */
-#define NRFX_CUSTOM_ERROR_CODES 0
-
-//------------------------------------------------------------------------------
-
-/**
- * @brief Bitmask defining PPI channels reserved to be used outside of nrfx.
- */
-#define NRFX_PPI_CHANNELS_USED  0
-
-/**
- * @brief Bitmask defining PPI groups reserved to be used outside of nrfx.
- */
-#define NRFX_PPI_GROUPS_USED    0
-
-/**
- * @brief Bitmask defining SWI instances reserved to be used outside of nrfx.
- */
-#define NRFX_SWI_USED           0
-
-/**
- * @brief Bitmask defining TIMER instances reserved to be used outside of nrfx.
- */
-#define NRFX_TIMERS_USED        0
-
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // NRFX_GLUE_H__
diff --git a/tinyusb/hw/mcu/nordic/nrfx_log.h b/tinyusb/hw/mcu/nordic/nrfx_log.h
deleted file mode 100755
index 3bc1b424..00000000
--- a/tinyusb/hw/mcu/nordic/nrfx_log.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- *    list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- *    contributors may be used to endorse or promote products derived from this
- *    software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef NRFX_LOG_H__
-#define NRFX_LOG_H__
-
-// THIS IS A TEMPLATE FILE.
-// It should be copied to a suitable location within the host environment into
-// which nrfx is integrated, and the following macros should be provided with
-// appropriate implementations.
-// And this comment should be removed from the customized file.
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @defgroup nrfx_log nrfx_log.h
- * @{
- * @ingroup nrfx
- *
- * @brief This file contains macros that should be implemented according to
- *        the needs of the host environment into which @em nrfx is integrated.
- */
-
-/**
- * @brief Macro for logging a message with the severity level ERROR.
- *
- * @param format printf-style format string, optionally followed by arguments
- *               to be formatted and inserted in the resulting string.
- */
-#define NRFX_LOG_ERROR(format, ...)
-
-/**
- * @brief Macro for logging a message with the severity level WARNING.
- *
- * @param format printf-style format string, optionally followed by arguments
- *               to be formatted and inserted in the resulting string.
- */
-#define NRFX_LOG_WARNING(format, ...)
-
-/**
- * @brief Macro for logging a message with the severity level INFO.
- *
- * @param format printf-style format string, optionally followed by arguments
- *               to be formatted and inserted in the resulting string.
- */
-#define NRFX_LOG_INFO(format, ...)
-
-/**
- * @brief Macro for logging a message with the severity level DEBUG.
- *
- * @param format printf-style format string, optionally followed by arguments
- *               to be formatted and inserted in the resulting string.
- */
-#define NRFX_LOG_DEBUG(format, ...)
-
-
-/**
- * @brief Macro for logging a memory dump with the severity level ERROR.
- *
- * @param[in] p_memory Pointer to the memory region to be dumped.
- * @param[in] length   Length of the memory region in bytes.
- */
-#define NRFX_LOG_HEXDUMP_ERROR(p_memory, length)
-
-/**
- * @brief Macro for logging a memory dump with the severity level WARNING.
- *
- * @param[in] p_memory Pointer to the memory region to be dumped.
- * @param[in] length   Length of the memory region in bytes.
- */
-#define NRFX_LOG_HEXDUMP_WARNING(p_memory, length)
-
-/**
- * @brief Macro for logging a memory dump with the severity level INFO.
- *
- * @param[in] p_memory Pointer to the memory region to be dumped.
- * @param[in] length   Length of the memory region in bytes.
- */
-#define NRFX_LOG_HEXDUMP_INFO(p_memory, length)
-
-/**
- * @brief Macro for logging a memory dump with the severity level DEBUG.
- *
- * @param[in] p_memory Pointer to the memory region to be dumped.
- * @param[in] length   Length of the memory region in bytes.
- */
-#define NRFX_LOG_HEXDUMP_DEBUG(p_memory, length)
-
-
-/**
- * @brief Macro for getting the textual representation of a given error code.
- *
- * @param[in] error_code Error code.
- *
- * @return String containing the textual representation of the error code.
- */
-#define NRFX_LOG_ERROR_STRING_GET(error_code)
-
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // NRFX_LOG_H__
diff --git a/tinyusb/hw/mcu/sony/cxd56/mkspk/.gitignore b/tinyusb/hw/mcu/sony/cxd56/mkspk/.gitignore
deleted file mode 100755
index 4c3d12e3..00000000
--- a/tinyusb/hw/mcu/sony/cxd56/mkspk/.gitignore
+++ /dev/null
@@ -1,2 +0,0 @@
-/mkspk
-/mkspk.exe
diff --git a/tinyusb/hw/mcu/sony/cxd56/mkspk/Makefile b/tinyusb/hw/mcu/sony/cxd56/mkspk/Makefile
deleted file mode 100755
index d91d17a3..00000000
--- a/tinyusb/hw/mcu/sony/cxd56/mkspk/Makefile
+++ /dev/null
@@ -1,51 +0,0 @@
-############################################################################
-# tools/mkspk/Makefile
-#
-#   Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
-#   Author: Gregory Nutt <gnutt@nuttx.org>
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions
-# are met:
-#
-# 1. Redistributions of source code must retain the above copyright
-#    notice, this list of conditions and the following disclaimer.
-# 2. Redistributions in binary form must reproduce the above copyright
-#    notice, this list of conditions and the following disclaimer in
-#    the documentation and/or other materials provided with the
-#    distribution.
-# 3. Neither the name NuttX nor the names of its contributors may be
-#    used to endorse or promote products derived from this software
-#    without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
-# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
-# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-# POSSIBILITY OF SUCH DAMAGE.
-#
-############################################################################
-
-all: mkspk
-default: mkspk
-.PHONY: clean
-
-# Add CFLAGS=-g on the make command line to build debug versions
-
-CFLAGS = -O2 -Wall -I.
-
-# mkspk - Convert nuttx.hex image to nuttx.spk image
-
-mkspk:
-	@gcc $(CFLAGS) -o mkspk mkspk.c clefia.c
-
-clean:
-	@rm -f *.o *.a *.dSYM *~ .*.swp
-	@rm -f mkspk mkspk.exe
diff --git a/tinyusb/hw/mcu/sony/cxd56/mkspk/clefia.c b/tinyusb/hw/mcu/sony/cxd56/mkspk/clefia.c
deleted file mode 100755
index 02a17550..00000000
--- a/tinyusb/hw/mcu/sony/cxd56/mkspk/clefia.c
+++ /dev/null
@@ -1,517 +0,0 @@
-/****************************************************************************
- * tools/cxd56/clefia.c
- *
- * Copyright (C) 2007, 2008 Sony Corporation
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <stdint.h>
-#include <assert.h>
-
-#include "clefia.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#define clefiamul4(_x) (clefiamul2(clefiamul2((_x))))
-#define clefiamul6(_x) (clefiamul2((_x)) ^ clefiamul4((_x)))
-#define clefiamul8(_x) (clefiamul2(clefiamul4((_x))))
-#define clefiamula(_x) (clefiamul2((_x)) ^ clefiamul8((_x)))
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/* S0 (8-bit S-box based on four 4-bit S-boxes) */
-
-static const unsigned char clefia_s0[256] =
-{
-  0x57u, 0x49u, 0xd1u, 0xc6u, 0x2fu, 0x33u, 0x74u, 0xfbu,
-  0x95u, 0x6du, 0x82u, 0xeau, 0x0eu, 0xb0u, 0xa8u, 0x1cu,
-  0x28u, 0xd0u, 0x4bu, 0x92u, 0x5cu, 0xeeu, 0x85u, 0xb1u,
-  0xc4u, 0x0au, 0x76u, 0x3du, 0x63u, 0xf9u, 0x17u, 0xafu,
-  0xbfu, 0xa1u, 0x19u, 0x65u, 0xf7u, 0x7au, 0x32u, 0x20u,
-  0x06u, 0xceu, 0xe4u, 0x83u, 0x9du, 0x5bu, 0x4cu, 0xd8u,
-  0x42u, 0x5du, 0x2eu, 0xe8u, 0xd4u, 0x9bu, 0x0fu, 0x13u,
-  0x3cu, 0x89u, 0x67u, 0xc0u, 0x71u, 0xaau, 0xb6u, 0xf5u,
-  0xa4u, 0xbeu, 0xfdu, 0x8cu, 0x12u, 0x00u, 0x97u, 0xdau,
-  0x78u, 0xe1u, 0xcfu, 0x6bu, 0x39u, 0x43u, 0x55u, 0x26u,
-  0x30u, 0x98u, 0xccu, 0xddu, 0xebu, 0x54u, 0xb3u, 0x8fu,
-  0x4eu, 0x16u, 0xfau, 0x22u, 0xa5u, 0x77u, 0x09u, 0x61u,
-  0xd6u, 0x2au, 0x53u, 0x37u, 0x45u, 0xc1u, 0x6cu, 0xaeu,
-  0xefu, 0x70u, 0x08u, 0x99u, 0x8bu, 0x1du, 0xf2u, 0xb4u,
-  0xe9u, 0xc7u, 0x9fu, 0x4au, 0x31u, 0x25u, 0xfeu, 0x7cu,
-  0xd3u, 0xa2u, 0xbdu, 0x56u, 0x14u, 0x88u, 0x60u, 0x0bu,
-  0xcdu, 0xe2u, 0x34u, 0x50u, 0x9eu, 0xdcu, 0x11u, 0x05u,
-  0x2bu, 0xb7u, 0xa9u, 0x48u, 0xffu, 0x66u, 0x8au, 0x73u,
-  0x03u, 0x75u, 0x86u, 0xf1u, 0x6au, 0xa7u, 0x40u, 0xc2u,
-  0xb9u, 0x2cu, 0xdbu, 0x1fu, 0x58u, 0x94u, 0x3eu, 0xedu,
-  0xfcu, 0x1bu, 0xa0u, 0x04u, 0xb8u, 0x8du, 0xe6u, 0x59u,
-  0x62u, 0x93u, 0x35u, 0x7eu, 0xcau, 0x21u, 0xdfu, 0x47u,
-  0x15u, 0xf3u, 0xbau, 0x7fu, 0xa6u, 0x69u, 0xc8u, 0x4du,
-  0x87u, 0x3bu, 0x9cu, 0x01u, 0xe0u, 0xdeu, 0x24u, 0x52u,
-  0x7bu, 0x0cu, 0x68u, 0x1eu, 0x80u, 0xb2u, 0x5au, 0xe7u,
-  0xadu, 0xd5u, 0x23u, 0xf4u, 0x46u, 0x3fu, 0x91u, 0xc9u,
-  0x6eu, 0x84u, 0x72u, 0xbbu, 0x0du, 0x18u, 0xd9u, 0x96u,
-  0xf0u, 0x5fu, 0x41u, 0xacu, 0x27u, 0xc5u, 0xe3u, 0x3au,
-  0x81u, 0x6fu, 0x07u, 0xa3u, 0x79u, 0xf6u, 0x2du, 0x38u,
-  0x1au, 0x44u, 0x5eu, 0xb5u, 0xd2u, 0xecu, 0xcbu, 0x90u,
-  0x9au, 0x36u, 0xe5u, 0x29u, 0xc3u, 0x4fu, 0xabu, 0x64u,
-  0x51u, 0xf8u, 0x10u, 0xd7u, 0xbcu, 0x02u, 0x7du, 0x8eu
-};
-
-/* S1 (8-bit S-box based on inverse function) */
-
-static const unsigned char clefia_s1[256] =
-{
-  0x6cu, 0xdau, 0xc3u, 0xe9u, 0x4eu, 0x9du, 0x0au, 0x3du,
-  0xb8u, 0x36u, 0xb4u, 0x38u, 0x13u, 0x34u, 0x0cu, 0xd9u,
-  0xbfu, 0x74u, 0x94u, 0x8fu, 0xb7u, 0x9cu, 0xe5u, 0xdcu,
-  0x9eu, 0x07u, 0x49u, 0x4fu, 0x98u, 0x2cu, 0xb0u, 0x93u,
-  0x12u, 0xebu, 0xcdu, 0xb3u, 0x92u, 0xe7u, 0x41u, 0x60u,
-  0xe3u, 0x21u, 0x27u, 0x3bu, 0xe6u, 0x19u, 0xd2u, 0x0eu,
-  0x91u, 0x11u, 0xc7u, 0x3fu, 0x2au, 0x8eu, 0xa1u, 0xbcu,
-  0x2bu, 0xc8u, 0xc5u, 0x0fu, 0x5bu, 0xf3u, 0x87u, 0x8bu,
-  0xfbu, 0xf5u, 0xdeu, 0x20u, 0xc6u, 0xa7u, 0x84u, 0xceu,
-  0xd8u, 0x65u, 0x51u, 0xc9u, 0xa4u, 0xefu, 0x43u, 0x53u,
-  0x25u, 0x5du, 0x9bu, 0x31u, 0xe8u, 0x3eu, 0x0du, 0xd7u,
-  0x80u, 0xffu, 0x69u, 0x8au, 0xbau, 0x0bu, 0x73u, 0x5cu,
-  0x6eu, 0x54u, 0x15u, 0x62u, 0xf6u, 0x35u, 0x30u, 0x52u,
-  0xa3u, 0x16u, 0xd3u, 0x28u, 0x32u, 0xfau, 0xaau, 0x5eu,
-  0xcfu, 0xeau, 0xedu, 0x78u, 0x33u, 0x58u, 0x09u, 0x7bu,
-  0x63u, 0xc0u, 0xc1u, 0x46u, 0x1eu, 0xdfu, 0xa9u, 0x99u,
-  0x55u, 0x04u, 0xc4u, 0x86u, 0x39u, 0x77u, 0x82u, 0xecu,
-  0x40u, 0x18u, 0x90u, 0x97u, 0x59u, 0xddu, 0x83u, 0x1fu,
-  0x9au, 0x37u, 0x06u, 0x24u, 0x64u, 0x7cu, 0xa5u, 0x56u,
-  0x48u, 0x08u, 0x85u, 0xd0u, 0x61u, 0x26u, 0xcau, 0x6fu,
-  0x7eu, 0x6au, 0xb6u, 0x71u, 0xa0u, 0x70u, 0x05u, 0xd1u,
-  0x45u, 0x8cu, 0x23u, 0x1cu, 0xf0u, 0xeeu, 0x89u, 0xadu,
-  0x7au, 0x4bu, 0xc2u, 0x2fu, 0xdbu, 0x5au, 0x4du, 0x76u,
-  0x67u, 0x17u, 0x2du, 0xf4u, 0xcbu, 0xb1u, 0x4au, 0xa8u,
-  0xb5u, 0x22u, 0x47u, 0x3au, 0xd5u, 0x10u, 0x4cu, 0x72u,
-  0xccu, 0x00u, 0xf9u, 0xe0u, 0xfdu, 0xe2u, 0xfeu, 0xaeu,
-  0xf8u, 0x5fu, 0xabu, 0xf1u, 0x1bu, 0x42u, 0x81u, 0xd6u,
-  0xbeu, 0x44u, 0x29u, 0xa6u, 0x57u, 0xb9u, 0xafu, 0xf2u,
-  0xd4u, 0x75u, 0x66u, 0xbbu, 0x68u, 0x9fu, 0x50u, 0x02u,
-  0x01u, 0x3cu, 0x7fu, 0x8du, 0x1au, 0x88u, 0xbdu, 0xacu,
-  0xf7u, 0xe4u, 0x79u, 0x96u, 0xa2u, 0xfcu, 0x6du, 0xb2u,
-  0x6bu, 0x03u, 0xe1u, 0x2eu, 0x7du, 0x14u, 0x95u, 0x1du
-};
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-static void bytecpy(unsigned char *dst, const unsigned char *src, int bytelen)
-{
-  while (bytelen-- > 0)
-    {
-      *dst++ = *src++;
-    }
-}
-
-static unsigned char clefiamul2(unsigned char x)
-{
-  /* multiplication over GF(2^8) (p(x) = '11d') */
-
-  if (x & 0x80u)
-    {
-      x ^= 0x0eu;
-    }
-
-  return ((x << 1) | (x >> 7));
-}
-
-static void clefiaf0xor(unsigned char *dst, const unsigned char *src,
-                        const unsigned char *rk)
-{
-  unsigned char x[4];
-  unsigned char y[4];
-  unsigned char z[4];
-
-  /* F0 */
-
-  /* Key addition */
-
-  bytexor(x, src, rk, 4);
-
-  /* Substitution layer */
-
-  z[0] = clefia_s0[x[0]];
-  z[1] = clefia_s1[x[1]];
-  z[2] = clefia_s0[x[2]];
-  z[3] = clefia_s1[x[3]];
-
-  /* Diffusion layer (M0) */
-
-  y[0] = z[0] ^ clefiamul2(z[1]) ^ clefiamul4(z[2]) ^ clefiamul6(z[3]);
-  y[1] = clefiamul2(z[0]) ^ z[1] ^ clefiamul6(z[2]) ^ clefiamul4(z[3]);
-  y[2] = clefiamul4(z[0]) ^ clefiamul6(z[1]) ^ z[2] ^ clefiamul2(z[3]);
-  y[3] = clefiamul6(z[0]) ^ clefiamul4(z[1]) ^ clefiamul2(z[2]) ^ z[3];
-
-  /* Xoring after F0 */
-
-  bytecpy(dst + 0, src + 0, 4);
-  bytexor(dst + 4, src + 4, y, 4);
-}
-
-static void clefiaf1xor(unsigned char *dst, const unsigned char *src,
-                        const unsigned char *rk)
-{
-  unsigned char x[4];
-  unsigned char y[4];
-  unsigned char z[4];
-
-  /* F1 */
-
-  /* Key addition */
-
-  bytexor(x, src, rk, 4);
-
-  /* Substitution layer */
-
-  z[0] = clefia_s1[x[0]];
-  z[1] = clefia_s0[x[1]];
-  z[2] = clefia_s1[x[2]];
-  z[3] = clefia_s0[x[3]];
-
-  /* Diffusion layer (M1) */
-
-  y[0] = z[0] ^ clefiamul8(z[1]) ^ clefiamul2(z[2]) ^ clefiamula(z[3]);
-  y[1] = clefiamul8(z[0]) ^ z[1] ^ clefiamula(z[2]) ^ clefiamul2(z[3]);
-  y[2] = clefiamul2(z[0]) ^ clefiamula(z[1]) ^ z[2] ^ clefiamul8(z[3]);
-  y[3] = clefiamula(z[0]) ^ clefiamul2(z[1]) ^ clefiamul8(z[2]) ^ z[3];
-
-  /* Xoring after F1 */
-
-  bytecpy(dst + 0, src + 0, 4);
-  bytexor(dst + 4, src + 4, y, 4);
-}
-
-static void clefiagfn4(unsigned char *y, const unsigned char *x,
-                       const unsigned char *rk, int r)
-{
-  unsigned char fin[16];
-  unsigned char fout[16];
-
-  bytecpy(fin, x, 16);
-  while (r-- > 0)
-    {
-      clefiaf0xor(fout + 0, fin + 0, rk + 0);
-      clefiaf1xor(fout + 8, fin + 8, rk + 4);
-      rk += 8;
-      if (r)
-        {
-          /* swapping for encryption */
-
-          bytecpy(fin + 0, fout + 4, 12);
-          bytecpy(fin + 12, fout + 0, 4);
-        }
-    }
-
-  bytecpy(y, fout, 16);
-}
-
-#if 0 /* Not used */
-static void clefiagfn8(unsigned char *y, const unsigned char *x,
-                       const unsigned char *rk, int r)
-{
-  unsigned char fin[32];
-  unsigned char fout[32];
-
-  bytecpy(fin, x, 32);
-  while (r-- > 0)
-    {
-      clefiaf0xor(fout + 0, fin + 0, rk + 0);
-      clefiaf1xor(fout + 8, fin + 8, rk + 4);
-      clefiaf0xor(fout + 16, fin + 16, rk + 8);
-      clefiaf1xor(fout + 24, fin + 24, rk + 12);
-      rk += 16;
-      if (r)
-        {
-          /* swapping for encryption */
-
-          bytecpy(fin + 0, fout + 4, 28);
-          bytecpy(fin + 28, fout + 0, 4);
-        }
-    }
-
-  bytecpy(y, fout, 32);
-}
-#endif
-
-#if 0 /* Not used */
-static void clefiagfn4inv(unsigned char *y, const unsigned char *x,
-                          const unsigned char *rk, int r)
-{
-  unsigned char fin[16];
-  unsigned char fout[16];
-
-  rk += (r - 1) * 8;
-  bytecpy(fin, x, 16);
-  while (r-- > 0)
-    {
-      clefiaf0xor(fout + 0, fin + 0, rk + 0);
-      clefiaf1xor(fout + 8, fin + 8, rk + 4);
-      rk -= 8;
-      if (r)
-        {
-          /* swapping for decryption */
-
-          bytecpy(fin + 0, fout + 12, 4);
-          bytecpy(fin + 4, fout + 0, 12);
-        }
-    }
-
-  bytecpy(y, fout, 16);
-}
-#endif
-
-static void clefiadoubleswap(unsigned char *lk)
-{
-  unsigned char t[16];
-
-  t[0] = (lk[0] << 7) | (lk[1] >> 1);
-  t[1] = (lk[1] << 7) | (lk[2] >> 1);
-  t[2] = (lk[2] << 7) | (lk[3] >> 1);
-  t[3] = (lk[3] << 7) | (lk[4] >> 1);
-  t[4] = (lk[4] << 7) | (lk[5] >> 1);
-  t[5] = (lk[5] << 7) | (lk[6] >> 1);
-  t[6] = (lk[6] << 7) | (lk[7] >> 1);
-  t[7] = (lk[7] << 7) | (lk[15] & 0x7fu);
-
-  t[8] = (lk[8] >> 7) | (lk[0] & 0xfeu);
-  t[9] = (lk[9] >> 7) | (lk[8] << 1);
-  t[10] = (lk[10] >> 7) | (lk[9] << 1);
-  t[11] = (lk[11] >> 7) | (lk[10] << 1);
-  t[12] = (lk[12] >> 7) | (lk[11] << 1);
-  t[13] = (lk[13] >> 7) | (lk[12] << 1);
-  t[14] = (lk[14] >> 7) | (lk[13] << 1);
-  t[15] = (lk[15] >> 7) | (lk[14] << 1);
-
-  bytecpy(lk, t, 16);
-}
-
-static void clefiaconset(unsigned char *con, const unsigned char *iv, int lk)
-{
-  unsigned char t[2];
-  unsigned char tmp;
-
-  bytecpy(t, iv, 2);
-  while (lk-- > 0)
-    {
-      con[0] = t[0] ^ 0xb7u;    /* P_16 = 0xb7e1 (natural logarithm) */
-      con[1] = t[1] ^ 0xe1u;
-      con[2] = ~((t[0] << 1) | (t[1] >> 7));
-      con[3] = ~((t[1] << 1) | (t[0] >> 7));
-      con[4] = ~t[0] ^ 0x24u;   /* Q_16 = 0x243f (circle ratio) */
-      con[5] = ~t[1] ^ 0x3fu;
-      con[6] = t[1];
-      con[7] = t[0];
-      con += 8;
-
-      /* updating T */
-
-      if (t[1] & 0x01u)
-        {
-          t[0] ^= 0xa8u;
-          t[1] ^= 0x30u;
-        }
-
-      tmp = t[0] << 7;
-      t[0] = (t[0] >> 1) | (t[1] << 7);
-      t[1] = (t[1] >> 1) | tmp;
-    }
-}
-
-static void left_shift_one(uint8_t * in, uint8_t * out)
-{
-  int i;
-  int overflow;
-
-  overflow = 0;
-  for (i = 15; i >= 0; i--)
-    {
-      out[i] = in[i] << 1;
-      out[i] |= overflow;
-      overflow = (in[i] >> 7) & 1;
-    }
-}
-
-static void gen_subkey(struct cipher *c)
-{
-  uint8_t L[16];
-
-  memset(L, 0, 16);
-  clefiaencrypt(L, L, c->rk, c->round);
-
-  left_shift_one(L, c->k1);
-  if (L[0] & 0x80)
-    {
-      c->k1[15] = c->k1[15] ^ 0x87;
-    }
-
-  left_shift_one(c->k1, c->k2);
-  if (c->k1[0] & 0x80)
-    {
-      c->k2[15] = c->k2[15] ^ 0x87;
-    }
-
-  memset(L, 0, 16);
-}
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-struct cipher *cipher_init(uint8_t * key, uint8_t * iv)
-{
-  struct cipher *c;
-
-  c = (struct cipher *)malloc(sizeof(*c));
-  if (!c)
-    {
-      return NULL;
-    }
-
-  c->round = clefiakeyset(c->rk, key);
-
-  gen_subkey(c);
-  memset(c->vector, 0, 16);
-
-  return c;
-}
-
-void cipher_deinit(struct cipher *c)
-{
-  memset(c, 0, sizeof(*c));
-  free(c);
-}
-
-int cipher_calc_cmac(struct cipher *c, void *data, int size, void *cmac)
-{
-  uint8_t m[16];
-  uint8_t *p;
-
-  if (size & 0xf)
-    {
-      return -1;
-    }
-
-  p = (uint8_t *) data;
-  while (size)
-    {
-      bytexor(m, c->vector, p, 16);
-      clefiaencrypt(c->vector, m, c->rk, c->round);
-      size -= 16;
-      p += 16;
-    }
-
-  bytexor(cmac, m, c->k1, 16);
-  clefiaencrypt(cmac, cmac, c->rk, c->round);
-  memset(m, 0, 16);
-
-  return 0;
-}
-
-void bytexor(unsigned char *dst, const unsigned char *a,
-             const unsigned char *b, int bytelen)
-{
-  while (bytelen-- > 0)
-    {
-      *dst++ = *a++ ^ *b++;
-    }
-}
-
-int clefiakeyset(unsigned char *rk, const unsigned char *skey)
-{
-  const unsigned char iv[2] =
-  {
-    0x42u, 0x8au  /* cubic root of 2 */
-  };
-
-  unsigned char lk[16];
-  unsigned char con128[4 * 60];
-  int i;
-
-  /* generating CONi^(128) (0 <= i < 60, lk = 30) */
-
-  clefiaconset(con128, iv, 30);
-
-  /* GFN_{4,12} (generating L from K) */
-
-  clefiagfn4(lk, skey, con128, 12);
-
-  bytecpy(rk, skey, 8);    /* initial whitening key (WK0, WK1) */
-  rk += 8;
-  for (i = 0; i < 9; i++)
-    {
-      /* round key (RKi (0 <= i < 36)) */
-
-      bytexor(rk, lk, con128 + i * 16 + (4 * 24), 16);
-      if (i % 2)
-        {
-          bytexor(rk, rk, skey, 16);    /* Xoring K */
-        }
-
-      clefiadoubleswap(lk);     /* Updating L (DoubleSwap function) */
-      rk += 16;
-    }
-
-  bytecpy(rk, skey + 8, 8);     /* final whitening key (WK2, WK3) */
-
-  return 18;
-}
-
-void clefiaencrypt(unsigned char *ct, const unsigned char *pt,
-                   const unsigned char *rk, const int r)
-{
-  unsigned char rin[16];
-  unsigned char  rout[16];
-
-  bytecpy(rin, pt, 16);
-
-  bytexor(rin + 4, rin + 4, rk + 0, 4); /* initial key whitening */
-  bytexor(rin + 12, rin + 12, rk + 4, 4);
-  rk += 8;
-
-  clefiagfn4(rout, rin, rk, r); /* GFN_{4,r} */
-
-  bytecpy(ct, rout, 16);
-  bytexor(ct + 4, ct + 4, rk + r * 8 + 0, 4);   /* final key whitening */
-  bytexor(ct + 12, ct + 12, rk + r * 8 + 4, 4);
-}
diff --git a/tinyusb/hw/mcu/sony/cxd56/mkspk/clefia.h b/tinyusb/hw/mcu/sony/cxd56/mkspk/clefia.h
deleted file mode 100755
index a0e02587..00000000
--- a/tinyusb/hw/mcu/sony/cxd56/mkspk/clefia.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/****************************************************************************
- * tools/cxd56/clefia.h
- *
- * Copyright (C) 2007, 2008 Sony Corporation
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *****************************************************************************/
-
-#ifndef _TOOLS_CXD56_CLEFIA_H_
-#define _TOOLS_CXD56_CLEFIA_H_
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-struct cipher
-  {
-    int mode;
-    int dir;
-    uint8_t rk[8 * 26 + 16];
-    uint8_t vector[16];
-    int round;
-    uint8_t k1[16];
-    uint8_t k2[16];
-  };
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-struct cipher *cipher_init(uint8_t * key, uint8_t * iv);
-void cipher_deinit(struct cipher *c);
-int cipher_calc_cmac(struct cipher *c, void *data, int size, void *cmac);
-void bytexor(unsigned char *dst, const unsigned char *a,
-             const unsigned char *b, int bytelen);
-int clefiakeyset(unsigned char *rk, const unsigned char *skey);
-void clefiaencrypt(unsigned char *ct, const unsigned char *pt,
-                   const unsigned char *rk, const int r);
-
-#endif
diff --git a/tinyusb/hw/mcu/sony/cxd56/mkspk/elf32.h b/tinyusb/hw/mcu/sony/cxd56/mkspk/elf32.h
deleted file mode 100755
index 94a9c81b..00000000
--- a/tinyusb/hw/mcu/sony/cxd56/mkspk/elf32.h
+++ /dev/null
@@ -1,175 +0,0 @@
-/****************************************************************************
- * include/elf32.h
- *
- *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Reference: System V Application Binary Interface, Edition 4.1, March 18,
- * 1997, The Santa Cruz Operation, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-#ifndef __INCLUDE_ELF32_H
-#define __INCLUDE_ELF32_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <stdint.h>
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#define EI_NIDENT          16     /* Size of e_ident[] */
-
-#define ELF32_ST_BIND(i)   ((i) >> 4)
-#define ELF32_ST_TYPE(i)   ((i) & 0xf)
-#define ELF32_ST_INFO(b,t) (((b) << 4) | ((t) & 0xf))
-
-/* Definitions for Elf32_Rel*::r_info */
-
-#define ELF32_R_SYM(i)    ((i) >> 8)
-#define ELF32_R_TYPE(i)   ((i) & 0xff)
-#define ELF32_R_INFO(s,t) (((s)<< 8) | ((t) & 0xff))
-
-#define ELF_R_SYM(i)      ELF32_R_SYM(i)
-
-/****************************************************************************
- * Public Type Definitions
- ****************************************************************************/
-
-/* Figure 4.2: 32-Bit Data Types */
-
-typedef uint32_t  Elf32_Addr;  /* Unsigned program address */
-typedef uint16_t  Elf32_Half;  /* Unsigned medium integer */
-typedef uint32_t  Elf32_Off;   /* Unsigned file offset */
-typedef int32_t   Elf32_Sword; /* Signed large integer */
-typedef uint32_t  Elf32_Word;  /* Unsigned large integer */
-
-/* Figure 4-3: ELF Header */
-
-typedef struct
-{
-  unsigned char e_ident[EI_NIDENT];
-  Elf32_Half    e_type;
-  Elf32_Half    e_machine;
-  Elf32_Word    e_version;
-  Elf32_Addr    e_entry;
-  Elf32_Off     e_phoff;
-  Elf32_Off     e_shoff;
-  Elf32_Word    e_flags;
-  Elf32_Half    e_ehsize;
-  Elf32_Half    e_phentsize;
-  Elf32_Half    e_phnum;
-  Elf32_Half    e_shentsize;
-  Elf32_Half    e_shnum;
-  Elf32_Half    e_shstrndx;
-} Elf32_Ehdr;
-
-/* Figure 4-8: Section Header */
-
-typedef struct
-{
-  Elf32_Word    sh_name;
-  Elf32_Word    sh_type;
-  Elf32_Word    sh_flags;
-  Elf32_Addr    sh_addr;
-  Elf32_Off     sh_offset;
-  Elf32_Word    sh_size;
-  Elf32_Word    sh_link;
-  Elf32_Word    sh_info;
-  Elf32_Word    sh_addralign;
-  Elf32_Word    sh_entsize;
-} Elf32_Shdr;
-
-/* Figure 4-15: Symbol Table Entry */
-
-typedef struct
-{
-  Elf32_Word    st_name;
-  Elf32_Addr    st_value;
-  Elf32_Word    st_size;
-  unsigned char st_info;
-  unsigned char st_other;
-  Elf32_Half    st_shndx;
-} Elf32_Sym;
-
-/* Figure 4-19: Relocation Entries */
-
-typedef struct
-{
-  Elf32_Addr   r_offset;
-  Elf32_Word   r_info;
-} Elf32_Rel;
-
-typedef struct
-{
-  Elf32_Addr   r_offset;
-  Elf32_Word   r_info;
-  Elf32_Sword  r_addend;
-} Elf32_Rela;
-
-/* Figure 5-1: Program Header */
-
-typedef struct
-{
-  Elf32_Word   p_type;
-  Elf32_Off    p_offset;
-  Elf32_Addr   p_vaddr;
-  Elf32_Addr   p_paddr;
-  Elf32_Word   p_filesz;
-  Elf32_Word   p_memsz;
-  Elf32_Word   p_flags;
-  Elf32_Word   p_align;
-} Elf32_Phdr;
-
-/* Figure 5-9: Dynamic Structure */
-
-typedef struct
-{
-  Elf32_Sword  d_tag;
-  union
-  {
-    Elf32_Word d_val;
-    Elf32_Addr d_ptr;
-  } d_un;
-} Elf32_Dyn;
-
-typedef Elf32_Addr  Elf_Addr;
-typedef Elf32_Ehdr  Elf_Ehdr;
-typedef Elf32_Rel   Elf_Rel;
-typedef Elf32_Rela  Elf_Rela;
-typedef Elf32_Sym   Elf_Sym;
-typedef Elf32_Shdr  Elf_Shdr;
-typedef Elf32_Word  Elf_Word;
-
-#endif /* __INCLUDE_ELF32_H */
diff --git a/tinyusb/hw/mcu/sony/cxd56/mkspk/mkspk.c b/tinyusb/hw/mcu/sony/cxd56/mkspk/mkspk.c
deleted file mode 100755
index c447ad7d..00000000
--- a/tinyusb/hw/mcu/sony/cxd56/mkspk/mkspk.c
+++ /dev/null
@@ -1,383 +0,0 @@
-/****************************************************************************
- * tools/cxd56/mkspk.c
- *
- * Copyright (C) 2007, 2008 Sony Corporation
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-#include <stdint.h>
-#include <stdbool.h>
-#include <assert.h>
-
-#include "mkspk.h"
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-struct args
-{
-  int core;
-  char *elffile;
-  char *savename;
-  char *outputfile;
-};
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-static uint8_t vmk[16] =
-  "\x27\xc0\xaf\x1b\x5d\xcb\xc6\xc5\x58\x22\x1c\xdd\xaf\xf3\x20\x21";
-
-static struct args g_options =
-{
-  0
-};
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-static struct args *parse_args(int argc, char **argv)
-{
-  int opt;
-  int show_help;
-  struct args *args = &g_options;
-  char *endp;
-
-  show_help = 0;
-
-  if (argc < 2)
-    {
-      show_help = 1;
-    }
-
-  memset(args, 0, sizeof(*args));
-  args->core = -1;
-
-  while ((opt = getopt(argc, argv, "h:c:")) != -1)
-    {
-      switch (opt)
-        {
-        case 'c':
-          args->core = strtol(optarg, &endp, 0);
-          if (*endp)
-            {
-              fprintf(stderr, "Invalid core number \"%s\"\n", optarg);
-              show_help = 1;
-            }
-          break;
-
-        case 'h':
-        default:
-          show_help = 1;
-        }
-    }
-
-  argc -= optind;
-  argv += optind;
-
-  args->elffile = argv[0];
-  args->savename = argv[1];
-  argc -= 2;
-  argv += 2;
-
-  if (argc > 0)
-    {
-      args->outputfile = strdup(argv[0]);
-    }
-  else
-    {
-      show_help = 1;
-    }
-
-  /* Sanity checks for options */
-
-  if (show_help == 1)
-    {
-      fprintf(stderr,
-              "mkspk [-c <number>] <filename> <save name> [<output file>]\n");
-      exit(EXIT_FAILURE);
-    }
-
-  if (args->core < 0)
-    {
-      fprintf(stderr, "Core number is not set. Please use -c option.\n");
-      exit(EXIT_FAILURE);
-    }
-
-  if (strlen(args->savename) > 63)
-    {
-      fprintf(stderr, "savename too long.\n");
-      exit(EXIT_FAILURE);
-    }
-
-  return args;
-}
-
-static struct elf_file *load_elf(const char *filename)
-{
-  size_t fsize;
-  int pos;
-  char *buf;
-  FILE *fp;
-  struct elf_file *ef;
-  Elf32_Shdr *sh;
-  uint16_t i;
-  int ret;
-
-  fp = fopen(filename, "rb");
-  if (!fp)
-    {
-      return NULL;
-    }
-
-  ef = (struct elf_file *)malloc(sizeof(*ef));
-  if (!ef)
-    {
-      return NULL;
-    }
-
-  pos = fseek(fp, 0, SEEK_END);
-  fsize = (size_t) ftell(fp);
-  fseek(fp, pos, SEEK_SET);
-
-  buf = (char *)malloc(fsize);
-  if (!buf)
-    {
-      return NULL;
-    }
-
-  ret = fread(buf, fsize, 1, fp);
-  fclose(fp);
-  if (ret != 1)
-    {
-      return NULL;
-    }
-
-  ef->data = buf;
-
-  ef->ehdr = (Elf32_Ehdr *) buf;
-
-  Elf32_Ehdr *h = (Elf32_Ehdr *) buf;
-
-  if (!(h->e_ident[EI_MAG0] == 0x7f &&
-        h->e_ident[EI_MAG1] == 'E' &&
-        h->e_ident[EI_MAG2] == 'L' && h->e_ident[EI_MAG3] == 'F'))
-    {
-      free(ef);
-      free(buf);
-      return NULL;
-    }
-
-  ef->phdr = (Elf32_Phdr *) (buf + ef->ehdr->e_phoff);
-  ef->shdr = (Elf32_Shdr *) (buf + ef->ehdr->e_shoff);
-  ef->shstring = buf + ef->shdr[ef->ehdr->e_shstrndx].sh_offset;
-
-  for (i = 0, sh = ef->shdr; i < ef->ehdr->e_shnum; i++, sh++)
-    {
-      if (sh->sh_type == SHT_SYMTAB)
-        {
-          ef->symtab = (Elf32_Sym *) (buf + sh->sh_offset);
-          ef->nsyms = sh->sh_size / sh->sh_entsize;
-          continue;
-        }
-
-      if (sh->sh_type == SHT_STRTAB)
-        {
-          if (!strcmp(".strtab", ef->shstring + sh->sh_name))
-            {
-              ef->string = buf + sh->sh_offset;
-            }
-        }
-    }
-
-  return ef;
-}
-
-static void *create_image(struct elf_file *elf, int core, char *savename,
-                         int *image_size)
-{
-  char *img;
-  struct spk_header *header;
-  struct spk_prog_info *pi;
-  Elf32_Phdr *ph;
-  Elf32_Sym *sym;
-  char *name;
-  int snlen;
-  int nphs, psize, imgsize;
-  int i;
-  int j;
-  uint32_t offset;
-  uint32_t sp;
-
-  snlen = alignup(strlen(savename) + 1, 16);
-
-  nphs = 0;
-  psize = 0;
-  for (i = 0, ph = elf->phdr; i < elf->ehdr->e_phnum; i++, ph++)
-    {
-      if (ph->p_type != PT_LOAD || ph->p_filesz == 0)
-        {
-          continue;
-        }
-
-      nphs++;
-      psize += alignup(ph->p_filesz, 16);
-    }
-
-  imgsize = sizeof(*header) + snlen + (nphs * 16) + psize;
-
-  img = (char *)malloc(imgsize + 32);
-  if (!img)
-    {
-      return NULL;
-    }
-
-  *image_size = imgsize;
-  sym = elf->symtab;
-  name = elf->string;
-  sp = 0;
-
-  for (j = 0; j < elf->nsyms; j++, sym++)
-    {
-      if (!strcmp("__stack", name + sym->st_name))
-        {
-          sp = sym->st_value;
-        }
-    }
-
-  memset(img, 0, imgsize);
-
-  header = (struct spk_header *)img;
-  header->magic[0] = 0xef;
-  header->magic[1] = 'M';
-  header->magic[2] = 'O';
-  header->magic[3] = 'D';
-  header->cpu = core;
-
-  header->entry = elf->ehdr->e_entry;
-  header->stack = sp;
-  header->core = core;
-
-  header->binaries = nphs;
-  header->phoffs = sizeof(*header) + snlen;
-  header->mode = 0777;
-
-  strncpy(img + sizeof(*header), savename, 63);
-
-  ph = elf->phdr;
-  pi = (struct spk_prog_info *)(img + header->phoffs);
-  offset = ((char *)pi - img) + (nphs * sizeof(*pi));
-  for (i = 0; i < elf->ehdr->e_phnum; i++, ph++)
-    {
-      if (ph->p_type != PT_LOAD || ph->p_filesz == 0)
-        continue;
-      pi->load_address = ph->p_paddr;
-      pi->offset = offset;
-      pi->size = alignup(ph->p_filesz, 16);     /* need 16 bytes align for
-                                                 * decryption */
-      pi->memsize = ph->p_memsz;
-
-      memcpy(img + pi->offset, elf->data + ph->p_offset, ph->p_filesz);
-
-      offset += alignup(ph->p_filesz, 16);
-      pi++;
-    }
-
-  return img;
-}
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-int main(int argc, char **argv)
-{
-  struct args *args;
-  struct elf_file *elf;
-  struct cipher *c;
-  uint8_t *spkimage;
-  int size = 0;
-  FILE *fp;
-  char footer[16];
-
-  args = parse_args(argc, argv);
-
-  elf = load_elf(args->elffile);
-  if (!elf)
-    {
-      fprintf(stderr, "Loading ELF %s failure.\n", args->elffile);
-      exit(EXIT_FAILURE);
-    }
-
-  spkimage = create_image(elf, args->core, args->savename, &size);
-  free(elf);
-
-  c = cipher_init(vmk, NULL);
-  cipher_calc_cmac(c, spkimage, size, (uint8_t *) spkimage + size);
-  cipher_deinit(c);
-
-  size += 16;                   /* Extend CMAC size */
-
-  snprintf(footer, 16, "MKSPK_BN_HOOTER");
-  footer[15] = '\0';
-
-  fp = fopen(args->outputfile, "wb");
-  if (!fp)
-    {
-      fprintf(stderr, "Output file open error.\n");
-      free(spkimage);
-      exit(EXIT_FAILURE);
-    }
-
-  fwrite(spkimage, size, 1, fp);
-  fwrite(footer, 16, 1, fp);
-
-  fclose(fp);
-
-  printf("File %s is successfully created.\n", args->outputfile);
-  free(args->outputfile);
-
-  memset(spkimage, 0, size);
-  free(spkimage);
-
-  exit(EXIT_SUCCESS);
-}
diff --git a/tinyusb/hw/mcu/sony/cxd56/mkspk/mkspk.h b/tinyusb/hw/mcu/sony/cxd56/mkspk/mkspk.h
deleted file mode 100755
index 5c1b979c..00000000
--- a/tinyusb/hw/mcu/sony/cxd56/mkspk/mkspk.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/****************************************************************************
- * tools/cxd56/mkspk.h
- *
- * Copyright (C) 2007, 2008 Sony Corporation
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "clefia.h"
-#include "elf32.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#define EI_MAG0            0      /* File identification */
-#define EI_MAG1            1
-#define EI_MAG2            2
-#define EI_MAG3            3
-
-#define SHT_SYMTAB         2
-#define SHT_STRTAB         3
-
-#define PT_LOAD            1
-
-#define alignup(x, a) (((x) + ((a) - 1)) & ~((a) - 1))
-#define swap(a, b) { (a) ^= (b); (b) ^= (a); (a) ^= (b); }
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-struct spk_header
-  {
-    uint8_t magic[4];
-    uint8_t cpu;
-    uint8_t reserved[11];
-    uint32_t entry;
-    uint32_t stack;
-    uint16_t core;
-    uint16_t binaries;
-    uint16_t phoffs;
-    uint16_t mode;
-  };
-
-struct spk_prog_info
-  {
-    uint32_t load_address;
-    uint32_t offset;
-    uint32_t size;
-    uint32_t memsize;
-  };
-
-struct elf_file
-  {
-    Elf32_Ehdr *ehdr;
-    Elf32_Phdr *phdr;
-    Elf32_Shdr *shdr;
-    Elf32_Sym *symtab;
-    int nsyms;
-    char *shstring;
-    char *string;
-    char *data;
-  };
diff --git a/tinyusb/hw/mcu/sony/cxd56/tools/__pycache__/xmodem.cpython-36.pyc b/tinyusb/hw/mcu/sony/cxd56/tools/__pycache__/xmodem.cpython-36.pyc
deleted file mode 100755
index cfa917f7..00000000
--- a/tinyusb/hw/mcu/sony/cxd56/tools/__pycache__/xmodem.cpython-36.pyc
+++ /dev/null
diff --git a/tinyusb/hw/mcu/sony/cxd56/tools/flash_writer.py b/tinyusb/hw/mcu/sony/cxd56/tools/flash_writer.py
deleted file mode 100755
index 840f10c3..00000000
--- a/tinyusb/hw/mcu/sony/cxd56/tools/flash_writer.py
+++ /dev/null
@@ -1,580 +0,0 @@
-#! /usr/bin/env python3
-
-# Copyright (C) 2018 Sony Semiconductor Solutions Corp.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions
-# are met:
-#
-# 1. Redistributions of source code must retain the above copyright
-#    notice, this list of conditions and the following disclaimer.
-# 2. Redistributions in binary form must reproduce the above copyright
-#    notice, this list of conditions and the following disclaimer in
-#    the documentation and/or other materials provided with the
-#    distribution.
-# 3. Neither the name NuttX nor the names of its contributors may be
-#    used to endorse or promote products derived from this software
-#    without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
-# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
-# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-# POSSIBILITY OF SUCH DAMAGE.
-#
-
-import time
-import sys
-import os
-import struct
-import glob
-import fnmatch
-import errno
-import telnetlib
-import argparse
-import shutil
-import subprocess
-import re
-import xmodem
-
-import_serial_module = True
-
-# When SDK release, plase set SDK_RELEASE as True.
-SDK_RELEASE = False
-
-if SDK_RELEASE :
-	PRINT_RAW_COMMAND = False
-	REBOOT_AT_END = True
-else :
-	PRINT_RAW_COMMAND = True
-	REBOOT_AT_END = True
-
-try:
-	import serial
-except:
-	import_serial_module = False
-
-# supported environment various
-# CXD56_PORT
-# CXD56_TELNETSRV_PORT
-# CXD56_TELNETSRV_IP
-
-PROTOCOL_SERIAL = 0
-PROTOCOL_TELNET = 1
-
-MAX_DOT_COUNT = 70
-
-# configure parameters and default value
-class ConfigArgs:
-	PROTOCOL_TYPE = None
-	SERIAL_PORT = "COM1"
-	SERVER_PORT = 4569
-	SERVER_IP = "localhost"
-	EOL = bytes([10])
-	WAIT_RESET = True
-	AUTO_RESET = False
-	DTR_RESET = False
-	XMODEM_BAUD = 0
-	NO_SET_BOOTABLE = False
-	PACKAGE_NAME = []
-	FILE_NAME = []
-	ERASE_NAME = []
-	PKGSYS_NAME = []
-	PKGAPP_NAME = []
-	PKGUPD_NAME = []
-
-ROM_MSG = [b"Welcome to nash"]
-XMDM_MSG = "Waiting for XMODEM (CRC or 1K) transfer. Ctrl-X to cancel."
-
-class ConfigArgsLoader():
-	def __init__(self):
-		self.parser = argparse.ArgumentParser(formatter_class=argparse.RawTextHelpFormatter)
-		self.parser.add_argument("package_name", help="the name of the package to install", nargs='*')
-		self.parser.add_argument("-f", "--file", dest="file_name", help="save file", action='append')
-		self.parser.add_argument("-e", "--erase", dest="erase_name", help="erase file", action='append')
-
-		self.parser.add_argument("-S", "--sys", dest="pkgsys_name", help="the name of the system package to install", action='append')
-		self.parser.add_argument("-A", "--app", dest="pkgapp_name", help="the name of the application package to install", action='append')
-		self.parser.add_argument("-U", "--upd", dest="pkgupd_name", help="the name of the updater package to install", action='append')
-
-		self.parser.add_argument("-a", "--auto-reset", dest="auto_reset",
-									action="store_true", default=None,
-									help="try to auto reset develop board if possible")
-		self.parser.add_argument("-d", "--dtr-reset", dest="dtr_reset",
-									action="store_true", default=None,
-									help="try to auto reset develop board if possible")
-		self.parser.add_argument("-n", "--no-set-bootable", dest="no_set_bootable",
-									action="store_true", default=None,
-									help="not to set bootable")
-
-		group = self.parser.add_argument_group()
-		group.add_argument("-i", "--server-ip", dest="server_ip",
-						   help="the ip address connected to the telnet server")
-		group.add_argument("-p", "--server-port", dest="server_port", type=int,
-						   help="the port connected to the telnet server")
-
-		group = self.parser.add_argument_group()
-		group.add_argument("-c", "--serial-port", dest="serial_port", help="the serial port")
-		group.add_argument("-b", "--xmodem-baudrate", dest="xmodem_baud", help="Use the faster baudrate in xmodem")
-
-		mutually_group = self.parser.add_mutually_exclusive_group()
-		mutually_group.add_argument("-t", "--telnet-protocol", dest="telnet_protocol",
-									action="store_true", default=None,
-									help="use the telnet protocol for binary transmission")
-		mutually_group.add_argument("-s", "--serial-protocol", dest="serial_protocol",
-									action="store_true", default=None,
-									help="use the serial port for binary transmission, default options")
-
-		mutually_group2 = self.parser.add_mutually_exclusive_group()
-		mutually_group2.add_argument("-F", "--force-wait-reset", dest="wait_reset",
-									action="store_true", default=None,
-									help="force wait for pressing RESET button")
-		mutually_group2.add_argument("-N", "--no-wait-reset", dest="wait_reset",
-									action="store_false", default=None,
-									help="if possible, skip to wait for pressing RESET button")
-
-	def update_config(self):
-		args = self.parser.parse_args()
-
-		ConfigArgs.PACKAGE_NAME = args.package_name
-		ConfigArgs.FILE_NAME = args.file_name
-		ConfigArgs.ERASE_NAME = args.erase_name
-		ConfigArgs.PKGSYS_NAME = args.pkgsys_name
-		ConfigArgs.PKGAPP_NAME = args.pkgapp_name
-		ConfigArgs.PKGUPD_NAME = args.pkgupd_name
-
-		# Get serial port or telnet server ip etc
-		if args.serial_protocol == True:
-			ConfigArgs.PROTOCOL_TYPE = PROTOCOL_SERIAL
-		elif args.telnet_protocol == True:
-			ConfigArgs.PROTOCOL_TYPE = PROTOCOL_TELNET
-
-		if ConfigArgs.PROTOCOL_TYPE == None:
-			proto = os.environ.get("CXD56_PROTOCOL")
-			if proto is not None:
-				if 's' in proto:
-					ConfigArgs.PROTOCOL_TYPE = PROTOCOL_SERIAL
-				elif 't' in proto:
-					ConfigArgs.PROTOCOL_TYPE = PROTOCOL_TELNET
-
-		if ConfigArgs.PROTOCOL_TYPE == None:
-			ConfigArgs.PROTOCOL_TYPE = PROTOCOL_SERIAL
-
-		if ConfigArgs.PROTOCOL_TYPE == PROTOCOL_SERIAL:
-			if args.serial_port is not None:
-				ConfigArgs.SERIAL_PORT = args.serial_port
-			else:
-				# Get serial port from the environment
-				port = os.environ.get("CXD56_PORT")
-				if port is not None:
-					ConfigArgs.SERIAL_PORT = port
-				else:
-					print("CXD56_PORT is not set, Use " + ConfigArgs.SERIAL_PORT + ".")
-		else:
-			ConfigArgs.PROTOCOL_TYPE = PROTOCOL_TELNET
-			if args.server_port is not None:
-				ConfigArgs.SERVER_PORT = args.server_port
-			else:
-				port = os.environ.get("CXD56_TELNETSRV_PORT")
-				if port is not None:
-					ConfigArgs.SERVER_PORT = port
-				else:
-					print("CXD56_TELNETSRV_PORT is not set, Use " + str(ConfigArgs.SERVER_PORT) + ".")
-			if args.server_ip is not None:
-				ConfigArgs.SERVER_IP = args.server_ip
-			else:
-				ip = os.environ.get("CXD56_TELNETSRV_IP")
-				if ip is not None:
-					ConfigArgs.SERVER_IP = ip
-				else:
-					print("CXD56_TELNETSRV_IP is not set, Use " + ConfigArgs.SERVER_IP + ".")
-
-		if args.xmodem_baud is not None:
-			ConfigArgs.XMODEM_BAUD = args.xmodem_baud
-
-		if args.auto_reset is not None:
-			ConfigArgs.AUTO_RESET = args.auto_reset
-
-		if args.dtr_reset is not None:
-			ConfigArgs.DTR_RESET = args.dtr_reset
-
-		if args.no_set_bootable is not None:
-			ConfigArgs.NO_SET_BOOTABLE = args.no_set_bootable
-
-		if args.wait_reset is not None:
-			ConfigArgs.WAIT_RESET = args.wait_reset
-
-class TelnetDev:
-	def __init__(self):
-		srv_ipaddr = ConfigArgs.SERVER_IP
-		srv_port = ConfigArgs.SERVER_PORT
-		self.recvbuf = b'';
-		try:
-			self.telnet = telnetlib.Telnet(host=srv_ipaddr, port=srv_port, timeout=10)
-			# There is a ack to be sent after connecting to the telnet server.
-			self.telnet.write(b"\xff")
-		except Exception as e:
-			print("Cannot connect to the server %s:%d" % (srv_ipaddr, srv_port))
-			sys.exit(e.args[0])
-
-	def readline(self, size=None):
-		res = b''
-		ch = b''
-		while ch != ConfigArgs.EOL:
-			ch = self.getc_raw(1, timeout=0.1)
-			if ch == b'':
-				return res
-			res += ch
-		return res
-
-	def getc_raw(self, size, timeout=1):
-		res = b''
-		tm = time.monotonic()
-		while size > 0:
-			while self.recvbuf == b'':
-				self.recvbuf = self.telnet.read_eager()
-				if self.recvbuf == b'':
-					if (time.monotonic() - tm) > timeout:
-						return res
-					time.sleep(0.1)
-			res += self.recvbuf[0:1]
-			self.recvbuf = self.recvbuf[1:]
-			size -= 1
-		return res
-
-	def write(self, buffer):
-		self.telnet.write(buffer)
-
-	def discard_inputs(self, timeout=1.0):
-		while True:
-			ch = self.getc_raw(1, timeout=timeout)
-			if ch == b'':
-				break
-
-	def getc(self, size, timeout=1):
-		c = self.getc_raw(size, timeout)
-		return c
-
-	def putc(self, buffer, timeout=1):
-		self.telnet.write(buffer)
-		self.show_progress(len(buffer))
-
-	def reboot(self):
-		# no-op
-		pass
-
-	def set_file_size(self, filesize):
-		self.bytes_transfered = 0
-		self.filesize = filesize
-		self.count = 0
-
-	def show_progress(self, sendsize):
-		if PRINT_RAW_COMMAND:
-			if self.count < MAX_DOT_COUNT:
-				self.bytes_transfered = self.bytes_transfered + sendsize
-				cur_count = int(self.bytes_transfered * MAX_DOT_COUNT / self.filesize)
-				if MAX_DOT_COUNT < cur_count:
-					cur_count = MAX_DOT_COUNT
-				for idx in range(cur_count - self.count):
-					print('#',end='')
-					sys.stdout.flush()
-				self.count = cur_count
-				if self.count == MAX_DOT_COUNT:
-					print("\n")
-
-class SerialDev:
-	def __init__(self):
-		if import_serial_module is False:
-			print("Cannot import serial module, maybe it's not install yet.")
-			print("\n", end="")
-			print("Please install python-setuptool by Cygwin installer.")
-			print("After that use easy_intall command to install serial module")
-			print("    $ cd tool/")
-			print("    $ python3 -m easy_install pyserial-2.7.tar.gz")
-			quit()
-		else:
-			port = ConfigArgs.SERIAL_PORT
-			try:
-				self.serial = serial.Serial(port, baudrate=115200,
-					parity=serial.PARITY_NONE, stopbits=serial.STOPBITS_ONE,
-					bytesize=serial.EIGHTBITS, timeout=0.1)
-			except Exception as e:
-				print("Cannot open port : " + port)
-				sys.exit(e.args[0])
-
-	def readline(self, size=None):
-		return self.serial.readline(size)
-
-	def write(self, buffer):
-		self.serial.write(buffer)
-		self.serial.flush()
-
-	def discard_inputs(self, timeout=1.0):
-		time.sleep(timeout)
-		self.serial.flushInput()
-
-	def getc(self, size, timeout=1):
-		self.serial.timeout = timeout
-		c = self.serial.read(size)
-		self.serial.timeout = 0.1
-		return c
-
-	def putc(self, buffer, timeout=1):
-		self.serial.timeout = timeout
-		self.serial.write(buffer)
-		self.serial.flush()
-		self.serial.timeout = 0.1
-		self.show_progress(len(buffer))
-
-	# Note: windows platform dependent code
-	def putc_win(self, buffer, timeout=1):
-		self.serial.write(buffer)
-		self.show_progress(len(buffer))
-		while True:
-			if self.serial.out_waiting == 0:
-				break
-
-	def setBaudrate(self, baudrate):
-#		self.serial.setBaudrate(baudrate)
-		self.serial.baudrate = baudrate
-
-	def reboot(self):
-		# Target Reset by DTR
-		self.serial.setDTR(False)
-		self.serial.setDTR(True)
-		self.serial.setDTR(False)
-
-	def set_file_size(self, filesize):
-		self.bytes_transfered = 0
-		self.filesize = filesize
-		self.count = 0
-
-	def show_progress(self, sendsize):
-		if PRINT_RAW_COMMAND:
-			if self.count < MAX_DOT_COUNT:
-				self.bytes_transfered = self.bytes_transfered + sendsize
-				cur_count = int(self.bytes_transfered * MAX_DOT_COUNT / self.filesize)
-				if MAX_DOT_COUNT < cur_count:
-					cur_count = MAX_DOT_COUNT
-				for idx in range(cur_count - self.count):
-					print('#',end='')
-					sys.stdout.flush()
-				self.count = cur_count
-				if self.count == MAX_DOT_COUNT:
-					print("\n")
-
-class FlashWriter:
-	def __init__(self, protocol_sel=PROTOCOL_SERIAL):
-		if protocol_sel == PROTOCOL_TELNET:
-			self.serial = TelnetDev()
-		else:
-			self.serial = SerialDev()
-
-	def cancel_autoboot(self) :
-		boot_msg = ''
-		self.serial.reboot()  # Target reboot before send 'r'
-		while boot_msg == '' :
-			rx = self.serial.readline().strip()
-			self.serial.write(b"r")  # Send "r" key to avoid auto boot
-			for msg in ROM_MSG :
-				if msg in rx :
-					boot_msg = msg
-					break
-		while True :
-			rx = self.serial.readline().decode(errors="replace").strip()
-			if "updater" in rx :
-				# Workaround : Sometime first character is dropped.
-				# Send line feed as air shot before actual command.
-				self.serial.write(b"\n")    # Send line feed
-				self.serial.discard_inputs()# Clear input buffer to sync
-				return boot_msg.decode(errors="ignore")
-
-	def recv(self):
-		rx = self.serial.readline()
-		if PRINT_RAW_COMMAND :
-			serial_line = rx.decode(errors="replace")
-			if serial_line.strip() != "" and not serial_line.startswith(XMDM_MSG):
-				print(serial_line, end="")
-		return rx
-
-	def wait(self, string):
-		while True:
-			rx = self.recv()
-			if string.encode() in rx:
-				time.sleep(0.1)
-				break
-
-	def wait_for_prompt(self):
-		prompt_pat = re.compile(b"updater")
-		while True:
-			rx = self.recv()
-			if prompt_pat.search(rx):
-				time.sleep(0.1)
-				break
-
-	def send(self, string):
-		self.serial.write(str(string).encode() + b"\n")
-		rx = self.serial.readline()
-		if PRINT_RAW_COMMAND :
-			print(rx.decode(errors="replace"), end="")
-
-	def read_output(self, prompt_text) :
-		output = []
-		while True :
-			rx = self.serial.readline()
-			if prompt_text.encode() in rx :
-				time.sleep(0.1)
-				break
-			if rx != "" :
-				output.append(rx.decode(errors="ignore").rstrip())
-		return output
-
-	def install_files(self, files, command) :
-		if ConfigArgs.XMODEM_BAUD:
-			command += " -b " + ConfigArgs.XMODEM_BAUD
-		if os.name == 'nt':
-			modem = xmodem.XMODEM(self.serial.getc, self.serial.putc_win, 'xmodem1k')
-		else:
-			modem = xmodem.XMODEM(self.serial.getc, self.serial.putc, 'xmodem1k')
-		for file in files:
-			with open(file, "rb") as bin :
-				self.send(command)
-				print("Install " + file)
-				self.wait(XMDM_MSG)
-				print("|0%" +
-						"-" * (int(MAX_DOT_COUNT / 2) - 6) +
-						"50%" +
-						"-" * (MAX_DOT_COUNT - int(MAX_DOT_COUNT / 2) - 5) +
-						"100%|")
-				if ConfigArgs.XMODEM_BAUD:
-					self.serial.setBaudrate(ConfigArgs.XMODEM_BAUD)
-					self.serial.discard_inputs() # Clear input buffer to sync
-				self.serial.set_file_size(os.path.getsize(file))
-				modem.send(bin)
-				if ConfigArgs.XMODEM_BAUD:
-					self.serial.setBaudrate(115200)
-			self.wait_for_prompt()
-
-	def save_files(self, files) :
-		if ConfigArgs.XMODEM_BAUD:
-			command = "save_file -b " + ConfigArgs.XMODEM_BAUD + " -x "
-		else:
-			command = "save_file -x "
-		if os.name == 'nt':
-			modem = xmodem.XMODEM(self.serial.getc, self.serial.putc_win, 'xmodem1k')
-		else:
-			modem = xmodem.XMODEM(self.serial.getc, self.serial.putc, 'xmodem1k')
-		for file in files:
-			with open(file, "rb") as bin :
-				self.send(command + os.path.basename(file))
-				print("Save " + file)
-				self.wait(XMDM_MSG)
-				if ConfigArgs.XMODEM_BAUD:
-					self.serial.setBaudrate(ConfigArgs.XMODEM_BAUD)
-					self.serial.discard_inputs() # Clear input buffer to sync
-				self.serial.set_file_size(os.path.getsize(file))
-				modem.send(bin)
-				if ConfigArgs.XMODEM_BAUD:
-					self.serial.setBaudrate(115200)
-				self.wait_for_prompt()
-				self.send("chmod d+rw " + os.path.basename(file))
-				self.wait_for_prompt()
-
-	def delete_files(self, files) :
-		for file in files :
-			self.delete_binary(file)
-
-	def delete_binary(self, bin_name) :
-		self.send("rm " + bin_name)
-		self.wait_for_prompt()
-
-def main():
-	try:
-		config_loader = ConfigArgsLoader()
-		config_loader.update_config()
-	except:
-		return errno.EINVAL
-
-	# Wait to reset the board
-	writer = FlashWriter(ConfigArgs.PROTOCOL_TYPE)
-
-	do_wait_reset = True
-	if ConfigArgs.AUTO_RESET:
-		if subprocess.call("cd " + sys.path[0] + "; ./reset_board.sh", shell=True) == 0:
-			print("auto reset board sucess!!")
-			do_wait_reset = False
-			bootrom_msg = writer.cancel_autoboot()
-
-	if ConfigArgs.DTR_RESET:
-		do_wait_reset = False
-		bootrom_msg = writer.cancel_autoboot()
-
-	if ConfigArgs.WAIT_RESET == False and do_wait_reset == True:
-		rx = writer.recv()
-		time.sleep(1)
-		for i in range(3):
-			writer.send("")
-			rx = writer.recv()
-			if "updater".encode() in rx:
-				# No need to wait for reset
-				do_wait_reset = False
-				break
-			time.sleep(1)
-
-	if do_wait_reset:
-		# Wait to reset the board
-		print('Please press RESET button on target board')
-		sys.stdout.flush()
-		bootrom_msg = writer.cancel_autoboot()
-
-	# Remove files
-	if ConfigArgs.ERASE_NAME :
-		print(">>> Remove exisiting files ...")
-		writer.delete_files(ConfigArgs.ERASE_NAME)
-
-	# Install files
-	if ConfigArgs.PACKAGE_NAME or ConfigArgs.PKGSYS_NAME or ConfigArgs.PKGAPP_NAME or ConfigArgs.PKGUPD_NAME:
-		print(">>> Install files ...")
-	if ConfigArgs.PACKAGE_NAME :
-		writer.install_files(ConfigArgs.PACKAGE_NAME, "install")
-	if ConfigArgs.PKGSYS_NAME :
-		writer.install_files(ConfigArgs.PKGSYS_NAME, "install")
-	if ConfigArgs.PKGAPP_NAME :
-		writer.install_files(ConfigArgs.PKGAPP_NAME, "install")
-	if ConfigArgs.PKGUPD_NAME :
-		writer.install_files(ConfigArgs.PKGUPD_NAME, "install -k updater.key")
-
-	# Save files
-	if ConfigArgs.FILE_NAME :
-		print(">>> Save files ...")
-		writer.save_files(ConfigArgs.FILE_NAME)
-
-	# Set auto boot
-	if not ConfigArgs.NO_SET_BOOTABLE:
-		print(">>> Save Configuration to FlashROM ...")
-		writer.send("set bootable M0P")
-		writer.wait_for_prompt()
-
-	# Sync all cached data to flash
-	writer.send("sync")
-	writer.wait_for_prompt()
-
-	if REBOOT_AT_END :
-		print("Restarting the board ...")
-		writer.send("reboot")
-
-	return 0
-
-if __name__ == "__main__":
-	try:
-		sys.exit(main())
-	except KeyboardInterrupt:
-		print("Canceled by keyboard interrupt.")
-		pass
diff --git a/tinyusb/hw/mcu/sony/cxd56/tools/xmodem.py b/tinyusb/hw/mcu/sony/cxd56/tools/xmodem.py
deleted file mode 100755
index c9343005..00000000
--- a/tinyusb/hw/mcu/sony/cxd56/tools/xmodem.py
+++ /dev/null
@@ -1,590 +0,0 @@
-'''
-===============================
- XMODEM file transfer protocol
-===============================
-
-.. $Id$
-
-This is a literal implementation of XMODEM.TXT_, XMODEM1K.TXT_ and
-XMODMCRC.TXT_, support for YMODEM and ZMODEM is pending. YMODEM should
-be fairly easy to implement as it is a hack on top of the XMODEM
-protocol using sequence bytes ``0x00`` for sending file names (and some
-meta data).
-
-.. _XMODEM.TXT: doc/XMODEM.TXT
-.. _XMODEM1K.TXT: doc/XMODEM1K.TXT
-.. _XMODMCRC.TXT: doc/XMODMCRC.TXT
-
-Data flow example including error recovery
-==========================================
-
-Here is a sample of the data flow, sending a 3-block message.
-It includes the two most common line hits - a garbaged block,
-and an ``ACK`` reply getting garbaged. ``CRC`` or ``CSUM`` represents
-the checksum bytes.
-
-XMODEM 128 byte blocks
-----------------------
-
-::
-
-    SENDER                                      RECEIVER
-
-                                            <-- NAK
-    SOH 01 FE Data[128] CSUM                -->
-                                            <-- ACK
-    SOH 02 FD Data[128] CSUM                -->
-                                            <-- ACK
-    SOH 03 FC Data[128] CSUM                -->
-                                            <-- ACK
-    SOH 04 FB Data[128] CSUM                -->
-                                            <-- ACK
-    SOH 05 FA Data[100] CPMEOF[28] CSUM     -->
-                                            <-- ACK
-    EOT                                     -->
-                                            <-- ACK
-
-XMODEM-1k blocks, CRC mode
---------------------------
-
-::
-
-    SENDER                                      RECEIVER
-
-                                            <-- C
-    STX 01 FE Data[1024] CRC CRC            -->
-                                            <-- ACK
-    STX 02 FD Data[1024] CRC CRC            -->
-                                            <-- ACK
-    STX 03 FC Data[1000] CPMEOF[24] CRC CRC -->
-                                            <-- ACK
-    EOT                                     -->
-                                            <-- ACK
-
-Mixed 1024 and 128 byte Blocks
-------------------------------
-
-::
-
-    SENDER                                      RECEIVER
-
-                                            <-- C
-    STX 01 FE Data[1024] CRC CRC            -->
-                                            <-- ACK
-    STX 02 FD Data[1024] CRC CRC            -->
-                                            <-- ACK
-    SOH 03 FC Data[128] CRC CRC             -->
-                                            <-- ACK
-    SOH 04 FB Data[100] CPMEOF[28] CRC CRC  -->
-                                            <-- ACK
-    EOT                                     -->
-                                            <-- ACK
-
-YMODEM Batch Transmission Session (1 file)
-------------------------------------------
-
-::
-
-    SENDER                                      RECEIVER
-                                            <-- C (command:rb)
-    SOH 00 FF foo.c NUL[123] CRC CRC        -->
-                                            <-- ACK
-                                            <-- C
-    SOH 01 FE Data[128] CRC CRC             -->
-                                            <-- ACK
-    SOH 02 FC Data[128] CRC CRC             -->
-                                            <-- ACK
-    SOH 03 FB Data[100] CPMEOF[28] CRC CRC  -->
-                                            <-- ACK
-    EOT                                     -->
-                                            <-- NAK
-    EOT                                     -->
-                                            <-- ACK
-                                            <-- C
-    SOH 00 FF NUL[128] CRC CRC              -->
-                                            <-- ACK
-
-
-'''
-
-__author__ = 'Wijnand Modderman <maze@pyth0n.org>'
-__copyright__ = ['Copyright (c) 2010 Wijnand Modderman',
-                 'Copyright (c) 1981 Chuck Forsberg']
-__license__ = 'MIT'
-__version__ = '0.3.2'
-
-import logging
-import time
-import sys
-from functools import partial
-import collections
-
-# Loggerr
-log = logging.getLogger('xmodem')
-
-# Protocol bytes
-SOH = bytes([0x01])
-STX = bytes([0x02])
-EOT = bytes([0x04])
-ACK = bytes([0x06])
-DLE = bytes([0x10])
-NAK = bytes([0x15])
-CAN = bytes([0x18])
-CRC = bytes([0x43]) # C
-
-
-class XMODEM(object):
-    '''
-    XMODEM Protocol handler, expects an object to read from and an object to
-    write to.
-
-    >>> def getc(size, timeout=1):
-    ...     return data or None
-    ...
-    >>> def putc(data, timeout=1):
-    ...     return size or None
-    ...
-    >>> modem = XMODEM(getc, putc)
-
-
-    :param getc: Function to retreive bytes from a stream
-    :type getc: callable
-    :param putc: Function to transmit bytes to a stream
-    :type putc: callable
-    :param mode: XMODEM protocol mode
-    :type mode: string
-    :param pad: Padding character to make the packets match the packet size
-    :type pad: char
-
-    '''
-
-    # crctab calculated by Mark G. Mendel, Network Systems Corporation
-    crctable = [
-        0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7,
-        0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef,
-        0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6,
-        0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de,
-        0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485,
-        0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d,
-        0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4,
-        0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc,
-        0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823,
-        0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b,
-        0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12,
-        0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a,
-        0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41,
-        0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49,
-        0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70,
-        0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78,
-        0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f,
-        0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067,
-        0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e,
-        0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256,
-        0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d,
-        0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
-        0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c,
-        0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634,
-        0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab,
-        0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3,
-        0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a,
-        0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92,
-        0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9,
-        0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1,
-        0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8,
-        0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0,
-    ]
-
-    def __init__(self, getc, putc, mode='xmodem', pad=b'\x1a'):
-        self.getc = getc
-        self.putc = putc
-        self.mode = mode
-        self.pad = pad
-
-    def abort(self, count=2, timeout=60):
-        '''
-        Send an abort sequence using CAN bytes.
-        '''
-        for counter in range(0, count):
-            self.putc(CAN, timeout)
-
-    def send(self, stream, retry=32, timeout=360, quiet=0, callback=None):
-        '''
-        Send a stream via the XMODEM protocol.
-
-            >>> stream = file('/etc/issue', 'rb')
-            >>> print modem.send(stream)
-            True
-
-        Returns ``True`` upon succesful transmission or ``False`` in case of
-        failure.
-
-        :param stream: The stream object to send data from.
-        :type stream: stream (file, etc.)
-        :param retry: The maximum number of times to try to resend a failed
-                      packet before failing.
-        :type retry: int
-        :param timeout: The number of seconds to wait for a response before
-                        timing out.
-        :type timeout: int
-        :param quiet: If 0, it prints info to stderr.  If 1, it does not print any info.
-        :type quiet: int
-        :param callback: Reference to a callback function that has the
-                         following signature.  This is useful for
-                         getting status updates while a xmodem
-                         transfer is underway.
-                         Expected callback signature:
-                         def callback(total_packets, success_count, error_count)
-        :type callback: callable
-        '''
-
-        # initialize protocol
-        try:
-            packet_size = dict(
-                xmodem    = 128,
-                xmodem1k  = 1024,
-            )[self.mode]
-        except AttributeError:
-            raise ValueError("An invalid mode was supplied")
-
-        error_count = 0
-        crc_mode = 0
-        cancel = 0
-        while True:
-            char = self.getc(1)
-            if char:
-                if char == NAK:
-                    crc_mode = 0
-                    break
-                elif char == CRC:
-                    crc_mode = 1
-                    break
-                elif char == CAN:
-                    if not quiet:
-                        print('received CAN', file=sys.stderr)
-                    if cancel:
-                        return False
-                    else:
-                        cancel = 1
-                else:
-                    log.error('send ERROR expected NAK/CRC, got %s' % \
-                        (ord(char),))
-
-            error_count += 1
-            if error_count >= retry:
-                self.abort(timeout=timeout)
-                return False
-
-        # send data
-        error_count = 0
-        success_count = 0
-        total_packets = 0
-        sequence = 1
-        while True:
-            data = stream.read(packet_size)
-            if not data:
-                log.info('sending EOT')
-                # end of stream
-                break
-            total_packets += 1
-            data = data.ljust(packet_size, self.pad)
-            if crc_mode:
-                crc = self.calc_crc(data)
-            else:
-                crc = self.calc_checksum(data)
-
-            # emit packet
-            while True:
-                if packet_size == 128:
-                    self.putc(SOH)
-                else:  # packet_size == 1024
-                    self.putc(STX)
-                self.putc(bytes([sequence]))
-                self.putc(bytes([0xff - sequence]))
-                self.putc(data)
-                if crc_mode:
-                    self.putc(bytes([crc >> 8]))
-                    self.putc(bytes([crc & 0xff]))
-                else:
-                    self.putc(bytes([crc]))
-
-                char = self.getc(1, timeout)
-                if char == ACK:
-                    success_count += 1
-                    if isinstance(callback, collections.Callable):
-                        callback(total_packets, success_count, error_count)
-                    break
-                if char == NAK:
-                    error_count += 1
-                    if isinstance(callback, collections.Callable):
-                        callback(total_packets, success_count, error_count)
-                    if error_count >= retry:
-                        # excessive amounts of retransmissions requested,
-                        # abort transfer
-                        self.abort(timeout=timeout)
-                        log.warning('excessive NAKs, transfer aborted')
-                        return False
-
-                    # return to loop and resend
-                    continue
-                else:
-                    log.error('Not ACK, Not NAK')
-                    error_count += 1
-                    if isinstance(callback, collections.Callable):
-                        callback(total_packets, success_count, error_count)
-                    if error_count >= retry:
-                        # excessive amounts of retransmissions requested,
-                        # abort transfer
-                        self.abort(timeout=timeout)
-                        log.warning('excessive protocol errors, transfer aborted')
-                        return False
-
-                    # return to loop and resend
-                    continue
-
-                # protocol error
-                self.abort(timeout=timeout)
-                log.error('protocol error')
-                return False
-
-            # keep track of sequence
-            sequence = (sequence + 1) % 0x100
-
-        while True:
-            # end of transmission
-            self.putc(EOT)
-
-            #An ACK should be returned
-            char = self.getc(1, timeout)
-            if char == ACK:
-                break
-            else:
-                error_count += 1
-                if error_count >= retry:
-                    self.abort(timeout=timeout)
-                    log.warning('EOT was not ACKd, transfer aborted')
-                    return False
-
-        return True
-
-    def recv(self, stream, crc_mode=1, retry=16, timeout=60, delay=1, quiet=0):
-        '''
-        Receive a stream via the XMODEM protocol.
-
-            >>> stream = file('/etc/issue', 'wb')
-            >>> print modem.recv(stream)
-            2342
-
-        Returns the number of bytes received on success or ``None`` in case of
-        failure.
-        '''
-
-        # initiate protocol
-        error_count = 0
-        char = 0
-        cancel = 0
-        while True:
-            # first try CRC mode, if this fails,
-            # fall back to checksum mode
-            if error_count >= retry:
-                self.abort(timeout=timeout)
-                return None
-            elif crc_mode and error_count < (retry / 2):
-                if not self.putc(CRC):
-                    time.sleep(delay)
-                    error_count += 1
-            else:
-                crc_mode = 0
-                if not self.putc(NAK):
-                    time.sleep(delay)
-                    error_count += 1
-
-            char = self.getc(1, timeout)
-            if not char:
-                error_count += 1
-                continue
-            elif char == SOH:
-                #crc_mode = 0
-                break
-            elif char == STX:
-                break
-            elif char == CAN:
-                if cancel:
-                    return None
-                else:
-                    cancel = 1
-            else:
-                error_count += 1
-
-        # read data
-        error_count = 0
-        income_size = 0
-        packet_size = 128
-        sequence = 1
-        cancel = 0
-        while True:
-            while True:
-                if char == SOH:
-                    packet_size = 128
-                    break
-                elif char == STX:
-                    packet_size = 1024
-                    break
-                elif char == EOT:
-                    # We received an EOT, so send an ACK and return the received
-                    # data length
-                    self.putc(ACK)
-                    return income_size
-                elif char == CAN:
-                    # cancel at two consecutive cancels
-                    if cancel:
-                        return None
-                    else:
-                        cancel = 1
-                else:
-                    if not quiet:
-                        print('recv ERROR expected SOH/EOT, got', ord(char), file=sys.stderr)
-                    error_count += 1
-                    if error_count >= retry:
-                        self.abort()
-                        return None
-            # read sequence
-            error_count = 0
-            cancel = 0
-            seq1 = ord(self.getc(1))
-            seq2 = 0xff - ord(self.getc(1))
-            if seq1 == sequence and seq2 == sequence:
-                # sequence is ok, read packet
-                # packet_size + checksum
-                data = self.getc(packet_size + 1 + crc_mode, timeout)
-                if crc_mode:
-                    csum = (ord(data[-2]) << 8) + ord(data[-1])
-                    data = data[:-2]
-                    log.debug('CRC (%04x <> %04x)' % \
-                        (csum, self.calc_crc(data)))
-                    valid = csum == self.calc_crc(data)
-                else:
-                    csum = data[-1]
-                    data = data[:-1]
-                    log.debug('checksum (checksum(%02x <> %02x)' % \
-                        (ord(csum), self.calc_checksum(data)))
-                    valid = ord(csum) == self.calc_checksum(data)
-
-                # valid data, append chunk
-                if valid:
-                    income_size += len(data)
-                    stream.write(data)
-                    self.putc(ACK)
-                    sequence = (sequence + 1) % 0x100
-                    char = self.getc(1, timeout)
-                    continue
-            else:
-                # consume data
-                self.getc(packet_size + 1 + crc_mode)
-                self.debug('expecting sequence %d, got %d/%d' % \
-                    (sequence, seq1, seq2))
-
-            # something went wrong, request retransmission
-            self.putc(NAK)
-
-    def calc_checksum(self, data, checksum=0):
-        '''
-        Calculate the checksum for a given block of data, can also be used to
-        update a checksum.
-
-            >>> csum = modem.calc_checksum('hello')
-            >>> csum = modem.calc_checksum('world', csum)
-            >>> hex(csum)
-            '0x3c'
-
-        '''
-        return (sum(map(ord, data)) + checksum) % 256
-
-    def calc_crc(self, data, crc=0):
-        '''
-        Calculate the Cyclic Redundancy Check for a given block of data, can
-        also be used to update a CRC.
-
-            >>> crc = modem.calc_crc('hello')
-            >>> crc = modem.calc_crc('world', crc)
-            >>> hex(crc)
-            '0xd5e3'
-
-        '''
-        for char in data:
-            crc = (crc << 8) ^ self.crctable[((crc >> 8) ^ int(char)) & 0xff]
-        return crc & 0xffff
-
-
-XMODEM1k  = partial(XMODEM, mode='xmodem1k')
-
-
-def run():
-    import optparse
-    import subprocess
-
-    parser = optparse.OptionParser(usage='%prog [<options>] <send|recv> filename filename')
-    parser.add_option('-m', '--mode', default='xmodem',
-        help='XMODEM mode (xmodem, xmodem1k)')
-
-    options, args = parser.parse_args()
-    if len(args) != 3:
-        parser.error('invalid arguments')
-        return 1
-
-    elif args[0] not in ('send', 'recv'):
-        parser.error('invalid mode')
-        return 1
-
-    def _func(so, si):
-        import select
-        import subprocess
-
-        print('si', si)
-        print('so', so)
-
-        def getc(size, timeout=3):
-            w,t,f = select.select([so], [], [], timeout)
-            if w:
-                data = so.read(size)
-            else:
-                data = None
-
-            print('getc(', repr(data), ')')
-            return data
-
-        def putc(data, timeout=3):
-            w,t,f = select.select([], [si], [], timeout)
-            if t:
-                si.write(data)
-                si.flush()
-                size = len(data)
-            else:
-                size = None
-
-            print('putc(', repr(data), repr(size), ')')
-            return size
-
-        return getc, putc
-
-    def _pipe(*command):
-        pipe = subprocess.Popen(command,
-            stdout=subprocess.PIPE, stdin=subprocess.PIPE)
-        return pipe.stdout, pipe.stdin
-
-    if args[0] == 'recv':
-        import io
-        getc, putc = _func(*_pipe('sz', '--xmodem', args[2]))
-        stream = open(args[1], 'wb')
-        xmodem = XMODEM(getc, putc, mode=options.mode)
-        status = xmodem.recv(stream, retry=8)
-        stream.close()
-
-    elif args[0] == 'send':
-        getc, putc = _func(*_pipe('rz', '--xmodem', args[2]))
-        stream = open(args[1], 'rb')
-        xmodem = XMODEM(getc, putc, mode=options.mode)
-        status = xmodem.send(stream, retry=8)
-        stream.close()
-
-if __name__ == '__main__':
-    sys.exit(run())