diff options
| author | Joey Castillo <jose.castillo@gmail.com> | 2021-08-28 12:50:18 -0400 |
|---|---|---|
| committer | Joey Castillo <jose.castillo@gmail.com> | 2021-08-28 12:50:18 -0400 |
| commit | 39a5c822a2a2e798e2e39ff8a98b7af84253026c (patch) | |
| tree | fa157c98d3aea0d4f996e4415aa2a7ad1093ac05 /tinyusb/hw/mcu | |
| parent | c9e00b83bbdcb05058806d915ec4fff3cf4e596f (diff) | |
| download | Sensor-Watch-39a5c822a2a2e798e2e39ff8a98b7af84253026c.tar.gz Sensor-Watch-39a5c822a2a2e798e2e39ff8a98b7af84253026c.tar.bz2 Sensor-Watch-39a5c822a2a2e798e2e39ff8a98b7af84253026c.zip | |
add tinyusb
Diffstat (limited to 'tinyusb/hw/mcu')
52 files changed, 28867 insertions, 0 deletions
diff --git a/tinyusb/hw/mcu/dialog/README.md b/tinyusb/hw/mcu/dialog/README.md new file mode 100755 index 00000000..69676f08 --- /dev/null +++ b/tinyusb/hw/mcu/dialog/README.md @@ -0,0 +1,9 @@ +# Dialog DA1469x MCU + +**Dialog Semiconductors** provides SDKs for DA146x MCU family. +Most of the files there can't be redistributed. +Registers definition file `DA1469xAB.h` and some **ARM** originated headers are have licenses that allow +for redistribution. +Whole SDK repository can be downloaded from Dialog Semiconductor web page `https://www.dialog.com` + + diff --git a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/arm_license.txt b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/arm_license.txt new file mode 100755 index 00000000..b324eb28 --- /dev/null +++ b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/arm_license.txt @@ -0,0 +1,27 @@ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + diff --git a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/DA1469xAB.h b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/DA1469xAB.h new file mode 100755 index 00000000..fa2ca5d9 --- /dev/null +++ b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/DA1469xAB.h @@ -0,0 +1,8657 @@ +/* + * Copyright (C) 2019 Dialog Semiconductor. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of Dialog Semiconductor nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * @file DA1469xAB.h + * @brief CMSIS HeaderFile + * @version 1.2 + * @date 22. April 2019 + * @note Generated by SVDConv V3.3.25 on Monday, 22.04.2019 11:06:30 + * from File 'DA1469xAB.xml', + */ + + + +/** @addtogroup PLA_BSP_REGISTERS + * @{ + */ + + +/** @addtogroup DA1469x + * @{ + */ + + +#ifndef DA1469X_H +#define DA1469X_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Number Definition + */ + +typedef enum { +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ========================================== DA1469x Specific Interrupt Numbers =========================================== */ + SNC_IRQn = 0, /*!< 0 Sensor Node Controller interrupt request. */ + DMA_IRQn = 1, /*!< 1 General Purpose DMA interrupt request. */ + CHARGER_STATE_IRQn = 2, /*!< 2 Charger State interrupt request. */ + CHARGER_ERROR_IRQn = 3, /*!< 3 Charger Error interrupt request. */ + CMAC2SYS_IRQn = 4, /*!< 4 CMAC and mailbox interrupt request. */ + UART_IRQn = 5, /*!< 5 UART interrupt request. */ + UART2_IRQn = 6, /*!< 6 UART2 interrupt request. */ + UART3_IRQn = 7, /*!< 7 UART3 interrupt request. */ + I2C_IRQn = 8, /*!< 8 I2C interrupt request. */ + I2C2_IRQn = 9, /*!< 9 I2C2 interrupt request. */ + SPI_IRQn = 10, /*!< 10 SPI interrupt request. */ + SPI2_IRQn = 11, /*!< 11 SPI2 interrupt request. */ + PCM_IRQn = 12, /*!< 12 PCM interrupt request. */ + SRC_IN_IRQn = 13, /*!< 13 SRC input interrupt request. */ + SRC_OUT_IRQn = 14, /*!< 14 SRC output interrupt request. */ + USB_IRQn = 15, /*!< 15 USB interrupt request. */ + TIMER_IRQn = 16, /*!< 16 TIMER interrupt request. */ + TIMER2_IRQn = 17, /*!< 17 TIMER2 interrupt request. */ + RTC_IRQn = 18, /*!< 18 RTC interrupt request. */ + KEY_WKUP_GPIO_IRQn = 19, /*!< 19 Debounced button press interrupt request. */ + PDC_IRQn = 20, /*!< 20 Wakeup IRQ from PDC to CM33 */ + VBUS_IRQn = 21, /*!< 21 VBUS presence interrupt request. */ + MRM_IRQn = 22, /*!< 22 Cache Miss Rate Monitor interrupt request. */ + MOTOR_CONTROLLER_IRQn = 23, /*!< 23 MOTOR and mailbox interrupt request. */ + TRNG_IRQn = 24, /*!< 24 True Random Number Generation interrupt request. */ + DCDC_IRQn = 25, /*!< 25 DCDC interrupt request. */ + XTAL32M_RDY_IRQn = 26, /*!< 26 XTAL32M trimmed and ready interrupt request. */ + GPADC_IRQn = 27, /*!< 27 General Purpose Analog-Digital Converter interrupt request. */ + SDADC_IRQn = 28, /*!< 28 Sigma Delta Analog-Digital Converter interrupt request. */ + CRYPTO_IRQn = 29, /*!< 29 Crypto interrupt request. */ + CAPTIMER_IRQn = 30, /*!< 30 GPIO triggered Timer Capture interrupt request. */ + RFDIAG_IRQn = 31, /*!< 31 Baseband or Radio Diagnostics interrupt request. */ + LCD_CONTROLLER_IRQn = 32, /*!< 32 Parallel LCD Controller interrupt request. */ + PLL_LOCK_IRQn = 33, /*!< 33 Pll lock interrupt request. */ + TIMER3_IRQn = 34, /*!< 34 TIMER3 interrupt request. */ + TIMER4_IRQn = 35, /*!< 35 TIMER4 interrupt request. */ + LRA_IRQn = 36, /*!< 36 LRA/ERM interrupt request. */ + RTC_EVENT_IRQn = 37, /*!< 37 RTC event interrupt request. */ + GPIO_P0_IRQn = 38, /*!< 38 GPIO port 0 toggle interrupt request. */ + GPIO_P1_IRQn = 39 /*!< 39 GPIO port 1 toggle interrupt request. */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ +#define __CM33_REV 0x0000U /*!< CM33 Core Revision */ +#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present */ +#define __FPU_PRESENT 1 /*!< FPU present */ +#define __FPU_DP 0 /*!< Double Precision FPU */ +#define __DSP_PRESENT 1 /*!< DSP extension present */ +#define __SAU_REGION_PRESENT 0 /*!< SAU present */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_DA1469x.h" /*!< DA1469x System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ AES_HASH ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief AES_HASH registers (AES_HASH) + */ + +typedef struct { /*!< (@ 0x30040000) AES_HASH Structure */ + __IOM uint32_t CRYPTO_CTRL_REG; /*!< (@ 0x00000000) Crypto Control register */ + __IOM uint32_t CRYPTO_START_REG; /*!< (@ 0x00000004) Crypto Start calculation */ + __IOM uint32_t CRYPTO_FETCH_ADDR_REG; /*!< (@ 0x00000008) Crypto DMA fetch register */ + __IOM uint32_t CRYPTO_LEN_REG; /*!< (@ 0x0000000C) Crypto Length of the input block in bytes */ + __IOM uint32_t CRYPTO_DEST_ADDR_REG; /*!< (@ 0x00000010) Crypto DMA destination memory */ + __IOM uint32_t CRYPTO_STATUS_REG; /*!< (@ 0x00000014) Crypto Status register */ + __IOM uint32_t CRYPTO_CLRIRQ_REG; /*!< (@ 0x00000018) Crypto Clear interrupt request */ + __IOM uint32_t CRYPTO_MREG0_REG; /*!< (@ 0x0000001C) Crypto Mode depended register 0 */ + __IOM uint32_t CRYPTO_MREG1_REG; /*!< (@ 0x00000020) Crypto Mode depended register 1 */ + __IOM uint32_t CRYPTO_MREG2_REG; /*!< (@ 0x00000024) Crypto Mode depended register 2 */ + __IOM uint32_t CRYPTO_MREG3_REG; /*!< (@ 0x00000028) Crypto Mode depended register 3 */ + __IM uint32_t RESERVED[53]; + __IOM uint32_t CRYPTO_KEYS_START; /*!< (@ 0x00000100) Crypto First position of the AES keys storage + memory */ +} AES_HASH_Type; /*!< Size = 260 (0x104) */ + + + +/* =========================================================================================================================== */ +/* ================ ANAMISC_BIF ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief ANAMISC_BIF registers (ANAMISC_BIF) + */ + +typedef struct { /*!< (@ 0x50030B00) ANAMISC_BIF Structure */ + __IM uint32_t RESERVED[4]; + __IOM uint32_t CLK_REF_SEL_REG; /*!< (@ 0x00000010) Select clock for oscillator calibration */ + __IOM uint32_t CLK_REF_CNT_REG; /*!< (@ 0x00000014) Count value for oscillator calibration */ + __IOM uint32_t CLK_REF_VAL_REG; /*!< (@ 0x00000018) DIVN reference cycles, lower 16 bits */ +} ANAMISC_BIF_Type; /*!< Size = 28 (0x1c) */ + + + +/* =========================================================================================================================== */ +/* ================ APU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief APU registers (APU) + */ + +typedef struct { /*!< (@ 0x50030600) APU Structure */ + __IOM uint32_t SRC1_CTRL_REG; /*!< (@ 0x00000000) SRC1 control register */ + __IOM uint32_t SRC1_IN_FS_REG; /*!< (@ 0x00000004) SRC1 Sample input rate */ + __IOM uint32_t SRC1_OUT_FS_REG; /*!< (@ 0x00000008) SRC1 Sample output rate */ + __IOM uint32_t SRC1_IN1_REG; /*!< (@ 0x0000000C) SRC1 data in 1 */ + __IOM uint32_t SRC1_IN2_REG; /*!< (@ 0x00000010) SRC1 data in 2 */ + __IOM uint32_t SRC1_OUT1_REG; /*!< (@ 0x00000014) SRC1 data out 1 */ + __IOM uint32_t SRC1_OUT2_REG; /*!< (@ 0x00000018) SRC1 data out 2 */ + __IOM uint32_t APU_MUX_REG; /*!< (@ 0x0000001C) APU mux register */ + __IOM uint32_t COEF10_SET1_REG; /*!< (@ 0x00000020) SRC coefficient 1,0 set 1 */ + __IOM uint32_t COEF32_SET1_REG; /*!< (@ 0x00000024) SRC coefficient 3,2 set 1 */ + __IOM uint32_t COEF54_SET1_REG; /*!< (@ 0x00000028) SRC coefficient 5,4 set 1 */ + __IOM uint32_t COEF76_SET1_REG; /*!< (@ 0x0000002C) SRC coefficient 7,6 set 1 */ + __IOM uint32_t COEF98_SET1_REG; /*!< (@ 0x00000030) SRC coefficient 9,8 set 1 */ + __IOM uint32_t COEF0A_SET1_REG; /*!< (@ 0x00000034) SRC coefficient 10 set 1 */ + __IM uint32_t RESERVED[50]; + __IOM uint32_t PCM1_CTRL_REG; /*!< (@ 0x00000100) PCM1 Control register */ + __IOM uint32_t PCM1_IN1_REG; /*!< (@ 0x00000104) PCM1 data in 1 */ + __IOM uint32_t PCM1_IN2_REG; /*!< (@ 0x00000108) PCM1 data in 2 */ + __IOM uint32_t PCM1_OUT1_REG; /*!< (@ 0x0000010C) PCM1 data out 1 */ + __IOM uint32_t PCM1_OUT2_REG; /*!< (@ 0x00000110) PCM1 data out 2 */ +} APU_Type; /*!< Size = 276 (0x114) */ + + + +/* =========================================================================================================================== */ +/* ================ CACHE ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief CACHE registers (CACHE) + */ + +typedef struct { /*!< (@ 0x100C0000) CACHE Structure */ + __IOM uint32_t CACHE_CTRL1_REG; /*!< (@ 0x00000000) Cache control register 1 */ + __IOM uint32_t CACHE_LNSIZECFG_REG; /*!< (@ 0x00000004) Cache line size configuration register */ + __IOM uint32_t CACHE_ASSOCCFG_REG; /*!< (@ 0x00000008) Cache associativity configuration register */ + __IM uint32_t RESERVED[5]; + __IOM uint32_t CACHE_CTRL2_REG; /*!< (@ 0x00000020) Cache control register 2 */ + __IM uint32_t RESERVED1; + __IOM uint32_t CACHE_MRM_HITS_REG; /*!< (@ 0x00000028) Cache MRM (Miss Rate Monitor) HITS register */ + __IOM uint32_t CACHE_MRM_MISSES_REG; /*!< (@ 0x0000002C) Cache MRM (Miss Rate Monitor) MISSES register */ + __IOM uint32_t CACHE_MRM_CTRL_REG; /*!< (@ 0x00000030) Cache MRM (Miss Rate Monitor) CONTROL register */ + __IOM uint32_t CACHE_MRM_TINT_REG; /*!< (@ 0x00000034) Cache MRM (Miss Rate Monitor) TIME INTERVAL register */ + __IOM uint32_t CACHE_MRM_MISSES_THRES_REG; /*!< (@ 0x00000038) Cache MRM (Miss Rate Monitor) THRESHOLD register */ + __IOM uint32_t CACHE_MRM_HITS_THRES_REG; /*!< (@ 0x0000003C) Cache MRM (Miss Rate Monitor) HITS THRESHOLD + register */ + __IOM uint32_t CACHE_FLASH_REG; /*!< (@ 0x00000040) Cache Flash program size and base address register */ + __IM uint32_t RESERVED2[3]; + __IOM uint32_t SWD_RESET_REG; /*!< (@ 0x00000050) SWD HW reset control register */ +} CACHE_Type; /*!< Size = 84 (0x54) */ + + + +/* =========================================================================================================================== */ +/* ================ CHARGER ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief CHARGER registers (CHARGER) + */ + +typedef struct { /*!< (@ 0x50040400) CHARGER Structure */ + __IOM uint32_t CHARGER_CTRL_REG; /*!< (@ 0x00000000) Charger main control register */ + __IOM uint32_t CHARGER_TEST_CTRL_REG; /*!< (@ 0x00000004) Charger test control register */ + __IOM uint32_t CHARGER_STATUS_REG; /*!< (@ 0x00000008) Charger main status register */ + __IOM uint32_t CHARGER_VOLTAGE_PARAM_REG; /*!< (@ 0x0000000C) Charger voltage settings register */ + __IOM uint32_t CHARGER_CURRENT_PARAM_REG; /*!< (@ 0x00000010) Charger current settings register */ + __IOM uint32_t CHARGER_TEMPSET_PARAM_REG; /*!< (@ 0x00000014) Charger battery temperature settings register */ + __IOM uint32_t CHARGER_PRE_CHARGE_TIMER_REG; /*!< (@ 0x00000018) Maximum pre-charge time limit register */ + __IOM uint32_t CHARGER_CC_CHARGE_TIMER_REG; /*!< (@ 0x0000001C) Maximum CC-charge time limit register */ + __IOM uint32_t CHARGER_CV_CHARGE_TIMER_REG; /*!< (@ 0x00000020) Maximum CV-charge time limit register */ + __IOM uint32_t CHARGER_TOTAL_CHARGE_TIMER_REG;/*!< (@ 0x00000024) Maximum total charge time limit register */ + __IOM uint32_t CHARGER_JEITA_V_CHARGE_REG; /*!< (@ 0x00000028) JEITA-compliant Charge voltage settings register */ + __IOM uint32_t CHARGER_JEITA_V_PRECHARGE_REG;/*!< (@ 0x0000002C) JEITA-compliant Pre-Charge voltage settings register */ + __IOM uint32_t CHARGER_JEITA_V_REPLENISH_REG;/*!< (@ 0x00000030) JEITA-compliant Replenish settings register */ + __IOM uint32_t CHARGER_JEITA_V_OVP_REG; /*!< (@ 0x00000034) JEITA-compliant OVP settings register */ + __IOM uint32_t CHARGER_JEITA_CURRENT_REG; /*!< (@ 0x00000038) JEITA-compliant current settings register */ + __IOM uint32_t CHARGER_VBAT_COMP_TIMER_REG; /*!< (@ 0x0000003C) Main Vbat comparator timer register */ + __IOM uint32_t CHARGER_VOVP_COMP_TIMER_REG; /*!< (@ 0x00000040) Vbat OVP comparator timer register */ + __IOM uint32_t CHARGER_TDIE_COMP_TIMER_REG; /*!< (@ 0x00000044) Die temperature comparator timer register */ + __IOM uint32_t CHARGER_TBAT_MON_TIMER_REG; /*!< (@ 0x00000048) Battery temperature monitor interval timer */ + __IOM uint32_t CHARGER_TBAT_COMP_TIMER_REG; /*!< (@ 0x0000004C) Battery temperature (main) comparator timer */ + __IOM uint32_t CHARGER_THOT_COMP_TIMER_REG; /*!< (@ 0x00000050) Battery temperature comparator timer for 'Hot' + zone */ + __IOM uint32_t CHARGER_PWR_UP_TIMER_REG; /*!< (@ 0x00000054) Charger power-up (settling) timer */ + __IOM uint32_t CHARGER_STATE_IRQ_MASK_REG; /*!< (@ 0x00000058) Mask register of Charger FSM IRQs */ + __IOM uint32_t CHARGER_ERROR_IRQ_MASK_REG; /*!< (@ 0x0000005C) Mask register of Charger Error IRQs */ + __IOM uint32_t CHARGER_STATE_IRQ_STATUS_REG; /*!< (@ 0x00000060) Status register of Charger FSM IRQs */ + __IOM uint32_t CHARGER_ERROR_IRQ_STATUS_REG; /*!< (@ 0x00000064) Status register of Charger Error IRQs */ + __IOM uint32_t CHARGER_STATE_IRQ_CLR_REG; /*!< (@ 0x00000068) Interrupt clear register of Charger FSM IRQs */ + __IOM uint32_t CHARGER_ERROR_IRQ_CLR_REG; /*!< (@ 0x0000006C) Interrupt clear register of Charger Error IRQs */ +} CHARGER_Type; /*!< Size = 112 (0x70) */ + + + +/* =========================================================================================================================== */ +/* ================ CHIP_VERSION ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief CHIP_VERSION registers (CHIP_VERSION) + */ + +typedef struct { /*!< (@ 0x50040200) CHIP_VERSION Structure */ + __IOM uint32_t CHIP_ID1_REG; /*!< (@ 0x00000000) Chip identification register 1. */ + __IOM uint32_t CHIP_ID2_REG; /*!< (@ 0x00000004) Chip identification register 2. */ + __IOM uint32_t CHIP_ID3_REG; /*!< (@ 0x00000008) Chip identification register 3. */ + __IOM uint32_t CHIP_ID4_REG; /*!< (@ 0x0000000C) Chip identification register 4. */ + __IOM uint32_t CHIP_SWC_REG; /*!< (@ 0x00000010) Software compatibility register. */ + __IOM uint32_t CHIP_REVISION_REG; /*!< (@ 0x00000014) Chip revision register. */ + __IM uint32_t RESERVED[56]; + __IOM uint32_t CHIP_TEST1_REG; /*!< (@ 0x000000F8) Chip test register 1. */ + __IOM uint32_t CHIP_TEST2_REG; /*!< (@ 0x000000FC) Chip test register 2. */ +} CHIP_VERSION_Type; /*!< Size = 256 (0x100) */ + + + +/* =========================================================================================================================== */ +/* ================ CRG_COM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief CRG_COM registers (CRG_COM) + */ + +typedef struct { /*!< (@ 0x50020900) CRG_COM Structure */ + __IM uint32_t RESERVED; + __IOM uint32_t CLK_COM_REG; /*!< (@ 0x00000004) Peripheral divider register */ + __IOM uint32_t SET_CLK_COM_REG; /*!< (@ 0x00000008) Peripheral divider register SET register. Reads + back 0x0000 */ + __IOM uint32_t RESET_CLK_COM_REG; /*!< (@ 0x0000000C) Peripheral divider register RESET register. Reads + back 0x0000 */ +} CRG_COM_Type; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ CRG_PER ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief CRG_PER registers (CRG_PER) + */ + +typedef struct { /*!< (@ 0x50030C00) CRG_PER Structure */ + __IM uint32_t RESERVED; + __IOM uint32_t CLK_PER_REG; /*!< (@ 0x00000004) Peripheral divider register */ + __IOM uint32_t SET_CLK_PER_REG; /*!< (@ 0x00000008) Peripheral divider register SET register, reads + 0x0000 */ + __IOM uint32_t RESET_CLK_PER_REG; /*!< (@ 0x0000000C) Peripheral divider register RESET register, reads + 0x0000 */ + __IM uint32_t RESERVED1[12]; + __IOM uint32_t PCM_DIV_REG; /*!< (@ 0x00000040) PCM divider and enables */ + __IOM uint32_t PCM_FDIV_REG; /*!< (@ 0x00000044) PCM fractional division register */ + __IOM uint32_t PDM_DIV_REG; /*!< (@ 0x00000048) PDM divider and enables */ + __IOM uint32_t SRC_DIV_REG; /*!< (@ 0x0000004C) SRC divider and enables */ +} CRG_PER_Type; /*!< Size = 80 (0x50) */ + + + +/* =========================================================================================================================== */ +/* ================ CRG_SYS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief CRG_SYS registers (CRG_SYS) + */ + +typedef struct { /*!< (@ 0x50040500) CRG_SYS Structure */ + __IOM uint32_t CLK_SYS_REG; /*!< (@ 0x00000000) Peripheral divider register */ + __IOM uint32_t BATCHECK_REG; /*!< (@ 0x00000004) BATCHECK_REG */ +} CRG_SYS_Type; /*!< Size = 8 (0x8) */ + + + +/* =========================================================================================================================== */ +/* ================ CRG_TOP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief CRG_TOP registers (CRG_TOP) + */ + +typedef struct { /*!< (@ 0x50000000) CRG_TOP Structure */ + __IOM uint32_t CLK_AMBA_REG; /*!< (@ 0x00000000) HCLK, PCLK, divider and clock gates */ + __IM uint32_t RESERVED[3]; + __IOM uint32_t CLK_RADIO_REG; /*!< (@ 0x00000010) Radio PLL control register */ + __IOM uint32_t CLK_CTRL_REG; /*!< (@ 0x00000014) Clock control register */ + __IOM uint32_t CLK_TMR_REG; /*!< (@ 0x00000018) Clock control for the timers */ + __IOM uint32_t CLK_SWITCH2XTAL_REG; /*!< (@ 0x0000001C) Switches clock from RC32M to XTAL32M */ + __IOM uint32_t PMU_CTRL_REG; /*!< (@ 0x00000020) Power Management Unit control register */ + __IOM uint32_t SYS_CTRL_REG; /*!< (@ 0x00000024) System Control register */ + __IOM uint32_t SYS_STAT_REG; /*!< (@ 0x00000028) System status register */ + __IM uint32_t RESERVED1[4]; + __IOM uint32_t CLK_RC32K_REG; /*!< (@ 0x0000003C) 32 kHz RC oscillator register */ + __IOM uint32_t CLK_XTAL32K_REG; /*!< (@ 0x00000040) 32 kHz XTAL oscillator register */ + __IOM uint32_t CLK_RC32M_REG; /*!< (@ 0x00000044) Fast RC control register */ + __IOM uint32_t CLK_RCX_REG; /*!< (@ 0x00000048) RCX-oscillator control register */ + __IOM uint32_t CLK_RTCDIV_REG; /*!< (@ 0x0000004C) Divisor for RTC 100Hz clock */ + __IOM uint32_t BANDGAP_REG; /*!< (@ 0x00000050) bandgap trimming */ + __IOM uint32_t VBUS_IRQ_MASK_REG; /*!< (@ 0x00000054) IRQ masking */ + __IOM uint32_t VBUS_IRQ_CLEAR_REG; /*!< (@ 0x00000058) Clear pending IRQ register */ + __IM uint32_t RESERVED2; + __IOM uint32_t BOD_CTRL_REG; /*!< (@ 0x00000060) Brown Out Detection control register */ + __IOM uint32_t BOD_LVL_CTRL0_REG; /*!< (@ 0x00000064) BOD_LVL_CTRL0_REG */ + __IOM uint32_t BOD_LVL_CTRL1_REG; /*!< (@ 0x00000068) BOD_LVL_CTRL1_REG */ + __IOM uint32_t BOD_LVL_CTRL2_REG; /*!< (@ 0x0000006C) BOD_LVL_CTRL2_REG */ + __IOM uint32_t P0_PAD_LATCH_REG; /*!< (@ 0x00000070) Control the state retention of the GPIO ports */ + __IOM uint32_t P0_SET_PAD_LATCH_REG; /*!< (@ 0x00000074) Control the state retention of the GPIO ports */ + __IOM uint32_t P0_RESET_PAD_LATCH_REG; /*!< (@ 0x00000078) Control the state retention of the GPIO ports */ + __IOM uint32_t P1_PAD_LATCH_REG; /*!< (@ 0x0000007C) Control the state retention of the GPIO ports */ + __IOM uint32_t P1_SET_PAD_LATCH_REG; /*!< (@ 0x00000080) Control the state retention of the GPIO ports */ + __IOM uint32_t P1_RESET_PAD_LATCH_REG; /*!< (@ 0x00000084) Control the state retention of the GPIO ports */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t BOD_STATUS_REG; /*!< (@ 0x00000090) BOD_STATUS_REG */ + __IOM uint32_t POR_VBAT_CTRL_REG; /*!< (@ 0x00000094) Controls the POR on VBAT */ + __IOM uint32_t POR_PIN_REG; /*!< (@ 0x00000098) Selects a GPIO pin for POR generation */ + __IOM uint32_t POR_TIMER_REG; /*!< (@ 0x0000009C) Time for POR to happen */ + __IOM uint32_t LDO_VDDD_HIGH_CTRL_REG; /*!< (@ 0x000000A0) LDO control register */ + __IOM uint32_t BIAS_VREF_SEL_REG; /*!< (@ 0x000000A4) BIAS_VREF_SEL_REG */ + __IM uint32_t RESERVED4[5]; + __IOM uint32_t RESET_STAT_REG; /*!< (@ 0x000000BC) Reset status register */ + __IOM uint32_t RAM_PWR_CTRL_REG; /*!< (@ 0x000000C0) Control power state of System RAMS */ + __IM uint32_t RESERVED5[2]; + __IOM uint32_t SECURE_BOOT_REG; /*!< (@ 0x000000CC) Controls secure booting */ + __IM uint32_t RESERVED6; + __IOM uint32_t DISCHARGE_RAIL_REG; /*!< (@ 0x000000D4) Immediate rail resetting. There is no LDO/DCDC + gating */ + __IM uint32_t RESERVED7[5]; + __IOM uint32_t ANA_STATUS_REG; /*!< (@ 0x000000EC) Analog Signals Status Register */ + __IOM uint32_t POWER_CTRL_REG; /*!< (@ 0x000000F0) Power control register */ + __IOM uint32_t PMU_SLEEP_REG; /*!< (@ 0x000000F4) Configures the sleep/wakeup strategy */ + __IOM uint32_t PMU_TRIM_REG; /*!< (@ 0x000000F8) LDO trimming register */ +} CRG_TOP_Type; /*!< Size = 252 (0xfc) */ + + + +/* =========================================================================================================================== */ +/* ================ CRG_XTAL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief CRG_XTAL registers (CRG_XTAL) + */ + +typedef struct { /*!< (@ 0x50010000) CRG_XTAL Structure */ + __IOM uint32_t CLK_FREQ_TRIM_REG; /*!< (@ 0x00000000) Xtal frequency trimming register. */ + __IM uint32_t RESERVED[3]; + __IOM uint32_t TRIM_CTRL_REG; /*!< (@ 0x00000010) Control trimming of the XTAL32M */ + __IM uint32_t RESERVED1; + __IOM uint32_t XTALRDY_CTRL_REG; /*!< (@ 0x00000018) Control register for XTALRDY IRQ */ + __IOM uint32_t XTALRDY_STAT_REG; /*!< (@ 0x0000001C) Difference between XTAL_OK and XTALRDY_IRQ in + LP clock cycles */ + __IM uint32_t RESERVED2[4]; + __IOM uint32_t XTAL32M_CTRL0_REG; /*!< (@ 0x00000030) Control register for XTAL32M */ + __IOM uint32_t XTAL32M_CTRL1_REG; /*!< (@ 0x00000034) Control register for XTAL32M */ + __IOM uint32_t XTAL32M_CTRL2_REG; /*!< (@ 0x00000038) Control register for XTAL32M */ + __IOM uint32_t XTAL32M_CTRL3_REG; /*!< (@ 0x0000003C) Control register for XTAL32M */ + __IOM uint32_t XTAL32M_CTRL4_REG; /*!< (@ 0x00000040) Control register for XTAL32M */ + __IM uint32_t RESERVED3[3]; + __IOM uint32_t XTAL32M_STAT0_REG; /*!< (@ 0x00000050) Status register for XTAL32M */ + __IOM uint32_t XTAL32M_STAT1_REG; /*!< (@ 0x00000054) Status register for XTAL32M */ + __IM uint32_t RESERVED4[2]; + __IOM uint32_t PLL_SYS_CTRL1_REG; /*!< (@ 0x00000060) System PLL control register 1. */ + __IOM uint32_t PLL_SYS_CTRL2_REG; /*!< (@ 0x00000064) System PLL control register 2. */ + __IOM uint32_t PLL_SYS_CTRL3_REG; /*!< (@ 0x00000068) System PLL control register 3. */ + __IM uint32_t RESERVED5; + __IOM uint32_t PLL_SYS_STATUS_REG; /*!< (@ 0x00000070) System PLL status register. */ +} CRG_XTAL_Type; /*!< Size = 116 (0x74) */ + + + +/* =========================================================================================================================== */ +/* ================ DCDC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DCDC registers (DCDC) + */ + +typedef struct { /*!< (@ 0x50000300) DCDC Structure */ + __IM uint32_t RESERVED; + __IOM uint32_t DCDC_CTRL1_REG; /*!< (@ 0x00000004) DCDC First Control Register */ + __IOM uint32_t DCDC_CTRL2_REG; /*!< (@ 0x00000008) DCDC Second Control Register */ + __IOM uint32_t DCDC_V14_REG; /*!< (@ 0x0000000C) DCDC V14 Control Register */ + __IOM uint32_t DCDC_VDD_REG; /*!< (@ 0x00000010) DCDC VDD Control Register */ + __IOM uint32_t DCDC_V18_REG; /*!< (@ 0x00000014) DCDC V18 Control Register */ + __IOM uint32_t DCDC_V18P_REG; /*!< (@ 0x00000018) DCDC V18P Control Register */ + __IM uint32_t RESERVED1; + __IOM uint32_t DCDC_STATUS1_REG; /*!< (@ 0x00000020) DCDC First Status Register */ + __IM uint32_t RESERVED2[3]; + __IOM uint32_t DCDC_IRQ_STATUS_REG; /*!< (@ 0x00000030) DCDC Interrupt Status Register */ + __IOM uint32_t DCDC_IRQ_CLEAR_REG; /*!< (@ 0x00000034) DCDC Interrupt Clear Register */ + __IOM uint32_t DCDC_IRQ_MASK_REG; /*!< (@ 0x00000038) DCDC Interrupt Mask Register */ +} DCDC_Type; /*!< Size = 60 (0x3c) */ + + + +/* =========================================================================================================================== */ +/* ================ DMA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DMA registers (DMA) + */ + +typedef struct { /*!< (@ 0x50040800) DMA Structure */ + __IOM uint32_t DMA0_A_START_REG; /*!< (@ 0x00000000) Start address A of DMA channel 0 */ + __IOM uint32_t DMA0_B_START_REG; /*!< (@ 0x00000004) Start address B of DMA channel 0 */ + __IOM uint32_t DMA0_INT_REG; /*!< (@ 0x00000008) DMA receive interrupt register channel 0 */ + __IOM uint32_t DMA0_LEN_REG; /*!< (@ 0x0000000C) DMA receive length register channel 0 */ + __IOM uint32_t DMA0_CTRL_REG; /*!< (@ 0x00000010) Control register for the DMA channel 0 */ + __IOM uint32_t DMA0_IDX_REG; /*!< (@ 0x00000014) Index value of DMA channel 0 */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t DMA1_A_START_REG; /*!< (@ 0x00000020) Start address A of DMA channel 1 */ + __IOM uint32_t DMA1_B_START_REG; /*!< (@ 0x00000024) Start address B of DMA channel 1 */ + __IOM uint32_t DMA1_INT_REG; /*!< (@ 0x00000028) DMA receive interrupt register channel 1 */ + __IOM uint32_t DMA1_LEN_REG; /*!< (@ 0x0000002C) DMA receive length register channel 1 */ + __IOM uint32_t DMA1_CTRL_REG; /*!< (@ 0x00000030) Control register for the DMA channel 1 */ + __IOM uint32_t DMA1_IDX_REG; /*!< (@ 0x00000034) Index value of DMA channel 1 */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t DMA2_A_START_REG; /*!< (@ 0x00000040) Start address A of DMA channel 2 */ + __IOM uint32_t DMA2_B_START_REG; /*!< (@ 0x00000044) Start address B of DMA channel 2 */ + __IOM uint32_t DMA2_INT_REG; /*!< (@ 0x00000048) DMA receive interrupt register channel 2 */ + __IOM uint32_t DMA2_LEN_REG; /*!< (@ 0x0000004C) DMA receive length register channel 2 */ + __IOM uint32_t DMA2_CTRL_REG; /*!< (@ 0x00000050) Control register for the DMA channel 2 */ + __IOM uint32_t DMA2_IDX_REG; /*!< (@ 0x00000054) Index value of DMA channel 2 */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t DMA3_A_START_REG; /*!< (@ 0x00000060) Start address A of DMA channel 3 */ + __IOM uint32_t DMA3_B_START_REG; /*!< (@ 0x00000064) Start address B of DMA channel 3 */ + __IOM uint32_t DMA3_INT_REG; /*!< (@ 0x00000068) DMA receive interrupt register channel 3 */ + __IOM uint32_t DMA3_LEN_REG; /*!< (@ 0x0000006C) DMA receive length register channel 3 */ + __IOM uint32_t DMA3_CTRL_REG; /*!< (@ 0x00000070) Control register for the DMA channel 3 */ + __IOM uint32_t DMA3_IDX_REG; /*!< (@ 0x00000074) Index value of DMA channel 3 */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t DMA4_A_START_REG; /*!< (@ 0x00000080) Start address A of DMA channel 4 */ + __IOM uint32_t DMA4_B_START_REG; /*!< (@ 0x00000084) Start address B of DMA channel 4 */ + __IOM uint32_t DMA4_INT_REG; /*!< (@ 0x00000088) DMA receive interrupt register channel 4 */ + __IOM uint32_t DMA4_LEN_REG; /*!< (@ 0x0000008C) DMA receive length register channel 4 */ + __IOM uint32_t DMA4_CTRL_REG; /*!< (@ 0x00000090) Control register for the DMA channel 4 */ + __IOM uint32_t DMA4_IDX_REG; /*!< (@ 0x00000094) Index value of DMA channel 4 */ + __IM uint32_t RESERVED4[2]; + __IOM uint32_t DMA5_A_START_REG; /*!< (@ 0x000000A0) Start address A of DMA channel 5 */ + __IOM uint32_t DMA5_B_START_REG; /*!< (@ 0x000000A4) Start address B of DMA channel 5 */ + __IOM uint32_t DMA5_INT_REG; /*!< (@ 0x000000A8) DMA receive interrupt register channel 5 */ + __IOM uint32_t DMA5_LEN_REG; /*!< (@ 0x000000AC) DMA receive length register channel 5 */ + __IOM uint32_t DMA5_CTRL_REG; /*!< (@ 0x000000B0) Control register for the DMA channel 5 */ + __IOM uint32_t DMA5_IDX_REG; /*!< (@ 0x000000B4) Index value of DMA channel 5 */ + __IM uint32_t RESERVED5[2]; + __IOM uint32_t DMA6_A_START_REG; /*!< (@ 0x000000C0) Start address A of DMA channel 6 */ + __IOM uint32_t DMA6_B_START_REG; /*!< (@ 0x000000C4) Start address B of DMA channel 6 */ + __IOM uint32_t DMA6_INT_REG; /*!< (@ 0x000000C8) DMA receive interrupt register channel 6 */ + __IOM uint32_t DMA6_LEN_REG; /*!< (@ 0x000000CC) DMA receive length register channel 6 */ + __IOM uint32_t DMA6_CTRL_REG; /*!< (@ 0x000000D0) Control register for the DMA channel 6 */ + __IOM uint32_t DMA6_IDX_REG; /*!< (@ 0x000000D4) Index value of DMA channel 6 */ + __IM uint32_t RESERVED6[2]; + __IOM uint32_t DMA7_A_START_REG; /*!< (@ 0x000000E0) Start address A of DMA channel 7 */ + __IOM uint32_t DMA7_B_START_REG; /*!< (@ 0x000000E4) Start address B of DMA channel 7 */ + __IOM uint32_t DMA7_INT_REG; /*!< (@ 0x000000E8) DMA receive interrupt register channel 7 */ + __IOM uint32_t DMA7_LEN_REG; /*!< (@ 0x000000EC) DMA receive length register channel 7 */ + __IOM uint32_t DMA7_CTRL_REG; /*!< (@ 0x000000F0) Control register for the DMA channel 7 */ + __IOM uint32_t DMA7_IDX_REG; /*!< (@ 0x000000F4) Index value of DMA channel 7 */ + __IM uint32_t RESERVED7[2]; + __IOM uint32_t DMA_REQ_MUX_REG; /*!< (@ 0x00000100) DMA channel assignments */ + __IOM uint32_t DMA_INT_STATUS_REG; /*!< (@ 0x00000104) DMA interrupt status register */ + __IOM uint32_t DMA_CLEAR_INT_REG; /*!< (@ 0x00000108) DMA clear interrupt register */ + __IOM uint32_t DMA_INT_MASK_REG; /*!< (@ 0x0000010C) DMA Interrupt mask register */ +} DMA_Type; /*!< Size = 272 (0x110) */ + + + +/* =========================================================================================================================== */ +/* ================ DW ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DW registers (DW) + */ + +typedef struct { /*!< (@ 0x30020000) DW Structure */ + __IOM uint32_t AHB_DMA_PL1_REG; /*!< (@ 0x00000000) AHB-DMA layer priority level for RFTP (AHB DMA + layer only) */ + __IOM uint32_t AHB_DMA_PL2_REG; /*!< (@ 0x00000004) AHB-DMA layer priority level for LCD (AHB DMA + layer only) */ + __IOM uint32_t AHB_DMA_PL3_REG; /*!< (@ 0x00000008) AHB-DMA layer Priority level for GEN-DMA (AHB + DMA layer only) */ + __IOM uint32_t AHB_DMA_PL4_REG; /*!< (@ 0x0000000C) AHB-DMA layer Priority level for CRYPTO-DMA (AHB + DMA layer only) */ + __IM uint32_t RESERVED[14]; + __IOM uint32_t AHB_DMA_DFLT_MASTER_REG; /*!< (@ 0x00000048) Default master ID number (AHB DMA layer only) */ + __IOM uint32_t AHB_DMA_WTEN_REG; /*!< (@ 0x0000004C) Weighted-Token Arbitration Scheme Enable (AHB + DMA layer only) */ + __IOM uint32_t AHB_DMA_TCL_REG; /*!< (@ 0x00000050) Master clock refresh period (AHB DMA layer only) */ + __IOM uint32_t AHB_DMA_CCLM1_REG; /*!< (@ 0x00000054) USB Master clock tokens (AHB DMA layer only) */ + __IOM uint32_t AHB_DMA_CCLM2_REG; /*!< (@ 0x00000058) GenDMA Master clock tokens (AHB DMA layer only) */ + __IOM uint32_t AHB_DMA_CCLM3_REG; /*!< (@ 0x0000005C) CRYPTO Master clock tokens (AHB DMA layer only) */ + __IOM uint32_t AHB_DMA_CCLM4_REG; /*!< (@ 0x00000060) CRYPTO Master clock tokens (AHB DMA layer only) */ + __IM uint32_t RESERVED1[11]; + __IOM uint32_t AHB_DMA_VERSION_REG; /*!< (@ 0x00000090) Version ID (AHB DMA layer only) */ +} DW_Type; /*!< Size = 148 (0x94) */ + + + +/* =========================================================================================================================== */ +/* ================ GPADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPADC registers (GPADC) + */ + +typedef struct { /*!< (@ 0x50030900) GPADC Structure */ + __IOM uint32_t GP_ADC_CTRL_REG; /*!< (@ 0x00000000) General Purpose ADC Control Register */ + __IOM uint32_t GP_ADC_CTRL2_REG; /*!< (@ 0x00000004) General Purpose ADC Second Control Register */ + __IOM uint32_t GP_ADC_CTRL3_REG; /*!< (@ 0x00000008) General Purpose ADC Third Control Register */ + __IOM uint32_t GP_ADC_OFFP_REG; /*!< (@ 0x0000000C) General Purpose ADC Positive Offset Register */ + __IOM uint32_t GP_ADC_OFFN_REG; /*!< (@ 0x00000010) General Purpose ADC Negative Offset Register */ + __IOM uint32_t GP_ADC_CLEAR_INT_REG; /*!< (@ 0x00000014) General Purpose ADC Clear Interrupt Register */ + __IOM uint32_t GP_ADC_RESULT_REG; /*!< (@ 0x00000018) General Purpose ADC Result Register */ +} GPADC_Type; /*!< Size = 28 (0x1c) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPIO registers (GPIO) + */ + +typedef struct { /*!< (@ 0x50020A00) GPIO Structure */ + __IOM uint32_t P0_DATA_REG; /*!< (@ 0x00000000) P0 Data input / output Register */ + __IOM uint32_t P1_DATA_REG; /*!< (@ 0x00000004) P1 Data input / output Register */ + __IOM uint32_t P0_SET_DATA_REG; /*!< (@ 0x00000008) P0 Set port pins Register */ + __IOM uint32_t P1_SET_DATA_REG; /*!< (@ 0x0000000C) P1 Set port pins Register */ + __IOM uint32_t P0_RESET_DATA_REG; /*!< (@ 0x00000010) P0 Reset port pins Register */ + __IOM uint32_t P1_RESET_DATA_REG; /*!< (@ 0x00000014) P1 Reset port pins Register */ + __IOM uint32_t P0_00_MODE_REG; /*!< (@ 0x00000018) P0_00 Mode Register */ + __IOM uint32_t P0_01_MODE_REG; /*!< (@ 0x0000001C) P0_01 Mode Register */ + __IOM uint32_t P0_02_MODE_REG; /*!< (@ 0x00000020) P0_02 Mode Register */ + __IOM uint32_t P0_03_MODE_REG; /*!< (@ 0x00000024) P0_03 Mode Register */ + __IOM uint32_t P0_04_MODE_REG; /*!< (@ 0x00000028) P0_04 Mode Register */ + __IOM uint32_t P0_05_MODE_REG; /*!< (@ 0x0000002C) P0_05 Mode Register */ + __IOM uint32_t P0_06_MODE_REG; /*!< (@ 0x00000030) P0_06 Mode Register */ + __IOM uint32_t P0_07_MODE_REG; /*!< (@ 0x00000034) P0_07 Mode Register */ + __IOM uint32_t P0_08_MODE_REG; /*!< (@ 0x00000038) P0_08 Mode Register */ + __IOM uint32_t P0_09_MODE_REG; /*!< (@ 0x0000003C) P0_09 Mode Register */ + __IOM uint32_t P0_10_MODE_REG; /*!< (@ 0x00000040) P0_10 Mode Register */ + __IOM uint32_t P0_11_MODE_REG; /*!< (@ 0x00000044) P0_11 Mode Register */ + __IOM uint32_t P0_12_MODE_REG; /*!< (@ 0x00000048) P0_12 Mode Register */ + __IOM uint32_t P0_13_MODE_REG; /*!< (@ 0x0000004C) P0_13 Mode Register */ + __IOM uint32_t P0_14_MODE_REG; /*!< (@ 0x00000050) P0_14 Mode Register */ + __IOM uint32_t P0_15_MODE_REG; /*!< (@ 0x00000054) P0_15 Mode Register */ + __IOM uint32_t P0_16_MODE_REG; /*!< (@ 0x00000058) P0_16 Mode Register */ + __IOM uint32_t P0_17_MODE_REG; /*!< (@ 0x0000005C) P0_17 Mode Register */ + __IOM uint32_t P0_18_MODE_REG; /*!< (@ 0x00000060) P0_18 Mode Register */ + __IOM uint32_t P0_19_MODE_REG; /*!< (@ 0x00000064) P0_19 Mode Register */ + __IOM uint32_t P0_20_MODE_REG; /*!< (@ 0x00000068) P0_20 Mode Register */ + __IOM uint32_t P0_21_MODE_REG; /*!< (@ 0x0000006C) P0_21 Mode Register */ + __IOM uint32_t P0_22_MODE_REG; /*!< (@ 0x00000070) P0_22 Mode Register */ + __IOM uint32_t P0_23_MODE_REG; /*!< (@ 0x00000074) P0_23 Mode Register */ + __IOM uint32_t P0_24_MODE_REG; /*!< (@ 0x00000078) P0_24 Mode Register */ + __IOM uint32_t P0_25_MODE_REG; /*!< (@ 0x0000007C) P0_25 Mode Register */ + __IOM uint32_t P0_26_MODE_REG; /*!< (@ 0x00000080) P0_26 Mode Register */ + __IOM uint32_t P0_27_MODE_REG; /*!< (@ 0x00000084) P0_27 Mode Register */ + __IOM uint32_t P0_28_MODE_REG; /*!< (@ 0x00000088) P0_28 Mode Register */ + __IOM uint32_t P0_29_MODE_REG; /*!< (@ 0x0000008C) P0_29 Mode Register */ + __IOM uint32_t P0_30_MODE_REG; /*!< (@ 0x00000090) P0_30 Mode Register */ + __IOM uint32_t P0_31_MODE_REG; /*!< (@ 0x00000094) P0_31 Mode Register */ + __IOM uint32_t P1_00_MODE_REG; /*!< (@ 0x00000098) P1_00 Mode Register */ + __IOM uint32_t P1_01_MODE_REG; /*!< (@ 0x0000009C) P1_01 Mode Register */ + __IOM uint32_t P1_02_MODE_REG; /*!< (@ 0x000000A0) P1_02 Mode Register */ + __IOM uint32_t P1_03_MODE_REG; /*!< (@ 0x000000A4) P1_03 Mode Register */ + __IOM uint32_t P1_04_MODE_REG; /*!< (@ 0x000000A8) P1_04 Mode Register */ + __IOM uint32_t P1_05_MODE_REG; /*!< (@ 0x000000AC) P1_05 Mode Register */ + __IOM uint32_t P1_06_MODE_REG; /*!< (@ 0x000000B0) P1_06 Mode Register */ + __IOM uint32_t P1_07_MODE_REG; /*!< (@ 0x000000B4) P1_07 Mode Register */ + __IOM uint32_t P1_08_MODE_REG; /*!< (@ 0x000000B8) P1_08 Mode Register */ + __IOM uint32_t P1_09_MODE_REG; /*!< (@ 0x000000BC) P1_09 Mode Register */ + __IOM uint32_t P1_10_MODE_REG; /*!< (@ 0x000000C0) P1_10 Mode Register */ + __IOM uint32_t P1_11_MODE_REG; /*!< (@ 0x000000C4) P1_11 Mode Register */ + __IOM uint32_t P1_12_MODE_REG; /*!< (@ 0x000000C8) P1_12 Mode Register */ + __IOM uint32_t P1_13_MODE_REG; /*!< (@ 0x000000CC) P1_13 Mode Register */ + __IOM uint32_t P1_14_MODE_REG; /*!< (@ 0x000000D0) P1_14 Mode Register */ + __IOM uint32_t P1_15_MODE_REG; /*!< (@ 0x000000D4) P1_15 Mode Register */ + __IOM uint32_t P1_16_MODE_REG; /*!< (@ 0x000000D8) P1_16 Mode Register */ + __IOM uint32_t P1_17_MODE_REG; /*!< (@ 0x000000DC) P1_17 Mode Register */ + __IOM uint32_t P1_18_MODE_REG; /*!< (@ 0x000000E0) P1_18 Mode Register */ + __IOM uint32_t P1_19_MODE_REG; /*!< (@ 0x000000E4) P1_19 Mode Register */ + __IOM uint32_t P1_20_MODE_REG; /*!< (@ 0x000000E8) P1_20 Mode Register */ + __IOM uint32_t P1_21_MODE_REG; /*!< (@ 0x000000EC) P1_21 Mode Register */ + __IOM uint32_t P1_22_MODE_REG; /*!< (@ 0x000000F0) P1_22 Mode Register */ + __IOM uint32_t P0_PADPWR_CTRL_REG; /*!< (@ 0x000000F4) P0 Output Power Control Register */ + __IOM uint32_t P1_PADPWR_CTRL_REG; /*!< (@ 0x000000F8) P1 Output Power Control Register */ + __IOM uint32_t GPIO_CLK_SEL_REG; /*!< (@ 0x000000FC) Select which clock to map on ports P0/P1 */ + __IOM uint32_t PAD_WEAK_CTRL_REG; /*!< (@ 0x00000100) Weak Pads Control Register */ +} GPIO_Type; /*!< Size = 260 (0x104) */ + + + +/* =========================================================================================================================== */ +/* ================ GPREG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPREG registers (GPREG) + */ + +typedef struct { /*!< (@ 0x50040300) GPREG Structure */ + __IOM uint32_t SET_FREEZE_REG; /*!< (@ 0x00000000) Controls freezing of various timers/counters + (incl. DMA and USB). */ + __IOM uint32_t RESET_FREEZE_REG; /*!< (@ 0x00000004) Controls unfreezing of various timers/counters + (incl. DMA and USB). */ + __IOM uint32_t DEBUG_REG; /*!< (@ 0x00000008) Various debug information register. */ + __IOM uint32_t GP_STATUS_REG; /*!< (@ 0x0000000C) General purpose system status register. */ + __IOM uint32_t GP_CONTROL_REG; /*!< (@ 0x00000010) General purpose system control register. */ + __IM uint32_t RESERVED; + __IOM uint32_t USBPAD_REG; /*!< (@ 0x00000018) USB pads control register */ +} GPREG_Type; /*!< Size = 28 (0x1c) */ + + + +/* =========================================================================================================================== */ +/* ================ I2C ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C registers (I2C) + */ + +typedef struct { /*!< (@ 0x50020600) I2C Structure */ + __IOM uint32_t I2C_CON_REG; /*!< (@ 0x00000000) I2C Control Register */ + __IOM uint32_t I2C_TAR_REG; /*!< (@ 0x00000004) I2C Target Address Register */ + __IOM uint32_t I2C_SAR_REG; /*!< (@ 0x00000008) I2C Slave Address Register */ + __IOM uint32_t I2C_HS_MADDR_REG; /*!< (@ 0x0000000C) I2C High Speed Master Mode Code Address Register */ + __IOM uint32_t I2C_DATA_CMD_REG; /*!< (@ 0x00000010) I2C Rx/Tx Data Buffer and Command Register */ + __IOM uint32_t I2C_SS_SCL_HCNT_REG; /*!< (@ 0x00000014) Standard Speed I2C Clock SCL High Count Register */ + __IOM uint32_t I2C_SS_SCL_LCNT_REG; /*!< (@ 0x00000018) Standard Speed I2C Clock SCL Low Count Register */ + __IOM uint32_t I2C_FS_SCL_HCNT_REG; /*!< (@ 0x0000001C) Fast Speed I2C Clock SCL High Count Register */ + __IOM uint32_t I2C_FS_SCL_LCNT_REG; /*!< (@ 0x00000020) Fast Speed I2C Clock SCL Low Count Register */ + __IOM uint32_t I2C_HS_SCL_HCNT_REG; /*!< (@ 0x00000024) High Speed I2C Clock SCL High Count Register */ + __IOM uint32_t I2C_HS_SCL_LCNT_REG; /*!< (@ 0x00000028) High Speed I2C Clock SCL Low Count Register */ + __IOM uint32_t I2C_INTR_STAT_REG; /*!< (@ 0x0000002C) I2C Interrupt Status Register */ + __IOM uint32_t I2C_INTR_MASK_REG; /*!< (@ 0x00000030) I2C Interrupt Mask Register */ + __IOM uint32_t I2C_RAW_INTR_STAT_REG; /*!< (@ 0x00000034) I2C Raw Interrupt Status Register */ + __IOM uint32_t I2C_RX_TL_REG; /*!< (@ 0x00000038) I2C Receive FIFO Threshold Register */ + __IOM uint32_t I2C_TX_TL_REG; /*!< (@ 0x0000003C) I2C Transmit FIFO Threshold Register */ + __IOM uint32_t I2C_CLR_INTR_REG; /*!< (@ 0x00000040) Clear Combined and Individual Interrupt Register */ + __IOM uint32_t I2C_CLR_RX_UNDER_REG; /*!< (@ 0x00000044) Clear RX_UNDER Interrupt Register */ + __IOM uint32_t I2C_CLR_RX_OVER_REG; /*!< (@ 0x00000048) Clear RX_OVER Interrupt Register */ + __IOM uint32_t I2C_CLR_TX_OVER_REG; /*!< (@ 0x0000004C) Clear TX_OVER Interrupt Register */ + __IOM uint32_t I2C_CLR_RD_REQ_REG; /*!< (@ 0x00000050) Clear RD_REQ Interrupt Register */ + __IOM uint32_t I2C_CLR_TX_ABRT_REG; /*!< (@ 0x00000054) Clear TX_ABRT Interrupt Register */ + __IOM uint32_t I2C_CLR_RX_DONE_REG; /*!< (@ 0x00000058) Clear RX_DONE Interrupt Register */ + __IOM uint32_t I2C_CLR_ACTIVITY_REG; /*!< (@ 0x0000005C) Clear ACTIVITY Interrupt Register */ + __IOM uint32_t I2C_CLR_STOP_DET_REG; /*!< (@ 0x00000060) Clear STOP_DET Interrupt Register */ + __IOM uint32_t I2C_CLR_START_DET_REG; /*!< (@ 0x00000064) Clear START_DET Interrupt Register */ + __IOM uint32_t I2C_CLR_GEN_CALL_REG; /*!< (@ 0x00000068) Clear GEN_CALL Interrupt Register */ + __IOM uint32_t I2C_ENABLE_REG; /*!< (@ 0x0000006C) I2C Enable Register */ + __IOM uint32_t I2C_STATUS_REG; /*!< (@ 0x00000070) I2C Status Register */ + __IOM uint32_t I2C_TXFLR_REG; /*!< (@ 0x00000074) I2C Transmit FIFO Level Register */ + __IOM uint32_t I2C_RXFLR_REG; /*!< (@ 0x00000078) I2C Receive FIFO Level Register */ + __IOM uint32_t I2C_SDA_HOLD_REG; /*!< (@ 0x0000007C) I2C SDA Hold Time Length Register */ + __IOM uint32_t I2C_TX_ABRT_SOURCE_REG; /*!< (@ 0x00000080) I2C Transmit Abort Source Register */ + __IM uint32_t RESERVED; + __IOM uint32_t I2C_DMA_CR_REG; /*!< (@ 0x00000088) DMA Control Register */ + __IOM uint32_t I2C_DMA_TDLR_REG; /*!< (@ 0x0000008C) DMA Transmit Data Level Register */ + __IOM uint32_t I2C_DMA_RDLR_REG; /*!< (@ 0x00000090) I2C Receive Data Level Register */ + __IOM uint32_t I2C_SDA_SETUP_REG; /*!< (@ 0x00000094) I2C SDA Setup Register */ + __IOM uint32_t I2C_ACK_GENERAL_CALL_REG; /*!< (@ 0x00000098) I2C ACK General Call Register */ + __IOM uint32_t I2C_ENABLE_STATUS_REG; /*!< (@ 0x0000009C) I2C Enable Status Register */ + __IOM uint32_t I2C_IC_FS_SPKLEN_REG; /*!< (@ 0x000000A0) I2C SS and FS spike suppression limit Size */ + __IOM uint32_t I2C_IC_HS_SPKLEN_REG; /*!< (@ 0x000000A4) I2C HS spike suppression limit Size */ +} I2C_Type; /*!< Size = 168 (0xa8) */ + + + +/* =========================================================================================================================== */ +/* ================ I2C2 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C2 registers (I2C2) + */ + +typedef struct { /*!< (@ 0x50020700) I2C2 Structure */ + __IOM uint32_t I2C2_CON_REG; /*!< (@ 0x00000000) I2C Control Register */ + __IOM uint32_t I2C2_TAR_REG; /*!< (@ 0x00000004) I2C Target Address Register */ + __IOM uint32_t I2C2_SAR_REG; /*!< (@ 0x00000008) I2C Slave Address Register */ + __IOM uint32_t I2C2_HS_MADDR_REG; /*!< (@ 0x0000000C) I2C High Speed Master Mode Code Address Register */ + __IOM uint32_t I2C2_DATA_CMD_REG; /*!< (@ 0x00000010) I2C Rx/Tx Data Buffer and Command Register */ + __IOM uint32_t I2C2_SS_SCL_HCNT_REG; /*!< (@ 0x00000014) Standard Speed I2C Clock SCL High Count Register */ + __IOM uint32_t I2C2_SS_SCL_LCNT_REG; /*!< (@ 0x00000018) Standard Speed I2C Clock SCL Low Count Register */ + __IOM uint32_t I2C2_FS_SCL_HCNT_REG; /*!< (@ 0x0000001C) Fast Speed I2C Clock SCL High Count Register */ + __IOM uint32_t I2C2_FS_SCL_LCNT_REG; /*!< (@ 0x00000020) Fast Speed I2C Clock SCL Low Count Register */ + __IOM uint32_t I2C2_HS_SCL_HCNT_REG; /*!< (@ 0x00000024) High Speed I2C Clock SCL High Count Register */ + __IOM uint32_t I2C2_HS_SCL_LCNT_REG; /*!< (@ 0x00000028) High Speed I2C Clock SCL Low Count Register */ + __IOM uint32_t I2C2_INTR_STAT_REG; /*!< (@ 0x0000002C) I2C Interrupt Status Register */ + __IOM uint32_t I2C2_INTR_MASK_REG; /*!< (@ 0x00000030) I2C Interrupt Mask Register */ + __IOM uint32_t I2C2_RAW_INTR_STAT_REG; /*!< (@ 0x00000034) I2C Raw Interrupt Status Register */ + __IOM uint32_t I2C2_RX_TL_REG; /*!< (@ 0x00000038) I2C Receive FIFO Threshold Register */ + __IOM uint32_t I2C2_TX_TL_REG; /*!< (@ 0x0000003C) I2C Transmit FIFO Threshold Register */ + __IOM uint32_t I2C2_CLR_INTR_REG; /*!< (@ 0x00000040) Clear Combined and Individual Interrupt Register */ + __IOM uint32_t I2C2_CLR_RX_UNDER_REG; /*!< (@ 0x00000044) Clear RX_UNDER Interrupt Register */ + __IOM uint32_t I2C2_CLR_RX_OVER_REG; /*!< (@ 0x00000048) Clear RX_OVER Interrupt Register */ + __IOM uint32_t I2C2_CLR_TX_OVER_REG; /*!< (@ 0x0000004C) Clear TX_OVER Interrupt Register */ + __IOM uint32_t I2C2_CLR_RD_REQ_REG; /*!< (@ 0x00000050) Clear RD_REQ Interrupt Register */ + __IOM uint32_t I2C2_CLR_TX_ABRT_REG; /*!< (@ 0x00000054) Clear TX_ABRT Interrupt Register */ + __IOM uint32_t I2C2_CLR_RX_DONE_REG; /*!< (@ 0x00000058) Clear RX_DONE Interrupt Register */ + __IOM uint32_t I2C2_CLR_ACTIVITY_REG; /*!< (@ 0x0000005C) Clear ACTIVITY Interrupt Register */ + __IOM uint32_t I2C2_CLR_STOP_DET_REG; /*!< (@ 0x00000060) Clear STOP_DET Interrupt Register */ + __IOM uint32_t I2C2_CLR_START_DET_REG; /*!< (@ 0x00000064) Clear START_DET Interrupt Register */ + __IOM uint32_t I2C2_CLR_GEN_CALL_REG; /*!< (@ 0x00000068) Clear GEN_CALL Interrupt Register */ + __IOM uint32_t I2C2_ENABLE_REG; /*!< (@ 0x0000006C) I2C Enable Register */ + __IOM uint32_t I2C2_STATUS_REG; /*!< (@ 0x00000070) I2C Status Register */ + __IOM uint32_t I2C2_TXFLR_REG; /*!< (@ 0x00000074) I2C Transmit FIFO Level Register */ + __IOM uint32_t I2C2_RXFLR_REG; /*!< (@ 0x00000078) I2C Receive FIFO Level Register */ + __IOM uint32_t I2C2_SDA_HOLD_REG; /*!< (@ 0x0000007C) I2C SDA Hold Time Length Register */ + __IOM uint32_t I2C2_TX_ABRT_SOURCE_REG; /*!< (@ 0x00000080) I2C Transmit Abort Source Register */ + __IM uint32_t RESERVED; + __IOM uint32_t I2C2_DMA_CR_REG; /*!< (@ 0x00000088) DMA Control Register */ + __IOM uint32_t I2C2_DMA_TDLR_REG; /*!< (@ 0x0000008C) DMA Transmit Data Level Register */ + __IOM uint32_t I2C2_DMA_RDLR_REG; /*!< (@ 0x00000090) I2C Receive Data Level Register */ + __IOM uint32_t I2C2_SDA_SETUP_REG; /*!< (@ 0x00000094) I2C SDA Setup Register */ + __IOM uint32_t I2C2_ACK_GENERAL_CALL_REG; /*!< (@ 0x00000098) I2C ACK General Call Register */ + __IOM uint32_t I2C2_ENABLE_STATUS_REG; /*!< (@ 0x0000009C) I2C Enable Status Register */ + __IOM uint32_t I2C2_IC_FS_SPKLEN_REG; /*!< (@ 0x000000A0) I2C SS and FS spike suppression limit Size */ + __IOM uint32_t I2C2_IC_HS_SPKLEN_REG; /*!< (@ 0x000000A4) I2C HS spike suppression limit Size */ +} I2C2_Type; /*!< Size = 168 (0xa8) */ + + + +/* =========================================================================================================================== */ +/* ================ LCDC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief LCDC registers (LCDC) + */ + +typedef struct { /*!< (@ 0x30030000) LCDC Structure */ + __IOM uint32_t LCDC_MODE_REG; /*!< (@ 0x00000000) Display Mode */ + __IOM uint32_t LCDC_CLKCTRL_REG; /*!< (@ 0x00000004) Clock Divider */ + __IOM uint32_t LCDC_BGCOLOR_REG; /*!< (@ 0x00000008) Background Color */ + __IOM uint32_t LCDC_RESXY_REG; /*!< (@ 0x0000000C) Resolution X,Y */ + __IM uint32_t RESERVED; + __IOM uint32_t LCDC_FRONTPORCHXY_REG; /*!< (@ 0x00000014) Front Porch X and Y */ + __IOM uint32_t LCDC_BLANKINGXY_REG; /*!< (@ 0x00000018) Blanking X and Y */ + __IOM uint32_t LCDC_BACKPORCHXY_REG; /*!< (@ 0x0000001C) Back Porch X and Y */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t LCDC_DBIB_CFG_REG; /*!< (@ 0x00000028) MIPI Config Register */ + __IOM uint32_t LCDC_GPIO_REG; /*!< (@ 0x0000002C) General Purpose IO (2-bits) */ + __IOM uint32_t LCDC_LAYER0_MODE_REG; /*!< (@ 0x00000030) Layer0 Mode */ + __IOM uint32_t LCDC_LAYER0_STARTXY_REG; /*!< (@ 0x00000034) Layer0 Start XY */ + __IOM uint32_t LCDC_LAYER0_SIZEXY_REG; /*!< (@ 0x00000038) Layer0 Size XY */ + __IOM uint32_t LCDC_LAYER0_BASEADDR_REG; /*!< (@ 0x0000003C) Layer0 Base Addr */ + __IOM uint32_t LCDC_LAYER0_STRIDE_REG; /*!< (@ 0x00000040) Layer0 Stride */ + __IOM uint32_t LCDC_LAYER0_RESXY_REG; /*!< (@ 0x00000044) Layer0 Res XY */ + __IM uint32_t RESERVED2[18]; + __IOM uint32_t LCDC_JDI_RESXY_REG; /*!< (@ 0x00000090) Resolution XY for the JDI parallel I/F */ + __IOM uint32_t LCDC_JDI_FBX_BLANKING_REG; /*!< (@ 0x00000094) Horizontal front/back blanking (hck half periods) */ + __IOM uint32_t LCDC_JDI_FBY_BLANKING_REG; /*!< (@ 0x00000098) Vertical front/back blanking (vck half periods) */ + __IOM uint32_t LCDC_JDI_HCK_WIDTH_REG; /*!< (@ 0x0000009C) HCK high/low width */ + __IOM uint32_t LCDC_JDI_XRST_WIDTH_REG; /*!< (@ 0x000000A0) XRST width */ + __IOM uint32_t LCDC_JDI_VST_DELAY_REG; /*!< (@ 0x000000A4) XRST-to-VST delay */ + __IOM uint32_t LCDC_JDI_VST_WIDTH_REG; /*!< (@ 0x000000A8) VST width */ + __IOM uint32_t LCDC_JDI_VCK_DELAY_REG; /*!< (@ 0x000000AC) XRST-to-VCK delay */ + __IOM uint32_t LCDC_JDI_HST_DELAY_REG; /*!< (@ 0x000000B0) VCK-to-HST delay */ + __IOM uint32_t LCDC_JDI_HST_WIDTH_REG; /*!< (@ 0x000000B4) HST width */ + __IOM uint32_t LCDC_JDI_ENB_START_HLINE_REG; /*!< (@ 0x000000B8) ENB start horizontal line */ + __IOM uint32_t LCDC_JDI_ENB_END_HLINE_REG; /*!< (@ 0x000000BC) ENB end horizontal line */ + __IOM uint32_t LCDC_JDI_ENB_START_CLK_REG; /*!< (@ 0x000000C0) ENB start delay */ + __IOM uint32_t LCDC_JDI_ENB_WIDTH_CLK_REG; /*!< (@ 0x000000C4) ENB width */ + __IM uint32_t RESERVED3[8]; + __IOM uint32_t LCDC_DBIB_CMD_REG; /*!< (@ 0x000000E8) MIPI DBIB Command Register */ + __IM uint32_t RESERVED4[2]; + __IOM uint32_t LCDC_IDREG_REG; /*!< (@ 0x000000F4) Identification Register */ + __IOM uint32_t LCDC_INTERRUPT_REG; /*!< (@ 0x000000F8) Interrupt Register */ + __IOM uint32_t LCDC_STATUS_REG; /*!< (@ 0x000000FC) Status Register */ + __IM uint32_t RESERVED5[33]; + __IOM uint32_t LCDC_CRC_REG; /*!< (@ 0x00000184) CRC check */ + __IOM uint32_t LCDC_LAYER0_OFFSETX_REG; /*!< (@ 0x00000188) Layer0 OffsetX and DMA prefetch */ +} LCDC_Type; /*!< Size = 396 (0x18c) */ + + + +/* =========================================================================================================================== */ +/* ================ LRA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief LRA registers (LRA) + */ + +typedef struct { /*!< (@ 0x50030A00) LRA Structure */ + __IOM uint32_t LRA_CTRL1_REG; /*!< (@ 0x00000000) General Purpose LRA Control Register */ + __IOM uint32_t LRA_CTRL2_REG; /*!< (@ 0x00000004) General Purpose LRA Control Register */ + __IOM uint32_t LRA_CTRL3_REG; /*!< (@ 0x00000008) General Purpose LRA Control Register */ + __IOM uint32_t LRA_FLT_SMP1_REG; /*!< (@ 0x0000000C) LRA Sample Register */ + __IOM uint32_t LRA_FLT_SMP2_REG; /*!< (@ 0x00000010) LRA Sample Register */ + __IOM uint32_t LRA_FLT_SMP3_REG; /*!< (@ 0x00000014) LRA Sample Register */ + __IOM uint32_t LRA_FLT_SMP4_REG; /*!< (@ 0x00000018) LRA Sample Register */ + __IOM uint32_t LRA_FLT_SMP5_REG; /*!< (@ 0x0000001C) LRA Sample Register */ + __IOM uint32_t LRA_FLT_SMP6_REG; /*!< (@ 0x00000020) LRA Sample Register */ + __IOM uint32_t LRA_FLT_SMP7_REG; /*!< (@ 0x00000024) LRA Sample Register */ + __IOM uint32_t LRA_FLT_SMP8_REG; /*!< (@ 0x00000028) LRA Sample Register */ + __IOM uint32_t LRA_FLT_COEF1_REG; /*!< (@ 0x0000002C) LRA Filter Coefficient Register */ + __IOM uint32_t LRA_FLT_COEF2_REG; /*!< (@ 0x00000030) LRA Filter Coefficient Register */ + __IOM uint32_t LRA_FLT_COEF3_REG; /*!< (@ 0x00000034) LRA Filter Coefficient Register */ + __IOM uint32_t LRA_BRD_LS_REG; /*!< (@ 0x00000038) LRA Bridge Register */ + __IOM uint32_t LRA_BRD_HS_REG; /*!< (@ 0x0000003C) LRA Bridge Register */ + __IOM uint32_t LRA_BRD_STAT_REG; /*!< (@ 0x00000040) LRA Bridge Staus Register */ + __IOM uint32_t LRA_ADC_CTRL1_REG; /*!< (@ 0x00000044) General Purpose ADC Control Register */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t LRA_ADC_RESULT_REG; /*!< (@ 0x00000050) General Purpose ADC Result Register */ + __IOM uint32_t LRA_LDO_REG; /*!< (@ 0x00000054) LRA LDO Regsiter */ + __IOM uint32_t LRA_DFT_REG; /*!< (@ 0x00000058) LRA test Register */ +} LRA_Type; /*!< Size = 92 (0x5c) */ + + + +/* =========================================================================================================================== */ +/* ================ MEMCTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MEMCTRL registers (MEMCTRL) + */ + +typedef struct { /*!< (@ 0x50050000) MEMCTRL Structure */ + __IM uint32_t RESERVED; + __IOM uint32_t MEM_PRIO_REG; /*!< (@ 0x00000004) Priority Control Register */ + __IOM uint32_t MEM_STALL_REG; /*!< (@ 0x00000008) Maximum Stall cycles Control Register */ + __IOM uint32_t MEM_STATUS_REG; /*!< (@ 0x0000000C) Memory Arbiter Status Register */ + __IOM uint32_t MEM_STATUS2_REG; /*!< (@ 0x00000010) RAM cells Status Register */ + __IM uint32_t RESERVED1[3]; + __IOM uint32_t CMI_CODE_BASE_REG; /*!< (@ 0x00000020) CMAC code Base Address Register */ + __IOM uint32_t CMI_DATA_BASE_REG; /*!< (@ 0x00000024) CMAC data Base Address Register */ + __IOM uint32_t CMI_SHARED_BASE_REG; /*!< (@ 0x00000028) CMAC shared data Base Address Register */ + __IOM uint32_t CMI_END_REG; /*!< (@ 0x0000002C) CMAC end Address Register */ + __IOM uint32_t SNC_BASE_REG; /*!< (@ 0x00000030) Sensor Node Controller Base Address Register */ + __IM uint32_t RESERVED2[16]; + __IOM uint32_t BUSY_SET_REG; /*!< (@ 0x00000074) BSR Set Register */ + __IOM uint32_t BUSY_RESET_REG; /*!< (@ 0x00000078) BSR Reset Register */ + __IOM uint32_t BUSY_STAT_REG; /*!< (@ 0x0000007C) BSR Status Register */ +} MEMCTRL_Type; /*!< Size = 128 (0x80) */ + + + +/* =========================================================================================================================== */ +/* ================ OTPC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief OTPC registers (OTPC) + */ + +typedef struct { /*!< (@ 0x30070000) OTPC Structure */ + __IOM uint32_t OTPC_MODE_REG; /*!< (@ 0x00000000) Mode register */ + __IOM uint32_t OTPC_STAT_REG; /*!< (@ 0x00000004) Status register */ + __IOM uint32_t OTPC_PADDR_REG; /*!< (@ 0x00000008) The address of the word that will be programmed, + when the PROG mode is used. */ + __IOM uint32_t OTPC_PWORD_REG; /*!< (@ 0x0000000C) The 32-bit word that will be programmed, when + the PROG mode is used. */ + __IOM uint32_t OTPC_TIM1_REG; /*!< (@ 0x00000010) Various timing parameters of the OTP cell. */ + __IOM uint32_t OTPC_TIM2_REG; /*!< (@ 0x00000014) Various timing parameters of the OTP cell. */ +} OTPC_Type; /*!< Size = 24 (0x18) */ + + + +/* =========================================================================================================================== */ +/* ================ PDC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PDC registers (PDC) + */ + +typedef struct { /*!< (@ 0x50000200) PDC Structure */ + __IOM uint32_t PDC_CTRL0_REG; /*!< (@ 0x00000000) PDC control register */ + __IOM uint32_t PDC_CTRL1_REG; /*!< (@ 0x00000004) PDC control register */ + __IOM uint32_t PDC_CTRL2_REG; /*!< (@ 0x00000008) PDC control register */ + __IOM uint32_t PDC_CTRL3_REG; /*!< (@ 0x0000000C) PDC control register */ + __IOM uint32_t PDC_CTRL4_REG; /*!< (@ 0x00000010) PDC control register */ + __IOM uint32_t PDC_CTRL5_REG; /*!< (@ 0x00000014) PDC control register */ + __IOM uint32_t PDC_CTRL6_REG; /*!< (@ 0x00000018) PDC control register */ + __IOM uint32_t PDC_CTRL7_REG; /*!< (@ 0x0000001C) PDC control register */ + __IOM uint32_t PDC_CTRL8_REG; /*!< (@ 0x00000020) PDC control register */ + __IOM uint32_t PDC_CTRL9_REG; /*!< (@ 0x00000024) PDC control register */ + __IOM uint32_t PDC_CTRL10_REG; /*!< (@ 0x00000028) PDC control register */ + __IOM uint32_t PDC_CTRL11_REG; /*!< (@ 0x0000002C) PDC control register */ + __IOM uint32_t PDC_CTRL12_REG; /*!< (@ 0x00000030) PDC control register */ + __IOM uint32_t PDC_CTRL13_REG; /*!< (@ 0x00000034) PDC control register */ + __IOM uint32_t PDC_CTRL14_REG; /*!< (@ 0x00000038) PDC control register */ + __IOM uint32_t PDC_CTRL15_REG; /*!< (@ 0x0000003C) PDC control register */ + __IM uint32_t RESERVED[16]; + __IOM uint32_t PDC_ACKNOWLEDGE_REG; /*!< (@ 0x00000080) Clear a pending PDC bit */ + __IOM uint32_t PDC_PENDING_REG; /*!< (@ 0x00000084) Shows any pending wakup event */ + __IOM uint32_t PDC_PENDING_SNC_REG; /*!< (@ 0x00000088) Shows any pending IRQ to SNC */ + __IOM uint32_t PDC_PENDING_CM33_REG; /*!< (@ 0x0000008C) Shows any pending IRQ to CM33 */ + __IOM uint32_t PDC_PENDING_CMAC_REG; /*!< (@ 0x00000090) Shows any pending IRQ to CM33 */ + __IOM uint32_t PDC_SET_PENDING_REG; /*!< (@ 0x00000094) Set a pending PDC bit */ +} PDC_Type; /*!< Size = 152 (0x98) */ + + + +/* =========================================================================================================================== */ +/* ================ PWMLED ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PWMLED registers (PWMLED) + */ + +typedef struct { /*!< (@ 0x50030500) PWMLED Structure */ + __IOM uint32_t PWMLED_DUTY_CYCLE_LED1_REG; /*!< (@ 0x00000000) Defines duty cycle for PWM1 */ + __IOM uint32_t PWMLED_DUTY_CYCLE_LED2_REG; /*!< (@ 0x00000004) Defines duty cycle for PWM2 */ + __IOM uint32_t PWMLED_FREQUENCY_REG; /*!< (@ 0x00000008) Defines the PWM frequecny */ + __IOM uint32_t PWMLED_CTRL_REG; /*!< (@ 0x0000000C) PWM Control register */ +} PWMLED_Type; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ QSPIC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief QSPIC registers (QSPIC) + */ + +typedef struct { /*!< (@ 0x38000000) QSPIC Structure */ + __IOM uint32_t QSPIC_CTRLBUS_REG; /*!< (@ 0x00000000) SPI Bus control register for the Manual mode */ + __IOM uint32_t QSPIC_CTRLMODE_REG; /*!< (@ 0x00000004) Mode Control register */ + __IOM uint32_t QSPIC_RECVDATA_REG; /*!< (@ 0x00000008) Received data for the Manual mode */ + __IOM uint32_t QSPIC_BURSTCMDA_REG; /*!< (@ 0x0000000C) The way of reading in Auto mode (command register + A) */ + __IOM uint32_t QSPIC_BURSTCMDB_REG; /*!< (@ 0x00000010) The way of reading in Auto mode (command register + B) */ + __IOM uint32_t QSPIC_STATUS_REG; /*!< (@ 0x00000014) The status register of the QSPI controller */ + __IOM uint32_t QSPIC_WRITEDATA_REG; /*!< (@ 0x00000018) Write data to SPI Bus for the Manual mode */ + __IOM uint32_t QSPIC_READDATA_REG; /*!< (@ 0x0000001C) Read data from SPI Bus for the Manual mode */ + __IOM uint32_t QSPIC_DUMMYDATA_REG; /*!< (@ 0x00000020) Send dummy clocks to SPI Bus for the Manual mode */ + __IOM uint32_t QSPIC_ERASECTRL_REG; /*!< (@ 0x00000024) QSPI Erase control register */ + __IOM uint32_t QSPIC_ERASECMDA_REG; /*!< (@ 0x00000028) The way of erasing in Auto mode (command register + A) */ + __IOM uint32_t QSPIC_ERASECMDB_REG; /*!< (@ 0x0000002C) The way of erasing in Auto mode (command register + B) */ + __IOM uint32_t QSPIC_BURSTBRK_REG; /*!< (@ 0x00000030) Read break sequence in Auto mode */ + __IOM uint32_t QSPIC_STATUSCMD_REG; /*!< (@ 0x00000034) The way of reading the status of external device + in Auto mode */ + __IOM uint32_t QSPIC_CHCKERASE_REG; /*!< (@ 0x00000038) Check erase progress in Auto mode */ + __IOM uint32_t QSPIC_GP_REG; /*!< (@ 0x0000003C) QSPI General Purpose control register */ + __IOM uint32_t QSPIC_UCODE_START; /*!< (@ 0x00000040) QSPIC uCode memory */ + __IM uint32_t RESERVED[15]; + __IOM uint32_t QSPIC_CTR_CTRL_REG; /*!< (@ 0x00000080) Control register for the decryption engine of + the QSPIC */ + __IOM uint32_t QSPIC_CTR_SADDR_REG; /*!< (@ 0x00000084) Start address of the encrypted content in the + QSPI flash */ + __IOM uint32_t QSPIC_CTR_EADDR_REG; /*!< (@ 0x00000088) End address of the encrypted content in the QSPI + flash */ + __IOM uint32_t QSPIC_CTR_NONCE_0_3_REG; /*!< (@ 0x0000008C) Nonce bytes 0 to 3 for the AES-CTR algorithm */ + __IOM uint32_t QSPIC_CTR_NONCE_4_7_REG; /*!< (@ 0x00000090) Nonce bytes 4 to 7 for the AES-CTR algorithm */ + __IOM uint32_t QSPIC_CTR_KEY_0_3_REG; /*!< (@ 0x00000094) Key bytes 0 to 3 for the AES-CTR algorithm */ + __IOM uint32_t QSPIC_CTR_KEY_4_7_REG; /*!< (@ 0x00000098) Key bytes 4 to 7 for the AES-CTR algorithm */ + __IOM uint32_t QSPIC_CTR_KEY_8_11_REG; /*!< (@ 0x0000009C) Key bytes 8 to 11 for the AES-CTR algorithm */ + __IOM uint32_t QSPIC_CTR_KEY_12_15_REG; /*!< (@ 0x000000A0) Key bytes 12 to 15 for the AES-CTR algorithm */ + __IOM uint32_t QSPIC_CTR_KEY_16_19_REG; /*!< (@ 0x000000A4) Key bytes 16 to 19 for the AES-CTR algorithm */ + __IOM uint32_t QSPIC_CTR_KEY_20_23_REG; /*!< (@ 0x000000A8) Key bytes 20 to 23 for the AES-CTR algorithm */ + __IOM uint32_t QSPIC_CTR_KEY_24_27_REG; /*!< (@ 0x000000AC) Key bytes 24 to 27 for the AES-CTR algorithm */ + __IOM uint32_t QSPIC_CTR_KEY_28_31_REG; /*!< (@ 0x000000B0) Key bytes 28 to 31 for the AES-CTR algorithm */ +} QSPIC_Type; /*!< Size = 180 (0xb4) */ + + + +/* =========================================================================================================================== */ +/* ================ QSPIC2 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief QSPIC2 registers (QSPIC2) + */ + +typedef struct { /*!< (@ 0x34000000) QSPIC2 Structure */ + __IOM uint32_t QSPIC2_CTRLBUS_REG; /*!< (@ 0x00000000) SPI Bus control register for the Manual mode */ + __IOM uint32_t QSPIC2_CTRLMODE_REG; /*!< (@ 0x00000004) Mode control register */ + __IOM uint32_t QSPIC2_RECVDATA_REG; /*!< (@ 0x00000008) Received data for the Manual mode */ + __IOM uint32_t QSPIC2_BURSTCMDA_REG; /*!< (@ 0x0000000C) The way of reading in Auto mode (command register + A) */ + __IOM uint32_t QSPIC2_BURSTCMDB_REG; /*!< (@ 0x00000010) The way of reading in Auto mode (command register + B) */ + __IOM uint32_t QSPIC2_STATUS_REG; /*!< (@ 0x00000014) The status register of the QSPI controller */ + __IOM uint32_t QSPIC2_WRITEDATA_REG; /*!< (@ 0x00000018) Write data to SPI Bus for the Manual mode */ + __IOM uint32_t QSPIC2_READDATA_REG; /*!< (@ 0x0000001C) Read data from SPI Bus for the Manual mode */ + __IOM uint32_t QSPIC2_DUMMYDATA_REG; /*!< (@ 0x00000020) Send dummy clocks to SPI Bus for the Manual mode */ + __IOM uint32_t QSPIC2_ERASECTRL_REG; /*!< (@ 0x00000024) Erase control register */ + __IOM uint32_t QSPIC2_ERASECMDA_REG; /*!< (@ 0x00000028) The way of erasing in Auto mode (command register + A) */ + __IOM uint32_t QSPIC2_ERASECMDB_REG; /*!< (@ 0x0000002C) The way of erasing in Auto mode (command register + B) */ + __IOM uint32_t QSPIC2_BURSTBRK_REG; /*!< (@ 0x00000030) Read break sequence in Auto mode */ + __IOM uint32_t QSPIC2_STATUSCMD_REG; /*!< (@ 0x00000034) The way of reading the status of external device + in Auto mode */ + __IOM uint32_t QSPIC2_CHCKERASE_REG; /*!< (@ 0x00000038) Check erase progress in Auto mode */ + __IOM uint32_t QSPIC2_GP_REG; /*!< (@ 0x0000003C) General purpose QSPIC2 register */ + __IOM uint32_t QSPIC2_AWRITECMD_REG; /*!< (@ 0x00000040) The way of writing in Auto mode when the external + device is a serial SRAM */ + __IOM uint32_t QSPIC2_MEMBLEN_REG; /*!< (@ 0x00000044) External memory burst length configuration */ +} QSPIC2_Type; /*!< Size = 72 (0x48) */ + + + +/* =========================================================================================================================== */ +/* ================ RFMON ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief RFMON registers (RFMON) + */ + +typedef struct { /*!< (@ 0x50040600) RFMON Structure */ + __IOM uint32_t RFMON_CTRL_REG; /*!< (@ 0x00000000) Control register */ + __IOM uint32_t RFMON_ADDR_REG; /*!< (@ 0x00000004) AHB master start address */ + __IOM uint32_t RFMON_LEN_REG; /*!< (@ 0x00000008) Data length register */ + __IOM uint32_t RFMON_STAT_REG; /*!< (@ 0x0000000C) Status register */ + __IOM uint32_t RFMON_CRV_ADDR_REG; /*!< (@ 0x00000010) AHB master current address */ + __IOM uint32_t RFMON_CRV_LEN_REG; /*!< (@ 0x00000014) The remaining data to be transferred */ +} RFMON_Type; /*!< Size = 24 (0x18) */ + + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief RTC registers (RTC) + */ + +typedef struct { /*!< (@ 0x50000400) RTC Structure */ + __IOM uint32_t RTC_CONTROL_REG; /*!< (@ 0x00000000) RTC Control Register */ + __IOM uint32_t RTC_HOUR_MODE_REG; /*!< (@ 0x00000004) RTC Hour Mode Register */ + __IOM uint32_t RTC_TIME_REG; /*!< (@ 0x00000008) RTC Time Register */ + __IOM uint32_t RTC_CALENDAR_REG; /*!< (@ 0x0000000C) RTC Calendar Register */ + __IOM uint32_t RTC_TIME_ALARM_REG; /*!< (@ 0x00000010) RTC Time Alarm Register */ + __IOM uint32_t RTC_CALENDAR_ALARM_REG; /*!< (@ 0x00000014) RTC Calendar Alram Register */ + __IOM uint32_t RTC_ALARM_ENABLE_REG; /*!< (@ 0x00000018) RTC Alarm Enable Register */ + __IOM uint32_t RTC_EVENT_FLAGS_REG; /*!< (@ 0x0000001C) RTC Event Flags Register */ + __IOM uint32_t RTC_INTERRUPT_ENABLE_REG; /*!< (@ 0x00000020) RTC Interrupt Enable Register */ + __IOM uint32_t RTC_INTERRUPT_DISABLE_REG; /*!< (@ 0x00000024) RTC Interrupt Disable Register */ + __IOM uint32_t RTC_INTERRUPT_MASK_REG; /*!< (@ 0x00000028) RTC Interrupt Mask Register */ + __IOM uint32_t RTC_STATUS_REG; /*!< (@ 0x0000002C) RTC Status Register */ + __IOM uint32_t RTC_KEEP_RTC_REG; /*!< (@ 0x00000030) RTC Keep RTC Register */ + __IM uint32_t RESERVED[19]; + __IOM uint32_t RTC_EVENT_CTRL_REG; /*!< (@ 0x00000080) RTC Event Control Register */ + __IOM uint32_t RTC_MOTOR_EVENT_PERIOD_REG; /*!< (@ 0x00000084) RTC Motor Event Period Register */ + __IOM uint32_t RTC_PDC_EVENT_PERIOD_REG; /*!< (@ 0x00000088) RTC PDC Event Period Register */ + __IOM uint32_t RTC_PDC_EVENT_CLEAR_REG; /*!< (@ 0x0000008C) RTC PDC Event Clear Register */ + __IOM uint32_t RTC_MOTOR_EVENT_CNT_REG; /*!< (@ 0x00000090) RTC Motor Event Counter Register */ + __IOM uint32_t RTC_PDC_EVENT_CNT_REG; /*!< (@ 0x00000094) RTC PDC Event Counter Register */ +} RTC_Type; /*!< Size = 152 (0x98) */ + + + +/* =========================================================================================================================== */ +/* ================ SDADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SDADC registers (SDADC) + */ + +typedef struct { /*!< (@ 0x50020800) SDADC Structure */ + __IOM uint32_t SDADC_CTRL_REG; /*!< (@ 0x00000000) Sigma Delta ADC Control Register */ + __IM uint32_t RESERVED; + __IOM uint32_t SDADC_TEST_REG; /*!< (@ 0x00000008) Sigma Delta ADC Test Register */ + __IOM uint32_t SDADC_GAIN_CORR_REG; /*!< (@ 0x0000000C) Sigma Delta ADC Gain Correction Register */ + __IOM uint32_t SDADC_OFFS_CORR_REG; /*!< (@ 0x00000010) Sigma Delta ADC Offset Correction Register */ + __IOM uint32_t SDADC_CLEAR_INT_REG; /*!< (@ 0x00000014) Sigma Delta ADC Clear Interrupt Register */ + __IOM uint32_t SDADC_RESULT_REG; /*!< (@ 0x00000018) Sigma Delta ADC Result Register */ +} SDADC_Type; /*!< Size = 28 (0x1c) */ + + + +/* =========================================================================================================================== */ +/* ================ SMOTOR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SMOTOR registers (SMOTOR) + */ + +typedef struct { /*!< (@ 0x50030E00) SMOTOR Structure */ + __IOM uint32_t SMOTOR_CTRL_REG; /*!< (@ 0x00000000) Motor control register */ + __IOM uint32_t PG0_CTRL_REG; /*!< (@ 0x00000004) Pattern generator 0 control register */ + __IOM uint32_t PG1_CTRL_REG; /*!< (@ 0x00000008) Pattern generator 1 control register */ + __IOM uint32_t PG2_CTRL_REG; /*!< (@ 0x0000000C) Pattern generator 2 control register */ + __IOM uint32_t PG3_CTRL_REG; /*!< (@ 0x00000010) Pattern generator 3 control register */ + __IOM uint32_t PG4_CTRL_REG; /*!< (@ 0x00000014) Pattern generator 4 control register */ + __IOM uint32_t SMOTOR_TRIGGER_REG; /*!< (@ 0x00000018) Motor controller trigger register */ + __IM uint32_t RESERVED; + __IOM uint32_t SMOTOR_CMD_FIFO_REG; /*!< (@ 0x00000020) Motor control command FIFO register */ + __IOM uint32_t SMOTOR_CMD_READ_PTR_REG; /*!< (@ 0x00000024) Command read pointer register */ + __IOM uint32_t SMOTOR_CMD_WRITE_PTR_REG; /*!< (@ 0x00000028) Command write pointer register */ + __IOM uint32_t SMOTOR_STATUS_REG; /*!< (@ 0x0000002C) Motor controller status register */ + __IOM uint32_t SMOTOR_IRQ_CLEAR_REG; /*!< (@ 0x00000030) Motor control IRQ clear register */ + __IM uint32_t RESERVED1[3]; + __IOM uint32_t WAVETABLE_BASE; /*!< (@ 0x00000040) Base address of the wavetable */ + __IM uint32_t RESERVED2[15]; + __IOM uint32_t CMD_TABLE_BASE; /*!< (@ 0x00000080) Base address of the command table */ +} SMOTOR_Type; /*!< Size = 132 (0x84) */ + + + +/* =========================================================================================================================== */ +/* ================ SNC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SNC registers (SNC) + */ + +typedef struct { /*!< (@ 0x50020C00) SNC Structure */ + __IOM uint32_t SNC_CTRL_REG; /*!< (@ 0x00000000) Sensor Node Control Register */ + __IOM uint32_t SNC_STATUS_REG; /*!< (@ 0x00000004) Sensor Node Status Register */ + __IOM uint32_t SNC_LP_TIMER_REG; /*!< (@ 0x00000008) Sensor Node Low-Power Timer Register */ + __IOM uint32_t SNC_PC_REG; /*!< (@ 0x0000000C) Sensor Node Program Counter */ + __IOM uint32_t SNC_R1_REG; /*!< (@ 0x00000010) Sensor Node core - Operand 1 Register */ + __IOM uint32_t SNC_R2_REG; /*!< (@ 0x00000014) Sensor Node core - Operand 2 Register */ + __IOM uint32_t SNC_TMP1_REG; /*!< (@ 0x00000018) Sensor Node core - Temporary Register 1 */ + __IOM uint32_t SNC_TMP2_REG; /*!< (@ 0x0000001C) Sensor Node core - Temporary Register 2 */ +} SNC_Type; /*!< Size = 32 (0x20) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI registers (SPI) + */ + +typedef struct { /*!< (@ 0x50020300) SPI Structure */ + __IOM uint32_t SPI_CTRL_REG; /*!< (@ 0x00000000) SPI control register 0 */ + __IOM uint32_t SPI_RX_TX_REG; /*!< (@ 0x00000004) SPI RX/TX register0 */ + __IOM uint32_t SPI_CLEAR_INT_REG; /*!< (@ 0x00000008) SPI clear interrupt register */ +} SPI_Type; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI2 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI2 registers (SPI2) + */ + +typedef struct { /*!< (@ 0x50020400) SPI2 Structure */ + __IOM uint32_t SPI2_CTRL_REG; /*!< (@ 0x00000000) SPI control register 0 */ + __IOM uint32_t SPI2_RX_TX_REG; /*!< (@ 0x00000004) SPI RX/TX register0 */ + __IOM uint32_t SPI2_CLEAR_INT_REG; /*!< (@ 0x00000008) SPI clear interrupt register */ +} SPI2_Type; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ SYS_WDOG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SYS_WDOG registers (SYS_WDOG) + */ + +typedef struct { /*!< (@ 0x50000700) SYS_WDOG Structure */ + __IOM uint32_t WATCHDOG_REG; /*!< (@ 0x00000000) Watchdog timer register. */ + __IOM uint32_t WATCHDOG_CTRL_REG; /*!< (@ 0x00000004) Watchdog control register. */ +} SYS_WDOG_Type; /*!< Size = 8 (0x8) */ + + + +/* =========================================================================================================================== */ +/* ================ TIMER ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief TIMER registers (TIMER) + */ + +typedef struct { /*!< (@ 0x50010200) TIMER Structure */ + __IOM uint32_t TIMER_CTRL_REG; /*!< (@ 0x00000000) Timer control register */ + __IOM uint32_t TIMER_TIMER_VAL_REG; /*!< (@ 0x00000004) Timer counter value */ + __IOM uint32_t TIMER_STATUS_REG; /*!< (@ 0x00000008) Timer status register */ + __IOM uint32_t TIMER_GPIO1_CONF_REG; /*!< (@ 0x0000000C) Timer gpio1 selection */ + __IOM uint32_t TIMER_GPIO2_CONF_REG; /*!< (@ 0x00000010) Timer gpio2 selection */ + __IOM uint32_t TIMER_RELOAD_REG; /*!< (@ 0x00000014) Timer reload value and Delay in shot mode */ + __IOM uint32_t TIMER_SHOTWIDTH_REG; /*!< (@ 0x00000018) Timer Shot duration in shot mode */ + __IOM uint32_t TIMER_PRESCALER_REG; /*!< (@ 0x0000001C) Timer prescaler value */ + __IOM uint32_t TIMER_CAPTURE_GPIO1_REG; /*!< (@ 0x00000020) Timer value for event on GPIO1 */ + __IOM uint32_t TIMER_CAPTURE_GPIO2_REG; /*!< (@ 0x00000024) Timer value for event on GPIO2 */ + __IOM uint32_t TIMER_PRESCALER_VAL_REG; /*!< (@ 0x00000028) Timer prescaler counter valuew */ + __IOM uint32_t TIMER_PWM_FREQ_REG; /*!< (@ 0x0000002C) Timer pwm frequency register */ + __IOM uint32_t TIMER_PWM_DC_REG; /*!< (@ 0x00000030) Timer pwm dc register */ + __IOM uint32_t TIMER_GPIO3_CONF_REG; /*!< (@ 0x00000034) Timer gpio3 selection */ + __IOM uint32_t TIMER_GPIO4_CONF_REG; /*!< (@ 0x00000038) Timer gpio4 selection */ + __IOM uint32_t TIMER_CAPTURE_GPIO3_REG; /*!< (@ 0x0000003C) Timer value for event on GPIO1 */ + __IOM uint32_t TIMER_CAPTURE_GPIO4_REG; /*!< (@ 0x00000040) Timer value for event on GPIO1 */ + __IOM uint32_t TIMER_CLEAR_GPIO_EVENT_REG; /*!< (@ 0x00000044) Timer clear gpio event register */ + __IOM uint32_t TIMER_CLEAR_IRQ_REG; /*!< (@ 0x00000048) Timer clear interrupt */ +} TIMER_Type; /*!< Size = 76 (0x4c) */ + + + +/* =========================================================================================================================== */ +/* ================ TIMER2 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief TIMER2 registers (TIMER2) + */ + +typedef struct { /*!< (@ 0x50010300) TIMER2 Structure */ + __IOM uint32_t TIMER2_CTRL_REG; /*!< (@ 0x00000000) Timer control register */ + __IOM uint32_t TIMER2_TIMER_VAL_REG; /*!< (@ 0x00000004) Timer counter value */ + __IOM uint32_t TIMER2_STATUS_REG; /*!< (@ 0x00000008) Timer status register */ + __IOM uint32_t TIMER2_GPIO1_CONF_REG; /*!< (@ 0x0000000C) Timer gpio1 selection */ + __IOM uint32_t TIMER2_GPIO2_CONF_REG; /*!< (@ 0x00000010) Timer gpio2 selection */ + __IOM uint32_t TIMER2_RELOAD_REG; /*!< (@ 0x00000014) Timer reload value and Delay in shot mode */ + __IOM uint32_t TIMER2_SHOTWIDTH_REG; /*!< (@ 0x00000018) Timer Shot duration in shot mode */ + __IOM uint32_t TIMER2_PRESCALER_REG; /*!< (@ 0x0000001C) Timer prescaler value */ + __IOM uint32_t TIMER2_CAPTURE_GPIO1_REG; /*!< (@ 0x00000020) Timer value for event on GPIO1 */ + __IOM uint32_t TIMER2_CAPTURE_GPIO2_REG; /*!< (@ 0x00000024) Timer value for event on GPIO2 */ + __IOM uint32_t TIMER2_PRESCALER_VAL_REG; /*!< (@ 0x00000028) Timer prescaler counter valuew */ + __IOM uint32_t TIMER2_PWM_FREQ_REG; /*!< (@ 0x0000002C) Timer pwm frequency register */ + __IOM uint32_t TIMER2_PWM_DC_REG; /*!< (@ 0x00000030) Timer pwm dc register */ + __IOM uint32_t TIMER2_CLEAR_IRQ_REG; /*!< (@ 0x00000034) Timer clear interrupt */ +} TIMER2_Type; /*!< Size = 56 (0x38) */ + + + +/* =========================================================================================================================== */ +/* ================ TIMER3 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief TIMER3 registers (TIMER3) + */ + +typedef struct { /*!< (@ 0x50040A00) TIMER3 Structure */ + __IOM uint32_t TIMER3_CTRL_REG; /*!< (@ 0x00000000) Timer control register */ + __IOM uint32_t TIMER3_TIMER_VAL_REG; /*!< (@ 0x00000004) Timer counter value */ + __IOM uint32_t TIMER3_STATUS_REG; /*!< (@ 0x00000008) Timer status register */ + __IOM uint32_t TIMER3_GPIO1_CONF_REG; /*!< (@ 0x0000000C) Timer gpio1 selection */ + __IOM uint32_t TIMER3_GPIO2_CONF_REG; /*!< (@ 0x00000010) Timer gpio2 selection */ + __IOM uint32_t TIMER3_RELOAD_REG; /*!< (@ 0x00000014) Timer reload value and Delay in shot mode */ + __IM uint32_t RESERVED; + __IOM uint32_t TIMER3_PRESCALER_REG; /*!< (@ 0x0000001C) Timer prescaler value */ + __IOM uint32_t TIMER3_CAPTURE_GPIO1_REG; /*!< (@ 0x00000020) Timer value for event on GPIO1 */ + __IOM uint32_t TIMER3_CAPTURE_GPIO2_REG; /*!< (@ 0x00000024) Timer value for event on GPIO2 */ + __IOM uint32_t TIMER3_PRESCALER_VAL_REG; /*!< (@ 0x00000028) Timer prescaler counter valuew */ + __IOM uint32_t TIMER3_PWM_FREQ_REG; /*!< (@ 0x0000002C) Timer pwm frequency register */ + __IOM uint32_t TIMER3_PWM_DC_REG; /*!< (@ 0x00000030) Timer pwm dc register */ + __IOM uint32_t TIMER3_CLEAR_IRQ_REG; /*!< (@ 0x00000034) Timer clear interrupt */ +} TIMER3_Type; /*!< Size = 56 (0x38) */ + + + +/* =========================================================================================================================== */ +/* ================ TIMER4 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief TIMER4 registers (TIMER4) + */ + +typedef struct { /*!< (@ 0x50040B00) TIMER4 Structure */ + __IOM uint32_t TIMER4_CTRL_REG; /*!< (@ 0x00000000) Timer control register */ + __IOM uint32_t TIMER4_TIMER_VAL_REG; /*!< (@ 0x00000004) Timer counter value */ + __IOM uint32_t TIMER4_STATUS_REG; /*!< (@ 0x00000008) Timer status register */ + __IOM uint32_t TIMER4_GPIO1_CONF_REG; /*!< (@ 0x0000000C) Timer gpio1 selection */ + __IOM uint32_t TIMER4_GPIO2_CONF_REG; /*!< (@ 0x00000010) Timer gpio2 selection */ + __IOM uint32_t TIMER4_RELOAD_REG; /*!< (@ 0x00000014) Timer reload value and Delay in shot mode */ + __IM uint32_t RESERVED; + __IOM uint32_t TIMER4_PRESCALER_REG; /*!< (@ 0x0000001C) Timer prescaler value */ + __IOM uint32_t TIMER4_CAPTURE_GPIO1_REG; /*!< (@ 0x00000020) Timer value for event on GPIO1 */ + __IOM uint32_t TIMER4_CAPTURE_GPIO2_REG; /*!< (@ 0x00000024) Timer value for event on GPIO2 */ + __IOM uint32_t TIMER4_PRESCALER_VAL_REG; /*!< (@ 0x00000028) Timer prescaler counter valuew */ + __IOM uint32_t TIMER4_PWM_FREQ_REG; /*!< (@ 0x0000002C) Timer pwm frequency register */ + __IOM uint32_t TIMER4_PWM_DC_REG; /*!< (@ 0x00000030) Timer pwm dc register */ + __IOM uint32_t TIMER4_CLEAR_IRQ_REG; /*!< (@ 0x00000034) Timer clear interrupt */ +} TIMER4_Type; /*!< Size = 56 (0x38) */ + + + +/* =========================================================================================================================== */ +/* ================ TRNG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief TRNG registers (TRNG) + */ + +typedef struct { /*!< (@ 0x50040C00) TRNG Structure */ + __IOM uint32_t TRNG_CTRL_REG; /*!< (@ 0x00000000) TRNG control register */ + __IOM uint32_t TRNG_FIFOLVL_REG; /*!< (@ 0x00000004) TRNG FIFO level register */ + __IOM uint32_t TRNG_VER_REG; /*!< (@ 0x00000008) TRNG Version register */ +} TRNG_Type; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ UART ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART registers (UART) + */ + +typedef struct { /*!< (@ 0x50020000) UART Structure */ + __IOM uint32_t UART_RBR_THR_DLL_REG; /*!< (@ 0x00000000) Receive Buffer Register */ + __IOM uint32_t UART_IER_DLH_REG; /*!< (@ 0x00000004) Interrupt Enable Register */ + __IOM uint32_t UART_IIR_FCR_REG; /*!< (@ 0x00000008) Interrupt Identification Register/FIFO Control + Register */ + __IOM uint32_t UART_LCR_REG; /*!< (@ 0x0000000C) Line Control Register */ + __IOM uint32_t UART_MCR_REG; /*!< (@ 0x00000010) Modem Control Register */ + __IOM uint32_t UART_LSR_REG; /*!< (@ 0x00000014) Line Status Register */ + __IM uint32_t RESERVED; + __IOM uint32_t UART_SCR_REG; /*!< (@ 0x0000001C) Scratchpad Register */ + __IM uint32_t RESERVED1[4]; + __IOM uint32_t UART_SRBR_STHR0_REG; /*!< (@ 0x00000030) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART_SRBR_STHR1_REG; /*!< (@ 0x00000034) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART_SRBR_STHR2_REG; /*!< (@ 0x00000038) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART_SRBR_STHR3_REG; /*!< (@ 0x0000003C) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART_SRBR_STHR4_REG; /*!< (@ 0x00000040) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART_SRBR_STHR5_REG; /*!< (@ 0x00000044) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART_SRBR_STHR6_REG; /*!< (@ 0x00000048) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART_SRBR_STHR7_REG; /*!< (@ 0x0000004C) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART_SRBR_STHR8_REG; /*!< (@ 0x00000050) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART_SRBR_STHR9_REG; /*!< (@ 0x00000054) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART_SRBR_STHR10_REG; /*!< (@ 0x00000058) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART_SRBR_STHR11_REG; /*!< (@ 0x0000005C) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART_SRBR_STHR12_REG; /*!< (@ 0x00000060) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART_SRBR_STHR13_REG; /*!< (@ 0x00000064) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART_SRBR_STHR14_REG; /*!< (@ 0x00000068) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART_SRBR_STHR15_REG; /*!< (@ 0x0000006C) Shadow Receive/Transmit Buffer Register */ + __IM uint32_t RESERVED2[3]; + __IOM uint32_t UART_USR_REG; /*!< (@ 0x0000007C) UART Status register. */ + __IOM uint32_t UART_TFL_REG; /*!< (@ 0x00000080) Transmit FIFO Level */ + __IOM uint32_t UART_RFL_REG; /*!< (@ 0x00000084) Receive FIFO Level. */ + __IOM uint32_t UART_SRR_REG; /*!< (@ 0x00000088) Software Reset Register. */ + __IM uint32_t RESERVED3; + __IOM uint32_t UART_SBCR_REG; /*!< (@ 0x00000090) Shadow Break Control Register */ + __IOM uint32_t UART_SDMAM_REG; /*!< (@ 0x00000094) Shadow DMA Mode */ + __IOM uint32_t UART_SFE_REG; /*!< (@ 0x00000098) Shadow FIFO Enable */ + __IOM uint32_t UART_SRT_REG; /*!< (@ 0x0000009C) Shadow RCVR Trigger */ + __IOM uint32_t UART_STET_REG; /*!< (@ 0x000000A0) Shadow TX Empty Trigger */ + __IOM uint32_t UART_HTX_REG; /*!< (@ 0x000000A4) Halt TX */ + __IOM uint32_t UART_DMASA_REG; /*!< (@ 0x000000A8) DMA Software Acknowledge */ + __IM uint32_t RESERVED4[5]; + __IOM uint32_t UART_DLF_REG; /*!< (@ 0x000000C0) Divisor Latch Fraction Register */ + __IM uint32_t RESERVED5[13]; + __IOM uint32_t UART_UCV_REG; /*!< (@ 0x000000F8) Component Version */ + __IOM uint32_t UART_CTR_REG; /*!< (@ 0x000000FC) Component Type Register */ +} UART_Type; /*!< Size = 256 (0x100) */ + + + +/* =========================================================================================================================== */ +/* ================ UART2 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART2 registers (UART2) + */ + +typedef struct { /*!< (@ 0x50020100) UART2 Structure */ + __IOM uint32_t UART2_RBR_THR_DLL_REG; /*!< (@ 0x00000000) Receive Buffer Register */ + __IOM uint32_t UART2_IER_DLH_REG; /*!< (@ 0x00000004) Interrupt Enable Register */ + __IOM uint32_t UART2_IIR_FCR_REG; /*!< (@ 0x00000008) Interrupt Identification Register/FIFO Control + Register */ + __IOM uint32_t UART2_LCR_REG; /*!< (@ 0x0000000C) Line Control Register */ + __IOM uint32_t UART2_MCR_REG; /*!< (@ 0x00000010) Modem Control Register */ + __IOM uint32_t UART2_LSR_REG; /*!< (@ 0x00000014) Line Status Register */ + __IOM uint32_t UART2_MSR_REG; /*!< (@ 0x00000018) Modem Status Register */ + __IOM uint32_t UART2_SCR_REG; /*!< (@ 0x0000001C) Scratchpad Register */ + __IM uint32_t RESERVED[4]; + __IOM uint32_t UART2_SRBR_STHR0_REG; /*!< (@ 0x00000030) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART2_SRBR_STHR1_REG; /*!< (@ 0x00000034) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART2_SRBR_STHR2_REG; /*!< (@ 0x00000038) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART2_SRBR_STHR3_REG; /*!< (@ 0x0000003C) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART2_SRBR_STHR4_REG; /*!< (@ 0x00000040) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART2_SRBR_STHR5_REG; /*!< (@ 0x00000044) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART2_SRBR_STHR6_REG; /*!< (@ 0x00000048) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART2_SRBR_STHR7_REG; /*!< (@ 0x0000004C) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART2_SRBR_STHR8_REG; /*!< (@ 0x00000050) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART2_SRBR_STHR9_REG; /*!< (@ 0x00000054) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART2_SRBR_STHR10_REG; /*!< (@ 0x00000058) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART2_SRBR_STHR11_REG; /*!< (@ 0x0000005C) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART2_SRBR_STHR12_REG; /*!< (@ 0x00000060) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART2_SRBR_STHR13_REG; /*!< (@ 0x00000064) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART2_SRBR_STHR14_REG; /*!< (@ 0x00000068) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART2_SRBR_STHR15_REG; /*!< (@ 0x0000006C) Shadow Receive/Transmit Buffer Register */ + __IM uint32_t RESERVED1[3]; + __IOM uint32_t UART2_USR_REG; /*!< (@ 0x0000007C) UART Status register. */ + __IOM uint32_t UART2_TFL_REG; /*!< (@ 0x00000080) Transmit FIFO Level */ + __IOM uint32_t UART2_RFL_REG; /*!< (@ 0x00000084) Receive FIFO Level. */ + __IOM uint32_t UART2_SRR_REG; /*!< (@ 0x00000088) Software Reset Register. */ + __IOM uint32_t UART2_SRTS_REG; /*!< (@ 0x0000008C) Shadow Request to Send */ + __IOM uint32_t UART2_SBCR_REG; /*!< (@ 0x00000090) Shadow Break Control Register */ + __IOM uint32_t UART2_SDMAM_REG; /*!< (@ 0x00000094) Shadow DMA Mode */ + __IOM uint32_t UART2_SFE_REG; /*!< (@ 0x00000098) Shadow FIFO Enable */ + __IOM uint32_t UART2_SRT_REG; /*!< (@ 0x0000009C) Shadow RCVR Trigger */ + __IOM uint32_t UART2_STET_REG; /*!< (@ 0x000000A0) Shadow TX Empty Trigger */ + __IOM uint32_t UART2_HTX_REG; /*!< (@ 0x000000A4) Halt TX */ + __IOM uint32_t UART2_DMASA_REG; /*!< (@ 0x000000A8) DMA Software Acknowledge */ + __IM uint32_t RESERVED2[5]; + __IOM uint32_t UART2_DLF_REG; /*!< (@ 0x000000C0) Divisor Latch Fraction Register */ + __IOM uint32_t UART2_RAR_REG; /*!< (@ 0x000000C4) Receive Address Register */ + __IOM uint32_t UART2_TAR_REG; /*!< (@ 0x000000C8) Transmit Address Register */ + __IOM uint32_t UART2_LCR_EXT; /*!< (@ 0x000000CC) Line Extended Control Register */ + __IM uint32_t RESERVED3[10]; + __IOM uint32_t UART2_UCV_REG; /*!< (@ 0x000000F8) Component Version */ + __IOM uint32_t UART2_CTR_REG; /*!< (@ 0x000000FC) Component Type Register */ +} UART2_Type; /*!< Size = 256 (0x100) */ + + + +/* =========================================================================================================================== */ +/* ================ UART3 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART3 registers (UART3) + */ + +typedef struct { /*!< (@ 0x50020200) UART3 Structure */ + __IOM uint32_t UART3_RBR_THR_DLL_REG; /*!< (@ 0x00000000) Receive Buffer Register */ + __IOM uint32_t UART3_IER_DLH_REG; /*!< (@ 0x00000004) Interrupt Enable Register */ + __IOM uint32_t UART3_IIR_FCR_REG; /*!< (@ 0x00000008) Interrupt Identification Register/FIFO Control + Register */ + __IOM uint32_t UART3_LCR_REG; /*!< (@ 0x0000000C) Line Control Register */ + __IOM uint32_t UART3_MCR_REG; /*!< (@ 0x00000010) Modem Control Register */ + __IOM uint32_t UART3_LSR_REG; /*!< (@ 0x00000014) Line Status Register */ + __IOM uint32_t UART3_MSR_REG; /*!< (@ 0x00000018) Modem Status Register */ + __IOM uint32_t UART3_CONFIG_REG; /*!< (@ 0x0000001C) ISO7816 Config Register */ + __IM uint32_t RESERVED[4]; + __IOM uint32_t UART3_SRBR_STHR0_REG; /*!< (@ 0x00000030) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART3_SRBR_STHR1_REG; /*!< (@ 0x00000034) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART3_SRBR_STHR2_REG; /*!< (@ 0x00000038) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART3_SRBR_STHR3_REG; /*!< (@ 0x0000003C) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART3_SRBR_STHR4_REG; /*!< (@ 0x00000040) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART3_SRBR_STHR5_REG; /*!< (@ 0x00000044) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART3_SRBR_STHR6_REG; /*!< (@ 0x00000048) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART3_SRBR_STHR7_REG; /*!< (@ 0x0000004C) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART3_SRBR_STHR8_REG; /*!< (@ 0x00000050) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART3_SRBR_STHR9_REG; /*!< (@ 0x00000054) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART3_SRBR_STHR10_REG; /*!< (@ 0x00000058) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART3_SRBR_STHR11_REG; /*!< (@ 0x0000005C) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART3_SRBR_STHR12_REG; /*!< (@ 0x00000060) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART3_SRBR_STHR13_REG; /*!< (@ 0x00000064) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART3_SRBR_STHR14_REG; /*!< (@ 0x00000068) Shadow Receive/Transmit Buffer Register */ + __IOM uint32_t UART3_SRBR_STHR15_REG; /*!< (@ 0x0000006C) Shadow Receive/Transmit Buffer Register */ + __IM uint32_t RESERVED1[3]; + __IOM uint32_t UART3_USR_REG; /*!< (@ 0x0000007C) UART Status register. */ + __IOM uint32_t UART3_TFL_REG; /*!< (@ 0x00000080) Transmit FIFO Level */ + __IOM uint32_t UART3_RFL_REG; /*!< (@ 0x00000084) Receive FIFO Level. */ + __IOM uint32_t UART3_SRR_REG; /*!< (@ 0x00000088) Software Reset Register. */ + __IOM uint32_t UART3_SRTS_REG; /*!< (@ 0x0000008C) Shadow Request to Send */ + __IOM uint32_t UART3_SBCR_REG; /*!< (@ 0x00000090) Shadow Break Control Register */ + __IOM uint32_t UART3_SDMAM_REG; /*!< (@ 0x00000094) Shadow DMA Mode */ + __IOM uint32_t UART3_SFE_REG; /*!< (@ 0x00000098) Shadow FIFO Enable */ + __IOM uint32_t UART3_SRT_REG; /*!< (@ 0x0000009C) Shadow RCVR Trigger */ + __IOM uint32_t UART3_STET_REG; /*!< (@ 0x000000A0) Shadow TX Empty Trigger */ + __IOM uint32_t UART3_HTX_REG; /*!< (@ 0x000000A4) Halt TX */ + __IOM uint32_t UART3_DMASA_REG; /*!< (@ 0x000000A8) DMA Software Acknowledge */ + __IM uint32_t RESERVED2[5]; + __IOM uint32_t UART3_DLF_REG; /*!< (@ 0x000000C0) Divisor Latch Fraction Register */ + __IOM uint32_t UART3_RAR_REG; /*!< (@ 0x000000C4) Receive Address Register */ + __IOM uint32_t UART3_TAR_REG; /*!< (@ 0x000000C8) Transmit Address Register */ + __IOM uint32_t UART3_LCR_EXT; /*!< (@ 0x000000CC) Line Extended Control Register */ + __IM uint32_t RESERVED3[4]; + __IOM uint32_t UART3_CTRL_REG; /*!< (@ 0x000000E0) ISO7816 Control Register */ + __IOM uint32_t UART3_TIMER_REG; /*!< (@ 0x000000E4) ISO7816 Timer Register */ + __IOM uint32_t UART3_ERR_CTRL_REG; /*!< (@ 0x000000E8) ISO7816 Error Signal Control Register */ + __IOM uint32_t UART3_IRQ_STATUS_REG; /*!< (@ 0x000000EC) ISO7816 Interrupt Status Register */ + __IM uint32_t RESERVED4[2]; + __IOM uint32_t UART3_UCV_REG; /*!< (@ 0x000000F8) Component Version */ + __IOM uint32_t UART3_CTR_REG; /*!< (@ 0x000000FC) Component Type Register */ +} UART3_Type; /*!< Size = 256 (0x100) */ + + + +/* =========================================================================================================================== */ +/* ================ USB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief USB registers (USB) + */ + +typedef struct { /*!< (@ 0x50040000) USB Structure */ + __IOM uint32_t USB_MCTRL_REG; /*!< (@ 0x00000000) Main Control Register) */ + __IOM uint32_t USB_XCVDIAG_REG; /*!< (@ 0x00000004) Transceiver diagnostic Register (for test purpose + only) */ + __IOM uint32_t USB_TCR_REG; /*!< (@ 0x00000008) Transceiver configuration Register */ + __IOM uint32_t USB_UTR_REG; /*!< (@ 0x0000000C) USB test Register (for test purpose only) */ + __IOM uint32_t USB_FAR_REG; /*!< (@ 0x00000010) Function Address Register */ + __IOM uint32_t USB_NFSR_REG; /*!< (@ 0x00000014) Node Functional State Register */ + __IOM uint32_t USB_MAEV_REG; /*!< (@ 0x00000018) Main Event Register */ + __IOM uint32_t USB_MAMSK_REG; /*!< (@ 0x0000001C) Main Mask Register */ + __IOM uint32_t USB_ALTEV_REG; /*!< (@ 0x00000020) Alternate Event Register */ + __IOM uint32_t USB_ALTMSK_REG; /*!< (@ 0x00000024) Alternate Mask Register */ + __IOM uint32_t USB_TXEV_REG; /*!< (@ 0x00000028) Transmit Event Register */ + __IOM uint32_t USB_TXMSK_REG; /*!< (@ 0x0000002C) Transmit Mask Register */ + __IOM uint32_t USB_RXEV_REG; /*!< (@ 0x00000030) Receive Event Register */ + __IOM uint32_t USB_RXMSK_REG; /*!< (@ 0x00000034) Receive Mask Register */ + __IOM uint32_t USB_NAKEV_REG; /*!< (@ 0x00000038) NAK Event Register */ + __IOM uint32_t USB_NAKMSK_REG; /*!< (@ 0x0000003C) NAK Mask Register */ + __IOM uint32_t USB_FWEV_REG; /*!< (@ 0x00000040) FIFO Warning Event Register */ + __IOM uint32_t USB_FWMSK_REG; /*!< (@ 0x00000044) FIFO Warning Mask Register */ + __IOM uint32_t USB_FNH_REG; /*!< (@ 0x00000048) Frame Number High Byte Register */ + __IOM uint32_t USB_FNL_REG; /*!< (@ 0x0000004C) Frame Number Low Byte Register */ + __IM uint32_t RESERVED[11]; + __IOM uint32_t USB_UX20CDR_REG; /*!< (@ 0x0000007C) Transceiver 2.0 Configuration and Diagnostics + Register(for test purpose only) */ + __IOM uint32_t USB_EPC0_REG; /*!< (@ 0x00000080) Endpoint Control 0 Register */ + __IOM uint32_t USB_TXD0_REG; /*!< (@ 0x00000084) Transmit Data 0 Register */ + __IOM uint32_t USB_TXS0_REG; /*!< (@ 0x00000088) Transmit Status 0 Register */ + __IOM uint32_t USB_TXC0_REG; /*!< (@ 0x0000008C) Transmit command 0 Register */ + __IOM uint32_t USB_EP0_NAK_REG; /*!< (@ 0x00000090) EP0 INNAK and OUTNAK Register */ + __IOM uint32_t USB_RXD0_REG; /*!< (@ 0x00000094) Receive Data 0 Register */ + __IOM uint32_t USB_RXS0_REG; /*!< (@ 0x00000098) Receive Status 0 Register */ + __IOM uint32_t USB_RXC0_REG; /*!< (@ 0x0000009C) Receive Command 0 Register */ + __IOM uint32_t USB_EPC1_REG; /*!< (@ 0x000000A0) Endpoint Control Register 1 */ + __IOM uint32_t USB_TXD1_REG; /*!< (@ 0x000000A4) Transmit Data Register 1 */ + __IOM uint32_t USB_TXS1_REG; /*!< (@ 0x000000A8) Transmit Status Register 1 */ + __IOM uint32_t USB_TXC1_REG; /*!< (@ 0x000000AC) Transmit Command Register 1 */ + __IOM uint32_t USB_EPC2_REG; /*!< (@ 0x000000B0) Endpoint Control Register 2 */ + __IOM uint32_t USB_RXD1_REG; /*!< (@ 0x000000B4) Receive Data Register,1 */ + __IOM uint32_t USB_RXS1_REG; /*!< (@ 0x000000B8) Receive Status Register 1 */ + __IOM uint32_t USB_RXC1_REG; /*!< (@ 0x000000BC) Receive Command Register 1 */ + __IOM uint32_t USB_EPC3_REG; /*!< (@ 0x000000C0) Endpoint Control Register 3 */ + __IOM uint32_t USB_TXD2_REG; /*!< (@ 0x000000C4) Transmit Data Register 2 */ + __IOM uint32_t USB_TXS2_REG; /*!< (@ 0x000000C8) Transmit Status Register 2 */ + __IOM uint32_t USB_TXC2_REG; /*!< (@ 0x000000CC) Transmit Command Register 2 */ + __IOM uint32_t USB_EPC4_REG; /*!< (@ 0x000000D0) Endpoint Control Register 4 */ + __IOM uint32_t USB_RXD2_REG; /*!< (@ 0x000000D4) Receive Data Register 2 */ + __IOM uint32_t USB_RXS2_REG; /*!< (@ 0x000000D8) Receive Status Register 2 */ + __IOM uint32_t USB_RXC2_REG; /*!< (@ 0x000000DC) Receive Command Register 2 */ + __IOM uint32_t USB_EPC5_REG; /*!< (@ 0x000000E0) Endpoint Control Register 5 */ + __IOM uint32_t USB_TXD3_REG; /*!< (@ 0x000000E4) Transmit Data Register 3 */ + __IOM uint32_t USB_TXS3_REG; /*!< (@ 0x000000E8) Transmit Status Register 3 */ + __IOM uint32_t USB_TXC3_REG; /*!< (@ 0x000000EC) Transmit Command Register 3 */ + __IOM uint32_t USB_EPC6_REG; /*!< (@ 0x000000F0) Endpoint Control Register 6 */ + __IOM uint32_t USB_RXD3_REG; /*!< (@ 0x000000F4) Receive Data Register 3 */ + __IOM uint32_t USB_RXS3_REG; /*!< (@ 0x000000F8) Receive Status Register 3 */ + __IOM uint32_t USB_RXC3_REG; /*!< (@ 0x000000FC) Receive Command Register 3 */ + __IM uint32_t RESERVED1[40]; + __IOM uint32_t USB_DMA_CTRL_REG; /*!< (@ 0x000001A0) USB DMA control register */ + __IM uint32_t RESERVED2; + __IOM uint32_t USB_CHARGER_CTRL_REG; /*!< (@ 0x000001A8) USB Charger Control Register */ + __IOM uint32_t USB_CHARGER_STAT_REG; /*!< (@ 0x000001AC) USB Charger Status Register */ +} USB_Type; /*!< Size = 432 (0x1b0) */ + + + +/* =========================================================================================================================== */ +/* ================ WAKEUP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief WAKEUP registers (WAKEUP) + */ + +typedef struct { /*!< (@ 0x50000100) WAKEUP Structure */ + __IOM uint32_t WKUP_CTRL_REG; /*!< (@ 0x00000000) Control register for the wakeup counter */ + __IM uint32_t RESERVED; + __IOM uint32_t WKUP_RESET_IRQ_REG; /*!< (@ 0x00000008) Reset wakeup interrupt */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t WKUP_SELECT_P0_REG; /*!< (@ 0x00000014) select which inputs from P0 port can trigger + wkup counter */ + __IOM uint32_t WKUP_SELECT_P1_REG; /*!< (@ 0x00000018) select which inputs from P1 port can trigger + wkup counter */ + __IM uint32_t RESERVED2[3]; + __IOM uint32_t WKUP_POL_P0_REG; /*!< (@ 0x00000028) select the sesitivity polarity for each P0 input */ + __IOM uint32_t WKUP_POL_P1_REG; /*!< (@ 0x0000002C) select the sesitivity polarity for each P1 input */ + __IM uint32_t RESERVED3[3]; + __IOM uint32_t WKUP_STATUS_P0_REG; /*!< (@ 0x0000003C) Event status register for P0 */ + __IOM uint32_t WKUP_STATUS_P1_REG; /*!< (@ 0x00000040) Event status register for P1 */ + __IM uint32_t RESERVED4; + __IOM uint32_t WKUP_CLEAR_P0_REG; /*!< (@ 0x00000048) Clear event register for P0 */ + __IOM uint32_t WKUP_CLEAR_P1_REG; /*!< (@ 0x0000004C) Clear event register for P1 */ + __IM uint32_t RESERVED5; + __IOM uint32_t WKUP_SEL_GPIO_P0_REG; /*!< (@ 0x00000054) select which inputs from P0 port can trigger + interrupt */ + __IOM uint32_t WKUP_SEL_GPIO_P1_REG; /*!< (@ 0x00000058) select which inputs from P1 port can trigger + interrupt */ +} WAKEUP_Type; /*!< Size = 92 (0x5c) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +#define AES_HASH_BASE 0x30040000UL +#define ANAMISC_BIF_BASE 0x50030B00UL +#define APU_BASE 0x50030600UL +#define CACHE_BASE 0x100C0000UL +#define CHARGER_BASE 0x50040400UL +#define CHIP_VERSION_BASE 0x50040200UL +#define CRG_COM_BASE 0x50020900UL +#define CRG_PER_BASE 0x50030C00UL +#define CRG_SYS_BASE 0x50040500UL +#define CRG_TOP_BASE 0x50000000UL +#define CRG_XTAL_BASE 0x50010000UL +#define DCDC_BASE 0x50000300UL +#define DMA_BASE 0x50040800UL +#define DW_BASE 0x30020000UL +#define GPADC_BASE 0x50030900UL +#define GPIO_BASE 0x50020A00UL +#define GPREG_BASE 0x50040300UL +#define I2C_BASE 0x50020600UL +#define I2C2_BASE 0x50020700UL +#define LCDC_BASE 0x30030000UL +#define LRA_BASE 0x50030A00UL +#define MEMCTRL_BASE 0x50050000UL +#define OTPC_BASE 0x30070000UL +#define PDC_BASE 0x50000200UL +#define PWMLED_BASE 0x50030500UL +#define QSPIC_BASE 0x38000000UL +#define QSPIC2_BASE 0x34000000UL +#define RFMON_BASE 0x50040600UL +#define RTC_BASE 0x50000400UL +#define SDADC_BASE 0x50020800UL +#define SMOTOR_BASE 0x50030E00UL +#define SNC_BASE 0x50020C00UL +#define SPI_BASE 0x50020300UL +#define SPI2_BASE 0x50020400UL +#define SYS_WDOG_BASE 0x50000700UL +#define TIMER_BASE 0x50010200UL +#define TIMER2_BASE 0x50010300UL +#define TIMER3_BASE 0x50040A00UL +#define TIMER4_BASE 0x50040B00UL +#define TRNG_BASE 0x50040C00UL +#define UART_BASE 0x50020000UL +#define UART2_BASE 0x50020100UL +#define UART3_BASE 0x50020200UL +#define USB_BASE 0x50040000UL +#define WAKEUP_BASE 0x50000100UL + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +#define AES_HASH ((AES_HASH_Type*) AES_HASH_BASE) +#define ANAMISC_BIF ((ANAMISC_BIF_Type*) ANAMISC_BIF_BASE) +#define APU ((APU_Type*) APU_BASE) +#define CACHE ((CACHE_Type*) CACHE_BASE) +#define CHARGER ((CHARGER_Type*) CHARGER_BASE) +#define CHIP_VERSION ((CHIP_VERSION_Type*) CHIP_VERSION_BASE) +#define CRG_COM ((CRG_COM_Type*) CRG_COM_BASE) +#define CRG_PER ((CRG_PER_Type*) CRG_PER_BASE) +#define CRG_SYS ((CRG_SYS_Type*) CRG_SYS_BASE) +#define CRG_TOP ((CRG_TOP_Type*) CRG_TOP_BASE) +#define CRG_XTAL ((CRG_XTAL_Type*) CRG_XTAL_BASE) +#define DCDC ((DCDC_Type*) DCDC_BASE) +#define DMA ((DMA_Type*) DMA_BASE) +#define DW ((DW_Type*) DW_BASE) +#define GPADC ((GPADC_Type*) GPADC_BASE) +#define GPIO ((GPIO_Type*) GPIO_BASE) +#define GPREG ((GPREG_Type*) GPREG_BASE) +#define I2C ((I2C_Type*) I2C_BASE) +#define I2C2 ((I2C2_Type*) I2C2_BASE) +#define LCDC ((LCDC_Type*) LCDC_BASE) +#define LRA ((LRA_Type*) LRA_BASE) +#define MEMCTRL ((MEMCTRL_Type*) MEMCTRL_BASE) +#define OTPC ((OTPC_Type*) OTPC_BASE) +#define PDC ((PDC_Type*) PDC_BASE) +#define PWMLED ((PWMLED_Type*) PWMLED_BASE) +#define QSPIC ((QSPIC_Type*) QSPIC_BASE) +#define QSPIC2 ((QSPIC2_Type*) QSPIC2_BASE) +#define RFMON ((RFMON_Type*) RFMON_BASE) +#define RTC ((RTC_Type*) RTC_BASE) +#define SDADC ((SDADC_Type*) SDADC_BASE) +#define SMOTOR ((SMOTOR_Type*) SMOTOR_BASE) +#define SNC ((SNC_Type*) SNC_BASE) +#define SPI ((SPI_Type*) SPI_BASE) +#define SPI2 ((SPI2_Type*) SPI2_BASE) +#define SYS_WDOG ((SYS_WDOG_Type*) SYS_WDOG_BASE) +#define TIMER ((TIMER_Type*) TIMER_BASE) +#define TIMER2 ((TIMER2_Type*) TIMER2_BASE) +#define TIMER3 ((TIMER3_Type*) TIMER3_BASE) +#define TIMER4 ((TIMER4_Type*) TIMER4_BASE) +#define TRNG ((TRNG_Type*) TRNG_BASE) +#define UART ((UART_Type*) UART_BASE) +#define UART2 ((UART2_Type*) UART2_BASE) +#define UART3 ((UART3_Type*) UART3_BASE) +#define USB ((USB_Type*) USB_BASE) +#define WAKEUP ((WAKEUP_Type*) WAKEUP_BASE) + + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup PosMask_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ AES_HASH ================ */ +/* =========================================================================================================================== */ + +/* =================================================== CRYPTO_CLRIRQ_REG =================================================== */ +#define AES_HASH_CRYPTO_CLRIRQ_REG_CRYPTO_CLRIRQ_Pos (0UL) /*!< CRYPTO_CLRIRQ (Bit 0) */ +#define AES_HASH_CRYPTO_CLRIRQ_REG_CRYPTO_CLRIRQ_Msk (0x1UL) /*!< CRYPTO_CLRIRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== CRYPTO_CTRL_REG ==================================================== */ +#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEXP_Pos (17UL) /*!< CRYPTO_AES_KEXP (Bit 17) */ +#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEXP_Msk (0x20000UL) /*!< CRYPTO_AES_KEXP (Bitfield-Mask: 0x01) */ +#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_MORE_IN_Pos (16UL) /*!< CRYPTO_MORE_IN (Bit 16) */ +#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_MORE_IN_Msk (0x10000UL) /*!< CRYPTO_MORE_IN (Bitfield-Mask: 0x01) */ +#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_OUT_LEN_Pos (10UL) /*!< CRYPTO_HASH_OUT_LEN (Bit 10) */ +#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_OUT_LEN_Msk (0xfc00UL) /*!< CRYPTO_HASH_OUT_LEN (Bitfield-Mask: 0x3f) */ +#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_SEL_Pos (9UL) /*!< CRYPTO_HASH_SEL (Bit 9) */ +#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_SEL_Msk (0x200UL) /*!< CRYPTO_HASH_SEL (Bitfield-Mask: 0x01) */ +#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_IRQ_EN_Pos (8UL) /*!< CRYPTO_IRQ_EN (Bit 8) */ +#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_IRQ_EN_Msk (0x100UL) /*!< CRYPTO_IRQ_EN (Bitfield-Mask: 0x01) */ +#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ENCDEC_Pos (7UL) /*!< CRYPTO_ENCDEC (Bit 7) */ +#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ENCDEC_Msk (0x80UL) /*!< CRYPTO_ENCDEC (Bitfield-Mask: 0x01) */ +#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Pos (5UL) /*!< CRYPTO_AES_KEY_SZ (Bit 5) */ +#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Msk (0x60UL) /*!< CRYPTO_AES_KEY_SZ (Bitfield-Mask: 0x03) */ +#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_OUT_MD_Pos (4UL) /*!< CRYPTO_OUT_MD (Bit 4) */ +#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_OUT_MD_Msk (0x10UL) /*!< CRYPTO_OUT_MD (Bitfield-Mask: 0x01) */ +#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Pos (2UL) /*!< CRYPTO_ALG_MD (Bit 2) */ +#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Msk (0xcUL) /*!< CRYPTO_ALG_MD (Bitfield-Mask: 0x03) */ +#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_Pos (0UL) /*!< CRYPTO_ALG (Bit 0) */ +#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_Msk (0x3UL) /*!< CRYPTO_ALG (Bitfield-Mask: 0x03) */ +/* ================================================= CRYPTO_DEST_ADDR_REG ================================================== */ +#define AES_HASH_CRYPTO_DEST_ADDR_REG_CRYPTO_DEST_ADDR_Pos (0UL) /*!< CRYPTO_DEST_ADDR (Bit 0) */ +#define AES_HASH_CRYPTO_DEST_ADDR_REG_CRYPTO_DEST_ADDR_Msk (0xffffffffUL) /*!< CRYPTO_DEST_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CRYPTO_FETCH_ADDR_REG ================================================= */ +#define AES_HASH_CRYPTO_FETCH_ADDR_REG_CRYPTO_FETCH_ADDR_Pos (0UL) /*!< CRYPTO_FETCH_ADDR (Bit 0) */ +#define AES_HASH_CRYPTO_FETCH_ADDR_REG_CRYPTO_FETCH_ADDR_Msk (0xffffffffUL) /*!< CRYPTO_FETCH_ADDR (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CRYPTO_KEYS_START =================================================== */ +#define AES_HASH_CRYPTO_KEYS_START_CRYPTO_KEY_X_Pos (0UL) /*!< CRYPTO_KEY_X (Bit 0) */ +#define AES_HASH_CRYPTO_KEYS_START_CRYPTO_KEY_X_Msk (0xffffffffUL) /*!< CRYPTO_KEY_X (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CRYPTO_LEN_REG ===================================================== */ +#define AES_HASH_CRYPTO_LEN_REG_CRYPTO_LEN_Pos (0UL) /*!< CRYPTO_LEN (Bit 0) */ +#define AES_HASH_CRYPTO_LEN_REG_CRYPTO_LEN_Msk (0xffffffUL) /*!< CRYPTO_LEN (Bitfield-Mask: 0xffffff) */ +/* =================================================== CRYPTO_MREG0_REG ==================================================== */ +#define AES_HASH_CRYPTO_MREG0_REG_CRYPTO_MREG0_Pos (0UL) /*!< CRYPTO_MREG0 (Bit 0) */ +#define AES_HASH_CRYPTO_MREG0_REG_CRYPTO_MREG0_Msk (0xffffffffUL) /*!< CRYPTO_MREG0 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CRYPTO_MREG1_REG ==================================================== */ +#define AES_HASH_CRYPTO_MREG1_REG_CRYPTO_MREG1_Pos (0UL) /*!< CRYPTO_MREG1 (Bit 0) */ +#define AES_HASH_CRYPTO_MREG1_REG_CRYPTO_MREG1_Msk (0xffffffffUL) /*!< CRYPTO_MREG1 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CRYPTO_MREG2_REG ==================================================== */ +#define AES_HASH_CRYPTO_MREG2_REG_CRYPTO_MREG2_Pos (0UL) /*!< CRYPTO_MREG2 (Bit 0) */ +#define AES_HASH_CRYPTO_MREG2_REG_CRYPTO_MREG2_Msk (0xffffffffUL) /*!< CRYPTO_MREG2 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CRYPTO_MREG3_REG ==================================================== */ +#define AES_HASH_CRYPTO_MREG3_REG_CRYPTO_MREG3_Pos (0UL) /*!< CRYPTO_MREG3 (Bit 0) */ +#define AES_HASH_CRYPTO_MREG3_REG_CRYPTO_MREG3_Msk (0xffffffffUL) /*!< CRYPTO_MREG3 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== CRYPTO_START_REG ==================================================== */ +#define AES_HASH_CRYPTO_START_REG_CRYPTO_START_Pos (0UL) /*!< CRYPTO_START (Bit 0) */ +#define AES_HASH_CRYPTO_START_REG_CRYPTO_START_Msk (0x1UL) /*!< CRYPTO_START (Bitfield-Mask: 0x01) */ +/* =================================================== CRYPTO_STATUS_REG =================================================== */ +#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_IRQ_ST_Pos (2UL) /*!< CRYPTO_IRQ_ST (Bit 2) */ +#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_IRQ_ST_Msk (0x4UL) /*!< CRYPTO_IRQ_ST (Bitfield-Mask: 0x01) */ +#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_WAIT_FOR_IN_Pos (1UL) /*!< CRYPTO_WAIT_FOR_IN (Bit 1) */ +#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_WAIT_FOR_IN_Msk (0x2UL) /*!< CRYPTO_WAIT_FOR_IN (Bitfield-Mask: 0x01) */ +#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_INACTIVE_Pos (0UL) /*!< CRYPTO_INACTIVE (Bit 0) */ +#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_INACTIVE_Msk (0x1UL) /*!< CRYPTO_INACTIVE (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ ANAMISC_BIF ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== CLK_REF_CNT_REG ==================================================== */ +#define ANAMISC_BIF_CLK_REF_CNT_REG_REF_CNT_VAL_Pos (0UL) /*!< REF_CNT_VAL (Bit 0) */ +#define ANAMISC_BIF_CLK_REF_CNT_REG_REF_CNT_VAL_Msk (0xffffUL) /*!< REF_CNT_VAL (Bitfield-Mask: 0xffff) */ +/* ==================================================== CLK_REF_SEL_REG ==================================================== */ +#define ANAMISC_BIF_CLK_REF_SEL_REG_CAL_CLK_SEL_Pos (5UL) /*!< CAL_CLK_SEL (Bit 5) */ +#define ANAMISC_BIF_CLK_REF_SEL_REG_CAL_CLK_SEL_Msk (0xe0UL) /*!< CAL_CLK_SEL (Bitfield-Mask: 0x07) */ +#define ANAMISC_BIF_CLK_REF_SEL_REG_EXT_CNT_EN_SEL_Pos (4UL) /*!< EXT_CNT_EN_SEL (Bit 4) */ +#define ANAMISC_BIF_CLK_REF_SEL_REG_EXT_CNT_EN_SEL_Msk (0x10UL) /*!< EXT_CNT_EN_SEL (Bitfield-Mask: 0x01) */ +#define ANAMISC_BIF_CLK_REF_SEL_REG_REF_CAL_START_Pos (3UL) /*!< REF_CAL_START (Bit 3) */ +#define ANAMISC_BIF_CLK_REF_SEL_REG_REF_CAL_START_Msk (0x8UL) /*!< REF_CAL_START (Bitfield-Mask: 0x01) */ +#define ANAMISC_BIF_CLK_REF_SEL_REG_REF_CLK_SEL_Pos (0UL) /*!< REF_CLK_SEL (Bit 0) */ +#define ANAMISC_BIF_CLK_REF_SEL_REG_REF_CLK_SEL_Msk (0x7UL) /*!< REF_CLK_SEL (Bitfield-Mask: 0x07) */ +/* ==================================================== CLK_REF_VAL_REG ==================================================== */ +#define ANAMISC_BIF_CLK_REF_VAL_REG_XTAL_CNT_VAL_Pos (0UL) /*!< XTAL_CNT_VAL (Bit 0) */ +#define ANAMISC_BIF_CLK_REF_VAL_REG_XTAL_CNT_VAL_Msk (0xffffffffUL) /*!< XTAL_CNT_VAL (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ APU ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== APU_MUX_REG ====================================================== */ +#define APU_APU_MUX_REG_PDM1_MUX_IN_Pos (6UL) /*!< PDM1_MUX_IN (Bit 6) */ +#define APU_APU_MUX_REG_PDM1_MUX_IN_Msk (0x40UL) /*!< PDM1_MUX_IN (Bitfield-Mask: 0x01) */ +#define APU_APU_MUX_REG_PCM1_MUX_IN_Pos (3UL) /*!< PCM1_MUX_IN (Bit 3) */ +#define APU_APU_MUX_REG_PCM1_MUX_IN_Msk (0x38UL) /*!< PCM1_MUX_IN (Bitfield-Mask: 0x07) */ +#define APU_APU_MUX_REG_SRC1_MUX_IN_Pos (0UL) /*!< SRC1_MUX_IN (Bit 0) */ +#define APU_APU_MUX_REG_SRC1_MUX_IN_Msk (0x7UL) /*!< SRC1_MUX_IN (Bitfield-Mask: 0x07) */ +/* ==================================================== COEF0A_SET1_REG ==================================================== */ +#define APU_COEF0A_SET1_REG_SRC_COEF10_Pos (0UL) /*!< SRC_COEF10 (Bit 0) */ +#define APU_COEF0A_SET1_REG_SRC_COEF10_Msk (0xffffUL) /*!< SRC_COEF10 (Bitfield-Mask: 0xffff) */ +/* ==================================================== COEF10_SET1_REG ==================================================== */ +#define APU_COEF10_SET1_REG_SRC_COEF1_Pos (16UL) /*!< SRC_COEF1 (Bit 16) */ +#define APU_COEF10_SET1_REG_SRC_COEF1_Msk (0xffff0000UL) /*!< SRC_COEF1 (Bitfield-Mask: 0xffff) */ +#define APU_COEF10_SET1_REG_SRC_COEF0_Pos (0UL) /*!< SRC_COEF0 (Bit 0) */ +#define APU_COEF10_SET1_REG_SRC_COEF0_Msk (0xffffUL) /*!< SRC_COEF0 (Bitfield-Mask: 0xffff) */ +/* ==================================================== COEF32_SET1_REG ==================================================== */ +#define APU_COEF32_SET1_REG_SRC_COEF3_Pos (16UL) /*!< SRC_COEF3 (Bit 16) */ +#define APU_COEF32_SET1_REG_SRC_COEF3_Msk (0xffff0000UL) /*!< SRC_COEF3 (Bitfield-Mask: 0xffff) */ +#define APU_COEF32_SET1_REG_SRC_COEF2_Pos (0UL) /*!< SRC_COEF2 (Bit 0) */ +#define APU_COEF32_SET1_REG_SRC_COEF2_Msk (0xffffUL) /*!< SRC_COEF2 (Bitfield-Mask: 0xffff) */ +/* ==================================================== COEF54_SET1_REG ==================================================== */ +#define APU_COEF54_SET1_REG_SRC_COEF5_Pos (16UL) /*!< SRC_COEF5 (Bit 16) */ +#define APU_COEF54_SET1_REG_SRC_COEF5_Msk (0xffff0000UL) /*!< SRC_COEF5 (Bitfield-Mask: 0xffff) */ +#define APU_COEF54_SET1_REG_SRC_COEF4_Pos (0UL) /*!< SRC_COEF4 (Bit 0) */ +#define APU_COEF54_SET1_REG_SRC_COEF4_Msk (0xffffUL) /*!< SRC_COEF4 (Bitfield-Mask: 0xffff) */ +/* ==================================================== COEF76_SET1_REG ==================================================== */ +#define APU_COEF76_SET1_REG_SRC_COEF7_Pos (16UL) /*!< SRC_COEF7 (Bit 16) */ +#define APU_COEF76_SET1_REG_SRC_COEF7_Msk (0xffff0000UL) /*!< SRC_COEF7 (Bitfield-Mask: 0xffff) */ +#define APU_COEF76_SET1_REG_SRC_COEF6_Pos (0UL) /*!< SRC_COEF6 (Bit 0) */ +#define APU_COEF76_SET1_REG_SRC_COEF6_Msk (0xffffUL) /*!< SRC_COEF6 (Bitfield-Mask: 0xffff) */ +/* ==================================================== COEF98_SET1_REG ==================================================== */ +#define APU_COEF98_SET1_REG_SRC_COEF9_Pos (16UL) /*!< SRC_COEF9 (Bit 16) */ +#define APU_COEF98_SET1_REG_SRC_COEF9_Msk (0xffff0000UL) /*!< SRC_COEF9 (Bitfield-Mask: 0xffff) */ +#define APU_COEF98_SET1_REG_SRC_COEF8_Pos (0UL) /*!< SRC_COEF8 (Bit 0) */ +#define APU_COEF98_SET1_REG_SRC_COEF8_Msk (0xffffUL) /*!< SRC_COEF8 (Bitfield-Mask: 0xffff) */ +/* ===================================================== PCM1_CTRL_REG ===================================================== */ +#define APU_PCM1_CTRL_REG_PCM_FSC_DIV_Pos (20UL) /*!< PCM_FSC_DIV (Bit 20) */ +#define APU_PCM1_CTRL_REG_PCM_FSC_DIV_Msk (0xfff00000UL) /*!< PCM_FSC_DIV (Bitfield-Mask: 0xfff) */ +#define APU_PCM1_CTRL_REG_PCM_FSC_EDGE_Pos (16UL) /*!< PCM_FSC_EDGE (Bit 16) */ +#define APU_PCM1_CTRL_REG_PCM_FSC_EDGE_Msk (0x10000UL) /*!< PCM_FSC_EDGE (Bitfield-Mask: 0x01) */ +#define APU_PCM1_CTRL_REG_PCM_CH_DEL_Pos (11UL) /*!< PCM_CH_DEL (Bit 11) */ +#define APU_PCM1_CTRL_REG_PCM_CH_DEL_Msk (0xf800UL) /*!< PCM_CH_DEL (Bitfield-Mask: 0x1f) */ +#define APU_PCM1_CTRL_REG_PCM_CLK_BIT_Pos (10UL) /*!< PCM_CLK_BIT (Bit 10) */ +#define APU_PCM1_CTRL_REG_PCM_CLK_BIT_Msk (0x400UL) /*!< PCM_CLK_BIT (Bitfield-Mask: 0x01) */ +#define APU_PCM1_CTRL_REG_PCM_FSCINV_Pos (9UL) /*!< PCM_FSCINV (Bit 9) */ +#define APU_PCM1_CTRL_REG_PCM_FSCINV_Msk (0x200UL) /*!< PCM_FSCINV (Bitfield-Mask: 0x01) */ +#define APU_PCM1_CTRL_REG_PCM_CLKINV_Pos (8UL) /*!< PCM_CLKINV (Bit 8) */ +#define APU_PCM1_CTRL_REG_PCM_CLKINV_Msk (0x100UL) /*!< PCM_CLKINV (Bitfield-Mask: 0x01) */ +#define APU_PCM1_CTRL_REG_PCM_PPOD_Pos (7UL) /*!< PCM_PPOD (Bit 7) */ +#define APU_PCM1_CTRL_REG_PCM_PPOD_Msk (0x80UL) /*!< PCM_PPOD (Bitfield-Mask: 0x01) */ +#define APU_PCM1_CTRL_REG_PCM_FSCDEL_Pos (6UL) /*!< PCM_FSCDEL (Bit 6) */ +#define APU_PCM1_CTRL_REG_PCM_FSCDEL_Msk (0x40UL) /*!< PCM_FSCDEL (Bitfield-Mask: 0x01) */ +#define APU_PCM1_CTRL_REG_PCM_FSCLEN_Pos (2UL) /*!< PCM_FSCLEN (Bit 2) */ +#define APU_PCM1_CTRL_REG_PCM_FSCLEN_Msk (0x3cUL) /*!< PCM_FSCLEN (Bitfield-Mask: 0x0f) */ +#define APU_PCM1_CTRL_REG_PCM_MASTER_Pos (1UL) /*!< PCM_MASTER (Bit 1) */ +#define APU_PCM1_CTRL_REG_PCM_MASTER_Msk (0x2UL) /*!< PCM_MASTER (Bitfield-Mask: 0x01) */ +#define APU_PCM1_CTRL_REG_PCM_EN_Pos (0UL) /*!< PCM_EN (Bit 0) */ +#define APU_PCM1_CTRL_REG_PCM_EN_Msk (0x1UL) /*!< PCM_EN (Bitfield-Mask: 0x01) */ +/* ===================================================== PCM1_IN1_REG ====================================================== */ +#define APU_PCM1_IN1_REG_PCM_IN_Pos (0UL) /*!< PCM_IN (Bit 0) */ +#define APU_PCM1_IN1_REG_PCM_IN_Msk (0xffffffffUL) /*!< PCM_IN (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PCM1_IN2_REG ====================================================== */ +#define APU_PCM1_IN2_REG_PCM_IN_Pos (0UL) /*!< PCM_IN (Bit 0) */ +#define APU_PCM1_IN2_REG_PCM_IN_Msk (0xffffffffUL) /*!< PCM_IN (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PCM1_OUT1_REG ===================================================== */ +#define APU_PCM1_OUT1_REG_PCM_OUT_Pos (0UL) /*!< PCM_OUT (Bit 0) */ +#define APU_PCM1_OUT1_REG_PCM_OUT_Msk (0xffffffffUL) /*!< PCM_OUT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PCM1_OUT2_REG ===================================================== */ +#define APU_PCM1_OUT2_REG_PCM_OUT_Pos (0UL) /*!< PCM_OUT (Bit 0) */ +#define APU_PCM1_OUT2_REG_PCM_OUT_Msk (0xffffffffUL) /*!< PCM_OUT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SRC1_CTRL_REG ===================================================== */ +#define APU_SRC1_CTRL_REG_SRC_PDM_DO_DEL_Pos (30UL) /*!< SRC_PDM_DO_DEL (Bit 30) */ +#define APU_SRC1_CTRL_REG_SRC_PDM_DO_DEL_Msk (0xc0000000UL) /*!< SRC_PDM_DO_DEL (Bitfield-Mask: 0x03) */ +#define APU_SRC1_CTRL_REG_SRC_PDM_MODE_Pos (28UL) /*!< SRC_PDM_MODE (Bit 28) */ +#define APU_SRC1_CTRL_REG_SRC_PDM_MODE_Msk (0x30000000UL) /*!< SRC_PDM_MODE (Bitfield-Mask: 0x03) */ +#define APU_SRC1_CTRL_REG_SRC_PDM_DI_DEL_Pos (26UL) /*!< SRC_PDM_DI_DEL (Bit 26) */ +#define APU_SRC1_CTRL_REG_SRC_PDM_DI_DEL_Msk (0xc000000UL) /*!< SRC_PDM_DI_DEL (Bitfield-Mask: 0x03) */ +#define APU_SRC1_CTRL_REG_SRC_OUT_FLOWCLR_Pos (25UL) /*!< SRC_OUT_FLOWCLR (Bit 25) */ +#define APU_SRC1_CTRL_REG_SRC_OUT_FLOWCLR_Msk (0x2000000UL) /*!< SRC_OUT_FLOWCLR (Bitfield-Mask: 0x01) */ +#define APU_SRC1_CTRL_REG_SRC_IN_FLOWCLR_Pos (24UL) /*!< SRC_IN_FLOWCLR (Bit 24) */ +#define APU_SRC1_CTRL_REG_SRC_IN_FLOWCLR_Msk (0x1000000UL) /*!< SRC_IN_FLOWCLR (Bitfield-Mask: 0x01) */ +#define APU_SRC1_CTRL_REG_SRC_OUT_UNFLOW_Pos (23UL) /*!< SRC_OUT_UNFLOW (Bit 23) */ +#define APU_SRC1_CTRL_REG_SRC_OUT_UNFLOW_Msk (0x800000UL) /*!< SRC_OUT_UNFLOW (Bitfield-Mask: 0x01) */ +#define APU_SRC1_CTRL_REG_SRC_OUT_OVFLOW_Pos (22UL) /*!< SRC_OUT_OVFLOW (Bit 22) */ +#define APU_SRC1_CTRL_REG_SRC_OUT_OVFLOW_Msk (0x400000UL) /*!< SRC_OUT_OVFLOW (Bitfield-Mask: 0x01) */ +#define APU_SRC1_CTRL_REG_SRC_IN_UNFLOW_Pos (21UL) /*!< SRC_IN_UNFLOW (Bit 21) */ +#define APU_SRC1_CTRL_REG_SRC_IN_UNFLOW_Msk (0x200000UL) /*!< SRC_IN_UNFLOW (Bitfield-Mask: 0x01) */ +#define APU_SRC1_CTRL_REG_SRC_IN_OVFLOW_Pos (20UL) /*!< SRC_IN_OVFLOW (Bit 20) */ +#define APU_SRC1_CTRL_REG_SRC_IN_OVFLOW_Msk (0x100000UL) /*!< SRC_IN_OVFLOW (Bitfield-Mask: 0x01) */ +#define APU_SRC1_CTRL_REG_SRC_RESYNC_Pos (19UL) /*!< SRC_RESYNC (Bit 19) */ +#define APU_SRC1_CTRL_REG_SRC_RESYNC_Msk (0x80000UL) /*!< SRC_RESYNC (Bitfield-Mask: 0x01) */ +#define APU_SRC1_CTRL_REG_SRC_OUT_OK_Pos (18UL) /*!< SRC_OUT_OK (Bit 18) */ +#define APU_SRC1_CTRL_REG_SRC_OUT_OK_Msk (0x40000UL) /*!< SRC_OUT_OK (Bitfield-Mask: 0x01) */ +#define APU_SRC1_CTRL_REG_SRC_OUT_US_Pos (16UL) /*!< SRC_OUT_US (Bit 16) */ +#define APU_SRC1_CTRL_REG_SRC_OUT_US_Msk (0x30000UL) /*!< SRC_OUT_US (Bitfield-Mask: 0x03) */ +#define APU_SRC1_CTRL_REG_SRC_OUT_CAL_BYPASS_Pos (14UL) /*!< SRC_OUT_CAL_BYPASS (Bit 14) */ +#define APU_SRC1_CTRL_REG_SRC_OUT_CAL_BYPASS_Msk (0x4000UL) /*!< SRC_OUT_CAL_BYPASS (Bitfield-Mask: 0x01) */ +#define APU_SRC1_CTRL_REG_SRC_OUT_AMODE_Pos (13UL) /*!< SRC_OUT_AMODE (Bit 13) */ +#define APU_SRC1_CTRL_REG_SRC_OUT_AMODE_Msk (0x2000UL) /*!< SRC_OUT_AMODE (Bitfield-Mask: 0x01) */ +#define APU_SRC1_CTRL_REG_SRC_PDM_OUT_INV_Pos (12UL) /*!< SRC_PDM_OUT_INV (Bit 12) */ +#define APU_SRC1_CTRL_REG_SRC_PDM_OUT_INV_Msk (0x1000UL) /*!< SRC_PDM_OUT_INV (Bitfield-Mask: 0x01) */ +#define APU_SRC1_CTRL_REG_SRC_FIFO_DIRECTION_Pos (11UL) /*!< SRC_FIFO_DIRECTION (Bit 11) */ +#define APU_SRC1_CTRL_REG_SRC_FIFO_DIRECTION_Msk (0x800UL) /*!< SRC_FIFO_DIRECTION (Bitfield-Mask: 0x01) */ +#define APU_SRC1_CTRL_REG_SRC_FIFO_ENABLE_Pos (10UL) /*!< SRC_FIFO_ENABLE (Bit 10) */ +#define APU_SRC1_CTRL_REG_SRC_FIFO_ENABLE_Msk (0x400UL) /*!< SRC_FIFO_ENABLE (Bitfield-Mask: 0x01) */ +#define APU_SRC1_CTRL_REG_SRC_OUT_DSD_MODE_Pos (9UL) /*!< SRC_OUT_DSD_MODE (Bit 9) */ +#define APU_SRC1_CTRL_REG_SRC_OUT_DSD_MODE_Msk (0x200UL) /*!< SRC_OUT_DSD_MODE (Bitfield-Mask: 0x01) */ +#define APU_SRC1_CTRL_REG_SRC_IN_DSD_MODE_Pos (8UL) /*!< SRC_IN_DSD_MODE (Bit 8) */ +#define APU_SRC1_CTRL_REG_SRC_IN_DSD_MODE_Msk (0x100UL) /*!< SRC_IN_DSD_MODE (Bitfield-Mask: 0x01) */ +#define APU_SRC1_CTRL_REG_SRC_DITHER_DISABLE_Pos (7UL) /*!< SRC_DITHER_DISABLE (Bit 7) */ +#define APU_SRC1_CTRL_REG_SRC_DITHER_DISABLE_Msk (0x80UL) /*!< SRC_DITHER_DISABLE (Bitfield-Mask: 0x01) */ +#define APU_SRC1_CTRL_REG_SRC_IN_OK_Pos (6UL) /*!< SRC_IN_OK (Bit 6) */ +#define APU_SRC1_CTRL_REG_SRC_IN_OK_Msk (0x40UL) /*!< SRC_IN_OK (Bitfield-Mask: 0x01) */ +#define APU_SRC1_CTRL_REG_SRC_IN_DS_Pos (4UL) /*!< SRC_IN_DS (Bit 4) */ +#define APU_SRC1_CTRL_REG_SRC_IN_DS_Msk (0x30UL) /*!< SRC_IN_DS (Bitfield-Mask: 0x03) */ +#define APU_SRC1_CTRL_REG_SRC_PDM_IN_INV_Pos (3UL) /*!< SRC_PDM_IN_INV (Bit 3) */ +#define APU_SRC1_CTRL_REG_SRC_PDM_IN_INV_Msk (0x8UL) /*!< SRC_PDM_IN_INV (Bitfield-Mask: 0x01) */ +#define APU_SRC1_CTRL_REG_SRC_IN_CAL_BYPASS_Pos (2UL) /*!< SRC_IN_CAL_BYPASS (Bit 2) */ +#define APU_SRC1_CTRL_REG_SRC_IN_CAL_BYPASS_Msk (0x4UL) /*!< SRC_IN_CAL_BYPASS (Bitfield-Mask: 0x01) */ +#define APU_SRC1_CTRL_REG_SRC_IN_AMODE_Pos (1UL) /*!< SRC_IN_AMODE (Bit 1) */ +#define APU_SRC1_CTRL_REG_SRC_IN_AMODE_Msk (0x2UL) /*!< SRC_IN_AMODE (Bitfield-Mask: 0x01) */ +#define APU_SRC1_CTRL_REG_SRC_EN_Pos (0UL) /*!< SRC_EN (Bit 0) */ +#define APU_SRC1_CTRL_REG_SRC_EN_Msk (0x1UL) /*!< SRC_EN (Bitfield-Mask: 0x01) */ +/* ===================================================== SRC1_IN1_REG ====================================================== */ +#define APU_SRC1_IN1_REG_SRC_IN_Pos (0UL) /*!< SRC_IN (Bit 0) */ +#define APU_SRC1_IN1_REG_SRC_IN_Msk (0xffffffffUL) /*!< SRC_IN (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SRC1_IN2_REG ====================================================== */ +#define APU_SRC1_IN2_REG_SRC_IN_Pos (0UL) /*!< SRC_IN (Bit 0) */ +#define APU_SRC1_IN2_REG_SRC_IN_Msk (0xffffffffUL) /*!< SRC_IN (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== SRC1_IN_FS_REG ===================================================== */ +#define APU_SRC1_IN_FS_REG_SRC_IN_FS_Pos (0UL) /*!< SRC_IN_FS (Bit 0) */ +#define APU_SRC1_IN_FS_REG_SRC_IN_FS_Msk (0xffffffUL) /*!< SRC_IN_FS (Bitfield-Mask: 0xffffff) */ +/* ===================================================== SRC1_OUT1_REG ===================================================== */ +#define APU_SRC1_OUT1_REG_SRC_OUT_Pos (0UL) /*!< SRC_OUT (Bit 0) */ +#define APU_SRC1_OUT1_REG_SRC_OUT_Msk (0xffffffffUL) /*!< SRC_OUT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SRC1_OUT2_REG ===================================================== */ +#define APU_SRC1_OUT2_REG_SRC_OUT_Pos (0UL) /*!< SRC_OUT (Bit 0) */ +#define APU_SRC1_OUT2_REG_SRC_OUT_Msk (0xffffffffUL) /*!< SRC_OUT (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== SRC1_OUT_FS_REG ==================================================== */ +#define APU_SRC1_OUT_FS_REG_SRC_OUT_FS_Pos (0UL) /*!< SRC_OUT_FS (Bit 0) */ +#define APU_SRC1_OUT_FS_REG_SRC_OUT_FS_Msk (0xffffffUL) /*!< SRC_OUT_FS (Bitfield-Mask: 0xffffff) */ + + +/* =========================================================================================================================== */ +/* ================ CACHE ================ */ +/* =========================================================================================================================== */ + +/* ================================================== CACHE_ASSOCCFG_REG =================================================== */ +#define CACHE_CACHE_ASSOCCFG_REG_CACHE_ASSOC_Pos (0UL) /*!< CACHE_ASSOC (Bit 0) */ +#define CACHE_CACHE_ASSOCCFG_REG_CACHE_ASSOC_Msk (0x3UL) /*!< CACHE_ASSOC (Bitfield-Mask: 0x03) */ +/* ==================================================== CACHE_CTRL1_REG ==================================================== */ +#define CACHE_CACHE_CTRL1_REG_CACHE_RES1_Pos (1UL) /*!< CACHE_RES1 (Bit 1) */ +#define CACHE_CACHE_CTRL1_REG_CACHE_RES1_Msk (0x2UL) /*!< CACHE_RES1 (Bitfield-Mask: 0x01) */ +#define CACHE_CACHE_CTRL1_REG_CACHE_FLUSH_Pos (0UL) /*!< CACHE_FLUSH (Bit 0) */ +#define CACHE_CACHE_CTRL1_REG_CACHE_FLUSH_Msk (0x1UL) /*!< CACHE_FLUSH (Bitfield-Mask: 0x01) */ +/* ==================================================== CACHE_CTRL2_REG ==================================================== */ +#define CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Pos (10UL) /*!< CACHE_CGEN (Bit 10) */ +#define CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Msk (0x400UL) /*!< CACHE_CGEN (Bitfield-Mask: 0x01) */ +#define CACHE_CACHE_CTRL2_REG_CACHE_WEN_Pos (9UL) /*!< CACHE_WEN (Bit 9) */ +#define CACHE_CACHE_CTRL2_REG_CACHE_WEN_Msk (0x200UL) /*!< CACHE_WEN (Bitfield-Mask: 0x01) */ +#define CACHE_CACHE_CTRL2_REG_CACHE_LEN_Pos (0UL) /*!< CACHE_LEN (Bit 0) */ +#define CACHE_CACHE_CTRL2_REG_CACHE_LEN_Msk (0x1ffUL) /*!< CACHE_LEN (Bitfield-Mask: 0x1ff) */ +/* ==================================================== CACHE_FLASH_REG ==================================================== */ +#define CACHE_CACHE_FLASH_REG_FLASH_REGION_BASE_Pos (16UL) /*!< FLASH_REGION_BASE (Bit 16) */ +#define CACHE_CACHE_FLASH_REG_FLASH_REGION_BASE_Msk (0xffff0000UL) /*!< FLASH_REGION_BASE (Bitfield-Mask: 0xffff) */ +#define CACHE_CACHE_FLASH_REG_FLASH_REGION_OFFSET_Pos (4UL) /*!< FLASH_REGION_OFFSET (Bit 4) */ +#define CACHE_CACHE_FLASH_REG_FLASH_REGION_OFFSET_Msk (0xfff0UL) /*!< FLASH_REGION_OFFSET (Bitfield-Mask: 0xfff) */ +#define CACHE_CACHE_FLASH_REG_FLASH_REGION_SIZE_Pos (0UL) /*!< FLASH_REGION_SIZE (Bit 0) */ +#define CACHE_CACHE_FLASH_REG_FLASH_REGION_SIZE_Msk (0x7UL) /*!< FLASH_REGION_SIZE (Bitfield-Mask: 0x07) */ +/* ================================================== CACHE_LNSIZECFG_REG ================================================== */ +#define CACHE_CACHE_LNSIZECFG_REG_CACHE_LINE_Pos (0UL) /*!< CACHE_LINE (Bit 0) */ +#define CACHE_CACHE_LNSIZECFG_REG_CACHE_LINE_Msk (0x3UL) /*!< CACHE_LINE (Bitfield-Mask: 0x03) */ +/* ================================================== CACHE_MRM_CTRL_REG =================================================== */ +#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_HITS_THRES_STATUS_Pos (4UL) /*!< MRM_IRQ_HITS_THRES_STATUS (Bit 4) */ +#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_HITS_THRES_STATUS_Msk (0x10UL) /*!< MRM_IRQ_HITS_THRES_STATUS (Bitfield-Mask: 0x01) */ +#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MISSES_THRES_STATUS_Pos (3UL) /*!< MRM_IRQ_MISSES_THRES_STATUS (Bit 3) */ +#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MISSES_THRES_STATUS_Msk (0x8UL) /*!< MRM_IRQ_MISSES_THRES_STATUS (Bitfield-Mask: 0x01) */ +#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Pos (2UL) /*!< MRM_IRQ_TINT_STATUS (Bit 2) */ +#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Msk (0x4UL) /*!< MRM_IRQ_TINT_STATUS (Bitfield-Mask: 0x01) */ +#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Pos (1UL) /*!< MRM_IRQ_MASK (Bit 1) */ +#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Msk (0x2UL) /*!< MRM_IRQ_MASK (Bitfield-Mask: 0x01) */ +#define CACHE_CACHE_MRM_CTRL_REG_MRM_START_Pos (0UL) /*!< MRM_START (Bit 0) */ +#define CACHE_CACHE_MRM_CTRL_REG_MRM_START_Msk (0x1UL) /*!< MRM_START (Bitfield-Mask: 0x01) */ +/* ================================================== CACHE_MRM_HITS_REG =================================================== */ +#define CACHE_CACHE_MRM_HITS_REG_MRM_HITS_Pos (0UL) /*!< MRM_HITS (Bit 0) */ +#define CACHE_CACHE_MRM_HITS_REG_MRM_HITS_Msk (0xffffffffUL) /*!< MRM_HITS (Bitfield-Mask: 0xffffffff) */ +/* =============================================== CACHE_MRM_HITS_THRES_REG ================================================ */ +#define CACHE_CACHE_MRM_HITS_THRES_REG_MRM_HITS_THRES_Pos (0UL) /*!< MRM_HITS_THRES (Bit 0) */ +#define CACHE_CACHE_MRM_HITS_THRES_REG_MRM_HITS_THRES_Msk (0xffffffffUL) /*!< MRM_HITS_THRES (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CACHE_MRM_MISSES_REG ================================================== */ +#define CACHE_CACHE_MRM_MISSES_REG_MRM_MISSES_Pos (0UL) /*!< MRM_MISSES (Bit 0) */ +#define CACHE_CACHE_MRM_MISSES_REG_MRM_MISSES_Msk (0xffffffffUL) /*!< MRM_MISSES (Bitfield-Mask: 0xffffffff) */ +/* ============================================== CACHE_MRM_MISSES_THRES_REG =============================================== */ +#define CACHE_CACHE_MRM_MISSES_THRES_REG_MRM_MISSES_THRES_Pos (0UL) /*!< MRM_MISSES_THRES (Bit 0) */ +#define CACHE_CACHE_MRM_MISSES_THRES_REG_MRM_MISSES_THRES_Msk (0xffffffffUL) /*!< MRM_MISSES_THRES (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CACHE_MRM_TINT_REG =================================================== */ +#define CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Pos (0UL) /*!< MRM_TINT (Bit 0) */ +#define CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Msk (0x7ffffUL) /*!< MRM_TINT (Bitfield-Mask: 0x7ffff) */ +/* ===================================================== SWD_RESET_REG ===================================================== */ +#define CACHE_SWD_RESET_REG_SWD_HW_RESET_REQ_Pos (0UL) /*!< SWD_HW_RESET_REQ (Bit 0) */ +#define CACHE_SWD_RESET_REG_SWD_HW_RESET_REQ_Msk (0x1UL) /*!< SWD_HW_RESET_REQ (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ CHARGER ================ */ +/* =========================================================================================================================== */ + +/* ============================================== CHARGER_CC_CHARGE_TIMER_REG ============================================== */ +#define CHARGER_CHARGER_CC_CHARGE_TIMER_REG_CC_CHARGE_TIMER_Pos (16UL) /*!< CC_CHARGE_TIMER (Bit 16) */ +#define CHARGER_CHARGER_CC_CHARGE_TIMER_REG_CC_CHARGE_TIMER_Msk (0x7fff0000UL) /*!< CC_CHARGE_TIMER (Bitfield-Mask: 0x7fff) */ +#define CHARGER_CHARGER_CC_CHARGE_TIMER_REG_MAX_CC_CHARGE_TIME_Pos (0UL) /*!< MAX_CC_CHARGE_TIME (Bit 0) */ +#define CHARGER_CHARGER_CC_CHARGE_TIMER_REG_MAX_CC_CHARGE_TIME_Msk (0x7fffUL) /*!< MAX_CC_CHARGE_TIME (Bitfield-Mask: 0x7fff) */ +/* =================================================== CHARGER_CTRL_REG ==================================================== */ +#define CHARGER_CHARGER_CTRL_REG_EOC_INTERVAL_CHECK_TIMER_Pos (22UL) /*!< EOC_INTERVAL_CHECK_TIMER (Bit 22) */ +#define CHARGER_CHARGER_CTRL_REG_EOC_INTERVAL_CHECK_TIMER_Msk (0xfc00000UL) /*!< EOC_INTERVAL_CHECK_TIMER (Bitfield-Mask: 0x3f) */ +#define CHARGER_CHARGER_CTRL_REG_EOC_INTERVAL_CHECK_THRES_Pos (16UL) /*!< EOC_INTERVAL_CHECK_THRES (Bit 16) */ +#define CHARGER_CHARGER_CTRL_REG_EOC_INTERVAL_CHECK_THRES_Msk (0x3f0000UL) /*!< EOC_INTERVAL_CHECK_THRES (Bitfield-Mask: 0x3f) */ +#define CHARGER_CHARGER_CTRL_REG_REPLENISH_MODE_Pos (15UL) /*!< REPLENISH_MODE (Bit 15) */ +#define CHARGER_CHARGER_CTRL_REG_REPLENISH_MODE_Msk (0x8000UL) /*!< REPLENISH_MODE (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_CTRL_REG_PRE_CHARGE_MODE_Pos (14UL) /*!< PRE_CHARGE_MODE (Bit 14) */ +#define CHARGER_CHARGER_CTRL_REG_PRE_CHARGE_MODE_Msk (0x4000UL) /*!< PRE_CHARGE_MODE (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_CTRL_REG_CHARGE_LOOP_HOLD_Pos (13UL) /*!< CHARGE_LOOP_HOLD (Bit 13) */ +#define CHARGER_CHARGER_CTRL_REG_CHARGE_LOOP_HOLD_Msk (0x2000UL) /*!< CHARGE_LOOP_HOLD (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_CTRL_REG_JEITA_SUPPORT_DISABLED_Pos (12UL) /*!< JEITA_SUPPORT_DISABLED (Bit 12) */ +#define CHARGER_CHARGER_CTRL_REG_JEITA_SUPPORT_DISABLED_Msk (0x1000UL) /*!< JEITA_SUPPORT_DISABLED (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_CTRL_REG_TBAT_MONITOR_MODE_Pos (10UL) /*!< TBAT_MONITOR_MODE (Bit 10) */ +#define CHARGER_CHARGER_CTRL_REG_TBAT_MONITOR_MODE_Msk (0xc00UL) /*!< TBAT_MONITOR_MODE (Bitfield-Mask: 0x03) */ +#define CHARGER_CHARGER_CTRL_REG_CHARGE_TIMERS_HALT_ENABLE_Pos (9UL) /*!< CHARGE_TIMERS_HALT_ENABLE (Bit 9) */ +#define CHARGER_CHARGER_CTRL_REG_CHARGE_TIMERS_HALT_ENABLE_Msk (0x200UL) /*!< CHARGE_TIMERS_HALT_ENABLE (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_CTRL_REG_NTC_LOW_DISABLE_Pos (7UL) /*!< NTC_LOW_DISABLE (Bit 7) */ +#define CHARGER_CHARGER_CTRL_REG_NTC_LOW_DISABLE_Msk (0x80UL) /*!< NTC_LOW_DISABLE (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_CTRL_REG_TBAT_PROT_ENABLE_Pos (6UL) /*!< TBAT_PROT_ENABLE (Bit 6) */ +#define CHARGER_CHARGER_CTRL_REG_TBAT_PROT_ENABLE_Msk (0x40UL) /*!< TBAT_PROT_ENABLE (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_CTRL_REG_TDIE_ERROR_RESUME_Pos (5UL) /*!< TDIE_ERROR_RESUME (Bit 5) */ +#define CHARGER_CHARGER_CTRL_REG_TDIE_ERROR_RESUME_Msk (0x20UL) /*!< TDIE_ERROR_RESUME (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_CTRL_REG_TDIE_PROT_ENABLE_Pos (4UL) /*!< TDIE_PROT_ENABLE (Bit 4) */ +#define CHARGER_CHARGER_CTRL_REG_TDIE_PROT_ENABLE_Msk (0x10UL) /*!< TDIE_PROT_ENABLE (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_CTRL_REG_CHARGER_RESUME_Pos (3UL) /*!< CHARGER_RESUME (Bit 3) */ +#define CHARGER_CHARGER_CTRL_REG_CHARGER_RESUME_Msk (0x8UL) /*!< CHARGER_RESUME (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_CTRL_REG_CHARGER_BYPASS_Pos (2UL) /*!< CHARGER_BYPASS (Bit 2) */ +#define CHARGER_CHARGER_CTRL_REG_CHARGER_BYPASS_Msk (0x4UL) /*!< CHARGER_BYPASS (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_CTRL_REG_CHARGE_START_Pos (1UL) /*!< CHARGE_START (Bit 1) */ +#define CHARGER_CHARGER_CTRL_REG_CHARGE_START_Msk (0x2UL) /*!< CHARGE_START (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_CTRL_REG_CHARGER_ENABLE_Pos (0UL) /*!< CHARGER_ENABLE (Bit 0) */ +#define CHARGER_CHARGER_CTRL_REG_CHARGER_ENABLE_Msk (0x1UL) /*!< CHARGER_ENABLE (Bitfield-Mask: 0x01) */ +/* =============================================== CHARGER_CURRENT_PARAM_REG =============================================== */ +#define CHARGER_CHARGER_CURRENT_PARAM_REG_I_EOC_DOUBLE_RANGE_Pos (15UL) /*!< I_EOC_DOUBLE_RANGE (Bit 15) */ +#define CHARGER_CHARGER_CURRENT_PARAM_REG_I_EOC_DOUBLE_RANGE_Msk (0x8000UL) /*!< I_EOC_DOUBLE_RANGE (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_CURRENT_PARAM_REG_I_END_OF_CHARGE_Pos (12UL) /*!< I_END_OF_CHARGE (Bit 12) */ +#define CHARGER_CHARGER_CURRENT_PARAM_REG_I_END_OF_CHARGE_Msk (0x7000UL) /*!< I_END_OF_CHARGE (Bitfield-Mask: 0x07) */ +#define CHARGER_CHARGER_CURRENT_PARAM_REG_I_PRECHARGE_Pos (6UL) /*!< I_PRECHARGE (Bit 6) */ +#define CHARGER_CHARGER_CURRENT_PARAM_REG_I_PRECHARGE_Msk (0xfc0UL) /*!< I_PRECHARGE (Bitfield-Mask: 0x3f) */ +#define CHARGER_CHARGER_CURRENT_PARAM_REG_I_CHARGE_Pos (0UL) /*!< I_CHARGE (Bit 0) */ +#define CHARGER_CHARGER_CURRENT_PARAM_REG_I_CHARGE_Msk (0x3fUL) /*!< I_CHARGE (Bitfield-Mask: 0x3f) */ +/* ============================================== CHARGER_CV_CHARGE_TIMER_REG ============================================== */ +#define CHARGER_CHARGER_CV_CHARGE_TIMER_REG_CV_CHARGE_TIMER_Pos (16UL) /*!< CV_CHARGE_TIMER (Bit 16) */ +#define CHARGER_CHARGER_CV_CHARGE_TIMER_REG_CV_CHARGE_TIMER_Msk (0x7fff0000UL) /*!< CV_CHARGE_TIMER (Bitfield-Mask: 0x7fff) */ +#define CHARGER_CHARGER_CV_CHARGE_TIMER_REG_MAX_CV_CHARGE_TIME_Pos (0UL) /*!< MAX_CV_CHARGE_TIME (Bit 0) */ +#define CHARGER_CHARGER_CV_CHARGE_TIMER_REG_MAX_CV_CHARGE_TIME_Msk (0x7fffUL) /*!< MAX_CV_CHARGE_TIME (Bitfield-Mask: 0x7fff) */ +/* =============================================== CHARGER_ERROR_IRQ_CLR_REG =============================================== */ +#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_TBAT_ERROR_IRQ_CLR_Pos (6UL) /*!< TBAT_ERROR_IRQ_CLR (Bit 6) */ +#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_TBAT_ERROR_IRQ_CLR_Msk (0x40UL) /*!< TBAT_ERROR_IRQ_CLR (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_TDIE_ERROR_IRQ_CLR_Pos (5UL) /*!< TDIE_ERROR_IRQ_CLR (Bit 5) */ +#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_TDIE_ERROR_IRQ_CLR_Msk (0x20UL) /*!< TDIE_ERROR_IRQ_CLR (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_VBAT_OVP_ERROR_IRQ_CLR_Pos (4UL) /*!< VBAT_OVP_ERROR_IRQ_CLR (Bit 4) */ +#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_VBAT_OVP_ERROR_IRQ_CLR_Msk (0x10UL) /*!< VBAT_OVP_ERROR_IRQ_CLR (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_TOTAL_CHARGE_TIMEOUT_IRQ_CLR_Pos (3UL) /*!< TOTAL_CHARGE_TIMEOUT_IRQ_CLR (Bit 3) */ +#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_TOTAL_CHARGE_TIMEOUT_IRQ_CLR_Msk (0x8UL) /*!< TOTAL_CHARGE_TIMEOUT_IRQ_CLR (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_CV_CHARGE_TIMEOUT_IRQ_CLR_Pos (2UL) /*!< CV_CHARGE_TIMEOUT_IRQ_CLR (Bit 2) */ +#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_CV_CHARGE_TIMEOUT_IRQ_CLR_Msk (0x4UL) /*!< CV_CHARGE_TIMEOUT_IRQ_CLR (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_CC_CHARGE_TIMEOUT_IRQ_CLR_Pos (1UL) /*!< CC_CHARGE_TIMEOUT_IRQ_CLR (Bit 1) */ +#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_CC_CHARGE_TIMEOUT_IRQ_CLR_Msk (0x2UL) /*!< CC_CHARGE_TIMEOUT_IRQ_CLR (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_PRECHARGE_TIMEOUT_IRQ_CLR_Pos (0UL) /*!< PRECHARGE_TIMEOUT_IRQ_CLR (Bit 0) */ +#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_PRECHARGE_TIMEOUT_IRQ_CLR_Msk (0x1UL) /*!< PRECHARGE_TIMEOUT_IRQ_CLR (Bitfield-Mask: 0x01) */ +/* ============================================== CHARGER_ERROR_IRQ_MASK_REG =============================================== */ +#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_TBAT_ERROR_IRQ_EN_Pos (6UL) /*!< TBAT_ERROR_IRQ_EN (Bit 6) */ +#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_TBAT_ERROR_IRQ_EN_Msk (0x40UL) /*!< TBAT_ERROR_IRQ_EN (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_TDIE_ERROR_IRQ_EN_Pos (5UL) /*!< TDIE_ERROR_IRQ_EN (Bit 5) */ +#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_TDIE_ERROR_IRQ_EN_Msk (0x20UL) /*!< TDIE_ERROR_IRQ_EN (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_VBAT_OVP_ERROR_IRQ_EN_Pos (4UL) /*!< VBAT_OVP_ERROR_IRQ_EN (Bit 4) */ +#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_VBAT_OVP_ERROR_IRQ_EN_Msk (0x10UL) /*!< VBAT_OVP_ERROR_IRQ_EN (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_TOTAL_CHARGE_TIMEOUT_IRQ_EN_Pos (3UL) /*!< TOTAL_CHARGE_TIMEOUT_IRQ_EN (Bit 3) */ +#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_TOTAL_CHARGE_TIMEOUT_IRQ_EN_Msk (0x8UL) /*!< TOTAL_CHARGE_TIMEOUT_IRQ_EN (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_CV_CHARGE_TIMEOUT_IRQ_EN_Pos (2UL) /*!< CV_CHARGE_TIMEOUT_IRQ_EN (Bit 2) */ +#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_CV_CHARGE_TIMEOUT_IRQ_EN_Msk (0x4UL) /*!< CV_CHARGE_TIMEOUT_IRQ_EN (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_CC_CHARGE_TIMEOUT_IRQ_EN_Pos (1UL) /*!< CC_CHARGE_TIMEOUT_IRQ_EN (Bit 1) */ +#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_CC_CHARGE_TIMEOUT_IRQ_EN_Msk (0x2UL) /*!< CC_CHARGE_TIMEOUT_IRQ_EN (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_PRECHARGE_TIMEOUT_IRQ_EN_Pos (0UL) /*!< PRECHARGE_TIMEOUT_IRQ_EN (Bit 0) */ +#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_PRECHARGE_TIMEOUT_IRQ_EN_Msk (0x1UL) /*!< PRECHARGE_TIMEOUT_IRQ_EN (Bitfield-Mask: 0x01) */ +/* ============================================= CHARGER_ERROR_IRQ_STATUS_REG ============================================== */ +#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_TBAT_ERROR_IRQ_Pos (6UL) /*!< TBAT_ERROR_IRQ (Bit 6) */ +#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_TBAT_ERROR_IRQ_Msk (0x40UL) /*!< TBAT_ERROR_IRQ (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_TDIE_ERROR_IRQ_Pos (5UL) /*!< TDIE_ERROR_IRQ (Bit 5) */ +#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_TDIE_ERROR_IRQ_Msk (0x20UL) /*!< TDIE_ERROR_IRQ (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_VBAT_OVP_ERROR_IRQ_Pos (4UL) /*!< VBAT_OVP_ERROR_IRQ (Bit 4) */ +#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_VBAT_OVP_ERROR_IRQ_Msk (0x10UL) /*!< VBAT_OVP_ERROR_IRQ (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_TOTAL_CHARGE_TIMEOUT_IRQ_Pos (3UL) /*!< TOTAL_CHARGE_TIMEOUT_IRQ (Bit 3) */ +#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_TOTAL_CHARGE_TIMEOUT_IRQ_Msk (0x8UL) /*!< TOTAL_CHARGE_TIMEOUT_IRQ (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_CV_CHARGE_TIMEOUT_IRQ_Pos (2UL) /*!< CV_CHARGE_TIMEOUT_IRQ (Bit 2) */ +#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_CV_CHARGE_TIMEOUT_IRQ_Msk (0x4UL) /*!< CV_CHARGE_TIMEOUT_IRQ (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_CC_CHARGE_TIMEOUT_IRQ_Pos (1UL) /*!< CC_CHARGE_TIMEOUT_IRQ (Bit 1) */ +#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_CC_CHARGE_TIMEOUT_IRQ_Msk (0x2UL) /*!< CC_CHARGE_TIMEOUT_IRQ (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_PRECHARGE_TIMEOUT_IRQ_Pos (0UL) /*!< PRECHARGE_TIMEOUT_IRQ (Bit 0) */ +#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_PRECHARGE_TIMEOUT_IRQ_Msk (0x1UL) /*!< PRECHARGE_TIMEOUT_IRQ (Bitfield-Mask: 0x01) */ +/* =============================================== CHARGER_JEITA_CURRENT_REG =============================================== */ +#define CHARGER_CHARGER_JEITA_CURRENT_REG_I_PRECHARGE_TWARM_Pos (18UL) /*!< I_PRECHARGE_TWARM (Bit 18) */ +#define CHARGER_CHARGER_JEITA_CURRENT_REG_I_PRECHARGE_TWARM_Msk (0xfc0000UL) /*!< I_PRECHARGE_TWARM (Bitfield-Mask: 0x3f) */ +#define CHARGER_CHARGER_JEITA_CURRENT_REG_I_PRECHARGE_TCOOL_Pos (12UL) /*!< I_PRECHARGE_TCOOL (Bit 12) */ +#define CHARGER_CHARGER_JEITA_CURRENT_REG_I_PRECHARGE_TCOOL_Msk (0x3f000UL) /*!< I_PRECHARGE_TCOOL (Bitfield-Mask: 0x3f) */ +#define CHARGER_CHARGER_JEITA_CURRENT_REG_I_CHARGE_TWARM_Pos (6UL) /*!< I_CHARGE_TWARM (Bit 6) */ +#define CHARGER_CHARGER_JEITA_CURRENT_REG_I_CHARGE_TWARM_Msk (0xfc0UL) /*!< I_CHARGE_TWARM (Bitfield-Mask: 0x3f) */ +#define CHARGER_CHARGER_JEITA_CURRENT_REG_I_CHARGE_TCOOL_Pos (0UL) /*!< I_CHARGE_TCOOL (Bit 0) */ +#define CHARGER_CHARGER_JEITA_CURRENT_REG_I_CHARGE_TCOOL_Msk (0x3fUL) /*!< I_CHARGE_TCOOL (Bitfield-Mask: 0x3f) */ +/* ============================================== CHARGER_JEITA_V_CHARGE_REG =============================================== */ +#define CHARGER_CHARGER_JEITA_V_CHARGE_REG_V_CHARGE_TWARM_Pos (6UL) /*!< V_CHARGE_TWARM (Bit 6) */ +#define CHARGER_CHARGER_JEITA_V_CHARGE_REG_V_CHARGE_TWARM_Msk (0xfc0UL) /*!< V_CHARGE_TWARM (Bitfield-Mask: 0x3f) */ +#define CHARGER_CHARGER_JEITA_V_CHARGE_REG_V_CHARGE_TCOOL_Pos (0UL) /*!< V_CHARGE_TCOOL (Bit 0) */ +#define CHARGER_CHARGER_JEITA_V_CHARGE_REG_V_CHARGE_TCOOL_Msk (0x3fUL) /*!< V_CHARGE_TCOOL (Bitfield-Mask: 0x3f) */ +/* ================================================ CHARGER_JEITA_V_OVP_REG ================================================ */ +#define CHARGER_CHARGER_JEITA_V_OVP_REG_V_OVP_TWARM_Pos (6UL) /*!< V_OVP_TWARM (Bit 6) */ +#define CHARGER_CHARGER_JEITA_V_OVP_REG_V_OVP_TWARM_Msk (0xfc0UL) /*!< V_OVP_TWARM (Bitfield-Mask: 0x3f) */ +#define CHARGER_CHARGER_JEITA_V_OVP_REG_V_OVP_TCOOL_Pos (0UL) /*!< V_OVP_TCOOL (Bit 0) */ +#define CHARGER_CHARGER_JEITA_V_OVP_REG_V_OVP_TCOOL_Msk (0x3fUL) /*!< V_OVP_TCOOL (Bitfield-Mask: 0x3f) */ +/* ============================================= CHARGER_JEITA_V_PRECHARGE_REG ============================================= */ +#define CHARGER_CHARGER_JEITA_V_PRECHARGE_REG_V_PRECHARGE_TWARM_Pos (6UL) /*!< V_PRECHARGE_TWARM (Bit 6) */ +#define CHARGER_CHARGER_JEITA_V_PRECHARGE_REG_V_PRECHARGE_TWARM_Msk (0xfc0UL) /*!< V_PRECHARGE_TWARM (Bitfield-Mask: 0x3f) */ +#define CHARGER_CHARGER_JEITA_V_PRECHARGE_REG_V_PRECHARGE_TCOOL_Pos (0UL) /*!< V_PRECHARGE_TCOOL (Bit 0) */ +#define CHARGER_CHARGER_JEITA_V_PRECHARGE_REG_V_PRECHARGE_TCOOL_Msk (0x3fUL) /*!< V_PRECHARGE_TCOOL (Bitfield-Mask: 0x3f) */ +/* ============================================= CHARGER_JEITA_V_REPLENISH_REG ============================================= */ +#define CHARGER_CHARGER_JEITA_V_REPLENISH_REG_V_REPLENISH_TWARM_Pos (6UL) /*!< V_REPLENISH_TWARM (Bit 6) */ +#define CHARGER_CHARGER_JEITA_V_REPLENISH_REG_V_REPLENISH_TWARM_Msk (0xfc0UL) /*!< V_REPLENISH_TWARM (Bitfield-Mask: 0x3f) */ +#define CHARGER_CHARGER_JEITA_V_REPLENISH_REG_V_REPLENISH_TCOOL_Pos (0UL) /*!< V_REPLENISH_TCOOL (Bit 0) */ +#define CHARGER_CHARGER_JEITA_V_REPLENISH_REG_V_REPLENISH_TCOOL_Msk (0x3fUL) /*!< V_REPLENISH_TCOOL (Bitfield-Mask: 0x3f) */ +/* ============================================= CHARGER_PRE_CHARGE_TIMER_REG ============================================== */ +#define CHARGER_CHARGER_PRE_CHARGE_TIMER_REG_PRE_CHARGE_TIMER_Pos (16UL) /*!< PRE_CHARGE_TIMER (Bit 16) */ +#define CHARGER_CHARGER_PRE_CHARGE_TIMER_REG_PRE_CHARGE_TIMER_Msk (0x7fff0000UL) /*!< PRE_CHARGE_TIMER (Bitfield-Mask: 0x7fff) */ +#define CHARGER_CHARGER_PRE_CHARGE_TIMER_REG_MAX_PRE_CHARGE_TIME_Pos (0UL) /*!< MAX_PRE_CHARGE_TIME (Bit 0) */ +#define CHARGER_CHARGER_PRE_CHARGE_TIMER_REG_MAX_PRE_CHARGE_TIME_Msk (0x7fffUL) /*!< MAX_PRE_CHARGE_TIME (Bitfield-Mask: 0x7fff) */ +/* =============================================== CHARGER_PWR_UP_TIMER_REG ================================================ */ +#define CHARGER_CHARGER_PWR_UP_TIMER_REG_CHARGER_PWR_UP_TIMER_Pos (16UL) /*!< CHARGER_PWR_UP_TIMER (Bit 16) */ +#define CHARGER_CHARGER_PWR_UP_TIMER_REG_CHARGER_PWR_UP_TIMER_Msk (0x3ff0000UL) /*!< CHARGER_PWR_UP_TIMER (Bitfield-Mask: 0x3ff) */ +#define CHARGER_CHARGER_PWR_UP_TIMER_REG_CHARGER_PWR_UP_SETTLING_Pos (0UL) /*!< CHARGER_PWR_UP_SETTLING (Bit 0) */ +#define CHARGER_CHARGER_PWR_UP_TIMER_REG_CHARGER_PWR_UP_SETTLING_Msk (0x3ffUL) /*!< CHARGER_PWR_UP_SETTLING (Bitfield-Mask: 0x3ff) */ +/* =============================================== CHARGER_STATE_IRQ_CLR_REG =============================================== */ +#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CV_TO_PRECHARGE_IRQ_CLR_Pos (11UL) /*!< CV_TO_PRECHARGE_IRQ_CLR (Bit 11) */ +#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CV_TO_PRECHARGE_IRQ_CLR_Msk (0x800UL) /*!< CV_TO_PRECHARGE_IRQ_CLR (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CC_TO_PRECHARGE_IRQ_CLR_Pos (10UL) /*!< CC_TO_PRECHARGE_IRQ_CLR (Bit 10) */ +#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CC_TO_PRECHARGE_IRQ_CLR_Msk (0x400UL) /*!< CC_TO_PRECHARGE_IRQ_CLR (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CV_TO_CC_IRQ_CLR_Pos (9UL) /*!< CV_TO_CC_IRQ_CLR (Bit 9) */ +#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CV_TO_CC_IRQ_CLR_Msk (0x200UL) /*!< CV_TO_CC_IRQ_CLR (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_TBAT_STATUS_UPDATE_IRQ_CLR_Pos (8UL) /*!< TBAT_STATUS_UPDATE_IRQ_CLR (Bit 8) */ +#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_TBAT_STATUS_UPDATE_IRQ_CLR_Msk (0x100UL) /*!< TBAT_STATUS_UPDATE_IRQ_CLR (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_TBAT_PROT_TO_PRECHARGE_IRQ_CLR_Pos (7UL) /*!< TBAT_PROT_TO_PRECHARGE_IRQ_CLR (Bit 7) */ +#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_TBAT_PROT_TO_PRECHARGE_IRQ_CLR_Msk (0x80UL) /*!< TBAT_PROT_TO_PRECHARGE_IRQ_CLR (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_TDIE_PROT_TO_PRECHARGE_IRQ_CLR_Pos (6UL) /*!< TDIE_PROT_TO_PRECHARGE_IRQ_CLR (Bit 6) */ +#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_TDIE_PROT_TO_PRECHARGE_IRQ_CLR_Msk (0x40UL) /*!< TDIE_PROT_TO_PRECHARGE_IRQ_CLR (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_EOC_TO_PRECHARGE_IRQ_CLR_Pos (5UL) /*!< EOC_TO_PRECHARGE_IRQ_CLR (Bit 5) */ +#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_EOC_TO_PRECHARGE_IRQ_CLR_Msk (0x20UL) /*!< EOC_TO_PRECHARGE_IRQ_CLR (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CV_TO_EOC_IRQ_CLR_Pos (4UL) /*!< CV_TO_EOC_IRQ_CLR (Bit 4) */ +#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CV_TO_EOC_IRQ_CLR_Msk (0x10UL) /*!< CV_TO_EOC_IRQ_CLR (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CC_TO_EOC_IRQ_CLR_Pos (3UL) /*!< CC_TO_EOC_IRQ_CLR (Bit 3) */ +#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CC_TO_EOC_IRQ_CLR_Msk (0x8UL) /*!< CC_TO_EOC_IRQ_CLR (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CC_TO_CV_IRQ_CLR_Pos (2UL) /*!< CC_TO_CV_IRQ_CLR (Bit 2) */ +#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CC_TO_CV_IRQ_CLR_Msk (0x4UL) /*!< CC_TO_CV_IRQ_CLR (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_PRECHARGE_TO_CC_IRQ_CLR_Pos (1UL) /*!< PRECHARGE_TO_CC_IRQ_CLR (Bit 1) */ +#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_PRECHARGE_TO_CC_IRQ_CLR_Msk (0x2UL) /*!< PRECHARGE_TO_CC_IRQ_CLR (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_DISABLED_TO_PRECHARGE_IRQ_CLR_Pos (0UL) /*!< DISABLED_TO_PRECHARGE_IRQ_CLR (Bit 0) */ +#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_DISABLED_TO_PRECHARGE_IRQ_CLR_Msk (0x1UL) /*!< DISABLED_TO_PRECHARGE_IRQ_CLR (Bitfield-Mask: 0x01) */ +/* ============================================== CHARGER_STATE_IRQ_MASK_REG =============================================== */ +#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CV_TO_PRECHARGE_IRQ_EN_Pos (11UL) /*!< CV_TO_PRECHARGE_IRQ_EN (Bit 11) */ +#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CV_TO_PRECHARGE_IRQ_EN_Msk (0x800UL) /*!< CV_TO_PRECHARGE_IRQ_EN (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CC_TO_PRECHARGE_IRQ_EN_Pos (10UL) /*!< CC_TO_PRECHARGE_IRQ_EN (Bit 10) */ +#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CC_TO_PRECHARGE_IRQ_EN_Msk (0x400UL) /*!< CC_TO_PRECHARGE_IRQ_EN (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CV_TO_CC_IRQ_EN_Pos (9UL) /*!< CV_TO_CC_IRQ_EN (Bit 9) */ +#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CV_TO_CC_IRQ_EN_Msk (0x200UL) /*!< CV_TO_CC_IRQ_EN (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_TBAT_STATUS_UPDATE_IRQ_EN_Pos (8UL) /*!< TBAT_STATUS_UPDATE_IRQ_EN (Bit 8) */ +#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_TBAT_STATUS_UPDATE_IRQ_EN_Msk (0x100UL) /*!< TBAT_STATUS_UPDATE_IRQ_EN (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_TBAT_PROT_TO_PRECHARGE_IRQ_EN_Pos (7UL) /*!< TBAT_PROT_TO_PRECHARGE_IRQ_EN (Bit 7) */ +#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_TBAT_PROT_TO_PRECHARGE_IRQ_EN_Msk (0x80UL) /*!< TBAT_PROT_TO_PRECHARGE_IRQ_EN (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_TDIE_PROT_TO_PRECHARGE_IRQ_EN_Pos (6UL) /*!< TDIE_PROT_TO_PRECHARGE_IRQ_EN (Bit 6) */ +#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_TDIE_PROT_TO_PRECHARGE_IRQ_EN_Msk (0x40UL) /*!< TDIE_PROT_TO_PRECHARGE_IRQ_EN (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_EOC_TO_PRECHARGE_IRQ_EN_Pos (5UL) /*!< EOC_TO_PRECHARGE_IRQ_EN (Bit 5) */ +#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_EOC_TO_PRECHARGE_IRQ_EN_Msk (0x20UL) /*!< EOC_TO_PRECHARGE_IRQ_EN (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CV_TO_EOC_IRQ_EN_Pos (4UL) /*!< CV_TO_EOC_IRQ_EN (Bit 4) */ +#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CV_TO_EOC_IRQ_EN_Msk (0x10UL) /*!< CV_TO_EOC_IRQ_EN (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CC_TO_EOC_IRQ_EN_Pos (3UL) /*!< CC_TO_EOC_IRQ_EN (Bit 3) */ +#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CC_TO_EOC_IRQ_EN_Msk (0x8UL) /*!< CC_TO_EOC_IRQ_EN (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CC_TO_CV_IRQ_EN_Pos (2UL) /*!< CC_TO_CV_IRQ_EN (Bit 2) */ +#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CC_TO_CV_IRQ_EN_Msk (0x4UL) /*!< CC_TO_CV_IRQ_EN (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_PRECHARGE_TO_CC_IRQ_EN_Pos (1UL) /*!< PRECHARGE_TO_CC_IRQ_EN (Bit 1) */ +#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_PRECHARGE_TO_CC_IRQ_EN_Msk (0x2UL) /*!< PRECHARGE_TO_CC_IRQ_EN (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_DISABLED_TO_PRECHARGE_IRQ_EN_Pos (0UL) /*!< DISABLED_TO_PRECHARGE_IRQ_EN (Bit 0) */ +#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_DISABLED_TO_PRECHARGE_IRQ_EN_Msk (0x1UL) /*!< DISABLED_TO_PRECHARGE_IRQ_EN (Bitfield-Mask: 0x01) */ +/* ============================================= CHARGER_STATE_IRQ_STATUS_REG ============================================== */ +#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CV_TO_PRECHARGE_IRQ_Pos (11UL) /*!< CV_TO_PRECHARGE_IRQ (Bit 11) */ +#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CV_TO_PRECHARGE_IRQ_Msk (0x800UL) /*!< CV_TO_PRECHARGE_IRQ (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CC_TO_PRECHARGE_IRQ_Pos (10UL) /*!< CC_TO_PRECHARGE_IRQ (Bit 10) */ +#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CC_TO_PRECHARGE_IRQ_Msk (0x400UL) /*!< CC_TO_PRECHARGE_IRQ (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CV_TO_CC_IRQ_Pos (9UL) /*!< CV_TO_CC_IRQ (Bit 9) */ +#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CV_TO_CC_IRQ_Msk (0x200UL) /*!< CV_TO_CC_IRQ (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_TBAT_STATUS_UPDATE_IRQ_Pos (8UL) /*!< TBAT_STATUS_UPDATE_IRQ (Bit 8) */ +#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_TBAT_STATUS_UPDATE_IRQ_Msk (0x100UL) /*!< TBAT_STATUS_UPDATE_IRQ (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_TBAT_PROT_TO_PRECHARGE_IRQ_Pos (7UL) /*!< TBAT_PROT_TO_PRECHARGE_IRQ (Bit 7) */ +#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_TBAT_PROT_TO_PRECHARGE_IRQ_Msk (0x80UL) /*!< TBAT_PROT_TO_PRECHARGE_IRQ (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_TDIE_PROT_TO_PRECHARGE_IRQ_Pos (6UL) /*!< TDIE_PROT_TO_PRECHARGE_IRQ (Bit 6) */ +#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_TDIE_PROT_TO_PRECHARGE_IRQ_Msk (0x40UL) /*!< TDIE_PROT_TO_PRECHARGE_IRQ (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_EOC_TO_PRECHARGE_IRQ_Pos (5UL) /*!< EOC_TO_PRECHARGE_IRQ (Bit 5) */ +#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_EOC_TO_PRECHARGE_IRQ_Msk (0x20UL) /*!< EOC_TO_PRECHARGE_IRQ (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CV_TO_EOC_IRQ_Pos (4UL) /*!< CV_TO_EOC_IRQ (Bit 4) */ +#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CV_TO_EOC_IRQ_Msk (0x10UL) /*!< CV_TO_EOC_IRQ (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CC_TO_EOC_IRQ_Pos (3UL) /*!< CC_TO_EOC_IRQ (Bit 3) */ +#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CC_TO_EOC_IRQ_Msk (0x8UL) /*!< CC_TO_EOC_IRQ (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CC_TO_CV_IRQ_Pos (2UL) /*!< CC_TO_CV_IRQ (Bit 2) */ +#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CC_TO_CV_IRQ_Msk (0x4UL) /*!< CC_TO_CV_IRQ (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_PRECHARGE_TO_CC_IRQ_Pos (1UL) /*!< PRECHARGE_TO_CC_IRQ (Bit 1) */ +#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_PRECHARGE_TO_CC_IRQ_Msk (0x2UL) /*!< PRECHARGE_TO_CC_IRQ (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_DISABLED_TO_PRECHARGE_IRQ_Pos (0UL) /*!< DISABLED_TO_PRECHARGE_IRQ (Bit 0) */ +#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_DISABLED_TO_PRECHARGE_IRQ_Msk (0x1UL) /*!< DISABLED_TO_PRECHARGE_IRQ (Bitfield-Mask: 0x01) */ +/* ================================================== CHARGER_STATUS_REG =================================================== */ +#define CHARGER_CHARGER_STATUS_REG_OVP_EVENTS_DEBOUNCE_CNT_Pos (27UL) /*!< OVP_EVENTS_DEBOUNCE_CNT (Bit 27) */ +#define CHARGER_CHARGER_STATUS_REG_OVP_EVENTS_DEBOUNCE_CNT_Msk (0x38000000UL) /*!< OVP_EVENTS_DEBOUNCE_CNT (Bitfield-Mask: 0x07) */ +#define CHARGER_CHARGER_STATUS_REG_EOC_EVENTS_DEBOUNCE_CNT_Pos (24UL) /*!< EOC_EVENTS_DEBOUNCE_CNT (Bit 24) */ +#define CHARGER_CHARGER_STATUS_REG_EOC_EVENTS_DEBOUNCE_CNT_Msk (0x7000000UL) /*!< EOC_EVENTS_DEBOUNCE_CNT (Bitfield-Mask: 0x07) */ +#define CHARGER_CHARGER_STATUS_REG_TDIE_ERROR_DEBOUNCE_CNT_Pos (21UL) /*!< TDIE_ERROR_DEBOUNCE_CNT (Bit 21) */ +#define CHARGER_CHARGER_STATUS_REG_TDIE_ERROR_DEBOUNCE_CNT_Msk (0xe00000UL) /*!< TDIE_ERROR_DEBOUNCE_CNT (Bitfield-Mask: 0x07) */ +#define CHARGER_CHARGER_STATUS_REG_CHARGER_JEITA_STATE_Pos (18UL) /*!< CHARGER_JEITA_STATE (Bit 18) */ +#define CHARGER_CHARGER_STATUS_REG_CHARGER_JEITA_STATE_Msk (0x1c0000UL) /*!< CHARGER_JEITA_STATE (Bitfield-Mask: 0x07) */ +#define CHARGER_CHARGER_STATUS_REG_CHARGER_STATE_Pos (14UL) /*!< CHARGER_STATE (Bit 14) */ +#define CHARGER_CHARGER_STATUS_REG_CHARGER_STATE_Msk (0x3c000UL) /*!< CHARGER_STATE (Bitfield-Mask: 0x0f) */ +#define CHARGER_CHARGER_STATUS_REG_TBAT_STATUS_Pos (9UL) /*!< TBAT_STATUS (Bit 9) */ +#define CHARGER_CHARGER_STATUS_REG_TBAT_STATUS_Msk (0x3e00UL) /*!< TBAT_STATUS (Bitfield-Mask: 0x1f) */ +#define CHARGER_CHARGER_STATUS_REG_MAIN_TBAT_COMP_OUT_Pos (8UL) /*!< MAIN_TBAT_COMP_OUT (Bit 8) */ +#define CHARGER_CHARGER_STATUS_REG_MAIN_TBAT_COMP_OUT_Msk (0x100UL) /*!< MAIN_TBAT_COMP_OUT (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATUS_REG_TBAT_HOT_COMP_OUT_Pos (7UL) /*!< TBAT_HOT_COMP_OUT (Bit 7) */ +#define CHARGER_CHARGER_STATUS_REG_TBAT_HOT_COMP_OUT_Msk (0x80UL) /*!< TBAT_HOT_COMP_OUT (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATUS_REG_TDIE_COMP_OUT_Pos (6UL) /*!< TDIE_COMP_OUT (Bit 6) */ +#define CHARGER_CHARGER_STATUS_REG_TDIE_COMP_OUT_Msk (0x40UL) /*!< TDIE_COMP_OUT (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATUS_REG_VBAT_OVP_COMP_OUT_Pos (5UL) /*!< VBAT_OVP_COMP_OUT (Bit 5) */ +#define CHARGER_CHARGER_STATUS_REG_VBAT_OVP_COMP_OUT_Msk (0x20UL) /*!< VBAT_OVP_COMP_OUT (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATUS_REG_MAIN_VBAT_COMP_OUT_Pos (4UL) /*!< MAIN_VBAT_COMP_OUT (Bit 4) */ +#define CHARGER_CHARGER_STATUS_REG_MAIN_VBAT_COMP_OUT_Msk (0x10UL) /*!< MAIN_VBAT_COMP_OUT (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATUS_REG_END_OF_CHARGE_Pos (3UL) /*!< END_OF_CHARGE (Bit 3) */ +#define CHARGER_CHARGER_STATUS_REG_END_OF_CHARGE_Msk (0x8UL) /*!< END_OF_CHARGE (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATUS_REG_CHARGER_CV_MODE_Pos (2UL) /*!< CHARGER_CV_MODE (Bit 2) */ +#define CHARGER_CHARGER_STATUS_REG_CHARGER_CV_MODE_Msk (0x4UL) /*!< CHARGER_CV_MODE (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATUS_REG_CHARGER_CC_MODE_Pos (1UL) /*!< CHARGER_CC_MODE (Bit 1) */ +#define CHARGER_CHARGER_STATUS_REG_CHARGER_CC_MODE_Msk (0x2UL) /*!< CHARGER_CC_MODE (Bitfield-Mask: 0x01) */ +#define CHARGER_CHARGER_STATUS_REG_CHARGER_IS_POWERED_UP_Pos (0UL) /*!< CHARGER_IS_POWERED_UP (Bit 0) */ +#define CHARGER_CHARGER_STATUS_REG_CHARGER_IS_POWERED_UP_Msk (0x1UL) /*!< CHARGER_IS_POWERED_UP (Bitfield-Mask: 0x01) */ +/* ============================================== CHARGER_TBAT_COMP_TIMER_REG ============================================== */ +#define CHARGER_CHARGER_TBAT_COMP_TIMER_REG_TBAT_COMP_TIMER_Pos (16UL) /*!< TBAT_COMP_TIMER (Bit 16) */ +#define CHARGER_CHARGER_TBAT_COMP_TIMER_REG_TBAT_COMP_TIMER_Msk (0x3ff0000UL) /*!< TBAT_COMP_TIMER (Bitfield-Mask: 0x3ff) */ +#define CHARGER_CHARGER_TBAT_COMP_TIMER_REG_TBAT_COMP_SETTLING_Pos (0UL) /*!< TBAT_COMP_SETTLING (Bit 0) */ +#define CHARGER_CHARGER_TBAT_COMP_TIMER_REG_TBAT_COMP_SETTLING_Msk (0x3ffUL) /*!< TBAT_COMP_SETTLING (Bitfield-Mask: 0x3ff) */ +/* ============================================== CHARGER_TBAT_MON_TIMER_REG =============================================== */ +#define CHARGER_CHARGER_TBAT_MON_TIMER_REG_TBAT_MON_TIMER_Pos (16UL) /*!< TBAT_MON_TIMER (Bit 16) */ +#define CHARGER_CHARGER_TBAT_MON_TIMER_REG_TBAT_MON_TIMER_Msk (0x3ff0000UL) /*!< TBAT_MON_TIMER (Bitfield-Mask: 0x3ff) */ +#define CHARGER_CHARGER_TBAT_MON_TIMER_REG_TBAT_MON_INTERVAL_Pos (0UL) /*!< TBAT_MON_INTERVAL (Bit 0) */ +#define CHARGER_CHARGER_TBAT_MON_TIMER_REG_TBAT_MON_INTERVAL_Msk (0x3ffUL) /*!< TBAT_MON_INTERVAL (Bitfield-Mask: 0x3ff) */ +/* ============================================== CHARGER_TDIE_COMP_TIMER_REG ============================================== */ +#define CHARGER_CHARGER_TDIE_COMP_TIMER_REG_TDIE_COMP_TIMER_Pos (16UL) /*!< TDIE_COMP_TIMER (Bit 16) */ +#define CHARGER_CHARGER_TDIE_COMP_TIMER_REG_TDIE_COMP_TIMER_Msk (0x3ff0000UL) /*!< TDIE_COMP_TIMER (Bitfield-Mask: 0x3ff) */ +#define CHARGER_CHARGER_TDIE_COMP_TIMER_REG_TDIE_COMP_SETTLING_Pos (0UL) /*!< TDIE_COMP_SETTLING (Bit 0) */ +#define CHARGER_CHARGER_TDIE_COMP_TIMER_REG_TDIE_COMP_SETTLING_Msk (0x3ffUL) /*!< TDIE_COMP_SETTLING (Bitfield-Mask: 0x3ff) */ +/* =============================================== CHARGER_TEMPSET_PARAM_REG =============================================== */ +#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TDIE_MAX_Pos (24UL) /*!< TDIE_MAX (Bit 24) */ +#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TDIE_MAX_Msk (0x7000000UL) /*!< TDIE_MAX (Bitfield-Mask: 0x07) */ +#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TBAT_HOT_Pos (18UL) /*!< TBAT_HOT (Bit 18) */ +#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TBAT_HOT_Msk (0xfc0000UL) /*!< TBAT_HOT (Bitfield-Mask: 0x3f) */ +#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TBAT_WARM_Pos (12UL) /*!< TBAT_WARM (Bit 12) */ +#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TBAT_WARM_Msk (0x3f000UL) /*!< TBAT_WARM (Bitfield-Mask: 0x3f) */ +#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TBAT_COOL_Pos (6UL) /*!< TBAT_COOL (Bit 6) */ +#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TBAT_COOL_Msk (0xfc0UL) /*!< TBAT_COOL (Bitfield-Mask: 0x3f) */ +#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TBAT_COLD_Pos (0UL) /*!< TBAT_COLD (Bit 0) */ +#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TBAT_COLD_Msk (0x3fUL) /*!< TBAT_COLD (Bitfield-Mask: 0x3f) */ +/* ================================================= CHARGER_TEST_CTRL_REG ================================================= */ +/* ============================================== CHARGER_THOT_COMP_TIMER_REG ============================================== */ +#define CHARGER_CHARGER_THOT_COMP_TIMER_REG_THOT_COMP_TIMER_Pos (16UL) /*!< THOT_COMP_TIMER (Bit 16) */ +#define CHARGER_CHARGER_THOT_COMP_TIMER_REG_THOT_COMP_TIMER_Msk (0x3ff0000UL) /*!< THOT_COMP_TIMER (Bitfield-Mask: 0x3ff) */ +#define CHARGER_CHARGER_THOT_COMP_TIMER_REG_THOT_COMP_SETTLING_Pos (0UL) /*!< THOT_COMP_SETTLING (Bit 0) */ +#define CHARGER_CHARGER_THOT_COMP_TIMER_REG_THOT_COMP_SETTLING_Msk (0x3ffUL) /*!< THOT_COMP_SETTLING (Bitfield-Mask: 0x3ff) */ +/* ============================================ CHARGER_TOTAL_CHARGE_TIMER_REG ============================================= */ +#define CHARGER_CHARGER_TOTAL_CHARGE_TIMER_REG_TOTAL_CHARGE_TIMER_Pos (16UL) /*!< TOTAL_CHARGE_TIMER (Bit 16) */ +#define CHARGER_CHARGER_TOTAL_CHARGE_TIMER_REG_TOTAL_CHARGE_TIMER_Msk (0xffff0000UL) /*!< TOTAL_CHARGE_TIMER (Bitfield-Mask: 0xffff) */ +#define CHARGER_CHARGER_TOTAL_CHARGE_TIMER_REG_MAX_TOTAL_CHARGE_TIME_Pos (0UL) /*!< MAX_TOTAL_CHARGE_TIME (Bit 0) */ +#define CHARGER_CHARGER_TOTAL_CHARGE_TIMER_REG_MAX_TOTAL_CHARGE_TIME_Msk (0xffffUL) /*!< MAX_TOTAL_CHARGE_TIME (Bitfield-Mask: 0xffff) */ +/* ============================================== CHARGER_VBAT_COMP_TIMER_REG ============================================== */ +#define CHARGER_CHARGER_VBAT_COMP_TIMER_REG_VBAT_COMP_TIMER_Pos (16UL) /*!< VBAT_COMP_TIMER (Bit 16) */ +#define CHARGER_CHARGER_VBAT_COMP_TIMER_REG_VBAT_COMP_TIMER_Msk (0x3ff0000UL) /*!< VBAT_COMP_TIMER (Bitfield-Mask: 0x3ff) */ +#define CHARGER_CHARGER_VBAT_COMP_TIMER_REG_VBAT_COMP_SETTLING_Pos (0UL) /*!< VBAT_COMP_SETTLING (Bit 0) */ +#define CHARGER_CHARGER_VBAT_COMP_TIMER_REG_VBAT_COMP_SETTLING_Msk (0x3ffUL) /*!< VBAT_COMP_SETTLING (Bitfield-Mask: 0x3ff) */ +/* =============================================== CHARGER_VOLTAGE_PARAM_REG =============================================== */ +#define CHARGER_CHARGER_VOLTAGE_PARAM_REG_V_OVP_Pos (18UL) /*!< V_OVP (Bit 18) */ +#define CHARGER_CHARGER_VOLTAGE_PARAM_REG_V_OVP_Msk (0xfc0000UL) /*!< V_OVP (Bitfield-Mask: 0x3f) */ +#define CHARGER_CHARGER_VOLTAGE_PARAM_REG_V_REPLENISH_Pos (12UL) /*!< V_REPLENISH (Bit 12) */ +#define CHARGER_CHARGER_VOLTAGE_PARAM_REG_V_REPLENISH_Msk (0x3f000UL) /*!< V_REPLENISH (Bitfield-Mask: 0x3f) */ +#define CHARGER_CHARGER_VOLTAGE_PARAM_REG_V_PRECHARGE_Pos (6UL) /*!< V_PRECHARGE (Bit 6) */ +#define CHARGER_CHARGER_VOLTAGE_PARAM_REG_V_PRECHARGE_Msk (0xfc0UL) /*!< V_PRECHARGE (Bitfield-Mask: 0x3f) */ +#define CHARGER_CHARGER_VOLTAGE_PARAM_REG_V_CHARGE_Pos (0UL) /*!< V_CHARGE (Bit 0) */ +#define CHARGER_CHARGER_VOLTAGE_PARAM_REG_V_CHARGE_Msk (0x3fUL) /*!< V_CHARGE (Bitfield-Mask: 0x3f) */ +/* ============================================== CHARGER_VOVP_COMP_TIMER_REG ============================================== */ +#define CHARGER_CHARGER_VOVP_COMP_TIMER_REG_OVP_INTERVAL_CHECK_TIMER_Pos (26UL) /*!< OVP_INTERVAL_CHECK_TIMER (Bit 26) */ +#define CHARGER_CHARGER_VOVP_COMP_TIMER_REG_OVP_INTERVAL_CHECK_TIMER_Msk (0xfc000000UL) /*!< OVP_INTERVAL_CHECK_TIMER (Bitfield-Mask: 0x3f) */ +#define CHARGER_CHARGER_VOVP_COMP_TIMER_REG_VBAT_OVP_COMP_TIMER_Pos (16UL) /*!< VBAT_OVP_COMP_TIMER (Bit 16) */ +#define CHARGER_CHARGER_VOVP_COMP_TIMER_REG_VBAT_OVP_COMP_TIMER_Msk (0x3ff0000UL) /*!< VBAT_OVP_COMP_TIMER (Bitfield-Mask: 0x3ff) */ +#define CHARGER_CHARGER_VOVP_COMP_TIMER_REG_OVP_INTERVAL_CHECK_THRES_Pos (10UL) /*!< OVP_INTERVAL_CHECK_THRES (Bit 10) */ +#define CHARGER_CHARGER_VOVP_COMP_TIMER_REG_OVP_INTERVAL_CHECK_THRES_Msk (0xfc00UL) /*!< OVP_INTERVAL_CHECK_THRES (Bitfield-Mask: 0x3f) */ +#define CHARGER_CHARGER_VOVP_COMP_TIMER_REG_VBAT_OVP_COMP_SETTLING_Pos (0UL) /*!< VBAT_OVP_COMP_SETTLING (Bit 0) */ +#define CHARGER_CHARGER_VOVP_COMP_TIMER_REG_VBAT_OVP_COMP_SETTLING_Msk (0x3ffUL) /*!< VBAT_OVP_COMP_SETTLING (Bitfield-Mask: 0x3ff) */ + + +/* =========================================================================================================================== */ +/* ================ CHIP_VERSION ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== CHIP_ID1_REG ====================================================== */ +#define CHIP_VERSION_CHIP_ID1_REG_CHIP_ID1_Pos (0UL) /*!< CHIP_ID1 (Bit 0) */ +#define CHIP_VERSION_CHIP_ID1_REG_CHIP_ID1_Msk (0xffUL) /*!< CHIP_ID1 (Bitfield-Mask: 0xff) */ +/* ===================================================== CHIP_ID2_REG ====================================================== */ +#define CHIP_VERSION_CHIP_ID2_REG_CHIP_ID2_Pos (0UL) /*!< CHIP_ID2 (Bit 0) */ +#define CHIP_VERSION_CHIP_ID2_REG_CHIP_ID2_Msk (0xffUL) /*!< CHIP_ID2 (Bitfield-Mask: 0xff) */ +/* ===================================================== CHIP_ID3_REG ====================================================== */ +#define CHIP_VERSION_CHIP_ID3_REG_CHIP_ID3_Pos (0UL) /*!< CHIP_ID3 (Bit 0) */ +#define CHIP_VERSION_CHIP_ID3_REG_CHIP_ID3_Msk (0xffUL) /*!< CHIP_ID3 (Bitfield-Mask: 0xff) */ +/* ===================================================== CHIP_ID4_REG ====================================================== */ +#define CHIP_VERSION_CHIP_ID4_REG_CHIP_ID4_Pos (0UL) /*!< CHIP_ID4 (Bit 0) */ +#define CHIP_VERSION_CHIP_ID4_REG_CHIP_ID4_Msk (0xffUL) /*!< CHIP_ID4 (Bitfield-Mask: 0xff) */ +/* =================================================== CHIP_REVISION_REG =================================================== */ +#define CHIP_VERSION_CHIP_REVISION_REG_CHIP_REVISION_Pos (0UL) /*!< CHIP_REVISION (Bit 0) */ +#define CHIP_VERSION_CHIP_REVISION_REG_CHIP_REVISION_Msk (0xffUL) /*!< CHIP_REVISION (Bitfield-Mask: 0xff) */ +/* ===================================================== CHIP_SWC_REG ====================================================== */ +#define CHIP_VERSION_CHIP_SWC_REG_CHIP_SWC_Pos (0UL) /*!< CHIP_SWC (Bit 0) */ +#define CHIP_VERSION_CHIP_SWC_REG_CHIP_SWC_Msk (0xfUL) /*!< CHIP_SWC (Bitfield-Mask: 0x0f) */ +/* ==================================================== CHIP_TEST1_REG ===================================================== */ +#define CHIP_VERSION_CHIP_TEST1_REG_CHIP_LAYOUT_REVISION_Pos (0UL) /*!< CHIP_LAYOUT_REVISION (Bit 0) */ +#define CHIP_VERSION_CHIP_TEST1_REG_CHIP_LAYOUT_REVISION_Msk (0xffUL) /*!< CHIP_LAYOUT_REVISION (Bitfield-Mask: 0xff) */ +/* ==================================================== CHIP_TEST2_REG ===================================================== */ +#define CHIP_VERSION_CHIP_TEST2_REG_CHIP_METAL_OPTION_Pos (0UL) /*!< CHIP_METAL_OPTION (Bit 0) */ +#define CHIP_VERSION_CHIP_TEST2_REG_CHIP_METAL_OPTION_Msk (0xfUL) /*!< CHIP_METAL_OPTION (Bitfield-Mask: 0x0f) */ + + +/* =========================================================================================================================== */ +/* ================ CRG_COM ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== CLK_COM_REG ====================================================== */ +#define CRG_COM_CLK_COM_REG_LCD_EXT_CLK_SEL_Pos (16UL) /*!< LCD_EXT_CLK_SEL (Bit 16) */ +#define CRG_COM_CLK_COM_REG_LCD_EXT_CLK_SEL_Msk (0x30000UL) /*!< LCD_EXT_CLK_SEL (Bitfield-Mask: 0x03) */ +#define CRG_COM_CLK_COM_REG_SNC_DIV_Pos (14UL) /*!< SNC_DIV (Bit 14) */ +#define CRG_COM_CLK_COM_REG_SNC_DIV_Msk (0xc000UL) /*!< SNC_DIV (Bitfield-Mask: 0x03) */ +#define CRG_COM_CLK_COM_REG_I2C2_CLK_SEL_Pos (12UL) /*!< I2C2_CLK_SEL (Bit 12) */ +#define CRG_COM_CLK_COM_REG_I2C2_CLK_SEL_Msk (0x1000UL) /*!< I2C2_CLK_SEL (Bitfield-Mask: 0x01) */ +#define CRG_COM_CLK_COM_REG_I2C2_ENABLE_Pos (11UL) /*!< I2C2_ENABLE (Bit 11) */ +#define CRG_COM_CLK_COM_REG_I2C2_ENABLE_Msk (0x800UL) /*!< I2C2_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_COM_CLK_COM_REG_I2C_CLK_SEL_Pos (10UL) /*!< I2C_CLK_SEL (Bit 10) */ +#define CRG_COM_CLK_COM_REG_I2C_CLK_SEL_Msk (0x400UL) /*!< I2C_CLK_SEL (Bitfield-Mask: 0x01) */ +#define CRG_COM_CLK_COM_REG_I2C_ENABLE_Pos (9UL) /*!< I2C_ENABLE (Bit 9) */ +#define CRG_COM_CLK_COM_REG_I2C_ENABLE_Msk (0x200UL) /*!< I2C_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_COM_CLK_COM_REG_SPI2_CLK_SEL_Pos (8UL) /*!< SPI2_CLK_SEL (Bit 8) */ +#define CRG_COM_CLK_COM_REG_SPI2_CLK_SEL_Msk (0x100UL) /*!< SPI2_CLK_SEL (Bitfield-Mask: 0x01) */ +#define CRG_COM_CLK_COM_REG_SPI2_ENABLE_Pos (7UL) /*!< SPI2_ENABLE (Bit 7) */ +#define CRG_COM_CLK_COM_REG_SPI2_ENABLE_Msk (0x80UL) /*!< SPI2_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_COM_CLK_COM_REG_SPI_CLK_SEL_Pos (6UL) /*!< SPI_CLK_SEL (Bit 6) */ +#define CRG_COM_CLK_COM_REG_SPI_CLK_SEL_Msk (0x40UL) /*!< SPI_CLK_SEL (Bitfield-Mask: 0x01) */ +#define CRG_COM_CLK_COM_REG_SPI_ENABLE_Pos (5UL) /*!< SPI_ENABLE (Bit 5) */ +#define CRG_COM_CLK_COM_REG_SPI_ENABLE_Msk (0x20UL) /*!< SPI_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_COM_CLK_COM_REG_UART3_CLK_SEL_Pos (4UL) /*!< UART3_CLK_SEL (Bit 4) */ +#define CRG_COM_CLK_COM_REG_UART3_CLK_SEL_Msk (0x10UL) /*!< UART3_CLK_SEL (Bitfield-Mask: 0x01) */ +#define CRG_COM_CLK_COM_REG_UART3_ENABLE_Pos (3UL) /*!< UART3_ENABLE (Bit 3) */ +#define CRG_COM_CLK_COM_REG_UART3_ENABLE_Msk (0x8UL) /*!< UART3_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_COM_CLK_COM_REG_UART2_CLK_SEL_Pos (2UL) /*!< UART2_CLK_SEL (Bit 2) */ +#define CRG_COM_CLK_COM_REG_UART2_CLK_SEL_Msk (0x4UL) /*!< UART2_CLK_SEL (Bitfield-Mask: 0x01) */ +#define CRG_COM_CLK_COM_REG_UART2_ENABLE_Pos (1UL) /*!< UART2_ENABLE (Bit 1) */ +#define CRG_COM_CLK_COM_REG_UART2_ENABLE_Msk (0x2UL) /*!< UART2_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_COM_CLK_COM_REG_UART_ENABLE_Pos (0UL) /*!< UART_ENABLE (Bit 0) */ +#define CRG_COM_CLK_COM_REG_UART_ENABLE_Msk (0x1UL) /*!< UART_ENABLE (Bitfield-Mask: 0x01) */ +/* =================================================== RESET_CLK_COM_REG =================================================== */ +#define CRG_COM_RESET_CLK_COM_REG_LCD_EXT_CLK_SEL_Pos (16UL) /*!< LCD_EXT_CLK_SEL (Bit 16) */ +#define CRG_COM_RESET_CLK_COM_REG_LCD_EXT_CLK_SEL_Msk (0x30000UL) /*!< LCD_EXT_CLK_SEL (Bitfield-Mask: 0x03) */ +#define CRG_COM_RESET_CLK_COM_REG_SNC_DIV_Pos (14UL) /*!< SNC_DIV (Bit 14) */ +#define CRG_COM_RESET_CLK_COM_REG_SNC_DIV_Msk (0xc000UL) /*!< SNC_DIV (Bitfield-Mask: 0x03) */ +#define CRG_COM_RESET_CLK_COM_REG_I2C2_CLK_SEL_Pos (12UL) /*!< I2C2_CLK_SEL (Bit 12) */ +#define CRG_COM_RESET_CLK_COM_REG_I2C2_CLK_SEL_Msk (0x1000UL) /*!< I2C2_CLK_SEL (Bitfield-Mask: 0x01) */ +#define CRG_COM_RESET_CLK_COM_REG_I2C2_ENABLE_Pos (11UL) /*!< I2C2_ENABLE (Bit 11) */ +#define CRG_COM_RESET_CLK_COM_REG_I2C2_ENABLE_Msk (0x800UL) /*!< I2C2_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_COM_RESET_CLK_COM_REG_I2C_CLK_SEL_Pos (10UL) /*!< I2C_CLK_SEL (Bit 10) */ +#define CRG_COM_RESET_CLK_COM_REG_I2C_CLK_SEL_Msk (0x400UL) /*!< I2C_CLK_SEL (Bitfield-Mask: 0x01) */ +#define CRG_COM_RESET_CLK_COM_REG_I2C_ENABLE_Pos (9UL) /*!< I2C_ENABLE (Bit 9) */ +#define CRG_COM_RESET_CLK_COM_REG_I2C_ENABLE_Msk (0x200UL) /*!< I2C_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_COM_RESET_CLK_COM_REG_SPI2_CLK_SEL_Pos (8UL) /*!< SPI2_CLK_SEL (Bit 8) */ +#define CRG_COM_RESET_CLK_COM_REG_SPI2_CLK_SEL_Msk (0x100UL) /*!< SPI2_CLK_SEL (Bitfield-Mask: 0x01) */ +#define CRG_COM_RESET_CLK_COM_REG_SPI2_ENABLE_Pos (7UL) /*!< SPI2_ENABLE (Bit 7) */ +#define CRG_COM_RESET_CLK_COM_REG_SPI2_ENABLE_Msk (0x80UL) /*!< SPI2_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_COM_RESET_CLK_COM_REG_SPI_CLK_SEL_Pos (6UL) /*!< SPI_CLK_SEL (Bit 6) */ +#define CRG_COM_RESET_CLK_COM_REG_SPI_CLK_SEL_Msk (0x40UL) /*!< SPI_CLK_SEL (Bitfield-Mask: 0x01) */ +#define CRG_COM_RESET_CLK_COM_REG_SPI_ENABLE_Pos (5UL) /*!< SPI_ENABLE (Bit 5) */ +#define CRG_COM_RESET_CLK_COM_REG_SPI_ENABLE_Msk (0x20UL) /*!< SPI_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_COM_RESET_CLK_COM_REG_UART3_CLK_SEL_Pos (4UL) /*!< UART3_CLK_SEL (Bit 4) */ +#define CRG_COM_RESET_CLK_COM_REG_UART3_CLK_SEL_Msk (0x10UL) /*!< UART3_CLK_SEL (Bitfield-Mask: 0x01) */ +#define CRG_COM_RESET_CLK_COM_REG_UART3_ENABLE_Pos (3UL) /*!< UART3_ENABLE (Bit 3) */ +#define CRG_COM_RESET_CLK_COM_REG_UART3_ENABLE_Msk (0x8UL) /*!< UART3_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_COM_RESET_CLK_COM_REG_UART2_CLK_SEL_Pos (2UL) /*!< UART2_CLK_SEL (Bit 2) */ +#define CRG_COM_RESET_CLK_COM_REG_UART2_CLK_SEL_Msk (0x4UL) /*!< UART2_CLK_SEL (Bitfield-Mask: 0x01) */ +#define CRG_COM_RESET_CLK_COM_REG_UART2_ENABLE_Pos (1UL) /*!< UART2_ENABLE (Bit 1) */ +#define CRG_COM_RESET_CLK_COM_REG_UART2_ENABLE_Msk (0x2UL) /*!< UART2_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_COM_RESET_CLK_COM_REG_UART_ENABLE_Pos (0UL) /*!< UART_ENABLE (Bit 0) */ +#define CRG_COM_RESET_CLK_COM_REG_UART_ENABLE_Msk (0x1UL) /*!< UART_ENABLE (Bitfield-Mask: 0x01) */ +/* ==================================================== SET_CLK_COM_REG ==================================================== */ +#define CRG_COM_SET_CLK_COM_REG_LCD_EXT_CLK_SEL_Pos (16UL) /*!< LCD_EXT_CLK_SEL (Bit 16) */ +#define CRG_COM_SET_CLK_COM_REG_LCD_EXT_CLK_SEL_Msk (0x30000UL) /*!< LCD_EXT_CLK_SEL (Bitfield-Mask: 0x03) */ +#define CRG_COM_SET_CLK_COM_REG_SNC_DIV_Pos (14UL) /*!< SNC_DIV (Bit 14) */ +#define CRG_COM_SET_CLK_COM_REG_SNC_DIV_Msk (0xc000UL) /*!< SNC_DIV (Bitfield-Mask: 0x03) */ +#define CRG_COM_SET_CLK_COM_REG_I2C2_CLK_SEL_Pos (12UL) /*!< I2C2_CLK_SEL (Bit 12) */ +#define CRG_COM_SET_CLK_COM_REG_I2C2_CLK_SEL_Msk (0x1000UL) /*!< I2C2_CLK_SEL (Bitfield-Mask: 0x01) */ +#define CRG_COM_SET_CLK_COM_REG_I2C2_ENABLE_Pos (11UL) /*!< I2C2_ENABLE (Bit 11) */ +#define CRG_COM_SET_CLK_COM_REG_I2C2_ENABLE_Msk (0x800UL) /*!< I2C2_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_COM_SET_CLK_COM_REG_I2C_CLK_SEL_Pos (10UL) /*!< I2C_CLK_SEL (Bit 10) */ +#define CRG_COM_SET_CLK_COM_REG_I2C_CLK_SEL_Msk (0x400UL) /*!< I2C_CLK_SEL (Bitfield-Mask: 0x01) */ +#define CRG_COM_SET_CLK_COM_REG_I2C_ENABLE_Pos (9UL) /*!< I2C_ENABLE (Bit 9) */ +#define CRG_COM_SET_CLK_COM_REG_I2C_ENABLE_Msk (0x200UL) /*!< I2C_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_COM_SET_CLK_COM_REG_SPI2_CLK_SEL_Pos (8UL) /*!< SPI2_CLK_SEL (Bit 8) */ +#define CRG_COM_SET_CLK_COM_REG_SPI2_CLK_SEL_Msk (0x100UL) /*!< SPI2_CLK_SEL (Bitfield-Mask: 0x01) */ +#define CRG_COM_SET_CLK_COM_REG_SPI2_ENABLE_Pos (7UL) /*!< SPI2_ENABLE (Bit 7) */ +#define CRG_COM_SET_CLK_COM_REG_SPI2_ENABLE_Msk (0x80UL) /*!< SPI2_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_COM_SET_CLK_COM_REG_SPI_CLK_SEL_Pos (6UL) /*!< SPI_CLK_SEL (Bit 6) */ +#define CRG_COM_SET_CLK_COM_REG_SPI_CLK_SEL_Msk (0x40UL) /*!< SPI_CLK_SEL (Bitfield-Mask: 0x01) */ +#define CRG_COM_SET_CLK_COM_REG_SPI_ENABLE_Pos (5UL) /*!< SPI_ENABLE (Bit 5) */ +#define CRG_COM_SET_CLK_COM_REG_SPI_ENABLE_Msk (0x20UL) /*!< SPI_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_COM_SET_CLK_COM_REG_UART3_CLK_SEL_Pos (4UL) /*!< UART3_CLK_SEL (Bit 4) */ +#define CRG_COM_SET_CLK_COM_REG_UART3_CLK_SEL_Msk (0x10UL) /*!< UART3_CLK_SEL (Bitfield-Mask: 0x01) */ +#define CRG_COM_SET_CLK_COM_REG_UART3_ENABLE_Pos (3UL) /*!< UART3_ENABLE (Bit 3) */ +#define CRG_COM_SET_CLK_COM_REG_UART3_ENABLE_Msk (0x8UL) /*!< UART3_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_COM_SET_CLK_COM_REG_UART2_CLK_SEL_Pos (2UL) /*!< UART2_CLK_SEL (Bit 2) */ +#define CRG_COM_SET_CLK_COM_REG_UART2_CLK_SEL_Msk (0x4UL) /*!< UART2_CLK_SEL (Bitfield-Mask: 0x01) */ +#define CRG_COM_SET_CLK_COM_REG_UART2_ENABLE_Pos (1UL) /*!< UART2_ENABLE (Bit 1) */ +#define CRG_COM_SET_CLK_COM_REG_UART2_ENABLE_Msk (0x2UL) /*!< UART2_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_COM_SET_CLK_COM_REG_UART_ENABLE_Pos (0UL) /*!< UART_ENABLE (Bit 0) */ +#define CRG_COM_SET_CLK_COM_REG_UART_ENABLE_Msk (0x1UL) /*!< UART_ENABLE (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ CRG_PER ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== CLK_PER_REG ====================================================== */ +#define CRG_PER_CLK_PER_REG_MC_TRIG_DIV_Pos (8UL) /*!< MC_TRIG_DIV (Bit 8) */ +#define CRG_PER_CLK_PER_REG_MC_TRIG_DIV_Msk (0x1f00UL) /*!< MC_TRIG_DIV (Bitfield-Mask: 0x1f) */ +#define CRG_PER_CLK_PER_REG_MC_CLK_DIV_Pos (3UL) /*!< MC_CLK_DIV (Bit 3) */ +#define CRG_PER_CLK_PER_REG_MC_CLK_DIV_Msk (0xf8UL) /*!< MC_CLK_DIV (Bitfield-Mask: 0x1f) */ +#define CRG_PER_CLK_PER_REG_MC_CLK_EN_Pos (2UL) /*!< MC_CLK_EN (Bit 2) */ +#define CRG_PER_CLK_PER_REG_MC_CLK_EN_Msk (0x4UL) /*!< MC_CLK_EN (Bitfield-Mask: 0x01) */ +#define CRG_PER_CLK_PER_REG_LRA_CLK_EN_Pos (1UL) /*!< LRA_CLK_EN (Bit 1) */ +#define CRG_PER_CLK_PER_REG_LRA_CLK_EN_Msk (0x2UL) /*!< LRA_CLK_EN (Bitfield-Mask: 0x01) */ +#define CRG_PER_CLK_PER_REG_GPADC_CLK_SEL_Pos (0UL) /*!< GPADC_CLK_SEL (Bit 0) */ +#define CRG_PER_CLK_PER_REG_GPADC_CLK_SEL_Msk (0x1UL) /*!< GPADC_CLK_SEL (Bitfield-Mask: 0x01) */ +/* ====================================================== PCM_DIV_REG ====================================================== */ +#define CRG_PER_PCM_DIV_REG_PCM_SRC_SEL_Pos (13UL) /*!< PCM_SRC_SEL (Bit 13) */ +#define CRG_PER_PCM_DIV_REG_PCM_SRC_SEL_Msk (0x2000UL) /*!< PCM_SRC_SEL (Bitfield-Mask: 0x01) */ +#define CRG_PER_PCM_DIV_REG_CLK_PCM_EN_Pos (12UL) /*!< CLK_PCM_EN (Bit 12) */ +#define CRG_PER_PCM_DIV_REG_CLK_PCM_EN_Msk (0x1000UL) /*!< CLK_PCM_EN (Bitfield-Mask: 0x01) */ +#define CRG_PER_PCM_DIV_REG_PCM_DIV_Pos (0UL) /*!< PCM_DIV (Bit 0) */ +#define CRG_PER_PCM_DIV_REG_PCM_DIV_Msk (0xfffUL) /*!< PCM_DIV (Bitfield-Mask: 0xfff) */ +/* ===================================================== PCM_FDIV_REG ====================================================== */ +#define CRG_PER_PCM_FDIV_REG_PCM_FDIV_Pos (0UL) /*!< PCM_FDIV (Bit 0) */ +#define CRG_PER_PCM_FDIV_REG_PCM_FDIV_Msk (0xffffUL) /*!< PCM_FDIV (Bitfield-Mask: 0xffff) */ +/* ====================================================== PDM_DIV_REG ====================================================== */ +#define CRG_PER_PDM_DIV_REG_PDM_MASTER_MODE_Pos (9UL) /*!< PDM_MASTER_MODE (Bit 9) */ +#define CRG_PER_PDM_DIV_REG_PDM_MASTER_MODE_Msk (0x200UL) /*!< PDM_MASTER_MODE (Bitfield-Mask: 0x01) */ +#define CRG_PER_PDM_DIV_REG_CLK_PDM_EN_Pos (8UL) /*!< CLK_PDM_EN (Bit 8) */ +#define CRG_PER_PDM_DIV_REG_CLK_PDM_EN_Msk (0x100UL) /*!< CLK_PDM_EN (Bitfield-Mask: 0x01) */ +#define CRG_PER_PDM_DIV_REG_PDM_DIV_Pos (0UL) /*!< PDM_DIV (Bit 0) */ +#define CRG_PER_PDM_DIV_REG_PDM_DIV_Msk (0xffUL) /*!< PDM_DIV (Bitfield-Mask: 0xff) */ +/* =================================================== RESET_CLK_PER_REG =================================================== */ +#define CRG_PER_RESET_CLK_PER_REG_MC_TRIG_DIV_Pos (8UL) /*!< MC_TRIG_DIV (Bit 8) */ +#define CRG_PER_RESET_CLK_PER_REG_MC_TRIG_DIV_Msk (0x1f00UL) /*!< MC_TRIG_DIV (Bitfield-Mask: 0x1f) */ +#define CRG_PER_RESET_CLK_PER_REG_MC_CLK_DIV_Pos (3UL) /*!< MC_CLK_DIV (Bit 3) */ +#define CRG_PER_RESET_CLK_PER_REG_MC_CLK_DIV_Msk (0xf8UL) /*!< MC_CLK_DIV (Bitfield-Mask: 0x1f) */ +#define CRG_PER_RESET_CLK_PER_REG_MC_CLK_EN_Pos (2UL) /*!< MC_CLK_EN (Bit 2) */ +#define CRG_PER_RESET_CLK_PER_REG_MC_CLK_EN_Msk (0x4UL) /*!< MC_CLK_EN (Bitfield-Mask: 0x01) */ +#define CRG_PER_RESET_CLK_PER_REG_LRA_CLK_EN_Pos (1UL) /*!< LRA_CLK_EN (Bit 1) */ +#define CRG_PER_RESET_CLK_PER_REG_LRA_CLK_EN_Msk (0x2UL) /*!< LRA_CLK_EN (Bitfield-Mask: 0x01) */ +#define CRG_PER_RESET_CLK_PER_REG_GPADC_CLK_SEL_Pos (0UL) /*!< GPADC_CLK_SEL (Bit 0) */ +#define CRG_PER_RESET_CLK_PER_REG_GPADC_CLK_SEL_Msk (0x1UL) /*!< GPADC_CLK_SEL (Bitfield-Mask: 0x01) */ +/* ==================================================== SET_CLK_PER_REG ==================================================== */ +#define CRG_PER_SET_CLK_PER_REG_MC_TRIG_DIV_Pos (8UL) /*!< MC_TRIG_DIV (Bit 8) */ +#define CRG_PER_SET_CLK_PER_REG_MC_TRIG_DIV_Msk (0x1f00UL) /*!< MC_TRIG_DIV (Bitfield-Mask: 0x1f) */ +#define CRG_PER_SET_CLK_PER_REG_MC_CLK_DIV_Pos (3UL) /*!< MC_CLK_DIV (Bit 3) */ +#define CRG_PER_SET_CLK_PER_REG_MC_CLK_DIV_Msk (0xf8UL) /*!< MC_CLK_DIV (Bitfield-Mask: 0x1f) */ +#define CRG_PER_SET_CLK_PER_REG_MC_CLK_EN_Pos (2UL) /*!< MC_CLK_EN (Bit 2) */ +#define CRG_PER_SET_CLK_PER_REG_MC_CLK_EN_Msk (0x4UL) /*!< MC_CLK_EN (Bitfield-Mask: 0x01) */ +#define CRG_PER_SET_CLK_PER_REG_LRA_CLK_EN_Pos (1UL) /*!< LRA_CLK_EN (Bit 1) */ +#define CRG_PER_SET_CLK_PER_REG_LRA_CLK_EN_Msk (0x2UL) /*!< LRA_CLK_EN (Bitfield-Mask: 0x01) */ +#define CRG_PER_SET_CLK_PER_REG_GPADC_CLK_SEL_Pos (0UL) /*!< GPADC_CLK_SEL (Bit 0) */ +#define CRG_PER_SET_CLK_PER_REG_GPADC_CLK_SEL_Msk (0x1UL) /*!< GPADC_CLK_SEL (Bitfield-Mask: 0x01) */ +/* ====================================================== SRC_DIV_REG ====================================================== */ +#define CRG_PER_SRC_DIV_REG_CLK_SRC_EN_Pos (8UL) /*!< CLK_SRC_EN (Bit 8) */ +#define CRG_PER_SRC_DIV_REG_CLK_SRC_EN_Msk (0x100UL) /*!< CLK_SRC_EN (Bitfield-Mask: 0x01) */ +#define CRG_PER_SRC_DIV_REG_SRC_DIV_Pos (0UL) /*!< SRC_DIV (Bit 0) */ +#define CRG_PER_SRC_DIV_REG_SRC_DIV_Msk (0xffUL) /*!< SRC_DIV (Bitfield-Mask: 0xff) */ + + +/* =========================================================================================================================== */ +/* ================ CRG_SYS ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== BATCHECK_REG ====================================================== */ +#define CRG_SYS_BATCHECK_REG_BATCHECK_LOAD_ENABLE_Pos (7UL) /*!< BATCHECK_LOAD_ENABLE (Bit 7) */ +#define CRG_SYS_BATCHECK_REG_BATCHECK_LOAD_ENABLE_Msk (0x80UL) /*!< BATCHECK_LOAD_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_SYS_BATCHECK_REG_BATCHECK_ILOAD_Pos (4UL) /*!< BATCHECK_ILOAD (Bit 4) */ +#define CRG_SYS_BATCHECK_REG_BATCHECK_ILOAD_Msk (0x70UL) /*!< BATCHECK_ILOAD (Bitfield-Mask: 0x07) */ +#define CRG_SYS_BATCHECK_REG_BATCHECK_TRIM_Pos (0UL) /*!< BATCHECK_TRIM (Bit 0) */ +#define CRG_SYS_BATCHECK_REG_BATCHECK_TRIM_Msk (0xfUL) /*!< BATCHECK_TRIM (Bitfield-Mask: 0x0f) */ +/* ====================================================== CLK_SYS_REG ====================================================== */ +#define CRG_SYS_CLK_SYS_REG_CLK_CHG_EN_Pos (5UL) /*!< CLK_CHG_EN (Bit 5) */ +#define CRG_SYS_CLK_SYS_REG_CLK_CHG_EN_Msk (0x20UL) /*!< CLK_CHG_EN (Bitfield-Mask: 0x01) */ +#define CRG_SYS_CLK_SYS_REG_LCD_RESET_REQ_Pos (4UL) /*!< LCD_RESET_REQ (Bit 4) */ +#define CRG_SYS_CLK_SYS_REG_LCD_RESET_REQ_Msk (0x10UL) /*!< LCD_RESET_REQ (Bitfield-Mask: 0x01) */ +#define CRG_SYS_CLK_SYS_REG_LCD_CLK_SEL_Pos (1UL) /*!< LCD_CLK_SEL (Bit 1) */ +#define CRG_SYS_CLK_SYS_REG_LCD_CLK_SEL_Msk (0x2UL) /*!< LCD_CLK_SEL (Bitfield-Mask: 0x01) */ +#define CRG_SYS_CLK_SYS_REG_LCD_ENABLE_Pos (0UL) /*!< LCD_ENABLE (Bit 0) */ +#define CRG_SYS_CLK_SYS_REG_LCD_ENABLE_Msk (0x1UL) /*!< LCD_ENABLE (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ CRG_TOP ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== ANA_STATUS_REG ===================================================== */ +#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_HIGH_Pos (14UL) /*!< COMP_VBUS_HIGH (Bit 14) */ +#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_HIGH_Msk (0x4000UL) /*!< COMP_VBUS_HIGH (Bitfield-Mask: 0x01) */ +#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_LOW_Pos (13UL) /*!< COMP_VBUS_LOW (Bit 13) */ +#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_LOW_Msk (0x2000UL) /*!< COMP_VBUS_LOW (Bitfield-Mask: 0x01) */ +#define CRG_TOP_ANA_STATUS_REG_COMP_VBAT_HIGH_Pos (12UL) /*!< COMP_VBAT_HIGH (Bit 12) */ +#define CRG_TOP_ANA_STATUS_REG_COMP_VBAT_HIGH_Msk (0x1000UL) /*!< COMP_VBAT_HIGH (Bitfield-Mask: 0x01) */ +#define CRG_TOP_ANA_STATUS_REG_COMP_VBAT_LOW_Pos (11UL) /*!< COMP_VBAT_LOW (Bit 11) */ +#define CRG_TOP_ANA_STATUS_REG_COMP_VBAT_LOW_Msk (0x800UL) /*!< COMP_VBAT_LOW (Bitfield-Mask: 0x01) */ +#define CRG_TOP_ANA_STATUS_REG_COMP_VDD_OK_Pos (10UL) /*!< COMP_VDD_OK (Bit 10) */ +#define CRG_TOP_ANA_STATUS_REG_COMP_VDD_OK_Msk (0x400UL) /*!< COMP_VDD_OK (Bitfield-Mask: 0x01) */ +#define CRG_TOP_ANA_STATUS_REG_VBUS_AVAILABLE_Pos (9UL) /*!< VBUS_AVAILABLE (Bit 9) */ +#define CRG_TOP_ANA_STATUS_REG_VBUS_AVAILABLE_Msk (0x200UL) /*!< VBUS_AVAILABLE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_ANA_STATUS_REG_BANDGAP_OK_Pos (8UL) /*!< BANDGAP_OK (Bit 8) */ +#define CRG_TOP_ANA_STATUS_REG_BANDGAP_OK_Msk (0x100UL) /*!< BANDGAP_OK (Bitfield-Mask: 0x01) */ +#define CRG_TOP_ANA_STATUS_REG_LDO_3V0_VBAT_OK_Pos (7UL) /*!< LDO_3V0_VBAT_OK (Bit 7) */ +#define CRG_TOP_ANA_STATUS_REG_LDO_3V0_VBAT_OK_Msk (0x80UL) /*!< LDO_3V0_VBAT_OK (Bitfield-Mask: 0x01) */ +#define CRG_TOP_ANA_STATUS_REG_LDO_3V0_VBUS_OK_Pos (6UL) /*!< LDO_3V0_VBUS_OK (Bit 6) */ +#define CRG_TOP_ANA_STATUS_REG_LDO_3V0_VBUS_OK_Msk (0x40UL) /*!< LDO_3V0_VBUS_OK (Bitfield-Mask: 0x01) */ +#define CRG_TOP_ANA_STATUS_REG_LDO_1V8P_OK_Pos (5UL) /*!< LDO_1V8P_OK (Bit 5) */ +#define CRG_TOP_ANA_STATUS_REG_LDO_1V8P_OK_Msk (0x20UL) /*!< LDO_1V8P_OK (Bitfield-Mask: 0x01) */ +#define CRG_TOP_ANA_STATUS_REG_LDO_1V8_OK_Pos (4UL) /*!< LDO_1V8_OK (Bit 4) */ +#define CRG_TOP_ANA_STATUS_REG_LDO_1V8_OK_Msk (0x10UL) /*!< LDO_1V8_OK (Bitfield-Mask: 0x01) */ +#define CRG_TOP_ANA_STATUS_REG_LDO_RADIO_OK_Pos (3UL) /*!< LDO_RADIO_OK (Bit 3) */ +#define CRG_TOP_ANA_STATUS_REG_LDO_RADIO_OK_Msk (0x8UL) /*!< LDO_RADIO_OK (Bitfield-Mask: 0x01) */ +#define CRG_TOP_ANA_STATUS_REG_LDO_CORE_OK_Pos (2UL) /*!< LDO_CORE_OK (Bit 2) */ +#define CRG_TOP_ANA_STATUS_REG_LDO_CORE_OK_Msk (0x4UL) /*!< LDO_CORE_OK (Bitfield-Mask: 0x01) */ +#define CRG_TOP_ANA_STATUS_REG_LDO_VDD_HIGH_OK_Pos (1UL) /*!< LDO_VDD_HIGH_OK (Bit 1) */ +#define CRG_TOP_ANA_STATUS_REG_LDO_VDD_HIGH_OK_Msk (0x2UL) /*!< LDO_VDD_HIGH_OK (Bitfield-Mask: 0x01) */ +#define CRG_TOP_ANA_STATUS_REG_BOD_VIN_NOK_Pos (0UL) /*!< BOD_VIN_NOK (Bit 0) */ +#define CRG_TOP_ANA_STATUS_REG_BOD_VIN_NOK_Msk (0x1UL) /*!< BOD_VIN_NOK (Bitfield-Mask: 0x01) */ +/* ====================================================== BANDGAP_REG ====================================================== */ +#define CRG_TOP_BANDGAP_REG_BANDGAP_ENABLE_CLAMP_Pos (12UL) /*!< BANDGAP_ENABLE_CLAMP (Bit 12) */ +#define CRG_TOP_BANDGAP_REG_BANDGAP_ENABLE_CLAMP_Msk (0x1000UL) /*!< BANDGAP_ENABLE_CLAMP (Bitfield-Mask: 0x01) */ +#define CRG_TOP_BANDGAP_REG_BGR_ITRIM_Pos (6UL) /*!< BGR_ITRIM (Bit 6) */ +#define CRG_TOP_BANDGAP_REG_BGR_ITRIM_Msk (0xfc0UL) /*!< BGR_ITRIM (Bitfield-Mask: 0x3f) */ +#define CRG_TOP_BANDGAP_REG_SYSRAM_LPMX_Pos (5UL) /*!< SYSRAM_LPMX (Bit 5) */ +#define CRG_TOP_BANDGAP_REG_SYSRAM_LPMX_Msk (0x20UL) /*!< SYSRAM_LPMX (Bitfield-Mask: 0x01) */ +#define CRG_TOP_BANDGAP_REG_BGR_TRIM_Pos (0UL) /*!< BGR_TRIM (Bit 0) */ +#define CRG_TOP_BANDGAP_REG_BGR_TRIM_Msk (0x1fUL) /*!< BGR_TRIM (Bitfield-Mask: 0x1f) */ +/* =================================================== BIAS_VREF_SEL_REG =================================================== */ +#define CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF2_SEL_Pos (4UL) /*!< BIAS_VREF_RF2_SEL (Bit 4) */ +#define CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF2_SEL_Msk (0xf0UL) /*!< BIAS_VREF_RF2_SEL (Bitfield-Mask: 0x0f) */ +#define CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF1_SEL_Pos (0UL) /*!< BIAS_VREF_RF1_SEL (Bit 0) */ +#define CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF1_SEL_Msk (0xfUL) /*!< BIAS_VREF_RF1_SEL (Bitfield-Mask: 0x0f) */ +/* ===================================================== BOD_CTRL_REG ====================================================== */ +#define CRG_TOP_BOD_CTRL_REG_BOD_V14_RST_EN_Pos (16UL) /*!< BOD_V14_RST_EN (Bit 16) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_V14_RST_EN_Msk (0x10000UL) /*!< BOD_V14_RST_EN (Bitfield-Mask: 0x01) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_V18F_RST_EN_Pos (15UL) /*!< BOD_V18F_RST_EN (Bit 15) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_V18F_RST_EN_Msk (0x8000UL) /*!< BOD_V18F_RST_EN (Bitfield-Mask: 0x01) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_RST_EN_Pos (14UL) /*!< BOD_VDD_RST_EN (Bit 14) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_RST_EN_Msk (0x4000UL) /*!< BOD_VDD_RST_EN (Bitfield-Mask: 0x01) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_V18P_RST_EN_Pos (13UL) /*!< BOD_V18P_RST_EN (Bit 13) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_V18P_RST_EN_Msk (0x2000UL) /*!< BOD_V18P_RST_EN (Bitfield-Mask: 0x01) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_V18_RST_EN_Pos (12UL) /*!< BOD_V18_RST_EN (Bit 12) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_V18_RST_EN_Msk (0x1000UL) /*!< BOD_V18_RST_EN (Bitfield-Mask: 0x01) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_V30_RST_EN_Pos (11UL) /*!< BOD_V30_RST_EN (Bit 11) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_V30_RST_EN_Msk (0x800UL) /*!< BOD_V30_RST_EN (Bitfield-Mask: 0x01) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_VBAT_RST_EN_Pos (10UL) /*!< BOD_VBAT_RST_EN (Bit 10) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_VBAT_RST_EN_Msk (0x400UL) /*!< BOD_VBAT_RST_EN (Bitfield-Mask: 0x01) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_V14_EN_Pos (9UL) /*!< BOD_V14_EN (Bit 9) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_V14_EN_Msk (0x200UL) /*!< BOD_V14_EN (Bitfield-Mask: 0x01) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_V18F_EN_Pos (8UL) /*!< BOD_V18F_EN (Bit 8) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_V18F_EN_Msk (0x100UL) /*!< BOD_V18F_EN (Bitfield-Mask: 0x01) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_EN_Pos (7UL) /*!< BOD_VDD_EN (Bit 7) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_EN_Msk (0x80UL) /*!< BOD_VDD_EN (Bitfield-Mask: 0x01) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_V18P_EN_Pos (6UL) /*!< BOD_V18P_EN (Bit 6) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_V18P_EN_Msk (0x40UL) /*!< BOD_V18P_EN (Bitfield-Mask: 0x01) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_V18_EN_Pos (5UL) /*!< BOD_V18_EN (Bit 5) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_V18_EN_Msk (0x20UL) /*!< BOD_V18_EN (Bitfield-Mask: 0x01) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_V30_EN_Pos (4UL) /*!< BOD_V30_EN (Bit 4) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_V30_EN_Msk (0x10UL) /*!< BOD_V30_EN (Bitfield-Mask: 0x01) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_VBAT_EN_Pos (3UL) /*!< BOD_VBAT_EN (Bit 3) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_VBAT_EN_Msk (0x8UL) /*!< BOD_VBAT_EN (Bitfield-Mask: 0x01) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_STATUS_CLEAR_Pos (2UL) /*!< BOD_STATUS_CLEAR (Bit 2) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_STATUS_CLEAR_Msk (0x4UL) /*!< BOD_STATUS_CLEAR (Bitfield-Mask: 0x01) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_CLK_DIV_Pos (0UL) /*!< BOD_CLK_DIV (Bit 0) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_CLK_DIV_Msk (0x3UL) /*!< BOD_CLK_DIV (Bitfield-Mask: 0x03) */ +/* =================================================== BOD_LVL_CTRL0_REG =================================================== */ +#define CRG_TOP_BOD_LVL_CTRL0_REG_BOD_LVL_V18_Pos (18UL) /*!< BOD_LVL_V18 (Bit 18) */ +#define CRG_TOP_BOD_LVL_CTRL0_REG_BOD_LVL_V18_Msk (0x7fc0000UL) /*!< BOD_LVL_V18 (Bitfield-Mask: 0x1ff) */ +#define CRG_TOP_BOD_LVL_CTRL0_REG_BOD_LVL_V30_Pos (9UL) /*!< BOD_LVL_V30 (Bit 9) */ +#define CRG_TOP_BOD_LVL_CTRL0_REG_BOD_LVL_V30_Msk (0x3fe00UL) /*!< BOD_LVL_V30 (Bitfield-Mask: 0x1ff) */ +#define CRG_TOP_BOD_LVL_CTRL0_REG_BOD_LVL_VBAT_Pos (0UL) /*!< BOD_LVL_VBAT (Bit 0) */ +#define CRG_TOP_BOD_LVL_CTRL0_REG_BOD_LVL_VBAT_Msk (0x1ffUL) /*!< BOD_LVL_VBAT (Bitfield-Mask: 0x1ff) */ +/* =================================================== BOD_LVL_CTRL1_REG =================================================== */ +#define CRG_TOP_BOD_LVL_CTRL1_REG_BOD_LVL_VDD_RET_Pos (17UL) /*!< BOD_LVL_VDD_RET (Bit 17) */ +#define CRG_TOP_BOD_LVL_CTRL1_REG_BOD_LVL_VDD_RET_Msk (0x1fe0000UL) /*!< BOD_LVL_VDD_RET (Bitfield-Mask: 0xff) */ +#define CRG_TOP_BOD_LVL_CTRL1_REG_BOD_LVL_VDD_ON_Pos (9UL) /*!< BOD_LVL_VDD_ON (Bit 9) */ +#define CRG_TOP_BOD_LVL_CTRL1_REG_BOD_LVL_VDD_ON_Msk (0x1fe00UL) /*!< BOD_LVL_VDD_ON (Bitfield-Mask: 0xff) */ +#define CRG_TOP_BOD_LVL_CTRL1_REG_BOD_LVL_V18P_Pos (0UL) /*!< BOD_LVL_V18P (Bit 0) */ +#define CRG_TOP_BOD_LVL_CTRL1_REG_BOD_LVL_V18P_Msk (0x1ffUL) /*!< BOD_LVL_V18P (Bitfield-Mask: 0x1ff) */ +/* =================================================== BOD_LVL_CTRL2_REG =================================================== */ +#define CRG_TOP_BOD_LVL_CTRL2_REG_BOD_LVL_V14_Pos (9UL) /*!< BOD_LVL_V14 (Bit 9) */ +#define CRG_TOP_BOD_LVL_CTRL2_REG_BOD_LVL_V14_Msk (0x3fe00UL) /*!< BOD_LVL_V14 (Bitfield-Mask: 0x1ff) */ +#define CRG_TOP_BOD_LVL_CTRL2_REG_BOD_LVL_V18F_Pos (0UL) /*!< BOD_LVL_V18F (Bit 0) */ +#define CRG_TOP_BOD_LVL_CTRL2_REG_BOD_LVL_V18F_Msk (0x1ffUL) /*!< BOD_LVL_V18F (Bitfield-Mask: 0x1ff) */ +/* ==================================================== BOD_STATUS_REG ===================================================== */ +#define CRG_TOP_BOD_STATUS_REG_BOD_V14_Pos (6UL) /*!< BOD_V14 (Bit 6) */ +#define CRG_TOP_BOD_STATUS_REG_BOD_V14_Msk (0x40UL) /*!< BOD_V14 (Bitfield-Mask: 0x01) */ +#define CRG_TOP_BOD_STATUS_REG_BOD_V18F_Pos (5UL) /*!< BOD_V18F (Bit 5) */ +#define CRG_TOP_BOD_STATUS_REG_BOD_V18F_Msk (0x20UL) /*!< BOD_V18F (Bitfield-Mask: 0x01) */ +#define CRG_TOP_BOD_STATUS_REG_BOD_VDD_Pos (4UL) /*!< BOD_VDD (Bit 4) */ +#define CRG_TOP_BOD_STATUS_REG_BOD_VDD_Msk (0x10UL) /*!< BOD_VDD (Bitfield-Mask: 0x01) */ +#define CRG_TOP_BOD_STATUS_REG_BOD_V18P_Pos (3UL) /*!< BOD_V18P (Bit 3) */ +#define CRG_TOP_BOD_STATUS_REG_BOD_V18P_Msk (0x8UL) /*!< BOD_V18P (Bitfield-Mask: 0x01) */ +#define CRG_TOP_BOD_STATUS_REG_BOD_V18_Pos (2UL) /*!< BOD_V18 (Bit 2) */ +#define CRG_TOP_BOD_STATUS_REG_BOD_V18_Msk (0x4UL) /*!< BOD_V18 (Bitfield-Mask: 0x01) */ +#define CRG_TOP_BOD_STATUS_REG_BOD_V30_Pos (1UL) /*!< BOD_V30 (Bit 1) */ +#define CRG_TOP_BOD_STATUS_REG_BOD_V30_Msk (0x2UL) /*!< BOD_V30 (Bitfield-Mask: 0x01) */ +#define CRG_TOP_BOD_STATUS_REG_BOD_VBAT_Pos (0UL) /*!< BOD_VBAT (Bit 0) */ +#define CRG_TOP_BOD_STATUS_REG_BOD_VBAT_Msk (0x1UL) /*!< BOD_VBAT (Bitfield-Mask: 0x01) */ +/* ===================================================== CLK_AMBA_REG ====================================================== */ +#define CRG_TOP_CLK_AMBA_REG_QSPI2_ENABLE_Pos (15UL) /*!< QSPI2_ENABLE (Bit 15) */ +#define CRG_TOP_CLK_AMBA_REG_QSPI2_ENABLE_Msk (0x8000UL) /*!< QSPI2_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_CLK_AMBA_REG_QSPI2_DIV_Pos (13UL) /*!< QSPI2_DIV (Bit 13) */ +#define CRG_TOP_CLK_AMBA_REG_QSPI2_DIV_Msk (0x6000UL) /*!< QSPI2_DIV (Bitfield-Mask: 0x03) */ +#define CRG_TOP_CLK_AMBA_REG_QSPI_ENABLE_Pos (12UL) /*!< QSPI_ENABLE (Bit 12) */ +#define CRG_TOP_CLK_AMBA_REG_QSPI_ENABLE_Msk (0x1000UL) /*!< QSPI_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_CLK_AMBA_REG_QSPI_DIV_Pos (10UL) /*!< QSPI_DIV (Bit 10) */ +#define CRG_TOP_CLK_AMBA_REG_QSPI_DIV_Msk (0xc00UL) /*!< QSPI_DIV (Bitfield-Mask: 0x03) */ +#define CRG_TOP_CLK_AMBA_REG_OTP_ENABLE_Pos (9UL) /*!< OTP_ENABLE (Bit 9) */ +#define CRG_TOP_CLK_AMBA_REG_OTP_ENABLE_Msk (0x200UL) /*!< OTP_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_CLK_AMBA_REG_TRNG_CLK_ENABLE_Pos (8UL) /*!< TRNG_CLK_ENABLE (Bit 8) */ +#define CRG_TOP_CLK_AMBA_REG_TRNG_CLK_ENABLE_Msk (0x100UL) /*!< TRNG_CLK_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_CLK_AMBA_REG_AES_CLK_ENABLE_Pos (6UL) /*!< AES_CLK_ENABLE (Bit 6) */ +#define CRG_TOP_CLK_AMBA_REG_AES_CLK_ENABLE_Msk (0x40UL) /*!< AES_CLK_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Pos (4UL) /*!< PCLK_DIV (Bit 4) */ +#define CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk (0x30UL) /*!< PCLK_DIV (Bitfield-Mask: 0x03) */ +#define CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Pos (0UL) /*!< HCLK_DIV (Bit 0) */ +#define CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk (0x7UL) /*!< HCLK_DIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CLK_CTRL_REG ====================================================== */ +#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Pos (15UL) /*!< RUNNING_AT_PLL96M (Bit 15) */ +#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Msk (0x8000UL) /*!< RUNNING_AT_PLL96M (Bitfield-Mask: 0x01) */ +#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL32M_Pos (14UL) /*!< RUNNING_AT_XTAL32M (Bit 14) */ +#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL32M_Msk (0x4000UL) /*!< RUNNING_AT_XTAL32M (Bitfield-Mask: 0x01) */ +#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC32M_Pos (13UL) /*!< RUNNING_AT_RC32M (Bit 13) */ +#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC32M_Msk (0x2000UL) /*!< RUNNING_AT_RC32M (Bitfield-Mask: 0x01) */ +#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_LP_CLK_Pos (12UL) /*!< RUNNING_AT_LP_CLK (Bit 12) */ +#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_LP_CLK_Msk (0x1000UL) /*!< RUNNING_AT_LP_CLK (Bitfield-Mask: 0x01) */ +#define CRG_TOP_CLK_CTRL_REG_USB_CLK_SRC_Pos (4UL) /*!< USB_CLK_SRC (Bit 4) */ +#define CRG_TOP_CLK_CTRL_REG_USB_CLK_SRC_Msk (0x10UL) /*!< USB_CLK_SRC (Bitfield-Mask: 0x01) */ +#define CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos (2UL) /*!< LP_CLK_SEL (Bit 2) */ +#define CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk (0xcUL) /*!< LP_CLK_SEL (Bitfield-Mask: 0x03) */ +#define CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Pos (0UL) /*!< SYS_CLK_SEL (Bit 0) */ +#define CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk (0x3UL) /*!< SYS_CLK_SEL (Bitfield-Mask: 0x03) */ +/* ===================================================== CLK_RADIO_REG ===================================================== */ +#define CRG_TOP_CLK_RADIO_REG_RFCU_ENABLE_Pos (5UL) /*!< RFCU_ENABLE (Bit 5) */ +#define CRG_TOP_CLK_RADIO_REG_RFCU_ENABLE_Msk (0x20UL) /*!< RFCU_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_CLK_RADIO_REG_CMAC_SYNCH_RESET_Pos (4UL) /*!< CMAC_SYNCH_RESET (Bit 4) */ +#define CRG_TOP_CLK_RADIO_REG_CMAC_SYNCH_RESET_Msk (0x10UL) /*!< CMAC_SYNCH_RESET (Bitfield-Mask: 0x01) */ +#define CRG_TOP_CLK_RADIO_REG_CMAC_CLK_SEL_Pos (3UL) /*!< CMAC_CLK_SEL (Bit 3) */ +#define CRG_TOP_CLK_RADIO_REG_CMAC_CLK_SEL_Msk (0x8UL) /*!< CMAC_CLK_SEL (Bitfield-Mask: 0x01) */ +#define CRG_TOP_CLK_RADIO_REG_CMAC_CLK_ENABLE_Pos (2UL) /*!< CMAC_CLK_ENABLE (Bit 2) */ +#define CRG_TOP_CLK_RADIO_REG_CMAC_CLK_ENABLE_Msk (0x4UL) /*!< CMAC_CLK_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_CLK_RADIO_REG_CMAC_DIV_Pos (0UL) /*!< CMAC_DIV (Bit 0) */ +#define CRG_TOP_CLK_RADIO_REG_CMAC_DIV_Msk (0x3UL) /*!< CMAC_DIV (Bitfield-Mask: 0x03) */ +/* ===================================================== CLK_RC32K_REG ===================================================== */ +#define CRG_TOP_CLK_RC32K_REG_RC32K_TRIM_Pos (1UL) /*!< RC32K_TRIM (Bit 1) */ +#define CRG_TOP_CLK_RC32K_REG_RC32K_TRIM_Msk (0x1eUL) /*!< RC32K_TRIM (Bitfield-Mask: 0x0f) */ +#define CRG_TOP_CLK_RC32K_REG_RC32K_ENABLE_Pos (0UL) /*!< RC32K_ENABLE (Bit 0) */ +#define CRG_TOP_CLK_RC32K_REG_RC32K_ENABLE_Msk (0x1UL) /*!< RC32K_ENABLE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLK_RC32M_REG ===================================================== */ +#define CRG_TOP_CLK_RC32M_REG_RC32M_INIT_RANGE_Pos (20UL) /*!< RC32M_INIT_RANGE (Bit 20) */ +#define CRG_TOP_CLK_RC32M_REG_RC32M_INIT_RANGE_Msk (0x300000UL) /*!< RC32M_INIT_RANGE (Bitfield-Mask: 0x03) */ +#define CRG_TOP_CLK_RC32M_REG_RC32M_INIT_DEL_Pos (12UL) /*!< RC32M_INIT_DEL (Bit 12) */ +#define CRG_TOP_CLK_RC32M_REG_RC32M_INIT_DEL_Msk (0xff000UL) /*!< RC32M_INIT_DEL (Bitfield-Mask: 0xff) */ +#define CRG_TOP_CLK_RC32M_REG_RC32M_INIT_DTCF_Pos (9UL) /*!< RC32M_INIT_DTCF (Bit 9) */ +#define CRG_TOP_CLK_RC32M_REG_RC32M_INIT_DTCF_Msk (0xe00UL) /*!< RC32M_INIT_DTCF (Bitfield-Mask: 0x07) */ +#define CRG_TOP_CLK_RC32M_REG_RC32M_INIT_DTC_Pos (5UL) /*!< RC32M_INIT_DTC (Bit 5) */ +#define CRG_TOP_CLK_RC32M_REG_RC32M_INIT_DTC_Msk (0x1e0UL) /*!< RC32M_INIT_DTC (Bitfield-Mask: 0x0f) */ +#define CRG_TOP_CLK_RC32M_REG_RC32M_BIAS_Pos (1UL) /*!< RC32M_BIAS (Bit 1) */ +#define CRG_TOP_CLK_RC32M_REG_RC32M_BIAS_Msk (0x1eUL) /*!< RC32M_BIAS (Bitfield-Mask: 0x0f) */ +#define CRG_TOP_CLK_RC32M_REG_RC32M_ENABLE_Pos (0UL) /*!< RC32M_ENABLE (Bit 0) */ +#define CRG_TOP_CLK_RC32M_REG_RC32M_ENABLE_Msk (0x1UL) /*!< RC32M_ENABLE (Bitfield-Mask: 0x01) */ +/* ====================================================== CLK_RCX_REG ====================================================== */ +#define CRG_TOP_CLK_RCX_REG_RCX_BIAS_Pos (8UL) /*!< RCX_BIAS (Bit 8) */ +#define CRG_TOP_CLK_RCX_REG_RCX_BIAS_Msk (0xf00UL) /*!< RCX_BIAS (Bitfield-Mask: 0x0f) */ +#define CRG_TOP_CLK_RCX_REG_RCX_C0_Pos (7UL) /*!< RCX_C0 (Bit 7) */ +#define CRG_TOP_CLK_RCX_REG_RCX_C0_Msk (0x80UL) /*!< RCX_C0 (Bitfield-Mask: 0x01) */ +#define CRG_TOP_CLK_RCX_REG_RCX_CADJUST_Pos (2UL) /*!< RCX_CADJUST (Bit 2) */ +#define CRG_TOP_CLK_RCX_REG_RCX_CADJUST_Msk (0x7cUL) /*!< RCX_CADJUST (Bitfield-Mask: 0x1f) */ +#define CRG_TOP_CLK_RCX_REG_RCX_RADJUST_Pos (1UL) /*!< RCX_RADJUST (Bit 1) */ +#define CRG_TOP_CLK_RCX_REG_RCX_RADJUST_Msk (0x2UL) /*!< RCX_RADJUST (Bitfield-Mask: 0x01) */ +#define CRG_TOP_CLK_RCX_REG_RCX_ENABLE_Pos (0UL) /*!< RCX_ENABLE (Bit 0) */ +#define CRG_TOP_CLK_RCX_REG_RCX_ENABLE_Msk (0x1UL) /*!< RCX_ENABLE (Bitfield-Mask: 0x01) */ +/* ==================================================== CLK_RTCDIV_REG ===================================================== */ +#define CRG_TOP_CLK_RTCDIV_REG_RTC_RESET_REQ_Pos (21UL) /*!< RTC_RESET_REQ (Bit 21) */ +#define CRG_TOP_CLK_RTCDIV_REG_RTC_RESET_REQ_Msk (0x200000UL) /*!< RTC_RESET_REQ (Bitfield-Mask: 0x01) */ +#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_ENABLE_Pos (20UL) /*!< RTC_DIV_ENABLE (Bit 20) */ +#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_ENABLE_Msk (0x100000UL) /*!< RTC_DIV_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_DENOM_Pos (19UL) /*!< RTC_DIV_DENOM (Bit 19) */ +#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_DENOM_Msk (0x80000UL) /*!< RTC_DIV_DENOM (Bitfield-Mask: 0x01) */ +#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_INT_Pos (10UL) /*!< RTC_DIV_INT (Bit 10) */ +#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_INT_Msk (0x7fc00UL) /*!< RTC_DIV_INT (Bitfield-Mask: 0x1ff) */ +#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_FRAC_Pos (0UL) /*!< RTC_DIV_FRAC (Bit 0) */ +#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_FRAC_Msk (0x3ffUL) /*!< RTC_DIV_FRAC (Bitfield-Mask: 0x3ff) */ +/* ================================================== CLK_SWITCH2XTAL_REG ================================================== */ +#define CRG_TOP_CLK_SWITCH2XTAL_REG_SWITCH2XTAL_Pos (0UL) /*!< SWITCH2XTAL (Bit 0) */ +#define CRG_TOP_CLK_SWITCH2XTAL_REG_SWITCH2XTAL_Msk (0x1UL) /*!< SWITCH2XTAL (Bitfield-Mask: 0x01) */ +/* ====================================================== CLK_TMR_REG ====================================================== */ +#define CRG_TOP_CLK_TMR_REG_TMR2_PWM_AON_MODE_Pos (2UL) /*!< TMR2_PWM_AON_MODE (Bit 2) */ +#define CRG_TOP_CLK_TMR_REG_TMR2_PWM_AON_MODE_Msk (0x4UL) /*!< TMR2_PWM_AON_MODE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_CLK_TMR_REG_TMR_PWM_AON_MODE_Pos (1UL) /*!< TMR_PWM_AON_MODE (Bit 1) */ +#define CRG_TOP_CLK_TMR_REG_TMR_PWM_AON_MODE_Msk (0x2UL) /*!< TMR_PWM_AON_MODE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Pos (0UL) /*!< WAKEUPCT_ENABLE (Bit 0) */ +#define CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Msk (0x1UL) /*!< WAKEUPCT_ENABLE (Bitfield-Mask: 0x01) */ +/* ==================================================== CLK_XTAL32K_REG ==================================================== */ +#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_DISABLE_OUTPUT_Pos (9UL) /*!< XTAL32K_DISABLE_OUTPUT (Bit 9) */ +#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_DISABLE_OUTPUT_Msk (0x200UL) /*!< XTAL32K_DISABLE_OUTPUT (Bitfield-Mask: 0x01) */ +#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_DISABLE_AMPREG_Pos (7UL) /*!< XTAL32K_DISABLE_AMPREG (Bit 7) */ +#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_DISABLE_AMPREG_Msk (0x80UL) /*!< XTAL32K_DISABLE_AMPREG (Bitfield-Mask: 0x01) */ +#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_CUR_Pos (3UL) /*!< XTAL32K_CUR (Bit 3) */ +#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_CUR_Msk (0x78UL) /*!< XTAL32K_CUR (Bitfield-Mask: 0x0f) */ +#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_RBIAS_Pos (1UL) /*!< XTAL32K_RBIAS (Bit 1) */ +#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_RBIAS_Msk (0x6UL) /*!< XTAL32K_RBIAS (Bitfield-Mask: 0x03) */ +#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_ENABLE_Pos (0UL) /*!< XTAL32K_ENABLE (Bit 0) */ +#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_ENABLE_Msk (0x1UL) /*!< XTAL32K_ENABLE (Bitfield-Mask: 0x01) */ +/* ================================================== DISCHARGE_RAIL_REG =================================================== */ +#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18P_Pos (2UL) /*!< RESET_V18P (Bit 2) */ +#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18P_Msk (0x4UL) /*!< RESET_V18P (Bitfield-Mask: 0x01) */ +#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18_Pos (1UL) /*!< RESET_V18 (Bit 1) */ +#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18_Msk (0x2UL) /*!< RESET_V18 (Bitfield-Mask: 0x01) */ +#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V14_Pos (0UL) /*!< RESET_V14 (Bit 0) */ +#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V14_Msk (0x1UL) /*!< RESET_V14 (Bitfield-Mask: 0x01) */ +/* ================================================ LDO_VDDD_HIGH_CTRL_REG ================================================= */ +#define CRG_TOP_LDO_VDDD_HIGH_CTRL_REG_LDO_VDDD_HIGH_LOW_ZOUT_DISABLE_Pos (3UL) /*!< LDO_VDDD_HIGH_LOW_ZOUT_DISABLE (Bit 3) */ +#define CRG_TOP_LDO_VDDD_HIGH_CTRL_REG_LDO_VDDD_HIGH_LOW_ZOUT_DISABLE_Msk (0x8UL) /*!< LDO_VDDD_HIGH_LOW_ZOUT_DISABLE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_LDO_VDDD_HIGH_CTRL_REG_LDO_VDDD_HIGH_STATIC_LOAD_ENABLE_Pos (2UL) /*!< LDO_VDDD_HIGH_STATIC_LOAD_ENABLE (Bit 2) */ +#define CRG_TOP_LDO_VDDD_HIGH_CTRL_REG_LDO_VDDD_HIGH_STATIC_LOAD_ENABLE_Msk (0x4UL) /*!< LDO_VDDD_HIGH_STATIC_LOAD_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_LDO_VDDD_HIGH_CTRL_REG_LDO_VDDD_HIGH_ENABLE_Pos (1UL) /*!< LDO_VDDD_HIGH_ENABLE (Bit 1) */ +#define CRG_TOP_LDO_VDDD_HIGH_CTRL_REG_LDO_VDDD_HIGH_ENABLE_Msk (0x2UL) /*!< LDO_VDDD_HIGH_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_LDO_VDDD_HIGH_CTRL_REG_LDO_VDDD_HIGH_VREF_HOLD_Pos (0UL) /*!< LDO_VDDD_HIGH_VREF_HOLD (Bit 0) */ +#define CRG_TOP_LDO_VDDD_HIGH_CTRL_REG_LDO_VDDD_HIGH_VREF_HOLD_Msk (0x1UL) /*!< LDO_VDDD_HIGH_VREF_HOLD (Bitfield-Mask: 0x01) */ +/* =================================================== P0_PAD_LATCH_REG ==================================================== */ +#define CRG_TOP_P0_PAD_LATCH_REG_P0_LATCH_EN_Pos (0UL) /*!< P0_LATCH_EN (Bit 0) */ +#define CRG_TOP_P0_PAD_LATCH_REG_P0_LATCH_EN_Msk (0xffffffffUL) /*!< P0_LATCH_EN (Bitfield-Mask: 0xffffffff) */ +/* ================================================ P0_RESET_PAD_LATCH_REG ================================================= */ +#define CRG_TOP_P0_RESET_PAD_LATCH_REG_P0_RESET_LATCH_EN_Pos (0UL) /*!< P0_RESET_LATCH_EN (Bit 0) */ +#define CRG_TOP_P0_RESET_PAD_LATCH_REG_P0_RESET_LATCH_EN_Msk (0xffffffffUL) /*!< P0_RESET_LATCH_EN (Bitfield-Mask: 0xffffffff) */ +/* ================================================= P0_SET_PAD_LATCH_REG ================================================== */ +#define CRG_TOP_P0_SET_PAD_LATCH_REG_P0_SET_LATCH_EN_Pos (0UL) /*!< P0_SET_LATCH_EN (Bit 0) */ +#define CRG_TOP_P0_SET_PAD_LATCH_REG_P0_SET_LATCH_EN_Msk (0xffffffffUL) /*!< P0_SET_LATCH_EN (Bitfield-Mask: 0xffffffff) */ +/* =================================================== P1_PAD_LATCH_REG ==================================================== */ +#define CRG_TOP_P1_PAD_LATCH_REG_P1_LATCH_EN_Pos (0UL) /*!< P1_LATCH_EN (Bit 0) */ +#define CRG_TOP_P1_PAD_LATCH_REG_P1_LATCH_EN_Msk (0x7fffffUL) /*!< P1_LATCH_EN (Bitfield-Mask: 0x7fffff) */ +/* ================================================ P1_RESET_PAD_LATCH_REG ================================================= */ +#define CRG_TOP_P1_RESET_PAD_LATCH_REG_P1_RESET_LATCH_EN_Pos (0UL) /*!< P1_RESET_LATCH_EN (Bit 0) */ +#define CRG_TOP_P1_RESET_PAD_LATCH_REG_P1_RESET_LATCH_EN_Msk (0x7fffffUL) /*!< P1_RESET_LATCH_EN (Bitfield-Mask: 0x7fffff) */ +/* ================================================= P1_SET_PAD_LATCH_REG ================================================== */ +#define CRG_TOP_P1_SET_PAD_LATCH_REG_P1_SET_LATCH_EN_Pos (0UL) /*!< P1_SET_LATCH_EN (Bit 0) */ +#define CRG_TOP_P1_SET_PAD_LATCH_REG_P1_SET_LATCH_EN_Msk (0x7fffffUL) /*!< P1_SET_LATCH_EN (Bitfield-Mask: 0x7fffff) */ +/* ===================================================== PMU_CTRL_REG ====================================================== */ +#define CRG_TOP_PMU_CTRL_REG_ENABLE_CLKLESS_Pos (8UL) /*!< ENABLE_CLKLESS (Bit 8) */ +#define CRG_TOP_PMU_CTRL_REG_ENABLE_CLKLESS_Msk (0x100UL) /*!< ENABLE_CLKLESS (Bitfield-Mask: 0x01) */ +#define CRG_TOP_PMU_CTRL_REG_RETAIN_CACHE_Pos (7UL) /*!< RETAIN_CACHE (Bit 7) */ +#define CRG_TOP_PMU_CTRL_REG_RETAIN_CACHE_Msk (0x80UL) /*!< RETAIN_CACHE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_PMU_CTRL_REG_SYS_SLEEP_Pos (6UL) /*!< SYS_SLEEP (Bit 6) */ +#define CRG_TOP_PMU_CTRL_REG_SYS_SLEEP_Msk (0x40UL) /*!< SYS_SLEEP (Bitfield-Mask: 0x01) */ +#define CRG_TOP_PMU_CTRL_REG_RESET_ON_WAKEUP_Pos (5UL) /*!< RESET_ON_WAKEUP (Bit 5) */ +#define CRG_TOP_PMU_CTRL_REG_RESET_ON_WAKEUP_Msk (0x20UL) /*!< RESET_ON_WAKEUP (Bitfield-Mask: 0x01) */ +#define CRG_TOP_PMU_CTRL_REG_MAP_BANDGAP_EN_Pos (4UL) /*!< MAP_BANDGAP_EN (Bit 4) */ +#define CRG_TOP_PMU_CTRL_REG_MAP_BANDGAP_EN_Msk (0x10UL) /*!< MAP_BANDGAP_EN (Bitfield-Mask: 0x01) */ +#define CRG_TOP_PMU_CTRL_REG_COM_SLEEP_Pos (3UL) /*!< COM_SLEEP (Bit 3) */ +#define CRG_TOP_PMU_CTRL_REG_COM_SLEEP_Msk (0x8UL) /*!< COM_SLEEP (Bitfield-Mask: 0x01) */ +#define CRG_TOP_PMU_CTRL_REG_TIM_SLEEP_Pos (2UL) /*!< TIM_SLEEP (Bit 2) */ +#define CRG_TOP_PMU_CTRL_REG_TIM_SLEEP_Msk (0x4UL) /*!< TIM_SLEEP (Bitfield-Mask: 0x01) */ +#define CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Pos (1UL) /*!< RADIO_SLEEP (Bit 1) */ +#define CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Msk (0x2UL) /*!< RADIO_SLEEP (Bitfield-Mask: 0x01) */ +#define CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Pos (0UL) /*!< PERIPH_SLEEP (Bit 0) */ +#define CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Msk (0x1UL) /*!< PERIPH_SLEEP (Bitfield-Mask: 0x01) */ +/* ===================================================== PMU_SLEEP_REG ===================================================== */ +#define CRG_TOP_PMU_SLEEP_REG_CLAMP_VDD_WKUP_MAX_Pos (18UL) /*!< CLAMP_VDD_WKUP_MAX (Bit 18) */ +#define CRG_TOP_PMU_SLEEP_REG_CLAMP_VDD_WKUP_MAX_Msk (0x40000UL) /*!< CLAMP_VDD_WKUP_MAX (Bitfield-Mask: 0x01) */ +#define CRG_TOP_PMU_SLEEP_REG_ULTRA_FAST_WAKEUP_Pos (17UL) /*!< ULTRA_FAST_WAKEUP (Bit 17) */ +#define CRG_TOP_PMU_SLEEP_REG_ULTRA_FAST_WAKEUP_Msk (0x20000UL) /*!< ULTRA_FAST_WAKEUP (Bitfield-Mask: 0x01) */ +#define CRG_TOP_PMU_SLEEP_REG_FAST_WAKEUP_Pos (16UL) /*!< FAST_WAKEUP (Bit 16) */ +#define CRG_TOP_PMU_SLEEP_REG_FAST_WAKEUP_Msk (0x10000UL) /*!< FAST_WAKEUP (Bitfield-Mask: 0x01) */ +#define CRG_TOP_PMU_SLEEP_REG_BOD_SLEEP_INTERVAL_Pos (12UL) /*!< BOD_SLEEP_INTERVAL (Bit 12) */ +#define CRG_TOP_PMU_SLEEP_REG_BOD_SLEEP_INTERVAL_Msk (0xf000UL) /*!< BOD_SLEEP_INTERVAL (Bitfield-Mask: 0x0f) */ +#define CRG_TOP_PMU_SLEEP_REG_BG_REFRESH_INTERVAL_Pos (0UL) /*!< BG_REFRESH_INTERVAL (Bit 0) */ +#define CRG_TOP_PMU_SLEEP_REG_BG_REFRESH_INTERVAL_Msk (0xfffUL) /*!< BG_REFRESH_INTERVAL (Bitfield-Mask: 0xfff) */ +/* ===================================================== PMU_TRIM_REG ====================================================== */ +#define CRG_TOP_PMU_TRIM_REG_LDO_1V8_TRIM_Pos (12UL) /*!< LDO_1V8_TRIM (Bit 12) */ +#define CRG_TOP_PMU_TRIM_REG_LDO_1V8_TRIM_Msk (0xf000UL) /*!< LDO_1V8_TRIM (Bitfield-Mask: 0x0f) */ +#define CRG_TOP_PMU_TRIM_REG_LDO_1V8P_TRIM_Pos (8UL) /*!< LDO_1V8P_TRIM (Bit 8) */ +#define CRG_TOP_PMU_TRIM_REG_LDO_1V8P_TRIM_Msk (0xf00UL) /*!< LDO_1V8P_TRIM (Bitfield-Mask: 0x0f) */ +#define CRG_TOP_PMU_TRIM_REG_LDO_SUPPLY_VBAT_TRIM_Pos (4UL) /*!< LDO_SUPPLY_VBAT_TRIM (Bit 4) */ +#define CRG_TOP_PMU_TRIM_REG_LDO_SUPPLY_VBAT_TRIM_Msk (0xf0UL) /*!< LDO_SUPPLY_VBAT_TRIM (Bitfield-Mask: 0x0f) */ +#define CRG_TOP_PMU_TRIM_REG_LDO_SUPPLY_VBUS_TRIM_Pos (0UL) /*!< LDO_SUPPLY_VBUS_TRIM (Bit 0) */ +#define CRG_TOP_PMU_TRIM_REG_LDO_SUPPLY_VBUS_TRIM_Msk (0xfUL) /*!< LDO_SUPPLY_VBUS_TRIM (Bitfield-Mask: 0x0f) */ +/* ====================================================== POR_PIN_REG ====================================================== */ +#define CRG_TOP_POR_PIN_REG_POR_PIN_POLARITY_Pos (7UL) /*!< POR_PIN_POLARITY (Bit 7) */ +#define CRG_TOP_POR_PIN_REG_POR_PIN_POLARITY_Msk (0x80UL) /*!< POR_PIN_POLARITY (Bitfield-Mask: 0x01) */ +#define CRG_TOP_POR_PIN_REG_POR_PIN_SELECT_Pos (0UL) /*!< POR_PIN_SELECT (Bit 0) */ +#define CRG_TOP_POR_PIN_REG_POR_PIN_SELECT_Msk (0x3fUL) /*!< POR_PIN_SELECT (Bitfield-Mask: 0x3f) */ +/* ===================================================== POR_TIMER_REG ===================================================== */ +#define CRG_TOP_POR_TIMER_REG_POR_TIME_Pos (0UL) /*!< POR_TIME (Bit 0) */ +#define CRG_TOP_POR_TIMER_REG_POR_TIME_Msk (0x7fUL) /*!< POR_TIME (Bitfield-Mask: 0x7f) */ +/* =================================================== POR_VBAT_CTRL_REG =================================================== */ +#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_MASK_N_Pos (13UL) /*!< POR_VBAT_MASK_N (Bit 13) */ +#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_MASK_N_Msk (0x2000UL) /*!< POR_VBAT_MASK_N (Bitfield-Mask: 0x01) */ +#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_ENABLE_Pos (12UL) /*!< POR_VBAT_ENABLE (Bit 12) */ +#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_ENABLE_Msk (0x1000UL) /*!< POR_VBAT_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_HYST_LOW_Pos (8UL) /*!< POR_VBAT_HYST_LOW (Bit 8) */ +#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_HYST_LOW_Msk (0xf00UL) /*!< POR_VBAT_HYST_LOW (Bitfield-Mask: 0x0f) */ +#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_HIGH_Pos (4UL) /*!< POR_VBAT_THRES_HIGH (Bit 4) */ +#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_HIGH_Msk (0xf0UL) /*!< POR_VBAT_THRES_HIGH (Bitfield-Mask: 0x0f) */ +#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_LOW_Pos (0UL) /*!< POR_VBAT_THRES_LOW (Bit 0) */ +#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_LOW_Msk (0xfUL) /*!< POR_VBAT_THRES_LOW (Bitfield-Mask: 0x0f) */ +/* ==================================================== POWER_CTRL_REG ===================================================== */ +#define CRG_TOP_POWER_CTRL_REG_VDD_SLEEP_LEVEL_Pos (29UL) /*!< VDD_SLEEP_LEVEL (Bit 29) */ +#define CRG_TOP_POWER_CTRL_REG_VDD_SLEEP_LEVEL_Msk (0xe0000000UL) /*!< VDD_SLEEP_LEVEL (Bitfield-Mask: 0x07) */ +#define CRG_TOP_POWER_CTRL_REG_VDD_CLAMP_LEVEL_Pos (25UL) /*!< VDD_CLAMP_LEVEL (Bit 25) */ +#define CRG_TOP_POWER_CTRL_REG_VDD_CLAMP_LEVEL_Msk (0x1e000000UL) /*!< VDD_CLAMP_LEVEL (Bitfield-Mask: 0x0f) */ +#define CRG_TOP_POWER_CTRL_REG_CLAMP_3V0_VBAT_ENABLE_Pos (24UL) /*!< CLAMP_3V0_VBAT_ENABLE (Bit 24) */ +#define CRG_TOP_POWER_CTRL_REG_CLAMP_3V0_VBAT_ENABLE_Msk (0x1000000UL) /*!< CLAMP_3V0_VBAT_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_POWER_CTRL_REG_V18_LEVEL_Pos (23UL) /*!< V18_LEVEL (Bit 23) */ +#define CRG_TOP_POWER_CTRL_REG_V18_LEVEL_Msk (0x800000UL) /*!< V18_LEVEL (Bitfield-Mask: 0x01) */ +#define CRG_TOP_POWER_CTRL_REG_V14_LEVEL_Pos (20UL) /*!< V14_LEVEL (Bit 20) */ +#define CRG_TOP_POWER_CTRL_REG_V14_LEVEL_Msk (0x700000UL) /*!< V14_LEVEL (Bitfield-Mask: 0x07) */ +#define CRG_TOP_POWER_CTRL_REG_V30_LEVEL_Pos (18UL) /*!< V30_LEVEL (Bit 18) */ +#define CRG_TOP_POWER_CTRL_REG_V30_LEVEL_Msk (0xc0000UL) /*!< V30_LEVEL (Bitfield-Mask: 0x03) */ +#define CRG_TOP_POWER_CTRL_REG_VDD_LEVEL_Pos (16UL) /*!< VDD_LEVEL (Bit 16) */ +#define CRG_TOP_POWER_CTRL_REG_VDD_LEVEL_Msk (0x30000UL) /*!< VDD_LEVEL (Bitfield-Mask: 0x03) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_3V0_REF_Pos (15UL) /*!< LDO_3V0_REF (Bit 15) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_3V0_REF_Msk (0x8000UL) /*!< LDO_3V0_REF (Bitfield-Mask: 0x01) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_SLEEP_Pos (14UL) /*!< LDO_CORE_RET_ENABLE_SLEEP (Bit 14) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_SLEEP_Msk (0x4000UL) /*!< LDO_CORE_RET_ENABLE_SLEEP (Bitfield-Mask: 0x01) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_ACTIVE_Pos (13UL) /*!< LDO_CORE_RET_ENABLE_ACTIVE (Bit 13) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_ACTIVE_Msk (0x2000UL) /*!< LDO_CORE_RET_ENABLE_ACTIVE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_CORE_ENABLE_Pos (12UL) /*!< LDO_CORE_ENABLE (Bit 12) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_CORE_ENABLE_Msk (0x1000UL) /*!< LDO_CORE_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_3V0_RET_ENABLE_SLEEP_Pos (11UL) /*!< LDO_3V0_RET_ENABLE_SLEEP (Bit 11) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_3V0_RET_ENABLE_SLEEP_Msk (0x800UL) /*!< LDO_3V0_RET_ENABLE_SLEEP (Bitfield-Mask: 0x01) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_3V0_RET_ENABLE_ACTIVE_Pos (10UL) /*!< LDO_3V0_RET_ENABLE_ACTIVE (Bit 10) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_3V0_RET_ENABLE_ACTIVE_Msk (0x400UL) /*!< LDO_3V0_RET_ENABLE_ACTIVE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_3V0_MODE_Pos (8UL) /*!< LDO_3V0_MODE (Bit 8) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_3V0_MODE_Msk (0x300UL) /*!< LDO_3V0_MODE (Bitfield-Mask: 0x03) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_RADIO_ENABLE_Pos (7UL) /*!< LDO_RADIO_ENABLE (Bit 7) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_RADIO_ENABLE_Msk (0x80UL) /*!< LDO_RADIO_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_1V8_RET_ENABLE_SLEEP_Pos (6UL) /*!< LDO_1V8_RET_ENABLE_SLEEP (Bit 6) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_1V8_RET_ENABLE_SLEEP_Msk (0x40UL) /*!< LDO_1V8_RET_ENABLE_SLEEP (Bitfield-Mask: 0x01) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_1V8_RET_ENABLE_ACTIVE_Pos (5UL) /*!< LDO_1V8_RET_ENABLE_ACTIVE (Bit 5) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_1V8_RET_ENABLE_ACTIVE_Msk (0x20UL) /*!< LDO_1V8_RET_ENABLE_ACTIVE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_1V8_ENABLE_Pos (4UL) /*!< LDO_1V8_ENABLE (Bit 4) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_1V8_ENABLE_Msk (0x10UL) /*!< LDO_1V8_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_POWER_CTRL_REG_SW_1V8F_ENABLE_FORCE_Pos (3UL) /*!< SW_1V8F_ENABLE_FORCE (Bit 3) */ +#define CRG_TOP_POWER_CTRL_REG_SW_1V8F_ENABLE_FORCE_Msk (0x8UL) /*!< SW_1V8F_ENABLE_FORCE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_1V8P_RET_ENABLE_SLEEP_Pos (2UL) /*!< LDO_1V8P_RET_ENABLE_SLEEP (Bit 2) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_1V8P_RET_ENABLE_SLEEP_Msk (0x4UL) /*!< LDO_1V8P_RET_ENABLE_SLEEP (Bitfield-Mask: 0x01) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_1V8P_RET_ENABLE_ACTIVE_Pos (1UL) /*!< LDO_1V8P_RET_ENABLE_ACTIVE (Bit 1) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_1V8P_RET_ENABLE_ACTIVE_Msk (0x2UL) /*!< LDO_1V8P_RET_ENABLE_ACTIVE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_1V8P_ENABLE_Pos (0UL) /*!< LDO_1V8P_ENABLE (Bit 0) */ +#define CRG_TOP_POWER_CTRL_REG_LDO_1V8P_ENABLE_Msk (0x1UL) /*!< LDO_1V8P_ENABLE (Bitfield-Mask: 0x01) */ +/* =================================================== RAM_PWR_CTRL_REG ==================================================== */ +#define CRG_TOP_RAM_PWR_CTRL_REG_RAM8_PWR_CTRL_Pos (14UL) /*!< RAM8_PWR_CTRL (Bit 14) */ +#define CRG_TOP_RAM_PWR_CTRL_REG_RAM8_PWR_CTRL_Msk (0xc000UL) /*!< RAM8_PWR_CTRL (Bitfield-Mask: 0x03) */ +#define CRG_TOP_RAM_PWR_CTRL_REG_RAM7_PWR_CTRL_Pos (12UL) /*!< RAM7_PWR_CTRL (Bit 12) */ +#define CRG_TOP_RAM_PWR_CTRL_REG_RAM7_PWR_CTRL_Msk (0x3000UL) /*!< RAM7_PWR_CTRL (Bitfield-Mask: 0x03) */ +#define CRG_TOP_RAM_PWR_CTRL_REG_RAM6_PWR_CTRL_Pos (10UL) /*!< RAM6_PWR_CTRL (Bit 10) */ +#define CRG_TOP_RAM_PWR_CTRL_REG_RAM6_PWR_CTRL_Msk (0xc00UL) /*!< RAM6_PWR_CTRL (Bitfield-Mask: 0x03) */ +#define CRG_TOP_RAM_PWR_CTRL_REG_RAM5_PWR_CTRL_Pos (8UL) /*!< RAM5_PWR_CTRL (Bit 8) */ +#define CRG_TOP_RAM_PWR_CTRL_REG_RAM5_PWR_CTRL_Msk (0x300UL) /*!< RAM5_PWR_CTRL (Bitfield-Mask: 0x03) */ +#define CRG_TOP_RAM_PWR_CTRL_REG_RAM4_PWR_CTRL_Pos (6UL) /*!< RAM4_PWR_CTRL (Bit 6) */ +#define CRG_TOP_RAM_PWR_CTRL_REG_RAM4_PWR_CTRL_Msk (0xc0UL) /*!< RAM4_PWR_CTRL (Bitfield-Mask: 0x03) */ +#define CRG_TOP_RAM_PWR_CTRL_REG_RAM3_PWR_CTRL_Pos (4UL) /*!< RAM3_PWR_CTRL (Bit 4) */ +#define CRG_TOP_RAM_PWR_CTRL_REG_RAM3_PWR_CTRL_Msk (0x30UL) /*!< RAM3_PWR_CTRL (Bitfield-Mask: 0x03) */ +#define CRG_TOP_RAM_PWR_CTRL_REG_RAM2_PWR_CTRL_Pos (2UL) /*!< RAM2_PWR_CTRL (Bit 2) */ +#define CRG_TOP_RAM_PWR_CTRL_REG_RAM2_PWR_CTRL_Msk (0xcUL) /*!< RAM2_PWR_CTRL (Bitfield-Mask: 0x03) */ +#define CRG_TOP_RAM_PWR_CTRL_REG_RAM1_PWR_CTRL_Pos (0UL) /*!< RAM1_PWR_CTRL (Bit 0) */ +#define CRG_TOP_RAM_PWR_CTRL_REG_RAM1_PWR_CTRL_Msk (0x3UL) /*!< RAM1_PWR_CTRL (Bitfield-Mask: 0x03) */ +/* ==================================================== RESET_STAT_REG ===================================================== */ +#define CRG_TOP_RESET_STAT_REG_CMAC_WDOGRESET_STAT_Pos (5UL) /*!< CMAC_WDOGRESET_STAT (Bit 5) */ +#define CRG_TOP_RESET_STAT_REG_CMAC_WDOGRESET_STAT_Msk (0x20UL) /*!< CMAC_WDOGRESET_STAT (Bitfield-Mask: 0x01) */ +#define CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Pos (4UL) /*!< SWD_HWRESET_STAT (Bit 4) */ +#define CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Msk (0x10UL) /*!< SWD_HWRESET_STAT (Bitfield-Mask: 0x01) */ +#define CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Pos (3UL) /*!< WDOGRESET_STAT (Bit 3) */ +#define CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Msk (0x8UL) /*!< WDOGRESET_STAT (Bitfield-Mask: 0x01) */ +#define CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Pos (2UL) /*!< SWRESET_STAT (Bit 2) */ +#define CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Msk (0x4UL) /*!< SWRESET_STAT (Bitfield-Mask: 0x01) */ +#define CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Pos (1UL) /*!< HWRESET_STAT (Bit 1) */ +#define CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Msk (0x2UL) /*!< HWRESET_STAT (Bitfield-Mask: 0x01) */ +#define CRG_TOP_RESET_STAT_REG_PORESET_STAT_Pos (0UL) /*!< PORESET_STAT (Bit 0) */ +#define CRG_TOP_RESET_STAT_REG_PORESET_STAT_Msk (0x1UL) /*!< PORESET_STAT (Bitfield-Mask: 0x01) */ +/* ==================================================== SECURE_BOOT_REG ==================================================== */ +#define CRG_TOP_SECURE_BOOT_REG_PROT_QSPI_KEY_READ_Pos (7UL) /*!< PROT_QSPI_KEY_READ (Bit 7) */ +#define CRG_TOP_SECURE_BOOT_REG_PROT_QSPI_KEY_READ_Msk (0x80UL) /*!< PROT_QSPI_KEY_READ (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SECURE_BOOT_REG_PROT_QSPI_KEY_WRITE_Pos (6UL) /*!< PROT_QSPI_KEY_WRITE (Bit 6) */ +#define CRG_TOP_SECURE_BOOT_REG_PROT_QSPI_KEY_WRITE_Msk (0x40UL) /*!< PROT_QSPI_KEY_WRITE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SECURE_BOOT_REG_PROT_AES_KEY_READ_Pos (5UL) /*!< PROT_AES_KEY_READ (Bit 5) */ +#define CRG_TOP_SECURE_BOOT_REG_PROT_AES_KEY_READ_Msk (0x20UL) /*!< PROT_AES_KEY_READ (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SECURE_BOOT_REG_PROT_AES_KEY_WRITE_Pos (4UL) /*!< PROT_AES_KEY_WRITE (Bit 4) */ +#define CRG_TOP_SECURE_BOOT_REG_PROT_AES_KEY_WRITE_Msk (0x10UL) /*!< PROT_AES_KEY_WRITE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SECURE_BOOT_REG_PROT_SIG_KEY_WRITE_Pos (3UL) /*!< PROT_SIG_KEY_WRITE (Bit 3) */ +#define CRG_TOP_SECURE_BOOT_REG_PROT_SIG_KEY_WRITE_Msk (0x8UL) /*!< PROT_SIG_KEY_WRITE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SECURE_BOOT_REG_FORCE_CMAC_DEBUGGER_OFF_Pos (2UL) /*!< FORCE_CMAC_DEBUGGER_OFF (Bit 2) */ +#define CRG_TOP_SECURE_BOOT_REG_FORCE_CMAC_DEBUGGER_OFF_Msk (0x4UL) /*!< FORCE_CMAC_DEBUGGER_OFF (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SECURE_BOOT_REG_FORCE_DEBUGGER_OFF_Pos (1UL) /*!< FORCE_DEBUGGER_OFF (Bit 1) */ +#define CRG_TOP_SECURE_BOOT_REG_FORCE_DEBUGGER_OFF_Msk (0x2UL) /*!< FORCE_DEBUGGER_OFF (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SECURE_BOOT_REG_SECURE_BOOT_Pos (0UL) /*!< SECURE_BOOT (Bit 0) */ +#define CRG_TOP_SECURE_BOOT_REG_SECURE_BOOT_Msk (0x1UL) /*!< SECURE_BOOT (Bitfield-Mask: 0x01) */ +/* ===================================================== SYS_CTRL_REG ====================================================== */ +#define CRG_TOP_SYS_CTRL_REG_SW_RESET_Pos (15UL) /*!< SW_RESET (Bit 15) */ +#define CRG_TOP_SYS_CTRL_REG_SW_RESET_Msk (0x8000UL) /*!< SW_RESET (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Pos (10UL) /*!< CACHERAM_MUX (Bit 10) */ +#define CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Msk (0x400UL) /*!< CACHERAM_MUX (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SYS_CTRL_REG_TIMEOUT_DISABLE_Pos (9UL) /*!< TIMEOUT_DISABLE (Bit 9) */ +#define CRG_TOP_SYS_CTRL_REG_TIMEOUT_DISABLE_Msk (0x200UL) /*!< TIMEOUT_DISABLE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Pos (7UL) /*!< DEBUGGER_ENABLE (Bit 7) */ +#define CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Msk (0x80UL) /*!< DEBUGGER_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SYS_CTRL_REG_QSPI_INIT_Pos (4UL) /*!< QSPI_INIT (Bit 4) */ +#define CRG_TOP_SYS_CTRL_REG_QSPI_INIT_Msk (0x10UL) /*!< QSPI_INIT (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SYS_CTRL_REG_REMAP_INTVECT_Pos (3UL) /*!< REMAP_INTVECT (Bit 3) */ +#define CRG_TOP_SYS_CTRL_REG_REMAP_INTVECT_Msk (0x8UL) /*!< REMAP_INTVECT (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Pos (0UL) /*!< REMAP_ADR0 (Bit 0) */ +#define CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Msk (0x7UL) /*!< REMAP_ADR0 (Bitfield-Mask: 0x07) */ +/* ===================================================== SYS_STAT_REG ====================================================== */ +#define CRG_TOP_SYS_STAT_REG_POWER_IS_UP_Pos (13UL) /*!< POWER_IS_UP (Bit 13) */ +#define CRG_TOP_SYS_STAT_REG_POWER_IS_UP_Msk (0x2000UL) /*!< POWER_IS_UP (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Pos (12UL) /*!< DBG_IS_ACTIVE (Bit 12) */ +#define CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Msk (0x1000UL) /*!< DBG_IS_ACTIVE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SYS_STAT_REG_COM_IS_UP_Pos (11UL) /*!< COM_IS_UP (Bit 11) */ +#define CRG_TOP_SYS_STAT_REG_COM_IS_UP_Msk (0x800UL) /*!< COM_IS_UP (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SYS_STAT_REG_COM_IS_DOWN_Pos (10UL) /*!< COM_IS_DOWN (Bit 10) */ +#define CRG_TOP_SYS_STAT_REG_COM_IS_DOWN_Msk (0x400UL) /*!< COM_IS_DOWN (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SYS_STAT_REG_TIM_IS_UP_Pos (9UL) /*!< TIM_IS_UP (Bit 9) */ +#define CRG_TOP_SYS_STAT_REG_TIM_IS_UP_Msk (0x200UL) /*!< TIM_IS_UP (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SYS_STAT_REG_TIM_IS_DOWN_Pos (8UL) /*!< TIM_IS_DOWN (Bit 8) */ +#define CRG_TOP_SYS_STAT_REG_TIM_IS_DOWN_Msk (0x100UL) /*!< TIM_IS_DOWN (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SYS_STAT_REG_MEM_IS_UP_Pos (7UL) /*!< MEM_IS_UP (Bit 7) */ +#define CRG_TOP_SYS_STAT_REG_MEM_IS_UP_Msk (0x80UL) /*!< MEM_IS_UP (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SYS_STAT_REG_MEM_IS_DOWN_Pos (6UL) /*!< MEM_IS_DOWN (Bit 6) */ +#define CRG_TOP_SYS_STAT_REG_MEM_IS_DOWN_Msk (0x40UL) /*!< MEM_IS_DOWN (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SYS_STAT_REG_SYS_IS_UP_Pos (5UL) /*!< SYS_IS_UP (Bit 5) */ +#define CRG_TOP_SYS_STAT_REG_SYS_IS_UP_Msk (0x20UL) /*!< SYS_IS_UP (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SYS_STAT_REG_SYS_IS_DOWN_Pos (4UL) /*!< SYS_IS_DOWN (Bit 4) */ +#define CRG_TOP_SYS_STAT_REG_SYS_IS_DOWN_Msk (0x10UL) /*!< SYS_IS_DOWN (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SYS_STAT_REG_PER_IS_UP_Pos (3UL) /*!< PER_IS_UP (Bit 3) */ +#define CRG_TOP_SYS_STAT_REG_PER_IS_UP_Msk (0x8UL) /*!< PER_IS_UP (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SYS_STAT_REG_PER_IS_DOWN_Pos (2UL) /*!< PER_IS_DOWN (Bit 2) */ +#define CRG_TOP_SYS_STAT_REG_PER_IS_DOWN_Msk (0x4UL) /*!< PER_IS_DOWN (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SYS_STAT_REG_RAD_IS_UP_Pos (1UL) /*!< RAD_IS_UP (Bit 1) */ +#define CRG_TOP_SYS_STAT_REG_RAD_IS_UP_Msk (0x2UL) /*!< RAD_IS_UP (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SYS_STAT_REG_RAD_IS_DOWN_Pos (0UL) /*!< RAD_IS_DOWN (Bit 0) */ +#define CRG_TOP_SYS_STAT_REG_RAD_IS_DOWN_Msk (0x1UL) /*!< RAD_IS_DOWN (Bitfield-Mask: 0x01) */ +/* ================================================== VBUS_IRQ_CLEAR_REG =================================================== */ +#define CRG_TOP_VBUS_IRQ_CLEAR_REG_VBUS_IRQ_CLEAR_Pos (0UL) /*!< VBUS_IRQ_CLEAR (Bit 0) */ +#define CRG_TOP_VBUS_IRQ_CLEAR_REG_VBUS_IRQ_CLEAR_Msk (0xffffUL) /*!< VBUS_IRQ_CLEAR (Bitfield-Mask: 0xffff) */ +/* =================================================== VBUS_IRQ_MASK_REG =================================================== */ +#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_RISE_Pos (1UL) /*!< VBUS_IRQ_EN_RISE (Bit 1) */ +#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_RISE_Msk (0x2UL) /*!< VBUS_IRQ_EN_RISE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_FALL_Pos (0UL) /*!< VBUS_IRQ_EN_FALL (Bit 0) */ +#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_FALL_Msk (0x1UL) /*!< VBUS_IRQ_EN_FALL (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ CRG_XTAL ================ */ +/* =========================================================================================================================== */ + +/* =================================================== CLK_FREQ_TRIM_REG =================================================== */ +#define CRG_XTAL_CLK_FREQ_TRIM_REG_XTAL32M_START_Pos (20UL) /*!< XTAL32M_START (Bit 20) */ +#define CRG_XTAL_CLK_FREQ_TRIM_REG_XTAL32M_START_Msk (0x3ff00000UL) /*!< XTAL32M_START (Bitfield-Mask: 0x3ff) */ +#define CRG_XTAL_CLK_FREQ_TRIM_REG_XTAL32M_RAMP_Pos (10UL) /*!< XTAL32M_RAMP (Bit 10) */ +#define CRG_XTAL_CLK_FREQ_TRIM_REG_XTAL32M_RAMP_Msk (0xffc00UL) /*!< XTAL32M_RAMP (Bitfield-Mask: 0x3ff) */ +#define CRG_XTAL_CLK_FREQ_TRIM_REG_XTAL32M_TRIM_Pos (0UL) /*!< XTAL32M_TRIM (Bit 0) */ +#define CRG_XTAL_CLK_FREQ_TRIM_REG_XTAL32M_TRIM_Msk (0x3ffUL) /*!< XTAL32M_TRIM (Bitfield-Mask: 0x3ff) */ +/* =================================================== PLL_SYS_CTRL1_REG =================================================== */ +#define CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_SEL_MIN_CUR_INT_Pos (14UL) /*!< PLL_SEL_MIN_CUR_INT (Bit 14) */ +#define CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_SEL_MIN_CUR_INT_Msk (0x4000UL) /*!< PLL_SEL_MIN_CUR_INT (Bitfield-Mask: 0x01) */ +#define CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_PRE_DIV_Pos (11UL) /*!< PLL_PRE_DIV (Bit 11) */ +#define CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_PRE_DIV_Msk (0x800UL) /*!< PLL_PRE_DIV (Bitfield-Mask: 0x01) */ +#define CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_N_DIV_Pos (4UL) /*!< PLL_N_DIV (Bit 4) */ +#define CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_N_DIV_Msk (0x7f0UL) /*!< PLL_N_DIV (Bitfield-Mask: 0x7f) */ +#define CRG_XTAL_PLL_SYS_CTRL1_REG_LDO_PLL_VREF_HOLD_Pos (3UL) /*!< LDO_PLL_VREF_HOLD (Bit 3) */ +#define CRG_XTAL_PLL_SYS_CTRL1_REG_LDO_PLL_VREF_HOLD_Msk (0x8UL) /*!< LDO_PLL_VREF_HOLD (Bitfield-Mask: 0x01) */ +#define CRG_XTAL_PLL_SYS_CTRL1_REG_LDO_PLL_ENABLE_Pos (2UL) /*!< LDO_PLL_ENABLE (Bit 2) */ +#define CRG_XTAL_PLL_SYS_CTRL1_REG_LDO_PLL_ENABLE_Msk (0x4UL) /*!< LDO_PLL_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_EN_Pos (1UL) /*!< PLL_EN (Bit 1) */ +#define CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_EN_Msk (0x2UL) /*!< PLL_EN (Bitfield-Mask: 0x01) */ +/* =================================================== PLL_SYS_CTRL2_REG =================================================== */ +#define CRG_XTAL_PLL_SYS_CTRL2_REG_PLL_RECALIB_Pos (15UL) /*!< PLL_RECALIB (Bit 15) */ +#define CRG_XTAL_PLL_SYS_CTRL2_REG_PLL_RECALIB_Msk (0x8000UL) /*!< PLL_RECALIB (Bitfield-Mask: 0x01) */ +/* =================================================== PLL_SYS_CTRL3_REG =================================================== */ +#define CRG_XTAL_PLL_SYS_CTRL3_REG_PLL_TEST_VCTR_Pos (7UL) /*!< PLL_TEST_VCTR (Bit 7) */ +#define CRG_XTAL_PLL_SYS_CTRL3_REG_PLL_TEST_VCTR_Msk (0x80UL) /*!< PLL_TEST_VCTR (Bitfield-Mask: 0x01) */ +#define CRG_XTAL_PLL_SYS_CTRL3_REG_PLL_MIN_CURRENT_Pos (1UL) /*!< PLL_MIN_CURRENT (Bit 1) */ +#define CRG_XTAL_PLL_SYS_CTRL3_REG_PLL_MIN_CURRENT_Msk (0x7eUL) /*!< PLL_MIN_CURRENT (Bitfield-Mask: 0x3f) */ +/* ================================================== PLL_SYS_STATUS_REG =================================================== */ +#define CRG_XTAL_PLL_SYS_STATUS_REG_LDO_PLL_OK_Pos (15UL) /*!< LDO_PLL_OK (Bit 15) */ +#define CRG_XTAL_PLL_SYS_STATUS_REG_LDO_PLL_OK_Msk (0x8000UL) /*!< LDO_PLL_OK (Bitfield-Mask: 0x01) */ +#define CRG_XTAL_PLL_SYS_STATUS_REG_PLL_CALIBRATION_END_Pos (11UL) /*!< PLL_CALIBRATION_END (Bit 11) */ +#define CRG_XTAL_PLL_SYS_STATUS_REG_PLL_CALIBRATION_END_Msk (0x800UL) /*!< PLL_CALIBRATION_END (Bitfield-Mask: 0x01) */ +#define CRG_XTAL_PLL_SYS_STATUS_REG_PLL_BEST_MIN_CUR_Pos (5UL) /*!< PLL_BEST_MIN_CUR (Bit 5) */ +#define CRG_XTAL_PLL_SYS_STATUS_REG_PLL_BEST_MIN_CUR_Msk (0x7e0UL) /*!< PLL_BEST_MIN_CUR (Bitfield-Mask: 0x3f) */ +#define CRG_XTAL_PLL_SYS_STATUS_REG_PLL_LOCK_FINE_Pos (0UL) /*!< PLL_LOCK_FINE (Bit 0) */ +#define CRG_XTAL_PLL_SYS_STATUS_REG_PLL_LOCK_FINE_Msk (0x1UL) /*!< PLL_LOCK_FINE (Bitfield-Mask: 0x01) */ +/* ===================================================== TRIM_CTRL_REG ===================================================== */ +#define CRG_XTAL_TRIM_CTRL_REG_XTAL_SETTLE_N_Pos (8UL) /*!< XTAL_SETTLE_N (Bit 8) */ +#define CRG_XTAL_TRIM_CTRL_REG_XTAL_SETTLE_N_Msk (0x3f00UL) /*!< XTAL_SETTLE_N (Bitfield-Mask: 0x3f) */ +#define CRG_XTAL_TRIM_CTRL_REG_XTAL_TRIM_SELECT_Pos (6UL) /*!< XTAL_TRIM_SELECT (Bit 6) */ +#define CRG_XTAL_TRIM_CTRL_REG_XTAL_TRIM_SELECT_Msk (0xc0UL) /*!< XTAL_TRIM_SELECT (Bitfield-Mask: 0x03) */ +#define CRG_XTAL_TRIM_CTRL_REG_XTAL_COUNT_N_Pos (0UL) /*!< XTAL_COUNT_N (Bit 0) */ +#define CRG_XTAL_TRIM_CTRL_REG_XTAL_COUNT_N_Msk (0x3fUL) /*!< XTAL_COUNT_N (Bitfield-Mask: 0x3f) */ +/* =================================================== XTAL32M_CTRL0_REG =================================================== */ +#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_DXTAL_SYSPLL_ENABLE_Pos (30UL) /*!< XTAL32M_DXTAL_SYSPLL_ENABLE (Bit 30) */ +#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_DXTAL_SYSPLL_ENABLE_Msk (0x40000000UL) /*!< XTAL32M_DXTAL_SYSPLL_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_CORE_CUR_SET_Pos (15UL) /*!< XTAL32M_CORE_CUR_SET (Bit 15) */ +#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_CORE_CUR_SET_Msk (0x38000UL) /*!< XTAL32M_CORE_CUR_SET (Bitfield-Mask: 0x07) */ +#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_RCOSC_CALIBRATE_Pos (3UL) /*!< XTAL32M_RCOSC_CALIBRATE (Bit 3) */ +#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_RCOSC_CALIBRATE_Msk (0x8UL) /*!< XTAL32M_RCOSC_CALIBRATE (Bitfield-Mask: 0x01) */ +#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_RCOSC_XTAL_DRIVE_Pos (1UL) /*!< XTAL32M_RCOSC_XTAL_DRIVE (Bit 1) */ +#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_RCOSC_XTAL_DRIVE_Msk (0x2UL) /*!< XTAL32M_RCOSC_XTAL_DRIVE (Bitfield-Mask: 0x01) */ +#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_CXCOMP_ENABLE_Pos (0UL) /*!< XTAL32M_CXCOMP_ENABLE (Bit 0) */ +#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_CXCOMP_ENABLE_Msk (0x1UL) /*!< XTAL32M_CXCOMP_ENABLE (Bitfield-Mask: 0x01) */ +/* =================================================== XTAL32M_CTRL1_REG =================================================== */ +#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_STARTUP_TDISCHARGE_Pos (28UL) /*!< XTAL32M_STARTUP_TDISCHARGE (Bit 28) */ +#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_STARTUP_TDISCHARGE_Msk (0x70000000UL) /*!< XTAL32M_STARTUP_TDISCHARGE (Bitfield-Mask: 0x07) */ +#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_STARTUP_TSETTLE_Pos (24UL) /*!< XTAL32M_STARTUP_TSETTLE (Bit 24) */ +#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_STARTUP_TSETTLE_Msk (0x7000000UL) /*!< XTAL32M_STARTUP_TSETTLE (Bitfield-Mask: 0x07) */ +#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_XTAL_ENABLE_Pos (23UL) /*!< XTAL32M_XTAL_ENABLE (Bit 23) */ +#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_XTAL_ENABLE_Msk (0x800000UL) /*!< XTAL32M_XTAL_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_STARTUP_TDRIVE_LSB_Pos (13UL) /*!< XTAL32M_STARTUP_TDRIVE_LSB (Bit 13) */ +#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_STARTUP_TDRIVE_LSB_Msk (0x7fe000UL) /*!< XTAL32M_STARTUP_TDRIVE_LSB (Bitfield-Mask: 0x3ff) */ +#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_DRIVE_CYCLES_Pos (8UL) /*!< XTAL32M_DRIVE_CYCLES (Bit 8) */ +#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_DRIVE_CYCLES_Msk (0x1f00UL) /*!< XTAL32M_DRIVE_CYCLES (Bitfield-Mask: 0x1f) */ +#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_STARTUP_TDRIVE_Pos (5UL) /*!< XTAL32M_STARTUP_TDRIVE (Bit 5) */ +#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_STARTUP_TDRIVE_Msk (0xe0UL) /*!< XTAL32M_STARTUP_TDRIVE (Bitfield-Mask: 0x07) */ +#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_RCOSC_SYNC_DELAY_TRIM_Pos (0UL) /*!< XTAL32M_RCOSC_SYNC_DELAY_TRIM (Bit 0) */ +#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_RCOSC_SYNC_DELAY_TRIM_Msk (0x1fUL) /*!< XTAL32M_RCOSC_SYNC_DELAY_TRIM (Bitfield-Mask: 0x1f) */ +/* =================================================== XTAL32M_CTRL2_REG =================================================== */ +#define CRG_XTAL_XTAL32M_CTRL2_REG_XTAL32M_RCOSC_TRIM_SNS_Pos (14UL) /*!< XTAL32M_RCOSC_TRIM_SNS (Bit 14) */ +#define CRG_XTAL_XTAL32M_CTRL2_REG_XTAL32M_RCOSC_TRIM_SNS_Msk (0x3fc000UL) /*!< XTAL32M_RCOSC_TRIM_SNS (Bitfield-Mask: 0xff) */ +#define CRG_XTAL_XTAL32M_CTRL2_REG_XTAL32M_CXCOMP_PHI_TRIM_Pos (12UL) /*!< XTAL32M_CXCOMP_PHI_TRIM (Bit 12) */ +#define CRG_XTAL_XTAL32M_CTRL2_REG_XTAL32M_CXCOMP_PHI_TRIM_Msk (0x3000UL) /*!< XTAL32M_CXCOMP_PHI_TRIM (Bitfield-Mask: 0x03) */ +#define CRG_XTAL_XTAL32M_CTRL2_REG_XTAL32M_CXCOMP_TRIM_CAP_Pos (3UL) /*!< XTAL32M_CXCOMP_TRIM_CAP (Bit 3) */ +#define CRG_XTAL_XTAL32M_CTRL2_REG_XTAL32M_CXCOMP_TRIM_CAP_Msk (0xff8UL) /*!< XTAL32M_CXCOMP_TRIM_CAP (Bitfield-Mask: 0x1ff) */ +/* =================================================== XTAL32M_CTRL3_REG =================================================== */ +#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_RCOSC_TRIM_STROBE_Pos (30UL) /*!< XTAL32M_RCOSC_TRIM_STROBE (Bit 30) */ +#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_RCOSC_TRIM_STROBE_Msk (0x40000000UL) /*!< XTAL32M_RCOSC_TRIM_STROBE (Bitfield-Mask: 0x01) */ +#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_FREQ_DET_START_Pos (22UL) /*!< XTAL32M_FREQ_DET_START (Bit 22) */ +#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_FREQ_DET_START_Msk (0x400000UL) /*!< XTAL32M_FREQ_DET_START (Bitfield-Mask: 0x01) */ +#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_SW_CTRL_MODE_Pos (18UL) /*!< XTAL32M_SW_CTRL_MODE (Bit 18) */ +#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_SW_CTRL_MODE_Msk (0x40000UL) /*!< XTAL32M_SW_CTRL_MODE (Bitfield-Mask: 0x01) */ +#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_RCOSC_BAND_SELECT_Pos (14UL) /*!< XTAL32M_RCOSC_BAND_SELECT (Bit 14) */ +#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_RCOSC_BAND_SELECT_Msk (0x3c000UL) /*!< XTAL32M_RCOSC_BAND_SELECT (Bitfield-Mask: 0x0f) */ +#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_RCOSC_TRIM_Pos (4UL) /*!< XTAL32M_RCOSC_TRIM (Bit 4) */ +#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_RCOSC_TRIM_Msk (0x3ff0UL) /*!< XTAL32M_RCOSC_TRIM (Bitfield-Mask: 0x3ff) */ +/* =================================================== XTAL32M_CTRL4_REG =================================================== */ +/* =================================================== XTAL32M_STAT0_REG =================================================== */ +#define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_RCOSC_BAND_SELECT_STAT_Pos (28UL) /*!< XTAL32M_RCOSC_BAND_SELECT_STAT (Bit 28) */ +#define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_RCOSC_BAND_SELECT_STAT_Msk (0xf0000000UL) /*!< XTAL32M_RCOSC_BAND_SELECT_STAT (Bitfield-Mask: 0x0f) */ +#define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_RCOSC_CALIBRATION_DONE_Pos (15UL) /*!< XTAL32M_RCOSC_CALIBRATION_DONE (Bit 15) */ +#define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_RCOSC_CALIBRATION_DONE_Msk (0x8000UL) /*!< XTAL32M_RCOSC_CALIBRATION_DONE (Bitfield-Mask: 0x01) */ +/* =================================================== XTAL32M_STAT1_REG =================================================== */ +#define CRG_XTAL_XTAL32M_STAT1_REG_XTAL32M_CAL_STATE_Pos (4UL) /*!< XTAL32M_CAL_STATE (Bit 4) */ +#define CRG_XTAL_XTAL32M_STAT1_REG_XTAL32M_CAL_STATE_Msk (0xf0UL) /*!< XTAL32M_CAL_STATE (Bitfield-Mask: 0x0f) */ +#define CRG_XTAL_XTAL32M_STAT1_REG_XTAL32M_STATE_Pos (0UL) /*!< XTAL32M_STATE (Bit 0) */ +#define CRG_XTAL_XTAL32M_STAT1_REG_XTAL32M_STATE_Msk (0xfUL) /*!< XTAL32M_STATE (Bitfield-Mask: 0x0f) */ +/* =================================================== XTALRDY_CTRL_REG ==================================================== */ +#define CRG_XTAL_XTALRDY_CTRL_REG_XTALRDY_CLK_SEL_Pos (8UL) /*!< XTALRDY_CLK_SEL (Bit 8) */ +#define CRG_XTAL_XTALRDY_CTRL_REG_XTALRDY_CLK_SEL_Msk (0x100UL) /*!< XTALRDY_CLK_SEL (Bitfield-Mask: 0x01) */ +#define CRG_XTAL_XTALRDY_CTRL_REG_XTALRDY_CNT_Pos (0UL) /*!< XTALRDY_CNT (Bit 0) */ +#define CRG_XTAL_XTALRDY_CTRL_REG_XTALRDY_CNT_Msk (0xffUL) /*!< XTALRDY_CNT (Bitfield-Mask: 0xff) */ +/* =================================================== XTALRDY_STAT_REG ==================================================== */ +#define CRG_XTAL_XTALRDY_STAT_REG_XTALRDY_COUNT_Pos (8UL) /*!< XTALRDY_COUNT (Bit 8) */ +#define CRG_XTAL_XTALRDY_STAT_REG_XTALRDY_COUNT_Msk (0xff00UL) /*!< XTALRDY_COUNT (Bitfield-Mask: 0xff) */ +#define CRG_XTAL_XTALRDY_STAT_REG_XTALRDY_STAT_Pos (0UL) /*!< XTALRDY_STAT (Bit 0) */ +#define CRG_XTAL_XTALRDY_STAT_REG_XTALRDY_STAT_Msk (0xffUL) /*!< XTALRDY_STAT (Bitfield-Mask: 0xff) */ + + +/* =========================================================================================================================== */ +/* ================ DCDC ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== DCDC_CTRL1_REG ===================================================== */ +#define DCDC_DCDC_CTRL1_REG_DCDC_SH_ENABLE_Pos (31UL) /*!< DCDC_SH_ENABLE (Bit 31) */ +#define DCDC_DCDC_CTRL1_REG_DCDC_SH_ENABLE_Msk (0x80000000UL) /*!< DCDC_SH_ENABLE (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_CTRL1_REG_DCDC_STARTUP_DELAY_Pos (26UL) /*!< DCDC_STARTUP_DELAY (Bit 26) */ +#define DCDC_DCDC_CTRL1_REG_DCDC_STARTUP_DELAY_Msk (0x7c000000UL) /*!< DCDC_STARTUP_DELAY (Bitfield-Mask: 0x1f) */ +#define DCDC_DCDC_CTRL1_REG_DCDC_IDLE_MAX_FAST_DOWNRAMP_Pos (20UL) /*!< DCDC_IDLE_MAX_FAST_DOWNRAMP (Bit 20) */ +#define DCDC_DCDC_CTRL1_REG_DCDC_IDLE_MAX_FAST_DOWNRAMP_Msk (0x3f00000UL) /*!< DCDC_IDLE_MAX_FAST_DOWNRAMP (Bitfield-Mask: 0x3f) */ +#define DCDC_DCDC_CTRL1_REG_DCDC_SW_TIMEOUT_Pos (15UL) /*!< DCDC_SW_TIMEOUT (Bit 15) */ +#define DCDC_DCDC_CTRL1_REG_DCDC_SW_TIMEOUT_Msk (0xf8000UL) /*!< DCDC_SW_TIMEOUT (Bitfield-Mask: 0x1f) */ +#define DCDC_DCDC_CTRL1_REG_DCDC_FAST_STARTUP_Pos (14UL) /*!< DCDC_FAST_STARTUP (Bit 14) */ +#define DCDC_DCDC_CTRL1_REG_DCDC_FAST_STARTUP_Msk (0x4000UL) /*!< DCDC_FAST_STARTUP (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_CTRL1_REG_DCDC_MAN_LV_MODE_Pos (13UL) /*!< DCDC_MAN_LV_MODE (Bit 13) */ +#define DCDC_DCDC_CTRL1_REG_DCDC_MAN_LV_MODE_Msk (0x2000UL) /*!< DCDC_MAN_LV_MODE (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_CTRL1_REG_DCDC_AUTO_LV_MODE_Pos (12UL) /*!< DCDC_AUTO_LV_MODE (Bit 12) */ +#define DCDC_DCDC_CTRL1_REG_DCDC_AUTO_LV_MODE_Msk (0x1000UL) /*!< DCDC_AUTO_LV_MODE (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_CTRL1_REG_DCDC_IDLE_CLK_DIV_Pos (10UL) /*!< DCDC_IDLE_CLK_DIV (Bit 10) */ +#define DCDC_DCDC_CTRL1_REG_DCDC_IDLE_CLK_DIV_Msk (0xc00UL) /*!< DCDC_IDLE_CLK_DIV (Bitfield-Mask: 0x03) */ +#define DCDC_DCDC_CTRL1_REG_DCDC_PRIORITY_Pos (2UL) /*!< DCDC_PRIORITY (Bit 2) */ +#define DCDC_DCDC_CTRL1_REG_DCDC_PRIORITY_Msk (0x3fcUL) /*!< DCDC_PRIORITY (Bitfield-Mask: 0xff) */ +#define DCDC_DCDC_CTRL1_REG_DCDC_FW_ENABLE_Pos (1UL) /*!< DCDC_FW_ENABLE (Bit 1) */ +#define DCDC_DCDC_CTRL1_REG_DCDC_FW_ENABLE_Msk (0x2UL) /*!< DCDC_FW_ENABLE (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_CTRL1_REG_DCDC_ENABLE_Pos (0UL) /*!< DCDC_ENABLE (Bit 0) */ +#define DCDC_DCDC_CTRL1_REG_DCDC_ENABLE_Msk (0x1UL) /*!< DCDC_ENABLE (Bitfield-Mask: 0x01) */ +/* ==================================================== DCDC_CTRL2_REG ===================================================== */ +#define DCDC_DCDC_CTRL2_REG_DCDC_V_NOK_CNT_MAX_Pos (24UL) /*!< DCDC_V_NOK_CNT_MAX (Bit 24) */ +#define DCDC_DCDC_CTRL2_REG_DCDC_V_NOK_CNT_MAX_Msk (0xf000000UL) /*!< DCDC_V_NOK_CNT_MAX (Bitfield-Mask: 0x0f) */ +#define DCDC_DCDC_CTRL2_REG_DCDC_N_COMP_TRIM_MAN_Pos (22UL) /*!< DCDC_N_COMP_TRIM_MAN (Bit 22) */ +#define DCDC_DCDC_CTRL2_REG_DCDC_N_COMP_TRIM_MAN_Msk (0x400000UL) /*!< DCDC_N_COMP_TRIM_MAN (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_CTRL2_REG_DCDC_N_COMP_TRIM_VAL_Pos (16UL) /*!< DCDC_N_COMP_TRIM_VAL (Bit 16) */ +#define DCDC_DCDC_CTRL2_REG_DCDC_N_COMP_TRIM_VAL_Msk (0x3f0000UL) /*!< DCDC_N_COMP_TRIM_VAL (Bitfield-Mask: 0x3f) */ +#define DCDC_DCDC_CTRL2_REG_DCDC_TIMEOUT_IRQ_TRIG_Pos (12UL) /*!< DCDC_TIMEOUT_IRQ_TRIG (Bit 12) */ +#define DCDC_DCDC_CTRL2_REG_DCDC_TIMEOUT_IRQ_TRIG_Msk (0xf000UL) /*!< DCDC_TIMEOUT_IRQ_TRIG (Bitfield-Mask: 0x0f) */ +#define DCDC_DCDC_CTRL2_REG_DCDC_TIMEOUT_IRQ_RES_Pos (8UL) /*!< DCDC_TIMEOUT_IRQ_RES (Bit 8) */ +#define DCDC_DCDC_CTRL2_REG_DCDC_TIMEOUT_IRQ_RES_Msk (0xf00UL) /*!< DCDC_TIMEOUT_IRQ_RES (Bitfield-Mask: 0x0f) */ +#define DCDC_DCDC_CTRL2_REG_DCDC_SLOPE_CONTROL_Pos (6UL) /*!< DCDC_SLOPE_CONTROL (Bit 6) */ +#define DCDC_DCDC_CTRL2_REG_DCDC_SLOPE_CONTROL_Msk (0xc0UL) /*!< DCDC_SLOPE_CONTROL (Bitfield-Mask: 0x03) */ +#define DCDC_DCDC_CTRL2_REG_DCDC_VBTSTRP_TRIM_Pos (4UL) /*!< DCDC_VBTSTRP_TRIM (Bit 4) */ +#define DCDC_DCDC_CTRL2_REG_DCDC_VBTSTRP_TRIM_Msk (0x30UL) /*!< DCDC_VBTSTRP_TRIM (Bitfield-Mask: 0x03) */ +#define DCDC_DCDC_CTRL2_REG_DCDC_LSSUP_TRIM_Pos (2UL) /*!< DCDC_LSSUP_TRIM (Bit 2) */ +#define DCDC_DCDC_CTRL2_REG_DCDC_LSSUP_TRIM_Msk (0xcUL) /*!< DCDC_LSSUP_TRIM (Bitfield-Mask: 0x03) */ +#define DCDC_DCDC_CTRL2_REG_DCDC_HSGND_TRIM_Pos (0UL) /*!< DCDC_HSGND_TRIM (Bit 0) */ +#define DCDC_DCDC_CTRL2_REG_DCDC_HSGND_TRIM_Msk (0x3UL) /*!< DCDC_HSGND_TRIM (Bitfield-Mask: 0x03) */ +/* ================================================== DCDC_IRQ_CLEAR_REG =================================================== */ +#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_LOW_VBAT_IRQ_CLEAR_Pos (4UL) /*!< DCDC_LOW_VBAT_IRQ_CLEAR (Bit 4) */ +#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_LOW_VBAT_IRQ_CLEAR_Msk (0x10UL) /*!< DCDC_LOW_VBAT_IRQ_CLEAR (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18P_TIMEOUT_IRQ_CLEAR_Pos (3UL) /*!< DCDC_V18P_TIMEOUT_IRQ_CLEAR (Bit 3) */ +#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18P_TIMEOUT_IRQ_CLEAR_Msk (0x8UL) /*!< DCDC_V18P_TIMEOUT_IRQ_CLEAR (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_VDD_TIMEOUT_IRQ_CLEAR_Pos (2UL) /*!< DCDC_VDD_TIMEOUT_IRQ_CLEAR (Bit 2) */ +#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_VDD_TIMEOUT_IRQ_CLEAR_Msk (0x4UL) /*!< DCDC_VDD_TIMEOUT_IRQ_CLEAR (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18_TIMEOUT_IRQ_CLEAR_Pos (1UL) /*!< DCDC_V18_TIMEOUT_IRQ_CLEAR (Bit 1) */ +#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18_TIMEOUT_IRQ_CLEAR_Msk (0x2UL) /*!< DCDC_V18_TIMEOUT_IRQ_CLEAR (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V14_TIMEOUT_IRQ_CLEAR_Pos (0UL) /*!< DCDC_V14_TIMEOUT_IRQ_CLEAR (Bit 0) */ +#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V14_TIMEOUT_IRQ_CLEAR_Msk (0x1UL) /*!< DCDC_V14_TIMEOUT_IRQ_CLEAR (Bitfield-Mask: 0x01) */ +/* =================================================== DCDC_IRQ_MASK_REG =================================================== */ +#define DCDC_DCDC_IRQ_MASK_REG_DCDC_LOW_VBAT_IRQ_MASK_Pos (4UL) /*!< DCDC_LOW_VBAT_IRQ_MASK (Bit 4) */ +#define DCDC_DCDC_IRQ_MASK_REG_DCDC_LOW_VBAT_IRQ_MASK_Msk (0x10UL) /*!< DCDC_LOW_VBAT_IRQ_MASK (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18P_TIMEOUT_IRQ_MASK_Pos (3UL) /*!< DCDC_V18P_TIMEOUT_IRQ_MASK (Bit 3) */ +#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18P_TIMEOUT_IRQ_MASK_Msk (0x8UL) /*!< DCDC_V18P_TIMEOUT_IRQ_MASK (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_IRQ_MASK_REG_DCDC_VDD_TIMEOUT_IRQ_MASK_Pos (2UL) /*!< DCDC_VDD_TIMEOUT_IRQ_MASK (Bit 2) */ +#define DCDC_DCDC_IRQ_MASK_REG_DCDC_VDD_TIMEOUT_IRQ_MASK_Msk (0x4UL) /*!< DCDC_VDD_TIMEOUT_IRQ_MASK (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18_TIMEOUT_IRQ_MASK_Pos (1UL) /*!< DCDC_V18_TIMEOUT_IRQ_MASK (Bit 1) */ +#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18_TIMEOUT_IRQ_MASK_Msk (0x2UL) /*!< DCDC_V18_TIMEOUT_IRQ_MASK (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V14_TIMEOUT_IRQ_MASK_Pos (0UL) /*!< DCDC_V14_TIMEOUT_IRQ_MASK (Bit 0) */ +#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V14_TIMEOUT_IRQ_MASK_Msk (0x1UL) /*!< DCDC_V14_TIMEOUT_IRQ_MASK (Bitfield-Mask: 0x01) */ +/* ================================================== DCDC_IRQ_STATUS_REG ================================================== */ +#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_LOW_VBAT_IRQ_STATUS_Pos (4UL) /*!< DCDC_LOW_VBAT_IRQ_STATUS (Bit 4) */ +#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_LOW_VBAT_IRQ_STATUS_Msk (0x10UL) /*!< DCDC_LOW_VBAT_IRQ_STATUS (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18P_TIMEOUT_IRQ_STATUS_Pos (3UL) /*!< DCDC_V18P_TIMEOUT_IRQ_STATUS (Bit 3) */ +#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18P_TIMEOUT_IRQ_STATUS_Msk (0x8UL) /*!< DCDC_V18P_TIMEOUT_IRQ_STATUS (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_VDD_TIMEOUT_IRQ_STATUS_Pos (2UL) /*!< DCDC_VDD_TIMEOUT_IRQ_STATUS (Bit 2) */ +#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_VDD_TIMEOUT_IRQ_STATUS_Msk (0x4UL) /*!< DCDC_VDD_TIMEOUT_IRQ_STATUS (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18_TIMEOUT_IRQ_STATUS_Pos (1UL) /*!< DCDC_V18_TIMEOUT_IRQ_STATUS (Bit 1) */ +#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18_TIMEOUT_IRQ_STATUS_Msk (0x2UL) /*!< DCDC_V18_TIMEOUT_IRQ_STATUS (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V14_TIMEOUT_IRQ_STATUS_Pos (0UL) /*!< DCDC_V14_TIMEOUT_IRQ_STATUS (Bit 0) */ +#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V14_TIMEOUT_IRQ_STATUS_Msk (0x1UL) /*!< DCDC_V14_TIMEOUT_IRQ_STATUS (Bitfield-Mask: 0x01) */ +/* =================================================== DCDC_STATUS1_REG ==================================================== */ +#define DCDC_DCDC_STATUS1_REG_DCDC_V18P_AVAILABLE_Pos (27UL) /*!< DCDC_V18P_AVAILABLE (Bit 27) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_V18P_AVAILABLE_Msk (0x8000000UL) /*!< DCDC_V18P_AVAILABLE (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_VDD_AVAILABLE_Pos (26UL) /*!< DCDC_VDD_AVAILABLE (Bit 26) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_VDD_AVAILABLE_Msk (0x4000000UL) /*!< DCDC_VDD_AVAILABLE (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_V18_AVAILABLE_Pos (25UL) /*!< DCDC_V18_AVAILABLE (Bit 25) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_V18_AVAILABLE_Msk (0x2000000UL) /*!< DCDC_V18_AVAILABLE (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_V14_AVAILABLE_Pos (24UL) /*!< DCDC_V14_AVAILABLE (Bit 24) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_V14_AVAILABLE_Msk (0x1000000UL) /*!< DCDC_V14_AVAILABLE (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_V18P_COMP_OK_Pos (23UL) /*!< DCDC_V18P_COMP_OK (Bit 23) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_V18P_COMP_OK_Msk (0x800000UL) /*!< DCDC_V18P_COMP_OK (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_VDD_COMP_OK_Pos (22UL) /*!< DCDC_VDD_COMP_OK (Bit 22) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_VDD_COMP_OK_Msk (0x400000UL) /*!< DCDC_VDD_COMP_OK (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_V18_COMP_OK_Pos (21UL) /*!< DCDC_V18_COMP_OK (Bit 21) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_V18_COMP_OK_Msk (0x200000UL) /*!< DCDC_V18_COMP_OK (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_V14_COMP_OK_Pos (20UL) /*!< DCDC_V14_COMP_OK (Bit 20) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_V14_COMP_OK_Msk (0x100000UL) /*!< DCDC_V14_COMP_OK (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_V18P_COMP_NOK_Pos (19UL) /*!< DCDC_V18P_COMP_NOK (Bit 19) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_V18P_COMP_NOK_Msk (0x80000UL) /*!< DCDC_V18P_COMP_NOK (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_VDD_COMP_NOK_Pos (18UL) /*!< DCDC_VDD_COMP_NOK (Bit 18) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_VDD_COMP_NOK_Msk (0x40000UL) /*!< DCDC_VDD_COMP_NOK (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_V18_COMP_NOK_Pos (17UL) /*!< DCDC_V18_COMP_NOK (Bit 17) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_V18_COMP_NOK_Msk (0x20000UL) /*!< DCDC_V18_COMP_NOK (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_V14_COMP_NOK_Pos (16UL) /*!< DCDC_V14_COMP_NOK (Bit 16) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_V14_COMP_NOK_Msk (0x10000UL) /*!< DCDC_V14_COMP_NOK (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_N_COMP_P_Pos (11UL) /*!< DCDC_N_COMP_P (Bit 11) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_N_COMP_P_Msk (0x800UL) /*!< DCDC_N_COMP_P (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_N_COMP_N_Pos (10UL) /*!< DCDC_N_COMP_N (Bit 10) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_N_COMP_N_Msk (0x400UL) /*!< DCDC_N_COMP_N (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_P_COMP_Pos (9UL) /*!< DCDC_P_COMP (Bit 9) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_P_COMP_Msk (0x200UL) /*!< DCDC_P_COMP (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_N_COMP_Pos (8UL) /*!< DCDC_N_COMP (Bit 8) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_N_COMP_Msk (0x100UL) /*!< DCDC_N_COMP (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_LV_MODE_Pos (7UL) /*!< DCDC_LV_MODE (Bit 7) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_LV_MODE_Msk (0x80UL) /*!< DCDC_LV_MODE (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_V18P_SW_STATE_Pos (6UL) /*!< DCDC_V18P_SW_STATE (Bit 6) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_V18P_SW_STATE_Msk (0x40UL) /*!< DCDC_V18P_SW_STATE (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_VDD_SW_STATE_Pos (5UL) /*!< DCDC_VDD_SW_STATE (Bit 5) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_VDD_SW_STATE_Msk (0x20UL) /*!< DCDC_VDD_SW_STATE (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_V18_SW_STATE_Pos (4UL) /*!< DCDC_V18_SW_STATE (Bit 4) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_V18_SW_STATE_Msk (0x10UL) /*!< DCDC_V18_SW_STATE (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_V14_SW_STATE_Pos (3UL) /*!< DCDC_V14_SW_STATE (Bit 3) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_V14_SW_STATE_Msk (0x8UL) /*!< DCDC_V14_SW_STATE (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_N_SW_STATE_Pos (2UL) /*!< DCDC_N_SW_STATE (Bit 2) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_N_SW_STATE_Msk (0x4UL) /*!< DCDC_N_SW_STATE (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_P_SW_STATE_Pos (1UL) /*!< DCDC_P_SW_STATE (Bit 1) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_P_SW_STATE_Msk (0x2UL) /*!< DCDC_P_SW_STATE (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_STARTUP_COMPLETE_Pos (0UL) /*!< DCDC_STARTUP_COMPLETE (Bit 0) */ +#define DCDC_DCDC_STATUS1_REG_DCDC_STARTUP_COMPLETE_Msk (0x1UL) /*!< DCDC_STARTUP_COMPLETE (Bitfield-Mask: 0x01) */ +/* ===================================================== DCDC_V14_REG ====================================================== */ +#define DCDC_DCDC_V14_REG_DCDC_V14_FAST_RAMPING_Pos (31UL) /*!< DCDC_V14_FAST_RAMPING (Bit 31) */ +#define DCDC_DCDC_V14_REG_DCDC_V14_FAST_RAMPING_Msk (0x80000000UL) /*!< DCDC_V14_FAST_RAMPING (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_V14_REG_DCDC_V14_TRIM_Pos (27UL) /*!< DCDC_V14_TRIM (Bit 27) */ +#define DCDC_DCDC_V14_REG_DCDC_V14_TRIM_Msk (0x8000000UL) /*!< DCDC_V14_TRIM (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MAX_HV_Pos (22UL) /*!< DCDC_V14_CUR_LIM_MAX_HV (Bit 22) */ +#define DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MAX_HV_Msk (0x7c00000UL) /*!< DCDC_V14_CUR_LIM_MAX_HV (Bitfield-Mask: 0x1f) */ +#define DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MAX_LV_Pos (17UL) /*!< DCDC_V14_CUR_LIM_MAX_LV (Bit 17) */ +#define DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MAX_LV_Msk (0x3e0000UL) /*!< DCDC_V14_CUR_LIM_MAX_LV (Bitfield-Mask: 0x1f) */ +#define DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MIN_Pos (12UL) /*!< DCDC_V14_CUR_LIM_MIN (Bit 12) */ +#define DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MIN_Msk (0x1f000UL) /*!< DCDC_V14_CUR_LIM_MIN (Bitfield-Mask: 0x1f) */ +#define DCDC_DCDC_V14_REG_DCDC_V14_IDLE_HYST_Pos (7UL) /*!< DCDC_V14_IDLE_HYST (Bit 7) */ +#define DCDC_DCDC_V14_REG_DCDC_V14_IDLE_HYST_Msk (0xf80UL) /*!< DCDC_V14_IDLE_HYST (Bitfield-Mask: 0x1f) */ +#define DCDC_DCDC_V14_REG_DCDC_V14_IDLE_MIN_Pos (2UL) /*!< DCDC_V14_IDLE_MIN (Bit 2) */ +#define DCDC_DCDC_V14_REG_DCDC_V14_IDLE_MIN_Msk (0x7cUL) /*!< DCDC_V14_IDLE_MIN (Bitfield-Mask: 0x1f) */ +#define DCDC_DCDC_V14_REG_DCDC_V14_ENABLE_HV_Pos (1UL) /*!< DCDC_V14_ENABLE_HV (Bit 1) */ +#define DCDC_DCDC_V14_REG_DCDC_V14_ENABLE_HV_Msk (0x2UL) /*!< DCDC_V14_ENABLE_HV (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_V14_REG_DCDC_V14_ENABLE_LV_Pos (0UL) /*!< DCDC_V14_ENABLE_LV (Bit 0) */ +#define DCDC_DCDC_V14_REG_DCDC_V14_ENABLE_LV_Msk (0x1UL) /*!< DCDC_V14_ENABLE_LV (Bitfield-Mask: 0x01) */ +/* ===================================================== DCDC_V18P_REG ===================================================== */ +#define DCDC_DCDC_V18P_REG_DCDC_V18P_FAST_RAMPING_Pos (31UL) /*!< DCDC_V18P_FAST_RAMPING (Bit 31) */ +#define DCDC_DCDC_V18P_REG_DCDC_V18P_FAST_RAMPING_Msk (0x80000000UL) /*!< DCDC_V18P_FAST_RAMPING (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_V18P_REG_DCDC_V18P_TRIM_Pos (27UL) /*!< DCDC_V18P_TRIM (Bit 27) */ +#define DCDC_DCDC_V18P_REG_DCDC_V18P_TRIM_Msk (0x78000000UL) /*!< DCDC_V18P_TRIM (Bitfield-Mask: 0x0f) */ +#define DCDC_DCDC_V18P_REG_DCDC_V18P_CUR_LIM_MAX_HV_Pos (22UL) /*!< DCDC_V18P_CUR_LIM_MAX_HV (Bit 22) */ +#define DCDC_DCDC_V18P_REG_DCDC_V18P_CUR_LIM_MAX_HV_Msk (0x7c00000UL) /*!< DCDC_V18P_CUR_LIM_MAX_HV (Bitfield-Mask: 0x1f) */ +#define DCDC_DCDC_V18P_REG_DCDC_V18P_CUR_LIM_MAX_LV_Pos (17UL) /*!< DCDC_V18P_CUR_LIM_MAX_LV (Bit 17) */ +#define DCDC_DCDC_V18P_REG_DCDC_V18P_CUR_LIM_MAX_LV_Msk (0x3e0000UL) /*!< DCDC_V18P_CUR_LIM_MAX_LV (Bitfield-Mask: 0x1f) */ +#define DCDC_DCDC_V18P_REG_DCDC_V18P_CUR_LIM_MIN_Pos (12UL) /*!< DCDC_V18P_CUR_LIM_MIN (Bit 12) */ +#define DCDC_DCDC_V18P_REG_DCDC_V18P_CUR_LIM_MIN_Msk (0x1f000UL) /*!< DCDC_V18P_CUR_LIM_MIN (Bitfield-Mask: 0x1f) */ +#define DCDC_DCDC_V18P_REG_DCDC_V18P_IDLE_HYST_Pos (7UL) /*!< DCDC_V18P_IDLE_HYST (Bit 7) */ +#define DCDC_DCDC_V18P_REG_DCDC_V18P_IDLE_HYST_Msk (0xf80UL) /*!< DCDC_V18P_IDLE_HYST (Bitfield-Mask: 0x1f) */ +#define DCDC_DCDC_V18P_REG_DCDC_V18P_IDLE_MIN_Pos (2UL) /*!< DCDC_V18P_IDLE_MIN (Bit 2) */ +#define DCDC_DCDC_V18P_REG_DCDC_V18P_IDLE_MIN_Msk (0x7cUL) /*!< DCDC_V18P_IDLE_MIN (Bitfield-Mask: 0x1f) */ +#define DCDC_DCDC_V18P_REG_DCDC_V18P_ENABLE_HV_Pos (1UL) /*!< DCDC_V18P_ENABLE_HV (Bit 1) */ +#define DCDC_DCDC_V18P_REG_DCDC_V18P_ENABLE_HV_Msk (0x2UL) /*!< DCDC_V18P_ENABLE_HV (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_V18P_REG_DCDC_V18P_ENABLE_LV_Pos (0UL) /*!< DCDC_V18P_ENABLE_LV (Bit 0) */ +#define DCDC_DCDC_V18P_REG_DCDC_V18P_ENABLE_LV_Msk (0x1UL) /*!< DCDC_V18P_ENABLE_LV (Bitfield-Mask: 0x01) */ +/* ===================================================== DCDC_V18_REG ====================================================== */ +#define DCDC_DCDC_V18_REG_DCDC_V18_FAST_RAMPING_Pos (31UL) /*!< DCDC_V18_FAST_RAMPING (Bit 31) */ +#define DCDC_DCDC_V18_REG_DCDC_V18_FAST_RAMPING_Msk (0x80000000UL) /*!< DCDC_V18_FAST_RAMPING (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_V18_REG_DCDC_V18_TRIM_Pos (27UL) /*!< DCDC_V18_TRIM (Bit 27) */ +#define DCDC_DCDC_V18_REG_DCDC_V18_TRIM_Msk (0x78000000UL) /*!< DCDC_V18_TRIM (Bitfield-Mask: 0x0f) */ +#define DCDC_DCDC_V18_REG_DCDC_V18_CUR_LIM_MAX_HV_Pos (22UL) /*!< DCDC_V18_CUR_LIM_MAX_HV (Bit 22) */ +#define DCDC_DCDC_V18_REG_DCDC_V18_CUR_LIM_MAX_HV_Msk (0x7c00000UL) /*!< DCDC_V18_CUR_LIM_MAX_HV (Bitfield-Mask: 0x1f) */ +#define DCDC_DCDC_V18_REG_DCDC_V18_CUR_LIM_MAX_LV_Pos (17UL) /*!< DCDC_V18_CUR_LIM_MAX_LV (Bit 17) */ +#define DCDC_DCDC_V18_REG_DCDC_V18_CUR_LIM_MAX_LV_Msk (0x3e0000UL) /*!< DCDC_V18_CUR_LIM_MAX_LV (Bitfield-Mask: 0x1f) */ +#define DCDC_DCDC_V18_REG_DCDC_V18_CUR_LIM_MIN_Pos (12UL) /*!< DCDC_V18_CUR_LIM_MIN (Bit 12) */ +#define DCDC_DCDC_V18_REG_DCDC_V18_CUR_LIM_MIN_Msk (0x1f000UL) /*!< DCDC_V18_CUR_LIM_MIN (Bitfield-Mask: 0x1f) */ +#define DCDC_DCDC_V18_REG_DCDC_V18_IDLE_HYST_Pos (7UL) /*!< DCDC_V18_IDLE_HYST (Bit 7) */ +#define DCDC_DCDC_V18_REG_DCDC_V18_IDLE_HYST_Msk (0xf80UL) /*!< DCDC_V18_IDLE_HYST (Bitfield-Mask: 0x1f) */ +#define DCDC_DCDC_V18_REG_DCDC_V18_IDLE_MIN_Pos (2UL) /*!< DCDC_V18_IDLE_MIN (Bit 2) */ +#define DCDC_DCDC_V18_REG_DCDC_V18_IDLE_MIN_Msk (0x7cUL) /*!< DCDC_V18_IDLE_MIN (Bitfield-Mask: 0x1f) */ +#define DCDC_DCDC_V18_REG_DCDC_V18_ENABLE_HV_Pos (1UL) /*!< DCDC_V18_ENABLE_HV (Bit 1) */ +#define DCDC_DCDC_V18_REG_DCDC_V18_ENABLE_HV_Msk (0x2UL) /*!< DCDC_V18_ENABLE_HV (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_V18_REG_DCDC_V18_ENABLE_LV_Pos (0UL) /*!< DCDC_V18_ENABLE_LV (Bit 0) */ +#define DCDC_DCDC_V18_REG_DCDC_V18_ENABLE_LV_Msk (0x1UL) /*!< DCDC_V18_ENABLE_LV (Bitfield-Mask: 0x01) */ +/* ===================================================== DCDC_VDD_REG ====================================================== */ +#define DCDC_DCDC_VDD_REG_DCDC_VDD_FAST_RAMPING_Pos (31UL) /*!< DCDC_VDD_FAST_RAMPING (Bit 31) */ +#define DCDC_DCDC_VDD_REG_DCDC_VDD_FAST_RAMPING_Msk (0x80000000UL) /*!< DCDC_VDD_FAST_RAMPING (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_VDD_REG_DCDC_VDD_TRIM_Pos (27UL) /*!< DCDC_VDD_TRIM (Bit 27) */ +#define DCDC_DCDC_VDD_REG_DCDC_VDD_TRIM_Msk (0x38000000UL) /*!< DCDC_VDD_TRIM (Bitfield-Mask: 0x07) */ +#define DCDC_DCDC_VDD_REG_DCDC_VDD_CUR_LIM_MAX_HV_Pos (22UL) /*!< DCDC_VDD_CUR_LIM_MAX_HV (Bit 22) */ +#define DCDC_DCDC_VDD_REG_DCDC_VDD_CUR_LIM_MAX_HV_Msk (0x7c00000UL) /*!< DCDC_VDD_CUR_LIM_MAX_HV (Bitfield-Mask: 0x1f) */ +#define DCDC_DCDC_VDD_REG_DCDC_VDD_CUR_LIM_MAX_LV_Pos (17UL) /*!< DCDC_VDD_CUR_LIM_MAX_LV (Bit 17) */ +#define DCDC_DCDC_VDD_REG_DCDC_VDD_CUR_LIM_MAX_LV_Msk (0x3e0000UL) /*!< DCDC_VDD_CUR_LIM_MAX_LV (Bitfield-Mask: 0x1f) */ +#define DCDC_DCDC_VDD_REG_DCDC_VDD_CUR_LIM_MIN_Pos (12UL) /*!< DCDC_VDD_CUR_LIM_MIN (Bit 12) */ +#define DCDC_DCDC_VDD_REG_DCDC_VDD_CUR_LIM_MIN_Msk (0x1f000UL) /*!< DCDC_VDD_CUR_LIM_MIN (Bitfield-Mask: 0x1f) */ +#define DCDC_DCDC_VDD_REG_DCDC_VDD_IDLE_HYST_Pos (7UL) /*!< DCDC_VDD_IDLE_HYST (Bit 7) */ +#define DCDC_DCDC_VDD_REG_DCDC_VDD_IDLE_HYST_Msk (0xf80UL) /*!< DCDC_VDD_IDLE_HYST (Bitfield-Mask: 0x1f) */ +#define DCDC_DCDC_VDD_REG_DCDC_VDD_IDLE_MIN_Pos (2UL) /*!< DCDC_VDD_IDLE_MIN (Bit 2) */ +#define DCDC_DCDC_VDD_REG_DCDC_VDD_IDLE_MIN_Msk (0x7cUL) /*!< DCDC_VDD_IDLE_MIN (Bitfield-Mask: 0x1f) */ +#define DCDC_DCDC_VDD_REG_DCDC_VDD_ENABLE_HV_Pos (1UL) /*!< DCDC_VDD_ENABLE_HV (Bit 1) */ +#define DCDC_DCDC_VDD_REG_DCDC_VDD_ENABLE_HV_Msk (0x2UL) /*!< DCDC_VDD_ENABLE_HV (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_VDD_REG_DCDC_VDD_ENABLE_LV_Pos (0UL) /*!< DCDC_VDD_ENABLE_LV (Bit 0) */ +#define DCDC_DCDC_VDD_REG_DCDC_VDD_ENABLE_LV_Msk (0x1UL) /*!< DCDC_VDD_ENABLE_LV (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ DMA ================ */ +/* =========================================================================================================================== */ + +/* =================================================== DMA0_A_START_REG ==================================================== */ +#define DMA_DMA0_A_START_REG_DMA0_A_START_Pos (0UL) /*!< DMA0_A_START (Bit 0) */ +#define DMA_DMA0_A_START_REG_DMA0_A_START_Msk (0xffffffffUL) /*!< DMA0_A_START (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DMA0_B_START_REG ==================================================== */ +#define DMA_DMA0_B_START_REG_DMA0_B_START_Pos (0UL) /*!< DMA0_B_START (Bit 0) */ +#define DMA_DMA0_B_START_REG_DMA0_B_START_Msk (0xffffffffUL) /*!< DMA0_B_START (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== DMA0_CTRL_REG ===================================================== */ +#define DMA_DMA0_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */ +#define DMA_DMA0_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */ +#define DMA_DMA0_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */ +#define DMA_DMA0_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */ +#define DMA_DMA0_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */ +#define DMA_DMA0_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */ +#define DMA_DMA0_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */ +#define DMA_DMA0_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */ +#define DMA_DMA0_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */ +#define DMA_DMA0_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */ +#define DMA_DMA0_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */ +#define DMA_DMA0_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */ +#define DMA_DMA0_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */ +#define DMA_DMA0_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */ +#define DMA_DMA0_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */ +#define DMA_DMA0_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */ +#define DMA_DMA0_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */ +#define DMA_DMA0_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */ +#define DMA_DMA0_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */ +#define DMA_DMA0_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */ +#define DMA_DMA0_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */ +#define DMA_DMA0_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */ +#define DMA_DMA0_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */ +#define DMA_DMA0_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */ +/* ===================================================== DMA0_IDX_REG ====================================================== */ +#define DMA_DMA0_IDX_REG_DMA0_IDX_Pos (0UL) /*!< DMA0_IDX (Bit 0) */ +#define DMA_DMA0_IDX_REG_DMA0_IDX_Msk (0xffffUL) /*!< DMA0_IDX (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA0_INT_REG ====================================================== */ +#define DMA_DMA0_INT_REG_DMA0_INT_Pos (0UL) /*!< DMA0_INT (Bit 0) */ +#define DMA_DMA0_INT_REG_DMA0_INT_Msk (0xffffUL) /*!< DMA0_INT (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA0_LEN_REG ====================================================== */ +#define DMA_DMA0_LEN_REG_DMA0_LEN_Pos (0UL) /*!< DMA0_LEN (Bit 0) */ +#define DMA_DMA0_LEN_REG_DMA0_LEN_Msk (0xffffUL) /*!< DMA0_LEN (Bitfield-Mask: 0xffff) */ +/* =================================================== DMA1_A_START_REG ==================================================== */ +#define DMA_DMA1_A_START_REG_DMA1_A_START_Pos (0UL) /*!< DMA1_A_START (Bit 0) */ +#define DMA_DMA1_A_START_REG_DMA1_A_START_Msk (0xffffffffUL) /*!< DMA1_A_START (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DMA1_B_START_REG ==================================================== */ +#define DMA_DMA1_B_START_REG_DMA1_B_START_Pos (0UL) /*!< DMA1_B_START (Bit 0) */ +#define DMA_DMA1_B_START_REG_DMA1_B_START_Msk (0xffffffffUL) /*!< DMA1_B_START (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== DMA1_CTRL_REG ===================================================== */ +#define DMA_DMA1_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */ +#define DMA_DMA1_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */ +#define DMA_DMA1_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */ +#define DMA_DMA1_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */ +#define DMA_DMA1_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */ +#define DMA_DMA1_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */ +#define DMA_DMA1_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */ +#define DMA_DMA1_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */ +#define DMA_DMA1_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */ +#define DMA_DMA1_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */ +#define DMA_DMA1_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */ +#define DMA_DMA1_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */ +#define DMA_DMA1_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */ +#define DMA_DMA1_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */ +#define DMA_DMA1_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */ +#define DMA_DMA1_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */ +#define DMA_DMA1_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */ +#define DMA_DMA1_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */ +#define DMA_DMA1_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */ +#define DMA_DMA1_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */ +#define DMA_DMA1_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */ +#define DMA_DMA1_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */ +#define DMA_DMA1_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */ +#define DMA_DMA1_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */ +/* ===================================================== DMA1_IDX_REG ====================================================== */ +#define DMA_DMA1_IDX_REG_DMA1_IDX_Pos (0UL) /*!< DMA1_IDX (Bit 0) */ +#define DMA_DMA1_IDX_REG_DMA1_IDX_Msk (0xffffUL) /*!< DMA1_IDX (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA1_INT_REG ====================================================== */ +#define DMA_DMA1_INT_REG_DMA1_INT_Pos (0UL) /*!< DMA1_INT (Bit 0) */ +#define DMA_DMA1_INT_REG_DMA1_INT_Msk (0xffffUL) /*!< DMA1_INT (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA1_LEN_REG ====================================================== */ +#define DMA_DMA1_LEN_REG_DMA1_LEN_Pos (0UL) /*!< DMA1_LEN (Bit 0) */ +#define DMA_DMA1_LEN_REG_DMA1_LEN_Msk (0xffffUL) /*!< DMA1_LEN (Bitfield-Mask: 0xffff) */ +/* =================================================== DMA2_A_START_REG ==================================================== */ +#define DMA_DMA2_A_START_REG_DMA2_A_START_Pos (0UL) /*!< DMA2_A_START (Bit 0) */ +#define DMA_DMA2_A_START_REG_DMA2_A_START_Msk (0xffffffffUL) /*!< DMA2_A_START (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DMA2_B_START_REG ==================================================== */ +#define DMA_DMA2_B_START_REG_DMA2_B_START_Pos (0UL) /*!< DMA2_B_START (Bit 0) */ +#define DMA_DMA2_B_START_REG_DMA2_B_START_Msk (0xffffffffUL) /*!< DMA2_B_START (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== DMA2_CTRL_REG ===================================================== */ +#define DMA_DMA2_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */ +#define DMA_DMA2_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */ +#define DMA_DMA2_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */ +#define DMA_DMA2_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */ +#define DMA_DMA2_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */ +#define DMA_DMA2_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */ +#define DMA_DMA2_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */ +#define DMA_DMA2_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */ +#define DMA_DMA2_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */ +#define DMA_DMA2_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */ +#define DMA_DMA2_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */ +#define DMA_DMA2_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */ +#define DMA_DMA2_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */ +#define DMA_DMA2_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */ +#define DMA_DMA2_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */ +#define DMA_DMA2_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */ +#define DMA_DMA2_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */ +#define DMA_DMA2_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */ +#define DMA_DMA2_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */ +#define DMA_DMA2_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */ +#define DMA_DMA2_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */ +#define DMA_DMA2_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */ +#define DMA_DMA2_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */ +#define DMA_DMA2_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */ +/* ===================================================== DMA2_IDX_REG ====================================================== */ +#define DMA_DMA2_IDX_REG_DMA2_IDX_Pos (0UL) /*!< DMA2_IDX (Bit 0) */ +#define DMA_DMA2_IDX_REG_DMA2_IDX_Msk (0xffffUL) /*!< DMA2_IDX (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA2_INT_REG ====================================================== */ +#define DMA_DMA2_INT_REG_DMA2_INT_Pos (0UL) /*!< DMA2_INT (Bit 0) */ +#define DMA_DMA2_INT_REG_DMA2_INT_Msk (0xffffUL) /*!< DMA2_INT (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA2_LEN_REG ====================================================== */ +#define DMA_DMA2_LEN_REG_DMA2_LEN_Pos (0UL) /*!< DMA2_LEN (Bit 0) */ +#define DMA_DMA2_LEN_REG_DMA2_LEN_Msk (0xffffUL) /*!< DMA2_LEN (Bitfield-Mask: 0xffff) */ +/* =================================================== DMA3_A_START_REG ==================================================== */ +#define DMA_DMA3_A_START_REG_DMA3_A_START_Pos (0UL) /*!< DMA3_A_START (Bit 0) */ +#define DMA_DMA3_A_START_REG_DMA3_A_START_Msk (0xffffffffUL) /*!< DMA3_A_START (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DMA3_B_START_REG ==================================================== */ +#define DMA_DMA3_B_START_REG_DMA3_B_START_Pos (0UL) /*!< DMA3_B_START (Bit 0) */ +#define DMA_DMA3_B_START_REG_DMA3_B_START_Msk (0xffffffffUL) /*!< DMA3_B_START (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== DMA3_CTRL_REG ===================================================== */ +#define DMA_DMA3_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */ +#define DMA_DMA3_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */ +#define DMA_DMA3_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */ +#define DMA_DMA3_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */ +#define DMA_DMA3_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */ +#define DMA_DMA3_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */ +#define DMA_DMA3_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */ +#define DMA_DMA3_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */ +#define DMA_DMA3_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */ +#define DMA_DMA3_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */ +#define DMA_DMA3_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */ +#define DMA_DMA3_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */ +#define DMA_DMA3_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */ +#define DMA_DMA3_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */ +#define DMA_DMA3_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */ +#define DMA_DMA3_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */ +#define DMA_DMA3_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */ +#define DMA_DMA3_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */ +#define DMA_DMA3_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */ +#define DMA_DMA3_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */ +#define DMA_DMA3_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */ +#define DMA_DMA3_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */ +#define DMA_DMA3_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */ +#define DMA_DMA3_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */ +/* ===================================================== DMA3_IDX_REG ====================================================== */ +#define DMA_DMA3_IDX_REG_DMA3_IDX_Pos (0UL) /*!< DMA3_IDX (Bit 0) */ +#define DMA_DMA3_IDX_REG_DMA3_IDX_Msk (0xffffUL) /*!< DMA3_IDX (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA3_INT_REG ====================================================== */ +#define DMA_DMA3_INT_REG_DMA3_INT_Pos (0UL) /*!< DMA3_INT (Bit 0) */ +#define DMA_DMA3_INT_REG_DMA3_INT_Msk (0xffffUL) /*!< DMA3_INT (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA3_LEN_REG ====================================================== */ +#define DMA_DMA3_LEN_REG_DMA3_LEN_Pos (0UL) /*!< DMA3_LEN (Bit 0) */ +#define DMA_DMA3_LEN_REG_DMA3_LEN_Msk (0xffffUL) /*!< DMA3_LEN (Bitfield-Mask: 0xffff) */ +/* =================================================== DMA4_A_START_REG ==================================================== */ +#define DMA_DMA4_A_START_REG_DMA4_A_START_Pos (0UL) /*!< DMA4_A_START (Bit 0) */ +#define DMA_DMA4_A_START_REG_DMA4_A_START_Msk (0xffffffffUL) /*!< DMA4_A_START (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DMA4_B_START_REG ==================================================== */ +#define DMA_DMA4_B_START_REG_DMA4_B_START_Pos (0UL) /*!< DMA4_B_START (Bit 0) */ +#define DMA_DMA4_B_START_REG_DMA4_B_START_Msk (0xffffffffUL) /*!< DMA4_B_START (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== DMA4_CTRL_REG ===================================================== */ +#define DMA_DMA4_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */ +#define DMA_DMA4_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */ +#define DMA_DMA4_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */ +#define DMA_DMA4_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */ +#define DMA_DMA4_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */ +#define DMA_DMA4_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */ +#define DMA_DMA4_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */ +#define DMA_DMA4_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */ +#define DMA_DMA4_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */ +#define DMA_DMA4_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */ +#define DMA_DMA4_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */ +#define DMA_DMA4_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */ +#define DMA_DMA4_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */ +#define DMA_DMA4_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */ +#define DMA_DMA4_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */ +#define DMA_DMA4_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */ +#define DMA_DMA4_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */ +#define DMA_DMA4_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */ +#define DMA_DMA4_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */ +#define DMA_DMA4_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */ +#define DMA_DMA4_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */ +#define DMA_DMA4_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */ +#define DMA_DMA4_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */ +#define DMA_DMA4_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */ +/* ===================================================== DMA4_IDX_REG ====================================================== */ +#define DMA_DMA4_IDX_REG_DMA4_IDX_Pos (0UL) /*!< DMA4_IDX (Bit 0) */ +#define DMA_DMA4_IDX_REG_DMA4_IDX_Msk (0xffffUL) /*!< DMA4_IDX (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA4_INT_REG ====================================================== */ +#define DMA_DMA4_INT_REG_DMA4_INT_Pos (0UL) /*!< DMA4_INT (Bit 0) */ +#define DMA_DMA4_INT_REG_DMA4_INT_Msk (0xffffUL) /*!< DMA4_INT (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA4_LEN_REG ====================================================== */ +#define DMA_DMA4_LEN_REG_DMA4_LEN_Pos (0UL) /*!< DMA4_LEN (Bit 0) */ +#define DMA_DMA4_LEN_REG_DMA4_LEN_Msk (0xffffUL) /*!< DMA4_LEN (Bitfield-Mask: 0xffff) */ +/* =================================================== DMA5_A_START_REG ==================================================== */ +#define DMA_DMA5_A_START_REG_DMA5_A_START_Pos (0UL) /*!< DMA5_A_START (Bit 0) */ +#define DMA_DMA5_A_START_REG_DMA5_A_START_Msk (0xffffffffUL) /*!< DMA5_A_START (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DMA5_B_START_REG ==================================================== */ +#define DMA_DMA5_B_START_REG_DMA5_B_START_Pos (0UL) /*!< DMA5_B_START (Bit 0) */ +#define DMA_DMA5_B_START_REG_DMA5_B_START_Msk (0xffffffffUL) /*!< DMA5_B_START (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== DMA5_CTRL_REG ===================================================== */ +#define DMA_DMA5_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */ +#define DMA_DMA5_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */ +#define DMA_DMA5_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */ +#define DMA_DMA5_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */ +#define DMA_DMA5_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */ +#define DMA_DMA5_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */ +#define DMA_DMA5_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */ +#define DMA_DMA5_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */ +#define DMA_DMA5_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */ +#define DMA_DMA5_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */ +#define DMA_DMA5_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */ +#define DMA_DMA5_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */ +#define DMA_DMA5_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */ +#define DMA_DMA5_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */ +#define DMA_DMA5_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */ +#define DMA_DMA5_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */ +#define DMA_DMA5_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */ +#define DMA_DMA5_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */ +#define DMA_DMA5_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */ +#define DMA_DMA5_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */ +#define DMA_DMA5_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */ +#define DMA_DMA5_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */ +#define DMA_DMA5_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */ +#define DMA_DMA5_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */ +/* ===================================================== DMA5_IDX_REG ====================================================== */ +#define DMA_DMA5_IDX_REG_DMA5_IDX_Pos (0UL) /*!< DMA5_IDX (Bit 0) */ +#define DMA_DMA5_IDX_REG_DMA5_IDX_Msk (0xffffUL) /*!< DMA5_IDX (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA5_INT_REG ====================================================== */ +#define DMA_DMA5_INT_REG_DMA5_INT_Pos (0UL) /*!< DMA5_INT (Bit 0) */ +#define DMA_DMA5_INT_REG_DMA5_INT_Msk (0xffffUL) /*!< DMA5_INT (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA5_LEN_REG ====================================================== */ +#define DMA_DMA5_LEN_REG_DMA5_LEN_Pos (0UL) /*!< DMA5_LEN (Bit 0) */ +#define DMA_DMA5_LEN_REG_DMA5_LEN_Msk (0xffffUL) /*!< DMA5_LEN (Bitfield-Mask: 0xffff) */ +/* =================================================== DMA6_A_START_REG ==================================================== */ +#define DMA_DMA6_A_START_REG_DMA6_A_START_Pos (0UL) /*!< DMA6_A_START (Bit 0) */ +#define DMA_DMA6_A_START_REG_DMA6_A_START_Msk (0xffffffffUL) /*!< DMA6_A_START (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DMA6_B_START_REG ==================================================== */ +#define DMA_DMA6_B_START_REG_DMA6_B_START_Pos (0UL) /*!< DMA6_B_START (Bit 0) */ +#define DMA_DMA6_B_START_REG_DMA6_B_START_Msk (0xffffffffUL) /*!< DMA6_B_START (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== DMA6_CTRL_REG ===================================================== */ +#define DMA_DMA6_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */ +#define DMA_DMA6_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */ +#define DMA_DMA6_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */ +#define DMA_DMA6_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */ +#define DMA_DMA6_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */ +#define DMA_DMA6_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */ +#define DMA_DMA6_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */ +#define DMA_DMA6_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */ +#define DMA_DMA6_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */ +#define DMA_DMA6_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */ +#define DMA_DMA6_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */ +#define DMA_DMA6_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */ +#define DMA_DMA6_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */ +#define DMA_DMA6_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */ +#define DMA_DMA6_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */ +#define DMA_DMA6_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */ +#define DMA_DMA6_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */ +#define DMA_DMA6_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */ +#define DMA_DMA6_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */ +#define DMA_DMA6_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */ +#define DMA_DMA6_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */ +#define DMA_DMA6_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */ +#define DMA_DMA6_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */ +#define DMA_DMA6_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */ +/* ===================================================== DMA6_IDX_REG ====================================================== */ +#define DMA_DMA6_IDX_REG_DMA6_IDX_Pos (0UL) /*!< DMA6_IDX (Bit 0) */ +#define DMA_DMA6_IDX_REG_DMA6_IDX_Msk (0xffffUL) /*!< DMA6_IDX (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA6_INT_REG ====================================================== */ +#define DMA_DMA6_INT_REG_DMA6_INT_Pos (0UL) /*!< DMA6_INT (Bit 0) */ +#define DMA_DMA6_INT_REG_DMA6_INT_Msk (0xffffUL) /*!< DMA6_INT (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA6_LEN_REG ====================================================== */ +#define DMA_DMA6_LEN_REG_DMA6_LEN_Pos (0UL) /*!< DMA6_LEN (Bit 0) */ +#define DMA_DMA6_LEN_REG_DMA6_LEN_Msk (0xffffUL) /*!< DMA6_LEN (Bitfield-Mask: 0xffff) */ +/* =================================================== DMA7_A_START_REG ==================================================== */ +#define DMA_DMA7_A_START_REG_DMA7_A_START_Pos (0UL) /*!< DMA7_A_START (Bit 0) */ +#define DMA_DMA7_A_START_REG_DMA7_A_START_Msk (0xffffffffUL) /*!< DMA7_A_START (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DMA7_B_START_REG ==================================================== */ +#define DMA_DMA7_B_START_REG_DMA7_B_START_Pos (0UL) /*!< DMA7_B_START (Bit 0) */ +#define DMA_DMA7_B_START_REG_DMA7_B_START_Msk (0xffffffffUL) /*!< DMA7_B_START (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== DMA7_CTRL_REG ===================================================== */ +#define DMA_DMA7_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */ +#define DMA_DMA7_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */ +#define DMA_DMA7_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */ +#define DMA_DMA7_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */ +#define DMA_DMA7_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */ +#define DMA_DMA7_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */ +#define DMA_DMA7_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */ +#define DMA_DMA7_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */ +#define DMA_DMA7_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */ +#define DMA_DMA7_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */ +#define DMA_DMA7_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */ +#define DMA_DMA7_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */ +#define DMA_DMA7_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */ +#define DMA_DMA7_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */ +#define DMA_DMA7_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */ +#define DMA_DMA7_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */ +#define DMA_DMA7_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */ +#define DMA_DMA7_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */ +#define DMA_DMA7_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */ +#define DMA_DMA7_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */ +#define DMA_DMA7_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */ +#define DMA_DMA7_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */ +#define DMA_DMA7_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */ +#define DMA_DMA7_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */ +/* ===================================================== DMA7_IDX_REG ====================================================== */ +#define DMA_DMA7_IDX_REG_DMA7_IDX_Pos (0UL) /*!< DMA7_IDX (Bit 0) */ +#define DMA_DMA7_IDX_REG_DMA7_IDX_Msk (0xffffUL) /*!< DMA7_IDX (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA7_INT_REG ====================================================== */ +#define DMA_DMA7_INT_REG_DMA7_INT_Pos (0UL) /*!< DMA7_INT (Bit 0) */ +#define DMA_DMA7_INT_REG_DMA7_INT_Msk (0xffffUL) /*!< DMA7_INT (Bitfield-Mask: 0xffff) */ +/* ===================================================== DMA7_LEN_REG ====================================================== */ +#define DMA_DMA7_LEN_REG_DMA7_LEN_Pos (0UL) /*!< DMA7_LEN (Bit 0) */ +#define DMA_DMA7_LEN_REG_DMA7_LEN_Msk (0xffffUL) /*!< DMA7_LEN (Bitfield-Mask: 0xffff) */ +/* =================================================== DMA_CLEAR_INT_REG =================================================== */ +#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH7_Pos (7UL) /*!< DMA_RST_IRQ_CH7 (Bit 7) */ +#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH7_Msk (0x80UL) /*!< DMA_RST_IRQ_CH7 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH6_Pos (6UL) /*!< DMA_RST_IRQ_CH6 (Bit 6) */ +#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH6_Msk (0x40UL) /*!< DMA_RST_IRQ_CH6 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH5_Pos (5UL) /*!< DMA_RST_IRQ_CH5 (Bit 5) */ +#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH5_Msk (0x20UL) /*!< DMA_RST_IRQ_CH5 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH4_Pos (4UL) /*!< DMA_RST_IRQ_CH4 (Bit 4) */ +#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH4_Msk (0x10UL) /*!< DMA_RST_IRQ_CH4 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH3_Pos (3UL) /*!< DMA_RST_IRQ_CH3 (Bit 3) */ +#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH3_Msk (0x8UL) /*!< DMA_RST_IRQ_CH3 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH2_Pos (2UL) /*!< DMA_RST_IRQ_CH2 (Bit 2) */ +#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH2_Msk (0x4UL) /*!< DMA_RST_IRQ_CH2 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH1_Pos (1UL) /*!< DMA_RST_IRQ_CH1 (Bit 1) */ +#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH1_Msk (0x2UL) /*!< DMA_RST_IRQ_CH1 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH0_Pos (0UL) /*!< DMA_RST_IRQ_CH0 (Bit 0) */ +#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH0_Msk (0x1UL) /*!< DMA_RST_IRQ_CH0 (Bitfield-Mask: 0x01) */ +/* =================================================== DMA_INT_MASK_REG ==================================================== */ +#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE7_Pos (7UL) /*!< DMA_IRQ_ENABLE7 (Bit 7) */ +#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE7_Msk (0x80UL) /*!< DMA_IRQ_ENABLE7 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE6_Pos (6UL) /*!< DMA_IRQ_ENABLE6 (Bit 6) */ +#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE6_Msk (0x40UL) /*!< DMA_IRQ_ENABLE6 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE5_Pos (5UL) /*!< DMA_IRQ_ENABLE5 (Bit 5) */ +#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE5_Msk (0x20UL) /*!< DMA_IRQ_ENABLE5 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE4_Pos (4UL) /*!< DMA_IRQ_ENABLE4 (Bit 4) */ +#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE4_Msk (0x10UL) /*!< DMA_IRQ_ENABLE4 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE3_Pos (3UL) /*!< DMA_IRQ_ENABLE3 (Bit 3) */ +#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE3_Msk (0x8UL) /*!< DMA_IRQ_ENABLE3 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE2_Pos (2UL) /*!< DMA_IRQ_ENABLE2 (Bit 2) */ +#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE2_Msk (0x4UL) /*!< DMA_IRQ_ENABLE2 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE1_Pos (1UL) /*!< DMA_IRQ_ENABLE1 (Bit 1) */ +#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE1_Msk (0x2UL) /*!< DMA_IRQ_ENABLE1 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE0_Pos (0UL) /*!< DMA_IRQ_ENABLE0 (Bit 0) */ +#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE0_Msk (0x1UL) /*!< DMA_IRQ_ENABLE0 (Bitfield-Mask: 0x01) */ +/* ================================================== DMA_INT_STATUS_REG =================================================== */ +#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR7_Pos (15UL) /*!< DMA_BUS_ERR7 (Bit 15) */ +#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR7_Msk (0x8000UL) /*!< DMA_BUS_ERR7 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR6_Pos (14UL) /*!< DMA_BUS_ERR6 (Bit 14) */ +#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR6_Msk (0x4000UL) /*!< DMA_BUS_ERR6 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR5_Pos (13UL) /*!< DMA_BUS_ERR5 (Bit 13) */ +#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR5_Msk (0x2000UL) /*!< DMA_BUS_ERR5 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR4_Pos (12UL) /*!< DMA_BUS_ERR4 (Bit 12) */ +#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR4_Msk (0x1000UL) /*!< DMA_BUS_ERR4 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR3_Pos (11UL) /*!< DMA_BUS_ERR3 (Bit 11) */ +#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR3_Msk (0x800UL) /*!< DMA_BUS_ERR3 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR2_Pos (10UL) /*!< DMA_BUS_ERR2 (Bit 10) */ +#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR2_Msk (0x400UL) /*!< DMA_BUS_ERR2 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR1_Pos (9UL) /*!< DMA_BUS_ERR1 (Bit 9) */ +#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR1_Msk (0x200UL) /*!< DMA_BUS_ERR1 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR0_Pos (8UL) /*!< DMA_BUS_ERR0 (Bit 8) */ +#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR0_Msk (0x100UL) /*!< DMA_BUS_ERR0 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH7_Pos (7UL) /*!< DMA_IRQ_CH7 (Bit 7) */ +#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH7_Msk (0x80UL) /*!< DMA_IRQ_CH7 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH6_Pos (6UL) /*!< DMA_IRQ_CH6 (Bit 6) */ +#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH6_Msk (0x40UL) /*!< DMA_IRQ_CH6 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH5_Pos (5UL) /*!< DMA_IRQ_CH5 (Bit 5) */ +#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH5_Msk (0x20UL) /*!< DMA_IRQ_CH5 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH4_Pos (4UL) /*!< DMA_IRQ_CH4 (Bit 4) */ +#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH4_Msk (0x10UL) /*!< DMA_IRQ_CH4 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH3_Pos (3UL) /*!< DMA_IRQ_CH3 (Bit 3) */ +#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH3_Msk (0x8UL) /*!< DMA_IRQ_CH3 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH2_Pos (2UL) /*!< DMA_IRQ_CH2 (Bit 2) */ +#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH2_Msk (0x4UL) /*!< DMA_IRQ_CH2 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH1_Pos (1UL) /*!< DMA_IRQ_CH1 (Bit 1) */ +#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH1_Msk (0x2UL) /*!< DMA_IRQ_CH1 (Bitfield-Mask: 0x01) */ +#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH0_Pos (0UL) /*!< DMA_IRQ_CH0 (Bit 0) */ +#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH0_Msk (0x1UL) /*!< DMA_IRQ_CH0 (Bitfield-Mask: 0x01) */ +/* ==================================================== DMA_REQ_MUX_REG ==================================================== */ +#define DMA_DMA_REQ_MUX_REG_DMA67_SEL_Pos (12UL) /*!< DMA67_SEL (Bit 12) */ +#define DMA_DMA_REQ_MUX_REG_DMA67_SEL_Msk (0xf000UL) /*!< DMA67_SEL (Bitfield-Mask: 0x0f) */ +#define DMA_DMA_REQ_MUX_REG_DMA45_SEL_Pos (8UL) /*!< DMA45_SEL (Bit 8) */ +#define DMA_DMA_REQ_MUX_REG_DMA45_SEL_Msk (0xf00UL) /*!< DMA45_SEL (Bitfield-Mask: 0x0f) */ +#define DMA_DMA_REQ_MUX_REG_DMA23_SEL_Pos (4UL) /*!< DMA23_SEL (Bit 4) */ +#define DMA_DMA_REQ_MUX_REG_DMA23_SEL_Msk (0xf0UL) /*!< DMA23_SEL (Bitfield-Mask: 0x0f) */ +#define DMA_DMA_REQ_MUX_REG_DMA01_SEL_Pos (0UL) /*!< DMA01_SEL (Bit 0) */ +#define DMA_DMA_REQ_MUX_REG_DMA01_SEL_Msk (0xfUL) /*!< DMA01_SEL (Bitfield-Mask: 0x0f) */ + + +/* =========================================================================================================================== */ +/* ================ DW ================ */ +/* =========================================================================================================================== */ + +/* =================================================== AHB_DMA_CCLM1_REG =================================================== */ +#define DW_AHB_DMA_CCLM1_REG_AHB_DMA_CCLM_Pos (0UL) /*!< AHB_DMA_CCLM (Bit 0) */ +#define DW_AHB_DMA_CCLM1_REG_AHB_DMA_CCLM_Msk (0xffffUL) /*!< AHB_DMA_CCLM (Bitfield-Mask: 0xffff) */ +/* =================================================== AHB_DMA_CCLM2_REG =================================================== */ +#define DW_AHB_DMA_CCLM2_REG_AHB_DMA_CCLM_Pos (0UL) /*!< AHB_DMA_CCLM (Bit 0) */ +#define DW_AHB_DMA_CCLM2_REG_AHB_DMA_CCLM_Msk (0xffffUL) /*!< AHB_DMA_CCLM (Bitfield-Mask: 0xffff) */ +/* =================================================== AHB_DMA_CCLM3_REG =================================================== */ +#define DW_AHB_DMA_CCLM3_REG_AHB_DMA_CCLM_Pos (0UL) /*!< AHB_DMA_CCLM (Bit 0) */ +#define DW_AHB_DMA_CCLM3_REG_AHB_DMA_CCLM_Msk (0xffffUL) /*!< AHB_DMA_CCLM (Bitfield-Mask: 0xffff) */ +/* =================================================== AHB_DMA_CCLM4_REG =================================================== */ +#define DW_AHB_DMA_CCLM4_REG_AHB_DMA_CCLM_Pos (0UL) /*!< AHB_DMA_CCLM (Bit 0) */ +#define DW_AHB_DMA_CCLM4_REG_AHB_DMA_CCLM_Msk (0xffffUL) /*!< AHB_DMA_CCLM (Bitfield-Mask: 0xffff) */ +/* ================================================ AHB_DMA_DFLT_MASTER_REG ================================================ */ +#define DW_AHB_DMA_DFLT_MASTER_REG_AHB_DMA_DFLT_MASTER_Pos (0UL) /*!< AHB_DMA_DFLT_MASTER (Bit 0) */ +#define DW_AHB_DMA_DFLT_MASTER_REG_AHB_DMA_DFLT_MASTER_Msk (0xfUL) /*!< AHB_DMA_DFLT_MASTER (Bitfield-Mask: 0x0f) */ +/* ==================================================== AHB_DMA_PL1_REG ==================================================== */ +#define DW_AHB_DMA_PL1_REG_AHB_DMA_PL1_Pos (0UL) /*!< AHB_DMA_PL1 (Bit 0) */ +#define DW_AHB_DMA_PL1_REG_AHB_DMA_PL1_Msk (0xfUL) /*!< AHB_DMA_PL1 (Bitfield-Mask: 0x0f) */ +/* ==================================================== AHB_DMA_PL2_REG ==================================================== */ +#define DW_AHB_DMA_PL2_REG_AHB_DMA_PL2_Pos (0UL) /*!< AHB_DMA_PL2 (Bit 0) */ +#define DW_AHB_DMA_PL2_REG_AHB_DMA_PL2_Msk (0xfUL) /*!< AHB_DMA_PL2 (Bitfield-Mask: 0x0f) */ +/* ==================================================== AHB_DMA_PL3_REG ==================================================== */ +#define DW_AHB_DMA_PL3_REG_AHB_DMA_PL3_Pos (0UL) /*!< AHB_DMA_PL3 (Bit 0) */ +#define DW_AHB_DMA_PL3_REG_AHB_DMA_PL3_Msk (0xfUL) /*!< AHB_DMA_PL3 (Bitfield-Mask: 0x0f) */ +/* ==================================================== AHB_DMA_PL4_REG ==================================================== */ +#define DW_AHB_DMA_PL4_REG_AHB_DMA_PL4_Pos (0UL) /*!< AHB_DMA_PL4 (Bit 0) */ +#define DW_AHB_DMA_PL4_REG_AHB_DMA_PL4_Msk (0xfUL) /*!< AHB_DMA_PL4 (Bitfield-Mask: 0x0f) */ +/* ==================================================== AHB_DMA_TCL_REG ==================================================== */ +#define DW_AHB_DMA_TCL_REG_AHB_DMA_TCL_Pos (0UL) /*!< AHB_DMA_TCL (Bit 0) */ +#define DW_AHB_DMA_TCL_REG_AHB_DMA_TCL_Msk (0xffffUL) /*!< AHB_DMA_TCL (Bitfield-Mask: 0xffff) */ +/* ================================================== AHB_DMA_VERSION_REG ================================================== */ +#define DW_AHB_DMA_VERSION_REG_AHB_DMA_VERSION_Pos (0UL) /*!< AHB_DMA_VERSION (Bit 0) */ +#define DW_AHB_DMA_VERSION_REG_AHB_DMA_VERSION_Msk (0xffffffffUL) /*!< AHB_DMA_VERSION (Bitfield-Mask: 0xffffffff) */ +/* =================================================== AHB_DMA_WTEN_REG ==================================================== */ +#define DW_AHB_DMA_WTEN_REG_AHB_DMA_WTEN_Pos (0UL) /*!< AHB_DMA_WTEN (Bit 0) */ +#define DW_AHB_DMA_WTEN_REG_AHB_DMA_WTEN_Msk (0x1UL) /*!< AHB_DMA_WTEN (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ GPADC ================ */ +/* =========================================================================================================================== */ + +/* ================================================= GP_ADC_CLEAR_INT_REG ================================================== */ +#define GPADC_GP_ADC_CLEAR_INT_REG_GP_ADC_CLR_INT_Pos (0UL) /*!< GP_ADC_CLR_INT (Bit 0) */ +#define GPADC_GP_ADC_CLEAR_INT_REG_GP_ADC_CLR_INT_Msk (0xffffUL) /*!< GP_ADC_CLR_INT (Bitfield-Mask: 0xffff) */ +/* =================================================== GP_ADC_CTRL2_REG ==================================================== */ +#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_STORE_DEL_Pos (12UL) /*!< GP_ADC_STORE_DEL (Bit 12) */ +#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_STORE_DEL_Msk (0xf000UL) /*!< GP_ADC_STORE_DEL (Bitfield-Mask: 0x0f) */ +#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_SMPL_TIME_Pos (8UL) /*!< GP_ADC_SMPL_TIME (Bit 8) */ +#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_SMPL_TIME_Msk (0xf00UL) /*!< GP_ADC_SMPL_TIME (Bitfield-Mask: 0x0f) */ +#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_CONV_NRS_Pos (5UL) /*!< GP_ADC_CONV_NRS (Bit 5) */ +#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_CONV_NRS_Msk (0xe0UL) /*!< GP_ADC_CONV_NRS (Bitfield-Mask: 0x07) */ +#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_DMA_EN_Pos (3UL) /*!< GP_ADC_DMA_EN (Bit 3) */ +#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_DMA_EN_Msk (0x8UL) /*!< GP_ADC_DMA_EN (Bitfield-Mask: 0x01) */ +#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_I20U_Pos (2UL) /*!< GP_ADC_I20U (Bit 2) */ +#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_I20U_Msk (0x4UL) /*!< GP_ADC_I20U (Bitfield-Mask: 0x01) */ +#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_IDYN_Pos (1UL) /*!< GP_ADC_IDYN (Bit 1) */ +#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_IDYN_Msk (0x2UL) /*!< GP_ADC_IDYN (Bitfield-Mask: 0x01) */ +#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_ATTN3X_Pos (0UL) /*!< GP_ADC_ATTN3X (Bit 0) */ +#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_ATTN3X_Msk (0x1UL) /*!< GP_ADC_ATTN3X (Bitfield-Mask: 0x01) */ +/* =================================================== GP_ADC_CTRL3_REG ==================================================== */ +#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_INTERVAL_Pos (8UL) /*!< GP_ADC_INTERVAL (Bit 8) */ +#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_INTERVAL_Msk (0xff00UL) /*!< GP_ADC_INTERVAL (Bitfield-Mask: 0xff) */ +#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_EN_DEL_Pos (0UL) /*!< GP_ADC_EN_DEL (Bit 0) */ +#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_EN_DEL_Msk (0xffUL) /*!< GP_ADC_EN_DEL (Bitfield-Mask: 0xff) */ +/* ==================================================== GP_ADC_CTRL_REG ==================================================== */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_DIFF_TEMP_EN_Pos (18UL) /*!< GP_ADC_DIFF_TEMP_EN (Bit 18) */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_DIFF_TEMP_EN_Msk (0x40000UL) /*!< GP_ADC_DIFF_TEMP_EN (Bitfield-Mask: 0x01) */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_DIFF_TEMP_SEL_Pos (16UL) /*!< GP_ADC_DIFF_TEMP_SEL (Bit 16) */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_DIFF_TEMP_SEL_Msk (0x30000UL) /*!< GP_ADC_DIFF_TEMP_SEL (Bitfield-Mask: 0x03) */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_LDO_ZERO_Pos (15UL) /*!< GP_ADC_LDO_ZERO (Bit 15) */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_LDO_ZERO_Msk (0x8000UL) /*!< GP_ADC_LDO_ZERO (Bitfield-Mask: 0x01) */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CHOP_Pos (14UL) /*!< GP_ADC_CHOP (Bit 14) */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CHOP_Msk (0x4000UL) /*!< GP_ADC_CHOP (Bitfield-Mask: 0x01) */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SIGN_Pos (13UL) /*!< GP_ADC_SIGN (Bit 13) */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SIGN_Msk (0x2000UL) /*!< GP_ADC_SIGN (Bitfield-Mask: 0x01) */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SEL_Pos (8UL) /*!< GP_ADC_SEL (Bit 8) */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SEL_Msk (0x1f00UL) /*!< GP_ADC_SEL (Bitfield-Mask: 0x1f) */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MUTE_Pos (7UL) /*!< GP_ADC_MUTE (Bit 7) */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MUTE_Msk (0x80UL) /*!< GP_ADC_MUTE (Bitfield-Mask: 0x01) */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SE_Pos (6UL) /*!< GP_ADC_SE (Bit 6) */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SE_Msk (0x40UL) /*!< GP_ADC_SE (Bitfield-Mask: 0x01) */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MINT_Pos (5UL) /*!< GP_ADC_MINT (Bit 5) */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MINT_Msk (0x20UL) /*!< GP_ADC_MINT (Bitfield-Mask: 0x01) */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_INT_Pos (4UL) /*!< GP_ADC_INT (Bit 4) */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_INT_Msk (0x10UL) /*!< GP_ADC_INT (Bitfield-Mask: 0x01) */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CLK_SEL_Pos (3UL) /*!< GP_ADC_CLK_SEL (Bit 3) */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CLK_SEL_Msk (0x8UL) /*!< GP_ADC_CLK_SEL (Bitfield-Mask: 0x01) */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CONT_Pos (2UL) /*!< GP_ADC_CONT (Bit 2) */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CONT_Msk (0x4UL) /*!< GP_ADC_CONT (Bitfield-Mask: 0x01) */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_START_Pos (1UL) /*!< GP_ADC_START (Bit 1) */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_START_Msk (0x2UL) /*!< GP_ADC_START (Bitfield-Mask: 0x01) */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_EN_Pos (0UL) /*!< GP_ADC_EN (Bit 0) */ +#define GPADC_GP_ADC_CTRL_REG_GP_ADC_EN_Msk (0x1UL) /*!< GP_ADC_EN (Bitfield-Mask: 0x01) */ +/* ==================================================== GP_ADC_OFFN_REG ==================================================== */ +#define GPADC_GP_ADC_OFFN_REG_GP_ADC_OFFN_Pos (0UL) /*!< GP_ADC_OFFN (Bit 0) */ +#define GPADC_GP_ADC_OFFN_REG_GP_ADC_OFFN_Msk (0x3ffUL) /*!< GP_ADC_OFFN (Bitfield-Mask: 0x3ff) */ +/* ==================================================== GP_ADC_OFFP_REG ==================================================== */ +#define GPADC_GP_ADC_OFFP_REG_GP_ADC_OFFP_Pos (0UL) /*!< GP_ADC_OFFP (Bit 0) */ +#define GPADC_GP_ADC_OFFP_REG_GP_ADC_OFFP_Msk (0x3ffUL) /*!< GP_ADC_OFFP (Bitfield-Mask: 0x3ff) */ +/* =================================================== GP_ADC_RESULT_REG =================================================== */ +#define GPADC_GP_ADC_RESULT_REG_GP_ADC_VAL_Pos (0UL) /*!< GP_ADC_VAL (Bit 0) */ +#define GPADC_GP_ADC_RESULT_REG_GP_ADC_VAL_Msk (0xffffUL) /*!< GP_ADC_VAL (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + +/* =================================================== GPIO_CLK_SEL_REG ==================================================== */ +#define GPIO_GPIO_CLK_SEL_REG_DIVN_OUTPUT_EN_Pos (9UL) /*!< DIVN_OUTPUT_EN (Bit 9) */ +#define GPIO_GPIO_CLK_SEL_REG_DIVN_OUTPUT_EN_Msk (0x200UL) /*!< DIVN_OUTPUT_EN (Bitfield-Mask: 0x01) */ +#define GPIO_GPIO_CLK_SEL_REG_RC32M_OUTPUT_EN_Pos (8UL) /*!< RC32M_OUTPUT_EN (Bit 8) */ +#define GPIO_GPIO_CLK_SEL_REG_RC32M_OUTPUT_EN_Msk (0x100UL) /*!< RC32M_OUTPUT_EN (Bitfield-Mask: 0x01) */ +#define GPIO_GPIO_CLK_SEL_REG_XTAL32M_OUTPUT_EN_Pos (7UL) /*!< XTAL32M_OUTPUT_EN (Bit 7) */ +#define GPIO_GPIO_CLK_SEL_REG_XTAL32M_OUTPUT_EN_Msk (0x80UL) /*!< XTAL32M_OUTPUT_EN (Bitfield-Mask: 0x01) */ +#define GPIO_GPIO_CLK_SEL_REG_RCX_OUTPUT_EN_Pos (6UL) /*!< RCX_OUTPUT_EN (Bit 6) */ +#define GPIO_GPIO_CLK_SEL_REG_RCX_OUTPUT_EN_Msk (0x40UL) /*!< RCX_OUTPUT_EN (Bitfield-Mask: 0x01) */ +#define GPIO_GPIO_CLK_SEL_REG_RC32K_OUTPUT_EN_Pos (5UL) /*!< RC32K_OUTPUT_EN (Bit 5) */ +#define GPIO_GPIO_CLK_SEL_REG_RC32K_OUTPUT_EN_Msk (0x20UL) /*!< RC32K_OUTPUT_EN (Bitfield-Mask: 0x01) */ +#define GPIO_GPIO_CLK_SEL_REG_XTAL32K_OUTPUT_EN_Pos (4UL) /*!< XTAL32K_OUTPUT_EN (Bit 4) */ +#define GPIO_GPIO_CLK_SEL_REG_XTAL32K_OUTPUT_EN_Msk (0x10UL) /*!< XTAL32K_OUTPUT_EN (Bitfield-Mask: 0x01) */ +#define GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_EN_Pos (3UL) /*!< FUNC_CLOCK_EN (Bit 3) */ +#define GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_EN_Msk (0x8UL) /*!< FUNC_CLOCK_EN (Bitfield-Mask: 0x01) */ +#define GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_SEL_Pos (0UL) /*!< FUNC_CLOCK_SEL (Bit 0) */ +#define GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_SEL_Msk (0x7UL) /*!< FUNC_CLOCK_SEL (Bitfield-Mask: 0x07) */ +/* ==================================================== P0_00_MODE_REG ===================================================== */ +#define GPIO_P0_00_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_00_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_00_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_00_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_00_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_00_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_01_MODE_REG ===================================================== */ +#define GPIO_P0_01_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_01_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_01_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_01_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_01_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_01_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_02_MODE_REG ===================================================== */ +#define GPIO_P0_02_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_02_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_02_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_02_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_02_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_02_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_03_MODE_REG ===================================================== */ +#define GPIO_P0_03_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_03_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_03_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_03_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_03_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_03_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_04_MODE_REG ===================================================== */ +#define GPIO_P0_04_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_04_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_04_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_04_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_04_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_04_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_05_MODE_REG ===================================================== */ +#define GPIO_P0_05_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_05_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_05_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_05_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_05_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_05_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_06_MODE_REG ===================================================== */ +#define GPIO_P0_06_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_06_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_06_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_06_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_06_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_06_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_07_MODE_REG ===================================================== */ +#define GPIO_P0_07_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_07_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_07_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_07_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_07_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_07_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_08_MODE_REG ===================================================== */ +#define GPIO_P0_08_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_08_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_08_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_08_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_08_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_08_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_09_MODE_REG ===================================================== */ +#define GPIO_P0_09_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_09_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_09_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_09_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_09_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_09_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_10_MODE_REG ===================================================== */ +#define GPIO_P0_10_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_10_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_10_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_10_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_10_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_10_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_11_MODE_REG ===================================================== */ +#define GPIO_P0_11_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_11_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_11_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_11_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_11_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_11_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_12_MODE_REG ===================================================== */ +#define GPIO_P0_12_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_12_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_12_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_12_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_12_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_12_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_13_MODE_REG ===================================================== */ +#define GPIO_P0_13_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_13_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_13_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_13_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_13_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_13_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_14_MODE_REG ===================================================== */ +#define GPIO_P0_14_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_14_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_14_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_14_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_14_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_14_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_15_MODE_REG ===================================================== */ +#define GPIO_P0_15_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_15_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_15_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_15_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_15_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_15_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_16_MODE_REG ===================================================== */ +#define GPIO_P0_16_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_16_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_16_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_16_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_16_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_16_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_17_MODE_REG ===================================================== */ +#define GPIO_P0_17_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_17_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_17_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_17_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_17_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_17_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_18_MODE_REG ===================================================== */ +#define GPIO_P0_18_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_18_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_18_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_18_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_18_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_18_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_19_MODE_REG ===================================================== */ +#define GPIO_P0_19_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_19_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_19_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_19_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_19_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_19_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_20_MODE_REG ===================================================== */ +#define GPIO_P0_20_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_20_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_20_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_20_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_20_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_20_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_21_MODE_REG ===================================================== */ +#define GPIO_P0_21_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_21_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_21_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_21_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_21_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_21_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_22_MODE_REG ===================================================== */ +#define GPIO_P0_22_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_22_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_22_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_22_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_22_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_22_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_23_MODE_REG ===================================================== */ +#define GPIO_P0_23_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_23_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_23_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_23_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_23_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_23_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_24_MODE_REG ===================================================== */ +#define GPIO_P0_24_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_24_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_24_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_24_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_24_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_24_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_25_MODE_REG ===================================================== */ +#define GPIO_P0_25_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_25_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_25_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_25_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_25_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_25_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_26_MODE_REG ===================================================== */ +#define GPIO_P0_26_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_26_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_26_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_26_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_26_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_26_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_27_MODE_REG ===================================================== */ +#define GPIO_P0_27_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_27_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_27_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_27_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_27_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_27_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_28_MODE_REG ===================================================== */ +#define GPIO_P0_28_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_28_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_28_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_28_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_28_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_28_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_29_MODE_REG ===================================================== */ +#define GPIO_P0_29_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_29_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_29_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_29_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_29_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_29_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_30_MODE_REG ===================================================== */ +#define GPIO_P0_30_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_30_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_30_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_30_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_30_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_30_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P0_31_MODE_REG ===================================================== */ +#define GPIO_P0_31_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P0_31_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P0_31_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P0_31_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P0_31_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P0_31_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ====================================================== P0_DATA_REG ====================================================== */ +#define GPIO_P0_DATA_REG_P0_DATA_Pos (0UL) /*!< P0_DATA (Bit 0) */ +#define GPIO_P0_DATA_REG_P0_DATA_Msk (0xffffffffUL) /*!< P0_DATA (Bitfield-Mask: 0xffffffff) */ +/* ================================================== P0_PADPWR_CTRL_REG =================================================== */ +#define GPIO_P0_PADPWR_CTRL_REG_P0_OUT_CTRL_Pos (6UL) /*!< P0_OUT_CTRL (Bit 6) */ +#define GPIO_P0_PADPWR_CTRL_REG_P0_OUT_CTRL_Msk (0xffffffc0UL) /*!< P0_OUT_CTRL (Bitfield-Mask: 0x3ffffff) */ +/* =================================================== P0_RESET_DATA_REG =================================================== */ +#define GPIO_P0_RESET_DATA_REG_P0_RESET_Pos (0UL) /*!< P0_RESET (Bit 0) */ +#define GPIO_P0_RESET_DATA_REG_P0_RESET_Msk (0xffffffffUL) /*!< P0_RESET (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== P0_SET_DATA_REG ==================================================== */ +#define GPIO_P0_SET_DATA_REG_P0_SET_Pos (0UL) /*!< P0_SET (Bit 0) */ +#define GPIO_P0_SET_DATA_REG_P0_SET_Msk (0xffffffffUL) /*!< P0_SET (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== P1_00_MODE_REG ===================================================== */ +#define GPIO_P1_00_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P1_00_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P1_00_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P1_00_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P1_00_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P1_00_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P1_01_MODE_REG ===================================================== */ +#define GPIO_P1_01_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P1_01_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P1_01_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P1_01_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P1_01_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P1_01_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P1_02_MODE_REG ===================================================== */ +#define GPIO_P1_02_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P1_02_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P1_02_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P1_02_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P1_02_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P1_02_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P1_03_MODE_REG ===================================================== */ +#define GPIO_P1_03_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P1_03_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P1_03_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P1_03_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P1_03_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P1_03_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P1_04_MODE_REG ===================================================== */ +#define GPIO_P1_04_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P1_04_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P1_04_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P1_04_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P1_04_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P1_04_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P1_05_MODE_REG ===================================================== */ +#define GPIO_P1_05_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P1_05_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P1_05_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P1_05_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P1_05_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P1_05_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P1_06_MODE_REG ===================================================== */ +#define GPIO_P1_06_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P1_06_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P1_06_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P1_06_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P1_06_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P1_06_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P1_07_MODE_REG ===================================================== */ +#define GPIO_P1_07_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P1_07_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P1_07_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P1_07_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P1_07_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P1_07_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P1_08_MODE_REG ===================================================== */ +#define GPIO_P1_08_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P1_08_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P1_08_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P1_08_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P1_08_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P1_08_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P1_09_MODE_REG ===================================================== */ +#define GPIO_P1_09_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P1_09_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P1_09_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P1_09_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P1_09_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P1_09_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P1_10_MODE_REG ===================================================== */ +#define GPIO_P1_10_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P1_10_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P1_10_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P1_10_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P1_10_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P1_10_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P1_11_MODE_REG ===================================================== */ +#define GPIO_P1_11_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P1_11_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P1_11_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P1_11_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P1_11_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P1_11_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P1_12_MODE_REG ===================================================== */ +#define GPIO_P1_12_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P1_12_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P1_12_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P1_12_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P1_12_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P1_12_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P1_13_MODE_REG ===================================================== */ +#define GPIO_P1_13_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P1_13_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P1_13_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P1_13_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P1_13_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P1_13_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P1_14_MODE_REG ===================================================== */ +#define GPIO_P1_14_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P1_14_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P1_14_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P1_14_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P1_14_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P1_14_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P1_15_MODE_REG ===================================================== */ +#define GPIO_P1_15_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P1_15_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P1_15_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P1_15_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P1_15_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P1_15_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P1_16_MODE_REG ===================================================== */ +#define GPIO_P1_16_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P1_16_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P1_16_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P1_16_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P1_16_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P1_16_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P1_17_MODE_REG ===================================================== */ +#define GPIO_P1_17_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P1_17_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P1_17_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P1_17_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P1_17_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P1_17_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P1_18_MODE_REG ===================================================== */ +#define GPIO_P1_18_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P1_18_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P1_18_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P1_18_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P1_18_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P1_18_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P1_19_MODE_REG ===================================================== */ +#define GPIO_P1_19_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P1_19_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P1_19_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P1_19_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P1_19_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P1_19_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P1_20_MODE_REG ===================================================== */ +#define GPIO_P1_20_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P1_20_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P1_20_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P1_20_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P1_20_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P1_20_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P1_21_MODE_REG ===================================================== */ +#define GPIO_P1_21_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P1_21_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P1_21_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P1_21_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P1_21_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P1_21_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ==================================================== P1_22_MODE_REG ===================================================== */ +#define GPIO_P1_22_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */ +#define GPIO_P1_22_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */ +#define GPIO_P1_22_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */ +#define GPIO_P1_22_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */ +#define GPIO_P1_22_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define GPIO_P1_22_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */ +/* ====================================================== P1_DATA_REG ====================================================== */ +#define GPIO_P1_DATA_REG_P1_DATA_Pos (0UL) /*!< P1_DATA (Bit 0) */ +#define GPIO_P1_DATA_REG_P1_DATA_Msk (0x7fffffUL) /*!< P1_DATA (Bitfield-Mask: 0x7fffff) */ +/* ================================================== P1_PADPWR_CTRL_REG =================================================== */ +#define GPIO_P1_PADPWR_CTRL_REG_P1_OUT_CTRL_Pos (0UL) /*!< P1_OUT_CTRL (Bit 0) */ +#define GPIO_P1_PADPWR_CTRL_REG_P1_OUT_CTRL_Msk (0x7fffffUL) /*!< P1_OUT_CTRL (Bitfield-Mask: 0x7fffff) */ +/* =================================================== P1_RESET_DATA_REG =================================================== */ +#define GPIO_P1_RESET_DATA_REG_P1_RESET_Pos (0UL) /*!< P1_RESET (Bit 0) */ +#define GPIO_P1_RESET_DATA_REG_P1_RESET_Msk (0x7fffffUL) /*!< P1_RESET (Bitfield-Mask: 0x7fffff) */ +/* ==================================================== P1_SET_DATA_REG ==================================================== */ +#define GPIO_P1_SET_DATA_REG_P1_SET_Pos (0UL) /*!< P1_SET (Bit 0) */ +#define GPIO_P1_SET_DATA_REG_P1_SET_Msk (0x7fffffUL) /*!< P1_SET (Bitfield-Mask: 0x7fffff) */ +/* =================================================== PAD_WEAK_CTRL_REG =================================================== */ +#define GPIO_PAD_WEAK_CTRL_REG_P1_09_LOWDRV_Pos (12UL) /*!< P1_09_LOWDRV (Bit 12) */ +#define GPIO_PAD_WEAK_CTRL_REG_P1_09_LOWDRV_Msk (0x1000UL) /*!< P1_09_LOWDRV (Bitfield-Mask: 0x01) */ +#define GPIO_PAD_WEAK_CTRL_REG_P1_06_LOWDRV_Pos (11UL) /*!< P1_06_LOWDRV (Bit 11) */ +#define GPIO_PAD_WEAK_CTRL_REG_P1_06_LOWDRV_Msk (0x800UL) /*!< P1_06_LOWDRV (Bitfield-Mask: 0x01) */ +#define GPIO_PAD_WEAK_CTRL_REG_P1_02_LOWDRV_Pos (10UL) /*!< P1_02_LOWDRV (Bit 10) */ +#define GPIO_PAD_WEAK_CTRL_REG_P1_02_LOWDRV_Msk (0x400UL) /*!< P1_02_LOWDRV (Bitfield-Mask: 0x01) */ +#define GPIO_PAD_WEAK_CTRL_REG_P1_01_LOWDRV_Pos (9UL) /*!< P1_01_LOWDRV (Bit 9) */ +#define GPIO_PAD_WEAK_CTRL_REG_P1_01_LOWDRV_Msk (0x200UL) /*!< P1_01_LOWDRV (Bitfield-Mask: 0x01) */ +#define GPIO_PAD_WEAK_CTRL_REG_P1_00_LOWDRV_Pos (8UL) /*!< P1_00_LOWDRV (Bit 8) */ +#define GPIO_PAD_WEAK_CTRL_REG_P1_00_LOWDRV_Msk (0x100UL) /*!< P1_00_LOWDRV (Bitfield-Mask: 0x01) */ +#define GPIO_PAD_WEAK_CTRL_REG_P0_27_LOWDRV_Pos (7UL) /*!< P0_27_LOWDRV (Bit 7) */ +#define GPIO_PAD_WEAK_CTRL_REG_P0_27_LOWDRV_Msk (0x80UL) /*!< P0_27_LOWDRV (Bitfield-Mask: 0x01) */ +#define GPIO_PAD_WEAK_CTRL_REG_P0_26_LOWDRV_Pos (6UL) /*!< P0_26_LOWDRV (Bit 6) */ +#define GPIO_PAD_WEAK_CTRL_REG_P0_26_LOWDRV_Msk (0x40UL) /*!< P0_26_LOWDRV (Bitfield-Mask: 0x01) */ +#define GPIO_PAD_WEAK_CTRL_REG_P0_25_LOWDRV_Pos (5UL) /*!< P0_25_LOWDRV (Bit 5) */ +#define GPIO_PAD_WEAK_CTRL_REG_P0_25_LOWDRV_Msk (0x20UL) /*!< P0_25_LOWDRV (Bitfield-Mask: 0x01) */ +#define GPIO_PAD_WEAK_CTRL_REG_P0_18_LOWDRV_Pos (4UL) /*!< P0_18_LOWDRV (Bit 4) */ +#define GPIO_PAD_WEAK_CTRL_REG_P0_18_LOWDRV_Msk (0x10UL) /*!< P0_18_LOWDRV (Bitfield-Mask: 0x01) */ +#define GPIO_PAD_WEAK_CTRL_REG_P0_17_LOWDRV_Pos (3UL) /*!< P0_17_LOWDRV (Bit 3) */ +#define GPIO_PAD_WEAK_CTRL_REG_P0_17_LOWDRV_Msk (0x8UL) /*!< P0_17_LOWDRV (Bitfield-Mask: 0x01) */ +#define GPIO_PAD_WEAK_CTRL_REG_P0_16_LOWDRV_Pos (2UL) /*!< P0_16_LOWDRV (Bit 2) */ +#define GPIO_PAD_WEAK_CTRL_REG_P0_16_LOWDRV_Msk (0x4UL) /*!< P0_16_LOWDRV (Bitfield-Mask: 0x01) */ +#define GPIO_PAD_WEAK_CTRL_REG_P0_07_LOWDRV_Pos (1UL) /*!< P0_07_LOWDRV (Bit 1) */ +#define GPIO_PAD_WEAK_CTRL_REG_P0_07_LOWDRV_Msk (0x2UL) /*!< P0_07_LOWDRV (Bitfield-Mask: 0x01) */ +#define GPIO_PAD_WEAK_CTRL_REG_P0_06_LOWDRV_Pos (0UL) /*!< P0_06_LOWDRV (Bit 0) */ +#define GPIO_PAD_WEAK_CTRL_REG_P0_06_LOWDRV_Msk (0x1UL) /*!< P0_06_LOWDRV (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ GPREG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= DEBUG_REG ======================================================= */ +#define GPREG_DEBUG_REG_CROSS_CPU_HALT_SENSITIVITY_Pos (8UL) /*!< CROSS_CPU_HALT_SENSITIVITY (Bit 8) */ +#define GPREG_DEBUG_REG_CROSS_CPU_HALT_SENSITIVITY_Msk (0x100UL) /*!< CROSS_CPU_HALT_SENSITIVITY (Bitfield-Mask: 0x01) */ +#define GPREG_DEBUG_REG_SYS_CPUWAIT_ON_JTAG_Pos (7UL) /*!< SYS_CPUWAIT_ON_JTAG (Bit 7) */ +#define GPREG_DEBUG_REG_SYS_CPUWAIT_ON_JTAG_Msk (0x80UL) /*!< SYS_CPUWAIT_ON_JTAG (Bitfield-Mask: 0x01) */ +#define GPREG_DEBUG_REG_SYS_CPUWAIT_Pos (6UL) /*!< SYS_CPUWAIT (Bit 6) */ +#define GPREG_DEBUG_REG_SYS_CPUWAIT_Msk (0x40UL) /*!< SYS_CPUWAIT (Bitfield-Mask: 0x01) */ +#define GPREG_DEBUG_REG_CMAC_CPU_IS_HALTED_Pos (5UL) /*!< CMAC_CPU_IS_HALTED (Bit 5) */ +#define GPREG_DEBUG_REG_CMAC_CPU_IS_HALTED_Msk (0x20UL) /*!< CMAC_CPU_IS_HALTED (Bitfield-Mask: 0x01) */ +#define GPREG_DEBUG_REG_SYS_CPU_IS_HALTED_Pos (4UL) /*!< SYS_CPU_IS_HALTED (Bit 4) */ +#define GPREG_DEBUG_REG_SYS_CPU_IS_HALTED_Msk (0x10UL) /*!< SYS_CPU_IS_HALTED (Bitfield-Mask: 0x01) */ +#define GPREG_DEBUG_REG_HALT_CMAC_SYS_CPU_EN_Pos (3UL) /*!< HALT_CMAC_SYS_CPU_EN (Bit 3) */ +#define GPREG_DEBUG_REG_HALT_CMAC_SYS_CPU_EN_Msk (0x8UL) /*!< HALT_CMAC_SYS_CPU_EN (Bitfield-Mask: 0x01) */ +#define GPREG_DEBUG_REG_HALT_SYS_CMAC_CPU_EN_Pos (2UL) /*!< HALT_SYS_CMAC_CPU_EN (Bit 2) */ +#define GPREG_DEBUG_REG_HALT_SYS_CMAC_CPU_EN_Msk (0x4UL) /*!< HALT_SYS_CMAC_CPU_EN (Bitfield-Mask: 0x01) */ +#define GPREG_DEBUG_REG_CMAC_CPU_FREEZE_EN_Pos (1UL) /*!< CMAC_CPU_FREEZE_EN (Bit 1) */ +#define GPREG_DEBUG_REG_CMAC_CPU_FREEZE_EN_Msk (0x2UL) /*!< CMAC_CPU_FREEZE_EN (Bitfield-Mask: 0x01) */ +#define GPREG_DEBUG_REG_SYS_CPU_FREEZE_EN_Pos (0UL) /*!< SYS_CPU_FREEZE_EN (Bit 0) */ +#define GPREG_DEBUG_REG_SYS_CPU_FREEZE_EN_Msk (0x1UL) /*!< SYS_CPU_FREEZE_EN (Bitfield-Mask: 0x01) */ +/* ==================================================== GP_CONTROL_REG ===================================================== */ +#define GPREG_GP_CONTROL_REG_CMAC_H2H_BRIDGE_BYPASS_Pos (1UL) /*!< CMAC_H2H_BRIDGE_BYPASS (Bit 1) */ +#define GPREG_GP_CONTROL_REG_CMAC_H2H_BRIDGE_BYPASS_Msk (0x2UL) /*!< CMAC_H2H_BRIDGE_BYPASS (Bitfield-Mask: 0x01) */ +/* ===================================================== GP_STATUS_REG ===================================================== */ +#define GPREG_GP_STATUS_REG_CAL_PHASE_Pos (0UL) /*!< CAL_PHASE (Bit 0) */ +#define GPREG_GP_STATUS_REG_CAL_PHASE_Msk (0x1UL) /*!< CAL_PHASE (Bitfield-Mask: 0x01) */ +/* =================================================== RESET_FREEZE_REG ==================================================== */ +#define GPREG_RESET_FREEZE_REG_FRZ_CMAC_WDOG_Pos (10UL) /*!< FRZ_CMAC_WDOG (Bit 10) */ +#define GPREG_RESET_FREEZE_REG_FRZ_CMAC_WDOG_Msk (0x400UL) /*!< FRZ_CMAC_WDOG (Bitfield-Mask: 0x01) */ +#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM4_Pos (9UL) /*!< FRZ_SWTIM4 (Bit 9) */ +#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM4_Msk (0x200UL) /*!< FRZ_SWTIM4 (Bitfield-Mask: 0x01) */ +#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM3_Pos (8UL) /*!< FRZ_SWTIM3 (Bit 8) */ +#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM3_Msk (0x100UL) /*!< FRZ_SWTIM3 (Bitfield-Mask: 0x01) */ +#define GPREG_RESET_FREEZE_REG_FRZ_PWMLED_Pos (7UL) /*!< FRZ_PWMLED (Bit 7) */ +#define GPREG_RESET_FREEZE_REG_FRZ_PWMLED_Msk (0x80UL) /*!< FRZ_PWMLED (Bitfield-Mask: 0x01) */ +#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM2_Pos (6UL) /*!< FRZ_SWTIM2 (Bit 6) */ +#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM2_Msk (0x40UL) /*!< FRZ_SWTIM2 (Bitfield-Mask: 0x01) */ +#define GPREG_RESET_FREEZE_REG_FRZ_DMA_Pos (5UL) /*!< FRZ_DMA (Bit 5) */ +#define GPREG_RESET_FREEZE_REG_FRZ_DMA_Msk (0x20UL) /*!< FRZ_DMA (Bitfield-Mask: 0x01) */ +#define GPREG_RESET_FREEZE_REG_FRZ_USB_Pos (4UL) /*!< FRZ_USB (Bit 4) */ +#define GPREG_RESET_FREEZE_REG_FRZ_USB_Msk (0x10UL) /*!< FRZ_USB (Bitfield-Mask: 0x01) */ +#define GPREG_RESET_FREEZE_REG_FRZ_SYS_WDOG_Pos (3UL) /*!< FRZ_SYS_WDOG (Bit 3) */ +#define GPREG_RESET_FREEZE_REG_FRZ_SYS_WDOG_Msk (0x8UL) /*!< FRZ_SYS_WDOG (Bitfield-Mask: 0x01) */ +#define GPREG_RESET_FREEZE_REG_FRZ_RESERVED_Pos (2UL) /*!< FRZ_RESERVED (Bit 2) */ +#define GPREG_RESET_FREEZE_REG_FRZ_RESERVED_Msk (0x4UL) /*!< FRZ_RESERVED (Bitfield-Mask: 0x01) */ +#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM_Pos (1UL) /*!< FRZ_SWTIM (Bit 1) */ +#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM_Msk (0x2UL) /*!< FRZ_SWTIM (Bitfield-Mask: 0x01) */ +#define GPREG_RESET_FREEZE_REG_FRZ_WKUPTIM_Pos (0UL) /*!< FRZ_WKUPTIM (Bit 0) */ +#define GPREG_RESET_FREEZE_REG_FRZ_WKUPTIM_Msk (0x1UL) /*!< FRZ_WKUPTIM (Bitfield-Mask: 0x01) */ +/* ==================================================== SET_FREEZE_REG ===================================================== */ +#define GPREG_SET_FREEZE_REG_FRZ_CMAC_WDOG_Pos (10UL) /*!< FRZ_CMAC_WDOG (Bit 10) */ +#define GPREG_SET_FREEZE_REG_FRZ_CMAC_WDOG_Msk (0x400UL) /*!< FRZ_CMAC_WDOG (Bitfield-Mask: 0x01) */ +#define GPREG_SET_FREEZE_REG_FRZ_SWTIM4_Pos (9UL) /*!< FRZ_SWTIM4 (Bit 9) */ +#define GPREG_SET_FREEZE_REG_FRZ_SWTIM4_Msk (0x200UL) /*!< FRZ_SWTIM4 (Bitfield-Mask: 0x01) */ +#define GPREG_SET_FREEZE_REG_FRZ_SWTIM3_Pos (8UL) /*!< FRZ_SWTIM3 (Bit 8) */ +#define GPREG_SET_FREEZE_REG_FRZ_SWTIM3_Msk (0x100UL) /*!< FRZ_SWTIM3 (Bitfield-Mask: 0x01) */ +#define GPREG_SET_FREEZE_REG_FRZ_PWMLED_Pos (7UL) /*!< FRZ_PWMLED (Bit 7) */ +#define GPREG_SET_FREEZE_REG_FRZ_PWMLED_Msk (0x80UL) /*!< FRZ_PWMLED (Bitfield-Mask: 0x01) */ +#define GPREG_SET_FREEZE_REG_FRZ_SWTIM2_Pos (6UL) /*!< FRZ_SWTIM2 (Bit 6) */ +#define GPREG_SET_FREEZE_REG_FRZ_SWTIM2_Msk (0x40UL) /*!< FRZ_SWTIM2 (Bitfield-Mask: 0x01) */ +#define GPREG_SET_FREEZE_REG_FRZ_DMA_Pos (5UL) /*!< FRZ_DMA (Bit 5) */ +#define GPREG_SET_FREEZE_REG_FRZ_DMA_Msk (0x20UL) /*!< FRZ_DMA (Bitfield-Mask: 0x01) */ +#define GPREG_SET_FREEZE_REG_FRZ_USB_Pos (4UL) /*!< FRZ_USB (Bit 4) */ +#define GPREG_SET_FREEZE_REG_FRZ_USB_Msk (0x10UL) /*!< FRZ_USB (Bitfield-Mask: 0x01) */ +#define GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Pos (3UL) /*!< FRZ_SYS_WDOG (Bit 3) */ +#define GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Msk (0x8UL) /*!< FRZ_SYS_WDOG (Bitfield-Mask: 0x01) */ +#define GPREG_SET_FREEZE_REG_FRZ_RESERVED_Pos (2UL) /*!< FRZ_RESERVED (Bit 2) */ +#define GPREG_SET_FREEZE_REG_FRZ_RESERVED_Msk (0x4UL) /*!< FRZ_RESERVED (Bitfield-Mask: 0x01) */ +#define GPREG_SET_FREEZE_REG_FRZ_SWTIM_Pos (1UL) /*!< FRZ_SWTIM (Bit 1) */ +#define GPREG_SET_FREEZE_REG_FRZ_SWTIM_Msk (0x2UL) /*!< FRZ_SWTIM (Bitfield-Mask: 0x01) */ +#define GPREG_SET_FREEZE_REG_FRZ_WKUPTIM_Pos (0UL) /*!< FRZ_WKUPTIM (Bit 0) */ +#define GPREG_SET_FREEZE_REG_FRZ_WKUPTIM_Msk (0x1UL) /*!< FRZ_WKUPTIM (Bitfield-Mask: 0x01) */ +/* ====================================================== USBPAD_REG ======================================================= */ +#define GPREG_USBPAD_REG_USBPHY_FORCE_SW2_ON_Pos (2UL) /*!< USBPHY_FORCE_SW2_ON (Bit 2) */ +#define GPREG_USBPAD_REG_USBPHY_FORCE_SW2_ON_Msk (0x4UL) /*!< USBPHY_FORCE_SW2_ON (Bitfield-Mask: 0x01) */ +#define GPREG_USBPAD_REG_USBPHY_FORCE_SW1_OFF_Pos (1UL) /*!< USBPHY_FORCE_SW1_OFF (Bit 1) */ +#define GPREG_USBPAD_REG_USBPHY_FORCE_SW1_OFF_Msk (0x2UL) /*!< USBPHY_FORCE_SW1_OFF (Bitfield-Mask: 0x01) */ +#define GPREG_USBPAD_REG_USBPAD_EN_Pos (0UL) /*!< USBPAD_EN (Bit 0) */ +#define GPREG_USBPAD_REG_USBPAD_EN_Msk (0x1UL) /*!< USBPAD_EN (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ I2C ================ */ +/* =========================================================================================================================== */ + +/* =============================================== I2C_ACK_GENERAL_CALL_REG ================================================ */ +#define I2C_I2C_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Pos (0UL) /*!< ACK_GEN_CALL (Bit 0) */ +#define I2C_I2C_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Msk (0x1UL) /*!< ACK_GEN_CALL (Bitfield-Mask: 0x01) */ +/* ================================================= I2C_CLR_ACTIVITY_REG ================================================== */ +#define I2C_I2C_CLR_ACTIVITY_REG_CLR_ACTIVITY_Pos (0UL) /*!< CLR_ACTIVITY (Bit 0) */ +#define I2C_I2C_CLR_ACTIVITY_REG_CLR_ACTIVITY_Msk (0x1UL) /*!< CLR_ACTIVITY (Bitfield-Mask: 0x01) */ +/* ================================================= I2C_CLR_GEN_CALL_REG ================================================== */ +#define I2C_I2C_CLR_GEN_CALL_REG_CLR_GEN_CALL_Pos (0UL) /*!< CLR_GEN_CALL (Bit 0) */ +#define I2C_I2C_CLR_GEN_CALL_REG_CLR_GEN_CALL_Msk (0x1UL) /*!< CLR_GEN_CALL (Bitfield-Mask: 0x01) */ +/* =================================================== I2C_CLR_INTR_REG ==================================================== */ +#define I2C_I2C_CLR_INTR_REG_CLR_INTR_Pos (0UL) /*!< CLR_INTR (Bit 0) */ +#define I2C_I2C_CLR_INTR_REG_CLR_INTR_Msk (0x1UL) /*!< CLR_INTR (Bitfield-Mask: 0x01) */ +/* ================================================== I2C_CLR_RD_REQ_REG =================================================== */ +#define I2C_I2C_CLR_RD_REQ_REG_CLR_RD_REQ_Pos (0UL) /*!< CLR_RD_REQ (Bit 0) */ +#define I2C_I2C_CLR_RD_REQ_REG_CLR_RD_REQ_Msk (0x1UL) /*!< CLR_RD_REQ (Bitfield-Mask: 0x01) */ +/* ================================================== I2C_CLR_RX_DONE_REG ================================================== */ +#define I2C_I2C_CLR_RX_DONE_REG_CLR_RX_DONE_Pos (0UL) /*!< CLR_RX_DONE (Bit 0) */ +#define I2C_I2C_CLR_RX_DONE_REG_CLR_RX_DONE_Msk (0x1UL) /*!< CLR_RX_DONE (Bitfield-Mask: 0x01) */ +/* ================================================== I2C_CLR_RX_OVER_REG ================================================== */ +#define I2C_I2C_CLR_RX_OVER_REG_CLR_RX_OVER_Pos (0UL) /*!< CLR_RX_OVER (Bit 0) */ +#define I2C_I2C_CLR_RX_OVER_REG_CLR_RX_OVER_Msk (0x1UL) /*!< CLR_RX_OVER (Bitfield-Mask: 0x01) */ +/* ================================================= I2C_CLR_RX_UNDER_REG ================================================== */ +#define I2C_I2C_CLR_RX_UNDER_REG_CLR_RX_UNDER_Pos (0UL) /*!< CLR_RX_UNDER (Bit 0) */ +#define I2C_I2C_CLR_RX_UNDER_REG_CLR_RX_UNDER_Msk (0x1UL) /*!< CLR_RX_UNDER (Bitfield-Mask: 0x01) */ +/* ================================================= I2C_CLR_START_DET_REG ================================================= */ +#define I2C_I2C_CLR_START_DET_REG_CLR_START_DET_Pos (0UL) /*!< CLR_START_DET (Bit 0) */ +#define I2C_I2C_CLR_START_DET_REG_CLR_START_DET_Msk (0x1UL) /*!< CLR_START_DET (Bitfield-Mask: 0x01) */ +/* ================================================= I2C_CLR_STOP_DET_REG ================================================== */ +#define I2C_I2C_CLR_STOP_DET_REG_CLR_STOP_DET_Pos (0UL) /*!< CLR_STOP_DET (Bit 0) */ +#define I2C_I2C_CLR_STOP_DET_REG_CLR_STOP_DET_Msk (0x1UL) /*!< CLR_STOP_DET (Bitfield-Mask: 0x01) */ +/* ================================================== I2C_CLR_TX_ABRT_REG ================================================== */ +#define I2C_I2C_CLR_TX_ABRT_REG_CLR_TX_ABRT_Pos (0UL) /*!< CLR_TX_ABRT (Bit 0) */ +#define I2C_I2C_CLR_TX_ABRT_REG_CLR_TX_ABRT_Msk (0x1UL) /*!< CLR_TX_ABRT (Bitfield-Mask: 0x01) */ +/* ================================================== I2C_CLR_TX_OVER_REG ================================================== */ +#define I2C_I2C_CLR_TX_OVER_REG_CLR_TX_OVER_Pos (0UL) /*!< CLR_TX_OVER (Bit 0) */ +#define I2C_I2C_CLR_TX_OVER_REG_CLR_TX_OVER_Msk (0x1UL) /*!< CLR_TX_OVER (Bitfield-Mask: 0x01) */ +/* ====================================================== I2C_CON_REG ====================================================== */ +#define I2C_I2C_CON_REG_I2C_STOP_DET_IF_MASTER_ACTIVE_Pos (10UL) /*!< I2C_STOP_DET_IF_MASTER_ACTIVE (Bit 10) */ +#define I2C_I2C_CON_REG_I2C_STOP_DET_IF_MASTER_ACTIVE_Msk (0x400UL) /*!< I2C_STOP_DET_IF_MASTER_ACTIVE (Bitfield-Mask: 0x01) */ +#define I2C_I2C_CON_REG_I2C_RX_FIFO_FULL_HLD_CTRL_Pos (9UL) /*!< I2C_RX_FIFO_FULL_HLD_CTRL (Bit 9) */ +#define I2C_I2C_CON_REG_I2C_RX_FIFO_FULL_HLD_CTRL_Msk (0x200UL) /*!< I2C_RX_FIFO_FULL_HLD_CTRL (Bitfield-Mask: 0x01) */ +#define I2C_I2C_CON_REG_I2C_TX_EMPTY_CTRL_Pos (8UL) /*!< I2C_TX_EMPTY_CTRL (Bit 8) */ +#define I2C_I2C_CON_REG_I2C_TX_EMPTY_CTRL_Msk (0x100UL) /*!< I2C_TX_EMPTY_CTRL (Bitfield-Mask: 0x01) */ +#define I2C_I2C_CON_REG_I2C_STOP_DET_IFADDRESSED_Pos (7UL) /*!< I2C_STOP_DET_IFADDRESSED (Bit 7) */ +#define I2C_I2C_CON_REG_I2C_STOP_DET_IFADDRESSED_Msk (0x80UL) /*!< I2C_STOP_DET_IFADDRESSED (Bitfield-Mask: 0x01) */ +#define I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Pos (6UL) /*!< I2C_SLAVE_DISABLE (Bit 6) */ +#define I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Msk (0x40UL) /*!< I2C_SLAVE_DISABLE (Bitfield-Mask: 0x01) */ +#define I2C_I2C_CON_REG_I2C_RESTART_EN_Pos (5UL) /*!< I2C_RESTART_EN (Bit 5) */ +#define I2C_I2C_CON_REG_I2C_RESTART_EN_Msk (0x20UL) /*!< I2C_RESTART_EN (Bitfield-Mask: 0x01) */ +#define I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Pos (4UL) /*!< I2C_10BITADDR_MASTER (Bit 4) */ +#define I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Msk (0x10UL) /*!< I2C_10BITADDR_MASTER (Bitfield-Mask: 0x01) */ +#define I2C_I2C_CON_REG_I2C_10BITADDR_SLAVE_Pos (3UL) /*!< I2C_10BITADDR_SLAVE (Bit 3) */ +#define I2C_I2C_CON_REG_I2C_10BITADDR_SLAVE_Msk (0x8UL) /*!< I2C_10BITADDR_SLAVE (Bitfield-Mask: 0x01) */ +#define I2C_I2C_CON_REG_I2C_SPEED_Pos (1UL) /*!< I2C_SPEED (Bit 1) */ +#define I2C_I2C_CON_REG_I2C_SPEED_Msk (0x6UL) /*!< I2C_SPEED (Bitfield-Mask: 0x03) */ +#define I2C_I2C_CON_REG_I2C_MASTER_MODE_Pos (0UL) /*!< I2C_MASTER_MODE (Bit 0) */ +#define I2C_I2C_CON_REG_I2C_MASTER_MODE_Msk (0x1UL) /*!< I2C_MASTER_MODE (Bitfield-Mask: 0x01) */ +/* =================================================== I2C_DATA_CMD_REG ==================================================== */ +#define I2C_I2C_DATA_CMD_REG_I2C_RESTART_Pos (10UL) /*!< I2C_RESTART (Bit 10) */ +#define I2C_I2C_DATA_CMD_REG_I2C_RESTART_Msk (0x400UL) /*!< I2C_RESTART (Bitfield-Mask: 0x01) */ +#define I2C_I2C_DATA_CMD_REG_I2C_STOP_Pos (9UL) /*!< I2C_STOP (Bit 9) */ +#define I2C_I2C_DATA_CMD_REG_I2C_STOP_Msk (0x200UL) /*!< I2C_STOP (Bitfield-Mask: 0x01) */ +#define I2C_I2C_DATA_CMD_REG_I2C_CMD_Pos (8UL) /*!< I2C_CMD (Bit 8) */ +#define I2C_I2C_DATA_CMD_REG_I2C_CMD_Msk (0x100UL) /*!< I2C_CMD (Bitfield-Mask: 0x01) */ +#define I2C_I2C_DATA_CMD_REG_I2C_DAT_Pos (0UL) /*!< I2C_DAT (Bit 0) */ +#define I2C_I2C_DATA_CMD_REG_I2C_DAT_Msk (0xffUL) /*!< I2C_DAT (Bitfield-Mask: 0xff) */ +/* ==================================================== I2C_DMA_CR_REG ===================================================== */ +#define I2C_I2C_DMA_CR_REG_TDMAE_Pos (1UL) /*!< TDMAE (Bit 1) */ +#define I2C_I2C_DMA_CR_REG_TDMAE_Msk (0x2UL) /*!< TDMAE (Bitfield-Mask: 0x01) */ +#define I2C_I2C_DMA_CR_REG_RDMAE_Pos (0UL) /*!< RDMAE (Bit 0) */ +#define I2C_I2C_DMA_CR_REG_RDMAE_Msk (0x1UL) /*!< RDMAE (Bitfield-Mask: 0x01) */ +/* =================================================== I2C_DMA_RDLR_REG ==================================================== */ +#define I2C_I2C_DMA_RDLR_REG_DMARDL_Pos (0UL) /*!< DMARDL (Bit 0) */ +#define I2C_I2C_DMA_RDLR_REG_DMARDL_Msk (0x1fUL) /*!< DMARDL (Bitfield-Mask: 0x1f) */ +/* =================================================== I2C_DMA_TDLR_REG ==================================================== */ +#define I2C_I2C_DMA_TDLR_REG_DMATDL_Pos (0UL) /*!< DMATDL (Bit 0) */ +#define I2C_I2C_DMA_TDLR_REG_DMATDL_Msk (0x1fUL) /*!< DMATDL (Bitfield-Mask: 0x1f) */ +/* ==================================================== I2C_ENABLE_REG ===================================================== */ +#define I2C_I2C_ENABLE_REG_I2C_TX_CMD_BLOCK_Pos (2UL) /*!< I2C_TX_CMD_BLOCK (Bit 2) */ +#define I2C_I2C_ENABLE_REG_I2C_TX_CMD_BLOCK_Msk (0x4UL) /*!< I2C_TX_CMD_BLOCK (Bitfield-Mask: 0x01) */ +#define I2C_I2C_ENABLE_REG_I2C_ABORT_Pos (1UL) /*!< I2C_ABORT (Bit 1) */ +#define I2C_I2C_ENABLE_REG_I2C_ABORT_Msk (0x2UL) /*!< I2C_ABORT (Bitfield-Mask: 0x01) */ +#define I2C_I2C_ENABLE_REG_I2C_EN_Pos (0UL) /*!< I2C_EN (Bit 0) */ +#define I2C_I2C_ENABLE_REG_I2C_EN_Msk (0x1UL) /*!< I2C_EN (Bitfield-Mask: 0x01) */ +/* ================================================= I2C_ENABLE_STATUS_REG ================================================= */ +#define I2C_I2C_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Pos (2UL) /*!< SLV_RX_DATA_LOST (Bit 2) */ +#define I2C_I2C_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Msk (0x4UL) /*!< SLV_RX_DATA_LOST (Bitfield-Mask: 0x01) */ +#define I2C_I2C_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Pos (1UL) /*!< SLV_DISABLED_WHILE_BUSY (Bit 1) */ +#define I2C_I2C_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Msk (0x2UL) /*!< SLV_DISABLED_WHILE_BUSY (Bitfield-Mask: 0x01) */ +#define I2C_I2C_ENABLE_STATUS_REG_IC_EN_Pos (0UL) /*!< IC_EN (Bit 0) */ +#define I2C_I2C_ENABLE_STATUS_REG_IC_EN_Msk (0x1UL) /*!< IC_EN (Bitfield-Mask: 0x01) */ +/* ================================================== I2C_FS_SCL_HCNT_REG ================================================== */ +#define I2C_I2C_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Pos (0UL) /*!< IC_FS_SCL_HCNT (Bit 0) */ +#define I2C_I2C_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Msk (0xffffUL) /*!< IC_FS_SCL_HCNT (Bitfield-Mask: 0xffff) */ +/* ================================================== I2C_FS_SCL_LCNT_REG ================================================== */ +#define I2C_I2C_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Pos (0UL) /*!< IC_FS_SCL_LCNT (Bit 0) */ +#define I2C_I2C_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Msk (0xffffUL) /*!< IC_FS_SCL_LCNT (Bitfield-Mask: 0xffff) */ +/* =================================================== I2C_HS_MADDR_REG ==================================================== */ +#define I2C_I2C_HS_MADDR_REG_I2C_IC_HS_MAR_Pos (0UL) /*!< I2C_IC_HS_MAR (Bit 0) */ +#define I2C_I2C_HS_MADDR_REG_I2C_IC_HS_MAR_Msk (0x7UL) /*!< I2C_IC_HS_MAR (Bitfield-Mask: 0x07) */ +/* ================================================== I2C_HS_SCL_HCNT_REG ================================================== */ +#define I2C_I2C_HS_SCL_HCNT_REG_IC_HS_SCL_HCNT_Pos (0UL) /*!< IC_HS_SCL_HCNT (Bit 0) */ +#define I2C_I2C_HS_SCL_HCNT_REG_IC_HS_SCL_HCNT_Msk (0xffffUL) /*!< IC_HS_SCL_HCNT (Bitfield-Mask: 0xffff) */ +/* ================================================== I2C_HS_SCL_LCNT_REG ================================================== */ +#define I2C_I2C_HS_SCL_LCNT_REG_IC_HS_SCL_LCNT_Pos (0UL) /*!< IC_HS_SCL_LCNT (Bit 0) */ +#define I2C_I2C_HS_SCL_LCNT_REG_IC_HS_SCL_LCNT_Msk (0xffffUL) /*!< IC_HS_SCL_LCNT (Bitfield-Mask: 0xffff) */ +/* ================================================= I2C_IC_FS_SPKLEN_REG ================================================== */ +#define I2C_I2C_IC_FS_SPKLEN_REG_I2C_FS_SPKLEN_Pos (0UL) /*!< I2C_FS_SPKLEN (Bit 0) */ +#define I2C_I2C_IC_FS_SPKLEN_REG_I2C_FS_SPKLEN_Msk (0xffUL) /*!< I2C_FS_SPKLEN (Bitfield-Mask: 0xff) */ +/* ================================================= I2C_IC_HS_SPKLEN_REG ================================================== */ +#define I2C_I2C_IC_HS_SPKLEN_REG_I2C_HS_SPKLEN_Pos (0UL) /*!< I2C_HS_SPKLEN (Bit 0) */ +#define I2C_I2C_IC_HS_SPKLEN_REG_I2C_HS_SPKLEN_Msk (0xffUL) /*!< I2C_HS_SPKLEN (Bitfield-Mask: 0xff) */ +/* =================================================== I2C_INTR_MASK_REG =================================================== */ +#define I2C_I2C_INTR_MASK_REG_M_SCL_STUCK_AT_LOW_Pos (14UL) /*!< M_SCL_STUCK_AT_LOW (Bit 14) */ +#define I2C_I2C_INTR_MASK_REG_M_SCL_STUCK_AT_LOW_Msk (0x4000UL) /*!< M_SCL_STUCK_AT_LOW (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_MASK_REG_M_MASTER_ON_HOLD_Pos (13UL) /*!< M_MASTER_ON_HOLD (Bit 13) */ +#define I2C_I2C_INTR_MASK_REG_M_MASTER_ON_HOLD_Msk (0x2000UL) /*!< M_MASTER_ON_HOLD (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_MASK_REG_M_RESTART_DET_Pos (12UL) /*!< M_RESTART_DET (Bit 12) */ +#define I2C_I2C_INTR_MASK_REG_M_RESTART_DET_Msk (0x1000UL) /*!< M_RESTART_DET (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_MASK_REG_M_GEN_CALL_Pos (11UL) /*!< M_GEN_CALL (Bit 11) */ +#define I2C_I2C_INTR_MASK_REG_M_GEN_CALL_Msk (0x800UL) /*!< M_GEN_CALL (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_MASK_REG_M_START_DET_Pos (10UL) /*!< M_START_DET (Bit 10) */ +#define I2C_I2C_INTR_MASK_REG_M_START_DET_Msk (0x400UL) /*!< M_START_DET (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_MASK_REG_M_STOP_DET_Pos (9UL) /*!< M_STOP_DET (Bit 9) */ +#define I2C_I2C_INTR_MASK_REG_M_STOP_DET_Msk (0x200UL) /*!< M_STOP_DET (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_MASK_REG_M_ACTIVITY_Pos (8UL) /*!< M_ACTIVITY (Bit 8) */ +#define I2C_I2C_INTR_MASK_REG_M_ACTIVITY_Msk (0x100UL) /*!< M_ACTIVITY (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_MASK_REG_M_RX_DONE_Pos (7UL) /*!< M_RX_DONE (Bit 7) */ +#define I2C_I2C_INTR_MASK_REG_M_RX_DONE_Msk (0x80UL) /*!< M_RX_DONE (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_MASK_REG_M_TX_ABRT_Pos (6UL) /*!< M_TX_ABRT (Bit 6) */ +#define I2C_I2C_INTR_MASK_REG_M_TX_ABRT_Msk (0x40UL) /*!< M_TX_ABRT (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_MASK_REG_M_RD_REQ_Pos (5UL) /*!< M_RD_REQ (Bit 5) */ +#define I2C_I2C_INTR_MASK_REG_M_RD_REQ_Msk (0x20UL) /*!< M_RD_REQ (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Pos (4UL) /*!< M_TX_EMPTY (Bit 4) */ +#define I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Msk (0x10UL) /*!< M_TX_EMPTY (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_MASK_REG_M_TX_OVER_Pos (3UL) /*!< M_TX_OVER (Bit 3) */ +#define I2C_I2C_INTR_MASK_REG_M_TX_OVER_Msk (0x8UL) /*!< M_TX_OVER (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_MASK_REG_M_RX_FULL_Pos (2UL) /*!< M_RX_FULL (Bit 2) */ +#define I2C_I2C_INTR_MASK_REG_M_RX_FULL_Msk (0x4UL) /*!< M_RX_FULL (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_MASK_REG_M_RX_OVER_Pos (1UL) /*!< M_RX_OVER (Bit 1) */ +#define I2C_I2C_INTR_MASK_REG_M_RX_OVER_Msk (0x2UL) /*!< M_RX_OVER (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_MASK_REG_M_RX_UNDER_Pos (0UL) /*!< M_RX_UNDER (Bit 0) */ +#define I2C_I2C_INTR_MASK_REG_M_RX_UNDER_Msk (0x1UL) /*!< M_RX_UNDER (Bitfield-Mask: 0x01) */ +/* =================================================== I2C_INTR_STAT_REG =================================================== */ +#define I2C_I2C_INTR_STAT_REG_R_SCL_STUCK_AT_LOW_Pos (14UL) /*!< R_SCL_STUCK_AT_LOW (Bit 14) */ +#define I2C_I2C_INTR_STAT_REG_R_SCL_STUCK_AT_LOW_Msk (0x4000UL) /*!< R_SCL_STUCK_AT_LOW (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_STAT_REG_R_MASTER_ON_HOLD_Pos (13UL) /*!< R_MASTER_ON_HOLD (Bit 13) */ +#define I2C_I2C_INTR_STAT_REG_R_MASTER_ON_HOLD_Msk (0x2000UL) /*!< R_MASTER_ON_HOLD (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_STAT_REG_R_RESTART_DET_Pos (12UL) /*!< R_RESTART_DET (Bit 12) */ +#define I2C_I2C_INTR_STAT_REG_R_RESTART_DET_Msk (0x1000UL) /*!< R_RESTART_DET (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Pos (11UL) /*!< R_GEN_CALL (Bit 11) */ +#define I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Msk (0x800UL) /*!< R_GEN_CALL (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_STAT_REG_R_START_DET_Pos (10UL) /*!< R_START_DET (Bit 10) */ +#define I2C_I2C_INTR_STAT_REG_R_START_DET_Msk (0x400UL) /*!< R_START_DET (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_STAT_REG_R_STOP_DET_Pos (9UL) /*!< R_STOP_DET (Bit 9) */ +#define I2C_I2C_INTR_STAT_REG_R_STOP_DET_Msk (0x200UL) /*!< R_STOP_DET (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Pos (8UL) /*!< R_ACTIVITY (Bit 8) */ +#define I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Msk (0x100UL) /*!< R_ACTIVITY (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_STAT_REG_R_RX_DONE_Pos (7UL) /*!< R_RX_DONE (Bit 7) */ +#define I2C_I2C_INTR_STAT_REG_R_RX_DONE_Msk (0x80UL) /*!< R_RX_DONE (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Pos (6UL) /*!< R_TX_ABRT (Bit 6) */ +#define I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Msk (0x40UL) /*!< R_TX_ABRT (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_STAT_REG_R_RD_REQ_Pos (5UL) /*!< R_RD_REQ (Bit 5) */ +#define I2C_I2C_INTR_STAT_REG_R_RD_REQ_Msk (0x20UL) /*!< R_RD_REQ (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Pos (4UL) /*!< R_TX_EMPTY (Bit 4) */ +#define I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Msk (0x10UL) /*!< R_TX_EMPTY (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_STAT_REG_R_TX_OVER_Pos (3UL) /*!< R_TX_OVER (Bit 3) */ +#define I2C_I2C_INTR_STAT_REG_R_TX_OVER_Msk (0x8UL) /*!< R_TX_OVER (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_STAT_REG_R_RX_FULL_Pos (2UL) /*!< R_RX_FULL (Bit 2) */ +#define I2C_I2C_INTR_STAT_REG_R_RX_FULL_Msk (0x4UL) /*!< R_RX_FULL (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_STAT_REG_R_RX_OVER_Pos (1UL) /*!< R_RX_OVER (Bit 1) */ +#define I2C_I2C_INTR_STAT_REG_R_RX_OVER_Msk (0x2UL) /*!< R_RX_OVER (Bitfield-Mask: 0x01) */ +#define I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Pos (0UL) /*!< R_RX_UNDER (Bit 0) */ +#define I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Msk (0x1UL) /*!< R_RX_UNDER (Bitfield-Mask: 0x01) */ +/* ================================================= I2C_RAW_INTR_STAT_REG ================================================= */ +#define I2C_I2C_RAW_INTR_STAT_REG_SCL_STUCK_AT_LOW_Pos (14UL) /*!< SCL_STUCK_AT_LOW (Bit 14) */ +#define I2C_I2C_RAW_INTR_STAT_REG_SCL_STUCK_AT_LOW_Msk (0x4000UL) /*!< SCL_STUCK_AT_LOW (Bitfield-Mask: 0x01) */ +#define I2C_I2C_RAW_INTR_STAT_REG_MASTER_ON_HOLD_Pos (13UL) /*!< MASTER_ON_HOLD (Bit 13) */ +#define I2C_I2C_RAW_INTR_STAT_REG_MASTER_ON_HOLD_Msk (0x2000UL) /*!< MASTER_ON_HOLD (Bitfield-Mask: 0x01) */ +#define I2C_I2C_RAW_INTR_STAT_REG_RESTART_DET_Pos (12UL) /*!< RESTART_DET (Bit 12) */ +#define I2C_I2C_RAW_INTR_STAT_REG_RESTART_DET_Msk (0x1000UL) /*!< RESTART_DET (Bitfield-Mask: 0x01) */ +#define I2C_I2C_RAW_INTR_STAT_REG_GEN_CALL_Pos (11UL) /*!< GEN_CALL (Bit 11) */ +#define I2C_I2C_RAW_INTR_STAT_REG_GEN_CALL_Msk (0x800UL) /*!< GEN_CALL (Bitfield-Mask: 0x01) */ +#define I2C_I2C_RAW_INTR_STAT_REG_START_DET_Pos (10UL) /*!< START_DET (Bit 10) */ +#define I2C_I2C_RAW_INTR_STAT_REG_START_DET_Msk (0x400UL) /*!< START_DET (Bitfield-Mask: 0x01) */ +#define I2C_I2C_RAW_INTR_STAT_REG_STOP_DET_Pos (9UL) /*!< STOP_DET (Bit 9) */ +#define I2C_I2C_RAW_INTR_STAT_REG_STOP_DET_Msk (0x200UL) /*!< STOP_DET (Bitfield-Mask: 0x01) */ +#define I2C_I2C_RAW_INTR_STAT_REG_ACTIVITY_Pos (8UL) /*!< ACTIVITY (Bit 8) */ +#define I2C_I2C_RAW_INTR_STAT_REG_ACTIVITY_Msk (0x100UL) /*!< ACTIVITY (Bitfield-Mask: 0x01) */ +#define I2C_I2C_RAW_INTR_STAT_REG_RX_DONE_Pos (7UL) /*!< RX_DONE (Bit 7) */ +#define I2C_I2C_RAW_INTR_STAT_REG_RX_DONE_Msk (0x80UL) /*!< RX_DONE (Bitfield-Mask: 0x01) */ +#define I2C_I2C_RAW_INTR_STAT_REG_TX_ABRT_Pos (6UL) /*!< TX_ABRT (Bit 6) */ +#define I2C_I2C_RAW_INTR_STAT_REG_TX_ABRT_Msk (0x40UL) /*!< TX_ABRT (Bitfield-Mask: 0x01) */ +#define I2C_I2C_RAW_INTR_STAT_REG_RD_REQ_Pos (5UL) /*!< RD_REQ (Bit 5) */ +#define I2C_I2C_RAW_INTR_STAT_REG_RD_REQ_Msk (0x20UL) /*!< RD_REQ (Bitfield-Mask: 0x01) */ +#define I2C_I2C_RAW_INTR_STAT_REG_TX_EMPTY_Pos (4UL) /*!< TX_EMPTY (Bit 4) */ +#define I2C_I2C_RAW_INTR_STAT_REG_TX_EMPTY_Msk (0x10UL) /*!< TX_EMPTY (Bitfield-Mask: 0x01) */ +#define I2C_I2C_RAW_INTR_STAT_REG_TX_OVER_Pos (3UL) /*!< TX_OVER (Bit 3) */ +#define I2C_I2C_RAW_INTR_STAT_REG_TX_OVER_Msk (0x8UL) /*!< TX_OVER (Bitfield-Mask: 0x01) */ +#define I2C_I2C_RAW_INTR_STAT_REG_RX_FULL_Pos (2UL) /*!< RX_FULL (Bit 2) */ +#define I2C_I2C_RAW_INTR_STAT_REG_RX_FULL_Msk (0x4UL) /*!< RX_FULL (Bitfield-Mask: 0x01) */ +#define I2C_I2C_RAW_INTR_STAT_REG_RX_OVER_Pos (1UL) /*!< RX_OVER (Bit 1) */ +#define I2C_I2C_RAW_INTR_STAT_REG_RX_OVER_Msk (0x2UL) /*!< RX_OVER (Bitfield-Mask: 0x01) */ +#define I2C_I2C_RAW_INTR_STAT_REG_RX_UNDER_Pos (0UL) /*!< RX_UNDER (Bit 0) */ +#define I2C_I2C_RAW_INTR_STAT_REG_RX_UNDER_Msk (0x1UL) /*!< RX_UNDER (Bitfield-Mask: 0x01) */ +/* ===================================================== I2C_RXFLR_REG ===================================================== */ +#define I2C_I2C_RXFLR_REG_RXFLR_Pos (0UL) /*!< RXFLR (Bit 0) */ +#define I2C_I2C_RXFLR_REG_RXFLR_Msk (0x3fUL) /*!< RXFLR (Bitfield-Mask: 0x3f) */ +/* ===================================================== I2C_RX_TL_REG ===================================================== */ +#define I2C_I2C_RX_TL_REG_RX_TL_Pos (0UL) /*!< RX_TL (Bit 0) */ +#define I2C_I2C_RX_TL_REG_RX_TL_Msk (0x1fUL) /*!< RX_TL (Bitfield-Mask: 0x1f) */ +/* ====================================================== I2C_SAR_REG ====================================================== */ +#define I2C_I2C_SAR_REG_IC_SAR_Pos (0UL) /*!< IC_SAR (Bit 0) */ +#define I2C_I2C_SAR_REG_IC_SAR_Msk (0x3ffUL) /*!< IC_SAR (Bitfield-Mask: 0x3ff) */ +/* =================================================== I2C_SDA_HOLD_REG ==================================================== */ +#define I2C_I2C_SDA_HOLD_REG_I2C_SDA_RX_HOLD_Pos (16UL) /*!< I2C_SDA_RX_HOLD (Bit 16) */ +#define I2C_I2C_SDA_HOLD_REG_I2C_SDA_RX_HOLD_Msk (0xff0000UL) /*!< I2C_SDA_RX_HOLD (Bitfield-Mask: 0xff) */ +#define I2C_I2C_SDA_HOLD_REG_I2C_SDA_TX_HOLD_Pos (0UL) /*!< I2C_SDA_TX_HOLD (Bit 0) */ +#define I2C_I2C_SDA_HOLD_REG_I2C_SDA_TX_HOLD_Msk (0xffffUL) /*!< I2C_SDA_TX_HOLD (Bitfield-Mask: 0xffff) */ +/* =================================================== I2C_SDA_SETUP_REG =================================================== */ +#define I2C_I2C_SDA_SETUP_REG_SDA_SETUP_Pos (0UL) /*!< SDA_SETUP (Bit 0) */ +#define I2C_I2C_SDA_SETUP_REG_SDA_SETUP_Msk (0xffUL) /*!< SDA_SETUP (Bitfield-Mask: 0xff) */ +/* ================================================== I2C_SS_SCL_HCNT_REG ================================================== */ +#define I2C_I2C_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Pos (0UL) /*!< IC_SS_SCL_HCNT (Bit 0) */ +#define I2C_I2C_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Msk (0xffffUL) /*!< IC_SS_SCL_HCNT (Bitfield-Mask: 0xffff) */ +/* ================================================== I2C_SS_SCL_LCNT_REG ================================================== */ +#define I2C_I2C_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Pos (0UL) /*!< IC_SS_SCL_LCNT (Bit 0) */ +#define I2C_I2C_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Msk (0xffffUL) /*!< IC_SS_SCL_LCNT (Bitfield-Mask: 0xffff) */ +/* ==================================================== I2C_STATUS_REG ===================================================== */ +#define I2C_I2C_STATUS_REG_LV_HOLD_RX_FIFO_FULL_Pos (10UL) /*!< LV_HOLD_RX_FIFO_FULL (Bit 10) */ +#define I2C_I2C_STATUS_REG_LV_HOLD_RX_FIFO_FULL_Msk (0x400UL) /*!< LV_HOLD_RX_FIFO_FULL (Bitfield-Mask: 0x01) */ +#define I2C_I2C_STATUS_REG_SLV_HOLD_TX_FIFO_EMPTY_Pos (9UL) /*!< SLV_HOLD_TX_FIFO_EMPTY (Bit 9) */ +#define I2C_I2C_STATUS_REG_SLV_HOLD_TX_FIFO_EMPTY_Msk (0x200UL) /*!< SLV_HOLD_TX_FIFO_EMPTY (Bitfield-Mask: 0x01) */ +#define I2C_I2C_STATUS_REG_MST_HOLD_RX_FIFO_FULL_Pos (8UL) /*!< MST_HOLD_RX_FIFO_FULL (Bit 8) */ +#define I2C_I2C_STATUS_REG_MST_HOLD_RX_FIFO_FULL_Msk (0x100UL) /*!< MST_HOLD_RX_FIFO_FULL (Bitfield-Mask: 0x01) */ +#define I2C_I2C_STATUS_REG_MST_HOLD_TX_FIFO_EMPTY_Pos (7UL) /*!< MST_HOLD_TX_FIFO_EMPTY (Bit 7) */ +#define I2C_I2C_STATUS_REG_MST_HOLD_TX_FIFO_EMPTY_Msk (0x80UL) /*!< MST_HOLD_TX_FIFO_EMPTY (Bitfield-Mask: 0x01) */ +#define I2C_I2C_STATUS_REG_SLV_ACTIVITY_Pos (6UL) /*!< SLV_ACTIVITY (Bit 6) */ +#define I2C_I2C_STATUS_REG_SLV_ACTIVITY_Msk (0x40UL) /*!< SLV_ACTIVITY (Bitfield-Mask: 0x01) */ +#define I2C_I2C_STATUS_REG_MST_ACTIVITY_Pos (5UL) /*!< MST_ACTIVITY (Bit 5) */ +#define I2C_I2C_STATUS_REG_MST_ACTIVITY_Msk (0x20UL) /*!< MST_ACTIVITY (Bitfield-Mask: 0x01) */ +#define I2C_I2C_STATUS_REG_RFF_Pos (4UL) /*!< RFF (Bit 4) */ +#define I2C_I2C_STATUS_REG_RFF_Msk (0x10UL) /*!< RFF (Bitfield-Mask: 0x01) */ +#define I2C_I2C_STATUS_REG_RFNE_Pos (3UL) /*!< RFNE (Bit 3) */ +#define I2C_I2C_STATUS_REG_RFNE_Msk (0x8UL) /*!< RFNE (Bitfield-Mask: 0x01) */ +#define I2C_I2C_STATUS_REG_TFE_Pos (2UL) /*!< TFE (Bit 2) */ +#define I2C_I2C_STATUS_REG_TFE_Msk (0x4UL) /*!< TFE (Bitfield-Mask: 0x01) */ +#define I2C_I2C_STATUS_REG_TFNF_Pos (1UL) /*!< TFNF (Bit 1) */ +#define I2C_I2C_STATUS_REG_TFNF_Msk (0x2UL) /*!< TFNF (Bitfield-Mask: 0x01) */ +#define I2C_I2C_STATUS_REG_I2C_ACTIVITY_Pos (0UL) /*!< I2C_ACTIVITY (Bit 0) */ +#define I2C_I2C_STATUS_REG_I2C_ACTIVITY_Msk (0x1UL) /*!< I2C_ACTIVITY (Bitfield-Mask: 0x01) */ +/* ====================================================== I2C_TAR_REG ====================================================== */ +#define I2C_I2C_TAR_REG_SPECIAL_Pos (11UL) /*!< SPECIAL (Bit 11) */ +#define I2C_I2C_TAR_REG_SPECIAL_Msk (0x800UL) /*!< SPECIAL (Bitfield-Mask: 0x01) */ +#define I2C_I2C_TAR_REG_GC_OR_START_Pos (10UL) /*!< GC_OR_START (Bit 10) */ +#define I2C_I2C_TAR_REG_GC_OR_START_Msk (0x400UL) /*!< GC_OR_START (Bitfield-Mask: 0x01) */ +#define I2C_I2C_TAR_REG_IC_TAR_Pos (0UL) /*!< IC_TAR (Bit 0) */ +#define I2C_I2C_TAR_REG_IC_TAR_Msk (0x3ffUL) /*!< IC_TAR (Bitfield-Mask: 0x3ff) */ +/* ===================================================== I2C_TXFLR_REG ===================================================== */ +#define I2C_I2C_TXFLR_REG_TXFLR_Pos (0UL) /*!< TXFLR (Bit 0) */ +#define I2C_I2C_TXFLR_REG_TXFLR_Msk (0x3fUL) /*!< TXFLR (Bitfield-Mask: 0x3f) */ +/* ================================================ I2C_TX_ABRT_SOURCE_REG ================================================= */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_USER_ABRT_Pos (16UL) /*!< ABRT_USER_ABRT (Bit 16) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_USER_ABRT_Msk (0x10000UL) /*!< ABRT_USER_ABRT (Bitfield-Mask: 0x01) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Pos (15UL) /*!< ABRT_SLVRD_INTX (Bit 15) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Msk (0x8000UL) /*!< ABRT_SLVRD_INTX (Bitfield-Mask: 0x01) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Pos (14UL) /*!< ABRT_SLV_ARBLOST (Bit 14) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Msk (0x4000UL) /*!< ABRT_SLV_ARBLOST (Bitfield-Mask: 0x01) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Pos (13UL) /*!< ABRT_SLVFLUSH_TXFIFO (Bit 13) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Msk (0x2000UL) /*!< ABRT_SLVFLUSH_TXFIFO (Bitfield-Mask: 0x01) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ARB_LOST_Pos (12UL) /*!< ARB_LOST (Bit 12) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ARB_LOST_Msk (0x1000UL) /*!< ARB_LOST (Bitfield-Mask: 0x01) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Pos (11UL) /*!< ABRT_MASTER_DIS (Bit 11) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Msk (0x800UL) /*!< ABRT_MASTER_DIS (Bitfield-Mask: 0x01) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Pos (10UL) /*!< ABRT_10B_RD_NORSTRT (Bit 10) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Msk (0x400UL) /*!< ABRT_10B_RD_NORSTRT (Bitfield-Mask: 0x01) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Pos (9UL) /*!< ABRT_SBYTE_NORSTRT (Bit 9) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Msk (0x200UL) /*!< ABRT_SBYTE_NORSTRT (Bitfield-Mask: 0x01) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Pos (8UL) /*!< ABRT_HS_NORSTRT (Bit 8) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Msk (0x100UL) /*!< ABRT_HS_NORSTRT (Bitfield-Mask: 0x01) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Pos (7UL) /*!< ABRT_SBYTE_ACKDET (Bit 7) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Msk (0x80UL) /*!< ABRT_SBYTE_ACKDET (Bitfield-Mask: 0x01) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Pos (6UL) /*!< ABRT_HS_ACKDET (Bit 6) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Msk (0x40UL) /*!< ABRT_HS_ACKDET (Bitfield-Mask: 0x01) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Pos (5UL) /*!< ABRT_GCALL_READ (Bit 5) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Msk (0x20UL) /*!< ABRT_GCALL_READ (Bitfield-Mask: 0x01) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Pos (4UL) /*!< ABRT_GCALL_NOACK (Bit 4) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Msk (0x10UL) /*!< ABRT_GCALL_NOACK (Bitfield-Mask: 0x01) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Pos (3UL) /*!< ABRT_TXDATA_NOACK (Bit 3) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Msk (0x8UL) /*!< ABRT_TXDATA_NOACK (Bitfield-Mask: 0x01) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Pos (2UL) /*!< ABRT_10ADDR2_NOACK (Bit 2) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Msk (0x4UL) /*!< ABRT_10ADDR2_NOACK (Bitfield-Mask: 0x01) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Pos (1UL) /*!< ABRT_10ADDR1_NOACK (Bit 1) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Msk (0x2UL) /*!< ABRT_10ADDR1_NOACK (Bitfield-Mask: 0x01) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Pos (0UL) /*!< ABRT_7B_ADDR_NOACK (Bit 0) */ +#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Msk (0x1UL) /*!< ABRT_7B_ADDR_NOACK (Bitfield-Mask: 0x01) */ +/* ===================================================== I2C_TX_TL_REG ===================================================== */ +#define I2C_I2C_TX_TL_REG_TX_TL_Pos (0UL) /*!< TX_TL (Bit 0) */ +#define I2C_I2C_TX_TL_REG_TX_TL_Msk (0x1fUL) /*!< TX_TL (Bitfield-Mask: 0x1f) */ + + +/* =========================================================================================================================== */ +/* ================ I2C2 ================ */ +/* =========================================================================================================================== */ + +/* =============================================== I2C2_ACK_GENERAL_CALL_REG =============================================== */ +#define I2C2_I2C2_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Pos (0UL) /*!< ACK_GEN_CALL (Bit 0) */ +#define I2C2_I2C2_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Msk (0x1UL) /*!< ACK_GEN_CALL (Bitfield-Mask: 0x01) */ +/* ================================================= I2C2_CLR_ACTIVITY_REG ================================================= */ +#define I2C2_I2C2_CLR_ACTIVITY_REG_CLR_ACTIVITY_Pos (0UL) /*!< CLR_ACTIVITY (Bit 0) */ +#define I2C2_I2C2_CLR_ACTIVITY_REG_CLR_ACTIVITY_Msk (0x1UL) /*!< CLR_ACTIVITY (Bitfield-Mask: 0x01) */ +/* ================================================= I2C2_CLR_GEN_CALL_REG ================================================= */ +#define I2C2_I2C2_CLR_GEN_CALL_REG_CLR_GEN_CALL_Pos (0UL) /*!< CLR_GEN_CALL (Bit 0) */ +#define I2C2_I2C2_CLR_GEN_CALL_REG_CLR_GEN_CALL_Msk (0x1UL) /*!< CLR_GEN_CALL (Bitfield-Mask: 0x01) */ +/* =================================================== I2C2_CLR_INTR_REG =================================================== */ +#define I2C2_I2C2_CLR_INTR_REG_CLR_INTR_Pos (0UL) /*!< CLR_INTR (Bit 0) */ +#define I2C2_I2C2_CLR_INTR_REG_CLR_INTR_Msk (0x1UL) /*!< CLR_INTR (Bitfield-Mask: 0x01) */ +/* ================================================== I2C2_CLR_RD_REQ_REG ================================================== */ +#define I2C2_I2C2_CLR_RD_REQ_REG_CLR_RD_REQ_Pos (0UL) /*!< CLR_RD_REQ (Bit 0) */ +#define I2C2_I2C2_CLR_RD_REQ_REG_CLR_RD_REQ_Msk (0x1UL) /*!< CLR_RD_REQ (Bitfield-Mask: 0x01) */ +/* ================================================= I2C2_CLR_RX_DONE_REG ================================================== */ +#define I2C2_I2C2_CLR_RX_DONE_REG_CLR_RX_DONE_Pos (0UL) /*!< CLR_RX_DONE (Bit 0) */ +#define I2C2_I2C2_CLR_RX_DONE_REG_CLR_RX_DONE_Msk (0x1UL) /*!< CLR_RX_DONE (Bitfield-Mask: 0x01) */ +/* ================================================= I2C2_CLR_RX_OVER_REG ================================================== */ +#define I2C2_I2C2_CLR_RX_OVER_REG_CLR_RX_OVER_Pos (0UL) /*!< CLR_RX_OVER (Bit 0) */ +#define I2C2_I2C2_CLR_RX_OVER_REG_CLR_RX_OVER_Msk (0x1UL) /*!< CLR_RX_OVER (Bitfield-Mask: 0x01) */ +/* ================================================= I2C2_CLR_RX_UNDER_REG ================================================= */ +#define I2C2_I2C2_CLR_RX_UNDER_REG_CLR_RX_UNDER_Pos (0UL) /*!< CLR_RX_UNDER (Bit 0) */ +#define I2C2_I2C2_CLR_RX_UNDER_REG_CLR_RX_UNDER_Msk (0x1UL) /*!< CLR_RX_UNDER (Bitfield-Mask: 0x01) */ +/* ================================================ I2C2_CLR_START_DET_REG ================================================= */ +#define I2C2_I2C2_CLR_START_DET_REG_CLR_START_DET_Pos (0UL) /*!< CLR_START_DET (Bit 0) */ +#define I2C2_I2C2_CLR_START_DET_REG_CLR_START_DET_Msk (0x1UL) /*!< CLR_START_DET (Bitfield-Mask: 0x01) */ +/* ================================================= I2C2_CLR_STOP_DET_REG ================================================= */ +#define I2C2_I2C2_CLR_STOP_DET_REG_CLR_STOP_DET_Pos (0UL) /*!< CLR_STOP_DET (Bit 0) */ +#define I2C2_I2C2_CLR_STOP_DET_REG_CLR_STOP_DET_Msk (0x1UL) /*!< CLR_STOP_DET (Bitfield-Mask: 0x01) */ +/* ================================================= I2C2_CLR_TX_ABRT_REG ================================================== */ +#define I2C2_I2C2_CLR_TX_ABRT_REG_CLR_TX_ABRT_Pos (0UL) /*!< CLR_TX_ABRT (Bit 0) */ +#define I2C2_I2C2_CLR_TX_ABRT_REG_CLR_TX_ABRT_Msk (0x1UL) /*!< CLR_TX_ABRT (Bitfield-Mask: 0x01) */ +/* ================================================= I2C2_CLR_TX_OVER_REG ================================================== */ +#define I2C2_I2C2_CLR_TX_OVER_REG_CLR_TX_OVER_Pos (0UL) /*!< CLR_TX_OVER (Bit 0) */ +#define I2C2_I2C2_CLR_TX_OVER_REG_CLR_TX_OVER_Msk (0x1UL) /*!< CLR_TX_OVER (Bitfield-Mask: 0x01) */ +/* ===================================================== I2C2_CON_REG ====================================================== */ +#define I2C2_I2C2_CON_REG_I2C_STOP_DET_IF_MASTER_ACTIVE_Pos (10UL) /*!< I2C_STOP_DET_IF_MASTER_ACTIVE (Bit 10) */ +#define I2C2_I2C2_CON_REG_I2C_STOP_DET_IF_MASTER_ACTIVE_Msk (0x400UL) /*!< I2C_STOP_DET_IF_MASTER_ACTIVE (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_CON_REG_I2C_RX_FIFO_FULL_HLD_CTRL_Pos (9UL) /*!< I2C_RX_FIFO_FULL_HLD_CTRL (Bit 9) */ +#define I2C2_I2C2_CON_REG_I2C_RX_FIFO_FULL_HLD_CTRL_Msk (0x200UL) /*!< I2C_RX_FIFO_FULL_HLD_CTRL (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_CON_REG_I2C_TX_EMPTY_CTRL_Pos (8UL) /*!< I2C_TX_EMPTY_CTRL (Bit 8) */ +#define I2C2_I2C2_CON_REG_I2C_TX_EMPTY_CTRL_Msk (0x100UL) /*!< I2C_TX_EMPTY_CTRL (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_CON_REG_I2C_STOP_DET_IFADDRESSED_Pos (7UL) /*!< I2C_STOP_DET_IFADDRESSED (Bit 7) */ +#define I2C2_I2C2_CON_REG_I2C_STOP_DET_IFADDRESSED_Msk (0x80UL) /*!< I2C_STOP_DET_IFADDRESSED (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_CON_REG_I2C_SLAVE_DISABLE_Pos (6UL) /*!< I2C_SLAVE_DISABLE (Bit 6) */ +#define I2C2_I2C2_CON_REG_I2C_SLAVE_DISABLE_Msk (0x40UL) /*!< I2C_SLAVE_DISABLE (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_CON_REG_I2C_RESTART_EN_Pos (5UL) /*!< I2C_RESTART_EN (Bit 5) */ +#define I2C2_I2C2_CON_REG_I2C_RESTART_EN_Msk (0x20UL) /*!< I2C_RESTART_EN (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_CON_REG_I2C_10BITADDR_MASTER_Pos (4UL) /*!< I2C_10BITADDR_MASTER (Bit 4) */ +#define I2C2_I2C2_CON_REG_I2C_10BITADDR_MASTER_Msk (0x10UL) /*!< I2C_10BITADDR_MASTER (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_CON_REG_I2C_10BITADDR_SLAVE_Pos (3UL) /*!< I2C_10BITADDR_SLAVE (Bit 3) */ +#define I2C2_I2C2_CON_REG_I2C_10BITADDR_SLAVE_Msk (0x8UL) /*!< I2C_10BITADDR_SLAVE (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_CON_REG_I2C_SPEED_Pos (1UL) /*!< I2C_SPEED (Bit 1) */ +#define I2C2_I2C2_CON_REG_I2C_SPEED_Msk (0x6UL) /*!< I2C_SPEED (Bitfield-Mask: 0x03) */ +#define I2C2_I2C2_CON_REG_I2C_MASTER_MODE_Pos (0UL) /*!< I2C_MASTER_MODE (Bit 0) */ +#define I2C2_I2C2_CON_REG_I2C_MASTER_MODE_Msk (0x1UL) /*!< I2C_MASTER_MODE (Bitfield-Mask: 0x01) */ +/* =================================================== I2C2_DATA_CMD_REG =================================================== */ +#define I2C2_I2C2_DATA_CMD_REG_I2C_RESTART_Pos (10UL) /*!< I2C_RESTART (Bit 10) */ +#define I2C2_I2C2_DATA_CMD_REG_I2C_RESTART_Msk (0x400UL) /*!< I2C_RESTART (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_DATA_CMD_REG_I2C_STOP_Pos (9UL) /*!< I2C_STOP (Bit 9) */ +#define I2C2_I2C2_DATA_CMD_REG_I2C_STOP_Msk (0x200UL) /*!< I2C_STOP (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_DATA_CMD_REG_I2C_CMD_Pos (8UL) /*!< I2C_CMD (Bit 8) */ +#define I2C2_I2C2_DATA_CMD_REG_I2C_CMD_Msk (0x100UL) /*!< I2C_CMD (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_DATA_CMD_REG_I2C_DAT_Pos (0UL) /*!< I2C_DAT (Bit 0) */ +#define I2C2_I2C2_DATA_CMD_REG_I2C_DAT_Msk (0xffUL) /*!< I2C_DAT (Bitfield-Mask: 0xff) */ +/* ==================================================== I2C2_DMA_CR_REG ==================================================== */ +#define I2C2_I2C2_DMA_CR_REG_TDMAE_Pos (1UL) /*!< TDMAE (Bit 1) */ +#define I2C2_I2C2_DMA_CR_REG_TDMAE_Msk (0x2UL) /*!< TDMAE (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_DMA_CR_REG_RDMAE_Pos (0UL) /*!< RDMAE (Bit 0) */ +#define I2C2_I2C2_DMA_CR_REG_RDMAE_Msk (0x1UL) /*!< RDMAE (Bitfield-Mask: 0x01) */ +/* =================================================== I2C2_DMA_RDLR_REG =================================================== */ +#define I2C2_I2C2_DMA_RDLR_REG_DMARDL_Pos (0UL) /*!< DMARDL (Bit 0) */ +#define I2C2_I2C2_DMA_RDLR_REG_DMARDL_Msk (0x1fUL) /*!< DMARDL (Bitfield-Mask: 0x1f) */ +/* =================================================== I2C2_DMA_TDLR_REG =================================================== */ +#define I2C2_I2C2_DMA_TDLR_REG_DMATDL_Pos (0UL) /*!< DMATDL (Bit 0) */ +#define I2C2_I2C2_DMA_TDLR_REG_DMATDL_Msk (0x1fUL) /*!< DMATDL (Bitfield-Mask: 0x1f) */ +/* ==================================================== I2C2_ENABLE_REG ==================================================== */ +#define I2C2_I2C2_ENABLE_REG_I2C_TX_CMD_BLOCK_Pos (2UL) /*!< I2C_TX_CMD_BLOCK (Bit 2) */ +#define I2C2_I2C2_ENABLE_REG_I2C_TX_CMD_BLOCK_Msk (0x4UL) /*!< I2C_TX_CMD_BLOCK (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_ENABLE_REG_I2C_ABORT_Pos (1UL) /*!< I2C_ABORT (Bit 1) */ +#define I2C2_I2C2_ENABLE_REG_I2C_ABORT_Msk (0x2UL) /*!< I2C_ABORT (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_ENABLE_REG_I2C_EN_Pos (0UL) /*!< I2C_EN (Bit 0) */ +#define I2C2_I2C2_ENABLE_REG_I2C_EN_Msk (0x1UL) /*!< I2C_EN (Bitfield-Mask: 0x01) */ +/* ================================================ I2C2_ENABLE_STATUS_REG ================================================= */ +#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Pos (2UL) /*!< SLV_RX_DATA_LOST (Bit 2) */ +#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Msk (0x4UL) /*!< SLV_RX_DATA_LOST (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Pos (1UL) /*!< SLV_DISABLED_WHILE_BUSY (Bit 1) */ +#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Msk (0x2UL) /*!< SLV_DISABLED_WHILE_BUSY (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_ENABLE_STATUS_REG_IC_EN_Pos (0UL) /*!< IC_EN (Bit 0) */ +#define I2C2_I2C2_ENABLE_STATUS_REG_IC_EN_Msk (0x1UL) /*!< IC_EN (Bitfield-Mask: 0x01) */ +/* ================================================= I2C2_FS_SCL_HCNT_REG ================================================== */ +#define I2C2_I2C2_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Pos (0UL) /*!< IC_FS_SCL_HCNT (Bit 0) */ +#define I2C2_I2C2_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Msk (0xffffUL) /*!< IC_FS_SCL_HCNT (Bitfield-Mask: 0xffff) */ +/* ================================================= I2C2_FS_SCL_LCNT_REG ================================================== */ +#define I2C2_I2C2_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Pos (0UL) /*!< IC_FS_SCL_LCNT (Bit 0) */ +#define I2C2_I2C2_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Msk (0xffffUL) /*!< IC_FS_SCL_LCNT (Bitfield-Mask: 0xffff) */ +/* =================================================== I2C2_HS_MADDR_REG =================================================== */ +#define I2C2_I2C2_HS_MADDR_REG_I2C_IC_HS_MAR_Pos (0UL) /*!< I2C_IC_HS_MAR (Bit 0) */ +#define I2C2_I2C2_HS_MADDR_REG_I2C_IC_HS_MAR_Msk (0x7UL) /*!< I2C_IC_HS_MAR (Bitfield-Mask: 0x07) */ +/* ================================================= I2C2_HS_SCL_HCNT_REG ================================================== */ +#define I2C2_I2C2_HS_SCL_HCNT_REG_IC_HS_SCL_HCNT_Pos (0UL) /*!< IC_HS_SCL_HCNT (Bit 0) */ +#define I2C2_I2C2_HS_SCL_HCNT_REG_IC_HS_SCL_HCNT_Msk (0xffffUL) /*!< IC_HS_SCL_HCNT (Bitfield-Mask: 0xffff) */ +/* ================================================= I2C2_HS_SCL_LCNT_REG ================================================== */ +#define I2C2_I2C2_HS_SCL_LCNT_REG_IC_HS_SCL_LCNT_Pos (0UL) /*!< IC_HS_SCL_LCNT (Bit 0) */ +#define I2C2_I2C2_HS_SCL_LCNT_REG_IC_HS_SCL_LCNT_Msk (0xffffUL) /*!< IC_HS_SCL_LCNT (Bitfield-Mask: 0xffff) */ +/* ================================================= I2C2_IC_FS_SPKLEN_REG ================================================= */ +#define I2C2_I2C2_IC_FS_SPKLEN_REG_I2C_FS_SPKLEN_Pos (0UL) /*!< I2C_FS_SPKLEN (Bit 0) */ +#define I2C2_I2C2_IC_FS_SPKLEN_REG_I2C_FS_SPKLEN_Msk (0xffUL) /*!< I2C_FS_SPKLEN (Bitfield-Mask: 0xff) */ +/* ================================================= I2C2_IC_HS_SPKLEN_REG ================================================= */ +#define I2C2_I2C2_IC_HS_SPKLEN_REG_I2C_HS_SPKLEN_Pos (0UL) /*!< I2C_HS_SPKLEN (Bit 0) */ +#define I2C2_I2C2_IC_HS_SPKLEN_REG_I2C_HS_SPKLEN_Msk (0xffUL) /*!< I2C_HS_SPKLEN (Bitfield-Mask: 0xff) */ +/* ================================================== I2C2_INTR_MASK_REG =================================================== */ +#define I2C2_I2C2_INTR_MASK_REG_M_SCL_STUCK_AT_LOW_Pos (14UL) /*!< M_SCL_STUCK_AT_LOW (Bit 14) */ +#define I2C2_I2C2_INTR_MASK_REG_M_SCL_STUCK_AT_LOW_Msk (0x4000UL) /*!< M_SCL_STUCK_AT_LOW (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_MASK_REG_M_MASTER_ON_HOLD_Pos (13UL) /*!< M_MASTER_ON_HOLD (Bit 13) */ +#define I2C2_I2C2_INTR_MASK_REG_M_MASTER_ON_HOLD_Msk (0x2000UL) /*!< M_MASTER_ON_HOLD (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_MASK_REG_M_RESTART_DET_Pos (12UL) /*!< M_RESTART_DET (Bit 12) */ +#define I2C2_I2C2_INTR_MASK_REG_M_RESTART_DET_Msk (0x1000UL) /*!< M_RESTART_DET (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_MASK_REG_M_GEN_CALL_Pos (11UL) /*!< M_GEN_CALL (Bit 11) */ +#define I2C2_I2C2_INTR_MASK_REG_M_GEN_CALL_Msk (0x800UL) /*!< M_GEN_CALL (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_MASK_REG_M_START_DET_Pos (10UL) /*!< M_START_DET (Bit 10) */ +#define I2C2_I2C2_INTR_MASK_REG_M_START_DET_Msk (0x400UL) /*!< M_START_DET (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_MASK_REG_M_STOP_DET_Pos (9UL) /*!< M_STOP_DET (Bit 9) */ +#define I2C2_I2C2_INTR_MASK_REG_M_STOP_DET_Msk (0x200UL) /*!< M_STOP_DET (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_MASK_REG_M_ACTIVITY_Pos (8UL) /*!< M_ACTIVITY (Bit 8) */ +#define I2C2_I2C2_INTR_MASK_REG_M_ACTIVITY_Msk (0x100UL) /*!< M_ACTIVITY (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_MASK_REG_M_RX_DONE_Pos (7UL) /*!< M_RX_DONE (Bit 7) */ +#define I2C2_I2C2_INTR_MASK_REG_M_RX_DONE_Msk (0x80UL) /*!< M_RX_DONE (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_MASK_REG_M_TX_ABRT_Pos (6UL) /*!< M_TX_ABRT (Bit 6) */ +#define I2C2_I2C2_INTR_MASK_REG_M_TX_ABRT_Msk (0x40UL) /*!< M_TX_ABRT (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_MASK_REG_M_RD_REQ_Pos (5UL) /*!< M_RD_REQ (Bit 5) */ +#define I2C2_I2C2_INTR_MASK_REG_M_RD_REQ_Msk (0x20UL) /*!< M_RD_REQ (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_MASK_REG_M_TX_EMPTY_Pos (4UL) /*!< M_TX_EMPTY (Bit 4) */ +#define I2C2_I2C2_INTR_MASK_REG_M_TX_EMPTY_Msk (0x10UL) /*!< M_TX_EMPTY (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_MASK_REG_M_TX_OVER_Pos (3UL) /*!< M_TX_OVER (Bit 3) */ +#define I2C2_I2C2_INTR_MASK_REG_M_TX_OVER_Msk (0x8UL) /*!< M_TX_OVER (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_MASK_REG_M_RX_FULL_Pos (2UL) /*!< M_RX_FULL (Bit 2) */ +#define I2C2_I2C2_INTR_MASK_REG_M_RX_FULL_Msk (0x4UL) /*!< M_RX_FULL (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_MASK_REG_M_RX_OVER_Pos (1UL) /*!< M_RX_OVER (Bit 1) */ +#define I2C2_I2C2_INTR_MASK_REG_M_RX_OVER_Msk (0x2UL) /*!< M_RX_OVER (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_MASK_REG_M_RX_UNDER_Pos (0UL) /*!< M_RX_UNDER (Bit 0) */ +#define I2C2_I2C2_INTR_MASK_REG_M_RX_UNDER_Msk (0x1UL) /*!< M_RX_UNDER (Bitfield-Mask: 0x01) */ +/* ================================================== I2C2_INTR_STAT_REG =================================================== */ +#define I2C2_I2C2_INTR_STAT_REG_R_SCL_STUCK_AT_LOW_Pos (14UL) /*!< R_SCL_STUCK_AT_LOW (Bit 14) */ +#define I2C2_I2C2_INTR_STAT_REG_R_SCL_STUCK_AT_LOW_Msk (0x4000UL) /*!< R_SCL_STUCK_AT_LOW (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_STAT_REG_R_MASTER_ON_HOLD_Pos (13UL) /*!< R_MASTER_ON_HOLD (Bit 13) */ +#define I2C2_I2C2_INTR_STAT_REG_R_MASTER_ON_HOLD_Msk (0x2000UL) /*!< R_MASTER_ON_HOLD (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_STAT_REG_R_RESTART_DET_Pos (12UL) /*!< R_RESTART_DET (Bit 12) */ +#define I2C2_I2C2_INTR_STAT_REG_R_RESTART_DET_Msk (0x1000UL) /*!< R_RESTART_DET (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_STAT_REG_R_GEN_CALL_Pos (11UL) /*!< R_GEN_CALL (Bit 11) */ +#define I2C2_I2C2_INTR_STAT_REG_R_GEN_CALL_Msk (0x800UL) /*!< R_GEN_CALL (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_STAT_REG_R_START_DET_Pos (10UL) /*!< R_START_DET (Bit 10) */ +#define I2C2_I2C2_INTR_STAT_REG_R_START_DET_Msk (0x400UL) /*!< R_START_DET (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_STAT_REG_R_STOP_DET_Pos (9UL) /*!< R_STOP_DET (Bit 9) */ +#define I2C2_I2C2_INTR_STAT_REG_R_STOP_DET_Msk (0x200UL) /*!< R_STOP_DET (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_STAT_REG_R_ACTIVITY_Pos (8UL) /*!< R_ACTIVITY (Bit 8) */ +#define I2C2_I2C2_INTR_STAT_REG_R_ACTIVITY_Msk (0x100UL) /*!< R_ACTIVITY (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_STAT_REG_R_RX_DONE_Pos (7UL) /*!< R_RX_DONE (Bit 7) */ +#define I2C2_I2C2_INTR_STAT_REG_R_RX_DONE_Msk (0x80UL) /*!< R_RX_DONE (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_STAT_REG_R_TX_ABRT_Pos (6UL) /*!< R_TX_ABRT (Bit 6) */ +#define I2C2_I2C2_INTR_STAT_REG_R_TX_ABRT_Msk (0x40UL) /*!< R_TX_ABRT (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_STAT_REG_R_RD_REQ_Pos (5UL) /*!< R_RD_REQ (Bit 5) */ +#define I2C2_I2C2_INTR_STAT_REG_R_RD_REQ_Msk (0x20UL) /*!< R_RD_REQ (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_STAT_REG_R_TX_EMPTY_Pos (4UL) /*!< R_TX_EMPTY (Bit 4) */ +#define I2C2_I2C2_INTR_STAT_REG_R_TX_EMPTY_Msk (0x10UL) /*!< R_TX_EMPTY (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_STAT_REG_R_TX_OVER_Pos (3UL) /*!< R_TX_OVER (Bit 3) */ +#define I2C2_I2C2_INTR_STAT_REG_R_TX_OVER_Msk (0x8UL) /*!< R_TX_OVER (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_STAT_REG_R_RX_FULL_Pos (2UL) /*!< R_RX_FULL (Bit 2) */ +#define I2C2_I2C2_INTR_STAT_REG_R_RX_FULL_Msk (0x4UL) /*!< R_RX_FULL (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_STAT_REG_R_RX_OVER_Pos (1UL) /*!< R_RX_OVER (Bit 1) */ +#define I2C2_I2C2_INTR_STAT_REG_R_RX_OVER_Msk (0x2UL) /*!< R_RX_OVER (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_INTR_STAT_REG_R_RX_UNDER_Pos (0UL) /*!< R_RX_UNDER (Bit 0) */ +#define I2C2_I2C2_INTR_STAT_REG_R_RX_UNDER_Msk (0x1UL) /*!< R_RX_UNDER (Bitfield-Mask: 0x01) */ +/* ================================================ I2C2_RAW_INTR_STAT_REG ================================================= */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_SCL_STUCK_AT_LOW_Pos (14UL) /*!< SCL_STUCK_AT_LOW (Bit 14) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_SCL_STUCK_AT_LOW_Msk (0x4000UL) /*!< SCL_STUCK_AT_LOW (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_MASTER_ON_HOLD_Pos (13UL) /*!< MASTER_ON_HOLD (Bit 13) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_MASTER_ON_HOLD_Msk (0x2000UL) /*!< MASTER_ON_HOLD (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_RESTART_DET_Pos (12UL) /*!< RESTART_DET (Bit 12) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_RESTART_DET_Msk (0x1000UL) /*!< RESTART_DET (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_GEN_CALL_Pos (11UL) /*!< GEN_CALL (Bit 11) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_GEN_CALL_Msk (0x800UL) /*!< GEN_CALL (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_START_DET_Pos (10UL) /*!< START_DET (Bit 10) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_START_DET_Msk (0x400UL) /*!< START_DET (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_STOP_DET_Pos (9UL) /*!< STOP_DET (Bit 9) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_STOP_DET_Msk (0x200UL) /*!< STOP_DET (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_ACTIVITY_Pos (8UL) /*!< ACTIVITY (Bit 8) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_ACTIVITY_Msk (0x100UL) /*!< ACTIVITY (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_DONE_Pos (7UL) /*!< RX_DONE (Bit 7) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_DONE_Msk (0x80UL) /*!< RX_DONE (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_ABRT_Pos (6UL) /*!< TX_ABRT (Bit 6) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_ABRT_Msk (0x40UL) /*!< TX_ABRT (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_RD_REQ_Pos (5UL) /*!< RD_REQ (Bit 5) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_RD_REQ_Msk (0x20UL) /*!< RD_REQ (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_EMPTY_Pos (4UL) /*!< TX_EMPTY (Bit 4) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_EMPTY_Msk (0x10UL) /*!< TX_EMPTY (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_OVER_Pos (3UL) /*!< TX_OVER (Bit 3) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_OVER_Msk (0x8UL) /*!< TX_OVER (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_FULL_Pos (2UL) /*!< RX_FULL (Bit 2) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_FULL_Msk (0x4UL) /*!< RX_FULL (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_OVER_Pos (1UL) /*!< RX_OVER (Bit 1) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_OVER_Msk (0x2UL) /*!< RX_OVER (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_UNDER_Pos (0UL) /*!< RX_UNDER (Bit 0) */ +#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_UNDER_Msk (0x1UL) /*!< RX_UNDER (Bitfield-Mask: 0x01) */ +/* ==================================================== I2C2_RXFLR_REG ===================================================== */ +#define I2C2_I2C2_RXFLR_REG_RXFLR_Pos (0UL) /*!< RXFLR (Bit 0) */ +#define I2C2_I2C2_RXFLR_REG_RXFLR_Msk (0x3fUL) /*!< RXFLR (Bitfield-Mask: 0x3f) */ +/* ==================================================== I2C2_RX_TL_REG ===================================================== */ +#define I2C2_I2C2_RX_TL_REG_RX_TL_Pos (0UL) /*!< RX_TL (Bit 0) */ +#define I2C2_I2C2_RX_TL_REG_RX_TL_Msk (0x1fUL) /*!< RX_TL (Bitfield-Mask: 0x1f) */ +/* ===================================================== I2C2_SAR_REG ====================================================== */ +#define I2C2_I2C2_SAR_REG_IC_SAR_Pos (0UL) /*!< IC_SAR (Bit 0) */ +#define I2C2_I2C2_SAR_REG_IC_SAR_Msk (0x3ffUL) /*!< IC_SAR (Bitfield-Mask: 0x3ff) */ +/* =================================================== I2C2_SDA_HOLD_REG =================================================== */ +#define I2C2_I2C2_SDA_HOLD_REG_I2C_SDA_RX_HOLD_Pos (16UL) /*!< I2C_SDA_RX_HOLD (Bit 16) */ +#define I2C2_I2C2_SDA_HOLD_REG_I2C_SDA_RX_HOLD_Msk (0xff0000UL) /*!< I2C_SDA_RX_HOLD (Bitfield-Mask: 0xff) */ +#define I2C2_I2C2_SDA_HOLD_REG_I2C_SDA_TX_HOLD_Pos (0UL) /*!< I2C_SDA_TX_HOLD (Bit 0) */ +#define I2C2_I2C2_SDA_HOLD_REG_I2C_SDA_TX_HOLD_Msk (0xffffUL) /*!< I2C_SDA_TX_HOLD (Bitfield-Mask: 0xffff) */ +/* ================================================== I2C2_SDA_SETUP_REG =================================================== */ +#define I2C2_I2C2_SDA_SETUP_REG_SDA_SETUP_Pos (0UL) /*!< SDA_SETUP (Bit 0) */ +#define I2C2_I2C2_SDA_SETUP_REG_SDA_SETUP_Msk (0xffUL) /*!< SDA_SETUP (Bitfield-Mask: 0xff) */ +/* ================================================= I2C2_SS_SCL_HCNT_REG ================================================== */ +#define I2C2_I2C2_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Pos (0UL) /*!< IC_SS_SCL_HCNT (Bit 0) */ +#define I2C2_I2C2_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Msk (0xffffUL) /*!< IC_SS_SCL_HCNT (Bitfield-Mask: 0xffff) */ +/* ================================================= I2C2_SS_SCL_LCNT_REG ================================================== */ +#define I2C2_I2C2_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Pos (0UL) /*!< IC_SS_SCL_LCNT (Bit 0) */ +#define I2C2_I2C2_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Msk (0xffffUL) /*!< IC_SS_SCL_LCNT (Bitfield-Mask: 0xffff) */ +/* ==================================================== I2C2_STATUS_REG ==================================================== */ +#define I2C2_I2C2_STATUS_REG_LV_HOLD_RX_FIFO_FULL_Pos (10UL) /*!< LV_HOLD_RX_FIFO_FULL (Bit 10) */ +#define I2C2_I2C2_STATUS_REG_LV_HOLD_RX_FIFO_FULL_Msk (0x400UL) /*!< LV_HOLD_RX_FIFO_FULL (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_STATUS_REG_SLV_HOLD_TX_FIFO_EMPTY_Pos (9UL) /*!< SLV_HOLD_TX_FIFO_EMPTY (Bit 9) */ +#define I2C2_I2C2_STATUS_REG_SLV_HOLD_TX_FIFO_EMPTY_Msk (0x200UL) /*!< SLV_HOLD_TX_FIFO_EMPTY (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_STATUS_REG_MST_HOLD_RX_FIFO_FULL_Pos (8UL) /*!< MST_HOLD_RX_FIFO_FULL (Bit 8) */ +#define I2C2_I2C2_STATUS_REG_MST_HOLD_RX_FIFO_FULL_Msk (0x100UL) /*!< MST_HOLD_RX_FIFO_FULL (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_STATUS_REG_MST_HOLD_TX_FIFO_EMPTY_Pos (7UL) /*!< MST_HOLD_TX_FIFO_EMPTY (Bit 7) */ +#define I2C2_I2C2_STATUS_REG_MST_HOLD_TX_FIFO_EMPTY_Msk (0x80UL) /*!< MST_HOLD_TX_FIFO_EMPTY (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_STATUS_REG_SLV_ACTIVITY_Pos (6UL) /*!< SLV_ACTIVITY (Bit 6) */ +#define I2C2_I2C2_STATUS_REG_SLV_ACTIVITY_Msk (0x40UL) /*!< SLV_ACTIVITY (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_STATUS_REG_MST_ACTIVITY_Pos (5UL) /*!< MST_ACTIVITY (Bit 5) */ +#define I2C2_I2C2_STATUS_REG_MST_ACTIVITY_Msk (0x20UL) /*!< MST_ACTIVITY (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_STATUS_REG_RFF_Pos (4UL) /*!< RFF (Bit 4) */ +#define I2C2_I2C2_STATUS_REG_RFF_Msk (0x10UL) /*!< RFF (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_STATUS_REG_RFNE_Pos (3UL) /*!< RFNE (Bit 3) */ +#define I2C2_I2C2_STATUS_REG_RFNE_Msk (0x8UL) /*!< RFNE (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_STATUS_REG_TFE_Pos (2UL) /*!< TFE (Bit 2) */ +#define I2C2_I2C2_STATUS_REG_TFE_Msk (0x4UL) /*!< TFE (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_STATUS_REG_TFNF_Pos (1UL) /*!< TFNF (Bit 1) */ +#define I2C2_I2C2_STATUS_REG_TFNF_Msk (0x2UL) /*!< TFNF (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_STATUS_REG_I2C_ACTIVITY_Pos (0UL) /*!< I2C_ACTIVITY (Bit 0) */ +#define I2C2_I2C2_STATUS_REG_I2C_ACTIVITY_Msk (0x1UL) /*!< I2C_ACTIVITY (Bitfield-Mask: 0x01) */ +/* ===================================================== I2C2_TAR_REG ====================================================== */ +#define I2C2_I2C2_TAR_REG_SPECIAL_Pos (11UL) /*!< SPECIAL (Bit 11) */ +#define I2C2_I2C2_TAR_REG_SPECIAL_Msk (0x800UL) /*!< SPECIAL (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_TAR_REG_GC_OR_START_Pos (10UL) /*!< GC_OR_START (Bit 10) */ +#define I2C2_I2C2_TAR_REG_GC_OR_START_Msk (0x400UL) /*!< GC_OR_START (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_TAR_REG_IC_TAR_Pos (0UL) /*!< IC_TAR (Bit 0) */ +#define I2C2_I2C2_TAR_REG_IC_TAR_Msk (0x3ffUL) /*!< IC_TAR (Bitfield-Mask: 0x3ff) */ +/* ==================================================== I2C2_TXFLR_REG ===================================================== */ +#define I2C2_I2C2_TXFLR_REG_TXFLR_Pos (0UL) /*!< TXFLR (Bit 0) */ +#define I2C2_I2C2_TXFLR_REG_TXFLR_Msk (0x3fUL) /*!< TXFLR (Bitfield-Mask: 0x3f) */ +/* ================================================ I2C2_TX_ABRT_SOURCE_REG ================================================ */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_USER_ABRT_Pos (16UL) /*!< ABRT_USER_ABRT (Bit 16) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_USER_ABRT_Msk (0x10000UL) /*!< ABRT_USER_ABRT (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Pos (15UL) /*!< ABRT_SLVRD_INTX (Bit 15) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Msk (0x8000UL) /*!< ABRT_SLVRD_INTX (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Pos (14UL) /*!< ABRT_SLV_ARBLOST (Bit 14) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Msk (0x4000UL) /*!< ABRT_SLV_ARBLOST (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Pos (13UL) /*!< ABRT_SLVFLUSH_TXFIFO (Bit 13) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Msk (0x2000UL) /*!< ABRT_SLVFLUSH_TXFIFO (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ARB_LOST_Pos (12UL) /*!< ARB_LOST (Bit 12) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ARB_LOST_Msk (0x1000UL) /*!< ARB_LOST (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Pos (11UL) /*!< ABRT_MASTER_DIS (Bit 11) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Msk (0x800UL) /*!< ABRT_MASTER_DIS (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Pos (10UL) /*!< ABRT_10B_RD_NORSTRT (Bit 10) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Msk (0x400UL) /*!< ABRT_10B_RD_NORSTRT (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Pos (9UL) /*!< ABRT_SBYTE_NORSTRT (Bit 9) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Msk (0x200UL) /*!< ABRT_SBYTE_NORSTRT (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Pos (8UL) /*!< ABRT_HS_NORSTRT (Bit 8) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Msk (0x100UL) /*!< ABRT_HS_NORSTRT (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Pos (7UL) /*!< ABRT_SBYTE_ACKDET (Bit 7) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Msk (0x80UL) /*!< ABRT_SBYTE_ACKDET (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Pos (6UL) /*!< ABRT_HS_ACKDET (Bit 6) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Msk (0x40UL) /*!< ABRT_HS_ACKDET (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Pos (5UL) /*!< ABRT_GCALL_READ (Bit 5) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Msk (0x20UL) /*!< ABRT_GCALL_READ (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Pos (4UL) /*!< ABRT_GCALL_NOACK (Bit 4) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Msk (0x10UL) /*!< ABRT_GCALL_NOACK (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Pos (3UL) /*!< ABRT_TXDATA_NOACK (Bit 3) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Msk (0x8UL) /*!< ABRT_TXDATA_NOACK (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Pos (2UL) /*!< ABRT_10ADDR2_NOACK (Bit 2) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Msk (0x4UL) /*!< ABRT_10ADDR2_NOACK (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Pos (1UL) /*!< ABRT_10ADDR1_NOACK (Bit 1) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Msk (0x2UL) /*!< ABRT_10ADDR1_NOACK (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Pos (0UL) /*!< ABRT_7B_ADDR_NOACK (Bit 0) */ +#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Msk (0x1UL) /*!< ABRT_7B_ADDR_NOACK (Bitfield-Mask: 0x01) */ +/* ==================================================== I2C2_TX_TL_REG ===================================================== */ +#define I2C2_I2C2_TX_TL_REG_TX_TL_Pos (0UL) /*!< TX_TL (Bit 0) */ +#define I2C2_I2C2_TX_TL_REG_TX_TL_Msk (0x1fUL) /*!< TX_TL (Bitfield-Mask: 0x1f) */ + + +/* =========================================================================================================================== */ +/* ================ LCDC ================ */ +/* =========================================================================================================================== */ + +/* ================================================= LCDC_BACKPORCHXY_REG ================================================== */ +#define LCDC_LCDC_BACKPORCHXY_REG_LCDC_BPORCH_X_Pos (16UL) /*!< LCDC_BPORCH_X (Bit 16) */ +#define LCDC_LCDC_BACKPORCHXY_REG_LCDC_BPORCH_X_Msk (0xffff0000UL) /*!< LCDC_BPORCH_X (Bitfield-Mask: 0xffff) */ +#define LCDC_LCDC_BACKPORCHXY_REG_LCDC_BPORCH_Y_Pos (0UL) /*!< LCDC_BPORCH_Y (Bit 0) */ +#define LCDC_LCDC_BACKPORCHXY_REG_LCDC_BPORCH_Y_Msk (0xffffUL) /*!< LCDC_BPORCH_Y (Bitfield-Mask: 0xffff) */ +/* =================================================== LCDC_BGCOLOR_REG ==================================================== */ +#define LCDC_LCDC_BGCOLOR_REG_LCDC_BG_RED_Pos (24UL) /*!< LCDC_BG_RED (Bit 24) */ +#define LCDC_LCDC_BGCOLOR_REG_LCDC_BG_RED_Msk (0xff000000UL) /*!< LCDC_BG_RED (Bitfield-Mask: 0xff) */ +#define LCDC_LCDC_BGCOLOR_REG_LCDC_BG_GREEN_Pos (16UL) /*!< LCDC_BG_GREEN (Bit 16) */ +#define LCDC_LCDC_BGCOLOR_REG_LCDC_BG_GREEN_Msk (0xff0000UL) /*!< LCDC_BG_GREEN (Bitfield-Mask: 0xff) */ +#define LCDC_LCDC_BGCOLOR_REG_LCDC_BG_BLUE_Pos (8UL) /*!< LCDC_BG_BLUE (Bit 8) */ +#define LCDC_LCDC_BGCOLOR_REG_LCDC_BG_BLUE_Msk (0xff00UL) /*!< LCDC_BG_BLUE (Bitfield-Mask: 0xff) */ +#define LCDC_LCDC_BGCOLOR_REG_LCDC_BG_ALPHA_Pos (0UL) /*!< LCDC_BG_ALPHA (Bit 0) */ +#define LCDC_LCDC_BGCOLOR_REG_LCDC_BG_ALPHA_Msk (0xffUL) /*!< LCDC_BG_ALPHA (Bitfield-Mask: 0xff) */ +/* ================================================== LCDC_BLANKINGXY_REG ================================================== */ +#define LCDC_LCDC_BLANKINGXY_REG_LCDC_BLANKING_X_Pos (16UL) /*!< LCDC_BLANKING_X (Bit 16) */ +#define LCDC_LCDC_BLANKINGXY_REG_LCDC_BLANKING_X_Msk (0xffff0000UL) /*!< LCDC_BLANKING_X (Bitfield-Mask: 0xffff) */ +#define LCDC_LCDC_BLANKINGXY_REG_LCDC_BLANKING_Y_Pos (0UL) /*!< LCDC_BLANKING_Y (Bit 0) */ +#define LCDC_LCDC_BLANKINGXY_REG_LCDC_BLANKING_Y_Msk (0xffffUL) /*!< LCDC_BLANKING_Y (Bitfield-Mask: 0xffff) */ +/* =================================================== LCDC_CLKCTRL_REG ==================================================== */ +#define LCDC_LCDC_CLKCTRL_REG_LCDC_SEC_CLK_DIV_Pos (27UL) /*!< LCDC_SEC_CLK_DIV (Bit 27) */ +#define LCDC_LCDC_CLKCTRL_REG_LCDC_SEC_CLK_DIV_Msk (0xf8000000UL) /*!< LCDC_SEC_CLK_DIV (Bitfield-Mask: 0x1f) */ +#define LCDC_LCDC_CLKCTRL_REG_LCDC_DMA_HOLD_Pos (8UL) /*!< LCDC_DMA_HOLD (Bit 8) */ +#define LCDC_LCDC_CLKCTRL_REG_LCDC_DMA_HOLD_Msk (0x3f00UL) /*!< LCDC_DMA_HOLD (Bitfield-Mask: 0x3f) */ +#define LCDC_LCDC_CLKCTRL_REG_LCDC_CLK_DIV_Pos (0UL) /*!< LCDC_CLK_DIV (Bit 0) */ +#define LCDC_LCDC_CLKCTRL_REG_LCDC_CLK_DIV_Msk (0x3fUL) /*!< LCDC_CLK_DIV (Bitfield-Mask: 0x3f) */ +/* ===================================================== LCDC_CRC_REG ====================================================== */ +#define LCDC_LCDC_CRC_REG_LCDC_CRC_Pos (0UL) /*!< LCDC_CRC (Bit 0) */ +#define LCDC_LCDC_CRC_REG_LCDC_CRC_Msk (0xffffffffUL) /*!< LCDC_CRC (Bitfield-Mask: 0xffffffff) */ +/* =================================================== LCDC_DBIB_CFG_REG =================================================== */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_TE_DIS_Pos (31UL) /*!< LCDC_DBIB_TE_DIS (Bit 31) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_TE_DIS_Msk (0x80000000UL) /*!< LCDC_DBIB_TE_DIS (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_CSX_FORCE_Pos (30UL) /*!< LCDC_DBIB_CSX_FORCE (Bit 30) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_CSX_FORCE_Msk (0x40000000UL) /*!< LCDC_DBIB_CSX_FORCE (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_CSX_FORCE_VAL_Pos (29UL) /*!< LCDC_DBIB_CSX_FORCE_VAL (Bit 29) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_CSX_FORCE_VAL_Msk (0x20000000UL) /*!< LCDC_DBIB_CSX_FORCE_VAL (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_PAD_Pos (28UL) /*!< LCDC_DBIB_SPI_PAD (Bit 28) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_PAD_Msk (0x10000000UL) /*!< LCDC_DBIB_SPI_PAD (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_RESX_Pos (25UL) /*!< LCDC_DBIB_RESX (Bit 25) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_RESX_Msk (0x2000000UL) /*!< LCDC_DBIB_RESX (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_DMA_EN_Pos (24UL) /*!< LCDC_DBIB_DMA_EN (Bit 24) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_DMA_EN_Msk (0x1000000UL) /*!< LCDC_DBIB_DMA_EN (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI3_EN_Pos (23UL) /*!< LCDC_DBIB_SPI3_EN (Bit 23) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI3_EN_Msk (0x800000UL) /*!< LCDC_DBIB_SPI3_EN (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI4_EN_Pos (22UL) /*!< LCDC_DBIB_SPI4_EN (Bit 22) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI4_EN_Msk (0x400000UL) /*!< LCDC_DBIB_SPI4_EN (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_CPHA_Pos (20UL) /*!< LCDC_DBIB_SPI_CPHA (Bit 20) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_CPHA_Msk (0x100000UL) /*!< LCDC_DBIB_SPI_CPHA (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_CPOL_Pos (19UL) /*!< LCDC_DBIB_SPI_CPOL (Bit 19) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_CPOL_Msk (0x80000UL) /*!< LCDC_DBIB_SPI_CPOL (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_JDI_Pos (18UL) /*!< LCDC_DBIB_SPI_JDI (Bit 18) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_JDI_Msk (0x40000UL) /*!< LCDC_DBIB_SPI_JDI (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_HOLD_Pos (17UL) /*!< LCDC_DBIB_SPI_HOLD (Bit 17) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_HOLD_Msk (0x20000UL) /*!< LCDC_DBIB_SPI_HOLD (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_INV_ADDR_Pos (16UL) /*!< LCDC_DBIB_SPI_INV_ADDR (Bit 16) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_INV_ADDR_Msk (0x10000UL) /*!< LCDC_DBIB_SPI_INV_ADDR (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_INV_DATA_Pos (15UL) /*!< LCDC_DBIB_INV_DATA (Bit 15) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_INV_DATA_Msk (0x8000UL) /*!< LCDC_DBIB_INV_DATA (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_JDI_INV_PIX_Pos (14UL) /*!< LCDC_DBIB_JDI_INV_PIX (Bit 14) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_JDI_INV_PIX_Msk (0x4000UL) /*!< LCDC_DBIB_JDI_INV_PIX (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_JDI_SOFT_RST_Pos (13UL) /*!< LCDC_DBIB_JDI_SOFT_RST (Bit 13) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_JDI_SOFT_RST_Msk (0x2000UL) /*!< LCDC_DBIB_JDI_SOFT_RST (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_FMT_Pos (0UL) /*!< LCDC_DBIB_FMT (Bit 0) */ +#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_FMT_Msk (0x1fUL) /*!< LCDC_DBIB_FMT (Bitfield-Mask: 0x1f) */ +/* =================================================== LCDC_DBIB_CMD_REG =================================================== */ +#define LCDC_LCDC_DBIB_CMD_REG_LCDC_DBIB_CMD_SEND_Pos (30UL) /*!< LCDC_DBIB_CMD_SEND (Bit 30) */ +#define LCDC_LCDC_DBIB_CMD_REG_LCDC_DBIB_CMD_SEND_Msk (0x40000000UL) /*!< LCDC_DBIB_CMD_SEND (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_DBIB_CMD_REG_LCDC_DBIB_CMD_STORE_Pos (27UL) /*!< LCDC_DBIB_CMD_STORE (Bit 27) */ +#define LCDC_LCDC_DBIB_CMD_REG_LCDC_DBIB_CMD_STORE_Msk (0x8000000UL) /*!< LCDC_DBIB_CMD_STORE (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_DBIB_CMD_REG_LCDC_DBIB_CMD_VAL_Pos (0UL) /*!< LCDC_DBIB_CMD_VAL (Bit 0) */ +#define LCDC_LCDC_DBIB_CMD_REG_LCDC_DBIB_CMD_VAL_Msk (0xffffUL) /*!< LCDC_DBIB_CMD_VAL (Bitfield-Mask: 0xffff) */ +/* ================================================= LCDC_FRONTPORCHXY_REG ================================================= */ +#define LCDC_LCDC_FRONTPORCHXY_REG_LCDC_FPORCH_X_Pos (16UL) /*!< LCDC_FPORCH_X (Bit 16) */ +#define LCDC_LCDC_FRONTPORCHXY_REG_LCDC_FPORCH_X_Msk (0xffff0000UL) /*!< LCDC_FPORCH_X (Bitfield-Mask: 0xffff) */ +#define LCDC_LCDC_FRONTPORCHXY_REG_LCDC_FPORCH_Y_Pos (0UL) /*!< LCDC_FPORCH_Y (Bit 0) */ +#define LCDC_LCDC_FRONTPORCHXY_REG_LCDC_FPORCH_Y_Msk (0xffffUL) /*!< LCDC_FPORCH_Y (Bitfield-Mask: 0xffff) */ +/* ===================================================== LCDC_GPIO_REG ===================================================== */ +#define LCDC_LCDC_GPIO_REG_LCDC_TE_INV_Pos (1UL) /*!< LCDC_TE_INV (Bit 1) */ +#define LCDC_LCDC_GPIO_REG_LCDC_TE_INV_Msk (0x2UL) /*!< LCDC_TE_INV (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_GPIO_REG_LCDC_PARIF_SEL_Pos (0UL) /*!< LCDC_PARIF_SEL (Bit 0) */ +#define LCDC_LCDC_GPIO_REG_LCDC_PARIF_SEL_Msk (0x1UL) /*!< LCDC_PARIF_SEL (Bitfield-Mask: 0x01) */ +/* ==================================================== LCDC_IDREG_REG ===================================================== */ +#define LCDC_LCDC_IDREG_REG_LCDC_ID_Pos (0UL) /*!< LCDC_ID (Bit 0) */ +#define LCDC_LCDC_IDREG_REG_LCDC_ID_Msk (0xffffffffUL) /*!< LCDC_ID (Bitfield-Mask: 0xffffffff) */ +/* ================================================== LCDC_INTERRUPT_REG =================================================== */ +#define LCDC_LCDC_INTERRUPT_REG_LCDC_IRQ_TRIGGER_SEL_Pos (31UL) /*!< LCDC_IRQ_TRIGGER_SEL (Bit 31) */ +#define LCDC_LCDC_INTERRUPT_REG_LCDC_IRQ_TRIGGER_SEL_Msk (0x80000000UL) /*!< LCDC_IRQ_TRIGGER_SEL (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_INTERRUPT_REG_LCDC_FRAME_END_IRQ_EN_Pos (5UL) /*!< LCDC_FRAME_END_IRQ_EN (Bit 5) */ +#define LCDC_LCDC_INTERRUPT_REG_LCDC_FRAME_END_IRQ_EN_Msk (0x20UL) /*!< LCDC_FRAME_END_IRQ_EN (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_INTERRUPT_REG_LCDC_TE_IRQ_EN_Pos (3UL) /*!< LCDC_TE_IRQ_EN (Bit 3) */ +#define LCDC_LCDC_INTERRUPT_REG_LCDC_TE_IRQ_EN_Msk (0x8UL) /*!< LCDC_TE_IRQ_EN (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_INTERRUPT_REG_LCDC_HSYNC_IRQ_EN_Pos (1UL) /*!< LCDC_HSYNC_IRQ_EN (Bit 1) */ +#define LCDC_LCDC_INTERRUPT_REG_LCDC_HSYNC_IRQ_EN_Msk (0x2UL) /*!< LCDC_HSYNC_IRQ_EN (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_INTERRUPT_REG_LCDC_VSYNC_IRQ_EN_Pos (0UL) /*!< LCDC_VSYNC_IRQ_EN (Bit 0) */ +#define LCDC_LCDC_INTERRUPT_REG_LCDC_VSYNC_IRQ_EN_Msk (0x1UL) /*!< LCDC_VSYNC_IRQ_EN (Bitfield-Mask: 0x01) */ +/* ============================================== LCDC_JDI_ENB_END_HLINE_REG =============================================== */ +#define LCDC_LCDC_JDI_ENB_END_HLINE_REG_LCDC_JDI_ENB_END_HLINE_Pos (0UL) /*!< LCDC_JDI_ENB_END_HLINE (Bit 0) */ +#define LCDC_LCDC_JDI_ENB_END_HLINE_REG_LCDC_JDI_ENB_END_HLINE_Msk (0xffffffffUL) /*!< LCDC_JDI_ENB_END_HLINE (Bitfield-Mask: 0xffffffff) */ +/* ============================================== LCDC_JDI_ENB_START_CLK_REG =============================================== */ +#define LCDC_LCDC_JDI_ENB_START_CLK_REG_LCDC_JDI_ENB_START_CLK_Pos (0UL) /*!< LCDC_JDI_ENB_START_CLK (Bit 0) */ +#define LCDC_LCDC_JDI_ENB_START_CLK_REG_LCDC_JDI_ENB_START_CLK_Msk (0xffffffffUL) /*!< LCDC_JDI_ENB_START_CLK (Bitfield-Mask: 0xffffffff) */ +/* ============================================= LCDC_JDI_ENB_START_HLINE_REG ============================================== */ +#define LCDC_LCDC_JDI_ENB_START_HLINE_REG_LCDC_JDI_ENB_START_HLINE_Pos (0UL) /*!< LCDC_JDI_ENB_START_HLINE (Bit 0) */ +#define LCDC_LCDC_JDI_ENB_START_HLINE_REG_LCDC_JDI_ENB_START_HLINE_Msk (0xffffffffUL) /*!< LCDC_JDI_ENB_START_HLINE (Bitfield-Mask: 0xffffffff) */ +/* ============================================== LCDC_JDI_ENB_WIDTH_CLK_REG =============================================== */ +#define LCDC_LCDC_JDI_ENB_WIDTH_CLK_REG_LCDC_JDI_ENB_WIDTH_CLK_Pos (0UL) /*!< LCDC_JDI_ENB_WIDTH_CLK (Bit 0) */ +#define LCDC_LCDC_JDI_ENB_WIDTH_CLK_REG_LCDC_JDI_ENB_WIDTH_CLK_Msk (0xffffffffUL) /*!< LCDC_JDI_ENB_WIDTH_CLK (Bitfield-Mask: 0xffffffff) */ +/* =============================================== LCDC_JDI_FBX_BLANKING_REG =============================================== */ +#define LCDC_LCDC_JDI_FBX_BLANKING_REG_LCDC_JDI_FXBLANKING_Pos (16UL) /*!< LCDC_JDI_FXBLANKING (Bit 16) */ +#define LCDC_LCDC_JDI_FBX_BLANKING_REG_LCDC_JDI_FXBLANKING_Msk (0xffff0000UL) /*!< LCDC_JDI_FXBLANKING (Bitfield-Mask: 0xffff) */ +#define LCDC_LCDC_JDI_FBX_BLANKING_REG_LCDC_JDI_BXBLANKING_Pos (0UL) /*!< LCDC_JDI_BXBLANKING (Bit 0) */ +#define LCDC_LCDC_JDI_FBX_BLANKING_REG_LCDC_JDI_BXBLANKING_Msk (0xffffUL) /*!< LCDC_JDI_BXBLANKING (Bitfield-Mask: 0xffff) */ +/* =============================================== LCDC_JDI_FBY_BLANKING_REG =============================================== */ +#define LCDC_LCDC_JDI_FBY_BLANKING_REG_LCDC_JDI_FYBLANKING_Pos (16UL) /*!< LCDC_JDI_FYBLANKING (Bit 16) */ +#define LCDC_LCDC_JDI_FBY_BLANKING_REG_LCDC_JDI_FYBLANKING_Msk (0xffff0000UL) /*!< LCDC_JDI_FYBLANKING (Bitfield-Mask: 0xffff) */ +#define LCDC_LCDC_JDI_FBY_BLANKING_REG_LCDC_JDI_BYBLANKING_Pos (0UL) /*!< LCDC_JDI_BYBLANKING (Bit 0) */ +#define LCDC_LCDC_JDI_FBY_BLANKING_REG_LCDC_JDI_BYBLANKING_Msk (0xffffUL) /*!< LCDC_JDI_BYBLANKING (Bitfield-Mask: 0xffff) */ +/* ================================================ LCDC_JDI_HCK_WIDTH_REG ================================================= */ +#define LCDC_LCDC_JDI_HCK_WIDTH_REG_LCDC_JDI_HCK_WIDTH_Pos (0UL) /*!< LCDC_JDI_HCK_WIDTH (Bit 0) */ +#define LCDC_LCDC_JDI_HCK_WIDTH_REG_LCDC_JDI_HCK_WIDTH_Msk (0xffffffffUL) /*!< LCDC_JDI_HCK_WIDTH (Bitfield-Mask: 0xffffffff) */ +/* ================================================ LCDC_JDI_HST_DELAY_REG ================================================= */ +#define LCDC_LCDC_JDI_HST_DELAY_REG_LCDC_JDI_HST_DELAY_Pos (0UL) /*!< LCDC_JDI_HST_DELAY (Bit 0) */ +#define LCDC_LCDC_JDI_HST_DELAY_REG_LCDC_JDI_HST_DELAY_Msk (0xffffffffUL) /*!< LCDC_JDI_HST_DELAY (Bitfield-Mask: 0xffffffff) */ +/* ================================================ LCDC_JDI_HST_WIDTH_REG ================================================= */ +#define LCDC_LCDC_JDI_HST_WIDTH_REG_LCDC_JDI_HST_WIDTH_Pos (0UL) /*!< LCDC_JDI_HST_WIDTH (Bit 0) */ +#define LCDC_LCDC_JDI_HST_WIDTH_REG_LCDC_JDI_HST_WIDTH_Msk (0xffffffffUL) /*!< LCDC_JDI_HST_WIDTH (Bitfield-Mask: 0xffffffff) */ +/* ================================================== LCDC_JDI_RESXY_REG =================================================== */ +#define LCDC_LCDC_JDI_RESXY_REG_LCDC_JDI_RES_X_Pos (16UL) /*!< LCDC_JDI_RES_X (Bit 16) */ +#define LCDC_LCDC_JDI_RESXY_REG_LCDC_JDI_RES_X_Msk (0xffff0000UL) /*!< LCDC_JDI_RES_X (Bitfield-Mask: 0xffff) */ +#define LCDC_LCDC_JDI_RESXY_REG_LCDC_JDI_RES_Y_Pos (0UL) /*!< LCDC_JDI_RES_Y (Bit 0) */ +#define LCDC_LCDC_JDI_RESXY_REG_LCDC_JDI_RES_Y_Msk (0xffffUL) /*!< LCDC_JDI_RES_Y (Bitfield-Mask: 0xffff) */ +/* ================================================ LCDC_JDI_VCK_DELAY_REG ================================================= */ +#define LCDC_LCDC_JDI_VCK_DELAY_REG_LCDC_JDI_VCK_DELAY_Pos (0UL) /*!< LCDC_JDI_VCK_DELAY (Bit 0) */ +#define LCDC_LCDC_JDI_VCK_DELAY_REG_LCDC_JDI_VCK_DELAY_Msk (0xffffffffUL) /*!< LCDC_JDI_VCK_DELAY (Bitfield-Mask: 0xffffffff) */ +/* ================================================ LCDC_JDI_VST_DELAY_REG ================================================= */ +#define LCDC_LCDC_JDI_VST_DELAY_REG_LCDC_JDI_VST_DELAY_Pos (0UL) /*!< LCDC_JDI_VST_DELAY (Bit 0) */ +#define LCDC_LCDC_JDI_VST_DELAY_REG_LCDC_JDI_VST_DELAY_Msk (0xffffffffUL) /*!< LCDC_JDI_VST_DELAY (Bitfield-Mask: 0xffffffff) */ +/* ================================================ LCDC_JDI_VST_WIDTH_REG ================================================= */ +#define LCDC_LCDC_JDI_VST_WIDTH_REG_LCDC_JDI_VST_WIDTH_Pos (0UL) /*!< LCDC_JDI_VST_WIDTH (Bit 0) */ +#define LCDC_LCDC_JDI_VST_WIDTH_REG_LCDC_JDI_VST_WIDTH_Msk (0xffffffffUL) /*!< LCDC_JDI_VST_WIDTH (Bitfield-Mask: 0xffffffff) */ +/* ================================================ LCDC_JDI_XRST_WIDTH_REG ================================================ */ +#define LCDC_LCDC_JDI_XRST_WIDTH_REG_LCDC_JDI_XRST_WIDTH_Pos (0UL) /*!< LCDC_JDI_XRST_WIDTH (Bit 0) */ +#define LCDC_LCDC_JDI_XRST_WIDTH_REG_LCDC_JDI_XRST_WIDTH_Msk (0xffffffffUL) /*!< LCDC_JDI_XRST_WIDTH (Bitfield-Mask: 0xffffffff) */ +/* =============================================== LCDC_LAYER0_BASEADDR_REG ================================================ */ +#define LCDC_LCDC_LAYER0_BASEADDR_REG_LCDC_L0_FB_ADDR_Pos (0UL) /*!< LCDC_L0_FB_ADDR (Bit 0) */ +#define LCDC_LCDC_LAYER0_BASEADDR_REG_LCDC_L0_FB_ADDR_Msk (0xffffffffUL) /*!< LCDC_L0_FB_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ================================================= LCDC_LAYER0_MODE_REG ================================================== */ +#define LCDC_LCDC_LAYER0_MODE_REG_LCDC_L0_EN_Pos (31UL) /*!< LCDC_L0_EN (Bit 31) */ +#define LCDC_LCDC_LAYER0_MODE_REG_LCDC_L0_EN_Msk (0x80000000UL) /*!< LCDC_L0_EN (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_LAYER0_MODE_REG_LCDC_L0_COLOUR_MODE_Pos (0UL) /*!< LCDC_L0_COLOUR_MODE (Bit 0) */ +#define LCDC_LCDC_LAYER0_MODE_REG_LCDC_L0_COLOUR_MODE_Msk (0x1fUL) /*!< LCDC_L0_COLOUR_MODE (Bitfield-Mask: 0x1f) */ +/* ================================================ LCDC_LAYER0_OFFSETX_REG ================================================ */ +#define LCDC_LCDC_LAYER0_OFFSETX_REG_LCDC_L0_DMA_PREFETCH_Pos (16UL) /*!< LCDC_L0_DMA_PREFETCH (Bit 16) */ +#define LCDC_LCDC_LAYER0_OFFSETX_REG_LCDC_L0_DMA_PREFETCH_Msk (0xffff0000UL) /*!< LCDC_L0_DMA_PREFETCH (Bitfield-Mask: 0xffff) */ +#define LCDC_LCDC_LAYER0_OFFSETX_REG_LCDC_L0_OFFSETX_Pos (0UL) /*!< LCDC_L0_OFFSETX (Bit 0) */ +#define LCDC_LCDC_LAYER0_OFFSETX_REG_LCDC_L0_OFFSETX_Msk (0xffffUL) /*!< LCDC_L0_OFFSETX (Bitfield-Mask: 0xffff) */ +/* ================================================= LCDC_LAYER0_RESXY_REG ================================================= */ +#define LCDC_LCDC_LAYER0_RESXY_REG_LCDC_L0_RES_X_Pos (16UL) /*!< LCDC_L0_RES_X (Bit 16) */ +#define LCDC_LCDC_LAYER0_RESXY_REG_LCDC_L0_RES_X_Msk (0xffff0000UL) /*!< LCDC_L0_RES_X (Bitfield-Mask: 0xffff) */ +#define LCDC_LCDC_LAYER0_RESXY_REG_LCDC_L0_RES_Y_Pos (0UL) /*!< LCDC_L0_RES_Y (Bit 0) */ +#define LCDC_LCDC_LAYER0_RESXY_REG_LCDC_L0_RES_Y_Msk (0xffffUL) /*!< LCDC_L0_RES_Y (Bitfield-Mask: 0xffff) */ +/* ================================================ LCDC_LAYER0_SIZEXY_REG ================================================= */ +#define LCDC_LCDC_LAYER0_SIZEXY_REG_LCDC_L0_SIZE_X_Pos (16UL) /*!< LCDC_L0_SIZE_X (Bit 16) */ +#define LCDC_LCDC_LAYER0_SIZEXY_REG_LCDC_L0_SIZE_X_Msk (0xffff0000UL) /*!< LCDC_L0_SIZE_X (Bitfield-Mask: 0xffff) */ +#define LCDC_LCDC_LAYER0_SIZEXY_REG_LCDC_L0_SIZE_Y_Pos (0UL) /*!< LCDC_L0_SIZE_Y (Bit 0) */ +#define LCDC_LCDC_LAYER0_SIZEXY_REG_LCDC_L0_SIZE_Y_Msk (0xffffUL) /*!< LCDC_L0_SIZE_Y (Bitfield-Mask: 0xffff) */ +/* ================================================ LCDC_LAYER0_STARTXY_REG ================================================ */ +#define LCDC_LCDC_LAYER0_STARTXY_REG_LCDC_L0_START_X_Pos (16UL) /*!< LCDC_L0_START_X (Bit 16) */ +#define LCDC_LCDC_LAYER0_STARTXY_REG_LCDC_L0_START_X_Msk (0xffff0000UL) /*!< LCDC_L0_START_X (Bitfield-Mask: 0xffff) */ +#define LCDC_LCDC_LAYER0_STARTXY_REG_LCDC_L0_START_Y_Pos (0UL) /*!< LCDC_L0_START_Y (Bit 0) */ +#define LCDC_LCDC_LAYER0_STARTXY_REG_LCDC_L0_START_Y_Msk (0xffffUL) /*!< LCDC_L0_START_Y (Bitfield-Mask: 0xffff) */ +/* ================================================ LCDC_LAYER0_STRIDE_REG ================================================= */ +#define LCDC_LCDC_LAYER0_STRIDE_REG_LCDC_L0_FIFO_THR_Pos (19UL) /*!< LCDC_L0_FIFO_THR (Bit 19) */ +#define LCDC_LCDC_LAYER0_STRIDE_REG_LCDC_L0_FIFO_THR_Msk (0x180000UL) /*!< LCDC_L0_FIFO_THR (Bitfield-Mask: 0x03) */ +#define LCDC_LCDC_LAYER0_STRIDE_REG_LCDC_L0_BURST_LEN_Pos (16UL) /*!< LCDC_L0_BURST_LEN (Bit 16) */ +#define LCDC_LCDC_LAYER0_STRIDE_REG_LCDC_L0_BURST_LEN_Msk (0x70000UL) /*!< LCDC_L0_BURST_LEN (Bitfield-Mask: 0x07) */ +#define LCDC_LCDC_LAYER0_STRIDE_REG_LCDC_L0_STRIDE_Pos (0UL) /*!< LCDC_L0_STRIDE (Bit 0) */ +#define LCDC_LCDC_LAYER0_STRIDE_REG_LCDC_L0_STRIDE_Msk (0xffffUL) /*!< LCDC_L0_STRIDE (Bitfield-Mask: 0xffff) */ +/* ===================================================== LCDC_MODE_REG ===================================================== */ +#define LCDC_LCDC_MODE_REG_LCDC_MODE_EN_Pos (31UL) /*!< LCDC_MODE_EN (Bit 31) */ +#define LCDC_LCDC_MODE_REG_LCDC_MODE_EN_Msk (0x80000000UL) /*!< LCDC_MODE_EN (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_MODE_REG_LCDC_VSYNC_POL_Pos (28UL) /*!< LCDC_VSYNC_POL (Bit 28) */ +#define LCDC_LCDC_MODE_REG_LCDC_VSYNC_POL_Msk (0x10000000UL) /*!< LCDC_VSYNC_POL (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_MODE_REG_LCDC_HSYNC_POL_Pos (27UL) /*!< LCDC_HSYNC_POL (Bit 27) */ +#define LCDC_LCDC_MODE_REG_LCDC_HSYNC_POL_Msk (0x8000000UL) /*!< LCDC_HSYNC_POL (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_MODE_REG_LCDC_DE_POL_Pos (26UL) /*!< LCDC_DE_POL (Bit 26) */ +#define LCDC_LCDC_MODE_REG_LCDC_DE_POL_Msk (0x4000000UL) /*!< LCDC_DE_POL (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_MODE_REG_LCDC_VSYNC_SCPL_Pos (23UL) /*!< LCDC_VSYNC_SCPL (Bit 23) */ +#define LCDC_LCDC_MODE_REG_LCDC_VSYNC_SCPL_Msk (0x800000UL) /*!< LCDC_VSYNC_SCPL (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_MODE_REG_LCDC_PIXCLKOUT_POL_Pos (22UL) /*!< LCDC_PIXCLKOUT_POL (Bit 22) */ +#define LCDC_LCDC_MODE_REG_LCDC_PIXCLKOUT_POL_Msk (0x400000UL) /*!< LCDC_PIXCLKOUT_POL (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_MODE_REG_LCDC_FORCE_BLANK_Pos (19UL) /*!< LCDC_FORCE_BLANK (Bit 19) */ +#define LCDC_LCDC_MODE_REG_LCDC_FORCE_BLANK_Msk (0x80000UL) /*!< LCDC_FORCE_BLANK (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_MODE_REG_LCDC_SFRAME_UPD_Pos (17UL) /*!< LCDC_SFRAME_UPD (Bit 17) */ +#define LCDC_LCDC_MODE_REG_LCDC_SFRAME_UPD_Msk (0x20000UL) /*!< LCDC_SFRAME_UPD (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_MODE_REG_LCDC_PIXCLKOUT_SEL_Pos (11UL) /*!< LCDC_PIXCLKOUT_SEL (Bit 11) */ +#define LCDC_LCDC_MODE_REG_LCDC_PIXCLKOUT_SEL_Msk (0x800UL) /*!< LCDC_PIXCLKOUT_SEL (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_MODE_REG_LCDC_OUT_MODE_Pos (5UL) /*!< LCDC_OUT_MODE (Bit 5) */ +#define LCDC_LCDC_MODE_REG_LCDC_OUT_MODE_Msk (0x1e0UL) /*!< LCDC_OUT_MODE (Bitfield-Mask: 0x0f) */ +#define LCDC_LCDC_MODE_REG_LCDC_MIPI_OFF_Pos (4UL) /*!< LCDC_MIPI_OFF (Bit 4) */ +#define LCDC_LCDC_MODE_REG_LCDC_MIPI_OFF_Msk (0x10UL) /*!< LCDC_MIPI_OFF (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_MODE_REG_LCDC_FORM_OFF_Pos (3UL) /*!< LCDC_FORM_OFF (Bit 3) */ +#define LCDC_LCDC_MODE_REG_LCDC_FORM_OFF_Msk (0x8UL) /*!< LCDC_FORM_OFF (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_MODE_REG_LCDC_DSCAN_Pos (1UL) /*!< LCDC_DSCAN (Bit 1) */ +#define LCDC_LCDC_MODE_REG_LCDC_DSCAN_Msk (0x2UL) /*!< LCDC_DSCAN (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_MODE_REG_LCDC_TMODE_Pos (0UL) /*!< LCDC_TMODE (Bit 0) */ +#define LCDC_LCDC_MODE_REG_LCDC_TMODE_Msk (0x1UL) /*!< LCDC_TMODE (Bitfield-Mask: 0x01) */ +/* ==================================================== LCDC_RESXY_REG ===================================================== */ +#define LCDC_LCDC_RESXY_REG_LCDC_RES_X_Pos (16UL) /*!< LCDC_RES_X (Bit 16) */ +#define LCDC_LCDC_RESXY_REG_LCDC_RES_X_Msk (0xffff0000UL) /*!< LCDC_RES_X (Bitfield-Mask: 0xffff) */ +#define LCDC_LCDC_RESXY_REG_LCDC_RES_Y_Pos (0UL) /*!< LCDC_RES_Y (Bit 0) */ +#define LCDC_LCDC_RESXY_REG_LCDC_RES_Y_Msk (0xffffUL) /*!< LCDC_RES_Y (Bitfield-Mask: 0xffff) */ +/* ==================================================== LCDC_STATUS_REG ==================================================== */ +#define LCDC_LCDC_STATUS_REG_LCDC_JDI_TIM_SW_RST_Pos (15UL) /*!< LCDC_JDI_TIM_SW_RST (Bit 15) */ +#define LCDC_LCDC_STATUS_REG_LCDC_JDI_TIM_SW_RST_Msk (0x8000UL) /*!< LCDC_JDI_TIM_SW_RST (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_STATUS_REG_LCDC_FRAME_START_Pos (14UL) /*!< LCDC_FRAME_START (Bit 14) */ +#define LCDC_LCDC_STATUS_REG_LCDC_FRAME_START_Msk (0x4000UL) /*!< LCDC_FRAME_START (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_STATUS_REG_LCDC_FRAME_END_Pos (13UL) /*!< LCDC_FRAME_END (Bit 13) */ +#define LCDC_LCDC_STATUS_REG_LCDC_FRAME_END_Msk (0x2000UL) /*!< LCDC_FRAME_END (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_STATUS_REG_LCDC_DBIB_CMD_PENDING_Pos (12UL) /*!< LCDC_DBIB_CMD_PENDING (Bit 12) */ +#define LCDC_LCDC_STATUS_REG_LCDC_DBIB_CMD_PENDING_Msk (0x1000UL) /*!< LCDC_DBIB_CMD_PENDING (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_STATUS_REG_LCDC_DBIB_CMD_FIFO_FULL_Pos (11UL) /*!< LCDC_DBIB_CMD_FIFO_FULL (Bit 11) */ +#define LCDC_LCDC_STATUS_REG_LCDC_DBIB_CMD_FIFO_FULL_Msk (0x800UL) /*!< LCDC_DBIB_CMD_FIFO_FULL (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_STATUS_REG_LCDC_DBIB_CMD_FIFO_EMPTY_N_Pos (10UL) /*!< LCDC_DBIB_CMD_FIFO_EMPTY_N (Bit 10) */ +#define LCDC_LCDC_STATUS_REG_LCDC_DBIB_CMD_FIFO_EMPTY_N_Msk (0x400UL) /*!< LCDC_DBIB_CMD_FIFO_EMPTY_N (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_STATUS_REG_LCDC_DBIB_TE_Pos (8UL) /*!< LCDC_DBIB_TE (Bit 8) */ +#define LCDC_LCDC_STATUS_REG_LCDC_DBIB_TE_Msk (0x100UL) /*!< LCDC_DBIB_TE (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_STATUS_REG_LCDC_STICKY_UNDERFLOW_Pos (7UL) /*!< LCDC_STICKY_UNDERFLOW (Bit 7) */ +#define LCDC_LCDC_STATUS_REG_LCDC_STICKY_UNDERFLOW_Msk (0x80UL) /*!< LCDC_STICKY_UNDERFLOW (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_STATUS_REG_LCDC_UNDERFLOW_Pos (6UL) /*!< LCDC_UNDERFLOW (Bit 6) */ +#define LCDC_LCDC_STATUS_REG_LCDC_UNDERFLOW_Msk (0x40UL) /*!< LCDC_UNDERFLOW (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_STATUS_REG_LCDC_LAST_ROW_Pos (5UL) /*!< LCDC_LAST_ROW (Bit 5) */ +#define LCDC_LCDC_STATUS_REG_LCDC_LAST_ROW_Msk (0x20UL) /*!< LCDC_LAST_ROW (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_STATUS_REG_LCDC_STAT_CSYNC_Pos (4UL) /*!< LCDC_STAT_CSYNC (Bit 4) */ +#define LCDC_LCDC_STATUS_REG_LCDC_STAT_CSYNC_Msk (0x10UL) /*!< LCDC_STAT_CSYNC (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_STATUS_REG_LCDC_STAT_VSYNC_Pos (3UL) /*!< LCDC_STAT_VSYNC (Bit 3) */ +#define LCDC_LCDC_STATUS_REG_LCDC_STAT_VSYNC_Msk (0x8UL) /*!< LCDC_STAT_VSYNC (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_STATUS_REG_LCDC_STAT_HSYNC_Pos (2UL) /*!< LCDC_STAT_HSYNC (Bit 2) */ +#define LCDC_LCDC_STATUS_REG_LCDC_STAT_HSYNC_Msk (0x4UL) /*!< LCDC_STAT_HSYNC (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_STATUS_REG_LCDC_FRAMEGEN_BUSY_Pos (1UL) /*!< LCDC_FRAMEGEN_BUSY (Bit 1) */ +#define LCDC_LCDC_STATUS_REG_LCDC_FRAMEGEN_BUSY_Msk (0x2UL) /*!< LCDC_FRAMEGEN_BUSY (Bitfield-Mask: 0x01) */ +#define LCDC_LCDC_STATUS_REG_LCDC_STAT_ACTIVE_Pos (0UL) /*!< LCDC_STAT_ACTIVE (Bit 0) */ +#define LCDC_LCDC_STATUS_REG_LCDC_STAT_ACTIVE_Msk (0x1UL) /*!< LCDC_STAT_ACTIVE (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ LRA ================ */ +/* =========================================================================================================================== */ + +/* =================================================== LRA_ADC_CTRL1_REG =================================================== */ +#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_BUSY_Pos (31UL) /*!< LRA_ADC_BUSY (Bit 31) */ +#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_BUSY_Msk (0x80000000UL) /*!< LRA_ADC_BUSY (Bitfield-Mask: 0x01) */ +#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_OFFSET_Pos (9UL) /*!< LRA_ADC_OFFSET (Bit 9) */ +#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_OFFSET_Msk (0x1fe00UL) /*!< LRA_ADC_OFFSET (Bitfield-Mask: 0xff) */ +#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_TEST_PARAM_Pos (8UL) /*!< LRA_ADC_TEST_PARAM (Bit 8) */ +#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_TEST_PARAM_Msk (0x100UL) /*!< LRA_ADC_TEST_PARAM (Bitfield-Mask: 0x01) */ +#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_TEST_IN_SEL_Pos (7UL) /*!< LRA_ADC_TEST_IN_SEL (Bit 7) */ +#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_TEST_IN_SEL_Msk (0x80UL) /*!< LRA_ADC_TEST_IN_SEL (Bitfield-Mask: 0x01) */ +#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_FREQ_Pos (3UL) /*!< LRA_ADC_FREQ (Bit 3) */ +#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_FREQ_Msk (0x78UL) /*!< LRA_ADC_FREQ (Bitfield-Mask: 0x0f) */ +#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_SIGN_Pos (2UL) /*!< LRA_ADC_SIGN (Bit 2) */ +#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_SIGN_Msk (0x4UL) /*!< LRA_ADC_SIGN (Bitfield-Mask: 0x01) */ +#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_MUTE_Pos (1UL) /*!< LRA_ADC_MUTE (Bit 1) */ +#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_MUTE_Msk (0x2UL) /*!< LRA_ADC_MUTE (Bitfield-Mask: 0x01) */ +#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_START_Pos (0UL) /*!< LRA_ADC_START (Bit 0) */ +#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_START_Msk (0x1UL) /*!< LRA_ADC_START (Bitfield-Mask: 0x01) */ +/* ================================================== LRA_ADC_RESULT_REG =================================================== */ +#define LRA_LRA_ADC_RESULT_REG_MAN_FLT_IN_Pos (16UL) /*!< MAN_FLT_IN (Bit 16) */ +#define LRA_LRA_ADC_RESULT_REG_MAN_FLT_IN_Msk (0xffff0000UL) /*!< MAN_FLT_IN (Bitfield-Mask: 0xffff) */ +#define LRA_LRA_ADC_RESULT_REG_GP_ADC_VAL_Pos (0UL) /*!< GP_ADC_VAL (Bit 0) */ +#define LRA_LRA_ADC_RESULT_REG_GP_ADC_VAL_Msk (0xffffUL) /*!< GP_ADC_VAL (Bitfield-Mask: 0xffff) */ +/* ==================================================== LRA_BRD_HS_REG ===================================================== */ +#define LRA_LRA_BRD_HS_REG_TRIM_GAIN_Pos (11UL) /*!< TRIM_GAIN (Bit 11) */ +#define LRA_LRA_BRD_HS_REG_TRIM_GAIN_Msk (0x7800UL) /*!< TRIM_GAIN (Bitfield-Mask: 0x0f) */ +#define LRA_LRA_BRD_HS_REG_HSGND_TRIM_Pos (8UL) /*!< HSGND_TRIM (Bit 8) */ +#define LRA_LRA_BRD_HS_REG_HSGND_TRIM_Msk (0x700UL) /*!< HSGND_TRIM (Bitfield-Mask: 0x07) */ +#define LRA_LRA_BRD_HS_REG_SCP_HS_TRIM_Pos (4UL) /*!< SCP_HS_TRIM (Bit 4) */ +#define LRA_LRA_BRD_HS_REG_SCP_HS_TRIM_Msk (0xf0UL) /*!< SCP_HS_TRIM (Bitfield-Mask: 0x0f) */ +#define LRA_LRA_BRD_HS_REG_SCP_HS_EN_Pos (3UL) /*!< SCP_HS_EN (Bit 3) */ +#define LRA_LRA_BRD_HS_REG_SCP_HS_EN_Msk (0x8UL) /*!< SCP_HS_EN (Bitfield-Mask: 0x01) */ +#define LRA_LRA_BRD_HS_REG_ERC_HS_TRIM_Pos (1UL) /*!< ERC_HS_TRIM (Bit 1) */ +#define LRA_LRA_BRD_HS_REG_ERC_HS_TRIM_Msk (0x6UL) /*!< ERC_HS_TRIM (Bitfield-Mask: 0x03) */ +#define LRA_LRA_BRD_HS_REG_ERC_HS_EN_Pos (0UL) /*!< ERC_HS_EN (Bit 0) */ +#define LRA_LRA_BRD_HS_REG_ERC_HS_EN_Msk (0x1UL) /*!< ERC_HS_EN (Bitfield-Mask: 0x01) */ +/* ==================================================== LRA_BRD_LS_REG ===================================================== */ +#define LRA_LRA_BRD_LS_REG_SCP_LS_TRIM_N_Pos (8UL) /*!< SCP_LS_TRIM_N (Bit 8) */ +#define LRA_LRA_BRD_LS_REG_SCP_LS_TRIM_N_Msk (0xf00UL) /*!< SCP_LS_TRIM_N (Bitfield-Mask: 0x0f) */ +#define LRA_LRA_BRD_LS_REG_SCP_LS_TRIM_P_Pos (4UL) /*!< SCP_LS_TRIM_P (Bit 4) */ +#define LRA_LRA_BRD_LS_REG_SCP_LS_TRIM_P_Msk (0xf0UL) /*!< SCP_LS_TRIM_P (Bitfield-Mask: 0x0f) */ +#define LRA_LRA_BRD_LS_REG_SCP_LS_EN_Pos (3UL) /*!< SCP_LS_EN (Bit 3) */ +#define LRA_LRA_BRD_LS_REG_SCP_LS_EN_Msk (0x8UL) /*!< SCP_LS_EN (Bitfield-Mask: 0x01) */ +#define LRA_LRA_BRD_LS_REG_ERC_LS_TRIM_Pos (1UL) /*!< ERC_LS_TRIM (Bit 1) */ +#define LRA_LRA_BRD_LS_REG_ERC_LS_TRIM_Msk (0x6UL) /*!< ERC_LS_TRIM (Bitfield-Mask: 0x03) */ +#define LRA_LRA_BRD_LS_REG_ERC_LS_EN_Pos (0UL) /*!< ERC_LS_EN (Bit 0) */ +#define LRA_LRA_BRD_LS_REG_ERC_LS_EN_Msk (0x1UL) /*!< ERC_LS_EN (Bitfield-Mask: 0x01) */ +/* =================================================== LRA_BRD_STAT_REG ==================================================== */ +#define LRA_LRA_BRD_STAT_REG_SCP_HS_OUT_Pos (13UL) /*!< SCP_HS_OUT (Bit 13) */ +#define LRA_LRA_BRD_STAT_REG_SCP_HS_OUT_Msk (0x2000UL) /*!< SCP_HS_OUT (Bitfield-Mask: 0x01) */ +#define LRA_LRA_BRD_STAT_REG_SCP_LS_COMP_OUT_N_Pos (12UL) /*!< SCP_LS_COMP_OUT_N (Bit 12) */ +#define LRA_LRA_BRD_STAT_REG_SCP_LS_COMP_OUT_N_Msk (0x1000UL) /*!< SCP_LS_COMP_OUT_N (Bitfield-Mask: 0x01) */ +#define LRA_LRA_BRD_STAT_REG_SCP_LS_COMP_OUT_P_Pos (11UL) /*!< SCP_LS_COMP_OUT_P (Bit 11) */ +#define LRA_LRA_BRD_STAT_REG_SCP_LS_COMP_OUT_P_Msk (0x800UL) /*!< SCP_LS_COMP_OUT_P (Bitfield-Mask: 0x01) */ +#define LRA_LRA_BRD_STAT_REG_SC_EVENT_LS_Pos (10UL) /*!< SC_EVENT_LS (Bit 10) */ +#define LRA_LRA_BRD_STAT_REG_SC_EVENT_LS_Msk (0x400UL) /*!< SC_EVENT_LS (Bitfield-Mask: 0x01) */ +#define LRA_LRA_BRD_STAT_REG_SC_EVENT_HS_Pos (9UL) /*!< SC_EVENT_HS (Bit 9) */ +#define LRA_LRA_BRD_STAT_REG_SC_EVENT_HS_Msk (0x200UL) /*!< SC_EVENT_HS (Bitfield-Mask: 0x01) */ +#define LRA_LRA_BRD_STAT_REG_LOOP_STAT_Pos (8UL) /*!< LOOP_STAT (Bit 8) */ +#define LRA_LRA_BRD_STAT_REG_LOOP_STAT_Msk (0x100UL) /*!< LOOP_STAT (Bitfield-Mask: 0x01) */ +#define LRA_LRA_BRD_STAT_REG_LSN_ON_Pos (7UL) /*!< LSN_ON (Bit 7) */ +#define LRA_LRA_BRD_STAT_REG_LSN_ON_Msk (0x80UL) /*!< LSN_ON (Bitfield-Mask: 0x01) */ +#define LRA_LRA_BRD_STAT_REG_LSP_ON_Pos (6UL) /*!< LSP_ON (Bit 6) */ +#define LRA_LRA_BRD_STAT_REG_LSP_ON_Msk (0x40UL) /*!< LSP_ON (Bitfield-Mask: 0x01) */ +#define LRA_LRA_BRD_STAT_REG_HSN_ON_Pos (5UL) /*!< HSN_ON (Bit 5) */ +#define LRA_LRA_BRD_STAT_REG_HSN_ON_Msk (0x20UL) /*!< HSN_ON (Bitfield-Mask: 0x01) */ +#define LRA_LRA_BRD_STAT_REG_HSP_ON_Pos (4UL) /*!< HSP_ON (Bit 4) */ +#define LRA_LRA_BRD_STAT_REG_HSP_ON_Msk (0x10UL) /*!< HSP_ON (Bitfield-Mask: 0x01) */ +#define LRA_LRA_BRD_STAT_REG_LSN_STAT_Pos (3UL) /*!< LSN_STAT (Bit 3) */ +#define LRA_LRA_BRD_STAT_REG_LSN_STAT_Msk (0x8UL) /*!< LSN_STAT (Bitfield-Mask: 0x01) */ +#define LRA_LRA_BRD_STAT_REG_LSP_STAT_Pos (2UL) /*!< LSP_STAT (Bit 2) */ +#define LRA_LRA_BRD_STAT_REG_LSP_STAT_Msk (0x4UL) /*!< LSP_STAT (Bitfield-Mask: 0x01) */ +#define LRA_LRA_BRD_STAT_REG_HSN_STAT_Pos (1UL) /*!< HSN_STAT (Bit 1) */ +#define LRA_LRA_BRD_STAT_REG_HSN_STAT_Msk (0x2UL) /*!< HSN_STAT (Bitfield-Mask: 0x01) */ +#define LRA_LRA_BRD_STAT_REG_HSP_STAT_Pos (0UL) /*!< HSP_STAT (Bit 0) */ +#define LRA_LRA_BRD_STAT_REG_HSP_STAT_Msk (0x1UL) /*!< HSP_STAT (Bitfield-Mask: 0x01) */ +/* ===================================================== LRA_CTRL1_REG ===================================================== */ +#define LRA_LRA_CTRL1_REG_SMP_IDX_Pos (24UL) /*!< SMP_IDX (Bit 24) */ +#define LRA_LRA_CTRL1_REG_SMP_IDX_Msk (0xf000000UL) /*!< SMP_IDX (Bitfield-Mask: 0x0f) */ +#define LRA_LRA_CTRL1_REG_IRQ_SCP_EVENT_EN_Pos (18UL) /*!< IRQ_SCP_EVENT_EN (Bit 18) */ +#define LRA_LRA_CTRL1_REG_IRQ_SCP_EVENT_EN_Msk (0x40000UL) /*!< IRQ_SCP_EVENT_EN (Bitfield-Mask: 0x01) */ +#define LRA_LRA_CTRL1_REG_IRQ_ADC_EN_Pos (17UL) /*!< IRQ_ADC_EN (Bit 17) */ +#define LRA_LRA_CTRL1_REG_IRQ_ADC_EN_Msk (0x20000UL) /*!< IRQ_ADC_EN (Bitfield-Mask: 0x01) */ +#define LRA_LRA_CTRL1_REG_IRQ_CTRL_EN_Pos (16UL) /*!< IRQ_CTRL_EN (Bit 16) */ +#define LRA_LRA_CTRL1_REG_IRQ_CTRL_EN_Msk (0x10000UL) /*!< IRQ_CTRL_EN (Bitfield-Mask: 0x01) */ +#define LRA_LRA_CTRL1_REG_IRQ_IDX_Pos (12UL) /*!< IRQ_IDX (Bit 12) */ +#define LRA_LRA_CTRL1_REG_IRQ_IDX_Msk (0xf000UL) /*!< IRQ_IDX (Bitfield-Mask: 0x0f) */ +#define LRA_LRA_CTRL1_REG_IRQ_DIV_Pos (8UL) /*!< IRQ_DIV (Bit 8) */ +#define LRA_LRA_CTRL1_REG_IRQ_DIV_Msk (0xf00UL) /*!< IRQ_DIV (Bitfield-Mask: 0x0f) */ +#define LRA_LRA_CTRL1_REG_SMP_SEL_Pos (6UL) /*!< SMP_SEL (Bit 6) */ +#define LRA_LRA_CTRL1_REG_SMP_SEL_Msk (0xc0UL) /*!< SMP_SEL (Bitfield-Mask: 0x03) */ +#define LRA_LRA_CTRL1_REG_PULLDOWN_EN_Pos (5UL) /*!< PULLDOWN_EN (Bit 5) */ +#define LRA_LRA_CTRL1_REG_PULLDOWN_EN_Msk (0x20UL) /*!< PULLDOWN_EN (Bitfield-Mask: 0x01) */ +#define LRA_LRA_CTRL1_REG_LOOP_EN_Pos (4UL) /*!< LOOP_EN (Bit 4) */ +#define LRA_LRA_CTRL1_REG_LOOP_EN_Msk (0x10UL) /*!< LOOP_EN (Bitfield-Mask: 0x01) */ +#define LRA_LRA_CTRL1_REG_LDO_EN_Pos (3UL) /*!< LDO_EN (Bit 3) */ +#define LRA_LRA_CTRL1_REG_LDO_EN_Msk (0x8UL) /*!< LDO_EN (Bitfield-Mask: 0x01) */ +#define LRA_LRA_CTRL1_REG_ADC_EN_Pos (2UL) /*!< ADC_EN (Bit 2) */ +#define LRA_LRA_CTRL1_REG_ADC_EN_Msk (0x4UL) /*!< ADC_EN (Bitfield-Mask: 0x01) */ +#define LRA_LRA_CTRL1_REG_HBRIDGE_EN_Pos (1UL) /*!< HBRIDGE_EN (Bit 1) */ +#define LRA_LRA_CTRL1_REG_HBRIDGE_EN_Msk (0x2UL) /*!< HBRIDGE_EN (Bitfield-Mask: 0x01) */ +#define LRA_LRA_CTRL1_REG_LRA_EN_Pos (0UL) /*!< LRA_EN (Bit 0) */ +#define LRA_LRA_CTRL1_REG_LRA_EN_Msk (0x1UL) /*!< LRA_EN (Bitfield-Mask: 0x01) */ +/* ===================================================== LRA_CTRL2_REG ===================================================== */ +#define LRA_LRA_CTRL2_REG_HALF_PERIOD_Pos (16UL) /*!< HALF_PERIOD (Bit 16) */ +#define LRA_LRA_CTRL2_REG_HALF_PERIOD_Msk (0xffff0000UL) /*!< HALF_PERIOD (Bitfield-Mask: 0xffff) */ +#define LRA_LRA_CTRL2_REG_AUTO_MODE_Pos (5UL) /*!< AUTO_MODE (Bit 5) */ +#define LRA_LRA_CTRL2_REG_AUTO_MODE_Msk (0x20UL) /*!< AUTO_MODE (Bitfield-Mask: 0x01) */ +#define LRA_LRA_CTRL2_REG_SMP_MODE_Pos (4UL) /*!< SMP_MODE (Bit 4) */ +#define LRA_LRA_CTRL2_REG_SMP_MODE_Msk (0x10UL) /*!< SMP_MODE (Bitfield-Mask: 0x01) */ +#define LRA_LRA_CTRL2_REG_POLARITY_Pos (3UL) /*!< POLARITY (Bit 3) */ +#define LRA_LRA_CTRL2_REG_POLARITY_Msk (0x8UL) /*!< POLARITY (Bitfield-Mask: 0x01) */ +#define LRA_LRA_CTRL2_REG_FLT_IN_SEL_Pos (2UL) /*!< FLT_IN_SEL (Bit 2) */ +#define LRA_LRA_CTRL2_REG_FLT_IN_SEL_Msk (0x4UL) /*!< FLT_IN_SEL (Bitfield-Mask: 0x01) */ +#define LRA_LRA_CTRL2_REG_PWM_MODE_Pos (0UL) /*!< PWM_MODE (Bit 0) */ +#define LRA_LRA_CTRL2_REG_PWM_MODE_Msk (0x3UL) /*!< PWM_MODE (Bitfield-Mask: 0x03) */ +/* ===================================================== LRA_CTRL3_REG ===================================================== */ +#define LRA_LRA_CTRL3_REG_VREF_Pos (16UL) /*!< VREF (Bit 16) */ +#define LRA_LRA_CTRL3_REG_VREF_Msk (0xffff0000UL) /*!< VREF (Bitfield-Mask: 0xffff) */ +#define LRA_LRA_CTRL3_REG_DREF_Pos (0UL) /*!< DREF (Bit 0) */ +#define LRA_LRA_CTRL3_REG_DREF_Msk (0xffffUL) /*!< DREF (Bitfield-Mask: 0xffff) */ +/* ====================================================== LRA_DFT_REG ====================================================== */ +#define LRA_LRA_DFT_REG_SPARE_Pos (29UL) /*!< SPARE (Bit 29) */ +#define LRA_LRA_DFT_REG_SPARE_Msk (0xe0000000UL) /*!< SPARE (Bitfield-Mask: 0x07) */ +#define LRA_LRA_DFT_REG_SWM_SEL_Pos (28UL) /*!< SWM_SEL (Bit 28) */ +#define LRA_LRA_DFT_REG_SWM_SEL_Msk (0x10000000UL) /*!< SWM_SEL (Bitfield-Mask: 0x01) */ +#define LRA_LRA_DFT_REG_SWM_MAN_Pos (27UL) /*!< SWM_MAN (Bit 27) */ +#define LRA_LRA_DFT_REG_SWM_MAN_Msk (0x8000000UL) /*!< SWM_MAN (Bitfield-Mask: 0x01) */ +#define LRA_LRA_DFT_REG_PWM_SEL_Pos (26UL) /*!< PWM_SEL (Bit 26) */ +#define LRA_LRA_DFT_REG_PWM_SEL_Msk (0x4000000UL) /*!< PWM_SEL (Bitfield-Mask: 0x01) */ +#define LRA_LRA_DFT_REG_PWM_MAN_Pos (25UL) /*!< PWM_MAN (Bit 25) */ +#define LRA_LRA_DFT_REG_PWM_MAN_Msk (0x2000000UL) /*!< PWM_MAN (Bitfield-Mask: 0x01) */ +#define LRA_LRA_DFT_REG_TIMER_TRIM_Pos (23UL) /*!< TIMER_TRIM (Bit 23) */ +#define LRA_LRA_DFT_REG_TIMER_TRIM_Msk (0x1800000UL) /*!< TIMER_TRIM (Bitfield-Mask: 0x03) */ +#define LRA_LRA_DFT_REG_TIMER_SCALE_TRIM_Pos (21UL) /*!< TIMER_SCALE_TRIM (Bit 21) */ +#define LRA_LRA_DFT_REG_TIMER_SCALE_TRIM_Msk (0x600000UL) /*!< TIMER_SCALE_TRIM (Bitfield-Mask: 0x03) */ +#define LRA_LRA_DFT_REG_DFT_SEL_Pos (20UL) /*!< DFT_SEL (Bit 20) */ +#define LRA_LRA_DFT_REG_DFT_SEL_Msk (0x100000UL) /*!< DFT_SEL (Bitfield-Mask: 0x01) */ +#define LRA_LRA_DFT_REG_DFT_FORCE_HSPN_Pos (19UL) /*!< DFT_FORCE_HSPN (Bit 19) */ +#define LRA_LRA_DFT_REG_DFT_FORCE_HSPN_Msk (0x80000UL) /*!< DFT_FORCE_HSPN (Bitfield-Mask: 0x01) */ +#define LRA_LRA_DFT_REG_DFT_EN_TIMER_Pos (18UL) /*!< DFT_EN_TIMER (Bit 18) */ +#define LRA_LRA_DFT_REG_DFT_EN_TIMER_Msk (0x40000UL) /*!< DFT_EN_TIMER (Bitfield-Mask: 0x01) */ +#define LRA_LRA_DFT_REG_DFT_STALL_Pos (16UL) /*!< DFT_STALL (Bit 16) */ +#define LRA_LRA_DFT_REG_DFT_STALL_Msk (0x30000UL) /*!< DFT_STALL (Bitfield-Mask: 0x03) */ +#define LRA_LRA_DFT_REG_DFT_CTRL_Pos (0UL) /*!< DFT_CTRL (Bit 0) */ +#define LRA_LRA_DFT_REG_DFT_CTRL_Msk (0xffffUL) /*!< DFT_CTRL (Bitfield-Mask: 0xffff) */ +/* =================================================== LRA_FLT_COEF1_REG =================================================== */ +#define LRA_LRA_FLT_COEF1_REG_FLT_COEF_01_Pos (16UL) /*!< FLT_COEF_01 (Bit 16) */ +#define LRA_LRA_FLT_COEF1_REG_FLT_COEF_01_Msk (0xffff0000UL) /*!< FLT_COEF_01 (Bitfield-Mask: 0xffff) */ +#define LRA_LRA_FLT_COEF1_REG_FLT_COEF_00_Pos (0UL) /*!< FLT_COEF_00 (Bit 0) */ +#define LRA_LRA_FLT_COEF1_REG_FLT_COEF_00_Msk (0xffffUL) /*!< FLT_COEF_00 (Bitfield-Mask: 0xffff) */ +/* =================================================== LRA_FLT_COEF2_REG =================================================== */ +#define LRA_LRA_FLT_COEF2_REG_FLT_COEF_10_Pos (16UL) /*!< FLT_COEF_10 (Bit 16) */ +#define LRA_LRA_FLT_COEF2_REG_FLT_COEF_10_Msk (0xffff0000UL) /*!< FLT_COEF_10 (Bitfield-Mask: 0xffff) */ +#define LRA_LRA_FLT_COEF2_REG_FLT_COEF_02_Pos (0UL) /*!< FLT_COEF_02 (Bit 0) */ +#define LRA_LRA_FLT_COEF2_REG_FLT_COEF_02_Msk (0xffffUL) /*!< FLT_COEF_02 (Bitfield-Mask: 0xffff) */ +/* =================================================== LRA_FLT_COEF3_REG =================================================== */ +#define LRA_LRA_FLT_COEF3_REG_FLT_COEF_12_Pos (16UL) /*!< FLT_COEF_12 (Bit 16) */ +#define LRA_LRA_FLT_COEF3_REG_FLT_COEF_12_Msk (0xffff0000UL) /*!< FLT_COEF_12 (Bitfield-Mask: 0xffff) */ +#define LRA_LRA_FLT_COEF3_REG_FLT_COEF_11_Pos (0UL) /*!< FLT_COEF_11 (Bit 0) */ +#define LRA_LRA_FLT_COEF3_REG_FLT_COEF_11_Msk (0xffffUL) /*!< FLT_COEF_11 (Bitfield-Mask: 0xffff) */ +/* =================================================== LRA_FLT_SMP1_REG ==================================================== */ +#define LRA_LRA_FLT_SMP1_REG_LRA_SMP_2_Pos (16UL) /*!< LRA_SMP_2 (Bit 16) */ +#define LRA_LRA_FLT_SMP1_REG_LRA_SMP_2_Msk (0xffff0000UL) /*!< LRA_SMP_2 (Bitfield-Mask: 0xffff) */ +#define LRA_LRA_FLT_SMP1_REG_LRA_SMP_1_Pos (0UL) /*!< LRA_SMP_1 (Bit 0) */ +#define LRA_LRA_FLT_SMP1_REG_LRA_SMP_1_Msk (0xffffUL) /*!< LRA_SMP_1 (Bitfield-Mask: 0xffff) */ +/* =================================================== LRA_FLT_SMP2_REG ==================================================== */ +#define LRA_LRA_FLT_SMP2_REG_LRA_SMP_4_Pos (16UL) /*!< LRA_SMP_4 (Bit 16) */ +#define LRA_LRA_FLT_SMP2_REG_LRA_SMP_4_Msk (0xffff0000UL) /*!< LRA_SMP_4 (Bitfield-Mask: 0xffff) */ +#define LRA_LRA_FLT_SMP2_REG_LRA_SMP_3_Pos (0UL) /*!< LRA_SMP_3 (Bit 0) */ +#define LRA_LRA_FLT_SMP2_REG_LRA_SMP_3_Msk (0xffffUL) /*!< LRA_SMP_3 (Bitfield-Mask: 0xffff) */ +/* =================================================== LRA_FLT_SMP3_REG ==================================================== */ +#define LRA_LRA_FLT_SMP3_REG_LRA_SMP_6_Pos (16UL) /*!< LRA_SMP_6 (Bit 16) */ +#define LRA_LRA_FLT_SMP3_REG_LRA_SMP_6_Msk (0xffff0000UL) /*!< LRA_SMP_6 (Bitfield-Mask: 0xffff) */ +#define LRA_LRA_FLT_SMP3_REG_LRA_SMP_5_Pos (0UL) /*!< LRA_SMP_5 (Bit 0) */ +#define LRA_LRA_FLT_SMP3_REG_LRA_SMP_5_Msk (0xffffUL) /*!< LRA_SMP_5 (Bitfield-Mask: 0xffff) */ +/* =================================================== LRA_FLT_SMP4_REG ==================================================== */ +#define LRA_LRA_FLT_SMP4_REG_LRA_SMP_8_Pos (16UL) /*!< LRA_SMP_8 (Bit 16) */ +#define LRA_LRA_FLT_SMP4_REG_LRA_SMP_8_Msk (0xffff0000UL) /*!< LRA_SMP_8 (Bitfield-Mask: 0xffff) */ +#define LRA_LRA_FLT_SMP4_REG_LRA_SMP_7_Pos (0UL) /*!< LRA_SMP_7 (Bit 0) */ +#define LRA_LRA_FLT_SMP4_REG_LRA_SMP_7_Msk (0xffffUL) /*!< LRA_SMP_7 (Bitfield-Mask: 0xffff) */ +/* =================================================== LRA_FLT_SMP5_REG ==================================================== */ +#define LRA_LRA_FLT_SMP5_REG_LRA_SMP_10_Pos (16UL) /*!< LRA_SMP_10 (Bit 16) */ +#define LRA_LRA_FLT_SMP5_REG_LRA_SMP_10_Msk (0xffff0000UL) /*!< LRA_SMP_10 (Bitfield-Mask: 0xffff) */ +#define LRA_LRA_FLT_SMP5_REG_LRA_SMP_9_Pos (0UL) /*!< LRA_SMP_9 (Bit 0) */ +#define LRA_LRA_FLT_SMP5_REG_LRA_SMP_9_Msk (0xffffUL) /*!< LRA_SMP_9 (Bitfield-Mask: 0xffff) */ +/* =================================================== LRA_FLT_SMP6_REG ==================================================== */ +#define LRA_LRA_FLT_SMP6_REG_LRA_SMP_12_Pos (16UL) /*!< LRA_SMP_12 (Bit 16) */ +#define LRA_LRA_FLT_SMP6_REG_LRA_SMP_12_Msk (0xffff0000UL) /*!< LRA_SMP_12 (Bitfield-Mask: 0xffff) */ +#define LRA_LRA_FLT_SMP6_REG_LRA_SMP_11_Pos (0UL) /*!< LRA_SMP_11 (Bit 0) */ +#define LRA_LRA_FLT_SMP6_REG_LRA_SMP_11_Msk (0xffffUL) /*!< LRA_SMP_11 (Bitfield-Mask: 0xffff) */ +/* =================================================== LRA_FLT_SMP7_REG ==================================================== */ +#define LRA_LRA_FLT_SMP7_REG_LRA_SMP_14_Pos (16UL) /*!< LRA_SMP_14 (Bit 16) */ +#define LRA_LRA_FLT_SMP7_REG_LRA_SMP_14_Msk (0xffff0000UL) /*!< LRA_SMP_14 (Bitfield-Mask: 0xffff) */ +#define LRA_LRA_FLT_SMP7_REG_LRA_SMP_13_Pos (0UL) /*!< LRA_SMP_13 (Bit 0) */ +#define LRA_LRA_FLT_SMP7_REG_LRA_SMP_13_Msk (0xffffUL) /*!< LRA_SMP_13 (Bitfield-Mask: 0xffff) */ +/* =================================================== LRA_FLT_SMP8_REG ==================================================== */ +#define LRA_LRA_FLT_SMP8_REG_LRA_SMP_16_Pos (16UL) /*!< LRA_SMP_16 (Bit 16) */ +#define LRA_LRA_FLT_SMP8_REG_LRA_SMP_16_Msk (0xffff0000UL) /*!< LRA_SMP_16 (Bitfield-Mask: 0xffff) */ +#define LRA_LRA_FLT_SMP8_REG_LRA_SMP_15_Pos (0UL) /*!< LRA_SMP_15 (Bit 0) */ +#define LRA_LRA_FLT_SMP8_REG_LRA_SMP_15_Msk (0xffffUL) /*!< LRA_SMP_15 (Bitfield-Mask: 0xffff) */ +/* ====================================================== LRA_LDO_REG ====================================================== */ +#define LRA_LRA_LDO_REG_LDO_OK_Pos (31UL) /*!< LDO_OK (Bit 31) */ +#define LRA_LRA_LDO_REG_LDO_OK_Msk (0x80000000UL) /*!< LDO_OK (Bitfield-Mask: 0x01) */ +#define LRA_LRA_LDO_REG_LDO_TST_Pos (1UL) /*!< LDO_TST (Bit 1) */ +#define LRA_LRA_LDO_REG_LDO_TST_Msk (0x2UL) /*!< LDO_TST (Bitfield-Mask: 0x01) */ +#define LRA_LRA_LDO_REG_LDO_VREF_HOLD_Pos (0UL) /*!< LDO_VREF_HOLD (Bit 0) */ +#define LRA_LRA_LDO_REG_LDO_VREF_HOLD_Msk (0x1UL) /*!< LDO_VREF_HOLD (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ MEMCTRL ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== BUSY_RESET_REG ===================================================== */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_SPARE_Pos (30UL) /*!< BUSY_SPARE (Bit 30) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_SPARE_Msk (0xc0000000UL) /*!< BUSY_SPARE (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_MOTOR_Pos (28UL) /*!< BUSY_MOTOR (Bit 28) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_MOTOR_Msk (0x30000000UL) /*!< BUSY_MOTOR (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER2_Pos (26UL) /*!< BUSY_TIMER2 (Bit 26) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER2_Msk (0xc000000UL) /*!< BUSY_TIMER2 (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER_Pos (24UL) /*!< BUSY_TIMER (Bit 24) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER_Msk (0x3000000UL) /*!< BUSY_TIMER (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_UART3_Pos (22UL) /*!< BUSY_UART3 (Bit 22) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_UART3_Msk (0xc00000UL) /*!< BUSY_UART3 (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_GPADC_Pos (20UL) /*!< BUSY_GPADC (Bit 20) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_GPADC_Msk (0x300000UL) /*!< BUSY_GPADC (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_PDM_Pos (18UL) /*!< BUSY_PDM (Bit 18) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_PDM_Msk (0xc0000UL) /*!< BUSY_PDM (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_SRC_Pos (16UL) /*!< BUSY_SRC (Bit 16) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_SRC_Msk (0x30000UL) /*!< BUSY_SRC (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_PCM_Pos (14UL) /*!< BUSY_PCM (Bit 14) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_PCM_Msk (0xc000UL) /*!< BUSY_PCM (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_SDADC_Pos (12UL) /*!< BUSY_SDADC (Bit 12) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_SDADC_Msk (0x3000UL) /*!< BUSY_SDADC (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_I2C2_Pos (10UL) /*!< BUSY_I2C2 (Bit 10) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_I2C2_Msk (0xc00UL) /*!< BUSY_I2C2 (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_I2C_Pos (8UL) /*!< BUSY_I2C (Bit 8) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_I2C_Msk (0x300UL) /*!< BUSY_I2C (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_SPI2_Pos (6UL) /*!< BUSY_SPI2 (Bit 6) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_SPI2_Msk (0xc0UL) /*!< BUSY_SPI2 (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_SPI_Pos (4UL) /*!< BUSY_SPI (Bit 4) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_SPI_Msk (0x30UL) /*!< BUSY_SPI (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_UART2_Pos (2UL) /*!< BUSY_UART2 (Bit 2) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_UART2_Msk (0xcUL) /*!< BUSY_UART2 (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_UART_Pos (0UL) /*!< BUSY_UART (Bit 0) */ +#define MEMCTRL_BUSY_RESET_REG_BUSY_UART_Msk (0x3UL) /*!< BUSY_UART (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSY_SET_REG ====================================================== */ +#define MEMCTRL_BUSY_SET_REG_BUSY_SPARE_Pos (30UL) /*!< BUSY_SPARE (Bit 30) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_SPARE_Msk (0xc0000000UL) /*!< BUSY_SPARE (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_MOTOR_Pos (28UL) /*!< BUSY_MOTOR (Bit 28) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_MOTOR_Msk (0x30000000UL) /*!< BUSY_MOTOR (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_TIMER2_Pos (26UL) /*!< BUSY_TIMER2 (Bit 26) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_TIMER2_Msk (0xc000000UL) /*!< BUSY_TIMER2 (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_TIMER_Pos (24UL) /*!< BUSY_TIMER (Bit 24) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_TIMER_Msk (0x3000000UL) /*!< BUSY_TIMER (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_UART3_Pos (22UL) /*!< BUSY_UART3 (Bit 22) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_UART3_Msk (0xc00000UL) /*!< BUSY_UART3 (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_GPADC_Pos (20UL) /*!< BUSY_GPADC (Bit 20) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_GPADC_Msk (0x300000UL) /*!< BUSY_GPADC (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_PDM_Pos (18UL) /*!< BUSY_PDM (Bit 18) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_PDM_Msk (0xc0000UL) /*!< BUSY_PDM (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_SRC_Pos (16UL) /*!< BUSY_SRC (Bit 16) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_SRC_Msk (0x30000UL) /*!< BUSY_SRC (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_PCM_Pos (14UL) /*!< BUSY_PCM (Bit 14) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_PCM_Msk (0xc000UL) /*!< BUSY_PCM (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_SDADC_Pos (12UL) /*!< BUSY_SDADC (Bit 12) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_SDADC_Msk (0x3000UL) /*!< BUSY_SDADC (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_I2C2_Pos (10UL) /*!< BUSY_I2C2 (Bit 10) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_I2C2_Msk (0xc00UL) /*!< BUSY_I2C2 (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_I2C_Pos (8UL) /*!< BUSY_I2C (Bit 8) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_I2C_Msk (0x300UL) /*!< BUSY_I2C (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_SPI2_Pos (6UL) /*!< BUSY_SPI2 (Bit 6) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_SPI2_Msk (0xc0UL) /*!< BUSY_SPI2 (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_SPI_Pos (4UL) /*!< BUSY_SPI (Bit 4) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_SPI_Msk (0x30UL) /*!< BUSY_SPI (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_UART2_Pos (2UL) /*!< BUSY_UART2 (Bit 2) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_UART2_Msk (0xcUL) /*!< BUSY_UART2 (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_UART_Pos (0UL) /*!< BUSY_UART (Bit 0) */ +#define MEMCTRL_BUSY_SET_REG_BUSY_UART_Msk (0x3UL) /*!< BUSY_UART (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSY_STAT_REG ===================================================== */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_SPARE_Pos (30UL) /*!< BUSY_SPARE (Bit 30) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_SPARE_Msk (0xc0000000UL) /*!< BUSY_SPARE (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_MOTOR_Pos (28UL) /*!< BUSY_MOTOR (Bit 28) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_MOTOR_Msk (0x30000000UL) /*!< BUSY_MOTOR (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER2_Pos (26UL) /*!< BUSY_TIMER2 (Bit 26) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER2_Msk (0xc000000UL) /*!< BUSY_TIMER2 (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER_Pos (24UL) /*!< BUSY_TIMER (Bit 24) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER_Msk (0x3000000UL) /*!< BUSY_TIMER (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_UART3_Pos (22UL) /*!< BUSY_UART3 (Bit 22) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_UART3_Msk (0xc00000UL) /*!< BUSY_UART3 (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_GPADC_Pos (20UL) /*!< BUSY_GPADC (Bit 20) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_GPADC_Msk (0x300000UL) /*!< BUSY_GPADC (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_PDM_Pos (18UL) /*!< BUSY_PDM (Bit 18) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_PDM_Msk (0xc0000UL) /*!< BUSY_PDM (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_SRC_Pos (16UL) /*!< BUSY_SRC (Bit 16) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_SRC_Msk (0x30000UL) /*!< BUSY_SRC (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_PCM_Pos (14UL) /*!< BUSY_PCM (Bit 14) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_PCM_Msk (0xc000UL) /*!< BUSY_PCM (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_SDADC_Pos (12UL) /*!< BUSY_SDADC (Bit 12) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_SDADC_Msk (0x3000UL) /*!< BUSY_SDADC (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_I2C2_Pos (10UL) /*!< BUSY_I2C2 (Bit 10) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_I2C2_Msk (0xc00UL) /*!< BUSY_I2C2 (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_I2C_Pos (8UL) /*!< BUSY_I2C (Bit 8) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_I2C_Msk (0x300UL) /*!< BUSY_I2C (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_SPI2_Pos (6UL) /*!< BUSY_SPI2 (Bit 6) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_SPI2_Msk (0xc0UL) /*!< BUSY_SPI2 (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_SPI_Pos (4UL) /*!< BUSY_SPI (Bit 4) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_SPI_Msk (0x30UL) /*!< BUSY_SPI (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_UART2_Pos (2UL) /*!< BUSY_UART2 (Bit 2) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_UART2_Msk (0xcUL) /*!< BUSY_UART2 (Bitfield-Mask: 0x03) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_UART_Pos (0UL) /*!< BUSY_UART (Bit 0) */ +#define MEMCTRL_BUSY_STAT_REG_BUSY_UART_Msk (0x3UL) /*!< BUSY_UART (Bitfield-Mask: 0x03) */ +/* =================================================== CMI_CODE_BASE_REG =================================================== */ +#define MEMCTRL_CMI_CODE_BASE_REG_CMI_CODE_BASE_ADDR_Pos (10UL) /*!< CMI_CODE_BASE_ADDR (Bit 10) */ +#define MEMCTRL_CMI_CODE_BASE_REG_CMI_CODE_BASE_ADDR_Msk (0x7fc00UL) /*!< CMI_CODE_BASE_ADDR (Bitfield-Mask: 0x1ff) */ +/* =================================================== CMI_DATA_BASE_REG =================================================== */ +#define MEMCTRL_CMI_DATA_BASE_REG_CMI_DATA_BASE_ADDR_Pos (2UL) /*!< CMI_DATA_BASE_ADDR (Bit 2) */ +#define MEMCTRL_CMI_DATA_BASE_REG_CMI_DATA_BASE_ADDR_Msk (0x7fffcUL) /*!< CMI_DATA_BASE_ADDR (Bitfield-Mask: 0x1ffff) */ +/* ====================================================== CMI_END_REG ====================================================== */ +#define MEMCTRL_CMI_END_REG_CMI_END_ADDR_Pos (10UL) /*!< CMI_END_ADDR (Bit 10) */ +#define MEMCTRL_CMI_END_REG_CMI_END_ADDR_Msk (0x7fc00UL) /*!< CMI_END_ADDR (Bitfield-Mask: 0x1ff) */ +/* ================================================== CMI_SHARED_BASE_REG ================================================== */ +#define MEMCTRL_CMI_SHARED_BASE_REG_CMI_SHARED_BASE_ADDR_Pos (10UL) /*!< CMI_SHARED_BASE_ADDR (Bit 10) */ +#define MEMCTRL_CMI_SHARED_BASE_REG_CMI_SHARED_BASE_ADDR_Msk (0x7fc00UL) /*!< CMI_SHARED_BASE_ADDR (Bitfield-Mask: 0x1ff) */ +/* ===================================================== MEM_PRIO_REG ====================================================== */ +#define MEMCTRL_MEM_PRIO_REG_AHB_PRIO_Pos (4UL) /*!< AHB_PRIO (Bit 4) */ +#define MEMCTRL_MEM_PRIO_REG_AHB_PRIO_Msk (0x30UL) /*!< AHB_PRIO (Bitfield-Mask: 0x03) */ +#define MEMCTRL_MEM_PRIO_REG_AHB2_PRIO_Pos (2UL) /*!< AHB2_PRIO (Bit 2) */ +#define MEMCTRL_MEM_PRIO_REG_AHB2_PRIO_Msk (0xcUL) /*!< AHB2_PRIO (Bitfield-Mask: 0x03) */ +#define MEMCTRL_MEM_PRIO_REG_SNC_PRIO_Pos (0UL) /*!< SNC_PRIO (Bit 0) */ +#define MEMCTRL_MEM_PRIO_REG_SNC_PRIO_Msk (0x3UL) /*!< SNC_PRIO (Bitfield-Mask: 0x03) */ +/* ===================================================== MEM_STALL_REG ===================================================== */ +#define MEMCTRL_MEM_STALL_REG_AHB_MAX_STALL_Pos (8UL) /*!< AHB_MAX_STALL (Bit 8) */ +#define MEMCTRL_MEM_STALL_REG_AHB_MAX_STALL_Msk (0xf00UL) /*!< AHB_MAX_STALL (Bitfield-Mask: 0x0f) */ +#define MEMCTRL_MEM_STALL_REG_AHB2_MAX_STALL_Pos (4UL) /*!< AHB2_MAX_STALL (Bit 4) */ +#define MEMCTRL_MEM_STALL_REG_AHB2_MAX_STALL_Msk (0xf0UL) /*!< AHB2_MAX_STALL (Bitfield-Mask: 0x0f) */ +#define MEMCTRL_MEM_STALL_REG_SNC_MAX_STALL_Pos (0UL) /*!< SNC_MAX_STALL (Bit 0) */ +#define MEMCTRL_MEM_STALL_REG_SNC_MAX_STALL_Msk (0xfUL) /*!< SNC_MAX_STALL (Bitfield-Mask: 0x0f) */ +/* ==================================================== MEM_STATUS2_REG ==================================================== */ +#define MEMCTRL_MEM_STATUS2_REG_RAM8_OFF_BUT_ACCESS_Pos (7UL) /*!< RAM8_OFF_BUT_ACCESS (Bit 7) */ +#define MEMCTRL_MEM_STATUS2_REG_RAM8_OFF_BUT_ACCESS_Msk (0x80UL) /*!< RAM8_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ +#define MEMCTRL_MEM_STATUS2_REG_RAM7_OFF_BUT_ACCESS_Pos (6UL) /*!< RAM7_OFF_BUT_ACCESS (Bit 6) */ +#define MEMCTRL_MEM_STATUS2_REG_RAM7_OFF_BUT_ACCESS_Msk (0x40UL) /*!< RAM7_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ +#define MEMCTRL_MEM_STATUS2_REG_RAM6_OFF_BUT_ACCESS_Pos (5UL) /*!< RAM6_OFF_BUT_ACCESS (Bit 5) */ +#define MEMCTRL_MEM_STATUS2_REG_RAM6_OFF_BUT_ACCESS_Msk (0x20UL) /*!< RAM6_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ +#define MEMCTRL_MEM_STATUS2_REG_RAM5_OFF_BUT_ACCESS_Pos (4UL) /*!< RAM5_OFF_BUT_ACCESS (Bit 4) */ +#define MEMCTRL_MEM_STATUS2_REG_RAM5_OFF_BUT_ACCESS_Msk (0x10UL) /*!< RAM5_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ +#define MEMCTRL_MEM_STATUS2_REG_RAM4_OFF_BUT_ACCESS_Pos (3UL) /*!< RAM4_OFF_BUT_ACCESS (Bit 3) */ +#define MEMCTRL_MEM_STATUS2_REG_RAM4_OFF_BUT_ACCESS_Msk (0x8UL) /*!< RAM4_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ +#define MEMCTRL_MEM_STATUS2_REG_RAM3_OFF_BUT_ACCESS_Pos (2UL) /*!< RAM3_OFF_BUT_ACCESS (Bit 2) */ +#define MEMCTRL_MEM_STATUS2_REG_RAM3_OFF_BUT_ACCESS_Msk (0x4UL) /*!< RAM3_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ +#define MEMCTRL_MEM_STATUS2_REG_RAM2_OFF_BUT_ACCESS_Pos (1UL) /*!< RAM2_OFF_BUT_ACCESS (Bit 1) */ +#define MEMCTRL_MEM_STATUS2_REG_RAM2_OFF_BUT_ACCESS_Msk (0x2UL) /*!< RAM2_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ +#define MEMCTRL_MEM_STATUS2_REG_RAM1_OFF_BUT_ACCESS_Pos (0UL) /*!< RAM1_OFF_BUT_ACCESS (Bit 0) */ +#define MEMCTRL_MEM_STATUS2_REG_RAM1_OFF_BUT_ACCESS_Msk (0x1UL) /*!< RAM1_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */ +/* ==================================================== MEM_STATUS_REG ===================================================== */ +#define MEMCTRL_MEM_STATUS_REG_CMI_CLEAR_READY_Pos (13UL) /*!< CMI_CLEAR_READY (Bit 13) */ +#define MEMCTRL_MEM_STATUS_REG_CMI_CLEAR_READY_Msk (0x2000UL) /*!< CMI_CLEAR_READY (Bitfield-Mask: 0x01) */ +#define MEMCTRL_MEM_STATUS_REG_CMI_NOT_READY_Pos (12UL) /*!< CMI_NOT_READY (Bit 12) */ +#define MEMCTRL_MEM_STATUS_REG_CMI_NOT_READY_Msk (0x1000UL) /*!< CMI_NOT_READY (Bitfield-Mask: 0x01) */ +#define MEMCTRL_MEM_STATUS_REG_AHB2_WR_BUFF_CNT_Pos (8UL) /*!< AHB2_WR_BUFF_CNT (Bit 8) */ +#define MEMCTRL_MEM_STATUS_REG_AHB2_WR_BUFF_CNT_Msk (0xf00UL) /*!< AHB2_WR_BUFF_CNT (Bitfield-Mask: 0x0f) */ +#define MEMCTRL_MEM_STATUS_REG_AHB_WR_BUFF_CNT_Pos (4UL) /*!< AHB_WR_BUFF_CNT (Bit 4) */ +#define MEMCTRL_MEM_STATUS_REG_AHB_WR_BUFF_CNT_Msk (0xf0UL) /*!< AHB_WR_BUFF_CNT (Bitfield-Mask: 0x0f) */ +#define MEMCTRL_MEM_STATUS_REG_AHB2_CLR_WR_BUFF_Pos (3UL) /*!< AHB2_CLR_WR_BUFF (Bit 3) */ +#define MEMCTRL_MEM_STATUS_REG_AHB2_CLR_WR_BUFF_Msk (0x8UL) /*!< AHB2_CLR_WR_BUFF (Bitfield-Mask: 0x01) */ +#define MEMCTRL_MEM_STATUS_REG_AHB_CLR_WR_BUFF_Pos (2UL) /*!< AHB_CLR_WR_BUFF (Bit 2) */ +#define MEMCTRL_MEM_STATUS_REG_AHB_CLR_WR_BUFF_Msk (0x4UL) /*!< AHB_CLR_WR_BUFF (Bitfield-Mask: 0x01) */ +#define MEMCTRL_MEM_STATUS_REG_AHB2_WRITE_BUFF_Pos (1UL) /*!< AHB2_WRITE_BUFF (Bit 1) */ +#define MEMCTRL_MEM_STATUS_REG_AHB2_WRITE_BUFF_Msk (0x2UL) /*!< AHB2_WRITE_BUFF (Bitfield-Mask: 0x01) */ +#define MEMCTRL_MEM_STATUS_REG_AHB_WRITE_BUFF_Pos (0UL) /*!< AHB_WRITE_BUFF (Bit 0) */ +#define MEMCTRL_MEM_STATUS_REG_AHB_WRITE_BUFF_Msk (0x1UL) /*!< AHB_WRITE_BUFF (Bitfield-Mask: 0x01) */ +/* ===================================================== SNC_BASE_REG ====================================================== */ +#define MEMCTRL_SNC_BASE_REG_SNC_BASE_ADDRESS_Pos (2UL) /*!< SNC_BASE_ADDRESS (Bit 2) */ +#define MEMCTRL_SNC_BASE_REG_SNC_BASE_ADDRESS_Msk (0x7fffcUL) /*!< SNC_BASE_ADDRESS (Bitfield-Mask: 0x1ffff) */ + + +/* =========================================================================================================================== */ +/* ================ OTPC ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== OTPC_MODE_REG ===================================================== */ +#define OTPC_OTPC_MODE_REG_OTPC_MODE_PRG_SEL_Pos (6UL) /*!< OTPC_MODE_PRG_SEL (Bit 6) */ +#define OTPC_OTPC_MODE_REG_OTPC_MODE_PRG_SEL_Msk (0xc0UL) /*!< OTPC_MODE_PRG_SEL (Bitfield-Mask: 0x03) */ +#define OTPC_OTPC_MODE_REG_OTPC_MODE_HT_MARG_EN_Pos (5UL) /*!< OTPC_MODE_HT_MARG_EN (Bit 5) */ +#define OTPC_OTPC_MODE_REG_OTPC_MODE_HT_MARG_EN_Msk (0x20UL) /*!< OTPC_MODE_HT_MARG_EN (Bitfield-Mask: 0x01) */ +#define OTPC_OTPC_MODE_REG_OTPC_MODE_USE_TST_ROW_Pos (4UL) /*!< OTPC_MODE_USE_TST_ROW (Bit 4) */ +#define OTPC_OTPC_MODE_REG_OTPC_MODE_USE_TST_ROW_Msk (0x10UL) /*!< OTPC_MODE_USE_TST_ROW (Bitfield-Mask: 0x01) */ +#define OTPC_OTPC_MODE_REG_OTPC_MODE_MODE_Pos (0UL) /*!< OTPC_MODE_MODE (Bit 0) */ +#define OTPC_OTPC_MODE_REG_OTPC_MODE_MODE_Msk (0x7UL) /*!< OTPC_MODE_MODE (Bitfield-Mask: 0x07) */ +/* ==================================================== OTPC_PADDR_REG ===================================================== */ +#define OTPC_OTPC_PADDR_REG_OTPC_PADDR_Pos (0UL) /*!< OTPC_PADDR (Bit 0) */ +#define OTPC_OTPC_PADDR_REG_OTPC_PADDR_Msk (0x3ffUL) /*!< OTPC_PADDR (Bitfield-Mask: 0x3ff) */ +/* ==================================================== OTPC_PWORD_REG ===================================================== */ +#define OTPC_OTPC_PWORD_REG_OTPC_PWORD_Pos (0UL) /*!< OTPC_PWORD (Bit 0) */ +#define OTPC_OTPC_PWORD_REG_OTPC_PWORD_Msk (0xffffffffUL) /*!< OTPC_PWORD (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== OTPC_STAT_REG ===================================================== */ +#define OTPC_OTPC_STAT_REG_OTPC_STAT_MRDY_Pos (2UL) /*!< OTPC_STAT_MRDY (Bit 2) */ +#define OTPC_OTPC_STAT_REG_OTPC_STAT_MRDY_Msk (0x4UL) /*!< OTPC_STAT_MRDY (Bitfield-Mask: 0x01) */ +#define OTPC_OTPC_STAT_REG_OTPC_STAT_PBUF_EMPTY_Pos (1UL) /*!< OTPC_STAT_PBUF_EMPTY (Bit 1) */ +#define OTPC_OTPC_STAT_REG_OTPC_STAT_PBUF_EMPTY_Msk (0x2UL) /*!< OTPC_STAT_PBUF_EMPTY (Bitfield-Mask: 0x01) */ +#define OTPC_OTPC_STAT_REG_OTPC_STAT_PRDY_Pos (0UL) /*!< OTPC_STAT_PRDY (Bit 0) */ +#define OTPC_OTPC_STAT_REG_OTPC_STAT_PRDY_Msk (0x1UL) /*!< OTPC_STAT_PRDY (Bitfield-Mask: 0x01) */ +/* ===================================================== OTPC_TIM1_REG ===================================================== */ +#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_CSP_Pos (24UL) /*!< OTPC_TIM1_US_T_CSP (Bit 24) */ +#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_CSP_Msk (0x7f000000UL) /*!< OTPC_TIM1_US_T_CSP (Bitfield-Mask: 0x7f) */ +#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_CS_Pos (20UL) /*!< OTPC_TIM1_US_T_CS (Bit 20) */ +#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_CS_Msk (0xf00000UL) /*!< OTPC_TIM1_US_T_CS (Bitfield-Mask: 0x0f) */ +#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_PL_Pos (16UL) /*!< OTPC_TIM1_US_T_PL (Bit 16) */ +#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_PL_Msk (0xf0000UL) /*!< OTPC_TIM1_US_T_PL (Bitfield-Mask: 0x0f) */ +#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_RD_Pos (12UL) /*!< OTPC_TIM1_CC_T_RD (Bit 12) */ +#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_RD_Msk (0x7000UL) /*!< OTPC_TIM1_CC_T_RD (Bitfield-Mask: 0x07) */ +#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_20NS_Pos (8UL) /*!< OTPC_TIM1_CC_T_20NS (Bit 8) */ +#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_20NS_Msk (0x300UL) /*!< OTPC_TIM1_CC_T_20NS (Bitfield-Mask: 0x03) */ +#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos (0UL) /*!< OTPC_TIM1_CC_T_1US (Bit 0) */ +#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Msk (0x7fUL) /*!< OTPC_TIM1_CC_T_1US (Bitfield-Mask: 0x7f) */ +/* ===================================================== OTPC_TIM2_REG ===================================================== */ +#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_ADD_CC_EN_Pos (31UL) /*!< OTPC_TIM2_US_ADD_CC_EN (Bit 31) */ +#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_ADD_CC_EN_Msk (0x80000000UL) /*!< OTPC_TIM2_US_ADD_CC_EN (Bitfield-Mask: 0x01) */ +#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_SAS_Pos (29UL) /*!< OTPC_TIM2_US_T_SAS (Bit 29) */ +#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_SAS_Msk (0x60000000UL) /*!< OTPC_TIM2_US_T_SAS (Bitfield-Mask: 0x03) */ +#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PPH_Pos (24UL) /*!< OTPC_TIM2_US_T_PPH (Bit 24) */ +#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PPH_Msk (0x1f000000UL) /*!< OTPC_TIM2_US_T_PPH (Bitfield-Mask: 0x1f) */ +#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_VDS_Pos (21UL) /*!< OTPC_TIM2_US_T_VDS (Bit 21) */ +#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_VDS_Msk (0xe00000UL) /*!< OTPC_TIM2_US_T_VDS (Bitfield-Mask: 0x07) */ +#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PPS_Pos (16UL) /*!< OTPC_TIM2_US_T_PPS (Bit 16) */ +#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PPS_Msk (0x1f0000UL) /*!< OTPC_TIM2_US_T_PPS (Bitfield-Mask: 0x1f) */ +#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PPR_Pos (8UL) /*!< OTPC_TIM2_US_T_PPR (Bit 8) */ +#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PPR_Msk (0x7f00UL) /*!< OTPC_TIM2_US_T_PPR (Bitfield-Mask: 0x7f) */ +#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PWI_Pos (5UL) /*!< OTPC_TIM2_US_T_PWI (Bit 5) */ +#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PWI_Msk (0xe0UL) /*!< OTPC_TIM2_US_T_PWI (Bitfield-Mask: 0x07) */ +#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PW_Pos (0UL) /*!< OTPC_TIM2_US_T_PW (Bit 0) */ +#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PW_Msk (0x1fUL) /*!< OTPC_TIM2_US_T_PW (Bitfield-Mask: 0x1f) */ + + +/* =========================================================================================================================== */ +/* ================ PDC ================ */ +/* =========================================================================================================================== */ + +/* ================================================== PDC_ACKNOWLEDGE_REG ================================================== */ +#define PDC_PDC_ACKNOWLEDGE_REG_PDC_ACKNOWLEDGE_Pos (0UL) /*!< PDC_ACKNOWLEDGE (Bit 0) */ +#define PDC_PDC_ACKNOWLEDGE_REG_PDC_ACKNOWLEDGE_Msk (0x1fUL) /*!< PDC_ACKNOWLEDGE (Bitfield-Mask: 0x1f) */ +/* ===================================================== PDC_CTRL0_REG ===================================================== */ +#define PDC_PDC_CTRL0_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */ +#define PDC_PDC_CTRL0_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */ +#define PDC_PDC_CTRL0_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */ +#define PDC_PDC_CTRL0_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL0_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */ +#define PDC_PDC_CTRL0_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL0_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */ +#define PDC_PDC_CTRL0_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL0_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */ +#define PDC_PDC_CTRL0_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL0_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */ +#define PDC_PDC_CTRL0_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */ +#define PDC_PDC_CTRL0_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */ +#define PDC_PDC_CTRL0_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */ +/* ==================================================== PDC_CTRL10_REG ===================================================== */ +#define PDC_PDC_CTRL10_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */ +#define PDC_PDC_CTRL10_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */ +#define PDC_PDC_CTRL10_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */ +#define PDC_PDC_CTRL10_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL10_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */ +#define PDC_PDC_CTRL10_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL10_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */ +#define PDC_PDC_CTRL10_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL10_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */ +#define PDC_PDC_CTRL10_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL10_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */ +#define PDC_PDC_CTRL10_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */ +#define PDC_PDC_CTRL10_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */ +#define PDC_PDC_CTRL10_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */ +/* ==================================================== PDC_CTRL11_REG ===================================================== */ +#define PDC_PDC_CTRL11_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */ +#define PDC_PDC_CTRL11_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */ +#define PDC_PDC_CTRL11_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */ +#define PDC_PDC_CTRL11_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL11_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */ +#define PDC_PDC_CTRL11_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL11_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */ +#define PDC_PDC_CTRL11_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL11_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */ +#define PDC_PDC_CTRL11_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL11_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */ +#define PDC_PDC_CTRL11_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */ +#define PDC_PDC_CTRL11_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */ +#define PDC_PDC_CTRL11_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */ +/* ==================================================== PDC_CTRL12_REG ===================================================== */ +#define PDC_PDC_CTRL12_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */ +#define PDC_PDC_CTRL12_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */ +#define PDC_PDC_CTRL12_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */ +#define PDC_PDC_CTRL12_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL12_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */ +#define PDC_PDC_CTRL12_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL12_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */ +#define PDC_PDC_CTRL12_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL12_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */ +#define PDC_PDC_CTRL12_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL12_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */ +#define PDC_PDC_CTRL12_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */ +#define PDC_PDC_CTRL12_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */ +#define PDC_PDC_CTRL12_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */ +/* ==================================================== PDC_CTRL13_REG ===================================================== */ +#define PDC_PDC_CTRL13_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */ +#define PDC_PDC_CTRL13_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */ +#define PDC_PDC_CTRL13_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */ +#define PDC_PDC_CTRL13_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL13_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */ +#define PDC_PDC_CTRL13_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL13_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */ +#define PDC_PDC_CTRL13_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL13_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */ +#define PDC_PDC_CTRL13_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL13_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */ +#define PDC_PDC_CTRL13_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */ +#define PDC_PDC_CTRL13_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */ +#define PDC_PDC_CTRL13_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */ +/* ==================================================== PDC_CTRL14_REG ===================================================== */ +#define PDC_PDC_CTRL14_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */ +#define PDC_PDC_CTRL14_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */ +#define PDC_PDC_CTRL14_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */ +#define PDC_PDC_CTRL14_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL14_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */ +#define PDC_PDC_CTRL14_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL14_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */ +#define PDC_PDC_CTRL14_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL14_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */ +#define PDC_PDC_CTRL14_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL14_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */ +#define PDC_PDC_CTRL14_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */ +#define PDC_PDC_CTRL14_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */ +#define PDC_PDC_CTRL14_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */ +/* ==================================================== PDC_CTRL15_REG ===================================================== */ +#define PDC_PDC_CTRL15_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */ +#define PDC_PDC_CTRL15_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */ +#define PDC_PDC_CTRL15_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */ +#define PDC_PDC_CTRL15_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL15_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */ +#define PDC_PDC_CTRL15_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL15_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */ +#define PDC_PDC_CTRL15_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL15_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */ +#define PDC_PDC_CTRL15_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL15_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */ +#define PDC_PDC_CTRL15_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */ +#define PDC_PDC_CTRL15_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */ +#define PDC_PDC_CTRL15_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */ +/* ===================================================== PDC_CTRL1_REG ===================================================== */ +#define PDC_PDC_CTRL1_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */ +#define PDC_PDC_CTRL1_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */ +#define PDC_PDC_CTRL1_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */ +#define PDC_PDC_CTRL1_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL1_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */ +#define PDC_PDC_CTRL1_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL1_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */ +#define PDC_PDC_CTRL1_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL1_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */ +#define PDC_PDC_CTRL1_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL1_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */ +#define PDC_PDC_CTRL1_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */ +#define PDC_PDC_CTRL1_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */ +#define PDC_PDC_CTRL1_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */ +/* ===================================================== PDC_CTRL2_REG ===================================================== */ +#define PDC_PDC_CTRL2_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */ +#define PDC_PDC_CTRL2_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */ +#define PDC_PDC_CTRL2_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */ +#define PDC_PDC_CTRL2_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL2_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */ +#define PDC_PDC_CTRL2_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL2_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */ +#define PDC_PDC_CTRL2_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL2_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */ +#define PDC_PDC_CTRL2_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL2_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */ +#define PDC_PDC_CTRL2_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */ +#define PDC_PDC_CTRL2_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */ +#define PDC_PDC_CTRL2_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */ +/* ===================================================== PDC_CTRL3_REG ===================================================== */ +#define PDC_PDC_CTRL3_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */ +#define PDC_PDC_CTRL3_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */ +#define PDC_PDC_CTRL3_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */ +#define PDC_PDC_CTRL3_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL3_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */ +#define PDC_PDC_CTRL3_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL3_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */ +#define PDC_PDC_CTRL3_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL3_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */ +#define PDC_PDC_CTRL3_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL3_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */ +#define PDC_PDC_CTRL3_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */ +#define PDC_PDC_CTRL3_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */ +#define PDC_PDC_CTRL3_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */ +/* ===================================================== PDC_CTRL4_REG ===================================================== */ +#define PDC_PDC_CTRL4_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */ +#define PDC_PDC_CTRL4_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */ +#define PDC_PDC_CTRL4_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */ +#define PDC_PDC_CTRL4_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL4_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */ +#define PDC_PDC_CTRL4_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL4_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */ +#define PDC_PDC_CTRL4_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL4_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */ +#define PDC_PDC_CTRL4_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL4_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */ +#define PDC_PDC_CTRL4_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */ +#define PDC_PDC_CTRL4_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */ +#define PDC_PDC_CTRL4_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */ +/* ===================================================== PDC_CTRL5_REG ===================================================== */ +#define PDC_PDC_CTRL5_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */ +#define PDC_PDC_CTRL5_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */ +#define PDC_PDC_CTRL5_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */ +#define PDC_PDC_CTRL5_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL5_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */ +#define PDC_PDC_CTRL5_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL5_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */ +#define PDC_PDC_CTRL5_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL5_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */ +#define PDC_PDC_CTRL5_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL5_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */ +#define PDC_PDC_CTRL5_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */ +#define PDC_PDC_CTRL5_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */ +#define PDC_PDC_CTRL5_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */ +/* ===================================================== PDC_CTRL6_REG ===================================================== */ +#define PDC_PDC_CTRL6_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */ +#define PDC_PDC_CTRL6_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */ +#define PDC_PDC_CTRL6_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */ +#define PDC_PDC_CTRL6_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL6_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */ +#define PDC_PDC_CTRL6_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL6_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */ +#define PDC_PDC_CTRL6_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL6_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */ +#define PDC_PDC_CTRL6_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL6_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */ +#define PDC_PDC_CTRL6_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */ +#define PDC_PDC_CTRL6_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */ +#define PDC_PDC_CTRL6_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */ +/* ===================================================== PDC_CTRL7_REG ===================================================== */ +#define PDC_PDC_CTRL7_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */ +#define PDC_PDC_CTRL7_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */ +#define PDC_PDC_CTRL7_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */ +#define PDC_PDC_CTRL7_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL7_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */ +#define PDC_PDC_CTRL7_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL7_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */ +#define PDC_PDC_CTRL7_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL7_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */ +#define PDC_PDC_CTRL7_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL7_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */ +#define PDC_PDC_CTRL7_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */ +#define PDC_PDC_CTRL7_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */ +#define PDC_PDC_CTRL7_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */ +/* ===================================================== PDC_CTRL8_REG ===================================================== */ +#define PDC_PDC_CTRL8_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */ +#define PDC_PDC_CTRL8_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */ +#define PDC_PDC_CTRL8_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */ +#define PDC_PDC_CTRL8_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL8_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */ +#define PDC_PDC_CTRL8_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL8_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */ +#define PDC_PDC_CTRL8_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL8_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */ +#define PDC_PDC_CTRL8_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL8_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */ +#define PDC_PDC_CTRL8_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */ +#define PDC_PDC_CTRL8_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */ +#define PDC_PDC_CTRL8_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */ +/* ===================================================== PDC_CTRL9_REG ===================================================== */ +#define PDC_PDC_CTRL9_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */ +#define PDC_PDC_CTRL9_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */ +#define PDC_PDC_CTRL9_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */ +#define PDC_PDC_CTRL9_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL9_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */ +#define PDC_PDC_CTRL9_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL9_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */ +#define PDC_PDC_CTRL9_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL9_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */ +#define PDC_PDC_CTRL9_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */ +#define PDC_PDC_CTRL9_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */ +#define PDC_PDC_CTRL9_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */ +#define PDC_PDC_CTRL9_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */ +#define PDC_PDC_CTRL9_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */ +/* ================================================= PDC_PENDING_CM33_REG ================================================== */ +#define PDC_PDC_PENDING_CM33_REG_PDC_PENDING_Pos (0UL) /*!< PDC_PENDING (Bit 0) */ +#define PDC_PDC_PENDING_CM33_REG_PDC_PENDING_Msk (0xffffUL) /*!< PDC_PENDING (Bitfield-Mask: 0xffff) */ +/* ================================================= PDC_PENDING_CMAC_REG ================================================== */ +#define PDC_PDC_PENDING_CMAC_REG_PDC_PENDING_Pos (0UL) /*!< PDC_PENDING (Bit 0) */ +#define PDC_PDC_PENDING_CMAC_REG_PDC_PENDING_Msk (0xffffUL) /*!< PDC_PENDING (Bitfield-Mask: 0xffff) */ +/* ==================================================== PDC_PENDING_REG ==================================================== */ +#define PDC_PDC_PENDING_REG_PDC_PENDING_Pos (0UL) /*!< PDC_PENDING (Bit 0) */ +#define PDC_PDC_PENDING_REG_PDC_PENDING_Msk (0xffffUL) /*!< PDC_PENDING (Bitfield-Mask: 0xffff) */ +/* ================================================== PDC_PENDING_SNC_REG ================================================== */ +#define PDC_PDC_PENDING_SNC_REG_PDC_PENDING_Pos (0UL) /*!< PDC_PENDING (Bit 0) */ +#define PDC_PDC_PENDING_SNC_REG_PDC_PENDING_Msk (0xffffUL) /*!< PDC_PENDING (Bitfield-Mask: 0xffff) */ +/* ================================================== PDC_SET_PENDING_REG ================================================== */ +#define PDC_PDC_SET_PENDING_REG_PDC_SET_PENDING_Pos (0UL) /*!< PDC_SET_PENDING (Bit 0) */ +#define PDC_PDC_SET_PENDING_REG_PDC_SET_PENDING_Msk (0x1fUL) /*!< PDC_SET_PENDING (Bitfield-Mask: 0x1f) */ + + +/* =========================================================================================================================== */ +/* ================ PWMLED ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== PWMLED_CTRL_REG ==================================================== */ +#define PWMLED_PWMLED_CTRL_REG_LED2_LOAD_SEL_Pos (11UL) /*!< LED2_LOAD_SEL (Bit 11) */ +#define PWMLED_PWMLED_CTRL_REG_LED2_LOAD_SEL_Msk (0x3800UL) /*!< LED2_LOAD_SEL (Bitfield-Mask: 0x07) */ +#define PWMLED_PWMLED_CTRL_REG_LED1_LOAD_SEL_Pos (8UL) /*!< LED1_LOAD_SEL (Bit 8) */ +#define PWMLED_PWMLED_CTRL_REG_LED1_LOAD_SEL_Msk (0x700UL) /*!< LED1_LOAD_SEL (Bitfield-Mask: 0x07) */ +#define PWMLED_PWMLED_CTRL_REG_LED2_EN_Pos (7UL) /*!< LED2_EN (Bit 7) */ +#define PWMLED_PWMLED_CTRL_REG_LED2_EN_Msk (0x80UL) /*!< LED2_EN (Bitfield-Mask: 0x01) */ +#define PWMLED_PWMLED_CTRL_REG_LED1_EN_Pos (6UL) /*!< LED1_EN (Bit 6) */ +#define PWMLED_PWMLED_CTRL_REG_LED1_EN_Msk (0x40UL) /*!< LED1_EN (Bitfield-Mask: 0x01) */ +#define PWMLED_PWMLED_CTRL_REG_LED_TRIM_Pos (2UL) /*!< LED_TRIM (Bit 2) */ +#define PWMLED_PWMLED_CTRL_REG_LED_TRIM_Msk (0x3cUL) /*!< LED_TRIM (Bitfield-Mask: 0x0f) */ +#define PWMLED_PWMLED_CTRL_REG_SW_PAUSE_EN_Pos (1UL) /*!< SW_PAUSE_EN (Bit 1) */ +#define PWMLED_PWMLED_CTRL_REG_SW_PAUSE_EN_Msk (0x2UL) /*!< SW_PAUSE_EN (Bitfield-Mask: 0x01) */ +#define PWMLED_PWMLED_CTRL_REG_PWM_ENABLE_Pos (0UL) /*!< PWM_ENABLE (Bit 0) */ +#define PWMLED_PWMLED_CTRL_REG_PWM_ENABLE_Msk (0x1UL) /*!< PWM_ENABLE (Bitfield-Mask: 0x01) */ +/* ============================================== PWMLED_DUTY_CYCLE_LED1_REG =============================================== */ +#define PWMLED_PWMLED_DUTY_CYCLE_LED1_REG_LED1_PWM_START_CYCLE_Pos (8UL) /*!< LED1_PWM_START_CYCLE (Bit 8) */ +#define PWMLED_PWMLED_DUTY_CYCLE_LED1_REG_LED1_PWM_START_CYCLE_Msk (0xff00UL) /*!< LED1_PWM_START_CYCLE (Bitfield-Mask: 0xff) */ +#define PWMLED_PWMLED_DUTY_CYCLE_LED1_REG_LED1_PWM_END_CYCLE_Pos (0UL) /*!< LED1_PWM_END_CYCLE (Bit 0) */ +#define PWMLED_PWMLED_DUTY_CYCLE_LED1_REG_LED1_PWM_END_CYCLE_Msk (0xffUL) /*!< LED1_PWM_END_CYCLE (Bitfield-Mask: 0xff) */ +/* ============================================== PWMLED_DUTY_CYCLE_LED2_REG =============================================== */ +#define PWMLED_PWMLED_DUTY_CYCLE_LED2_REG_LED2_PWM_START_CYCLE_Pos (8UL) /*!< LED2_PWM_START_CYCLE (Bit 8) */ +#define PWMLED_PWMLED_DUTY_CYCLE_LED2_REG_LED2_PWM_START_CYCLE_Msk (0xff00UL) /*!< LED2_PWM_START_CYCLE (Bitfield-Mask: 0xff) */ +#define PWMLED_PWMLED_DUTY_CYCLE_LED2_REG_LED2_PWM_END_CYCLE_Pos (0UL) /*!< LED2_PWM_END_CYCLE (Bit 0) */ +#define PWMLED_PWMLED_DUTY_CYCLE_LED2_REG_LED2_PWM_END_CYCLE_Msk (0xffUL) /*!< LED2_PWM_END_CYCLE (Bitfield-Mask: 0xff) */ +/* ================================================= PWMLED_FREQUENCY_REG ================================================== */ +#define PWMLED_PWMLED_FREQUENCY_REG_LED_PWM_FREQUENCY_Pos (0UL) /*!< LED_PWM_FREQUENCY (Bit 0) */ +#define PWMLED_PWMLED_FREQUENCY_REG_LED_PWM_FREQUENCY_Msk (0xffUL) /*!< LED_PWM_FREQUENCY (Bitfield-Mask: 0xff) */ + + +/* =========================================================================================================================== */ +/* ================ QSPIC ================ */ +/* =========================================================================================================================== */ + +/* ================================================== QSPIC_BURSTBRK_REG =================================================== */ +#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_SEC_HF_DS_Pos (20UL) /*!< QSPIC_SEC_HF_DS (Bit 20) */ +#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_SEC_HF_DS_Msk (0x100000UL) /*!< QSPIC_SEC_HF_DS (Bitfield-Mask: 0x01) */ +#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_TX_MD_Pos (18UL) /*!< QSPIC_BRK_TX_MD (Bit 18) */ +#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_TX_MD_Msk (0xc0000UL) /*!< QSPIC_BRK_TX_MD (Bitfield-Mask: 0x03) */ +#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_SZ_Pos (17UL) /*!< QSPIC_BRK_SZ (Bit 17) */ +#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_SZ_Msk (0x20000UL) /*!< QSPIC_BRK_SZ (Bitfield-Mask: 0x01) */ +#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_EN_Pos (16UL) /*!< QSPIC_BRK_EN (Bit 16) */ +#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_EN_Msk (0x10000UL) /*!< QSPIC_BRK_EN (Bitfield-Mask: 0x01) */ +#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_WRD_Pos (0UL) /*!< QSPIC_BRK_WRD (Bit 0) */ +#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_WRD_Msk (0xffffUL) /*!< QSPIC_BRK_WRD (Bitfield-Mask: 0xffff) */ +/* ================================================== QSPIC_BURSTCMDA_REG ================================================== */ +#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Pos (30UL) /*!< QSPIC_DMY_TX_MD (Bit 30) */ +#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Msk (0xc0000000UL) /*!< QSPIC_DMY_TX_MD (Bitfield-Mask: 0x03) */ +#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Pos (28UL) /*!< QSPIC_EXT_TX_MD (Bit 28) */ +#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Msk (0x30000000UL) /*!< QSPIC_EXT_TX_MD (Bitfield-Mask: 0x03) */ +#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Pos (26UL) /*!< QSPIC_ADR_TX_MD (Bit 26) */ +#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Msk (0xc000000UL) /*!< QSPIC_ADR_TX_MD (Bitfield-Mask: 0x03) */ +#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_TX_MD_Pos (24UL) /*!< QSPIC_INST_TX_MD (Bit 24) */ +#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_TX_MD_Msk (0x3000000UL) /*!< QSPIC_INST_TX_MD (Bitfield-Mask: 0x03) */ +#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_BYTE_Pos (16UL) /*!< QSPIC_EXT_BYTE (Bit 16) */ +#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_BYTE_Msk (0xff0000UL) /*!< QSPIC_EXT_BYTE (Bitfield-Mask: 0xff) */ +#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_WB_Pos (8UL) /*!< QSPIC_INST_WB (Bit 8) */ +#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_WB_Msk (0xff00UL) /*!< QSPIC_INST_WB (Bitfield-Mask: 0xff) */ +#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_Pos (0UL) /*!< QSPIC_INST (Bit 0) */ +#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_Msk (0xffUL) /*!< QSPIC_INST (Bitfield-Mask: 0xff) */ +/* ================================================== QSPIC_BURSTCMDB_REG ================================================== */ +#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_FORCE_Pos (15UL) /*!< QSPIC_DMY_FORCE (Bit 15) */ +#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_FORCE_Msk (0x8000UL) /*!< QSPIC_DMY_FORCE (Bitfield-Mask: 0x01) */ +#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Pos (12UL) /*!< QSPIC_CS_HIGH_MIN (Bit 12) */ +#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Msk (0x7000UL) /*!< QSPIC_CS_HIGH_MIN (Bitfield-Mask: 0x07) */ +#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Pos (10UL) /*!< QSPIC_WRAP_SIZE (Bit 10) */ +#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Msk (0xc00UL) /*!< QSPIC_WRAP_SIZE (Bitfield-Mask: 0x03) */ +#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_LEN_Pos (8UL) /*!< QSPIC_WRAP_LEN (Bit 8) */ +#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_LEN_Msk (0x300UL) /*!< QSPIC_WRAP_LEN (Bitfield-Mask: 0x03) */ +#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_MD_Pos (7UL) /*!< QSPIC_WRAP_MD (Bit 7) */ +#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_MD_Msk (0x80UL) /*!< QSPIC_WRAP_MD (Bitfield-Mask: 0x01) */ +#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_INST_MD_Pos (6UL) /*!< QSPIC_INST_MD (Bit 6) */ +#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_INST_MD_Msk (0x40UL) /*!< QSPIC_INST_MD (Bitfield-Mask: 0x01) */ +#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_NUM_Pos (4UL) /*!< QSPIC_DMY_NUM (Bit 4) */ +#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_NUM_Msk (0x30UL) /*!< QSPIC_DMY_NUM (Bitfield-Mask: 0x03) */ +#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Pos (3UL) /*!< QSPIC_EXT_HF_DS (Bit 3) */ +#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Msk (0x8UL) /*!< QSPIC_EXT_HF_DS (Bitfield-Mask: 0x01) */ +#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Pos (2UL) /*!< QSPIC_EXT_BYTE_EN (Bit 2) */ +#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Msk (0x4UL) /*!< QSPIC_EXT_BYTE_EN (Bitfield-Mask: 0x01) */ +#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Pos (0UL) /*!< QSPIC_DAT_RX_MD (Bit 0) */ +#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Msk (0x3UL) /*!< QSPIC_DAT_RX_MD (Bitfield-Mask: 0x03) */ +/* ================================================== QSPIC_CHCKERASE_REG ================================================== */ +#define QSPIC_QSPIC_CHCKERASE_REG_QSPIC_CHCKERASE_Pos (0UL) /*!< QSPIC_CHCKERASE (Bit 0) */ +#define QSPIC_QSPIC_CHCKERASE_REG_QSPIC_CHCKERASE_Msk (0xffffffffUL) /*!< QSPIC_CHCKERASE (Bitfield-Mask: 0xffffffff) */ +/* =================================================== QSPIC_CTRLBUS_REG =================================================== */ +#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Pos (4UL) /*!< QSPIC_DIS_CS (Bit 4) */ +#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Msk (0x10UL) /*!< QSPIC_DIS_CS (Bitfield-Mask: 0x01) */ +#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Pos (3UL) /*!< QSPIC_EN_CS (Bit 3) */ +#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Msk (0x8UL) /*!< QSPIC_EN_CS (Bitfield-Mask: 0x01) */ +#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_QUAD_Pos (2UL) /*!< QSPIC_SET_QUAD (Bit 2) */ +#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_QUAD_Msk (0x4UL) /*!< QSPIC_SET_QUAD (Bitfield-Mask: 0x01) */ +#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_DUAL_Pos (1UL) /*!< QSPIC_SET_DUAL (Bit 1) */ +#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_DUAL_Msk (0x2UL) /*!< QSPIC_SET_DUAL (Bitfield-Mask: 0x01) */ +#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_SINGLE_Pos (0UL) /*!< QSPIC_SET_SINGLE (Bit 0) */ +#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_SINGLE_Msk (0x1UL) /*!< QSPIC_SET_SINGLE (Bitfield-Mask: 0x01) */ +/* ================================================== QSPIC_CTRLMODE_REG =================================================== */ +#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_USE_32BA_Pos (13UL) /*!< QSPIC_USE_32BA (Bit 13) */ +#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_USE_32BA_Msk (0x2000UL) /*!< QSPIC_USE_32BA (Bitfield-Mask: 0x01) */ +#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_BUF_LIM_EN_Pos (12UL) /*!< QSPIC_BUF_LIM_EN (Bit 12) */ +#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_BUF_LIM_EN_Msk (0x1000UL) /*!< QSPIC_BUF_LIM_EN (Bitfield-Mask: 0x01) */ +#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Pos (9UL) /*!< QSPIC_PCLK_MD (Bit 9) */ +#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Msk (0xe00UL) /*!< QSPIC_PCLK_MD (Bitfield-Mask: 0x07) */ +#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RPIPE_EN_Pos (8UL) /*!< QSPIC_RPIPE_EN (Bit 8) */ +#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RPIPE_EN_Msk (0x100UL) /*!< QSPIC_RPIPE_EN (Bitfield-Mask: 0x01) */ +#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RXD_NEG_Pos (7UL) /*!< QSPIC_RXD_NEG (Bit 7) */ +#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RXD_NEG_Msk (0x80UL) /*!< QSPIC_RXD_NEG (Bitfield-Mask: 0x01) */ +#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_HRDY_MD_Pos (6UL) /*!< QSPIC_HRDY_MD (Bit 6) */ +#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_HRDY_MD_Msk (0x40UL) /*!< QSPIC_HRDY_MD (Bitfield-Mask: 0x01) */ +#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_DAT_Pos (5UL) /*!< QSPIC_IO3_DAT (Bit 5) */ +#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_DAT_Msk (0x20UL) /*!< QSPIC_IO3_DAT (Bitfield-Mask: 0x01) */ +#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_DAT_Pos (4UL) /*!< QSPIC_IO2_DAT (Bit 4) */ +#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_DAT_Msk (0x10UL) /*!< QSPIC_IO2_DAT (Bitfield-Mask: 0x01) */ +#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_OEN_Pos (3UL) /*!< QSPIC_IO3_OEN (Bit 3) */ +#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_OEN_Msk (0x8UL) /*!< QSPIC_IO3_OEN (Bitfield-Mask: 0x01) */ +#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Pos (2UL) /*!< QSPIC_IO2_OEN (Bit 2) */ +#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Msk (0x4UL) /*!< QSPIC_IO2_OEN (Bitfield-Mask: 0x01) */ +#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_MD_Pos (1UL) /*!< QSPIC_CLK_MD (Bit 1) */ +#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_MD_Msk (0x2UL) /*!< QSPIC_CLK_MD (Bitfield-Mask: 0x01) */ +#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Pos (0UL) /*!< QSPIC_AUTO_MD (Bit 0) */ +#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Msk (0x1UL) /*!< QSPIC_AUTO_MD (Bitfield-Mask: 0x01) */ +/* ================================================== QSPIC_CTR_CTRL_REG =================================================== */ +#define QSPIC_QSPIC_CTR_CTRL_REG_QSPIC_CTR_EN_Pos (0UL) /*!< QSPIC_CTR_EN (Bit 0) */ +#define QSPIC_QSPIC_CTR_CTRL_REG_QSPIC_CTR_EN_Msk (0x1UL) /*!< QSPIC_CTR_EN (Bitfield-Mask: 0x01) */ +/* ================================================== QSPIC_CTR_EADDR_REG ================================================== */ +#define QSPIC_QSPIC_CTR_EADDR_REG_QSPIC_CTR_EADDR_Pos (10UL) /*!< QSPIC_CTR_EADDR (Bit 10) */ +#define QSPIC_QSPIC_CTR_EADDR_REG_QSPIC_CTR_EADDR_Msk (0xfffffc00UL) /*!< QSPIC_CTR_EADDR (Bitfield-Mask: 0x3fffff) */ +/* ================================================= QSPIC_CTR_KEY_0_3_REG ================================================= */ +#define QSPIC_QSPIC_CTR_KEY_0_3_REG_QSPIC_CTR_KEY_0_3_Pos (0UL) /*!< QSPIC_CTR_KEY_0_3 (Bit 0) */ +#define QSPIC_QSPIC_CTR_KEY_0_3_REG_QSPIC_CTR_KEY_0_3_Msk (0xffffffffUL) /*!< QSPIC_CTR_KEY_0_3 (Bitfield-Mask: 0xffffffff) */ +/* ================================================ QSPIC_CTR_KEY_12_15_REG ================================================ */ +#define QSPIC_QSPIC_CTR_KEY_12_15_REG_QSPIC_CTR_KEY_12_15_Pos (0UL) /*!< QSPIC_CTR_KEY_12_15 (Bit 0) */ +#define QSPIC_QSPIC_CTR_KEY_12_15_REG_QSPIC_CTR_KEY_12_15_Msk (0xffffffffUL) /*!< QSPIC_CTR_KEY_12_15 (Bitfield-Mask: 0xffffffff) */ +/* ================================================ QSPIC_CTR_KEY_16_19_REG ================================================ */ +#define QSPIC_QSPIC_CTR_KEY_16_19_REG_QSPIC_CTR_KEY_16_19_Pos (0UL) /*!< QSPIC_CTR_KEY_16_19 (Bit 0) */ +#define QSPIC_QSPIC_CTR_KEY_16_19_REG_QSPIC_CTR_KEY_16_19_Msk (0xffffffffUL) /*!< QSPIC_CTR_KEY_16_19 (Bitfield-Mask: 0xffffffff) */ +/* ================================================ QSPIC_CTR_KEY_20_23_REG ================================================ */ +#define QSPIC_QSPIC_CTR_KEY_20_23_REG_QSPIC_CTR_KEY_20_23_Pos (0UL) /*!< QSPIC_CTR_KEY_20_23 (Bit 0) */ +#define QSPIC_QSPIC_CTR_KEY_20_23_REG_QSPIC_CTR_KEY_20_23_Msk (0xffffffffUL) /*!< QSPIC_CTR_KEY_20_23 (Bitfield-Mask: 0xffffffff) */ +/* ================================================ QSPIC_CTR_KEY_24_27_REG ================================================ */ +#define QSPIC_QSPIC_CTR_KEY_24_27_REG_QSPIC_CTR_KEY_24_27_Pos (0UL) /*!< QSPIC_CTR_KEY_24_27 (Bit 0) */ +#define QSPIC_QSPIC_CTR_KEY_24_27_REG_QSPIC_CTR_KEY_24_27_Msk (0xffffffffUL) /*!< QSPIC_CTR_KEY_24_27 (Bitfield-Mask: 0xffffffff) */ +/* ================================================ QSPIC_CTR_KEY_28_31_REG ================================================ */ +#define QSPIC_QSPIC_CTR_KEY_28_31_REG_QSPIC_CTR_KEY_28_31_Pos (0UL) /*!< QSPIC_CTR_KEY_28_31 (Bit 0) */ +#define QSPIC_QSPIC_CTR_KEY_28_31_REG_QSPIC_CTR_KEY_28_31_Msk (0xffffffffUL) /*!< QSPIC_CTR_KEY_28_31 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= QSPIC_CTR_KEY_4_7_REG ================================================= */ +#define QSPIC_QSPIC_CTR_KEY_4_7_REG_QSPIC_CTR_KEY_4_7_Pos (0UL) /*!< QSPIC_CTR_KEY_4_7 (Bit 0) */ +#define QSPIC_QSPIC_CTR_KEY_4_7_REG_QSPIC_CTR_KEY_4_7_Msk (0xffffffffUL) /*!< QSPIC_CTR_KEY_4_7 (Bitfield-Mask: 0xffffffff) */ +/* ================================================ QSPIC_CTR_KEY_8_11_REG ================================================= */ +#define QSPIC_QSPIC_CTR_KEY_8_11_REG_QSPIC_CTR_KEY_8_11_Pos (0UL) /*!< QSPIC_CTR_KEY_8_11 (Bit 0) */ +#define QSPIC_QSPIC_CTR_KEY_8_11_REG_QSPIC_CTR_KEY_8_11_Msk (0xffffffffUL) /*!< QSPIC_CTR_KEY_8_11 (Bitfield-Mask: 0xffffffff) */ +/* ================================================ QSPIC_CTR_NONCE_0_3_REG ================================================ */ +#define QSPIC_QSPIC_CTR_NONCE_0_3_REG_QSPIC_CTR_NONCE_0_3_Pos (0UL) /*!< QSPIC_CTR_NONCE_0_3 (Bit 0) */ +#define QSPIC_QSPIC_CTR_NONCE_0_3_REG_QSPIC_CTR_NONCE_0_3_Msk (0xffffffffUL) /*!< QSPIC_CTR_NONCE_0_3 (Bitfield-Mask: 0xffffffff) */ +/* ================================================ QSPIC_CTR_NONCE_4_7_REG ================================================ */ +#define QSPIC_QSPIC_CTR_NONCE_4_7_REG_QSPIC_CTR_NONCE_4_7_Pos (0UL) /*!< QSPIC_CTR_NONCE_4_7 (Bit 0) */ +#define QSPIC_QSPIC_CTR_NONCE_4_7_REG_QSPIC_CTR_NONCE_4_7_Msk (0xffffffffUL) /*!< QSPIC_CTR_NONCE_4_7 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== QSPIC_CTR_SADDR_REG ================================================== */ +#define QSPIC_QSPIC_CTR_SADDR_REG_QSPIC_CTR_SADDR_Pos (10UL) /*!< QSPIC_CTR_SADDR (Bit 10) */ +#define QSPIC_QSPIC_CTR_SADDR_REG_QSPIC_CTR_SADDR_Msk (0xfffffc00UL) /*!< QSPIC_CTR_SADDR (Bitfield-Mask: 0x3fffff) */ +/* ================================================== QSPIC_DUMMYDATA_REG ================================================== */ +#define QSPIC_QSPIC_DUMMYDATA_REG_QSPIC_DUMMYDATA_Pos (0UL) /*!< QSPIC_DUMMYDATA (Bit 0) */ +#define QSPIC_QSPIC_DUMMYDATA_REG_QSPIC_DUMMYDATA_Msk (0xffffffffUL) /*!< QSPIC_DUMMYDATA (Bitfield-Mask: 0xffffffff) */ +/* ================================================== QSPIC_ERASECMDA_REG ================================================== */ +#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_RES_INST_Pos (24UL) /*!< QSPIC_RES_INST (Bit 24) */ +#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_RES_INST_Msk (0xff000000UL) /*!< QSPIC_RES_INST (Bitfield-Mask: 0xff) */ +#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_SUS_INST_Pos (16UL) /*!< QSPIC_SUS_INST (Bit 16) */ +#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_SUS_INST_Msk (0xff0000UL) /*!< QSPIC_SUS_INST (Bitfield-Mask: 0xff) */ +#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_WEN_INST_Pos (8UL) /*!< QSPIC_WEN_INST (Bit 8) */ +#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_WEN_INST_Msk (0xff00UL) /*!< QSPIC_WEN_INST (Bitfield-Mask: 0xff) */ +#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_ERS_INST_Pos (0UL) /*!< QSPIC_ERS_INST (Bit 0) */ +#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_ERS_INST_Msk (0xffUL) /*!< QSPIC_ERS_INST (Bitfield-Mask: 0xff) */ +/* ================================================== QSPIC_ERASECMDB_REG ================================================== */ +#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RESSUS_DLY_Pos (24UL) /*!< QSPIC_RESSUS_DLY (Bit 24) */ +#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RESSUS_DLY_Msk (0x3f000000UL) /*!< QSPIC_RESSUS_DLY (Bitfield-Mask: 0x3f) */ +#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERSRES_HLD_Pos (16UL) /*!< QSPIC_ERSRES_HLD (Bit 16) */ +#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERSRES_HLD_Msk (0xf0000UL) /*!< QSPIC_ERSRES_HLD (Bitfield-Mask: 0x0f) */ +#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Pos (10UL) /*!< QSPIC_ERS_CS_HI (Bit 10) */ +#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Msk (0x7c00UL) /*!< QSPIC_ERS_CS_HI (Bitfield-Mask: 0x1f) */ +#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_EAD_TX_MD_Pos (8UL) /*!< QSPIC_EAD_TX_MD (Bit 8) */ +#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_EAD_TX_MD_Msk (0x300UL) /*!< QSPIC_EAD_TX_MD (Bitfield-Mask: 0x03) */ +#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RES_TX_MD_Pos (6UL) /*!< QSPIC_RES_TX_MD (Bit 6) */ +#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RES_TX_MD_Msk (0xc0UL) /*!< QSPIC_RES_TX_MD (Bitfield-Mask: 0x03) */ +#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_SUS_TX_MD_Pos (4UL) /*!< QSPIC_SUS_TX_MD (Bit 4) */ +#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_SUS_TX_MD_Msk (0x30UL) /*!< QSPIC_SUS_TX_MD (Bitfield-Mask: 0x03) */ +#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_WEN_TX_MD_Pos (2UL) /*!< QSPIC_WEN_TX_MD (Bit 2) */ +#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_WEN_TX_MD_Msk (0xcUL) /*!< QSPIC_WEN_TX_MD (Bitfield-Mask: 0x03) */ +#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_TX_MD_Pos (0UL) /*!< QSPIC_ERS_TX_MD (Bit 0) */ +#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_TX_MD_Msk (0x3UL) /*!< QSPIC_ERS_TX_MD (Bitfield-Mask: 0x03) */ +/* ================================================== QSPIC_ERASECTRL_REG ================================================== */ +#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_STATE_Pos (25UL) /*!< QSPIC_ERS_STATE (Bit 25) */ +#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_STATE_Msk (0xe000000UL) /*!< QSPIC_ERS_STATE (Bitfield-Mask: 0x07) */ +#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERASE_EN_Pos (24UL) /*!< QSPIC_ERASE_EN (Bit 24) */ +#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERASE_EN_Msk (0x1000000UL) /*!< QSPIC_ERASE_EN (Bitfield-Mask: 0x01) */ +#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_ADDR_Pos (4UL) /*!< QSPIC_ERS_ADDR (Bit 4) */ +#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_ADDR_Msk (0xfffff0UL) /*!< QSPIC_ERS_ADDR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== QSPIC_GP_REG ====================================================== */ +#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_SLEW_Pos (3UL) /*!< QSPIC_PADS_SLEW (Bit 3) */ +#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_SLEW_Msk (0x18UL) /*!< QSPIC_PADS_SLEW (Bitfield-Mask: 0x03) */ +#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_DRV_Pos (1UL) /*!< QSPIC_PADS_DRV (Bit 1) */ +#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_DRV_Msk (0x6UL) /*!< QSPIC_PADS_DRV (Bitfield-Mask: 0x03) */ +/* ================================================== QSPIC_READDATA_REG =================================================== */ +#define QSPIC_QSPIC_READDATA_REG_QSPIC_READDATA_Pos (0UL) /*!< QSPIC_READDATA (Bit 0) */ +#define QSPIC_QSPIC_READDATA_REG_QSPIC_READDATA_Msk (0xffffffffUL) /*!< QSPIC_READDATA (Bitfield-Mask: 0xffffffff) */ +/* ================================================== QSPIC_RECVDATA_REG =================================================== */ +#define QSPIC_QSPIC_RECVDATA_REG_QSPIC_RECVDATA_Pos (0UL) /*!< QSPIC_RECVDATA (Bit 0) */ +#define QSPIC_QSPIC_RECVDATA_REG_QSPIC_RECVDATA_Msk (0xffffffffUL) /*!< QSPIC_RECVDATA (Bitfield-Mask: 0xffffffff) */ +/* ================================================== QSPIC_STATUSCMD_REG ================================================== */ +#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_STSDLY_SEL_Pos (22UL) /*!< QSPIC_STSDLY_SEL (Bit 22) */ +#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_STSDLY_SEL_Msk (0x400000UL) /*!< QSPIC_STSDLY_SEL (Bitfield-Mask: 0x01) */ +#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RESSTS_DLY_Pos (16UL) /*!< QSPIC_RESSTS_DLY (Bit 16) */ +#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RESSTS_DLY_Msk (0x3f0000UL) /*!< QSPIC_RESSTS_DLY (Bitfield-Mask: 0x3f) */ +#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_VAL_Pos (15UL) /*!< QSPIC_BUSY_VAL (Bit 15) */ +#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_VAL_Msk (0x8000UL) /*!< QSPIC_BUSY_VAL (Bitfield-Mask: 0x01) */ +#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_POS_Pos (12UL) /*!< QSPIC_BUSY_POS (Bit 12) */ +#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_POS_Msk (0x7000UL) /*!< QSPIC_BUSY_POS (Bitfield-Mask: 0x07) */ +#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Pos (10UL) /*!< QSPIC_RSTAT_RX_MD (Bit 10) */ +#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Msk (0xc00UL) /*!< QSPIC_RSTAT_RX_MD (Bitfield-Mask: 0x03) */ +#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Pos (8UL) /*!< QSPIC_RSTAT_TX_MD (Bit 8) */ +#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Msk (0x300UL) /*!< QSPIC_RSTAT_TX_MD (Bitfield-Mask: 0x03) */ +#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_INST_Pos (0UL) /*!< QSPIC_RSTAT_INST (Bit 0) */ +#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_INST_Msk (0xffUL) /*!< QSPIC_RSTAT_INST (Bitfield-Mask: 0xff) */ +/* =================================================== QSPIC_STATUS_REG ==================================================== */ +#define QSPIC_QSPIC_STATUS_REG_QSPIC_BUSY_Pos (0UL) /*!< QSPIC_BUSY (Bit 0) */ +#define QSPIC_QSPIC_STATUS_REG_QSPIC_BUSY_Msk (0x1UL) /*!< QSPIC_BUSY (Bitfield-Mask: 0x01) */ +/* =================================================== QSPIC_UCODE_START =================================================== */ +#define QSPIC_QSPIC_UCODE_START_QSPIC_UCODE_X_Pos (0UL) /*!< QSPIC_UCODE_X (Bit 0) */ +#define QSPIC_QSPIC_UCODE_START_QSPIC_UCODE_X_Msk (0xffffffffUL) /*!< QSPIC_UCODE_X (Bitfield-Mask: 0xffffffff) */ +/* ================================================== QSPIC_WRITEDATA_REG ================================================== */ +#define QSPIC_QSPIC_WRITEDATA_REG_QSPIC_WRITEDATA_Pos (0UL) /*!< QSPIC_WRITEDATA (Bit 0) */ +#define QSPIC_QSPIC_WRITEDATA_REG_QSPIC_WRITEDATA_Msk (0xffffffffUL) /*!< QSPIC_WRITEDATA (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ QSPIC2 ================ */ +/* =========================================================================================================================== */ + +/* ================================================= QSPIC2_AWRITECMD_REG ================================================== */ +#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_CS_HIGH_MIN_Pos (14UL) /*!< QSPIC_WR_CS_HIGH_MIN (Bit 14) */ +#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_CS_HIGH_MIN_Msk (0x7c000UL) /*!< QSPIC_WR_CS_HIGH_MIN (Bitfield-Mask: 0x1f) */ +#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_DAT_TX_MD_Pos (12UL) /*!< QSPIC_WR_DAT_TX_MD (Bit 12) */ +#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_DAT_TX_MD_Msk (0x3000UL) /*!< QSPIC_WR_DAT_TX_MD (Bitfield-Mask: 0x03) */ +#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_ADR_TX_MD_Pos (10UL) /*!< QSPIC_WR_ADR_TX_MD (Bit 10) */ +#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_ADR_TX_MD_Msk (0xc00UL) /*!< QSPIC_WR_ADR_TX_MD (Bitfield-Mask: 0x03) */ +#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_INST_TX_MD_Pos (8UL) /*!< QSPIC_WR_INST_TX_MD (Bit 8) */ +#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_INST_TX_MD_Msk (0x300UL) /*!< QSPIC_WR_INST_TX_MD (Bitfield-Mask: 0x03) */ +#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_INST_Pos (0UL) /*!< QSPIC_WR_INST (Bit 0) */ +#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_INST_Msk (0xffUL) /*!< QSPIC_WR_INST (Bitfield-Mask: 0xff) */ +/* ================================================== QSPIC2_BURSTBRK_REG ================================================== */ +#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_SEC_HF_DS_Pos (20UL) /*!< QSPIC_SEC_HF_DS (Bit 20) */ +#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_SEC_HF_DS_Msk (0x100000UL) /*!< QSPIC_SEC_HF_DS (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_BRK_TX_MD_Pos (18UL) /*!< QSPIC_BRK_TX_MD (Bit 18) */ +#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_BRK_TX_MD_Msk (0xc0000UL) /*!< QSPIC_BRK_TX_MD (Bitfield-Mask: 0x03) */ +#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_BRK_SZ_Pos (17UL) /*!< QSPIC_BRK_SZ (Bit 17) */ +#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_BRK_SZ_Msk (0x20000UL) /*!< QSPIC_BRK_SZ (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_BRK_EN_Pos (16UL) /*!< QSPIC_BRK_EN (Bit 16) */ +#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_BRK_EN_Msk (0x10000UL) /*!< QSPIC_BRK_EN (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_BRK_WRD_Pos (0UL) /*!< QSPIC_BRK_WRD (Bit 0) */ +#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_BRK_WRD_Msk (0xffffUL) /*!< QSPIC_BRK_WRD (Bitfield-Mask: 0xffff) */ +/* ================================================= QSPIC2_BURSTCMDA_REG ================================================== */ +#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Pos (30UL) /*!< QSPIC_DMY_TX_MD (Bit 30) */ +#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Msk (0xc0000000UL) /*!< QSPIC_DMY_TX_MD (Bitfield-Mask: 0x03) */ +#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Pos (28UL) /*!< QSPIC_EXT_TX_MD (Bit 28) */ +#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Msk (0x30000000UL) /*!< QSPIC_EXT_TX_MD (Bitfield-Mask: 0x03) */ +#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Pos (26UL) /*!< QSPIC_ADR_TX_MD (Bit 26) */ +#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Msk (0xc000000UL) /*!< QSPIC_ADR_TX_MD (Bitfield-Mask: 0x03) */ +#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_INST_TX_MD_Pos (24UL) /*!< QSPIC_INST_TX_MD (Bit 24) */ +#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_INST_TX_MD_Msk (0x3000000UL) /*!< QSPIC_INST_TX_MD (Bitfield-Mask: 0x03) */ +#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_EXT_BYTE_Pos (16UL) /*!< QSPIC_EXT_BYTE (Bit 16) */ +#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_EXT_BYTE_Msk (0xff0000UL) /*!< QSPIC_EXT_BYTE (Bitfield-Mask: 0xff) */ +#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_INST_WB_Pos (8UL) /*!< QSPIC_INST_WB (Bit 8) */ +#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_INST_WB_Msk (0xff00UL) /*!< QSPIC_INST_WB (Bitfield-Mask: 0xff) */ +#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_INST_Pos (0UL) /*!< QSPIC_INST (Bit 0) */ +#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_INST_Msk (0xffUL) /*!< QSPIC_INST (Bitfield-Mask: 0xff) */ +/* ================================================= QSPIC2_BURSTCMDB_REG ================================================== */ +#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_DMY_FORCE_Pos (15UL) /*!< QSPIC_DMY_FORCE (Bit 15) */ +#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_DMY_FORCE_Msk (0x8000UL) /*!< QSPIC_DMY_FORCE (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Pos (12UL) /*!< QSPIC_CS_HIGH_MIN (Bit 12) */ +#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Msk (0x7000UL) /*!< QSPIC_CS_HIGH_MIN (Bitfield-Mask: 0x07) */ +#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Pos (10UL) /*!< QSPIC_WRAP_SIZE (Bit 10) */ +#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Msk (0xc00UL) /*!< QSPIC_WRAP_SIZE (Bitfield-Mask: 0x03) */ +#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_WRAP_LEN_Pos (8UL) /*!< QSPIC_WRAP_LEN (Bit 8) */ +#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_WRAP_LEN_Msk (0x300UL) /*!< QSPIC_WRAP_LEN (Bitfield-Mask: 0x03) */ +#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_WRAP_MD_Pos (7UL) /*!< QSPIC_WRAP_MD (Bit 7) */ +#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_WRAP_MD_Msk (0x80UL) /*!< QSPIC_WRAP_MD (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_INST_MD_Pos (6UL) /*!< QSPIC_INST_MD (Bit 6) */ +#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_INST_MD_Msk (0x40UL) /*!< QSPIC_INST_MD (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_DMY_NUM_Pos (4UL) /*!< QSPIC_DMY_NUM (Bit 4) */ +#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_DMY_NUM_Msk (0x30UL) /*!< QSPIC_DMY_NUM (Bitfield-Mask: 0x03) */ +#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Pos (3UL) /*!< QSPIC_EXT_HF_DS (Bit 3) */ +#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Msk (0x8UL) /*!< QSPIC_EXT_HF_DS (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Pos (2UL) /*!< QSPIC_EXT_BYTE_EN (Bit 2) */ +#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Msk (0x4UL) /*!< QSPIC_EXT_BYTE_EN (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Pos (0UL) /*!< QSPIC_DAT_RX_MD (Bit 0) */ +#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Msk (0x3UL) /*!< QSPIC_DAT_RX_MD (Bitfield-Mask: 0x03) */ +/* ================================================= QSPIC2_CHCKERASE_REG ================================================== */ +#define QSPIC2_QSPIC2_CHCKERASE_REG_QSPIC_CHCKERASE_Pos (0UL) /*!< QSPIC_CHCKERASE (Bit 0) */ +#define QSPIC2_QSPIC2_CHCKERASE_REG_QSPIC_CHCKERASE_Msk (0xffffffffUL) /*!< QSPIC_CHCKERASE (Bitfield-Mask: 0xffffffff) */ +/* ================================================== QSPIC2_CTRLBUS_REG =================================================== */ +#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_DIS_CS_Pos (4UL) /*!< QSPIC_DIS_CS (Bit 4) */ +#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_DIS_CS_Msk (0x10UL) /*!< QSPIC_DIS_CS (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_EN_CS_Pos (3UL) /*!< QSPIC_EN_CS (Bit 3) */ +#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_EN_CS_Msk (0x8UL) /*!< QSPIC_EN_CS (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_SET_QUAD_Pos (2UL) /*!< QSPIC_SET_QUAD (Bit 2) */ +#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_SET_QUAD_Msk (0x4UL) /*!< QSPIC_SET_QUAD (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_SET_DUAL_Pos (1UL) /*!< QSPIC_SET_DUAL (Bit 1) */ +#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_SET_DUAL_Msk (0x2UL) /*!< QSPIC_SET_DUAL (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_SET_SINGLE_Pos (0UL) /*!< QSPIC_SET_SINGLE (Bit 0) */ +#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_SET_SINGLE_Msk (0x1UL) /*!< QSPIC_SET_SINGLE (Bitfield-Mask: 0x01) */ +/* ================================================== QSPIC2_CTRLMODE_REG ================================================== */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_CLK_FREE_EN_Pos (16UL) /*!< QSPIC_CLK_FREE_EN (Bit 16) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_CLK_FREE_EN_Msk (0x10000UL) /*!< QSPIC_CLK_FREE_EN (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_CS_MD_Pos (15UL) /*!< QSPIC_CS_MD (Bit 15) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_CS_MD_Msk (0x8000UL) /*!< QSPIC_CS_MD (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_SRAM_EN_Pos (14UL) /*!< QSPIC_SRAM_EN (Bit 14) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_SRAM_EN_Msk (0x4000UL) /*!< QSPIC_SRAM_EN (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_USE_32BA_Pos (13UL) /*!< QSPIC_USE_32BA (Bit 13) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_USE_32BA_Msk (0x2000UL) /*!< QSPIC_USE_32BA (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_FORCENSEQ_EN_Pos (12UL) /*!< QSPIC_FORCENSEQ_EN (Bit 12) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_FORCENSEQ_EN_Msk (0x1000UL) /*!< QSPIC_FORCENSEQ_EN (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_PCLK_MD_Pos (9UL) /*!< QSPIC_PCLK_MD (Bit 9) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_PCLK_MD_Msk (0xe00UL) /*!< QSPIC_PCLK_MD (Bitfield-Mask: 0x07) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_RPIPE_EN_Pos (8UL) /*!< QSPIC_RPIPE_EN (Bit 8) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_RPIPE_EN_Msk (0x100UL) /*!< QSPIC_RPIPE_EN (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_RXD_NEG_Pos (7UL) /*!< QSPIC_RXD_NEG (Bit 7) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_RXD_NEG_Msk (0x80UL) /*!< QSPIC_RXD_NEG (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_HRDY_MD_Pos (6UL) /*!< QSPIC_HRDY_MD (Bit 6) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_HRDY_MD_Msk (0x40UL) /*!< QSPIC_HRDY_MD (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_IO3_DAT_Pos (5UL) /*!< QSPIC_IO3_DAT (Bit 5) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_IO3_DAT_Msk (0x20UL) /*!< QSPIC_IO3_DAT (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_IO2_DAT_Pos (4UL) /*!< QSPIC_IO2_DAT (Bit 4) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_IO2_DAT_Msk (0x10UL) /*!< QSPIC_IO2_DAT (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_IO3_OEN_Pos (3UL) /*!< QSPIC_IO3_OEN (Bit 3) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_IO3_OEN_Msk (0x8UL) /*!< QSPIC_IO3_OEN (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_IO2_OEN_Pos (2UL) /*!< QSPIC_IO2_OEN (Bit 2) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_IO2_OEN_Msk (0x4UL) /*!< QSPIC_IO2_OEN (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_CLK_MD_Pos (1UL) /*!< QSPIC_CLK_MD (Bit 1) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_CLK_MD_Msk (0x2UL) /*!< QSPIC_CLK_MD (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_AUTO_MD_Pos (0UL) /*!< QSPIC_AUTO_MD (Bit 0) */ +#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_AUTO_MD_Msk (0x1UL) /*!< QSPIC_AUTO_MD (Bitfield-Mask: 0x01) */ +/* ================================================= QSPIC2_DUMMYDATA_REG ================================================== */ +#define QSPIC2_QSPIC2_DUMMYDATA_REG_QSPIC_DUMMYDATA_Pos (0UL) /*!< QSPIC_DUMMYDATA (Bit 0) */ +#define QSPIC2_QSPIC2_DUMMYDATA_REG_QSPIC_DUMMYDATA_Msk (0xffffffffUL) /*!< QSPIC_DUMMYDATA (Bitfield-Mask: 0xffffffff) */ +/* ================================================= QSPIC2_ERASECMDA_REG ================================================== */ +#define QSPIC2_QSPIC2_ERASECMDA_REG_QSPIC_RES_INST_Pos (24UL) /*!< QSPIC_RES_INST (Bit 24) */ +#define QSPIC2_QSPIC2_ERASECMDA_REG_QSPIC_RES_INST_Msk (0xff000000UL) /*!< QSPIC_RES_INST (Bitfield-Mask: 0xff) */ +#define QSPIC2_QSPIC2_ERASECMDA_REG_QSPIC_SUS_INST_Pos (16UL) /*!< QSPIC_SUS_INST (Bit 16) */ +#define QSPIC2_QSPIC2_ERASECMDA_REG_QSPIC_SUS_INST_Msk (0xff0000UL) /*!< QSPIC_SUS_INST (Bitfield-Mask: 0xff) */ +#define QSPIC2_QSPIC2_ERASECMDA_REG_QSPIC_WEN_INST_Pos (8UL) /*!< QSPIC_WEN_INST (Bit 8) */ +#define QSPIC2_QSPIC2_ERASECMDA_REG_QSPIC_WEN_INST_Msk (0xff00UL) /*!< QSPIC_WEN_INST (Bitfield-Mask: 0xff) */ +#define QSPIC2_QSPIC2_ERASECMDA_REG_QSPIC_ERS_INST_Pos (0UL) /*!< QSPIC_ERS_INST (Bit 0) */ +#define QSPIC2_QSPIC2_ERASECMDA_REG_QSPIC_ERS_INST_Msk (0xffUL) /*!< QSPIC_ERS_INST (Bitfield-Mask: 0xff) */ +/* ================================================= QSPIC2_ERASECMDB_REG ================================================== */ +#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_RESSUS_DLY_Pos (24UL) /*!< QSPIC_RESSUS_DLY (Bit 24) */ +#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_RESSUS_DLY_Msk (0x3f000000UL) /*!< QSPIC_RESSUS_DLY (Bitfield-Mask: 0x3f) */ +#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_ERSRES_HLD_Pos (16UL) /*!< QSPIC_ERSRES_HLD (Bit 16) */ +#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_ERSRES_HLD_Msk (0xf0000UL) /*!< QSPIC_ERSRES_HLD (Bitfield-Mask: 0x0f) */ +#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_ERS_CS_HI_Pos (10UL) /*!< QSPIC_ERS_CS_HI (Bit 10) */ +#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_ERS_CS_HI_Msk (0x7c00UL) /*!< QSPIC_ERS_CS_HI (Bitfield-Mask: 0x1f) */ +#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_EAD_TX_MD_Pos (8UL) /*!< QSPIC_EAD_TX_MD (Bit 8) */ +#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_EAD_TX_MD_Msk (0x300UL) /*!< QSPIC_EAD_TX_MD (Bitfield-Mask: 0x03) */ +#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_RES_TX_MD_Pos (6UL) /*!< QSPIC_RES_TX_MD (Bit 6) */ +#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_RES_TX_MD_Msk (0xc0UL) /*!< QSPIC_RES_TX_MD (Bitfield-Mask: 0x03) */ +#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_SUS_TX_MD_Pos (4UL) /*!< QSPIC_SUS_TX_MD (Bit 4) */ +#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_SUS_TX_MD_Msk (0x30UL) /*!< QSPIC_SUS_TX_MD (Bitfield-Mask: 0x03) */ +#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_WEN_TX_MD_Pos (2UL) /*!< QSPIC_WEN_TX_MD (Bit 2) */ +#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_WEN_TX_MD_Msk (0xcUL) /*!< QSPIC_WEN_TX_MD (Bitfield-Mask: 0x03) */ +#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_ERS_TX_MD_Pos (0UL) /*!< QSPIC_ERS_TX_MD (Bit 0) */ +#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_ERS_TX_MD_Msk (0x3UL) /*!< QSPIC_ERS_TX_MD (Bitfield-Mask: 0x03) */ +/* ================================================= QSPIC2_ERASECTRL_REG ================================================== */ +#define QSPIC2_QSPIC2_ERASECTRL_REG_QSPIC_ERS_STATE_Pos (25UL) /*!< QSPIC_ERS_STATE (Bit 25) */ +#define QSPIC2_QSPIC2_ERASECTRL_REG_QSPIC_ERS_STATE_Msk (0xe000000UL) /*!< QSPIC_ERS_STATE (Bitfield-Mask: 0x07) */ +#define QSPIC2_QSPIC2_ERASECTRL_REG_QSPIC_ERASE_EN_Pos (24UL) /*!< QSPIC_ERASE_EN (Bit 24) */ +#define QSPIC2_QSPIC2_ERASECTRL_REG_QSPIC_ERASE_EN_Msk (0x1000000UL) /*!< QSPIC_ERASE_EN (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_ERASECTRL_REG_QSPIC_ERS_ADDR_Pos (4UL) /*!< QSPIC_ERS_ADDR (Bit 4) */ +#define QSPIC2_QSPIC2_ERASECTRL_REG_QSPIC_ERS_ADDR_Msk (0xfffff0UL) /*!< QSPIC_ERS_ADDR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== QSPIC2_GP_REG ===================================================== */ +#define QSPIC2_QSPIC2_GP_REG_QSPIC_PADS_SLEW_Pos (3UL) /*!< QSPIC_PADS_SLEW (Bit 3) */ +#define QSPIC2_QSPIC2_GP_REG_QSPIC_PADS_SLEW_Msk (0x18UL) /*!< QSPIC_PADS_SLEW (Bitfield-Mask: 0x03) */ +#define QSPIC2_QSPIC2_GP_REG_QSPIC_PADS_DRV_Pos (1UL) /*!< QSPIC_PADS_DRV (Bit 1) */ +#define QSPIC2_QSPIC2_GP_REG_QSPIC_PADS_DRV_Msk (0x6UL) /*!< QSPIC_PADS_DRV (Bitfield-Mask: 0x03) */ +/* ================================================== QSPIC2_MEMBLEN_REG =================================================== */ +#define QSPIC2_QSPIC2_MEMBLEN_REG_QSPIC_T_CEM_CC_Pos (4UL) /*!< QSPIC_T_CEM_CC (Bit 4) */ +#define QSPIC2_QSPIC2_MEMBLEN_REG_QSPIC_T_CEM_CC_Msk (0x3ff0UL) /*!< QSPIC_T_CEM_CC (Bitfield-Mask: 0x3ff) */ +#define QSPIC2_QSPIC2_MEMBLEN_REG_QSPIC_T_CEM_EN_Pos (3UL) /*!< QSPIC_T_CEM_EN (Bit 3) */ +#define QSPIC2_QSPIC2_MEMBLEN_REG_QSPIC_T_CEM_EN_Msk (0x8UL) /*!< QSPIC_T_CEM_EN (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_MEMBLEN_REG_QSPIC_MEMBLEN_Pos (0UL) /*!< QSPIC_MEMBLEN (Bit 0) */ +#define QSPIC2_QSPIC2_MEMBLEN_REG_QSPIC_MEMBLEN_Msk (0x7UL) /*!< QSPIC_MEMBLEN (Bitfield-Mask: 0x07) */ +/* ================================================== QSPIC2_READDATA_REG ================================================== */ +#define QSPIC2_QSPIC2_READDATA_REG_QSPIC_READDATA_Pos (0UL) /*!< QSPIC_READDATA (Bit 0) */ +#define QSPIC2_QSPIC2_READDATA_REG_QSPIC_READDATA_Msk (0xffffffffUL) /*!< QSPIC_READDATA (Bitfield-Mask: 0xffffffff) */ +/* ================================================== QSPIC2_RECVDATA_REG ================================================== */ +#define QSPIC2_QSPIC2_RECVDATA_REG_QSPIC_RECVDATA_Pos (0UL) /*!< QSPIC_RECVDATA (Bit 0) */ +#define QSPIC2_QSPIC2_RECVDATA_REG_QSPIC_RECVDATA_Msk (0xffffffffUL) /*!< QSPIC_RECVDATA (Bitfield-Mask: 0xffffffff) */ +/* ================================================= QSPIC2_STATUSCMD_REG ================================================== */ +#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_STSDLY_SEL_Pos (22UL) /*!< QSPIC_STSDLY_SEL (Bit 22) */ +#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_STSDLY_SEL_Msk (0x400000UL) /*!< QSPIC_STSDLY_SEL (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_RESSTS_DLY_Pos (16UL) /*!< QSPIC_RESSTS_DLY (Bit 16) */ +#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_RESSTS_DLY_Msk (0x3f0000UL) /*!< QSPIC_RESSTS_DLY (Bitfield-Mask: 0x3f) */ +#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_BUSY_VAL_Pos (15UL) /*!< QSPIC_BUSY_VAL (Bit 15) */ +#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_BUSY_VAL_Msk (0x8000UL) /*!< QSPIC_BUSY_VAL (Bitfield-Mask: 0x01) */ +#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_BUSY_POS_Pos (12UL) /*!< QSPIC_BUSY_POS (Bit 12) */ +#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_BUSY_POS_Msk (0x7000UL) /*!< QSPIC_BUSY_POS (Bitfield-Mask: 0x07) */ +#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Pos (10UL) /*!< QSPIC_RSTAT_RX_MD (Bit 10) */ +#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Msk (0xc00UL) /*!< QSPIC_RSTAT_RX_MD (Bitfield-Mask: 0x03) */ +#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Pos (8UL) /*!< QSPIC_RSTAT_TX_MD (Bit 8) */ +#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Msk (0x300UL) /*!< QSPIC_RSTAT_TX_MD (Bitfield-Mask: 0x03) */ +#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_RSTAT_INST_Pos (0UL) /*!< QSPIC_RSTAT_INST (Bit 0) */ +#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_RSTAT_INST_Msk (0xffUL) /*!< QSPIC_RSTAT_INST (Bitfield-Mask: 0xff) */ +/* =================================================== QSPIC2_STATUS_REG =================================================== */ +#define QSPIC2_QSPIC2_STATUS_REG_QSPIC_BUSY_Pos (0UL) /*!< QSPIC_BUSY (Bit 0) */ +#define QSPIC2_QSPIC2_STATUS_REG_QSPIC_BUSY_Msk (0x1UL) /*!< QSPIC_BUSY (Bitfield-Mask: 0x01) */ +/* ================================================= QSPIC2_WRITEDATA_REG ================================================== */ +#define QSPIC2_QSPIC2_WRITEDATA_REG_QSPIC_WRITEDATA_Pos (0UL) /*!< QSPIC_WRITEDATA (Bit 0) */ +#define QSPIC2_QSPIC2_WRITEDATA_REG_QSPIC_WRITEDATA_Msk (0xffffffffUL) /*!< QSPIC_WRITEDATA (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ RFMON ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== RFMON_ADDR_REG ===================================================== */ +#define RFMON_RFMON_ADDR_REG_RFMON_ADDR_Pos (2UL) /*!< RFMON_ADDR (Bit 2) */ +#define RFMON_RFMON_ADDR_REG_RFMON_ADDR_Msk (0xfffffffcUL) /*!< RFMON_ADDR (Bitfield-Mask: 0x3fffffff) */ +/* ================================================== RFMON_CRV_ADDR_REG =================================================== */ +#define RFMON_RFMON_CRV_ADDR_REG_RFMON_CRV_ADDR_Pos (2UL) /*!< RFMON_CRV_ADDR (Bit 2) */ +#define RFMON_RFMON_CRV_ADDR_REG_RFMON_CRV_ADDR_Msk (0xfffffffcUL) /*!< RFMON_CRV_ADDR (Bitfield-Mask: 0x3fffffff) */ +/* =================================================== RFMON_CRV_LEN_REG =================================================== */ +#define RFMON_RFMON_CRV_LEN_REG_RFMON_CRV_LEN_Pos (0UL) /*!< RFMON_CRV_LEN (Bit 0) */ +#define RFMON_RFMON_CRV_LEN_REG_RFMON_CRV_LEN_Msk (0x1ffffUL) /*!< RFMON_CRV_LEN (Bitfield-Mask: 0x1ffff) */ +/* ==================================================== RFMON_CTRL_REG ===================================================== */ +#define RFMON_RFMON_CTRL_REG_RFMON_BREQ_FORCE_Pos (2UL) /*!< RFMON_BREQ_FORCE (Bit 2) */ +#define RFMON_RFMON_CTRL_REG_RFMON_BREQ_FORCE_Msk (0x4UL) /*!< RFMON_BREQ_FORCE (Bitfield-Mask: 0x01) */ +#define RFMON_RFMON_CTRL_REG_RFMON_CIRC_EN_Pos (1UL) /*!< RFMON_CIRC_EN (Bit 1) */ +#define RFMON_RFMON_CTRL_REG_RFMON_CIRC_EN_Msk (0x2UL) /*!< RFMON_CIRC_EN (Bitfield-Mask: 0x01) */ +#define RFMON_RFMON_CTRL_REG_RFMON_PACK_EN_Pos (0UL) /*!< RFMON_PACK_EN (Bit 0) */ +#define RFMON_RFMON_CTRL_REG_RFMON_PACK_EN_Msk (0x1UL) /*!< RFMON_PACK_EN (Bitfield-Mask: 0x01) */ +/* ===================================================== RFMON_LEN_REG ===================================================== */ +#define RFMON_RFMON_LEN_REG_RFMON_LEN_Pos (0UL) /*!< RFMON_LEN (Bit 0) */ +#define RFMON_RFMON_LEN_REG_RFMON_LEN_Msk (0x1ffffUL) /*!< RFMON_LEN (Bitfield-Mask: 0x1ffff) */ +/* ==================================================== RFMON_STAT_REG ===================================================== */ +#define RFMON_RFMON_STAT_REG_RFMON_OFLOW_STK_Pos (1UL) /*!< RFMON_OFLOW_STK (Bit 1) */ +#define RFMON_RFMON_STAT_REG_RFMON_OFLOW_STK_Msk (0x2UL) /*!< RFMON_OFLOW_STK (Bitfield-Mask: 0x01) */ +#define RFMON_RFMON_STAT_REG_RFMON_ACTIVE_Pos (0UL) /*!< RFMON_ACTIVE (Bit 0) */ +#define RFMON_RFMON_STAT_REG_RFMON_ACTIVE_Msk (0x1UL) /*!< RFMON_ACTIVE (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + +/* ================================================= RTC_ALARM_ENABLE_REG ================================================== */ +#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MNTH_EN_Pos (5UL) /*!< RTC_ALARM_MNTH_EN (Bit 5) */ +#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MNTH_EN_Msk (0x20UL) /*!< RTC_ALARM_MNTH_EN (Bitfield-Mask: 0x01) */ +#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_DATE_EN_Pos (4UL) /*!< RTC_ALARM_DATE_EN (Bit 4) */ +#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_DATE_EN_Msk (0x10UL) /*!< RTC_ALARM_DATE_EN (Bitfield-Mask: 0x01) */ +#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOUR_EN_Pos (3UL) /*!< RTC_ALARM_HOUR_EN (Bit 3) */ +#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOUR_EN_Msk (0x8UL) /*!< RTC_ALARM_HOUR_EN (Bitfield-Mask: 0x01) */ +#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MIN_EN_Pos (2UL) /*!< RTC_ALARM_MIN_EN (Bit 2) */ +#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MIN_EN_Msk (0x4UL) /*!< RTC_ALARM_MIN_EN (Bitfield-Mask: 0x01) */ +#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_SEC_EN_Pos (1UL) /*!< RTC_ALARM_SEC_EN (Bit 1) */ +#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_SEC_EN_Msk (0x2UL) /*!< RTC_ALARM_SEC_EN (Bitfield-Mask: 0x01) */ +#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOS_EN_Pos (0UL) /*!< RTC_ALARM_HOS_EN (Bit 0) */ +#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOS_EN_Msk (0x1UL) /*!< RTC_ALARM_HOS_EN (Bitfield-Mask: 0x01) */ +/* ================================================ RTC_CALENDAR_ALARM_REG ================================================= */ +#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_T_Pos (12UL) /*!< RTC_CAL_D_T (Bit 12) */ +#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_T_Msk (0x3000UL) /*!< RTC_CAL_D_T (Bitfield-Mask: 0x03) */ +#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_U_Pos (8UL) /*!< RTC_CAL_D_U (Bit 8) */ +#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_U_Msk (0xf00UL) /*!< RTC_CAL_D_U (Bitfield-Mask: 0x0f) */ +#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_T_Pos (7UL) /*!< RTC_CAL_M_T (Bit 7) */ +#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_T_Msk (0x80UL) /*!< RTC_CAL_M_T (Bitfield-Mask: 0x01) */ +#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_U_Pos (3UL) /*!< RTC_CAL_M_U (Bit 3) */ +#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_U_Msk (0x78UL) /*!< RTC_CAL_M_U (Bitfield-Mask: 0x0f) */ +/* =================================================== RTC_CALENDAR_REG ==================================================== */ +#define RTC_RTC_CALENDAR_REG_RTC_CAL_CH_Pos (31UL) /*!< RTC_CAL_CH (Bit 31) */ +#define RTC_RTC_CALENDAR_REG_RTC_CAL_CH_Msk (0x80000000UL) /*!< RTC_CAL_CH (Bitfield-Mask: 0x01) */ +#define RTC_RTC_CALENDAR_REG_RTC_CAL_C_T_Pos (28UL) /*!< RTC_CAL_C_T (Bit 28) */ +#define RTC_RTC_CALENDAR_REG_RTC_CAL_C_T_Msk (0x30000000UL) /*!< RTC_CAL_C_T (Bitfield-Mask: 0x03) */ +#define RTC_RTC_CALENDAR_REG_RTC_CAL_C_U_Pos (24UL) /*!< RTC_CAL_C_U (Bit 24) */ +#define RTC_RTC_CALENDAR_REG_RTC_CAL_C_U_Msk (0xf000000UL) /*!< RTC_CAL_C_U (Bitfield-Mask: 0x0f) */ +#define RTC_RTC_CALENDAR_REG_RTC_CAL_Y_T_Pos (20UL) /*!< RTC_CAL_Y_T (Bit 20) */ +#define RTC_RTC_CALENDAR_REG_RTC_CAL_Y_T_Msk (0xf00000UL) /*!< RTC_CAL_Y_T (Bitfield-Mask: 0x0f) */ +#define RTC_RTC_CALENDAR_REG_RTC_CAL_Y_U_Pos (16UL) /*!< RTC_CAL_Y_U (Bit 16) */ +#define RTC_RTC_CALENDAR_REG_RTC_CAL_Y_U_Msk (0xf0000UL) /*!< RTC_CAL_Y_U (Bitfield-Mask: 0x0f) */ +#define RTC_RTC_CALENDAR_REG_RTC_CAL_D_T_Pos (12UL) /*!< RTC_CAL_D_T (Bit 12) */ +#define RTC_RTC_CALENDAR_REG_RTC_CAL_D_T_Msk (0x3000UL) /*!< RTC_CAL_D_T (Bitfield-Mask: 0x03) */ +#define RTC_RTC_CALENDAR_REG_RTC_CAL_D_U_Pos (8UL) /*!< RTC_CAL_D_U (Bit 8) */ +#define RTC_RTC_CALENDAR_REG_RTC_CAL_D_U_Msk (0xf00UL) /*!< RTC_CAL_D_U (Bitfield-Mask: 0x0f) */ +#define RTC_RTC_CALENDAR_REG_RTC_CAL_M_T_Pos (7UL) /*!< RTC_CAL_M_T (Bit 7) */ +#define RTC_RTC_CALENDAR_REG_RTC_CAL_M_T_Msk (0x80UL) /*!< RTC_CAL_M_T (Bitfield-Mask: 0x01) */ +#define RTC_RTC_CALENDAR_REG_RTC_CAL_M_U_Pos (3UL) /*!< RTC_CAL_M_U (Bit 3) */ +#define RTC_RTC_CALENDAR_REG_RTC_CAL_M_U_Msk (0x78UL) /*!< RTC_CAL_M_U (Bitfield-Mask: 0x0f) */ +#define RTC_RTC_CALENDAR_REG_RTC_DAY_Pos (0UL) /*!< RTC_DAY (Bit 0) */ +#define RTC_RTC_CALENDAR_REG_RTC_DAY_Msk (0x7UL) /*!< RTC_DAY (Bitfield-Mask: 0x07) */ +/* ==================================================== RTC_CONTROL_REG ==================================================== */ +#define RTC_RTC_CONTROL_REG_RTC_CAL_DISABLE_Pos (1UL) /*!< RTC_CAL_DISABLE (Bit 1) */ +#define RTC_RTC_CONTROL_REG_RTC_CAL_DISABLE_Msk (0x2UL) /*!< RTC_CAL_DISABLE (Bitfield-Mask: 0x01) */ +#define RTC_RTC_CONTROL_REG_RTC_TIME_DISABLE_Pos (0UL) /*!< RTC_TIME_DISABLE (Bit 0) */ +#define RTC_RTC_CONTROL_REG_RTC_TIME_DISABLE_Msk (0x1UL) /*!< RTC_TIME_DISABLE (Bitfield-Mask: 0x01) */ +/* ================================================== RTC_EVENT_CTRL_REG =================================================== */ +#define RTC_RTC_EVENT_CTRL_REG_RTC_PDC_EVENT_EN_Pos (1UL) /*!< RTC_PDC_EVENT_EN (Bit 1) */ +#define RTC_RTC_EVENT_CTRL_REG_RTC_PDC_EVENT_EN_Msk (0x2UL) /*!< RTC_PDC_EVENT_EN (Bitfield-Mask: 0x01) */ +#define RTC_RTC_EVENT_CTRL_REG_RTC_MOTOR_EVENT_EN_Pos (0UL) /*!< RTC_MOTOR_EVENT_EN (Bit 0) */ +#define RTC_RTC_EVENT_CTRL_REG_RTC_MOTOR_EVENT_EN_Msk (0x1UL) /*!< RTC_MOTOR_EVENT_EN (Bitfield-Mask: 0x01) */ +/* ================================================== RTC_EVENT_FLAGS_REG ================================================== */ +#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_ALRM_Pos (6UL) /*!< RTC_EVENT_ALRM (Bit 6) */ +#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_ALRM_Msk (0x40UL) /*!< RTC_EVENT_ALRM (Bitfield-Mask: 0x01) */ +#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MNTH_Pos (5UL) /*!< RTC_EVENT_MNTH (Bit 5) */ +#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MNTH_Msk (0x20UL) /*!< RTC_EVENT_MNTH (Bitfield-Mask: 0x01) */ +#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_DATE_Pos (4UL) /*!< RTC_EVENT_DATE (Bit 4) */ +#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_DATE_Msk (0x10UL) /*!< RTC_EVENT_DATE (Bitfield-Mask: 0x01) */ +#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOUR_Pos (3UL) /*!< RTC_EVENT_HOUR (Bit 3) */ +#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOUR_Msk (0x8UL) /*!< RTC_EVENT_HOUR (Bitfield-Mask: 0x01) */ +#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MIN_Pos (2UL) /*!< RTC_EVENT_MIN (Bit 2) */ +#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MIN_Msk (0x4UL) /*!< RTC_EVENT_MIN (Bitfield-Mask: 0x01) */ +#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_SEC_Pos (1UL) /*!< RTC_EVENT_SEC (Bit 1) */ +#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_SEC_Msk (0x2UL) /*!< RTC_EVENT_SEC (Bitfield-Mask: 0x01) */ +#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOS_Pos (0UL) /*!< RTC_EVENT_HOS (Bit 0) */ +#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOS_Msk (0x1UL) /*!< RTC_EVENT_HOS (Bitfield-Mask: 0x01) */ +/* =================================================== RTC_HOUR_MODE_REG =================================================== */ +#define RTC_RTC_HOUR_MODE_REG_RTC_HMS_Pos (0UL) /*!< RTC_HMS (Bit 0) */ +#define RTC_RTC_HOUR_MODE_REG_RTC_HMS_Msk (0x1UL) /*!< RTC_HMS (Bitfield-Mask: 0x01) */ +/* =============================================== RTC_INTERRUPT_DISABLE_REG =============================================== */ +#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_ALRM_INT_DIS_Pos (6UL) /*!< RTC_ALRM_INT_DIS (Bit 6) */ +#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_ALRM_INT_DIS_Msk (0x40UL) /*!< RTC_ALRM_INT_DIS (Bitfield-Mask: 0x01) */ +#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MNTH_INT_DIS_Pos (5UL) /*!< RTC_MNTH_INT_DIS (Bit 5) */ +#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MNTH_INT_DIS_Msk (0x20UL) /*!< RTC_MNTH_INT_DIS (Bitfield-Mask: 0x01) */ +#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_DATE_INT_DIS_Pos (4UL) /*!< RTC_DATE_INT_DIS (Bit 4) */ +#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_DATE_INT_DIS_Msk (0x10UL) /*!< RTC_DATE_INT_DIS (Bitfield-Mask: 0x01) */ +#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOUR_INT_DIS_Pos (3UL) /*!< RTC_HOUR_INT_DIS (Bit 3) */ +#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOUR_INT_DIS_Msk (0x8UL) /*!< RTC_HOUR_INT_DIS (Bitfield-Mask: 0x01) */ +#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MIN_INT_DIS_Pos (2UL) /*!< RTC_MIN_INT_DIS (Bit 2) */ +#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MIN_INT_DIS_Msk (0x4UL) /*!< RTC_MIN_INT_DIS (Bitfield-Mask: 0x01) */ +#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_SEC_INT_DIS_Pos (1UL) /*!< RTC_SEC_INT_DIS (Bit 1) */ +#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_SEC_INT_DIS_Msk (0x2UL) /*!< RTC_SEC_INT_DIS (Bitfield-Mask: 0x01) */ +#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOS_INT_DIS_Pos (0UL) /*!< RTC_HOS_INT_DIS (Bit 0) */ +#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOS_INT_DIS_Msk (0x1UL) /*!< RTC_HOS_INT_DIS (Bitfield-Mask: 0x01) */ +/* =============================================== RTC_INTERRUPT_ENABLE_REG ================================================ */ +#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_ALRM_INT_EN_Pos (6UL) /*!< RTC_ALRM_INT_EN (Bit 6) */ +#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_ALRM_INT_EN_Msk (0x40UL) /*!< RTC_ALRM_INT_EN (Bitfield-Mask: 0x01) */ +#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MNTH_INT_EN_Pos (5UL) /*!< RTC_MNTH_INT_EN (Bit 5) */ +#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MNTH_INT_EN_Msk (0x20UL) /*!< RTC_MNTH_INT_EN (Bitfield-Mask: 0x01) */ +#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_DATE_INT_EN_Pos (4UL) /*!< RTC_DATE_INT_EN (Bit 4) */ +#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_DATE_INT_EN_Msk (0x10UL) /*!< RTC_DATE_INT_EN (Bitfield-Mask: 0x01) */ +#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOUR_INT_EN_Pos (3UL) /*!< RTC_HOUR_INT_EN (Bit 3) */ +#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOUR_INT_EN_Msk (0x8UL) /*!< RTC_HOUR_INT_EN (Bitfield-Mask: 0x01) */ +#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MIN_INT_EN_Pos (2UL) /*!< RTC_MIN_INT_EN (Bit 2) */ +#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MIN_INT_EN_Msk (0x4UL) /*!< RTC_MIN_INT_EN (Bitfield-Mask: 0x01) */ +#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_SEC_INT_EN_Pos (1UL) /*!< RTC_SEC_INT_EN (Bit 1) */ +#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_SEC_INT_EN_Msk (0x2UL) /*!< RTC_SEC_INT_EN (Bitfield-Mask: 0x01) */ +#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOS_INT_EN_Pos (0UL) /*!< RTC_HOS_INT_EN (Bit 0) */ +#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOS_INT_EN_Msk (0x1UL) /*!< RTC_HOS_INT_EN (Bitfield-Mask: 0x01) */ +/* ================================================ RTC_INTERRUPT_MASK_REG ================================================= */ +#define RTC_RTC_INTERRUPT_MASK_REG_RTC_ALRM_INT_MSK_Pos (6UL) /*!< RTC_ALRM_INT_MSK (Bit 6) */ +#define RTC_RTC_INTERRUPT_MASK_REG_RTC_ALRM_INT_MSK_Msk (0x40UL) /*!< RTC_ALRM_INT_MSK (Bitfield-Mask: 0x01) */ +#define RTC_RTC_INTERRUPT_MASK_REG_RTC_MNTH_INT_MSK_Pos (5UL) /*!< RTC_MNTH_INT_MSK (Bit 5) */ +#define RTC_RTC_INTERRUPT_MASK_REG_RTC_MNTH_INT_MSK_Msk (0x20UL) /*!< RTC_MNTH_INT_MSK (Bitfield-Mask: 0x01) */ +#define RTC_RTC_INTERRUPT_MASK_REG_RTC_DATE_INT_MSK_Pos (4UL) /*!< RTC_DATE_INT_MSK (Bit 4) */ +#define RTC_RTC_INTERRUPT_MASK_REG_RTC_DATE_INT_MSK_Msk (0x10UL) /*!< RTC_DATE_INT_MSK (Bitfield-Mask: 0x01) */ +#define RTC_RTC_INTERRUPT_MASK_REG_RTC_HOUR_INT_MSK_Pos (3UL) /*!< RTC_HOUR_INT_MSK (Bit 3) */ +#define RTC_RTC_INTERRUPT_MASK_REG_RTC_HOUR_INT_MSK_Msk (0x8UL) /*!< RTC_HOUR_INT_MSK (Bitfield-Mask: 0x01) */ +#define RTC_RTC_INTERRUPT_MASK_REG_RTC_MIN_INT_MSK_Pos (2UL) /*!< RTC_MIN_INT_MSK (Bit 2) */ +#define RTC_RTC_INTERRUPT_MASK_REG_RTC_MIN_INT_MSK_Msk (0x4UL) /*!< RTC_MIN_INT_MSK (Bitfield-Mask: 0x01) */ +#define RTC_RTC_INTERRUPT_MASK_REG_RTC_SEC_INT_MSK_Pos (1UL) /*!< RTC_SEC_INT_MSK (Bit 1) */ +#define RTC_RTC_INTERRUPT_MASK_REG_RTC_SEC_INT_MSK_Msk (0x2UL) /*!< RTC_SEC_INT_MSK (Bitfield-Mask: 0x01) */ +#define RTC_RTC_INTERRUPT_MASK_REG_RTC_HOS_INT_MSK_Pos (0UL) /*!< RTC_HOS_INT_MSK (Bit 0) */ +#define RTC_RTC_INTERRUPT_MASK_REG_RTC_HOS_INT_MSK_Msk (0x1UL) /*!< RTC_HOS_INT_MSK (Bitfield-Mask: 0x01) */ +/* =================================================== RTC_KEEP_RTC_REG ==================================================== */ +#define RTC_RTC_KEEP_RTC_REG_RTC_KEEP_Pos (0UL) /*!< RTC_KEEP (Bit 0) */ +#define RTC_RTC_KEEP_RTC_REG_RTC_KEEP_Msk (0x1UL) /*!< RTC_KEEP (Bitfield-Mask: 0x01) */ +/* ================================================ RTC_MOTOR_EVENT_CNT_REG ================================================ */ +#define RTC_RTC_MOTOR_EVENT_CNT_REG_RTC_MOTOR_EVENT_CNT_Pos (0UL) /*!< RTC_MOTOR_EVENT_CNT (Bit 0) */ +#define RTC_RTC_MOTOR_EVENT_CNT_REG_RTC_MOTOR_EVENT_CNT_Msk (0xfffUL) /*!< RTC_MOTOR_EVENT_CNT (Bitfield-Mask: 0xfff) */ +/* ============================================== RTC_MOTOR_EVENT_PERIOD_REG =============================================== */ +#define RTC_RTC_MOTOR_EVENT_PERIOD_REG_RTC_MOTOR_EVENT_PERIOD_Pos (0UL) /*!< RTC_MOTOR_EVENT_PERIOD (Bit 0) */ +#define RTC_RTC_MOTOR_EVENT_PERIOD_REG_RTC_MOTOR_EVENT_PERIOD_Msk (0xfffUL) /*!< RTC_MOTOR_EVENT_PERIOD (Bitfield-Mask: 0xfff) */ +/* ================================================ RTC_PDC_EVENT_CLEAR_REG ================================================ */ +#define RTC_RTC_PDC_EVENT_CLEAR_REG_PDC_EVENT_CLEAR_Pos (0UL) /*!< PDC_EVENT_CLEAR (Bit 0) */ +#define RTC_RTC_PDC_EVENT_CLEAR_REG_PDC_EVENT_CLEAR_Msk (0x1UL) /*!< PDC_EVENT_CLEAR (Bitfield-Mask: 0x01) */ +/* ================================================= RTC_PDC_EVENT_CNT_REG ================================================= */ +#define RTC_RTC_PDC_EVENT_CNT_REG_RTC_PDC_EVENT_CNT_Pos (0UL) /*!< RTC_PDC_EVENT_CNT (Bit 0) */ +#define RTC_RTC_PDC_EVENT_CNT_REG_RTC_PDC_EVENT_CNT_Msk (0x1fffUL) /*!< RTC_PDC_EVENT_CNT (Bitfield-Mask: 0x1fff) */ +/* =============================================== RTC_PDC_EVENT_PERIOD_REG ================================================ */ +#define RTC_RTC_PDC_EVENT_PERIOD_REG_RTC_PDC_EVENT_PERIOD_Pos (0UL) /*!< RTC_PDC_EVENT_PERIOD (Bit 0) */ +#define RTC_RTC_PDC_EVENT_PERIOD_REG_RTC_PDC_EVENT_PERIOD_Msk (0x1fffUL) /*!< RTC_PDC_EVENT_PERIOD (Bitfield-Mask: 0x1fff) */ +/* ==================================================== RTC_STATUS_REG ===================================================== */ +#define RTC_RTC_STATUS_REG_RTC_VALID_CAL_ALM_Pos (3UL) /*!< RTC_VALID_CAL_ALM (Bit 3) */ +#define RTC_RTC_STATUS_REG_RTC_VALID_CAL_ALM_Msk (0x8UL) /*!< RTC_VALID_CAL_ALM (Bitfield-Mask: 0x01) */ +#define RTC_RTC_STATUS_REG_RTC_VALID_TIME_ALM_Pos (2UL) /*!< RTC_VALID_TIME_ALM (Bit 2) */ +#define RTC_RTC_STATUS_REG_RTC_VALID_TIME_ALM_Msk (0x4UL) /*!< RTC_VALID_TIME_ALM (Bitfield-Mask: 0x01) */ +#define RTC_RTC_STATUS_REG_RTC_VALID_CAL_Pos (1UL) /*!< RTC_VALID_CAL (Bit 1) */ +#define RTC_RTC_STATUS_REG_RTC_VALID_CAL_Msk (0x2UL) /*!< RTC_VALID_CAL (Bitfield-Mask: 0x01) */ +#define RTC_RTC_STATUS_REG_RTC_VALID_TIME_Pos (0UL) /*!< RTC_VALID_TIME (Bit 0) */ +#define RTC_RTC_STATUS_REG_RTC_VALID_TIME_Msk (0x1UL) /*!< RTC_VALID_TIME (Bitfield-Mask: 0x01) */ +/* ================================================== RTC_TIME_ALARM_REG =================================================== */ +#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_PM_Pos (30UL) /*!< RTC_TIME_PM (Bit 30) */ +#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_PM_Msk (0x40000000UL) /*!< RTC_TIME_PM (Bitfield-Mask: 0x01) */ +#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_T_Pos (28UL) /*!< RTC_TIME_HR_T (Bit 28) */ +#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_T_Msk (0x30000000UL) /*!< RTC_TIME_HR_T (Bitfield-Mask: 0x03) */ +#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_U_Pos (24UL) /*!< RTC_TIME_HR_U (Bit 24) */ +#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_U_Msk (0xf000000UL) /*!< RTC_TIME_HR_U (Bitfield-Mask: 0x0f) */ +#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_T_Pos (20UL) /*!< RTC_TIME_M_T (Bit 20) */ +#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_T_Msk (0x700000UL) /*!< RTC_TIME_M_T (Bitfield-Mask: 0x07) */ +#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_U_Pos (16UL) /*!< RTC_TIME_M_U (Bit 16) */ +#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_U_Msk (0xf0000UL) /*!< RTC_TIME_M_U (Bitfield-Mask: 0x0f) */ +#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_T_Pos (12UL) /*!< RTC_TIME_S_T (Bit 12) */ +#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_T_Msk (0x7000UL) /*!< RTC_TIME_S_T (Bitfield-Mask: 0x07) */ +#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_U_Pos (8UL) /*!< RTC_TIME_S_U (Bit 8) */ +#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_U_Msk (0xf00UL) /*!< RTC_TIME_S_U (Bitfield-Mask: 0x0f) */ +#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_T_Pos (4UL) /*!< RTC_TIME_H_T (Bit 4) */ +#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_T_Msk (0xf0UL) /*!< RTC_TIME_H_T (Bitfield-Mask: 0x0f) */ +#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_U_Pos (0UL) /*!< RTC_TIME_H_U (Bit 0) */ +#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_U_Msk (0xfUL) /*!< RTC_TIME_H_U (Bitfield-Mask: 0x0f) */ +/* ===================================================== RTC_TIME_REG ====================================================== */ +#define RTC_RTC_TIME_REG_RTC_TIME_CH_Pos (31UL) /*!< RTC_TIME_CH (Bit 31) */ +#define RTC_RTC_TIME_REG_RTC_TIME_CH_Msk (0x80000000UL) /*!< RTC_TIME_CH (Bitfield-Mask: 0x01) */ +#define RTC_RTC_TIME_REG_RTC_TIME_PM_Pos (30UL) /*!< RTC_TIME_PM (Bit 30) */ +#define RTC_RTC_TIME_REG_RTC_TIME_PM_Msk (0x40000000UL) /*!< RTC_TIME_PM (Bitfield-Mask: 0x01) */ +#define RTC_RTC_TIME_REG_RTC_TIME_HR_T_Pos (28UL) /*!< RTC_TIME_HR_T (Bit 28) */ +#define RTC_RTC_TIME_REG_RTC_TIME_HR_T_Msk (0x30000000UL) /*!< RTC_TIME_HR_T (Bitfield-Mask: 0x03) */ +#define RTC_RTC_TIME_REG_RTC_TIME_HR_U_Pos (24UL) /*!< RTC_TIME_HR_U (Bit 24) */ +#define RTC_RTC_TIME_REG_RTC_TIME_HR_U_Msk (0xf000000UL) /*!< RTC_TIME_HR_U (Bitfield-Mask: 0x0f) */ +#define RTC_RTC_TIME_REG_RTC_TIME_M_T_Pos (20UL) /*!< RTC_TIME_M_T (Bit 20) */ +#define RTC_RTC_TIME_REG_RTC_TIME_M_T_Msk (0x700000UL) /*!< RTC_TIME_M_T (Bitfield-Mask: 0x07) */ +#define RTC_RTC_TIME_REG_RTC_TIME_M_U_Pos (16UL) /*!< RTC_TIME_M_U (Bit 16) */ +#define RTC_RTC_TIME_REG_RTC_TIME_M_U_Msk (0xf0000UL) /*!< RTC_TIME_M_U (Bitfield-Mask: 0x0f) */ +#define RTC_RTC_TIME_REG_RTC_TIME_S_T_Pos (12UL) /*!< RTC_TIME_S_T (Bit 12) */ +#define RTC_RTC_TIME_REG_RTC_TIME_S_T_Msk (0x7000UL) /*!< RTC_TIME_S_T (Bitfield-Mask: 0x07) */ +#define RTC_RTC_TIME_REG_RTC_TIME_S_U_Pos (8UL) /*!< RTC_TIME_S_U (Bit 8) */ +#define RTC_RTC_TIME_REG_RTC_TIME_S_U_Msk (0xf00UL) /*!< RTC_TIME_S_U (Bitfield-Mask: 0x0f) */ +#define RTC_RTC_TIME_REG_RTC_TIME_H_T_Pos (4UL) /*!< RTC_TIME_H_T (Bit 4) */ +#define RTC_RTC_TIME_REG_RTC_TIME_H_T_Msk (0xf0UL) /*!< RTC_TIME_H_T (Bitfield-Mask: 0x0f) */ +#define RTC_RTC_TIME_REG_RTC_TIME_H_U_Pos (0UL) /*!< RTC_TIME_H_U (Bit 0) */ +#define RTC_RTC_TIME_REG_RTC_TIME_H_U_Msk (0xfUL) /*!< RTC_TIME_H_U (Bitfield-Mask: 0x0f) */ + + +/* =========================================================================================================================== */ +/* ================ SDADC ================ */ +/* =========================================================================================================================== */ + +/* ================================================== SDADC_CLEAR_INT_REG ================================================== */ +#define SDADC_SDADC_CLEAR_INT_REG_SDADC_CLR_INT_Pos (0UL) /*!< SDADC_CLR_INT (Bit 0) */ +#define SDADC_SDADC_CLEAR_INT_REG_SDADC_CLR_INT_Msk (0xffffUL) /*!< SDADC_CLR_INT (Bitfield-Mask: 0xffff) */ +/* ==================================================== SDADC_CTRL_REG ===================================================== */ +#define SDADC_SDADC_CTRL_REG_SDADC_DMA_EN_Pos (17UL) /*!< SDADC_DMA_EN (Bit 17) */ +#define SDADC_SDADC_CTRL_REG_SDADC_DMA_EN_Msk (0x20000UL) /*!< SDADC_DMA_EN (Bitfield-Mask: 0x01) */ +#define SDADC_SDADC_CTRL_REG_SDADC_MINT_Pos (16UL) /*!< SDADC_MINT (Bit 16) */ +#define SDADC_SDADC_CTRL_REG_SDADC_MINT_Msk (0x10000UL) /*!< SDADC_MINT (Bitfield-Mask: 0x01) */ +#define SDADC_SDADC_CTRL_REG_SDADC_INT_Pos (15UL) /*!< SDADC_INT (Bit 15) */ +#define SDADC_SDADC_CTRL_REG_SDADC_INT_Msk (0x8000UL) /*!< SDADC_INT (Bitfield-Mask: 0x01) */ +#define SDADC_SDADC_CTRL_REG_SDADC_LDO_OK_Pos (14UL) /*!< SDADC_LDO_OK (Bit 14) */ +#define SDADC_SDADC_CTRL_REG_SDADC_LDO_OK_Msk (0x4000UL) /*!< SDADC_LDO_OK (Bitfield-Mask: 0x01) */ +#define SDADC_SDADC_CTRL_REG_SDADC_VREF_SEL_Pos (13UL) /*!< SDADC_VREF_SEL (Bit 13) */ +#define SDADC_SDADC_CTRL_REG_SDADC_VREF_SEL_Msk (0x2000UL) /*!< SDADC_VREF_SEL (Bitfield-Mask: 0x01) */ +#define SDADC_SDADC_CTRL_REG_SDADC_CONT_Pos (12UL) /*!< SDADC_CONT (Bit 12) */ +#define SDADC_SDADC_CTRL_REG_SDADC_CONT_Msk (0x1000UL) /*!< SDADC_CONT (Bitfield-Mask: 0x01) */ +#define SDADC_SDADC_CTRL_REG_SDADC_OSR_Pos (10UL) /*!< SDADC_OSR (Bit 10) */ +#define SDADC_SDADC_CTRL_REG_SDADC_OSR_Msk (0xc00UL) /*!< SDADC_OSR (Bitfield-Mask: 0x03) */ +#define SDADC_SDADC_CTRL_REG_SDADC_SE_Pos (9UL) /*!< SDADC_SE (Bit 9) */ +#define SDADC_SDADC_CTRL_REG_SDADC_SE_Msk (0x200UL) /*!< SDADC_SE (Bitfield-Mask: 0x01) */ +#define SDADC_SDADC_CTRL_REG_SDADC_INN_SEL_Pos (6UL) /*!< SDADC_INN_SEL (Bit 6) */ +#define SDADC_SDADC_CTRL_REG_SDADC_INN_SEL_Msk (0x1c0UL) /*!< SDADC_INN_SEL (Bitfield-Mask: 0x07) */ +#define SDADC_SDADC_CTRL_REG_SDADC_INP_SEL_Pos (2UL) /*!< SDADC_INP_SEL (Bit 2) */ +#define SDADC_SDADC_CTRL_REG_SDADC_INP_SEL_Msk (0x3cUL) /*!< SDADC_INP_SEL (Bitfield-Mask: 0x0f) */ +#define SDADC_SDADC_CTRL_REG_SDADC_START_Pos (1UL) /*!< SDADC_START (Bit 1) */ +#define SDADC_SDADC_CTRL_REG_SDADC_START_Msk (0x2UL) /*!< SDADC_START (Bitfield-Mask: 0x01) */ +#define SDADC_SDADC_CTRL_REG_SDADC_EN_Pos (0UL) /*!< SDADC_EN (Bit 0) */ +#define SDADC_SDADC_CTRL_REG_SDADC_EN_Msk (0x1UL) /*!< SDADC_EN (Bitfield-Mask: 0x01) */ +/* ================================================== SDADC_GAIN_CORR_REG ================================================== */ +#define SDADC_SDADC_GAIN_CORR_REG_SDADC_GAIN_CORR_Pos (0UL) /*!< SDADC_GAIN_CORR (Bit 0) */ +#define SDADC_SDADC_GAIN_CORR_REG_SDADC_GAIN_CORR_Msk (0x3ffUL) /*!< SDADC_GAIN_CORR (Bitfield-Mask: 0x3ff) */ +/* ================================================== SDADC_OFFS_CORR_REG ================================================== */ +#define SDADC_SDADC_OFFS_CORR_REG_SDADC_OFFS_CORR_Pos (0UL) /*!< SDADC_OFFS_CORR (Bit 0) */ +#define SDADC_SDADC_OFFS_CORR_REG_SDADC_OFFS_CORR_Msk (0x3ffUL) /*!< SDADC_OFFS_CORR (Bitfield-Mask: 0x3ff) */ +/* =================================================== SDADC_RESULT_REG ==================================================== */ +#define SDADC_SDADC_RESULT_REG_SDADC_VAL_Pos (0UL) /*!< SDADC_VAL (Bit 0) */ +#define SDADC_SDADC_RESULT_REG_SDADC_VAL_Msk (0xffffUL) /*!< SDADC_VAL (Bitfield-Mask: 0xffff) */ +/* ==================================================== SDADC_TEST_REG ===================================================== */ +#define SDADC_SDADC_TEST_REG_SDADC_CLK_FREQ_Pos (6UL) /*!< SDADC_CLK_FREQ (Bit 6) */ +#define SDADC_SDADC_TEST_REG_SDADC_CLK_FREQ_Msk (0xc0UL) /*!< SDADC_CLK_FREQ (Bitfield-Mask: 0x03) */ + + +/* =========================================================================================================================== */ +/* ================ SMOTOR ================ */ +/* =========================================================================================================================== */ + +/* ==================================================== CMD_TABLE_BASE ===================================================== */ +/* ===================================================== PG0_CTRL_REG ====================================================== */ +#define SMOTOR_PG0_CTRL_REG_GENEND_IRQ_EN_Pos (15UL) /*!< GENEND_IRQ_EN (Bit 15) */ +#define SMOTOR_PG0_CTRL_REG_GENEND_IRQ_EN_Msk (0x8000UL) /*!< GENEND_IRQ_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG0_CTRL_REG_GENSTART_IRQ_EN_Pos (14UL) /*!< GENSTART_IRQ_EN (Bit 14) */ +#define SMOTOR_PG0_CTRL_REG_GENSTART_IRQ_EN_Msk (0x4000UL) /*!< GENSTART_IRQ_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG0_CTRL_REG_PG_START_MODE_Pos (13UL) /*!< PG_START_MODE (Bit 13) */ +#define SMOTOR_PG0_CTRL_REG_PG_START_MODE_Msk (0x2000UL) /*!< PG_START_MODE (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG0_CTRL_REG_PG_MODE_Pos (12UL) /*!< PG_MODE (Bit 12) */ +#define SMOTOR_PG0_CTRL_REG_PG_MODE_Msk (0x1000UL) /*!< PG_MODE (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG0_CTRL_REG_SIG3_EN_Pos (11UL) /*!< SIG3_EN (Bit 11) */ +#define SMOTOR_PG0_CTRL_REG_SIG3_EN_Msk (0x800UL) /*!< SIG3_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG0_CTRL_REG_SIG2_EN_Pos (10UL) /*!< SIG2_EN (Bit 10) */ +#define SMOTOR_PG0_CTRL_REG_SIG2_EN_Msk (0x400UL) /*!< SIG2_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG0_CTRL_REG_SIG1_EN_Pos (9UL) /*!< SIG1_EN (Bit 9) */ +#define SMOTOR_PG0_CTRL_REG_SIG1_EN_Msk (0x200UL) /*!< SIG1_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG0_CTRL_REG_SIG0_EN_Pos (8UL) /*!< SIG0_EN (Bit 8) */ +#define SMOTOR_PG0_CTRL_REG_SIG0_EN_Msk (0x100UL) /*!< SIG0_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG0_CTRL_REG_OUT3_SIG_Pos (6UL) /*!< OUT3_SIG (Bit 6) */ +#define SMOTOR_PG0_CTRL_REG_OUT3_SIG_Msk (0xc0UL) /*!< OUT3_SIG (Bitfield-Mask: 0x03) */ +#define SMOTOR_PG0_CTRL_REG_OUT2_SIG_Pos (4UL) /*!< OUT2_SIG (Bit 4) */ +#define SMOTOR_PG0_CTRL_REG_OUT2_SIG_Msk (0x30UL) /*!< OUT2_SIG (Bitfield-Mask: 0x03) */ +#define SMOTOR_PG0_CTRL_REG_OUT1_SIG_Pos (2UL) /*!< OUT1_SIG (Bit 2) */ +#define SMOTOR_PG0_CTRL_REG_OUT1_SIG_Msk (0xcUL) /*!< OUT1_SIG (Bitfield-Mask: 0x03) */ +#define SMOTOR_PG0_CTRL_REG_OUT0_SIG_Pos (0UL) /*!< OUT0_SIG (Bit 0) */ +#define SMOTOR_PG0_CTRL_REG_OUT0_SIG_Msk (0x3UL) /*!< OUT0_SIG (Bitfield-Mask: 0x03) */ +/* ===================================================== PG1_CTRL_REG ====================================================== */ +#define SMOTOR_PG1_CTRL_REG_GENEND_IRQ_EN_Pos (15UL) /*!< GENEND_IRQ_EN (Bit 15) */ +#define SMOTOR_PG1_CTRL_REG_GENEND_IRQ_EN_Msk (0x8000UL) /*!< GENEND_IRQ_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG1_CTRL_REG_GENSTART_IRQ_EN_Pos (14UL) /*!< GENSTART_IRQ_EN (Bit 14) */ +#define SMOTOR_PG1_CTRL_REG_GENSTART_IRQ_EN_Msk (0x4000UL) /*!< GENSTART_IRQ_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG1_CTRL_REG_PG_START_MODE_Pos (13UL) /*!< PG_START_MODE (Bit 13) */ +#define SMOTOR_PG1_CTRL_REG_PG_START_MODE_Msk (0x2000UL) /*!< PG_START_MODE (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG1_CTRL_REG_PG_MODE_Pos (12UL) /*!< PG_MODE (Bit 12) */ +#define SMOTOR_PG1_CTRL_REG_PG_MODE_Msk (0x1000UL) /*!< PG_MODE (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG1_CTRL_REG_SIG3_EN_Pos (11UL) /*!< SIG3_EN (Bit 11) */ +#define SMOTOR_PG1_CTRL_REG_SIG3_EN_Msk (0x800UL) /*!< SIG3_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG1_CTRL_REG_SIG2_EN_Pos (10UL) /*!< SIG2_EN (Bit 10) */ +#define SMOTOR_PG1_CTRL_REG_SIG2_EN_Msk (0x400UL) /*!< SIG2_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG1_CTRL_REG_SIG1_EN_Pos (9UL) /*!< SIG1_EN (Bit 9) */ +#define SMOTOR_PG1_CTRL_REG_SIG1_EN_Msk (0x200UL) /*!< SIG1_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG1_CTRL_REG_SIG0_EN_Pos (8UL) /*!< SIG0_EN (Bit 8) */ +#define SMOTOR_PG1_CTRL_REG_SIG0_EN_Msk (0x100UL) /*!< SIG0_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG1_CTRL_REG_OUT3_SIG_Pos (6UL) /*!< OUT3_SIG (Bit 6) */ +#define SMOTOR_PG1_CTRL_REG_OUT3_SIG_Msk (0xc0UL) /*!< OUT3_SIG (Bitfield-Mask: 0x03) */ +#define SMOTOR_PG1_CTRL_REG_OUT2_SIG_Pos (4UL) /*!< OUT2_SIG (Bit 4) */ +#define SMOTOR_PG1_CTRL_REG_OUT2_SIG_Msk (0x30UL) /*!< OUT2_SIG (Bitfield-Mask: 0x03) */ +#define SMOTOR_PG1_CTRL_REG_OUT1_SIG_Pos (2UL) /*!< OUT1_SIG (Bit 2) */ +#define SMOTOR_PG1_CTRL_REG_OUT1_SIG_Msk (0xcUL) /*!< OUT1_SIG (Bitfield-Mask: 0x03) */ +#define SMOTOR_PG1_CTRL_REG_OUT0_SIG_Pos (0UL) /*!< OUT0_SIG (Bit 0) */ +#define SMOTOR_PG1_CTRL_REG_OUT0_SIG_Msk (0x3UL) /*!< OUT0_SIG (Bitfield-Mask: 0x03) */ +/* ===================================================== PG2_CTRL_REG ====================================================== */ +#define SMOTOR_PG2_CTRL_REG_GENEND_IRQ_EN_Pos (15UL) /*!< GENEND_IRQ_EN (Bit 15) */ +#define SMOTOR_PG2_CTRL_REG_GENEND_IRQ_EN_Msk (0x8000UL) /*!< GENEND_IRQ_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG2_CTRL_REG_GENSTART_IRQ_EN_Pos (14UL) /*!< GENSTART_IRQ_EN (Bit 14) */ +#define SMOTOR_PG2_CTRL_REG_GENSTART_IRQ_EN_Msk (0x4000UL) /*!< GENSTART_IRQ_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG2_CTRL_REG_PG_START_MODE_Pos (13UL) /*!< PG_START_MODE (Bit 13) */ +#define SMOTOR_PG2_CTRL_REG_PG_START_MODE_Msk (0x2000UL) /*!< PG_START_MODE (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG2_CTRL_REG_PG_MODE_Pos (12UL) /*!< PG_MODE (Bit 12) */ +#define SMOTOR_PG2_CTRL_REG_PG_MODE_Msk (0x1000UL) /*!< PG_MODE (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG2_CTRL_REG_SIG3_EN_Pos (11UL) /*!< SIG3_EN (Bit 11) */ +#define SMOTOR_PG2_CTRL_REG_SIG3_EN_Msk (0x800UL) /*!< SIG3_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG2_CTRL_REG_SIG2_EN_Pos (10UL) /*!< SIG2_EN (Bit 10) */ +#define SMOTOR_PG2_CTRL_REG_SIG2_EN_Msk (0x400UL) /*!< SIG2_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG2_CTRL_REG_SIG1_EN_Pos (9UL) /*!< SIG1_EN (Bit 9) */ +#define SMOTOR_PG2_CTRL_REG_SIG1_EN_Msk (0x200UL) /*!< SIG1_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG2_CTRL_REG_SIG0_EN_Pos (8UL) /*!< SIG0_EN (Bit 8) */ +#define SMOTOR_PG2_CTRL_REG_SIG0_EN_Msk (0x100UL) /*!< SIG0_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG2_CTRL_REG_OUT3_SIG_Pos (6UL) /*!< OUT3_SIG (Bit 6) */ +#define SMOTOR_PG2_CTRL_REG_OUT3_SIG_Msk (0xc0UL) /*!< OUT3_SIG (Bitfield-Mask: 0x03) */ +#define SMOTOR_PG2_CTRL_REG_OUT2_SIG_Pos (4UL) /*!< OUT2_SIG (Bit 4) */ +#define SMOTOR_PG2_CTRL_REG_OUT2_SIG_Msk (0x30UL) /*!< OUT2_SIG (Bitfield-Mask: 0x03) */ +#define SMOTOR_PG2_CTRL_REG_OUT1_SIG_Pos (2UL) /*!< OUT1_SIG (Bit 2) */ +#define SMOTOR_PG2_CTRL_REG_OUT1_SIG_Msk (0xcUL) /*!< OUT1_SIG (Bitfield-Mask: 0x03) */ +#define SMOTOR_PG2_CTRL_REG_OUT0_SIG_Pos (0UL) /*!< OUT0_SIG (Bit 0) */ +#define SMOTOR_PG2_CTRL_REG_OUT0_SIG_Msk (0x3UL) /*!< OUT0_SIG (Bitfield-Mask: 0x03) */ +/* ===================================================== PG3_CTRL_REG ====================================================== */ +#define SMOTOR_PG3_CTRL_REG_GENEND_IRQ_EN_Pos (15UL) /*!< GENEND_IRQ_EN (Bit 15) */ +#define SMOTOR_PG3_CTRL_REG_GENEND_IRQ_EN_Msk (0x8000UL) /*!< GENEND_IRQ_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG3_CTRL_REG_GENSTART_IRQ_EN_Pos (14UL) /*!< GENSTART_IRQ_EN (Bit 14) */ +#define SMOTOR_PG3_CTRL_REG_GENSTART_IRQ_EN_Msk (0x4000UL) /*!< GENSTART_IRQ_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG3_CTRL_REG_PG_START_MODE_Pos (13UL) /*!< PG_START_MODE (Bit 13) */ +#define SMOTOR_PG3_CTRL_REG_PG_START_MODE_Msk (0x2000UL) /*!< PG_START_MODE (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG3_CTRL_REG_PG_MODE_Pos (12UL) /*!< PG_MODE (Bit 12) */ +#define SMOTOR_PG3_CTRL_REG_PG_MODE_Msk (0x1000UL) /*!< PG_MODE (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG3_CTRL_REG_SIG3_EN_Pos (11UL) /*!< SIG3_EN (Bit 11) */ +#define SMOTOR_PG3_CTRL_REG_SIG3_EN_Msk (0x800UL) /*!< SIG3_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG3_CTRL_REG_SIG2_EN_Pos (10UL) /*!< SIG2_EN (Bit 10) */ +#define SMOTOR_PG3_CTRL_REG_SIG2_EN_Msk (0x400UL) /*!< SIG2_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG3_CTRL_REG_SIG1_EN_Pos (9UL) /*!< SIG1_EN (Bit 9) */ +#define SMOTOR_PG3_CTRL_REG_SIG1_EN_Msk (0x200UL) /*!< SIG1_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG3_CTRL_REG_SIG0_EN_Pos (8UL) /*!< SIG0_EN (Bit 8) */ +#define SMOTOR_PG3_CTRL_REG_SIG0_EN_Msk (0x100UL) /*!< SIG0_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG3_CTRL_REG_OUT3_SIG_Pos (6UL) /*!< OUT3_SIG (Bit 6) */ +#define SMOTOR_PG3_CTRL_REG_OUT3_SIG_Msk (0xc0UL) /*!< OUT3_SIG (Bitfield-Mask: 0x03) */ +#define SMOTOR_PG3_CTRL_REG_OUT2_SIG_Pos (4UL) /*!< OUT2_SIG (Bit 4) */ +#define SMOTOR_PG3_CTRL_REG_OUT2_SIG_Msk (0x30UL) /*!< OUT2_SIG (Bitfield-Mask: 0x03) */ +#define SMOTOR_PG3_CTRL_REG_OUT1_SIG_Pos (2UL) /*!< OUT1_SIG (Bit 2) */ +#define SMOTOR_PG3_CTRL_REG_OUT1_SIG_Msk (0xcUL) /*!< OUT1_SIG (Bitfield-Mask: 0x03) */ +#define SMOTOR_PG3_CTRL_REG_OUT0_SIG_Pos (0UL) /*!< OUT0_SIG (Bit 0) */ +#define SMOTOR_PG3_CTRL_REG_OUT0_SIG_Msk (0x3UL) /*!< OUT0_SIG (Bitfield-Mask: 0x03) */ +/* ===================================================== PG4_CTRL_REG ====================================================== */ +#define SMOTOR_PG4_CTRL_REG_GENEND_IRQ_EN_Pos (15UL) /*!< GENEND_IRQ_EN (Bit 15) */ +#define SMOTOR_PG4_CTRL_REG_GENEND_IRQ_EN_Msk (0x8000UL) /*!< GENEND_IRQ_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG4_CTRL_REG_GENSTART_IRQ_EN_Pos (14UL) /*!< GENSTART_IRQ_EN (Bit 14) */ +#define SMOTOR_PG4_CTRL_REG_GENSTART_IRQ_EN_Msk (0x4000UL) /*!< GENSTART_IRQ_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG4_CTRL_REG_PG_START_MODE_Pos (13UL) /*!< PG_START_MODE (Bit 13) */ +#define SMOTOR_PG4_CTRL_REG_PG_START_MODE_Msk (0x2000UL) /*!< PG_START_MODE (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG4_CTRL_REG_PG_MODE_Pos (12UL) /*!< PG_MODE (Bit 12) */ +#define SMOTOR_PG4_CTRL_REG_PG_MODE_Msk (0x1000UL) /*!< PG_MODE (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG4_CTRL_REG_SIG3_EN_Pos (11UL) /*!< SIG3_EN (Bit 11) */ +#define SMOTOR_PG4_CTRL_REG_SIG3_EN_Msk (0x800UL) /*!< SIG3_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG4_CTRL_REG_SIG2_EN_Pos (10UL) /*!< SIG2_EN (Bit 10) */ +#define SMOTOR_PG4_CTRL_REG_SIG2_EN_Msk (0x400UL) /*!< SIG2_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG4_CTRL_REG_SIG1_EN_Pos (9UL) /*!< SIG1_EN (Bit 9) */ +#define SMOTOR_PG4_CTRL_REG_SIG1_EN_Msk (0x200UL) /*!< SIG1_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG4_CTRL_REG_SIG0_EN_Pos (8UL) /*!< SIG0_EN (Bit 8) */ +#define SMOTOR_PG4_CTRL_REG_SIG0_EN_Msk (0x100UL) /*!< SIG0_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_PG4_CTRL_REG_OUT3_SIG_Pos (6UL) /*!< OUT3_SIG (Bit 6) */ +#define SMOTOR_PG4_CTRL_REG_OUT3_SIG_Msk (0xc0UL) /*!< OUT3_SIG (Bitfield-Mask: 0x03) */ +#define SMOTOR_PG4_CTRL_REG_OUT2_SIG_Pos (4UL) /*!< OUT2_SIG (Bit 4) */ +#define SMOTOR_PG4_CTRL_REG_OUT2_SIG_Msk (0x30UL) /*!< OUT2_SIG (Bitfield-Mask: 0x03) */ +#define SMOTOR_PG4_CTRL_REG_OUT1_SIG_Pos (2UL) /*!< OUT1_SIG (Bit 2) */ +#define SMOTOR_PG4_CTRL_REG_OUT1_SIG_Msk (0xcUL) /*!< OUT1_SIG (Bitfield-Mask: 0x03) */ +#define SMOTOR_PG4_CTRL_REG_OUT0_SIG_Pos (0UL) /*!< OUT0_SIG (Bit 0) */ +#define SMOTOR_PG4_CTRL_REG_OUT0_SIG_Msk (0x3UL) /*!< OUT0_SIG (Bitfield-Mask: 0x03) */ +/* ================================================== SMOTOR_CMD_FIFO_REG ================================================== */ +#define SMOTOR_SMOTOR_CMD_FIFO_REG_SMOTOR_CMD_FIFO_Pos (0UL) /*!< SMOTOR_CMD_FIFO (Bit 0) */ +#define SMOTOR_SMOTOR_CMD_FIFO_REG_SMOTOR_CMD_FIFO_Msk (0xffffUL) /*!< SMOTOR_CMD_FIFO (Bitfield-Mask: 0xffff) */ +/* ================================================ SMOTOR_CMD_READ_PTR_REG ================================================ */ +#define SMOTOR_SMOTOR_CMD_READ_PTR_REG_SMOTOR_CMD_READ_PTR_Pos (0UL) /*!< SMOTOR_CMD_READ_PTR (Bit 0) */ +#define SMOTOR_SMOTOR_CMD_READ_PTR_REG_SMOTOR_CMD_READ_PTR_Msk (0x3fUL) /*!< SMOTOR_CMD_READ_PTR (Bitfield-Mask: 0x3f) */ +/* =============================================== SMOTOR_CMD_WRITE_PTR_REG ================================================ */ +#define SMOTOR_SMOTOR_CMD_WRITE_PTR_REG_SMOTOR_CMD_WRITE_PTR_Pos (0UL) /*!< SMOTOR_CMD_WRITE_PTR (Bit 0) */ +#define SMOTOR_SMOTOR_CMD_WRITE_PTR_REG_SMOTOR_CMD_WRITE_PTR_Msk (0x3fUL) /*!< SMOTOR_CMD_WRITE_PTR (Bitfield-Mask: 0x3f) */ +/* ==================================================== SMOTOR_CTRL_REG ==================================================== */ +#define SMOTOR_SMOTOR_CTRL_REG_TRIG_RTC_EVENT_EN_Pos (28UL) /*!< TRIG_RTC_EVENT_EN (Bit 28) */ +#define SMOTOR_SMOTOR_CTRL_REG_TRIG_RTC_EVENT_EN_Msk (0x10000000UL) /*!< TRIG_RTC_EVENT_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_SMOTOR_CTRL_REG_MC_LP_CLK_TRIG_EN_Pos (27UL) /*!< MC_LP_CLK_TRIG_EN (Bit 27) */ +#define SMOTOR_SMOTOR_CTRL_REG_MC_LP_CLK_TRIG_EN_Msk (0x8000000UL) /*!< MC_LP_CLK_TRIG_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_THRESHOLD_IRQ_EN_Pos (26UL) /*!< SMOTOR_THRESHOLD_IRQ_EN (Bit 26) */ +#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_THRESHOLD_IRQ_EN_Msk (0x4000000UL) /*!< SMOTOR_THRESHOLD_IRQ_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_THRESHOLD_Pos (21UL) /*!< SMOTOR_THRESHOLD (Bit 21) */ +#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_THRESHOLD_Msk (0x3e00000UL) /*!< SMOTOR_THRESHOLD (Bitfield-Mask: 0x1f) */ +#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_FIFO_UNR_IRQ_EN_Pos (20UL) /*!< SMOTOR_FIFO_UNR_IRQ_EN (Bit 20) */ +#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_FIFO_UNR_IRQ_EN_Msk (0x100000UL) /*!< SMOTOR_FIFO_UNR_IRQ_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_FIFO_OVF_IRQ_EN_Pos (19UL) /*!< SMOTOR_FIFO_OVF_IRQ_EN (Bit 19) */ +#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_FIFO_OVF_IRQ_EN_Msk (0x80000UL) /*!< SMOTOR_FIFO_OVF_IRQ_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_GENEND_IRQ_EN_Pos (18UL) /*!< SMOTOR_GENEND_IRQ_EN (Bit 18) */ +#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_GENEND_IRQ_EN_Msk (0x40000UL) /*!< SMOTOR_GENEND_IRQ_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_GENSTART_IRQ_EN_Pos (17UL) /*!< SMOTOR_GENSTART_IRQ_EN (Bit 17) */ +#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_GENSTART_IRQ_EN_Msk (0x20000UL) /*!< SMOTOR_GENSTART_IRQ_EN (Bitfield-Mask: 0x01) */ +#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_MOI_Pos (7UL) /*!< SMOTOR_MOI (Bit 7) */ +#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_MOI_Msk (0x1ff80UL) /*!< SMOTOR_MOI (Bitfield-Mask: 0x3ff) */ +#define SMOTOR_SMOTOR_CTRL_REG_CYCLIC_SIZE_Pos (1UL) /*!< CYCLIC_SIZE (Bit 1) */ +#define SMOTOR_SMOTOR_CTRL_REG_CYCLIC_SIZE_Msk (0x7eUL) /*!< CYCLIC_SIZE (Bitfield-Mask: 0x3f) */ +#define SMOTOR_SMOTOR_CTRL_REG_CYCLIC_MODE_Pos (0UL) /*!< CYCLIC_MODE (Bit 0) */ +#define SMOTOR_SMOTOR_CTRL_REG_CYCLIC_MODE_Msk (0x1UL) /*!< CYCLIC_MODE (Bitfield-Mask: 0x01) */ +/* ================================================= SMOTOR_IRQ_CLEAR_REG ================================================== */ +#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_THRESHOLD_IRQ_CLEAR_Pos (4UL) /*!< THRESHOLD_IRQ_CLEAR (Bit 4) */ +#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_THRESHOLD_IRQ_CLEAR_Msk (0x10UL) /*!< THRESHOLD_IRQ_CLEAR (Bitfield-Mask: 0x01) */ +#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_FIFO_UNR_IRQ_CLEAR_Pos (3UL) /*!< FIFO_UNR_IRQ_CLEAR (Bit 3) */ +#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_FIFO_UNR_IRQ_CLEAR_Msk (0x8UL) /*!< FIFO_UNR_IRQ_CLEAR (Bitfield-Mask: 0x01) */ +#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_FIFO_OVF_IRQ_CLEAR_Pos (2UL) /*!< FIFO_OVF_IRQ_CLEAR (Bit 2) */ +#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_FIFO_OVF_IRQ_CLEAR_Msk (0x4UL) /*!< FIFO_OVF_IRQ_CLEAR (Bitfield-Mask: 0x01) */ +#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_GENEND_IRQ_CLEAR_Pos (1UL) /*!< GENEND_IRQ_CLEAR (Bit 1) */ +#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_GENEND_IRQ_CLEAR_Msk (0x2UL) /*!< GENEND_IRQ_CLEAR (Bitfield-Mask: 0x01) */ +#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_GENSTART_IRQ_CLEAR_Pos (0UL) /*!< GENSTART_IRQ_CLEAR (Bit 0) */ +#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_GENSTART_IRQ_CLEAR_Msk (0x1UL) /*!< GENSTART_IRQ_CLEAR (Bitfield-Mask: 0x01) */ +/* =================================================== SMOTOR_STATUS_REG =================================================== */ +#define SMOTOR_SMOTOR_STATUS_REG_PG4_BUSY_Pos (9UL) /*!< PG4_BUSY (Bit 9) */ +#define SMOTOR_SMOTOR_STATUS_REG_PG4_BUSY_Msk (0x200UL) /*!< PG4_BUSY (Bitfield-Mask: 0x01) */ +#define SMOTOR_SMOTOR_STATUS_REG_PG3_BUSY_Pos (8UL) /*!< PG3_BUSY (Bit 8) */ +#define SMOTOR_SMOTOR_STATUS_REG_PG3_BUSY_Msk (0x100UL) /*!< PG3_BUSY (Bitfield-Mask: 0x01) */ +#define SMOTOR_SMOTOR_STATUS_REG_PG2_BUSY_Pos (7UL) /*!< PG2_BUSY (Bit 7) */ +#define SMOTOR_SMOTOR_STATUS_REG_PG2_BUSY_Msk (0x80UL) /*!< PG2_BUSY (Bitfield-Mask: 0x01) */ +#define SMOTOR_SMOTOR_STATUS_REG_PG1_BUSY_Pos (6UL) /*!< PG1_BUSY (Bit 6) */ +#define SMOTOR_SMOTOR_STATUS_REG_PG1_BUSY_Msk (0x40UL) /*!< PG1_BUSY (Bitfield-Mask: 0x01) */ +#define SMOTOR_SMOTOR_STATUS_REG_PG0_BUSY_Pos (5UL) /*!< PG0_BUSY (Bit 5) */ +#define SMOTOR_SMOTOR_STATUS_REG_PG0_BUSY_Msk (0x20UL) /*!< PG0_BUSY (Bitfield-Mask: 0x01) */ +#define SMOTOR_SMOTOR_STATUS_REG_THRESHOLD_IRQ_STATUS_Pos (4UL) /*!< THRESHOLD_IRQ_STATUS (Bit 4) */ +#define SMOTOR_SMOTOR_STATUS_REG_THRESHOLD_IRQ_STATUS_Msk (0x10UL) /*!< THRESHOLD_IRQ_STATUS (Bitfield-Mask: 0x01) */ +#define SMOTOR_SMOTOR_STATUS_REG_FIFO_UNR_IRQ_STATUS_Pos (3UL) /*!< FIFO_UNR_IRQ_STATUS (Bit 3) */ +#define SMOTOR_SMOTOR_STATUS_REG_FIFO_UNR_IRQ_STATUS_Msk (0x8UL) /*!< FIFO_UNR_IRQ_STATUS (Bitfield-Mask: 0x01) */ +#define SMOTOR_SMOTOR_STATUS_REG_FIFO_OVF_IRQ_STATUS_Pos (2UL) /*!< FIFO_OVF_IRQ_STATUS (Bit 2) */ +#define SMOTOR_SMOTOR_STATUS_REG_FIFO_OVF_IRQ_STATUS_Msk (0x4UL) /*!< FIFO_OVF_IRQ_STATUS (Bitfield-Mask: 0x01) */ +#define SMOTOR_SMOTOR_STATUS_REG_GENEND_IRQ_STATUS_Pos (1UL) /*!< GENEND_IRQ_STATUS (Bit 1) */ +#define SMOTOR_SMOTOR_STATUS_REG_GENEND_IRQ_STATUS_Msk (0x2UL) /*!< GENEND_IRQ_STATUS (Bitfield-Mask: 0x01) */ +#define SMOTOR_SMOTOR_STATUS_REG_GENSTART_IRQ_STATUS_Pos (0UL) /*!< GENSTART_IRQ_STATUS (Bit 0) */ +#define SMOTOR_SMOTOR_STATUS_REG_GENSTART_IRQ_STATUS_Msk (0x1UL) /*!< GENSTART_IRQ_STATUS (Bitfield-Mask: 0x01) */ +/* ================================================== SMOTOR_TRIGGER_REG =================================================== */ +#define SMOTOR_SMOTOR_TRIGGER_REG_PG4_START_Pos (5UL) /*!< PG4_START (Bit 5) */ +#define SMOTOR_SMOTOR_TRIGGER_REG_PG4_START_Msk (0x20UL) /*!< PG4_START (Bitfield-Mask: 0x01) */ +#define SMOTOR_SMOTOR_TRIGGER_REG_PG3_START_Pos (4UL) /*!< PG3_START (Bit 4) */ +#define SMOTOR_SMOTOR_TRIGGER_REG_PG3_START_Msk (0x10UL) /*!< PG3_START (Bitfield-Mask: 0x01) */ +#define SMOTOR_SMOTOR_TRIGGER_REG_PG2_START_Pos (3UL) /*!< PG2_START (Bit 3) */ +#define SMOTOR_SMOTOR_TRIGGER_REG_PG2_START_Msk (0x8UL) /*!< PG2_START (Bitfield-Mask: 0x01) */ +#define SMOTOR_SMOTOR_TRIGGER_REG_PG1_START_Pos (2UL) /*!< PG1_START (Bit 2) */ +#define SMOTOR_SMOTOR_TRIGGER_REG_PG1_START_Msk (0x4UL) /*!< PG1_START (Bitfield-Mask: 0x01) */ +#define SMOTOR_SMOTOR_TRIGGER_REG_PG0_START_Pos (1UL) /*!< PG0_START (Bit 1) */ +#define SMOTOR_SMOTOR_TRIGGER_REG_PG0_START_Msk (0x2UL) /*!< PG0_START (Bitfield-Mask: 0x01) */ +#define SMOTOR_SMOTOR_TRIGGER_REG_POP_CMD_Pos (0UL) /*!< POP_CMD (Bit 0) */ +#define SMOTOR_SMOTOR_TRIGGER_REG_POP_CMD_Msk (0x1UL) /*!< POP_CMD (Bitfield-Mask: 0x01) */ +/* ==================================================== WAVETABLE_BASE ===================================================== */ + + +/* =========================================================================================================================== */ +/* ================ SNC ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== SNC_CTRL_REG ====================================================== */ +#define SNC_SNC_CTRL_REG_SNC_IRQ_ACK_Pos (8UL) /*!< SNC_IRQ_ACK (Bit 8) */ +#define SNC_SNC_CTRL_REG_SNC_IRQ_ACK_Msk (0x100UL) /*!< SNC_IRQ_ACK (Bitfield-Mask: 0x01) */ +#define SNC_SNC_CTRL_REG_SNC_IRQ_CONFIG_Pos (6UL) /*!< SNC_IRQ_CONFIG (Bit 6) */ +#define SNC_SNC_CTRL_REG_SNC_IRQ_CONFIG_Msk (0xc0UL) /*!< SNC_IRQ_CONFIG (Bitfield-Mask: 0x03) */ +#define SNC_SNC_CTRL_REG_SNC_IRQ_EN_Pos (5UL) /*!< SNC_IRQ_EN (Bit 5) */ +#define SNC_SNC_CTRL_REG_SNC_IRQ_EN_Msk (0x20UL) /*!< SNC_IRQ_EN (Bitfield-Mask: 0x01) */ +#define SNC_SNC_CTRL_REG_SNC_BRANCH_LOOP_INIT_Pos (4UL) /*!< SNC_BRANCH_LOOP_INIT (Bit 4) */ +#define SNC_SNC_CTRL_REG_SNC_BRANCH_LOOP_INIT_Msk (0x10UL) /*!< SNC_BRANCH_LOOP_INIT (Bitfield-Mask: 0x01) */ +#define SNC_SNC_CTRL_REG_SNC_RESET_Pos (3UL) /*!< SNC_RESET (Bit 3) */ +#define SNC_SNC_CTRL_REG_SNC_RESET_Msk (0x8UL) /*!< SNC_RESET (Bitfield-Mask: 0x01) */ +#define SNC_SNC_CTRL_REG_BUS_ERROR_DETECT_EN_Pos (2UL) /*!< BUS_ERROR_DETECT_EN (Bit 2) */ +#define SNC_SNC_CTRL_REG_BUS_ERROR_DETECT_EN_Msk (0x4UL) /*!< BUS_ERROR_DETECT_EN (Bitfield-Mask: 0x01) */ +#define SNC_SNC_CTRL_REG_SNC_SW_CTRL_Pos (1UL) /*!< SNC_SW_CTRL (Bit 1) */ +#define SNC_SNC_CTRL_REG_SNC_SW_CTRL_Msk (0x2UL) /*!< SNC_SW_CTRL (Bitfield-Mask: 0x01) */ +#define SNC_SNC_CTRL_REG_SNC_EN_Pos (0UL) /*!< SNC_EN (Bit 0) */ +#define SNC_SNC_CTRL_REG_SNC_EN_Msk (0x1UL) /*!< SNC_EN (Bitfield-Mask: 0x01) */ +/* =================================================== SNC_LP_TIMER_REG ==================================================== */ +#define SNC_SNC_LP_TIMER_REG_LP_TIMER_Pos (0UL) /*!< LP_TIMER (Bit 0) */ +#define SNC_SNC_LP_TIMER_REG_LP_TIMER_Msk (0xffUL) /*!< LP_TIMER (Bitfield-Mask: 0xff) */ +/* ====================================================== SNC_PC_REG ======================================================= */ +#define SNC_SNC_PC_REG_PC_REG_Pos (2UL) /*!< PC_REG (Bit 2) */ +#define SNC_SNC_PC_REG_PC_REG_Msk (0x7fffcUL) /*!< PC_REG (Bitfield-Mask: 0x1ffff) */ +/* ====================================================== SNC_R1_REG ======================================================= */ +#define SNC_SNC_R1_REG_R1_REG_Pos (0UL) /*!< R1_REG (Bit 0) */ +#define SNC_SNC_R1_REG_R1_REG_Msk (0xffffffffUL) /*!< R1_REG (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SNC_R2_REG ======================================================= */ +#define SNC_SNC_R2_REG_R2_REG_Pos (0UL) /*!< R2_REG (Bit 0) */ +#define SNC_SNC_R2_REG_R2_REG_Msk (0xffffffffUL) /*!< R2_REG (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== SNC_STATUS_REG ===================================================== */ +#define SNC_SNC_STATUS_REG_SNC_PC_LOADED_Pos (6UL) /*!< SNC_PC_LOADED (Bit 6) */ +#define SNC_SNC_STATUS_REG_SNC_PC_LOADED_Msk (0x40UL) /*!< SNC_PC_LOADED (Bitfield-Mask: 0x01) */ +#define SNC_SNC_STATUS_REG_SNC_IS_STOPPED_Pos (5UL) /*!< SNC_IS_STOPPED (Bit 5) */ +#define SNC_SNC_STATUS_REG_SNC_IS_STOPPED_Msk (0x20UL) /*!< SNC_IS_STOPPED (Bitfield-Mask: 0x01) */ +#define SNC_SNC_STATUS_REG_HARD_FAULT_STATUS_Pos (4UL) /*!< HARD_FAULT_STATUS (Bit 4) */ +#define SNC_SNC_STATUS_REG_HARD_FAULT_STATUS_Msk (0x10UL) /*!< HARD_FAULT_STATUS (Bitfield-Mask: 0x01) */ +#define SNC_SNC_STATUS_REG_BUS_ERROR_STATUS_Pos (3UL) /*!< BUS_ERROR_STATUS (Bit 3) */ +#define SNC_SNC_STATUS_REG_BUS_ERROR_STATUS_Msk (0x8UL) /*!< BUS_ERROR_STATUS (Bitfield-Mask: 0x01) */ +#define SNC_SNC_STATUS_REG_SNC_DONE_STATUS_Pos (2UL) /*!< SNC_DONE_STATUS (Bit 2) */ +#define SNC_SNC_STATUS_REG_SNC_DONE_STATUS_Msk (0x4UL) /*!< SNC_DONE_STATUS (Bitfield-Mask: 0x01) */ +#define SNC_SNC_STATUS_REG_GR_FLAG_Pos (1UL) /*!< GR_FLAG (Bit 1) */ +#define SNC_SNC_STATUS_REG_GR_FLAG_Msk (0x2UL) /*!< GR_FLAG (Bitfield-Mask: 0x01) */ +#define SNC_SNC_STATUS_REG_EQ_FLAG_Pos (0UL) /*!< EQ_FLAG (Bit 0) */ +#define SNC_SNC_STATUS_REG_EQ_FLAG_Msk (0x1UL) /*!< EQ_FLAG (Bitfield-Mask: 0x01) */ +/* ===================================================== SNC_TMP1_REG ====================================================== */ +#define SNC_SNC_TMP1_REG_TMP1_REG_Pos (0UL) /*!< TMP1_REG (Bit 0) */ +#define SNC_SNC_TMP1_REG_TMP1_REG_Msk (0xffffffffUL) /*!< TMP1_REG (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SNC_TMP2_REG ====================================================== */ +#define SNC_SNC_TMP2_REG_TMP2_REG_Pos (0UL) /*!< TMP2_REG (Bit 0) */ +#define SNC_SNC_TMP2_REG_TMP2_REG_Msk (0xffffffffUL) /*!< TMP2_REG (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ SPI ================ */ +/* =========================================================================================================================== */ + +/* =================================================== SPI_CLEAR_INT_REG =================================================== */ +#define SPI_SPI_CLEAR_INT_REG_SPI_CLEAR_INT_Pos (0UL) /*!< SPI_CLEAR_INT (Bit 0) */ +#define SPI_SPI_CLEAR_INT_REG_SPI_CLEAR_INT_Msk (0xffffffffUL) /*!< SPI_CLEAR_INT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SPI_CTRL_REG ====================================================== */ +#define SPI_SPI_CTRL_REG_SPI_TX_FIFO_NOTFULL_MASK_Pos (25UL) /*!< SPI_TX_FIFO_NOTFULL_MASK (Bit 25) */ +#define SPI_SPI_CTRL_REG_SPI_TX_FIFO_NOTFULL_MASK_Msk (0x2000000UL) /*!< SPI_TX_FIFO_NOTFULL_MASK (Bitfield-Mask: 0x01) */ +#define SPI_SPI_CTRL_REG_SPI_DMA_TXREQ_MODE_Pos (24UL) /*!< SPI_DMA_TXREQ_MODE (Bit 24) */ +#define SPI_SPI_CTRL_REG_SPI_DMA_TXREQ_MODE_Msk (0x1000000UL) /*!< SPI_DMA_TXREQ_MODE (Bitfield-Mask: 0x01) */ +#define SPI_SPI_CTRL_REG_SPI_TX_FIFO_EMPTY_Pos (23UL) /*!< SPI_TX_FIFO_EMPTY (Bit 23) */ +#define SPI_SPI_CTRL_REG_SPI_TX_FIFO_EMPTY_Msk (0x800000UL) /*!< SPI_TX_FIFO_EMPTY (Bitfield-Mask: 0x01) */ +#define SPI_SPI_CTRL_REG_SPI_RX_FIFO_FULL_Pos (22UL) /*!< SPI_RX_FIFO_FULL (Bit 22) */ +#define SPI_SPI_CTRL_REG_SPI_RX_FIFO_FULL_Msk (0x400000UL) /*!< SPI_RX_FIFO_FULL (Bitfield-Mask: 0x01) */ +#define SPI_SPI_CTRL_REG_SPI_RX_FIFO_EMPTY_Pos (21UL) /*!< SPI_RX_FIFO_EMPTY (Bit 21) */ +#define SPI_SPI_CTRL_REG_SPI_RX_FIFO_EMPTY_Msk (0x200000UL) /*!< SPI_RX_FIFO_EMPTY (Bitfield-Mask: 0x01) */ +#define SPI_SPI_CTRL_REG_SPI_9BIT_VAL_Pos (20UL) /*!< SPI_9BIT_VAL (Bit 20) */ +#define SPI_SPI_CTRL_REG_SPI_9BIT_VAL_Msk (0x100000UL) /*!< SPI_9BIT_VAL (Bitfield-Mask: 0x01) */ +#define SPI_SPI_CTRL_REG_SPI_BUSY_Pos (19UL) /*!< SPI_BUSY (Bit 19) */ +#define SPI_SPI_CTRL_REG_SPI_BUSY_Msk (0x80000UL) /*!< SPI_BUSY (Bitfield-Mask: 0x01) */ +#define SPI_SPI_CTRL_REG_SPI_PRIORITY_Pos (18UL) /*!< SPI_PRIORITY (Bit 18) */ +#define SPI_SPI_CTRL_REG_SPI_PRIORITY_Msk (0x40000UL) /*!< SPI_PRIORITY (Bitfield-Mask: 0x01) */ +#define SPI_SPI_CTRL_REG_SPI_FIFO_MODE_Pos (16UL) /*!< SPI_FIFO_MODE (Bit 16) */ +#define SPI_SPI_CTRL_REG_SPI_FIFO_MODE_Msk (0x30000UL) /*!< SPI_FIFO_MODE (Bitfield-Mask: 0x03) */ +#define SPI_SPI_CTRL_REG_SPI_EN_CTRL_Pos (15UL) /*!< SPI_EN_CTRL (Bit 15) */ +#define SPI_SPI_CTRL_REG_SPI_EN_CTRL_Msk (0x8000UL) /*!< SPI_EN_CTRL (Bitfield-Mask: 0x01) */ +#define SPI_SPI_CTRL_REG_SPI_MINT_Pos (14UL) /*!< SPI_MINT (Bit 14) */ +#define SPI_SPI_CTRL_REG_SPI_MINT_Msk (0x4000UL) /*!< SPI_MINT (Bitfield-Mask: 0x01) */ +#define SPI_SPI_CTRL_REG_SPI_INT_BIT_Pos (13UL) /*!< SPI_INT_BIT (Bit 13) */ +#define SPI_SPI_CTRL_REG_SPI_INT_BIT_Msk (0x2000UL) /*!< SPI_INT_BIT (Bitfield-Mask: 0x01) */ +#define SPI_SPI_CTRL_REG_SPI_DI_Pos (12UL) /*!< SPI_DI (Bit 12) */ +#define SPI_SPI_CTRL_REG_SPI_DI_Msk (0x1000UL) /*!< SPI_DI (Bitfield-Mask: 0x01) */ +#define SPI_SPI_CTRL_REG_SPI_TXH_Pos (11UL) /*!< SPI_TXH (Bit 11) */ +#define SPI_SPI_CTRL_REG_SPI_TXH_Msk (0x800UL) /*!< SPI_TXH (Bitfield-Mask: 0x01) */ +#define SPI_SPI_CTRL_REG_SPI_FORCE_DO_Pos (10UL) /*!< SPI_FORCE_DO (Bit 10) */ +#define SPI_SPI_CTRL_REG_SPI_FORCE_DO_Msk (0x400UL) /*!< SPI_FORCE_DO (Bitfield-Mask: 0x01) */ +#define SPI_SPI_CTRL_REG_SPI_WORD_Pos (8UL) /*!< SPI_WORD (Bit 8) */ +#define SPI_SPI_CTRL_REG_SPI_WORD_Msk (0x300UL) /*!< SPI_WORD (Bitfield-Mask: 0x03) */ +#define SPI_SPI_CTRL_REG_SPI_RST_Pos (7UL) /*!< SPI_RST (Bit 7) */ +#define SPI_SPI_CTRL_REG_SPI_RST_Msk (0x80UL) /*!< SPI_RST (Bitfield-Mask: 0x01) */ +#define SPI_SPI_CTRL_REG_SPI_SMN_Pos (6UL) /*!< SPI_SMN (Bit 6) */ +#define SPI_SPI_CTRL_REG_SPI_SMN_Msk (0x40UL) /*!< SPI_SMN (Bitfield-Mask: 0x01) */ +#define SPI_SPI_CTRL_REG_SPI_DO_Pos (5UL) /*!< SPI_DO (Bit 5) */ +#define SPI_SPI_CTRL_REG_SPI_DO_Msk (0x20UL) /*!< SPI_DO (Bitfield-Mask: 0x01) */ +#define SPI_SPI_CTRL_REG_SPI_CLK_Pos (3UL) /*!< SPI_CLK (Bit 3) */ +#define SPI_SPI_CTRL_REG_SPI_CLK_Msk (0x18UL) /*!< SPI_CLK (Bitfield-Mask: 0x03) */ +#define SPI_SPI_CTRL_REG_SPI_POL_Pos (2UL) /*!< SPI_POL (Bit 2) */ +#define SPI_SPI_CTRL_REG_SPI_POL_Msk (0x4UL) /*!< SPI_POL (Bitfield-Mask: 0x01) */ +#define SPI_SPI_CTRL_REG_SPI_PHA_Pos (1UL) /*!< SPI_PHA (Bit 1) */ +#define SPI_SPI_CTRL_REG_SPI_PHA_Msk (0x2UL) /*!< SPI_PHA (Bitfield-Mask: 0x01) */ +#define SPI_SPI_CTRL_REG_SPI_ON_Pos (0UL) /*!< SPI_ON (Bit 0) */ +#define SPI_SPI_CTRL_REG_SPI_ON_Msk (0x1UL) /*!< SPI_ON (Bitfield-Mask: 0x01) */ +/* ===================================================== SPI_RX_TX_REG ===================================================== */ +#define SPI_SPI_RX_TX_REG_SPI_DATA_Pos (0UL) /*!< SPI_DATA (Bit 0) */ +#define SPI_SPI_RX_TX_REG_SPI_DATA_Msk (0xffffffffUL) /*!< SPI_DATA (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ SPI2 ================ */ +/* =========================================================================================================================== */ + +/* ================================================== SPI2_CLEAR_INT_REG =================================================== */ +#define SPI2_SPI2_CLEAR_INT_REG_SPI_CLEAR_INT_Pos (0UL) /*!< SPI_CLEAR_INT (Bit 0) */ +#define SPI2_SPI2_CLEAR_INT_REG_SPI_CLEAR_INT_Msk (0xffffffffUL) /*!< SPI_CLEAR_INT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SPI2_CTRL_REG ===================================================== */ +#define SPI2_SPI2_CTRL_REG_SPI_TX_FIFO_NOTFULL_MASK_Pos (25UL) /*!< SPI_TX_FIFO_NOTFULL_MASK (Bit 25) */ +#define SPI2_SPI2_CTRL_REG_SPI_TX_FIFO_NOTFULL_MASK_Msk (0x2000000UL) /*!< SPI_TX_FIFO_NOTFULL_MASK (Bitfield-Mask: 0x01) */ +#define SPI2_SPI2_CTRL_REG_SPI_DMA_TXREQ_MODE_Pos (24UL) /*!< SPI_DMA_TXREQ_MODE (Bit 24) */ +#define SPI2_SPI2_CTRL_REG_SPI_DMA_TXREQ_MODE_Msk (0x1000000UL) /*!< SPI_DMA_TXREQ_MODE (Bitfield-Mask: 0x01) */ +#define SPI2_SPI2_CTRL_REG_SPI_TX_FIFO_EMPTY_Pos (23UL) /*!< SPI_TX_FIFO_EMPTY (Bit 23) */ +#define SPI2_SPI2_CTRL_REG_SPI_TX_FIFO_EMPTY_Msk (0x800000UL) /*!< SPI_TX_FIFO_EMPTY (Bitfield-Mask: 0x01) */ +#define SPI2_SPI2_CTRL_REG_SPI_RX_FIFO_FULL_Pos (22UL) /*!< SPI_RX_FIFO_FULL (Bit 22) */ +#define SPI2_SPI2_CTRL_REG_SPI_RX_FIFO_FULL_Msk (0x400000UL) /*!< SPI_RX_FIFO_FULL (Bitfield-Mask: 0x01) */ +#define SPI2_SPI2_CTRL_REG_SPI_RX_FIFO_EMPTY_Pos (21UL) /*!< SPI_RX_FIFO_EMPTY (Bit 21) */ +#define SPI2_SPI2_CTRL_REG_SPI_RX_FIFO_EMPTY_Msk (0x200000UL) /*!< SPI_RX_FIFO_EMPTY (Bitfield-Mask: 0x01) */ +#define SPI2_SPI2_CTRL_REG_SPI_9BIT_VAL_Pos (20UL) /*!< SPI_9BIT_VAL (Bit 20) */ +#define SPI2_SPI2_CTRL_REG_SPI_9BIT_VAL_Msk (0x100000UL) /*!< SPI_9BIT_VAL (Bitfield-Mask: 0x01) */ +#define SPI2_SPI2_CTRL_REG_SPI_BUSY_Pos (19UL) /*!< SPI_BUSY (Bit 19) */ +#define SPI2_SPI2_CTRL_REG_SPI_BUSY_Msk (0x80000UL) /*!< SPI_BUSY (Bitfield-Mask: 0x01) */ +#define SPI2_SPI2_CTRL_REG_SPI_PRIORITY_Pos (18UL) /*!< SPI_PRIORITY (Bit 18) */ +#define SPI2_SPI2_CTRL_REG_SPI_PRIORITY_Msk (0x40000UL) /*!< SPI_PRIORITY (Bitfield-Mask: 0x01) */ +#define SPI2_SPI2_CTRL_REG_SPI_FIFO_MODE_Pos (16UL) /*!< SPI_FIFO_MODE (Bit 16) */ +#define SPI2_SPI2_CTRL_REG_SPI_FIFO_MODE_Msk (0x30000UL) /*!< SPI_FIFO_MODE (Bitfield-Mask: 0x03) */ +#define SPI2_SPI2_CTRL_REG_SPI_EN_CTRL_Pos (15UL) /*!< SPI_EN_CTRL (Bit 15) */ +#define SPI2_SPI2_CTRL_REG_SPI_EN_CTRL_Msk (0x8000UL) /*!< SPI_EN_CTRL (Bitfield-Mask: 0x01) */ +#define SPI2_SPI2_CTRL_REG_SPI_MINT_Pos (14UL) /*!< SPI_MINT (Bit 14) */ +#define SPI2_SPI2_CTRL_REG_SPI_MINT_Msk (0x4000UL) /*!< SPI_MINT (Bitfield-Mask: 0x01) */ +#define SPI2_SPI2_CTRL_REG_SPI_INT_BIT_Pos (13UL) /*!< SPI_INT_BIT (Bit 13) */ +#define SPI2_SPI2_CTRL_REG_SPI_INT_BIT_Msk (0x2000UL) /*!< SPI_INT_BIT (Bitfield-Mask: 0x01) */ +#define SPI2_SPI2_CTRL_REG_SPI_DI_Pos (12UL) /*!< SPI_DI (Bit 12) */ +#define SPI2_SPI2_CTRL_REG_SPI_DI_Msk (0x1000UL) /*!< SPI_DI (Bitfield-Mask: 0x01) */ +#define SPI2_SPI2_CTRL_REG_SPI_TXH_Pos (11UL) /*!< SPI_TXH (Bit 11) */ +#define SPI2_SPI2_CTRL_REG_SPI_TXH_Msk (0x800UL) /*!< SPI_TXH (Bitfield-Mask: 0x01) */ +#define SPI2_SPI2_CTRL_REG_SPI_FORCE_DO_Pos (10UL) /*!< SPI_FORCE_DO (Bit 10) */ +#define SPI2_SPI2_CTRL_REG_SPI_FORCE_DO_Msk (0x400UL) /*!< SPI_FORCE_DO (Bitfield-Mask: 0x01) */ +#define SPI2_SPI2_CTRL_REG_SPI_WORD_Pos (8UL) /*!< SPI_WORD (Bit 8) */ +#define SPI2_SPI2_CTRL_REG_SPI_WORD_Msk (0x300UL) /*!< SPI_WORD (Bitfield-Mask: 0x03) */ +#define SPI2_SPI2_CTRL_REG_SPI_RST_Pos (7UL) /*!< SPI_RST (Bit 7) */ +#define SPI2_SPI2_CTRL_REG_SPI_RST_Msk (0x80UL) /*!< SPI_RST (Bitfield-Mask: 0x01) */ +#define SPI2_SPI2_CTRL_REG_SPI_SMN_Pos (6UL) /*!< SPI_SMN (Bit 6) */ +#define SPI2_SPI2_CTRL_REG_SPI_SMN_Msk (0x40UL) /*!< SPI_SMN (Bitfield-Mask: 0x01) */ +#define SPI2_SPI2_CTRL_REG_SPI_DO_Pos (5UL) /*!< SPI_DO (Bit 5) */ +#define SPI2_SPI2_CTRL_REG_SPI_DO_Msk (0x20UL) /*!< SPI_DO (Bitfield-Mask: 0x01) */ +#define SPI2_SPI2_CTRL_REG_SPI_CLK_Pos (3UL) /*!< SPI_CLK (Bit 3) */ +#define SPI2_SPI2_CTRL_REG_SPI_CLK_Msk (0x18UL) /*!< SPI_CLK (Bitfield-Mask: 0x03) */ +#define SPI2_SPI2_CTRL_REG_SPI_POL_Pos (2UL) /*!< SPI_POL (Bit 2) */ +#define SPI2_SPI2_CTRL_REG_SPI_POL_Msk (0x4UL) /*!< SPI_POL (Bitfield-Mask: 0x01) */ +#define SPI2_SPI2_CTRL_REG_SPI_PHA_Pos (1UL) /*!< SPI_PHA (Bit 1) */ +#define SPI2_SPI2_CTRL_REG_SPI_PHA_Msk (0x2UL) /*!< SPI_PHA (Bitfield-Mask: 0x01) */ +#define SPI2_SPI2_CTRL_REG_SPI_ON_Pos (0UL) /*!< SPI_ON (Bit 0) */ +#define SPI2_SPI2_CTRL_REG_SPI_ON_Msk (0x1UL) /*!< SPI_ON (Bitfield-Mask: 0x01) */ +/* ==================================================== SPI2_RX_TX_REG ===================================================== */ +#define SPI2_SPI2_RX_TX_REG_SPI_DATA_Pos (0UL) /*!< SPI_DATA (Bit 0) */ +#define SPI2_SPI2_RX_TX_REG_SPI_DATA_Msk (0xffffffffUL) /*!< SPI_DATA (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ SYS_WDOG ================ */ +/* =========================================================================================================================== */ + +/* =================================================== WATCHDOG_CTRL_REG =================================================== */ +#define SYS_WDOG_WATCHDOG_CTRL_REG_WRITE_BUSY_Pos (3UL) /*!< WRITE_BUSY (Bit 3) */ +#define SYS_WDOG_WATCHDOG_CTRL_REG_WRITE_BUSY_Msk (0x8UL) /*!< WRITE_BUSY (Bitfield-Mask: 0x01) */ +#define SYS_WDOG_WATCHDOG_CTRL_REG_WDOG_FREEZE_EN_Pos (2UL) /*!< WDOG_FREEZE_EN (Bit 2) */ +#define SYS_WDOG_WATCHDOG_CTRL_REG_WDOG_FREEZE_EN_Msk (0x4UL) /*!< WDOG_FREEZE_EN (Bitfield-Mask: 0x01) */ +#define SYS_WDOG_WATCHDOG_CTRL_REG_NMI_RST_Pos (0UL) /*!< NMI_RST (Bit 0) */ +#define SYS_WDOG_WATCHDOG_CTRL_REG_NMI_RST_Msk (0x1UL) /*!< NMI_RST (Bitfield-Mask: 0x01) */ +/* ===================================================== WATCHDOG_REG ====================================================== */ +#define SYS_WDOG_WATCHDOG_REG_WDOG_WEN_Pos (14UL) /*!< WDOG_WEN (Bit 14) */ +#define SYS_WDOG_WATCHDOG_REG_WDOG_WEN_Msk (0xffffc000UL) /*!< WDOG_WEN (Bitfield-Mask: 0x3ffff) */ +#define SYS_WDOG_WATCHDOG_REG_WDOG_VAL_NEG_Pos (13UL) /*!< WDOG_VAL_NEG (Bit 13) */ +#define SYS_WDOG_WATCHDOG_REG_WDOG_VAL_NEG_Msk (0x2000UL) /*!< WDOG_VAL_NEG (Bitfield-Mask: 0x01) */ +#define SYS_WDOG_WATCHDOG_REG_WDOG_VAL_Pos (0UL) /*!< WDOG_VAL (Bit 0) */ +#define SYS_WDOG_WATCHDOG_REG_WDOG_VAL_Msk (0x1fffUL) /*!< WDOG_VAL (Bitfield-Mask: 0x1fff) */ + + +/* =========================================================================================================================== */ +/* ================ TIMER ================ */ +/* =========================================================================================================================== */ + +/* ================================================ TIMER_CAPTURE_GPIO1_REG ================================================ */ +#define TIMER_TIMER_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos (0UL) /*!< TIM_CAPTURE_GPIO1 (Bit 0) */ +#define TIMER_TIMER_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO1 (Bitfield-Mask: 0xffffff) */ +/* ================================================ TIMER_CAPTURE_GPIO2_REG ================================================ */ +#define TIMER_TIMER_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos (0UL) /*!< TIM_CAPTURE_GPIO2 (Bit 0) */ +#define TIMER_TIMER_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO2 (Bitfield-Mask: 0xffffff) */ +/* ================================================ TIMER_CAPTURE_GPIO3_REG ================================================ */ +#define TIMER_TIMER_CAPTURE_GPIO3_REG_TIM_CAPTURE_GPIO3_Pos (0UL) /*!< TIM_CAPTURE_GPIO3 (Bit 0) */ +#define TIMER_TIMER_CAPTURE_GPIO3_REG_TIM_CAPTURE_GPIO3_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO3 (Bitfield-Mask: 0xffffff) */ +/* ================================================ TIMER_CAPTURE_GPIO4_REG ================================================ */ +#define TIMER_TIMER_CAPTURE_GPIO4_REG_TIM_CAPTURE_GPIO4_Pos (0UL) /*!< TIM_CAPTURE_GPIO4 (Bit 0) */ +#define TIMER_TIMER_CAPTURE_GPIO4_REG_TIM_CAPTURE_GPIO4_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO4 (Bitfield-Mask: 0xffffff) */ +/* ============================================== TIMER_CLEAR_GPIO_EVENT_REG =============================================== */ +#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO4_EVENT_Pos (3UL) /*!< TIM_CLEAR_GPIO4_EVENT (Bit 3) */ +#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO4_EVENT_Msk (0x8UL) /*!< TIM_CLEAR_GPIO4_EVENT (Bitfield-Mask: 0x01) */ +#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO3_EVENT_Pos (2UL) /*!< TIM_CLEAR_GPIO3_EVENT (Bit 2) */ +#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO3_EVENT_Msk (0x4UL) /*!< TIM_CLEAR_GPIO3_EVENT (Bitfield-Mask: 0x01) */ +#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO2_EVENT_Pos (1UL) /*!< TIM_CLEAR_GPIO2_EVENT (Bit 1) */ +#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO2_EVENT_Msk (0x2UL) /*!< TIM_CLEAR_GPIO2_EVENT (Bitfield-Mask: 0x01) */ +#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO1_EVENT_Pos (0UL) /*!< TIM_CLEAR_GPIO1_EVENT (Bit 0) */ +#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO1_EVENT_Msk (0x1UL) /*!< TIM_CLEAR_GPIO1_EVENT (Bitfield-Mask: 0x01) */ +/* ================================================== TIMER_CLEAR_IRQ_REG ================================================== */ +#define TIMER_TIMER_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL) /*!< TIM_CLEAR_IRQ (Bit 0) */ +#define TIMER_TIMER_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL) /*!< TIM_CLEAR_IRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== TIMER_CTRL_REG ===================================================== */ +#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO4_IRQ_EN_Pos (14UL) /*!< TIM_CAP_GPIO4_IRQ_EN (Bit 14) */ +#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO4_IRQ_EN_Msk (0x4000UL) /*!< TIM_CAP_GPIO4_IRQ_EN (Bitfield-Mask: 0x01) */ +#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO3_IRQ_EN_Pos (13UL) /*!< TIM_CAP_GPIO3_IRQ_EN (Bit 13) */ +#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO3_IRQ_EN_Msk (0x2000UL) /*!< TIM_CAP_GPIO3_IRQ_EN (Bitfield-Mask: 0x01) */ +#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO2_IRQ_EN_Pos (12UL) /*!< TIM_CAP_GPIO2_IRQ_EN (Bit 12) */ +#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO2_IRQ_EN_Msk (0x1000UL) /*!< TIM_CAP_GPIO2_IRQ_EN (Bitfield-Mask: 0x01) */ +#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO1_IRQ_EN_Pos (11UL) /*!< TIM_CAP_GPIO1_IRQ_EN (Bit 11) */ +#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO1_IRQ_EN_Msk (0x800UL) /*!< TIM_CAP_GPIO1_IRQ_EN (Bitfield-Mask: 0x01) */ +#define TIMER_TIMER_CTRL_REG_TIM_IN4_EVENT_FALL_EN_Pos (10UL) /*!< TIM_IN4_EVENT_FALL_EN (Bit 10) */ +#define TIMER_TIMER_CTRL_REG_TIM_IN4_EVENT_FALL_EN_Msk (0x400UL) /*!< TIM_IN4_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ +#define TIMER_TIMER_CTRL_REG_TIM_IN3_EVENT_FALL_EN_Pos (9UL) /*!< TIM_IN3_EVENT_FALL_EN (Bit 9) */ +#define TIMER_TIMER_CTRL_REG_TIM_IN3_EVENT_FALL_EN_Msk (0x200UL) /*!< TIM_IN3_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ +#define TIMER_TIMER_CTRL_REG_TIM_CLK_EN_Pos (8UL) /*!< TIM_CLK_EN (Bit 8) */ +#define TIMER_TIMER_CTRL_REG_TIM_CLK_EN_Msk (0x100UL) /*!< TIM_CLK_EN (Bitfield-Mask: 0x01) */ +#define TIMER_TIMER_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL) /*!< TIM_SYS_CLK_EN (Bit 7) */ +#define TIMER_TIMER_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL) /*!< TIM_SYS_CLK_EN (Bitfield-Mask: 0x01) */ +#define TIMER_TIMER_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL) /*!< TIM_FREE_RUN_MODE_EN (Bit 6) */ +#define TIMER_TIMER_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL) /*!< TIM_FREE_RUN_MODE_EN (Bitfield-Mask: 0x01) */ +#define TIMER_TIMER_CTRL_REG_TIM_IRQ_EN_Pos (5UL) /*!< TIM_IRQ_EN (Bit 5) */ +#define TIMER_TIMER_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL) /*!< TIM_IRQ_EN (Bitfield-Mask: 0x01) */ +#define TIMER_TIMER_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL) /*!< TIM_IN2_EVENT_FALL_EN (Bit 4) */ +#define TIMER_TIMER_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL) /*!< TIM_IN2_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ +#define TIMER_TIMER_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL) /*!< TIM_IN1_EVENT_FALL_EN (Bit 3) */ +#define TIMER_TIMER_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL) /*!< TIM_IN1_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ +#define TIMER_TIMER_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL) /*!< TIM_COUNT_DOWN_EN (Bit 2) */ +#define TIMER_TIMER_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL) /*!< TIM_COUNT_DOWN_EN (Bitfield-Mask: 0x01) */ +#define TIMER_TIMER_CTRL_REG_TIM_ONESHOT_MODE_EN_Pos (1UL) /*!< TIM_ONESHOT_MODE_EN (Bit 1) */ +#define TIMER_TIMER_CTRL_REG_TIM_ONESHOT_MODE_EN_Msk (0x2UL) /*!< TIM_ONESHOT_MODE_EN (Bitfield-Mask: 0x01) */ +#define TIMER_TIMER_CTRL_REG_TIM_EN_Pos (0UL) /*!< TIM_EN (Bit 0) */ +#define TIMER_TIMER_CTRL_REG_TIM_EN_Msk (0x1UL) /*!< TIM_EN (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER_GPIO1_CONF_REG ================================================== */ +#define TIMER_TIMER_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL) /*!< TIM_GPIO1_CONF (Bit 0) */ +#define TIMER_TIMER_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL) /*!< TIM_GPIO1_CONF (Bitfield-Mask: 0x3f) */ +/* ================================================= TIMER_GPIO2_CONF_REG ================================================== */ +#define TIMER_TIMER_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL) /*!< TIM_GPIO2_CONF (Bit 0) */ +#define TIMER_TIMER_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL) /*!< TIM_GPIO2_CONF (Bitfield-Mask: 0x3f) */ +/* ================================================= TIMER_GPIO3_CONF_REG ================================================== */ +#define TIMER_TIMER_GPIO3_CONF_REG_TIM_GPIO3_CONF_Pos (0UL) /*!< TIM_GPIO3_CONF (Bit 0) */ +#define TIMER_TIMER_GPIO3_CONF_REG_TIM_GPIO3_CONF_Msk (0x3fUL) /*!< TIM_GPIO3_CONF (Bitfield-Mask: 0x3f) */ +/* ================================================= TIMER_GPIO4_CONF_REG ================================================== */ +#define TIMER_TIMER_GPIO4_CONF_REG_TIM_GPIO4_CONF_Pos (0UL) /*!< TIM_GPIO4_CONF (Bit 0) */ +#define TIMER_TIMER_GPIO4_CONF_REG_TIM_GPIO4_CONF_Msk (0x3fUL) /*!< TIM_GPIO4_CONF (Bitfield-Mask: 0x3f) */ +/* ================================================== TIMER_PRESCALER_REG ================================================== */ +#define TIMER_TIMER_PRESCALER_REG_TIM_PRESCALER_Pos (0UL) /*!< TIM_PRESCALER (Bit 0) */ +#define TIMER_TIMER_PRESCALER_REG_TIM_PRESCALER_Msk (0x1fUL) /*!< TIM_PRESCALER (Bitfield-Mask: 0x1f) */ +/* ================================================ TIMER_PRESCALER_VAL_REG ================================================ */ +#define TIMER_TIMER_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL) /*!< TIM_PRESCALER_VAL (Bit 0) */ +#define TIMER_TIMER_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL) /*!< TIM_PRESCALER_VAL (Bitfield-Mask: 0x1f) */ +/* =================================================== TIMER_PWM_DC_REG ==================================================== */ +#define TIMER_TIMER_PWM_DC_REG_TIM_PWM_DC_Pos (0UL) /*!< TIM_PWM_DC (Bit 0) */ +#define TIMER_TIMER_PWM_DC_REG_TIM_PWM_DC_Msk (0xffffUL) /*!< TIM_PWM_DC (Bitfield-Mask: 0xffff) */ +/* ================================================== TIMER_PWM_FREQ_REG =================================================== */ +#define TIMER_TIMER_PWM_FREQ_REG_TIM_PWM_FREQ_Pos (0UL) /*!< TIM_PWM_FREQ (Bit 0) */ +#define TIMER_TIMER_PWM_FREQ_REG_TIM_PWM_FREQ_Msk (0xffffUL) /*!< TIM_PWM_FREQ (Bitfield-Mask: 0xffff) */ +/* =================================================== TIMER_RELOAD_REG ==================================================== */ +#define TIMER_TIMER_RELOAD_REG_TIM_RELOAD_Pos (0UL) /*!< TIM_RELOAD (Bit 0) */ +#define TIMER_TIMER_RELOAD_REG_TIM_RELOAD_Msk (0xffffffUL) /*!< TIM_RELOAD (Bitfield-Mask: 0xffffff) */ +/* ================================================== TIMER_SHOTWIDTH_REG ================================================== */ +#define TIMER_TIMER_SHOTWIDTH_REG_TIM_SHOTWIDTH_Pos (0UL) /*!< TIM_SHOTWIDTH (Bit 0) */ +#define TIMER_TIMER_SHOTWIDTH_REG_TIM_SHOTWIDTH_Msk (0xffffffUL) /*!< TIM_SHOTWIDTH (Bitfield-Mask: 0xffffff) */ +/* =================================================== TIMER_STATUS_REG ==================================================== */ +#define TIMER_TIMER_STATUS_REG_TIM_GPIO4_EVENT_PENDING_Pos (7UL) /*!< TIM_GPIO4_EVENT_PENDING (Bit 7) */ +#define TIMER_TIMER_STATUS_REG_TIM_GPIO4_EVENT_PENDING_Msk (0x80UL) /*!< TIM_GPIO4_EVENT_PENDING (Bitfield-Mask: 0x01) */ +#define TIMER_TIMER_STATUS_REG_TIM_GPIO3_EVENT_PENDING_Pos (6UL) /*!< TIM_GPIO3_EVENT_PENDING (Bit 6) */ +#define TIMER_TIMER_STATUS_REG_TIM_GPIO3_EVENT_PENDING_Msk (0x40UL) /*!< TIM_GPIO3_EVENT_PENDING (Bitfield-Mask: 0x01) */ +#define TIMER_TIMER_STATUS_REG_TIM_GPIO2_EVENT_PENDING_Pos (5UL) /*!< TIM_GPIO2_EVENT_PENDING (Bit 5) */ +#define TIMER_TIMER_STATUS_REG_TIM_GPIO2_EVENT_PENDING_Msk (0x20UL) /*!< TIM_GPIO2_EVENT_PENDING (Bitfield-Mask: 0x01) */ +#define TIMER_TIMER_STATUS_REG_TIM_GPIO1_EVENT_PENDING_Pos (4UL) /*!< TIM_GPIO1_EVENT_PENDING (Bit 4) */ +#define TIMER_TIMER_STATUS_REG_TIM_GPIO1_EVENT_PENDING_Msk (0x10UL) /*!< TIM_GPIO1_EVENT_PENDING (Bitfield-Mask: 0x01) */ +#define TIMER_TIMER_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL) /*!< TIM_ONESHOT_PHASE (Bit 2) */ +#define TIMER_TIMER_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL) /*!< TIM_ONESHOT_PHASE (Bitfield-Mask: 0x03) */ +#define TIMER_TIMER_STATUS_REG_TIM_IN2_STATE_Pos (1UL) /*!< TIM_IN2_STATE (Bit 1) */ +#define TIMER_TIMER_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL) /*!< TIM_IN2_STATE (Bitfield-Mask: 0x01) */ +#define TIMER_TIMER_STATUS_REG_TIM_IN1_STATE_Pos (0UL) /*!< TIM_IN1_STATE (Bit 0) */ +#define TIMER_TIMER_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL) /*!< TIM_IN1_STATE (Bitfield-Mask: 0x01) */ +/* ================================================== TIMER_TIMER_VAL_REG ================================================== */ +#define TIMER_TIMER_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos (0UL) /*!< TIM_TIMER_VALUE (Bit 0) */ +#define TIMER_TIMER_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk (0xffffffUL) /*!< TIM_TIMER_VALUE (Bitfield-Mask: 0xffffff) */ + + +/* =========================================================================================================================== */ +/* ================ TIMER2 ================ */ +/* =========================================================================================================================== */ + +/* =============================================== TIMER2_CAPTURE_GPIO1_REG ================================================ */ +#define TIMER2_TIMER2_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos (0UL) /*!< TIM_CAPTURE_GPIO1 (Bit 0) */ +#define TIMER2_TIMER2_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO1 (Bitfield-Mask: 0xffffff) */ +/* =============================================== TIMER2_CAPTURE_GPIO2_REG ================================================ */ +#define TIMER2_TIMER2_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos (0UL) /*!< TIM_CAPTURE_GPIO2 (Bit 0) */ +#define TIMER2_TIMER2_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO2 (Bitfield-Mask: 0xffffff) */ +/* ================================================= TIMER2_CLEAR_IRQ_REG ================================================== */ +#define TIMER2_TIMER2_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL) /*!< TIM_CLEAR_IRQ (Bit 0) */ +#define TIMER2_TIMER2_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL) /*!< TIM_CLEAR_IRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== TIMER2_CTRL_REG ==================================================== */ +#define TIMER2_TIMER2_CTRL_REG_TIM_CLK_EN_Pos (8UL) /*!< TIM_CLK_EN (Bit 8) */ +#define TIMER2_TIMER2_CTRL_REG_TIM_CLK_EN_Msk (0x100UL) /*!< TIM_CLK_EN (Bitfield-Mask: 0x01) */ +#define TIMER2_TIMER2_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL) /*!< TIM_SYS_CLK_EN (Bit 7) */ +#define TIMER2_TIMER2_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL) /*!< TIM_SYS_CLK_EN (Bitfield-Mask: 0x01) */ +#define TIMER2_TIMER2_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL) /*!< TIM_FREE_RUN_MODE_EN (Bit 6) */ +#define TIMER2_TIMER2_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL) /*!< TIM_FREE_RUN_MODE_EN (Bitfield-Mask: 0x01) */ +#define TIMER2_TIMER2_CTRL_REG_TIM_IRQ_EN_Pos (5UL) /*!< TIM_IRQ_EN (Bit 5) */ +#define TIMER2_TIMER2_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL) /*!< TIM_IRQ_EN (Bitfield-Mask: 0x01) */ +#define TIMER2_TIMER2_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL) /*!< TIM_IN2_EVENT_FALL_EN (Bit 4) */ +#define TIMER2_TIMER2_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL) /*!< TIM_IN2_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ +#define TIMER2_TIMER2_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL) /*!< TIM_IN1_EVENT_FALL_EN (Bit 3) */ +#define TIMER2_TIMER2_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL) /*!< TIM_IN1_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ +#define TIMER2_TIMER2_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL) /*!< TIM_COUNT_DOWN_EN (Bit 2) */ +#define TIMER2_TIMER2_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL) /*!< TIM_COUNT_DOWN_EN (Bitfield-Mask: 0x01) */ +#define TIMER2_TIMER2_CTRL_REG_TIM_ONESHOT_MODE_EN_Pos (1UL) /*!< TIM_ONESHOT_MODE_EN (Bit 1) */ +#define TIMER2_TIMER2_CTRL_REG_TIM_ONESHOT_MODE_EN_Msk (0x2UL) /*!< TIM_ONESHOT_MODE_EN (Bitfield-Mask: 0x01) */ +#define TIMER2_TIMER2_CTRL_REG_TIM_EN_Pos (0UL) /*!< TIM_EN (Bit 0) */ +#define TIMER2_TIMER2_CTRL_REG_TIM_EN_Msk (0x1UL) /*!< TIM_EN (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER2_GPIO1_CONF_REG ================================================= */ +#define TIMER2_TIMER2_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL) /*!< TIM_GPIO1_CONF (Bit 0) */ +#define TIMER2_TIMER2_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL) /*!< TIM_GPIO1_CONF (Bitfield-Mask: 0x3f) */ +/* ================================================= TIMER2_GPIO2_CONF_REG ================================================= */ +#define TIMER2_TIMER2_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL) /*!< TIM_GPIO2_CONF (Bit 0) */ +#define TIMER2_TIMER2_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL) /*!< TIM_GPIO2_CONF (Bitfield-Mask: 0x3f) */ +/* ================================================= TIMER2_PRESCALER_REG ================================================== */ +#define TIMER2_TIMER2_PRESCALER_REG_TIM_PRESCALER_Pos (0UL) /*!< TIM_PRESCALER (Bit 0) */ +#define TIMER2_TIMER2_PRESCALER_REG_TIM_PRESCALER_Msk (0x1fUL) /*!< TIM_PRESCALER (Bitfield-Mask: 0x1f) */ +/* =============================================== TIMER2_PRESCALER_VAL_REG ================================================ */ +#define TIMER2_TIMER2_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL) /*!< TIM_PRESCALER_VAL (Bit 0) */ +#define TIMER2_TIMER2_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL) /*!< TIM_PRESCALER_VAL (Bitfield-Mask: 0x1f) */ +/* =================================================== TIMER2_PWM_DC_REG =================================================== */ +#define TIMER2_TIMER2_PWM_DC_REG_TIM_PWM_DC_Pos (0UL) /*!< TIM_PWM_DC (Bit 0) */ +#define TIMER2_TIMER2_PWM_DC_REG_TIM_PWM_DC_Msk (0xffffUL) /*!< TIM_PWM_DC (Bitfield-Mask: 0xffff) */ +/* ================================================== TIMER2_PWM_FREQ_REG ================================================== */ +#define TIMER2_TIMER2_PWM_FREQ_REG_TIM_PWM_FREQ_Pos (0UL) /*!< TIM_PWM_FREQ (Bit 0) */ +#define TIMER2_TIMER2_PWM_FREQ_REG_TIM_PWM_FREQ_Msk (0xffffUL) /*!< TIM_PWM_FREQ (Bitfield-Mask: 0xffff) */ +/* =================================================== TIMER2_RELOAD_REG =================================================== */ +#define TIMER2_TIMER2_RELOAD_REG_TIM_RELOAD_Pos (0UL) /*!< TIM_RELOAD (Bit 0) */ +#define TIMER2_TIMER2_RELOAD_REG_TIM_RELOAD_Msk (0xffffffUL) /*!< TIM_RELOAD (Bitfield-Mask: 0xffffff) */ +/* ================================================= TIMER2_SHOTWIDTH_REG ================================================== */ +#define TIMER2_TIMER2_SHOTWIDTH_REG_TIM_SHOTWIDTH_Pos (0UL) /*!< TIM_SHOTWIDTH (Bit 0) */ +#define TIMER2_TIMER2_SHOTWIDTH_REG_TIM_SHOTWIDTH_Msk (0xffffffUL) /*!< TIM_SHOTWIDTH (Bitfield-Mask: 0xffffff) */ +/* =================================================== TIMER2_STATUS_REG =================================================== */ +#define TIMER2_TIMER2_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL) /*!< TIM_ONESHOT_PHASE (Bit 2) */ +#define TIMER2_TIMER2_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL) /*!< TIM_ONESHOT_PHASE (Bitfield-Mask: 0x03) */ +#define TIMER2_TIMER2_STATUS_REG_TIM_IN2_STATE_Pos (1UL) /*!< TIM_IN2_STATE (Bit 1) */ +#define TIMER2_TIMER2_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL) /*!< TIM_IN2_STATE (Bitfield-Mask: 0x01) */ +#define TIMER2_TIMER2_STATUS_REG_TIM_IN1_STATE_Pos (0UL) /*!< TIM_IN1_STATE (Bit 0) */ +#define TIMER2_TIMER2_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL) /*!< TIM_IN1_STATE (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER2_TIMER_VAL_REG ================================================== */ +#define TIMER2_TIMER2_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos (0UL) /*!< TIM_TIMER_VALUE (Bit 0) */ +#define TIMER2_TIMER2_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk (0xffffffUL) /*!< TIM_TIMER_VALUE (Bitfield-Mask: 0xffffff) */ + + +/* =========================================================================================================================== */ +/* ================ TIMER3 ================ */ +/* =========================================================================================================================== */ + +/* =============================================== TIMER3_CAPTURE_GPIO1_REG ================================================ */ +#define TIMER3_TIMER3_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos (0UL) /*!< TIM_CAPTURE_GPIO1 (Bit 0) */ +#define TIMER3_TIMER3_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO1 (Bitfield-Mask: 0xffffff) */ +/* =============================================== TIMER3_CAPTURE_GPIO2_REG ================================================ */ +#define TIMER3_TIMER3_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos (0UL) /*!< TIM_CAPTURE_GPIO2 (Bit 0) */ +#define TIMER3_TIMER3_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO2 (Bitfield-Mask: 0xffffff) */ +/* ================================================= TIMER3_CLEAR_IRQ_REG ================================================== */ +#define TIMER3_TIMER3_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL) /*!< TIM_CLEAR_IRQ (Bit 0) */ +#define TIMER3_TIMER3_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL) /*!< TIM_CLEAR_IRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== TIMER3_CTRL_REG ==================================================== */ +#define TIMER3_TIMER3_CTRL_REG_TIM_CLK_EN_Pos (8UL) /*!< TIM_CLK_EN (Bit 8) */ +#define TIMER3_TIMER3_CTRL_REG_TIM_CLK_EN_Msk (0x100UL) /*!< TIM_CLK_EN (Bitfield-Mask: 0x01) */ +#define TIMER3_TIMER3_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL) /*!< TIM_SYS_CLK_EN (Bit 7) */ +#define TIMER3_TIMER3_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL) /*!< TIM_SYS_CLK_EN (Bitfield-Mask: 0x01) */ +#define TIMER3_TIMER3_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL) /*!< TIM_FREE_RUN_MODE_EN (Bit 6) */ +#define TIMER3_TIMER3_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL) /*!< TIM_FREE_RUN_MODE_EN (Bitfield-Mask: 0x01) */ +#define TIMER3_TIMER3_CTRL_REG_TIM_IRQ_EN_Pos (5UL) /*!< TIM_IRQ_EN (Bit 5) */ +#define TIMER3_TIMER3_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL) /*!< TIM_IRQ_EN (Bitfield-Mask: 0x01) */ +#define TIMER3_TIMER3_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL) /*!< TIM_IN2_EVENT_FALL_EN (Bit 4) */ +#define TIMER3_TIMER3_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL) /*!< TIM_IN2_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ +#define TIMER3_TIMER3_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL) /*!< TIM_IN1_EVENT_FALL_EN (Bit 3) */ +#define TIMER3_TIMER3_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL) /*!< TIM_IN1_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ +#define TIMER3_TIMER3_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL) /*!< TIM_COUNT_DOWN_EN (Bit 2) */ +#define TIMER3_TIMER3_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL) /*!< TIM_COUNT_DOWN_EN (Bitfield-Mask: 0x01) */ +#define TIMER3_TIMER3_CTRL_REG_TIM_EN_Pos (0UL) /*!< TIM_EN (Bit 0) */ +#define TIMER3_TIMER3_CTRL_REG_TIM_EN_Msk (0x1UL) /*!< TIM_EN (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER3_GPIO1_CONF_REG ================================================= */ +#define TIMER3_TIMER3_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL) /*!< TIM_GPIO1_CONF (Bit 0) */ +#define TIMER3_TIMER3_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL) /*!< TIM_GPIO1_CONF (Bitfield-Mask: 0x3f) */ +/* ================================================= TIMER3_GPIO2_CONF_REG ================================================= */ +#define TIMER3_TIMER3_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL) /*!< TIM_GPIO2_CONF (Bit 0) */ +#define TIMER3_TIMER3_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL) /*!< TIM_GPIO2_CONF (Bitfield-Mask: 0x3f) */ +/* ================================================= TIMER3_PRESCALER_REG ================================================== */ +#define TIMER3_TIMER3_PRESCALER_REG_TIM_PRESCALER_Pos (0UL) /*!< TIM_PRESCALER (Bit 0) */ +#define TIMER3_TIMER3_PRESCALER_REG_TIM_PRESCALER_Msk (0x1fUL) /*!< TIM_PRESCALER (Bitfield-Mask: 0x1f) */ +/* =============================================== TIMER3_PRESCALER_VAL_REG ================================================ */ +#define TIMER3_TIMER3_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL) /*!< TIM_PRESCALER_VAL (Bit 0) */ +#define TIMER3_TIMER3_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL) /*!< TIM_PRESCALER_VAL (Bitfield-Mask: 0x1f) */ +/* =================================================== TIMER3_PWM_DC_REG =================================================== */ +#define TIMER3_TIMER3_PWM_DC_REG_TIM_PWM_DC_Pos (0UL) /*!< TIM_PWM_DC (Bit 0) */ +#define TIMER3_TIMER3_PWM_DC_REG_TIM_PWM_DC_Msk (0xffffUL) /*!< TIM_PWM_DC (Bitfield-Mask: 0xffff) */ +/* ================================================== TIMER3_PWM_FREQ_REG ================================================== */ +#define TIMER3_TIMER3_PWM_FREQ_REG_TIM_PWM_FREQ_Pos (0UL) /*!< TIM_PWM_FREQ (Bit 0) */ +#define TIMER3_TIMER3_PWM_FREQ_REG_TIM_PWM_FREQ_Msk (0xffffUL) /*!< TIM_PWM_FREQ (Bitfield-Mask: 0xffff) */ +/* =================================================== TIMER3_RELOAD_REG =================================================== */ +#define TIMER3_TIMER3_RELOAD_REG_TIM_RELOAD_Pos (0UL) /*!< TIM_RELOAD (Bit 0) */ +#define TIMER3_TIMER3_RELOAD_REG_TIM_RELOAD_Msk (0xffffffUL) /*!< TIM_RELOAD (Bitfield-Mask: 0xffffff) */ +/* =================================================== TIMER3_STATUS_REG =================================================== */ +#define TIMER3_TIMER3_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL) /*!< TIM_ONESHOT_PHASE (Bit 2) */ +#define TIMER3_TIMER3_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL) /*!< TIM_ONESHOT_PHASE (Bitfield-Mask: 0x03) */ +#define TIMER3_TIMER3_STATUS_REG_TIM_IN2_STATE_Pos (1UL) /*!< TIM_IN2_STATE (Bit 1) */ +#define TIMER3_TIMER3_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL) /*!< TIM_IN2_STATE (Bitfield-Mask: 0x01) */ +#define TIMER3_TIMER3_STATUS_REG_TIM_IN1_STATE_Pos (0UL) /*!< TIM_IN1_STATE (Bit 0) */ +#define TIMER3_TIMER3_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL) /*!< TIM_IN1_STATE (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER3_TIMER_VAL_REG ================================================== */ +#define TIMER3_TIMER3_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos (0UL) /*!< TIM_TIMER_VALUE (Bit 0) */ +#define TIMER3_TIMER3_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk (0xffffffUL) /*!< TIM_TIMER_VALUE (Bitfield-Mask: 0xffffff) */ + + +/* =========================================================================================================================== */ +/* ================ TIMER4 ================ */ +/* =========================================================================================================================== */ + +/* =============================================== TIMER4_CAPTURE_GPIO1_REG ================================================ */ +#define TIMER4_TIMER4_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos (0UL) /*!< TIM_CAPTURE_GPIO1 (Bit 0) */ +#define TIMER4_TIMER4_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO1 (Bitfield-Mask: 0xffffff) */ +/* =============================================== TIMER4_CAPTURE_GPIO2_REG ================================================ */ +#define TIMER4_TIMER4_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos (0UL) /*!< TIM_CAPTURE_GPIO2 (Bit 0) */ +#define TIMER4_TIMER4_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO2 (Bitfield-Mask: 0xffffff) */ +/* ================================================= TIMER4_CLEAR_IRQ_REG ================================================== */ +#define TIMER4_TIMER4_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL) /*!< TIM_CLEAR_IRQ (Bit 0) */ +#define TIMER4_TIMER4_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL) /*!< TIM_CLEAR_IRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== TIMER4_CTRL_REG ==================================================== */ +#define TIMER4_TIMER4_CTRL_REG_TIM_CLK_EN_Pos (8UL) /*!< TIM_CLK_EN (Bit 8) */ +#define TIMER4_TIMER4_CTRL_REG_TIM_CLK_EN_Msk (0x100UL) /*!< TIM_CLK_EN (Bitfield-Mask: 0x01) */ +#define TIMER4_TIMER4_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL) /*!< TIM_SYS_CLK_EN (Bit 7) */ +#define TIMER4_TIMER4_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL) /*!< TIM_SYS_CLK_EN (Bitfield-Mask: 0x01) */ +#define TIMER4_TIMER4_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL) /*!< TIM_FREE_RUN_MODE_EN (Bit 6) */ +#define TIMER4_TIMER4_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL) /*!< TIM_FREE_RUN_MODE_EN (Bitfield-Mask: 0x01) */ +#define TIMER4_TIMER4_CTRL_REG_TIM_IRQ_EN_Pos (5UL) /*!< TIM_IRQ_EN (Bit 5) */ +#define TIMER4_TIMER4_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL) /*!< TIM_IRQ_EN (Bitfield-Mask: 0x01) */ +#define TIMER4_TIMER4_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL) /*!< TIM_IN2_EVENT_FALL_EN (Bit 4) */ +#define TIMER4_TIMER4_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL) /*!< TIM_IN2_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ +#define TIMER4_TIMER4_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL) /*!< TIM_IN1_EVENT_FALL_EN (Bit 3) */ +#define TIMER4_TIMER4_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL) /*!< TIM_IN1_EVENT_FALL_EN (Bitfield-Mask: 0x01) */ +#define TIMER4_TIMER4_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL) /*!< TIM_COUNT_DOWN_EN (Bit 2) */ +#define TIMER4_TIMER4_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL) /*!< TIM_COUNT_DOWN_EN (Bitfield-Mask: 0x01) */ +#define TIMER4_TIMER4_CTRL_REG_TIM_EN_Pos (0UL) /*!< TIM_EN (Bit 0) */ +#define TIMER4_TIMER4_CTRL_REG_TIM_EN_Msk (0x1UL) /*!< TIM_EN (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER4_GPIO1_CONF_REG ================================================= */ +#define TIMER4_TIMER4_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL) /*!< TIM_GPIO1_CONF (Bit 0) */ +#define TIMER4_TIMER4_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL) /*!< TIM_GPIO1_CONF (Bitfield-Mask: 0x3f) */ +/* ================================================= TIMER4_GPIO2_CONF_REG ================================================= */ +#define TIMER4_TIMER4_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL) /*!< TIM_GPIO2_CONF (Bit 0) */ +#define TIMER4_TIMER4_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL) /*!< TIM_GPIO2_CONF (Bitfield-Mask: 0x3f) */ +/* ================================================= TIMER4_PRESCALER_REG ================================================== */ +#define TIMER4_TIMER4_PRESCALER_REG_TIM_PRESCALER_Pos (0UL) /*!< TIM_PRESCALER (Bit 0) */ +#define TIMER4_TIMER4_PRESCALER_REG_TIM_PRESCALER_Msk (0x1fUL) /*!< TIM_PRESCALER (Bitfield-Mask: 0x1f) */ +/* =============================================== TIMER4_PRESCALER_VAL_REG ================================================ */ +#define TIMER4_TIMER4_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL) /*!< TIM_PRESCALER_VAL (Bit 0) */ +#define TIMER4_TIMER4_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL) /*!< TIM_PRESCALER_VAL (Bitfield-Mask: 0x1f) */ +/* =================================================== TIMER4_PWM_DC_REG =================================================== */ +#define TIMER4_TIMER4_PWM_DC_REG_TIM_PWM_DC_Pos (0UL) /*!< TIM_PWM_DC (Bit 0) */ +#define TIMER4_TIMER4_PWM_DC_REG_TIM_PWM_DC_Msk (0xffffUL) /*!< TIM_PWM_DC (Bitfield-Mask: 0xffff) */ +/* ================================================== TIMER4_PWM_FREQ_REG ================================================== */ +#define TIMER4_TIMER4_PWM_FREQ_REG_TIM_PWM_FREQ_Pos (0UL) /*!< TIM_PWM_FREQ (Bit 0) */ +#define TIMER4_TIMER4_PWM_FREQ_REG_TIM_PWM_FREQ_Msk (0xffffUL) /*!< TIM_PWM_FREQ (Bitfield-Mask: 0xffff) */ +/* =================================================== TIMER4_RELOAD_REG =================================================== */ +#define TIMER4_TIMER4_RELOAD_REG_TIM_RELOAD_Pos (0UL) /*!< TIM_RELOAD (Bit 0) */ +#define TIMER4_TIMER4_RELOAD_REG_TIM_RELOAD_Msk (0xffffffUL) /*!< TIM_RELOAD (Bitfield-Mask: 0xffffff) */ +/* =================================================== TIMER4_STATUS_REG =================================================== */ +#define TIMER4_TIMER4_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL) /*!< TIM_ONESHOT_PHASE (Bit 2) */ +#define TIMER4_TIMER4_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL) /*!< TIM_ONESHOT_PHASE (Bitfield-Mask: 0x03) */ +#define TIMER4_TIMER4_STATUS_REG_TIM_IN2_STATE_Pos (1UL) /*!< TIM_IN2_STATE (Bit 1) */ +#define TIMER4_TIMER4_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL) /*!< TIM_IN2_STATE (Bitfield-Mask: 0x01) */ +#define TIMER4_TIMER4_STATUS_REG_TIM_IN1_STATE_Pos (0UL) /*!< TIM_IN1_STATE (Bit 0) */ +#define TIMER4_TIMER4_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL) /*!< TIM_IN1_STATE (Bitfield-Mask: 0x01) */ +/* ================================================= TIMER4_TIMER_VAL_REG ================================================== */ +#define TIMER4_TIMER4_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos (0UL) /*!< TIM_TIMER_VALUE (Bit 0) */ +#define TIMER4_TIMER4_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk (0xffffffUL) /*!< TIM_TIMER_VALUE (Bitfield-Mask: 0xffffff) */ + + +/* =========================================================================================================================== */ +/* ================ TRNG ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== TRNG_CTRL_REG ===================================================== */ +#define TRNG_TRNG_CTRL_REG_TRNG_ENABLE_Pos (0UL) /*!< TRNG_ENABLE (Bit 0) */ +#define TRNG_TRNG_CTRL_REG_TRNG_ENABLE_Msk (0x1UL) /*!< TRNG_ENABLE (Bitfield-Mask: 0x01) */ +/* =================================================== TRNG_FIFOLVL_REG ==================================================== */ +#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOFULL_Pos (5UL) /*!< TRNG_FIFOFULL (Bit 5) */ +#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOFULL_Msk (0x20UL) /*!< TRNG_FIFOFULL (Bitfield-Mask: 0x01) */ +#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOLVL_Pos (0UL) /*!< TRNG_FIFOLVL (Bit 0) */ +#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOLVL_Msk (0x1fUL) /*!< TRNG_FIFOLVL (Bitfield-Mask: 0x1f) */ +/* ===================================================== TRNG_VER_REG ====================================================== */ +#define TRNG_TRNG_VER_REG_TRNG_MAJ_Pos (24UL) /*!< TRNG_MAJ (Bit 24) */ +#define TRNG_TRNG_VER_REG_TRNG_MAJ_Msk (0xff000000UL) /*!< TRNG_MAJ (Bitfield-Mask: 0xff) */ +#define TRNG_TRNG_VER_REG_TRNG_MIN_Pos (16UL) /*!< TRNG_MIN (Bit 16) */ +#define TRNG_TRNG_VER_REG_TRNG_MIN_Msk (0xff0000UL) /*!< TRNG_MIN (Bitfield-Mask: 0xff) */ +#define TRNG_TRNG_VER_REG_TRNG_SVN_Pos (0UL) /*!< TRNG_SVN (Bit 0) */ +#define TRNG_TRNG_VER_REG_TRNG_SVN_Msk (0xffffUL) /*!< TRNG_SVN (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ UART ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== UART_CTR_REG ====================================================== */ +#define UART_UART_CTR_REG_UART_CTR_Pos (0UL) /*!< UART_CTR (Bit 0) */ +#define UART_UART_CTR_REG_UART_CTR_Msk (0xffffffffUL) /*!< UART_CTR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== UART_DLF_REG ====================================================== */ +#define UART_UART_DLF_REG_UART_DLF_Pos (0UL) /*!< UART_DLF (Bit 0) */ +#define UART_UART_DLF_REG_UART_DLF_Msk (0xfUL) /*!< UART_DLF (Bitfield-Mask: 0x0f) */ +/* ==================================================== UART_DMASA_REG ===================================================== */ +#define UART_UART_DMASA_REG_UART_DMASA_Pos (0UL) /*!< UART_DMASA (Bit 0) */ +#define UART_UART_DMASA_REG_UART_DMASA_Msk (0x1UL) /*!< UART_DMASA (Bitfield-Mask: 0x01) */ +/* ===================================================== UART_HTX_REG ====================================================== */ +#define UART_UART_HTX_REG_UART_HALT_TX_Pos (0UL) /*!< UART_HALT_TX (Bit 0) */ +#define UART_UART_HTX_REG_UART_HALT_TX_Msk (0x1UL) /*!< UART_HALT_TX (Bitfield-Mask: 0x01) */ +/* =================================================== UART_IER_DLH_REG ==================================================== */ +#define UART_UART_IER_DLH_REG_PTIME_DLH7_Pos (7UL) /*!< PTIME_DLH7 (Bit 7) */ +#define UART_UART_IER_DLH_REG_PTIME_DLH7_Msk (0x80UL) /*!< PTIME_DLH7 (Bitfield-Mask: 0x01) */ +#define UART_UART_IER_DLH_REG_DLH6_5_Pos (5UL) /*!< DLH6_5 (Bit 5) */ +#define UART_UART_IER_DLH_REG_DLH6_5_Msk (0x60UL) /*!< DLH6_5 (Bitfield-Mask: 0x03) */ +#define UART_UART_IER_DLH_REG_ELCOLR_DLH4_Pos (4UL) /*!< ELCOLR_DLH4 (Bit 4) */ +#define UART_UART_IER_DLH_REG_ELCOLR_DLH4_Msk (0x10UL) /*!< ELCOLR_DLH4 (Bitfield-Mask: 0x01) */ +#define UART_UART_IER_DLH_REG_EDSSI_DLH3_Pos (3UL) /*!< EDSSI_DLH3 (Bit 3) */ +#define UART_UART_IER_DLH_REG_EDSSI_DLH3_Msk (0x8UL) /*!< EDSSI_DLH3 (Bitfield-Mask: 0x01) */ +#define UART_UART_IER_DLH_REG_ELSI_DLH2_Pos (2UL) /*!< ELSI_DLH2 (Bit 2) */ +#define UART_UART_IER_DLH_REG_ELSI_DLH2_Msk (0x4UL) /*!< ELSI_DLH2 (Bitfield-Mask: 0x01) */ +#define UART_UART_IER_DLH_REG_ETBEI_DLH1_Pos (1UL) /*!< ETBEI_DLH1 (Bit 1) */ +#define UART_UART_IER_DLH_REG_ETBEI_DLH1_Msk (0x2UL) /*!< ETBEI_DLH1 (Bitfield-Mask: 0x01) */ +#define UART_UART_IER_DLH_REG_ERBFI_DLH0_Pos (0UL) /*!< ERBFI_DLH0 (Bit 0) */ +#define UART_UART_IER_DLH_REG_ERBFI_DLH0_Msk (0x1UL) /*!< ERBFI_DLH0 (Bitfield-Mask: 0x01) */ +/* =================================================== UART_IIR_FCR_REG ==================================================== */ +#define UART_UART_IIR_FCR_REG_IIR_FCR_Pos (0UL) /*!< IIR_FCR (Bit 0) */ +#define UART_UART_IIR_FCR_REG_IIR_FCR_Msk (0xffUL) /*!< IIR_FCR (Bitfield-Mask: 0xff) */ +/* ===================================================== UART_LCR_REG ====================================================== */ +#define UART_UART_LCR_REG_UART_DLAB_Pos (7UL) /*!< UART_DLAB (Bit 7) */ +#define UART_UART_LCR_REG_UART_DLAB_Msk (0x80UL) /*!< UART_DLAB (Bitfield-Mask: 0x01) */ +#define UART_UART_LCR_REG_UART_BC_Pos (6UL) /*!< UART_BC (Bit 6) */ +#define UART_UART_LCR_REG_UART_BC_Msk (0x40UL) /*!< UART_BC (Bitfield-Mask: 0x01) */ +#define UART_UART_LCR_REG_UART_EPS_Pos (4UL) /*!< UART_EPS (Bit 4) */ +#define UART_UART_LCR_REG_UART_EPS_Msk (0x10UL) /*!< UART_EPS (Bitfield-Mask: 0x01) */ +#define UART_UART_LCR_REG_UART_PEN_Pos (3UL) /*!< UART_PEN (Bit 3) */ +#define UART_UART_LCR_REG_UART_PEN_Msk (0x8UL) /*!< UART_PEN (Bitfield-Mask: 0x01) */ +#define UART_UART_LCR_REG_UART_STOP_Pos (2UL) /*!< UART_STOP (Bit 2) */ +#define UART_UART_LCR_REG_UART_STOP_Msk (0x4UL) /*!< UART_STOP (Bitfield-Mask: 0x01) */ +#define UART_UART_LCR_REG_UART_DLS_Pos (0UL) /*!< UART_DLS (Bit 0) */ +#define UART_UART_LCR_REG_UART_DLS_Msk (0x3UL) /*!< UART_DLS (Bitfield-Mask: 0x03) */ +/* ===================================================== UART_LSR_REG ====================================================== */ +#define UART_UART_LSR_REG_UART_RFE_Pos (7UL) /*!< UART_RFE (Bit 7) */ +#define UART_UART_LSR_REG_UART_RFE_Msk (0x80UL) /*!< UART_RFE (Bitfield-Mask: 0x01) */ +#define UART_UART_LSR_REG_UART_TEMT_Pos (6UL) /*!< UART_TEMT (Bit 6) */ +#define UART_UART_LSR_REG_UART_TEMT_Msk (0x40UL) /*!< UART_TEMT (Bitfield-Mask: 0x01) */ +#define UART_UART_LSR_REG_UART_THRE_Pos (5UL) /*!< UART_THRE (Bit 5) */ +#define UART_UART_LSR_REG_UART_THRE_Msk (0x20UL) /*!< UART_THRE (Bitfield-Mask: 0x01) */ +#define UART_UART_LSR_REG_UART_BI_Pos (4UL) /*!< UART_BI (Bit 4) */ +#define UART_UART_LSR_REG_UART_BI_Msk (0x10UL) /*!< UART_BI (Bitfield-Mask: 0x01) */ +#define UART_UART_LSR_REG_UART_FE_Pos (3UL) /*!< UART_FE (Bit 3) */ +#define UART_UART_LSR_REG_UART_FE_Msk (0x8UL) /*!< UART_FE (Bitfield-Mask: 0x01) */ +#define UART_UART_LSR_REG_UART_PE_Pos (2UL) /*!< UART_PE (Bit 2) */ +#define UART_UART_LSR_REG_UART_PE_Msk (0x4UL) /*!< UART_PE (Bitfield-Mask: 0x01) */ +#define UART_UART_LSR_REG_UART_OE_Pos (1UL) /*!< UART_OE (Bit 1) */ +#define UART_UART_LSR_REG_UART_OE_Msk (0x2UL) /*!< UART_OE (Bitfield-Mask: 0x01) */ +#define UART_UART_LSR_REG_UART_DR_Pos (0UL) /*!< UART_DR (Bit 0) */ +#define UART_UART_LSR_REG_UART_DR_Msk (0x1UL) /*!< UART_DR (Bitfield-Mask: 0x01) */ +/* ===================================================== UART_MCR_REG ====================================================== */ +#define UART_UART_MCR_REG_UART_LB_Pos (4UL) /*!< UART_LB (Bit 4) */ +#define UART_UART_MCR_REG_UART_LB_Msk (0x10UL) /*!< UART_LB (Bitfield-Mask: 0x01) */ +/* ================================================= UART_RBR_THR_DLL_REG ================================================== */ +#define UART_UART_RBR_THR_DLL_REG_RBR_THR_DLL_Pos (0UL) /*!< RBR_THR_DLL (Bit 0) */ +#define UART_UART_RBR_THR_DLL_REG_RBR_THR_DLL_Msk (0xffUL) /*!< RBR_THR_DLL (Bitfield-Mask: 0xff) */ +/* ===================================================== UART_RFL_REG ====================================================== */ +#define UART_UART_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Pos (0UL) /*!< UART_RECEIVE_FIFO_LEVEL (Bit 0) */ +#define UART_UART_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Msk (0x1fUL) /*!< UART_RECEIVE_FIFO_LEVEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== UART_SBCR_REG ===================================================== */ +#define UART_UART_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Pos (0UL) /*!< UART_SHADOW_BREAK_CONTROL (Bit 0) */ +#define UART_UART_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Msk (0x1UL) /*!< UART_SHADOW_BREAK_CONTROL (Bitfield-Mask: 0x01) */ +/* ===================================================== UART_SCR_REG ====================================================== */ +#define UART_UART_SCR_REG_UART_SCRATCH_PAD_Pos (0UL) /*!< UART_SCRATCH_PAD (Bit 0) */ +#define UART_UART_SCR_REG_UART_SCRATCH_PAD_Msk (0xffUL) /*!< UART_SCRATCH_PAD (Bitfield-Mask: 0xff) */ +/* ==================================================== UART_SDMAM_REG ===================================================== */ +#define UART_UART_SDMAM_REG_UART_SHADOW_DMA_MODE_Pos (0UL) /*!< UART_SHADOW_DMA_MODE (Bit 0) */ +#define UART_UART_SDMAM_REG_UART_SHADOW_DMA_MODE_Msk (0x1UL) /*!< UART_SHADOW_DMA_MODE (Bitfield-Mask: 0x01) */ +/* ===================================================== UART_SFE_REG ====================================================== */ +#define UART_UART_SFE_REG_UART_SHADOW_FIFO_ENABLE_Pos (0UL) /*!< UART_SHADOW_FIFO_ENABLE (Bit 0) */ +#define UART_UART_SFE_REG_UART_SHADOW_FIFO_ENABLE_Msk (0x1UL) /*!< UART_SHADOW_FIFO_ENABLE (Bitfield-Mask: 0x01) */ +/* ================================================== UART_SRBR_STHR0_REG ================================================== */ +#define UART_UART_SRBR_STHR0_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART_UART_SRBR_STHR0_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART_SRBR_STHR10_REG ================================================== */ +#define UART_UART_SRBR_STHR10_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART_UART_SRBR_STHR10_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART_SRBR_STHR11_REG ================================================== */ +#define UART_UART_SRBR_STHR11_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART_UART_SRBR_STHR11_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART_SRBR_STHR12_REG ================================================== */ +#define UART_UART_SRBR_STHR12_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART_UART_SRBR_STHR12_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART_SRBR_STHR13_REG ================================================== */ +#define UART_UART_SRBR_STHR13_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART_UART_SRBR_STHR13_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART_SRBR_STHR14_REG ================================================== */ +#define UART_UART_SRBR_STHR14_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART_UART_SRBR_STHR14_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART_SRBR_STHR15_REG ================================================== */ +#define UART_UART_SRBR_STHR15_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART_UART_SRBR_STHR15_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================== UART_SRBR_STHR1_REG ================================================== */ +#define UART_UART_SRBR_STHR1_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART_UART_SRBR_STHR1_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================== UART_SRBR_STHR2_REG ================================================== */ +#define UART_UART_SRBR_STHR2_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART_UART_SRBR_STHR2_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================== UART_SRBR_STHR3_REG ================================================== */ +#define UART_UART_SRBR_STHR3_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART_UART_SRBR_STHR3_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================== UART_SRBR_STHR4_REG ================================================== */ +#define UART_UART_SRBR_STHR4_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART_UART_SRBR_STHR4_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================== UART_SRBR_STHR5_REG ================================================== */ +#define UART_UART_SRBR_STHR5_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART_UART_SRBR_STHR5_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================== UART_SRBR_STHR6_REG ================================================== */ +#define UART_UART_SRBR_STHR6_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART_UART_SRBR_STHR6_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================== UART_SRBR_STHR7_REG ================================================== */ +#define UART_UART_SRBR_STHR7_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART_UART_SRBR_STHR7_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================== UART_SRBR_STHR8_REG ================================================== */ +#define UART_UART_SRBR_STHR8_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART_UART_SRBR_STHR8_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================== UART_SRBR_STHR9_REG ================================================== */ +#define UART_UART_SRBR_STHR9_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART_UART_SRBR_STHR9_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ===================================================== UART_SRR_REG ====================================================== */ +#define UART_UART_SRR_REG_UART_XFR_Pos (2UL) /*!< UART_XFR (Bit 2) */ +#define UART_UART_SRR_REG_UART_XFR_Msk (0x4UL) /*!< UART_XFR (Bitfield-Mask: 0x01) */ +#define UART_UART_SRR_REG_UART_RFR_Pos (1UL) /*!< UART_RFR (Bit 1) */ +#define UART_UART_SRR_REG_UART_RFR_Msk (0x2UL) /*!< UART_RFR (Bitfield-Mask: 0x01) */ +#define UART_UART_SRR_REG_UART_UR_Pos (0UL) /*!< UART_UR (Bit 0) */ +#define UART_UART_SRR_REG_UART_UR_Msk (0x1UL) /*!< UART_UR (Bitfield-Mask: 0x01) */ +/* ===================================================== UART_SRT_REG ====================================================== */ +#define UART_UART_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Pos (0UL) /*!< UART_SHADOW_RCVR_TRIGGER (Bit 0) */ +#define UART_UART_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Msk (0x3UL) /*!< UART_SHADOW_RCVR_TRIGGER (Bitfield-Mask: 0x03) */ +/* ===================================================== UART_STET_REG ===================================================== */ +#define UART_UART_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Pos (0UL) /*!< UART_SHADOW_TX_EMPTY_TRIGGER (Bit 0) */ +#define UART_UART_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Msk (0x3UL) /*!< UART_SHADOW_TX_EMPTY_TRIGGER (Bitfield-Mask: 0x03) */ +/* ===================================================== UART_TFL_REG ====================================================== */ +#define UART_UART_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Pos (0UL) /*!< UART_TRANSMIT_FIFO_LEVEL (Bit 0) */ +#define UART_UART_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Msk (0x1fUL) /*!< UART_TRANSMIT_FIFO_LEVEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== UART_UCV_REG ====================================================== */ +#define UART_UART_UCV_REG_UART_UCV_Pos (0UL) /*!< UART_UCV (Bit 0) */ +#define UART_UART_UCV_REG_UART_UCV_Msk (0xffffffffUL) /*!< UART_UCV (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== UART_USR_REG ====================================================== */ +#define UART_UART_USR_REG_UART_RFF_Pos (4UL) /*!< UART_RFF (Bit 4) */ +#define UART_UART_USR_REG_UART_RFF_Msk (0x10UL) /*!< UART_RFF (Bitfield-Mask: 0x01) */ +#define UART_UART_USR_REG_UART_RFNE_Pos (3UL) /*!< UART_RFNE (Bit 3) */ +#define UART_UART_USR_REG_UART_RFNE_Msk (0x8UL) /*!< UART_RFNE (Bitfield-Mask: 0x01) */ +#define UART_UART_USR_REG_UART_TFE_Pos (2UL) /*!< UART_TFE (Bit 2) */ +#define UART_UART_USR_REG_UART_TFE_Msk (0x4UL) /*!< UART_TFE (Bitfield-Mask: 0x01) */ +#define UART_UART_USR_REG_UART_TFNF_Pos (1UL) /*!< UART_TFNF (Bit 1) */ +#define UART_UART_USR_REG_UART_TFNF_Msk (0x2UL) /*!< UART_TFNF (Bitfield-Mask: 0x01) */ +#define UART_UART_USR_REG_UART_BUSY_Pos (0UL) /*!< UART_BUSY (Bit 0) */ +#define UART_UART_USR_REG_UART_BUSY_Msk (0x1UL) /*!< UART_BUSY (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ UART2 ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== UART2_CTR_REG ===================================================== */ +#define UART2_UART2_CTR_REG_UART_CTR_Pos (0UL) /*!< UART_CTR (Bit 0) */ +#define UART2_UART2_CTR_REG_UART_CTR_Msk (0xffffffffUL) /*!< UART_CTR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== UART2_DLF_REG ===================================================== */ +#define UART2_UART2_DLF_REG_UART_DLF_Pos (0UL) /*!< UART_DLF (Bit 0) */ +#define UART2_UART2_DLF_REG_UART_DLF_Msk (0xfUL) /*!< UART_DLF (Bitfield-Mask: 0x0f) */ +/* ==================================================== UART2_DMASA_REG ==================================================== */ +#define UART2_UART2_DMASA_REG_UART_DMASA_Pos (0UL) /*!< UART_DMASA (Bit 0) */ +#define UART2_UART2_DMASA_REG_UART_DMASA_Msk (0x1UL) /*!< UART_DMASA (Bitfield-Mask: 0x01) */ +/* ===================================================== UART2_HTX_REG ===================================================== */ +#define UART2_UART2_HTX_REG_UART_HALT_TX_Pos (0UL) /*!< UART_HALT_TX (Bit 0) */ +#define UART2_UART2_HTX_REG_UART_HALT_TX_Msk (0x1UL) /*!< UART_HALT_TX (Bitfield-Mask: 0x01) */ +/* =================================================== UART2_IER_DLH_REG =================================================== */ +#define UART2_UART2_IER_DLH_REG_PTIME_DLH7_Pos (7UL) /*!< PTIME_DLH7 (Bit 7) */ +#define UART2_UART2_IER_DLH_REG_PTIME_DLH7_Msk (0x80UL) /*!< PTIME_DLH7 (Bitfield-Mask: 0x01) */ +#define UART2_UART2_IER_DLH_REG_DLH6_5_Pos (5UL) /*!< DLH6_5 (Bit 5) */ +#define UART2_UART2_IER_DLH_REG_DLH6_5_Msk (0x60UL) /*!< DLH6_5 (Bitfield-Mask: 0x03) */ +#define UART2_UART2_IER_DLH_REG_ELCOLR_DLH4_Pos (4UL) /*!< ELCOLR_DLH4 (Bit 4) */ +#define UART2_UART2_IER_DLH_REG_ELCOLR_DLH4_Msk (0x10UL) /*!< ELCOLR_DLH4 (Bitfield-Mask: 0x01) */ +#define UART2_UART2_IER_DLH_REG_EDSSI_DLH3_Pos (3UL) /*!< EDSSI_DLH3 (Bit 3) */ +#define UART2_UART2_IER_DLH_REG_EDSSI_DLH3_Msk (0x8UL) /*!< EDSSI_DLH3 (Bitfield-Mask: 0x01) */ +#define UART2_UART2_IER_DLH_REG_ELSI_DLH2_Pos (2UL) /*!< ELSI_DLH2 (Bit 2) */ +#define UART2_UART2_IER_DLH_REG_ELSI_DLH2_Msk (0x4UL) /*!< ELSI_DLH2 (Bitfield-Mask: 0x01) */ +#define UART2_UART2_IER_DLH_REG_ETBEI_DLH1_Pos (1UL) /*!< ETBEI_DLH1 (Bit 1) */ +#define UART2_UART2_IER_DLH_REG_ETBEI_DLH1_Msk (0x2UL) /*!< ETBEI_DLH1 (Bitfield-Mask: 0x01) */ +#define UART2_UART2_IER_DLH_REG_ERBFI_DLH0_Pos (0UL) /*!< ERBFI_DLH0 (Bit 0) */ +#define UART2_UART2_IER_DLH_REG_ERBFI_DLH0_Msk (0x1UL) /*!< ERBFI_DLH0 (Bitfield-Mask: 0x01) */ +/* =================================================== UART2_IIR_FCR_REG =================================================== */ +#define UART2_UART2_IIR_FCR_REG_IIR_FCR_Pos (0UL) /*!< IIR_FCR (Bit 0) */ +#define UART2_UART2_IIR_FCR_REG_IIR_FCR_Msk (0xffUL) /*!< IIR_FCR (Bitfield-Mask: 0xff) */ +/* ===================================================== UART2_LCR_EXT ===================================================== */ +#define UART2_UART2_LCR_EXT_UART_TRANSMIT_MODE_Pos (3UL) /*!< UART_TRANSMIT_MODE (Bit 3) */ +#define UART2_UART2_LCR_EXT_UART_TRANSMIT_MODE_Msk (0x8UL) /*!< UART_TRANSMIT_MODE (Bitfield-Mask: 0x01) */ +#define UART2_UART2_LCR_EXT_UART_SEND_ADDR_Pos (2UL) /*!< UART_SEND_ADDR (Bit 2) */ +#define UART2_UART2_LCR_EXT_UART_SEND_ADDR_Msk (0x4UL) /*!< UART_SEND_ADDR (Bitfield-Mask: 0x01) */ +#define UART2_UART2_LCR_EXT_UART_ADDR_MATCH_Pos (1UL) /*!< UART_ADDR_MATCH (Bit 1) */ +#define UART2_UART2_LCR_EXT_UART_ADDR_MATCH_Msk (0x2UL) /*!< UART_ADDR_MATCH (Bitfield-Mask: 0x01) */ +#define UART2_UART2_LCR_EXT_UART_DLS_E_Pos (0UL) /*!< UART_DLS_E (Bit 0) */ +#define UART2_UART2_LCR_EXT_UART_DLS_E_Msk (0x1UL) /*!< UART_DLS_E (Bitfield-Mask: 0x01) */ +/* ===================================================== UART2_LCR_REG ===================================================== */ +#define UART2_UART2_LCR_REG_UART_DLAB_Pos (7UL) /*!< UART_DLAB (Bit 7) */ +#define UART2_UART2_LCR_REG_UART_DLAB_Msk (0x80UL) /*!< UART_DLAB (Bitfield-Mask: 0x01) */ +#define UART2_UART2_LCR_REG_UART_BC_Pos (6UL) /*!< UART_BC (Bit 6) */ +#define UART2_UART2_LCR_REG_UART_BC_Msk (0x40UL) /*!< UART_BC (Bitfield-Mask: 0x01) */ +#define UART2_UART2_LCR_REG_UART_SP_Pos (5UL) /*!< UART_SP (Bit 5) */ +#define UART2_UART2_LCR_REG_UART_SP_Msk (0x20UL) /*!< UART_SP (Bitfield-Mask: 0x01) */ +#define UART2_UART2_LCR_REG_UART_EPS_Pos (4UL) /*!< UART_EPS (Bit 4) */ +#define UART2_UART2_LCR_REG_UART_EPS_Msk (0x10UL) /*!< UART_EPS (Bitfield-Mask: 0x01) */ +#define UART2_UART2_LCR_REG_UART_PEN_Pos (3UL) /*!< UART_PEN (Bit 3) */ +#define UART2_UART2_LCR_REG_UART_PEN_Msk (0x8UL) /*!< UART_PEN (Bitfield-Mask: 0x01) */ +#define UART2_UART2_LCR_REG_UART_STOP_Pos (2UL) /*!< UART_STOP (Bit 2) */ +#define UART2_UART2_LCR_REG_UART_STOP_Msk (0x4UL) /*!< UART_STOP (Bitfield-Mask: 0x01) */ +#define UART2_UART2_LCR_REG_UART_DLS_Pos (0UL) /*!< UART_DLS (Bit 0) */ +#define UART2_UART2_LCR_REG_UART_DLS_Msk (0x3UL) /*!< UART_DLS (Bitfield-Mask: 0x03) */ +/* ===================================================== UART2_LSR_REG ===================================================== */ +#define UART2_UART2_LSR_REG_UART_ADDR_RCVD_Pos (8UL) /*!< UART_ADDR_RCVD (Bit 8) */ +#define UART2_UART2_LSR_REG_UART_ADDR_RCVD_Msk (0x100UL) /*!< UART_ADDR_RCVD (Bitfield-Mask: 0x01) */ +#define UART2_UART2_LSR_REG_UART_RFE_Pos (7UL) /*!< UART_RFE (Bit 7) */ +#define UART2_UART2_LSR_REG_UART_RFE_Msk (0x80UL) /*!< UART_RFE (Bitfield-Mask: 0x01) */ +#define UART2_UART2_LSR_REG_UART_TEMT_Pos (6UL) /*!< UART_TEMT (Bit 6) */ +#define UART2_UART2_LSR_REG_UART_TEMT_Msk (0x40UL) /*!< UART_TEMT (Bitfield-Mask: 0x01) */ +#define UART2_UART2_LSR_REG_UART_THRE_Pos (5UL) /*!< UART_THRE (Bit 5) */ +#define UART2_UART2_LSR_REG_UART_THRE_Msk (0x20UL) /*!< UART_THRE (Bitfield-Mask: 0x01) */ +#define UART2_UART2_LSR_REG_UART_BI_Pos (4UL) /*!< UART_BI (Bit 4) */ +#define UART2_UART2_LSR_REG_UART_BI_Msk (0x10UL) /*!< UART_BI (Bitfield-Mask: 0x01) */ +#define UART2_UART2_LSR_REG_UART_FE_Pos (3UL) /*!< UART_FE (Bit 3) */ +#define UART2_UART2_LSR_REG_UART_FE_Msk (0x8UL) /*!< UART_FE (Bitfield-Mask: 0x01) */ +#define UART2_UART2_LSR_REG_UART_PE_Pos (2UL) /*!< UART_PE (Bit 2) */ +#define UART2_UART2_LSR_REG_UART_PE_Msk (0x4UL) /*!< UART_PE (Bitfield-Mask: 0x01) */ +#define UART2_UART2_LSR_REG_UART_OE_Pos (1UL) /*!< UART_OE (Bit 1) */ +#define UART2_UART2_LSR_REG_UART_OE_Msk (0x2UL) /*!< UART_OE (Bitfield-Mask: 0x01) */ +#define UART2_UART2_LSR_REG_UART_DR_Pos (0UL) /*!< UART_DR (Bit 0) */ +#define UART2_UART2_LSR_REG_UART_DR_Msk (0x1UL) /*!< UART_DR (Bitfield-Mask: 0x01) */ +/* ===================================================== UART2_MCR_REG ===================================================== */ +#define UART2_UART2_MCR_REG_UART_AFCE_Pos (5UL) /*!< UART_AFCE (Bit 5) */ +#define UART2_UART2_MCR_REG_UART_AFCE_Msk (0x20UL) /*!< UART_AFCE (Bitfield-Mask: 0x01) */ +#define UART2_UART2_MCR_REG_UART_LB_Pos (4UL) /*!< UART_LB (Bit 4) */ +#define UART2_UART2_MCR_REG_UART_LB_Msk (0x10UL) /*!< UART_LB (Bitfield-Mask: 0x01) */ +#define UART2_UART2_MCR_REG_UART_RTS_Pos (1UL) /*!< UART_RTS (Bit 1) */ +#define UART2_UART2_MCR_REG_UART_RTS_Msk (0x2UL) /*!< UART_RTS (Bitfield-Mask: 0x01) */ +/* ===================================================== UART2_MSR_REG ===================================================== */ +#define UART2_UART2_MSR_REG_UART_CTS_Pos (4UL) /*!< UART_CTS (Bit 4) */ +#define UART2_UART2_MSR_REG_UART_CTS_Msk (0x10UL) /*!< UART_CTS (Bitfield-Mask: 0x01) */ +#define UART2_UART2_MSR_REG_UART_DCTS_Pos (0UL) /*!< UART_DCTS (Bit 0) */ +#define UART2_UART2_MSR_REG_UART_DCTS_Msk (0x1UL) /*!< UART_DCTS (Bitfield-Mask: 0x01) */ +/* ===================================================== UART2_RAR_REG ===================================================== */ +#define UART2_UART2_RAR_REG_UART_RAR_Pos (0UL) /*!< UART_RAR (Bit 0) */ +#define UART2_UART2_RAR_REG_UART_RAR_Msk (0xffUL) /*!< UART_RAR (Bitfield-Mask: 0xff) */ +/* ================================================= UART2_RBR_THR_DLL_REG ================================================= */ +#define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_9BIT_Pos (8UL) /*!< RBR_THR_9BIT (Bit 8) */ +#define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_9BIT_Msk (0x100UL) /*!< RBR_THR_9BIT (Bitfield-Mask: 0x01) */ +#define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_DLL_Pos (0UL) /*!< RBR_THR_DLL (Bit 0) */ +#define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_DLL_Msk (0xffUL) /*!< RBR_THR_DLL (Bitfield-Mask: 0xff) */ +/* ===================================================== UART2_RFL_REG ===================================================== */ +#define UART2_UART2_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Pos (0UL) /*!< UART_RECEIVE_FIFO_LEVEL (Bit 0) */ +#define UART2_UART2_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Msk (0x1fUL) /*!< UART_RECEIVE_FIFO_LEVEL (Bitfield-Mask: 0x1f) */ +/* ==================================================== UART2_SBCR_REG ===================================================== */ +#define UART2_UART2_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Pos (0UL) /*!< UART_SHADOW_BREAK_CONTROL (Bit 0) */ +#define UART2_UART2_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Msk (0x1UL) /*!< UART_SHADOW_BREAK_CONTROL (Bitfield-Mask: 0x01) */ +/* ===================================================== UART2_SCR_REG ===================================================== */ +#define UART2_UART2_SCR_REG_UART_SCRATCH_PAD_Pos (0UL) /*!< UART_SCRATCH_PAD (Bit 0) */ +#define UART2_UART2_SCR_REG_UART_SCRATCH_PAD_Msk (0xffUL) /*!< UART_SCRATCH_PAD (Bitfield-Mask: 0xff) */ +/* ==================================================== UART2_SDMAM_REG ==================================================== */ +#define UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Pos (0UL) /*!< UART_SHADOW_DMA_MODE (Bit 0) */ +#define UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Msk (0x1UL) /*!< UART_SHADOW_DMA_MODE (Bitfield-Mask: 0x01) */ +/* ===================================================== UART2_SFE_REG ===================================================== */ +#define UART2_UART2_SFE_REG_UART_SHADOW_FIFO_ENABLE_Pos (0UL) /*!< UART_SHADOW_FIFO_ENABLE (Bit 0) */ +#define UART2_UART2_SFE_REG_UART_SHADOW_FIFO_ENABLE_Msk (0x1UL) /*!< UART_SHADOW_FIFO_ENABLE (Bitfield-Mask: 0x01) */ +/* ================================================= UART2_SRBR_STHR0_REG ================================================== */ +#define UART2_UART2_SRBR_STHR0_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART2_UART2_SRBR_STHR0_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART2_SRBR_STHR10_REG ================================================= */ +#define UART2_UART2_SRBR_STHR10_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART2_UART2_SRBR_STHR10_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART2_SRBR_STHR11_REG ================================================= */ +#define UART2_UART2_SRBR_STHR11_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART2_UART2_SRBR_STHR11_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART2_SRBR_STHR12_REG ================================================= */ +#define UART2_UART2_SRBR_STHR12_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART2_UART2_SRBR_STHR12_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART2_SRBR_STHR13_REG ================================================= */ +#define UART2_UART2_SRBR_STHR13_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART2_UART2_SRBR_STHR13_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART2_SRBR_STHR14_REG ================================================= */ +#define UART2_UART2_SRBR_STHR14_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART2_UART2_SRBR_STHR14_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART2_SRBR_STHR15_REG ================================================= */ +#define UART2_UART2_SRBR_STHR15_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART2_UART2_SRBR_STHR15_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART2_SRBR_STHR1_REG ================================================== */ +#define UART2_UART2_SRBR_STHR1_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART2_UART2_SRBR_STHR1_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART2_SRBR_STHR2_REG ================================================== */ +#define UART2_UART2_SRBR_STHR2_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART2_UART2_SRBR_STHR2_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART2_SRBR_STHR3_REG ================================================== */ +#define UART2_UART2_SRBR_STHR3_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART2_UART2_SRBR_STHR3_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART2_SRBR_STHR4_REG ================================================== */ +#define UART2_UART2_SRBR_STHR4_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART2_UART2_SRBR_STHR4_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART2_SRBR_STHR5_REG ================================================== */ +#define UART2_UART2_SRBR_STHR5_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART2_UART2_SRBR_STHR5_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART2_SRBR_STHR6_REG ================================================== */ +#define UART2_UART2_SRBR_STHR6_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART2_UART2_SRBR_STHR6_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART2_SRBR_STHR7_REG ================================================== */ +#define UART2_UART2_SRBR_STHR7_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART2_UART2_SRBR_STHR7_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART2_SRBR_STHR8_REG ================================================== */ +#define UART2_UART2_SRBR_STHR8_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART2_UART2_SRBR_STHR8_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART2_SRBR_STHR9_REG ================================================== */ +#define UART2_UART2_SRBR_STHR9_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART2_UART2_SRBR_STHR9_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ===================================================== UART2_SRR_REG ===================================================== */ +#define UART2_UART2_SRR_REG_UART_XFR_Pos (2UL) /*!< UART_XFR (Bit 2) */ +#define UART2_UART2_SRR_REG_UART_XFR_Msk (0x4UL) /*!< UART_XFR (Bitfield-Mask: 0x01) */ +#define UART2_UART2_SRR_REG_UART_RFR_Pos (1UL) /*!< UART_RFR (Bit 1) */ +#define UART2_UART2_SRR_REG_UART_RFR_Msk (0x2UL) /*!< UART_RFR (Bitfield-Mask: 0x01) */ +#define UART2_UART2_SRR_REG_UART_UR_Pos (0UL) /*!< UART_UR (Bit 0) */ +#define UART2_UART2_SRR_REG_UART_UR_Msk (0x1UL) /*!< UART_UR (Bitfield-Mask: 0x01) */ +/* ==================================================== UART2_SRTS_REG ===================================================== */ +#define UART2_UART2_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Pos (0UL) /*!< UART_SHADOW_REQUEST_TO_SEND (Bit 0) */ +#define UART2_UART2_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Msk (0x1UL) /*!< UART_SHADOW_REQUEST_TO_SEND (Bitfield-Mask: 0x01) */ +/* ===================================================== UART2_SRT_REG ===================================================== */ +#define UART2_UART2_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Pos (0UL) /*!< UART_SHADOW_RCVR_TRIGGER (Bit 0) */ +#define UART2_UART2_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Msk (0x3UL) /*!< UART_SHADOW_RCVR_TRIGGER (Bitfield-Mask: 0x03) */ +/* ==================================================== UART2_STET_REG ===================================================== */ +#define UART2_UART2_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Pos (0UL) /*!< UART_SHADOW_TX_EMPTY_TRIGGER (Bit 0) */ +#define UART2_UART2_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Msk (0x3UL) /*!< UART_SHADOW_TX_EMPTY_TRIGGER (Bitfield-Mask: 0x03) */ +/* ===================================================== UART2_TAR_REG ===================================================== */ +#define UART2_UART2_TAR_REG_UART_TAR_Pos (0UL) /*!< UART_TAR (Bit 0) */ +#define UART2_UART2_TAR_REG_UART_TAR_Msk (0xffUL) /*!< UART_TAR (Bitfield-Mask: 0xff) */ +/* ===================================================== UART2_TFL_REG ===================================================== */ +#define UART2_UART2_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Pos (0UL) /*!< UART_TRANSMIT_FIFO_LEVEL (Bit 0) */ +#define UART2_UART2_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Msk (0x1fUL) /*!< UART_TRANSMIT_FIFO_LEVEL (Bitfield-Mask: 0x1f) */ +/* ===================================================== UART2_UCV_REG ===================================================== */ +#define UART2_UART2_UCV_REG_UART_UCV_Pos (0UL) /*!< UART_UCV (Bit 0) */ +#define UART2_UART2_UCV_REG_UART_UCV_Msk (0xffffffffUL) /*!< UART_UCV (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== UART2_USR_REG ===================================================== */ +#define UART2_UART2_USR_REG_UART_RFF_Pos (4UL) /*!< UART_RFF (Bit 4) */ +#define UART2_UART2_USR_REG_UART_RFF_Msk (0x10UL) /*!< UART_RFF (Bitfield-Mask: 0x01) */ +#define UART2_UART2_USR_REG_UART_RFNE_Pos (3UL) /*!< UART_RFNE (Bit 3) */ +#define UART2_UART2_USR_REG_UART_RFNE_Msk (0x8UL) /*!< UART_RFNE (Bitfield-Mask: 0x01) */ +#define UART2_UART2_USR_REG_UART_TFE_Pos (2UL) /*!< UART_TFE (Bit 2) */ +#define UART2_UART2_USR_REG_UART_TFE_Msk (0x4UL) /*!< UART_TFE (Bitfield-Mask: 0x01) */ +#define UART2_UART2_USR_REG_UART_TFNF_Pos (1UL) /*!< UART_TFNF (Bit 1) */ +#define UART2_UART2_USR_REG_UART_TFNF_Msk (0x2UL) /*!< UART_TFNF (Bitfield-Mask: 0x01) */ +#define UART2_UART2_USR_REG_UART_BUSY_Pos (0UL) /*!< UART_BUSY (Bit 0) */ +#define UART2_UART2_USR_REG_UART_BUSY_Msk (0x1UL) /*!< UART_BUSY (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ UART3 ================ */ +/* =========================================================================================================================== */ + +/* =================================================== UART3_CONFIG_REG ==================================================== */ +#define UART3_UART3_CONFIG_REG_ISO7816_SCRATCH_PAD_Pos (3UL) /*!< ISO7816_SCRATCH_PAD (Bit 3) */ +#define UART3_UART3_CONFIG_REG_ISO7816_SCRATCH_PAD_Msk (0xf8UL) /*!< ISO7816_SCRATCH_PAD (Bitfield-Mask: 0x1f) */ +#define UART3_UART3_CONFIG_REG_ISO7816_ENABLE_Pos (2UL) /*!< ISO7816_ENABLE (Bit 2) */ +#define UART3_UART3_CONFIG_REG_ISO7816_ENABLE_Msk (0x4UL) /*!< ISO7816_ENABLE (Bitfield-Mask: 0x01) */ +#define UART3_UART3_CONFIG_REG_ISO7816_ERR_SIG_EN_Pos (1UL) /*!< ISO7816_ERR_SIG_EN (Bit 1) */ +#define UART3_UART3_CONFIG_REG_ISO7816_ERR_SIG_EN_Msk (0x2UL) /*!< ISO7816_ERR_SIG_EN (Bitfield-Mask: 0x01) */ +#define UART3_UART3_CONFIG_REG_ISO7816_CONVENTION_Pos (0UL) /*!< ISO7816_CONVENTION (Bit 0) */ +#define UART3_UART3_CONFIG_REG_ISO7816_CONVENTION_Msk (0x1UL) /*!< ISO7816_CONVENTION (Bitfield-Mask: 0x01) */ +/* ==================================================== UART3_CTRL_REG ===================================================== */ +#define UART3_UART3_CTRL_REG_ISO7816_AUTO_GT_Pos (11UL) /*!< ISO7816_AUTO_GT (Bit 11) */ +#define UART3_UART3_CTRL_REG_ISO7816_AUTO_GT_Msk (0x800UL) /*!< ISO7816_AUTO_GT (Bitfield-Mask: 0x01) */ +#define UART3_UART3_CTRL_REG_ISO7816_ERR_TX_VALUE_IRQMASK_Pos (10UL) /*!< ISO7816_ERR_TX_VALUE_IRQMASK (Bit 10) */ +#define UART3_UART3_CTRL_REG_ISO7816_ERR_TX_VALUE_IRQMASK_Msk (0x400UL) /*!< ISO7816_ERR_TX_VALUE_IRQMASK (Bitfield-Mask: 0x01) */ +#define UART3_UART3_CTRL_REG_ISO7816_ERR_TX_TIME_IRQMASK_Pos (9UL) /*!< ISO7816_ERR_TX_TIME_IRQMASK (Bit 9) */ +#define UART3_UART3_CTRL_REG_ISO7816_ERR_TX_TIME_IRQMASK_Msk (0x200UL) /*!< ISO7816_ERR_TX_TIME_IRQMASK (Bitfield-Mask: 0x01) */ +#define UART3_UART3_CTRL_REG_ISO7816_TIM_EXPIRED_IRQMASK_Pos (8UL) /*!< ISO7816_TIM_EXPIRED_IRQMASK (Bit 8) */ +#define UART3_UART3_CTRL_REG_ISO7816_TIM_EXPIRED_IRQMASK_Msk (0x100UL) /*!< ISO7816_TIM_EXPIRED_IRQMASK (Bitfield-Mask: 0x01) */ +#define UART3_UART3_CTRL_REG_ISO7816_CLK_STATUS_Pos (7UL) /*!< ISO7816_CLK_STATUS (Bit 7) */ +#define UART3_UART3_CTRL_REG_ISO7816_CLK_STATUS_Msk (0x80UL) /*!< ISO7816_CLK_STATUS (Bitfield-Mask: 0x01) */ +#define UART3_UART3_CTRL_REG_ISO7816_CLK_LEVEL_Pos (6UL) /*!< ISO7816_CLK_LEVEL (Bit 6) */ +#define UART3_UART3_CTRL_REG_ISO7816_CLK_LEVEL_Msk (0x40UL) /*!< ISO7816_CLK_LEVEL (Bitfield-Mask: 0x01) */ +#define UART3_UART3_CTRL_REG_ISO7816_CLK_EN_Pos (5UL) /*!< ISO7816_CLK_EN (Bit 5) */ +#define UART3_UART3_CTRL_REG_ISO7816_CLK_EN_Msk (0x20UL) /*!< ISO7816_CLK_EN (Bitfield-Mask: 0x01) */ +#define UART3_UART3_CTRL_REG_ISO7816_CLK_DIV_Pos (0UL) /*!< ISO7816_CLK_DIV (Bit 0) */ +#define UART3_UART3_CTRL_REG_ISO7816_CLK_DIV_Msk (0x1fUL) /*!< ISO7816_CLK_DIV (Bitfield-Mask: 0x1f) */ +/* ===================================================== UART3_CTR_REG ===================================================== */ +#define UART3_UART3_CTR_REG_UART_CTR_Pos (0UL) /*!< UART_CTR (Bit 0) */ +#define UART3_UART3_CTR_REG_UART_CTR_Msk (0xffffffffUL) /*!< UART_CTR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== UART3_DLF_REG ===================================================== */ +#define UART3_UART3_DLF_REG_UART_DLF_Pos (0UL) /*!< UART_DLF (Bit 0) */ +#define UART3_UART3_DLF_REG_UART_DLF_Msk (0xfUL) /*!< UART_DLF (Bitfield-Mask: 0x0f) */ +/* ==================================================== UART3_DMASA_REG ==================================================== */ +#define UART3_UART3_DMASA_REG_UART_DMASA_Pos (0UL) /*!< UART_DMASA (Bit 0) */ +#define UART3_UART3_DMASA_REG_UART_DMASA_Msk (0x1UL) /*!< UART_DMASA (Bitfield-Mask: 0x01) */ +/* ================================================== UART3_ERR_CTRL_REG =================================================== */ +#define UART3_UART3_ERR_CTRL_REG_ISO7816_ERR_PULSE_WIDTH_Pos (4UL) /*!< ISO7816_ERR_PULSE_WIDTH (Bit 4) */ +#define UART3_UART3_ERR_CTRL_REG_ISO7816_ERR_PULSE_WIDTH_Msk (0x1f0UL) /*!< ISO7816_ERR_PULSE_WIDTH (Bitfield-Mask: 0x1f) */ +#define UART3_UART3_ERR_CTRL_REG_ISO7816_ERR_PULSE_OFFSET_Pos (0UL) /*!< ISO7816_ERR_PULSE_OFFSET (Bit 0) */ +#define UART3_UART3_ERR_CTRL_REG_ISO7816_ERR_PULSE_OFFSET_Msk (0xfUL) /*!< ISO7816_ERR_PULSE_OFFSET (Bitfield-Mask: 0x0f) */ +/* ===================================================== UART3_HTX_REG ===================================================== */ +#define UART3_UART3_HTX_REG_UART_HALT_TX_Pos (0UL) /*!< UART_HALT_TX (Bit 0) */ +#define UART3_UART3_HTX_REG_UART_HALT_TX_Msk (0x1UL) /*!< UART_HALT_TX (Bitfield-Mask: 0x01) */ +/* =================================================== UART3_IER_DLH_REG =================================================== */ +#define UART3_UART3_IER_DLH_REG_PTIME_DLH7_Pos (7UL) /*!< PTIME_DLH7 (Bit 7) */ +#define UART3_UART3_IER_DLH_REG_PTIME_DLH7_Msk (0x80UL) /*!< PTIME_DLH7 (Bitfield-Mask: 0x01) */ +#define UART3_UART3_IER_DLH_REG_DLH6_5_Pos (5UL) /*!< DLH6_5 (Bit 5) */ +#define UART3_UART3_IER_DLH_REG_DLH6_5_Msk (0x60UL) /*!< DLH6_5 (Bitfield-Mask: 0x03) */ +#define UART3_UART3_IER_DLH_REG_ELCOLR_DLH4_Pos (4UL) /*!< ELCOLR_DLH4 (Bit 4) */ +#define UART3_UART3_IER_DLH_REG_ELCOLR_DLH4_Msk (0x10UL) /*!< ELCOLR_DLH4 (Bitfield-Mask: 0x01) */ +#define UART3_UART3_IER_DLH_REG_EDSSI_DLH3_Pos (3UL) /*!< EDSSI_DLH3 (Bit 3) */ +#define UART3_UART3_IER_DLH_REG_EDSSI_DLH3_Msk (0x8UL) /*!< EDSSI_DLH3 (Bitfield-Mask: 0x01) */ +#define UART3_UART3_IER_DLH_REG_ELSI_DLH2_Pos (2UL) /*!< ELSI_DLH2 (Bit 2) */ +#define UART3_UART3_IER_DLH_REG_ELSI_DLH2_Msk (0x4UL) /*!< ELSI_DLH2 (Bitfield-Mask: 0x01) */ +#define UART3_UART3_IER_DLH_REG_ETBEI_DLH1_Pos (1UL) /*!< ETBEI_DLH1 (Bit 1) */ +#define UART3_UART3_IER_DLH_REG_ETBEI_DLH1_Msk (0x2UL) /*!< ETBEI_DLH1 (Bitfield-Mask: 0x01) */ +#define UART3_UART3_IER_DLH_REG_ERBFI_DLH0_Pos (0UL) /*!< ERBFI_DLH0 (Bit 0) */ +#define UART3_UART3_IER_DLH_REG_ERBFI_DLH0_Msk (0x1UL) /*!< ERBFI_DLH0 (Bitfield-Mask: 0x01) */ +/* =================================================== UART3_IIR_FCR_REG =================================================== */ +#define UART3_UART3_IIR_FCR_REG_IIR_FCR_Pos (0UL) /*!< IIR_FCR (Bit 0) */ +#define UART3_UART3_IIR_FCR_REG_IIR_FCR_Msk (0xffUL) /*!< IIR_FCR (Bitfield-Mask: 0xff) */ +/* ================================================= UART3_IRQ_STATUS_REG ================================================== */ +#define UART3_UART3_IRQ_STATUS_REG_ISO7816_ERR_TX_VALUE_IRQ_Pos (2UL) /*!< ISO7816_ERR_TX_VALUE_IRQ (Bit 2) */ +#define UART3_UART3_IRQ_STATUS_REG_ISO7816_ERR_TX_VALUE_IRQ_Msk (0x4UL) /*!< ISO7816_ERR_TX_VALUE_IRQ (Bitfield-Mask: 0x01) */ +#define UART3_UART3_IRQ_STATUS_REG_ISO7816_ERR_TX_TIME_IRQ_Pos (1UL) /*!< ISO7816_ERR_TX_TIME_IRQ (Bit 1) */ +#define UART3_UART3_IRQ_STATUS_REG_ISO7816_ERR_TX_TIME_IRQ_Msk (0x2UL) /*!< ISO7816_ERR_TX_TIME_IRQ (Bitfield-Mask: 0x01) */ +#define UART3_UART3_IRQ_STATUS_REG_ISO7816_TIM_EXPIRED_IRQ_Pos (0UL) /*!< ISO7816_TIM_EXPIRED_IRQ (Bit 0) */ +#define UART3_UART3_IRQ_STATUS_REG_ISO7816_TIM_EXPIRED_IRQ_Msk (0x1UL) /*!< ISO7816_TIM_EXPIRED_IRQ (Bitfield-Mask: 0x01) */ +/* ===================================================== UART3_LCR_EXT ===================================================== */ +#define UART3_UART3_LCR_EXT_UART_TRANSMIT_MODE_Pos (3UL) /*!< UART_TRANSMIT_MODE (Bit 3) */ +#define UART3_UART3_LCR_EXT_UART_TRANSMIT_MODE_Msk (0x8UL) /*!< UART_TRANSMIT_MODE (Bitfield-Mask: 0x01) */ +#define UART3_UART3_LCR_EXT_UART_SEND_ADDR_Pos (2UL) /*!< UART_SEND_ADDR (Bit 2) */ +#define UART3_UART3_LCR_EXT_UART_SEND_ADDR_Msk (0x4UL) /*!< UART_SEND_ADDR (Bitfield-Mask: 0x01) */ +#define UART3_UART3_LCR_EXT_UART_ADDR_MATCH_Pos (1UL) /*!< UART_ADDR_MATCH (Bit 1) */ +#define UART3_UART3_LCR_EXT_UART_ADDR_MATCH_Msk (0x2UL) /*!< UART_ADDR_MATCH (Bitfield-Mask: 0x01) */ +#define UART3_UART3_LCR_EXT_UART_DLS_E_Pos (0UL) /*!< UART_DLS_E (Bit 0) */ +#define UART3_UART3_LCR_EXT_UART_DLS_E_Msk (0x1UL) /*!< UART_DLS_E (Bitfield-Mask: 0x01) */ +/* ===================================================== UART3_LCR_REG ===================================================== */ +#define UART3_UART3_LCR_REG_UART_DLAB_Pos (7UL) /*!< UART_DLAB (Bit 7) */ +#define UART3_UART3_LCR_REG_UART_DLAB_Msk (0x80UL) /*!< UART_DLAB (Bitfield-Mask: 0x01) */ +#define UART3_UART3_LCR_REG_UART_BC_Pos (6UL) /*!< UART_BC (Bit 6) */ +#define UART3_UART3_LCR_REG_UART_BC_Msk (0x40UL) /*!< UART_BC (Bitfield-Mask: 0x01) */ +#define UART3_UART3_LCR_REG_UART_SP_Pos (5UL) /*!< UART_SP (Bit 5) */ +#define UART3_UART3_LCR_REG_UART_SP_Msk (0x20UL) /*!< UART_SP (Bitfield-Mask: 0x01) */ +#define UART3_UART3_LCR_REG_UART_EPS_Pos (4UL) /*!< UART_EPS (Bit 4) */ +#define UART3_UART3_LCR_REG_UART_EPS_Msk (0x10UL) /*!< UART_EPS (Bitfield-Mask: 0x01) */ +#define UART3_UART3_LCR_REG_UART_PEN_Pos (3UL) /*!< UART_PEN (Bit 3) */ +#define UART3_UART3_LCR_REG_UART_PEN_Msk (0x8UL) /*!< UART_PEN (Bitfield-Mask: 0x01) */ +#define UART3_UART3_LCR_REG_UART_STOP_Pos (2UL) /*!< UART_STOP (Bit 2) */ +#define UART3_UART3_LCR_REG_UART_STOP_Msk (0x4UL) /*!< UART_STOP (Bitfield-Mask: 0x01) */ +#define UART3_UART3_LCR_REG_UART_DLS_Pos (0UL) /*!< UART_DLS (Bit 0) */ +#define UART3_UART3_LCR_REG_UART_DLS_Msk (0x3UL) /*!< UART_DLS (Bitfield-Mask: 0x03) */ +/* ===================================================== UART3_LSR_REG ===================================================== */ +#define UART3_UART3_LSR_REG_UART_ADDR_RCVD_Pos (8UL) /*!< UART_ADDR_RCVD (Bit 8) */ +#define UART3_UART3_LSR_REG_UART_ADDR_RCVD_Msk (0x100UL) /*!< UART_ADDR_RCVD (Bitfield-Mask: 0x01) */ +#define UART3_UART3_LSR_REG_UART_RFE_Pos (7UL) /*!< UART_RFE (Bit 7) */ +#define UART3_UART3_LSR_REG_UART_RFE_Msk (0x80UL) /*!< UART_RFE (Bitfield-Mask: 0x01) */ +#define UART3_UART3_LSR_REG_UART_TEMT_Pos (6UL) /*!< UART_TEMT (Bit 6) */ +#define UART3_UART3_LSR_REG_UART_TEMT_Msk (0x40UL) /*!< UART_TEMT (Bitfield-Mask: 0x01) */ +#define UART3_UART3_LSR_REG_UART_THRE_Pos (5UL) /*!< UART_THRE (Bit 5) */ +#define UART3_UART3_LSR_REG_UART_THRE_Msk (0x20UL) /*!< UART_THRE (Bitfield-Mask: 0x01) */ +#define UART3_UART3_LSR_REG_UART_BI_Pos (4UL) /*!< UART_BI (Bit 4) */ +#define UART3_UART3_LSR_REG_UART_BI_Msk (0x10UL) /*!< UART_BI (Bitfield-Mask: 0x01) */ +#define UART3_UART3_LSR_REG_UART_FE_Pos (3UL) /*!< UART_FE (Bit 3) */ +#define UART3_UART3_LSR_REG_UART_FE_Msk (0x8UL) /*!< UART_FE (Bitfield-Mask: 0x01) */ +#define UART3_UART3_LSR_REG_UART_PE_Pos (2UL) /*!< UART_PE (Bit 2) */ +#define UART3_UART3_LSR_REG_UART_PE_Msk (0x4UL) /*!< UART_PE (Bitfield-Mask: 0x01) */ +#define UART3_UART3_LSR_REG_UART_OE_Pos (1UL) /*!< UART_OE (Bit 1) */ +#define UART3_UART3_LSR_REG_UART_OE_Msk (0x2UL) /*!< UART_OE (Bitfield-Mask: 0x01) */ +#define UART3_UART3_LSR_REG_UART_DR_Pos (0UL) /*!< UART_DR (Bit 0) */ +#define UART3_UART3_LSR_REG_UART_DR_Msk (0x1UL) /*!< UART_DR (Bitfield-Mask: 0x01) */ +/* ===================================================== UART3_MCR_REG ===================================================== */ +#define UART3_UART3_MCR_REG_UART_AFCE_Pos (5UL) /*!< UART_AFCE (Bit 5) */ +#define UART3_UART3_MCR_REG_UART_AFCE_Msk (0x20UL) /*!< UART_AFCE (Bitfield-Mask: 0x01) */ +#define UART3_UART3_MCR_REG_UART_LB_Pos (4UL) /*!< UART_LB (Bit 4) */ +#define UART3_UART3_MCR_REG_UART_LB_Msk (0x10UL) /*!< UART_LB (Bitfield-Mask: 0x01) */ +#define UART3_UART3_MCR_REG_UART_RTS_Pos (1UL) /*!< UART_RTS (Bit 1) */ +#define UART3_UART3_MCR_REG_UART_RTS_Msk (0x2UL) /*!< UART_RTS (Bitfield-Mask: 0x01) */ +/* ===================================================== UART3_MSR_REG ===================================================== */ +#define UART3_UART3_MSR_REG_UART_CTS_Pos (4UL) /*!< UART_CTS (Bit 4) */ +#define UART3_UART3_MSR_REG_UART_CTS_Msk (0x10UL) /*!< UART_CTS (Bitfield-Mask: 0x01) */ +#define UART3_UART3_MSR_REG_UART_DCTS_Pos (0UL) /*!< UART_DCTS (Bit 0) */ +#define UART3_UART3_MSR_REG_UART_DCTS_Msk (0x1UL) /*!< UART_DCTS (Bitfield-Mask: 0x01) */ +/* ===================================================== UART3_RAR_REG ===================================================== */ +#define UART3_UART3_RAR_REG_UART_RAR_Pos (0UL) /*!< UART_RAR (Bit 0) */ +#define UART3_UART3_RAR_REG_UART_RAR_Msk (0xffUL) /*!< UART_RAR (Bitfield-Mask: 0xff) */ +/* ================================================= UART3_RBR_THR_DLL_REG ================================================= */ +#define UART3_UART3_RBR_THR_DLL_REG_RBR_THR_9BIT_Pos (8UL) /*!< RBR_THR_9BIT (Bit 8) */ +#define UART3_UART3_RBR_THR_DLL_REG_RBR_THR_9BIT_Msk (0x100UL) /*!< RBR_THR_9BIT (Bitfield-Mask: 0x01) */ +#define UART3_UART3_RBR_THR_DLL_REG_RBR_THR_DLL_Pos (0UL) /*!< RBR_THR_DLL (Bit 0) */ +#define UART3_UART3_RBR_THR_DLL_REG_RBR_THR_DLL_Msk (0xffUL) /*!< RBR_THR_DLL (Bitfield-Mask: 0xff) */ +/* ===================================================== UART3_RFL_REG ===================================================== */ +#define UART3_UART3_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Pos (0UL) /*!< UART_RECEIVE_FIFO_LEVEL (Bit 0) */ +#define UART3_UART3_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Msk (0x1fUL) /*!< UART_RECEIVE_FIFO_LEVEL (Bitfield-Mask: 0x1f) */ +/* ==================================================== UART3_SBCR_REG ===================================================== */ +#define UART3_UART3_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Pos (0UL) /*!< UART_SHADOW_BREAK_CONTROL (Bit 0) */ +#define UART3_UART3_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Msk (0x1UL) /*!< UART_SHADOW_BREAK_CONTROL (Bitfield-Mask: 0x01) */ +/* ==================================================== UART3_SDMAM_REG ==================================================== */ +#define UART3_UART3_SDMAM_REG_UART_SHADOW_DMA_MODE_Pos (0UL) /*!< UART_SHADOW_DMA_MODE (Bit 0) */ +#define UART3_UART3_SDMAM_REG_UART_SHADOW_DMA_MODE_Msk (0x1UL) /*!< UART_SHADOW_DMA_MODE (Bitfield-Mask: 0x01) */ +/* ===================================================== UART3_SFE_REG ===================================================== */ +#define UART3_UART3_SFE_REG_UART_SHADOW_FIFO_ENABLE_Pos (0UL) /*!< UART_SHADOW_FIFO_ENABLE (Bit 0) */ +#define UART3_UART3_SFE_REG_UART_SHADOW_FIFO_ENABLE_Msk (0x1UL) /*!< UART_SHADOW_FIFO_ENABLE (Bitfield-Mask: 0x01) */ +/* ================================================= UART3_SRBR_STHR0_REG ================================================== */ +#define UART3_UART3_SRBR_STHR0_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART3_UART3_SRBR_STHR0_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART3_SRBR_STHR10_REG ================================================= */ +#define UART3_UART3_SRBR_STHR10_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART3_UART3_SRBR_STHR10_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART3_SRBR_STHR11_REG ================================================= */ +#define UART3_UART3_SRBR_STHR11_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART3_UART3_SRBR_STHR11_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART3_SRBR_STHR12_REG ================================================= */ +#define UART3_UART3_SRBR_STHR12_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART3_UART3_SRBR_STHR12_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART3_SRBR_STHR13_REG ================================================= */ +#define UART3_UART3_SRBR_STHR13_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART3_UART3_SRBR_STHR13_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART3_SRBR_STHR14_REG ================================================= */ +#define UART3_UART3_SRBR_STHR14_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART3_UART3_SRBR_STHR14_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART3_SRBR_STHR15_REG ================================================= */ +#define UART3_UART3_SRBR_STHR15_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART3_UART3_SRBR_STHR15_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART3_SRBR_STHR1_REG ================================================== */ +#define UART3_UART3_SRBR_STHR1_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART3_UART3_SRBR_STHR1_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART3_SRBR_STHR2_REG ================================================== */ +#define UART3_UART3_SRBR_STHR2_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART3_UART3_SRBR_STHR2_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART3_SRBR_STHR3_REG ================================================== */ +#define UART3_UART3_SRBR_STHR3_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART3_UART3_SRBR_STHR3_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART3_SRBR_STHR4_REG ================================================== */ +#define UART3_UART3_SRBR_STHR4_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART3_UART3_SRBR_STHR4_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART3_SRBR_STHR5_REG ================================================== */ +#define UART3_UART3_SRBR_STHR5_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART3_UART3_SRBR_STHR5_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART3_SRBR_STHR6_REG ================================================== */ +#define UART3_UART3_SRBR_STHR6_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART3_UART3_SRBR_STHR6_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART3_SRBR_STHR7_REG ================================================== */ +#define UART3_UART3_SRBR_STHR7_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART3_UART3_SRBR_STHR7_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART3_SRBR_STHR8_REG ================================================== */ +#define UART3_UART3_SRBR_STHR8_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART3_UART3_SRBR_STHR8_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ================================================= UART3_SRBR_STHR9_REG ================================================== */ +#define UART3_UART3_SRBR_STHR9_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */ +#define UART3_UART3_SRBR_STHR9_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */ +/* ===================================================== UART3_SRR_REG ===================================================== */ +#define UART3_UART3_SRR_REG_UART_XFR_Pos (2UL) /*!< UART_XFR (Bit 2) */ +#define UART3_UART3_SRR_REG_UART_XFR_Msk (0x4UL) /*!< UART_XFR (Bitfield-Mask: 0x01) */ +#define UART3_UART3_SRR_REG_UART_RFR_Pos (1UL) /*!< UART_RFR (Bit 1) */ +#define UART3_UART3_SRR_REG_UART_RFR_Msk (0x2UL) /*!< UART_RFR (Bitfield-Mask: 0x01) */ +#define UART3_UART3_SRR_REG_UART_UR_Pos (0UL) /*!< UART_UR (Bit 0) */ +#define UART3_UART3_SRR_REG_UART_UR_Msk (0x1UL) /*!< UART_UR (Bitfield-Mask: 0x01) */ +/* ==================================================== UART3_SRTS_REG ===================================================== */ +#define UART3_UART3_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Pos (0UL) /*!< UART_SHADOW_REQUEST_TO_SEND (Bit 0) */ +#define UART3_UART3_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Msk (0x1UL) /*!< UART_SHADOW_REQUEST_TO_SEND (Bitfield-Mask: 0x01) */ +/* ===================================================== UART3_SRT_REG ===================================================== */ +#define UART3_UART3_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Pos (0UL) /*!< UART_SHADOW_RCVR_TRIGGER (Bit 0) */ +#define UART3_UART3_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Msk (0x3UL) /*!< UART_SHADOW_RCVR_TRIGGER (Bitfield-Mask: 0x03) */ +/* ==================================================== UART3_STET_REG ===================================================== */ +#define UART3_UART3_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Pos (0UL) /*!< UART_SHADOW_TX_EMPTY_TRIGGER (Bit 0) */ +#define UART3_UART3_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Msk (0x3UL) /*!< UART_SHADOW_TX_EMPTY_TRIGGER (Bitfield-Mask: 0x03) */ +/* ===================================================== UART3_TAR_REG ===================================================== */ +#define UART3_UART3_TAR_REG_UART_TAR_Pos (0UL) /*!< UART_TAR (Bit 0) */ +#define UART3_UART3_TAR_REG_UART_TAR_Msk (0xffUL) /*!< UART_TAR (Bitfield-Mask: 0xff) */ +/* ===================================================== UART3_TFL_REG ===================================================== */ +#define UART3_UART3_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Pos (0UL) /*!< UART_TRANSMIT_FIFO_LEVEL (Bit 0) */ +#define UART3_UART3_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Msk (0x1fUL) /*!< UART_TRANSMIT_FIFO_LEVEL (Bitfield-Mask: 0x1f) */ +/* ==================================================== UART3_TIMER_REG ==================================================== */ +#define UART3_UART3_TIMER_REG_ISO7816_TIM_MODE_Pos (17UL) /*!< ISO7816_TIM_MODE (Bit 17) */ +#define UART3_UART3_TIMER_REG_ISO7816_TIM_MODE_Msk (0x20000UL) /*!< ISO7816_TIM_MODE (Bitfield-Mask: 0x01) */ +#define UART3_UART3_TIMER_REG_ISO7816_TIM_EN_Pos (16UL) /*!< ISO7816_TIM_EN (Bit 16) */ +#define UART3_UART3_TIMER_REG_ISO7816_TIM_EN_Msk (0x10000UL) /*!< ISO7816_TIM_EN (Bitfield-Mask: 0x01) */ +#define UART3_UART3_TIMER_REG_ISO7816_TIM_MAX_Pos (0UL) /*!< ISO7816_TIM_MAX (Bit 0) */ +#define UART3_UART3_TIMER_REG_ISO7816_TIM_MAX_Msk (0xffffUL) /*!< ISO7816_TIM_MAX (Bitfield-Mask: 0xffff) */ +/* ===================================================== UART3_UCV_REG ===================================================== */ +#define UART3_UART3_UCV_REG_UART_UCV_Pos (0UL) /*!< UART_UCV (Bit 0) */ +#define UART3_UART3_UCV_REG_UART_UCV_Msk (0xffffffffUL) /*!< UART_UCV (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== UART3_USR_REG ===================================================== */ +#define UART3_UART3_USR_REG_UART_RFF_Pos (4UL) /*!< UART_RFF (Bit 4) */ +#define UART3_UART3_USR_REG_UART_RFF_Msk (0x10UL) /*!< UART_RFF (Bitfield-Mask: 0x01) */ +#define UART3_UART3_USR_REG_UART_RFNE_Pos (3UL) /*!< UART_RFNE (Bit 3) */ +#define UART3_UART3_USR_REG_UART_RFNE_Msk (0x8UL) /*!< UART_RFNE (Bitfield-Mask: 0x01) */ +#define UART3_UART3_USR_REG_UART_TFE_Pos (2UL) /*!< UART_TFE (Bit 2) */ +#define UART3_UART3_USR_REG_UART_TFE_Msk (0x4UL) /*!< UART_TFE (Bitfield-Mask: 0x01) */ +#define UART3_UART3_USR_REG_UART_TFNF_Pos (1UL) /*!< UART_TFNF (Bit 1) */ +#define UART3_UART3_USR_REG_UART_TFNF_Msk (0x2UL) /*!< UART_TFNF (Bitfield-Mask: 0x01) */ +#define UART3_UART3_USR_REG_UART_BUSY_Pos (0UL) /*!< UART_BUSY (Bit 0) */ +#define UART3_UART3_USR_REG_UART_BUSY_Msk (0x1UL) /*!< UART_BUSY (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ USB ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== USB_ALTEV_REG ===================================================== */ +#define USB_USB_ALTEV_REG_USB_RESUME_Pos (7UL) /*!< USB_RESUME (Bit 7) */ +#define USB_USB_ALTEV_REG_USB_RESUME_Msk (0x80UL) /*!< USB_RESUME (Bitfield-Mask: 0x01) */ +#define USB_USB_ALTEV_REG_USB_RESET_Pos (6UL) /*!< USB_RESET (Bit 6) */ +#define USB_USB_ALTEV_REG_USB_RESET_Msk (0x40UL) /*!< USB_RESET (Bitfield-Mask: 0x01) */ +#define USB_USB_ALTEV_REG_USB_SD5_Pos (5UL) /*!< USB_SD5 (Bit 5) */ +#define USB_USB_ALTEV_REG_USB_SD5_Msk (0x20UL) /*!< USB_SD5 (Bitfield-Mask: 0x01) */ +#define USB_USB_ALTEV_REG_USB_SD3_Pos (4UL) /*!< USB_SD3 (Bit 4) */ +#define USB_USB_ALTEV_REG_USB_SD3_Msk (0x10UL) /*!< USB_SD3 (Bitfield-Mask: 0x01) */ +#define USB_USB_ALTEV_REG_USB_EOP_Pos (3UL) /*!< USB_EOP (Bit 3) */ +#define USB_USB_ALTEV_REG_USB_EOP_Msk (0x8UL) /*!< USB_EOP (Bitfield-Mask: 0x01) */ +/* ==================================================== USB_ALTMSK_REG ===================================================== */ +#define USB_USB_ALTMSK_REG_USB_M_RESUME_Pos (7UL) /*!< USB_M_RESUME (Bit 7) */ +#define USB_USB_ALTMSK_REG_USB_M_RESUME_Msk (0x80UL) /*!< USB_M_RESUME (Bitfield-Mask: 0x01) */ +#define USB_USB_ALTMSK_REG_USB_M_RESET_Pos (6UL) /*!< USB_M_RESET (Bit 6) */ +#define USB_USB_ALTMSK_REG_USB_M_RESET_Msk (0x40UL) /*!< USB_M_RESET (Bitfield-Mask: 0x01) */ +#define USB_USB_ALTMSK_REG_USB_M_SD5_Pos (5UL) /*!< USB_M_SD5 (Bit 5) */ +#define USB_USB_ALTMSK_REG_USB_M_SD5_Msk (0x20UL) /*!< USB_M_SD5 (Bitfield-Mask: 0x01) */ +#define USB_USB_ALTMSK_REG_USB_M_SD3_Pos (4UL) /*!< USB_M_SD3 (Bit 4) */ +#define USB_USB_ALTMSK_REG_USB_M_SD3_Msk (0x10UL) /*!< USB_M_SD3 (Bitfield-Mask: 0x01) */ +#define USB_USB_ALTMSK_REG_USB_M_EOP_Pos (3UL) /*!< USB_M_EOP (Bit 3) */ +#define USB_USB_ALTMSK_REG_USB_M_EOP_Msk (0x8UL) /*!< USB_M_EOP (Bitfield-Mask: 0x01) */ +/* ================================================= USB_CHARGER_CTRL_REG ================================================== */ +#define USB_USB_CHARGER_CTRL_REG_IDM_SINK_ON_Pos (5UL) /*!< IDM_SINK_ON (Bit 5) */ +#define USB_USB_CHARGER_CTRL_REG_IDM_SINK_ON_Msk (0x20UL) /*!< IDM_SINK_ON (Bitfield-Mask: 0x01) */ +#define USB_USB_CHARGER_CTRL_REG_IDP_SINK_ON_Pos (4UL) /*!< IDP_SINK_ON (Bit 4) */ +#define USB_USB_CHARGER_CTRL_REG_IDP_SINK_ON_Msk (0x10UL) /*!< IDP_SINK_ON (Bitfield-Mask: 0x01) */ +#define USB_USB_CHARGER_CTRL_REG_VDM_SRC_ON_Pos (3UL) /*!< VDM_SRC_ON (Bit 3) */ +#define USB_USB_CHARGER_CTRL_REG_VDM_SRC_ON_Msk (0x8UL) /*!< VDM_SRC_ON (Bitfield-Mask: 0x01) */ +#define USB_USB_CHARGER_CTRL_REG_VDP_SRC_ON_Pos (2UL) /*!< VDP_SRC_ON (Bit 2) */ +#define USB_USB_CHARGER_CTRL_REG_VDP_SRC_ON_Msk (0x4UL) /*!< VDP_SRC_ON (Bitfield-Mask: 0x01) */ +#define USB_USB_CHARGER_CTRL_REG_IDP_SRC_ON_Pos (1UL) /*!< IDP_SRC_ON (Bit 1) */ +#define USB_USB_CHARGER_CTRL_REG_IDP_SRC_ON_Msk (0x2UL) /*!< IDP_SRC_ON (Bitfield-Mask: 0x01) */ +#define USB_USB_CHARGER_CTRL_REG_USB_CHARGE_ON_Pos (0UL) /*!< USB_CHARGE_ON (Bit 0) */ +#define USB_USB_CHARGER_CTRL_REG_USB_CHARGE_ON_Msk (0x1UL) /*!< USB_CHARGE_ON (Bitfield-Mask: 0x01) */ +/* ================================================= USB_CHARGER_STAT_REG ================================================== */ +#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL2_Pos (5UL) /*!< USB_DM_VAL2 (Bit 5) */ +#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL2_Msk (0x20UL) /*!< USB_DM_VAL2 (Bitfield-Mask: 0x01) */ +#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL2_Pos (4UL) /*!< USB_DP_VAL2 (Bit 4) */ +#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL2_Msk (0x10UL) /*!< USB_DP_VAL2 (Bitfield-Mask: 0x01) */ +#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL_Pos (3UL) /*!< USB_DM_VAL (Bit 3) */ +#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL_Msk (0x8UL) /*!< USB_DM_VAL (Bitfield-Mask: 0x01) */ +#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL_Pos (2UL) /*!< USB_DP_VAL (Bit 2) */ +#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL_Msk (0x4UL) /*!< USB_DP_VAL (Bitfield-Mask: 0x01) */ +#define USB_USB_CHARGER_STAT_REG_USB_CHG_DET_Pos (1UL) /*!< USB_CHG_DET (Bit 1) */ +#define USB_USB_CHARGER_STAT_REG_USB_CHG_DET_Msk (0x2UL) /*!< USB_CHG_DET (Bitfield-Mask: 0x01) */ +#define USB_USB_CHARGER_STAT_REG_USB_DCP_DET_Pos (0UL) /*!< USB_DCP_DET (Bit 0) */ +#define USB_USB_CHARGER_STAT_REG_USB_DCP_DET_Msk (0x1UL) /*!< USB_DCP_DET (Bitfield-Mask: 0x01) */ +/* =================================================== USB_DMA_CTRL_REG ==================================================== */ +#define USB_USB_DMA_CTRL_REG_USB_DMA_EN_Pos (6UL) /*!< USB_DMA_EN (Bit 6) */ +#define USB_USB_DMA_CTRL_REG_USB_DMA_EN_Msk (0x40UL) /*!< USB_DMA_EN (Bitfield-Mask: 0x01) */ +#define USB_USB_DMA_CTRL_REG_USB_DMA_TX_Pos (3UL) /*!< USB_DMA_TX (Bit 3) */ +#define USB_USB_DMA_CTRL_REG_USB_DMA_TX_Msk (0x38UL) /*!< USB_DMA_TX (Bitfield-Mask: 0x07) */ +#define USB_USB_DMA_CTRL_REG_USB_DMA_RX_Pos (0UL) /*!< USB_DMA_RX (Bit 0) */ +#define USB_USB_DMA_CTRL_REG_USB_DMA_RX_Msk (0x7UL) /*!< USB_DMA_RX (Bitfield-Mask: 0x07) */ +/* ==================================================== USB_EP0_NAK_REG ==================================================== */ +#define USB_USB_EP0_NAK_REG_USB_EP0_OUTNAK_Pos (1UL) /*!< USB_EP0_OUTNAK (Bit 1) */ +#define USB_USB_EP0_NAK_REG_USB_EP0_OUTNAK_Msk (0x2UL) /*!< USB_EP0_OUTNAK (Bitfield-Mask: 0x01) */ +#define USB_USB_EP0_NAK_REG_USB_EP0_INNAK_Pos (0UL) /*!< USB_EP0_INNAK (Bit 0) */ +#define USB_USB_EP0_NAK_REG_USB_EP0_INNAK_Msk (0x1UL) /*!< USB_EP0_INNAK (Bitfield-Mask: 0x01) */ +/* ===================================================== USB_EPC0_REG ====================================================== */ +#define USB_USB_EPC0_REG_USB_STALL_Pos (7UL) /*!< USB_STALL (Bit 7) */ +#define USB_USB_EPC0_REG_USB_STALL_Msk (0x80UL) /*!< USB_STALL (Bitfield-Mask: 0x01) */ +#define USB_USB_EPC0_REG_USB_DEF_Pos (6UL) /*!< USB_DEF (Bit 6) */ +#define USB_USB_EPC0_REG_USB_DEF_Msk (0x40UL) /*!< USB_DEF (Bitfield-Mask: 0x01) */ +#define USB_USB_EPC0_REG_USB_EP_Pos (0UL) /*!< USB_EP (Bit 0) */ +#define USB_USB_EPC0_REG_USB_EP_Msk (0xfUL) /*!< USB_EP (Bitfield-Mask: 0x0f) */ +/* ===================================================== USB_EPC1_REG ====================================================== */ +#define USB_USB_EPC1_REG_USB_STALL_Pos (7UL) /*!< USB_STALL (Bit 7) */ +#define USB_USB_EPC1_REG_USB_STALL_Msk (0x80UL) /*!< USB_STALL (Bitfield-Mask: 0x01) */ +#define USB_USB_EPC1_REG_USB_ISO_Pos (5UL) /*!< USB_ISO (Bit 5) */ +#define USB_USB_EPC1_REG_USB_ISO_Msk (0x20UL) /*!< USB_ISO (Bitfield-Mask: 0x01) */ +#define USB_USB_EPC1_REG_USB_EP_EN_Pos (4UL) /*!< USB_EP_EN (Bit 4) */ +#define USB_USB_EPC1_REG_USB_EP_EN_Msk (0x10UL) /*!< USB_EP_EN (Bitfield-Mask: 0x01) */ +#define USB_USB_EPC1_REG_USB_EP_Pos (0UL) /*!< USB_EP (Bit 0) */ +#define USB_USB_EPC1_REG_USB_EP_Msk (0xfUL) /*!< USB_EP (Bitfield-Mask: 0x0f) */ +/* ===================================================== USB_EPC2_REG ====================================================== */ +#define USB_USB_EPC2_REG_USB_STALL_Pos (7UL) /*!< USB_STALL (Bit 7) */ +#define USB_USB_EPC2_REG_USB_STALL_Msk (0x80UL) /*!< USB_STALL (Bitfield-Mask: 0x01) */ +#define USB_USB_EPC2_REG_USB_ISO_Pos (5UL) /*!< USB_ISO (Bit 5) */ +#define USB_USB_EPC2_REG_USB_ISO_Msk (0x20UL) /*!< USB_ISO (Bitfield-Mask: 0x01) */ +#define USB_USB_EPC2_REG_USB_EP_EN_Pos (4UL) /*!< USB_EP_EN (Bit 4) */ +#define USB_USB_EPC2_REG_USB_EP_EN_Msk (0x10UL) /*!< USB_EP_EN (Bitfield-Mask: 0x01) */ +#define USB_USB_EPC2_REG_USB_EP_Pos (0UL) /*!< USB_EP (Bit 0) */ +#define USB_USB_EPC2_REG_USB_EP_Msk (0xfUL) /*!< USB_EP (Bitfield-Mask: 0x0f) */ +/* ===================================================== USB_EPC3_REG ====================================================== */ +#define USB_USB_EPC3_REG_USB_STALL_Pos (7UL) /*!< USB_STALL (Bit 7) */ +#define USB_USB_EPC3_REG_USB_STALL_Msk (0x80UL) /*!< USB_STALL (Bitfield-Mask: 0x01) */ +#define USB_USB_EPC3_REG_USB_ISO_Pos (5UL) /*!< USB_ISO (Bit 5) */ +#define USB_USB_EPC3_REG_USB_ISO_Msk (0x20UL) /*!< USB_ISO (Bitfield-Mask: 0x01) */ +#define USB_USB_EPC3_REG_USB_EP_EN_Pos (4UL) /*!< USB_EP_EN (Bit 4) */ +#define USB_USB_EPC3_REG_USB_EP_EN_Msk (0x10UL) /*!< USB_EP_EN (Bitfield-Mask: 0x01) */ +#define USB_USB_EPC3_REG_USB_EP_Pos (0UL) /*!< USB_EP (Bit 0) */ +#define USB_USB_EPC3_REG_USB_EP_Msk (0xfUL) /*!< USB_EP (Bitfield-Mask: 0x0f) */ +/* ===================================================== USB_EPC4_REG ====================================================== */ +#define USB_USB_EPC4_REG_USB_STALL_Pos (7UL) /*!< USB_STALL (Bit 7) */ +#define USB_USB_EPC4_REG_USB_STALL_Msk (0x80UL) /*!< USB_STALL (Bitfield-Mask: 0x01) */ +#define USB_USB_EPC4_REG_USB_ISO_Pos (5UL) /*!< USB_ISO (Bit 5) */ +#define USB_USB_EPC4_REG_USB_ISO_Msk (0x20UL) /*!< USB_ISO (Bitfield-Mask: 0x01) */ +#define USB_USB_EPC4_REG_USB_EP_EN_Pos (4UL) /*!< USB_EP_EN (Bit 4) */ +#define USB_USB_EPC4_REG_USB_EP_EN_Msk (0x10UL) /*!< USB_EP_EN (Bitfield-Mask: 0x01) */ +#define USB_USB_EPC4_REG_USB_EP_Pos (0UL) /*!< USB_EP (Bit 0) */ +#define USB_USB_EPC4_REG_USB_EP_Msk (0xfUL) /*!< USB_EP (Bitfield-Mask: 0x0f) */ +/* ===================================================== USB_EPC5_REG ====================================================== */ +#define USB_USB_EPC5_REG_USB_STALL_Pos (7UL) /*!< USB_STALL (Bit 7) */ +#define USB_USB_EPC5_REG_USB_STALL_Msk (0x80UL) /*!< USB_STALL (Bitfield-Mask: 0x01) */ +#define USB_USB_EPC5_REG_USB_ISO_Pos (5UL) /*!< USB_ISO (Bit 5) */ +#define USB_USB_EPC5_REG_USB_ISO_Msk (0x20UL) /*!< USB_ISO (Bitfield-Mask: 0x01) */ +#define USB_USB_EPC5_REG_USB_EP_EN_Pos (4UL) /*!< USB_EP_EN (Bit 4) */ +#define USB_USB_EPC5_REG_USB_EP_EN_Msk (0x10UL) /*!< USB_EP_EN (Bitfield-Mask: 0x01) */ +#define USB_USB_EPC5_REG_USB_EP_Pos (0UL) /*!< USB_EP (Bit 0) */ +#define USB_USB_EPC5_REG_USB_EP_Msk (0xfUL) /*!< USB_EP (Bitfield-Mask: 0x0f) */ +/* ===================================================== USB_EPC6_REG ====================================================== */ +#define USB_USB_EPC6_REG_USB_STALL_Pos (7UL) /*!< USB_STALL (Bit 7) */ +#define USB_USB_EPC6_REG_USB_STALL_Msk (0x80UL) /*!< USB_STALL (Bitfield-Mask: 0x01) */ +#define USB_USB_EPC6_REG_USB_ISO_Pos (5UL) /*!< USB_ISO (Bit 5) */ +#define USB_USB_EPC6_REG_USB_ISO_Msk (0x20UL) /*!< USB_ISO (Bitfield-Mask: 0x01) */ +#define USB_USB_EPC6_REG_USB_EP_EN_Pos (4UL) /*!< USB_EP_EN (Bit 4) */ +#define USB_USB_EPC6_REG_USB_EP_EN_Msk (0x10UL) /*!< USB_EP_EN (Bitfield-Mask: 0x01) */ +#define USB_USB_EPC6_REG_USB_EP_Pos (0UL) /*!< USB_EP (Bit 0) */ +#define USB_USB_EPC6_REG_USB_EP_Msk (0xfUL) /*!< USB_EP (Bitfield-Mask: 0x0f) */ +/* ====================================================== USB_FAR_REG ====================================================== */ +#define USB_USB_FAR_REG_USB_AD_EN_Pos (7UL) /*!< USB_AD_EN (Bit 7) */ +#define USB_USB_FAR_REG_USB_AD_EN_Msk (0x80UL) /*!< USB_AD_EN (Bitfield-Mask: 0x01) */ +#define USB_USB_FAR_REG_USB_AD_Pos (0UL) /*!< USB_AD (Bit 0) */ +#define USB_USB_FAR_REG_USB_AD_Msk (0x7fUL) /*!< USB_AD (Bitfield-Mask: 0x7f) */ +/* ====================================================== USB_FNH_REG ====================================================== */ +#define USB_USB_FNH_REG_USB_MF_Pos (7UL) /*!< USB_MF (Bit 7) */ +#define USB_USB_FNH_REG_USB_MF_Msk (0x80UL) /*!< USB_MF (Bitfield-Mask: 0x01) */ +#define USB_USB_FNH_REG_USB_UL_Pos (6UL) /*!< USB_UL (Bit 6) */ +#define USB_USB_FNH_REG_USB_UL_Msk (0x40UL) /*!< USB_UL (Bitfield-Mask: 0x01) */ +#define USB_USB_FNH_REG_USB_RFC_Pos (5UL) /*!< USB_RFC (Bit 5) */ +#define USB_USB_FNH_REG_USB_RFC_Msk (0x20UL) /*!< USB_RFC (Bitfield-Mask: 0x01) */ +#define USB_USB_FNH_REG_USB_FN_10_8_Pos (0UL) /*!< USB_FN_10_8 (Bit 0) */ +#define USB_USB_FNH_REG_USB_FN_10_8_Msk (0x7UL) /*!< USB_FN_10_8 (Bitfield-Mask: 0x07) */ +/* ====================================================== USB_FNL_REG ====================================================== */ +#define USB_USB_FNL_REG_USB_FN_Pos (0UL) /*!< USB_FN (Bit 0) */ +#define USB_USB_FNL_REG_USB_FN_Msk (0xffUL) /*!< USB_FN (Bitfield-Mask: 0xff) */ +/* ===================================================== USB_FWEV_REG ====================================================== */ +#define USB_USB_FWEV_REG_USB_RXWARN31_Pos (4UL) /*!< USB_RXWARN31 (Bit 4) */ +#define USB_USB_FWEV_REG_USB_RXWARN31_Msk (0x70UL) /*!< USB_RXWARN31 (Bitfield-Mask: 0x07) */ +#define USB_USB_FWEV_REG_USB_TXWARN31_Pos (0UL) /*!< USB_TXWARN31 (Bit 0) */ +#define USB_USB_FWEV_REG_USB_TXWARN31_Msk (0x7UL) /*!< USB_TXWARN31 (Bitfield-Mask: 0x07) */ +/* ===================================================== USB_FWMSK_REG ===================================================== */ +#define USB_USB_FWMSK_REG_USB_M_RXWARN31_Pos (4UL) /*!< USB_M_RXWARN31 (Bit 4) */ +#define USB_USB_FWMSK_REG_USB_M_RXWARN31_Msk (0x70UL) /*!< USB_M_RXWARN31 (Bitfield-Mask: 0x07) */ +#define USB_USB_FWMSK_REG_USB_M_TXWARN31_Pos (0UL) /*!< USB_M_TXWARN31 (Bit 0) */ +#define USB_USB_FWMSK_REG_USB_M_TXWARN31_Msk (0x7UL) /*!< USB_M_TXWARN31 (Bitfield-Mask: 0x07) */ +/* ===================================================== USB_MAEV_REG ====================================================== */ +#define USB_USB_MAEV_REG_USB_CH_EV_Pos (11UL) /*!< USB_CH_EV (Bit 11) */ +#define USB_USB_MAEV_REG_USB_CH_EV_Msk (0x800UL) /*!< USB_CH_EV (Bitfield-Mask: 0x01) */ +#define USB_USB_MAEV_REG_USB_EP0_NAK_Pos (10UL) /*!< USB_EP0_NAK (Bit 10) */ +#define USB_USB_MAEV_REG_USB_EP0_NAK_Msk (0x400UL) /*!< USB_EP0_NAK (Bitfield-Mask: 0x01) */ +#define USB_USB_MAEV_REG_USB_EP0_RX_Pos (9UL) /*!< USB_EP0_RX (Bit 9) */ +#define USB_USB_MAEV_REG_USB_EP0_RX_Msk (0x200UL) /*!< USB_EP0_RX (Bitfield-Mask: 0x01) */ +#define USB_USB_MAEV_REG_USB_EP0_TX_Pos (8UL) /*!< USB_EP0_TX (Bit 8) */ +#define USB_USB_MAEV_REG_USB_EP0_TX_Msk (0x100UL) /*!< USB_EP0_TX (Bitfield-Mask: 0x01) */ +#define USB_USB_MAEV_REG_USB_INTR_Pos (7UL) /*!< USB_INTR (Bit 7) */ +#define USB_USB_MAEV_REG_USB_INTR_Msk (0x80UL) /*!< USB_INTR (Bitfield-Mask: 0x01) */ +#define USB_USB_MAEV_REG_USB_RX_EV_Pos (6UL) /*!< USB_RX_EV (Bit 6) */ +#define USB_USB_MAEV_REG_USB_RX_EV_Msk (0x40UL) /*!< USB_RX_EV (Bitfield-Mask: 0x01) */ +#define USB_USB_MAEV_REG_USB_ULD_Pos (5UL) /*!< USB_ULD (Bit 5) */ +#define USB_USB_MAEV_REG_USB_ULD_Msk (0x20UL) /*!< USB_ULD (Bitfield-Mask: 0x01) */ +#define USB_USB_MAEV_REG_USB_NAK_Pos (4UL) /*!< USB_NAK (Bit 4) */ +#define USB_USB_MAEV_REG_USB_NAK_Msk (0x10UL) /*!< USB_NAK (Bitfield-Mask: 0x01) */ +#define USB_USB_MAEV_REG_USB_FRAME_Pos (3UL) /*!< USB_FRAME (Bit 3) */ +#define USB_USB_MAEV_REG_USB_FRAME_Msk (0x8UL) /*!< USB_FRAME (Bitfield-Mask: 0x01) */ +#define USB_USB_MAEV_REG_USB_TX_EV_Pos (2UL) /*!< USB_TX_EV (Bit 2) */ +#define USB_USB_MAEV_REG_USB_TX_EV_Msk (0x4UL) /*!< USB_TX_EV (Bitfield-Mask: 0x01) */ +#define USB_USB_MAEV_REG_USB_ALT_Pos (1UL) /*!< USB_ALT (Bit 1) */ +#define USB_USB_MAEV_REG_USB_ALT_Msk (0x2UL) /*!< USB_ALT (Bitfield-Mask: 0x01) */ +#define USB_USB_MAEV_REG_USB_WARN_Pos (0UL) /*!< USB_WARN (Bit 0) */ +#define USB_USB_MAEV_REG_USB_WARN_Msk (0x1UL) /*!< USB_WARN (Bitfield-Mask: 0x01) */ +/* ===================================================== USB_MAMSK_REG ===================================================== */ +#define USB_USB_MAMSK_REG_USB_M_CH_EV_Pos (11UL) /*!< USB_M_CH_EV (Bit 11) */ +#define USB_USB_MAMSK_REG_USB_M_CH_EV_Msk (0x800UL) /*!< USB_M_CH_EV (Bitfield-Mask: 0x01) */ +#define USB_USB_MAMSK_REG_USB_M_EP0_NAK_Pos (10UL) /*!< USB_M_EP0_NAK (Bit 10) */ +#define USB_USB_MAMSK_REG_USB_M_EP0_NAK_Msk (0x400UL) /*!< USB_M_EP0_NAK (Bitfield-Mask: 0x01) */ +#define USB_USB_MAMSK_REG_USB_M_EP0_RX_Pos (9UL) /*!< USB_M_EP0_RX (Bit 9) */ +#define USB_USB_MAMSK_REG_USB_M_EP0_RX_Msk (0x200UL) /*!< USB_M_EP0_RX (Bitfield-Mask: 0x01) */ +#define USB_USB_MAMSK_REG_USB_M_EP0_TX_Pos (8UL) /*!< USB_M_EP0_TX (Bit 8) */ +#define USB_USB_MAMSK_REG_USB_M_EP0_TX_Msk (0x100UL) /*!< USB_M_EP0_TX (Bitfield-Mask: 0x01) */ +#define USB_USB_MAMSK_REG_USB_M_INTR_Pos (7UL) /*!< USB_M_INTR (Bit 7) */ +#define USB_USB_MAMSK_REG_USB_M_INTR_Msk (0x80UL) /*!< USB_M_INTR (Bitfield-Mask: 0x01) */ +#define USB_USB_MAMSK_REG_USB_M_RX_EV_Pos (6UL) /*!< USB_M_RX_EV (Bit 6) */ +#define USB_USB_MAMSK_REG_USB_M_RX_EV_Msk (0x40UL) /*!< USB_M_RX_EV (Bitfield-Mask: 0x01) */ +#define USB_USB_MAMSK_REG_USB_M_ULD_Pos (5UL) /*!< USB_M_ULD (Bit 5) */ +#define USB_USB_MAMSK_REG_USB_M_ULD_Msk (0x20UL) /*!< USB_M_ULD (Bitfield-Mask: 0x01) */ +#define USB_USB_MAMSK_REG_USB_M_NAK_Pos (4UL) /*!< USB_M_NAK (Bit 4) */ +#define USB_USB_MAMSK_REG_USB_M_NAK_Msk (0x10UL) /*!< USB_M_NAK (Bitfield-Mask: 0x01) */ +#define USB_USB_MAMSK_REG_USB_M_FRAME_Pos (3UL) /*!< USB_M_FRAME (Bit 3) */ +#define USB_USB_MAMSK_REG_USB_M_FRAME_Msk (0x8UL) /*!< USB_M_FRAME (Bitfield-Mask: 0x01) */ +#define USB_USB_MAMSK_REG_USB_M_TX_EV_Pos (2UL) /*!< USB_M_TX_EV (Bit 2) */ +#define USB_USB_MAMSK_REG_USB_M_TX_EV_Msk (0x4UL) /*!< USB_M_TX_EV (Bitfield-Mask: 0x01) */ +#define USB_USB_MAMSK_REG_USB_M_ALT_Pos (1UL) /*!< USB_M_ALT (Bit 1) */ +#define USB_USB_MAMSK_REG_USB_M_ALT_Msk (0x2UL) /*!< USB_M_ALT (Bitfield-Mask: 0x01) */ +#define USB_USB_MAMSK_REG_USB_M_WARN_Pos (0UL) /*!< USB_M_WARN (Bit 0) */ +#define USB_USB_MAMSK_REG_USB_M_WARN_Msk (0x1UL) /*!< USB_M_WARN (Bitfield-Mask: 0x01) */ +/* ===================================================== USB_MCTRL_REG ===================================================== */ +#define USB_USB_MCTRL_REG_LSMODE_Pos (4UL) /*!< LSMODE (Bit 4) */ +#define USB_USB_MCTRL_REG_LSMODE_Msk (0x10UL) /*!< LSMODE (Bitfield-Mask: 0x01) */ +#define USB_USB_MCTRL_REG_USB_NAT_Pos (3UL) /*!< USB_NAT (Bit 3) */ +#define USB_USB_MCTRL_REG_USB_NAT_Msk (0x8UL) /*!< USB_NAT (Bitfield-Mask: 0x01) */ +#define USB_USB_MCTRL_REG_USB_DBG_Pos (1UL) /*!< USB_DBG (Bit 1) */ +#define USB_USB_MCTRL_REG_USB_DBG_Msk (0x2UL) /*!< USB_DBG (Bitfield-Mask: 0x01) */ +#define USB_USB_MCTRL_REG_USBEN_Pos (0UL) /*!< USBEN (Bit 0) */ +#define USB_USB_MCTRL_REG_USBEN_Msk (0x1UL) /*!< USBEN (Bitfield-Mask: 0x01) */ +/* ===================================================== USB_NAKEV_REG ===================================================== */ +#define USB_USB_NAKEV_REG_USB_OUT31_Pos (4UL) /*!< USB_OUT31 (Bit 4) */ +#define USB_USB_NAKEV_REG_USB_OUT31_Msk (0x70UL) /*!< USB_OUT31 (Bitfield-Mask: 0x07) */ +#define USB_USB_NAKEV_REG_USB_IN31_Pos (0UL) /*!< USB_IN31 (Bit 0) */ +#define USB_USB_NAKEV_REG_USB_IN31_Msk (0x7UL) /*!< USB_IN31 (Bitfield-Mask: 0x07) */ +/* ==================================================== USB_NAKMSK_REG ===================================================== */ +#define USB_USB_NAKMSK_REG_USB_M_OUT31_Pos (4UL) /*!< USB_M_OUT31 (Bit 4) */ +#define USB_USB_NAKMSK_REG_USB_M_OUT31_Msk (0x70UL) /*!< USB_M_OUT31 (Bitfield-Mask: 0x07) */ +#define USB_USB_NAKMSK_REG_USB_M_IN31_Pos (0UL) /*!< USB_M_IN31 (Bit 0) */ +#define USB_USB_NAKMSK_REG_USB_M_IN31_Msk (0x7UL) /*!< USB_M_IN31 (Bitfield-Mask: 0x07) */ +/* ===================================================== USB_NFSR_REG ====================================================== */ +#define USB_USB_NFSR_REG_USB_NFS_Pos (0UL) /*!< USB_NFS (Bit 0) */ +#define USB_USB_NFSR_REG_USB_NFS_Msk (0x3UL) /*!< USB_NFS (Bitfield-Mask: 0x03) */ +/* ===================================================== USB_RXC0_REG ====================================================== */ +#define USB_USB_RXC0_REG_USB_FLUSH_Pos (3UL) /*!< USB_FLUSH (Bit 3) */ +#define USB_USB_RXC0_REG_USB_FLUSH_Msk (0x8UL) /*!< USB_FLUSH (Bitfield-Mask: 0x01) */ +#define USB_USB_RXC0_REG_USB_IGN_SETUP_Pos (2UL) /*!< USB_IGN_SETUP (Bit 2) */ +#define USB_USB_RXC0_REG_USB_IGN_SETUP_Msk (0x4UL) /*!< USB_IGN_SETUP (Bitfield-Mask: 0x01) */ +#define USB_USB_RXC0_REG_USB_IGN_OUT_Pos (1UL) /*!< USB_IGN_OUT (Bit 1) */ +#define USB_USB_RXC0_REG_USB_IGN_OUT_Msk (0x2UL) /*!< USB_IGN_OUT (Bitfield-Mask: 0x01) */ +#define USB_USB_RXC0_REG_USB_RX_EN_Pos (0UL) /*!< USB_RX_EN (Bit 0) */ +#define USB_USB_RXC0_REG_USB_RX_EN_Msk (0x1UL) /*!< USB_RX_EN (Bitfield-Mask: 0x01) */ +/* ===================================================== USB_RXC1_REG ====================================================== */ +#define USB_USB_RXC1_REG_USB_RFWL_Pos (5UL) /*!< USB_RFWL (Bit 5) */ +#define USB_USB_RXC1_REG_USB_RFWL_Msk (0x60UL) /*!< USB_RFWL (Bitfield-Mask: 0x03) */ +#define USB_USB_RXC1_REG_USB_FLUSH_Pos (3UL) /*!< USB_FLUSH (Bit 3) */ +#define USB_USB_RXC1_REG_USB_FLUSH_Msk (0x8UL) /*!< USB_FLUSH (Bitfield-Mask: 0x01) */ +#define USB_USB_RXC1_REG_USB_IGN_SETUP_Pos (2UL) /*!< USB_IGN_SETUP (Bit 2) */ +#define USB_USB_RXC1_REG_USB_IGN_SETUP_Msk (0x4UL) /*!< USB_IGN_SETUP (Bitfield-Mask: 0x01) */ +#define USB_USB_RXC1_REG_USB_RX_EN_Pos (0UL) /*!< USB_RX_EN (Bit 0) */ +#define USB_USB_RXC1_REG_USB_RX_EN_Msk (0x1UL) /*!< USB_RX_EN (Bitfield-Mask: 0x01) */ +/* ===================================================== USB_RXC2_REG ====================================================== */ +#define USB_USB_RXC2_REG_USB_RFWL_Pos (5UL) /*!< USB_RFWL (Bit 5) */ +#define USB_USB_RXC2_REG_USB_RFWL_Msk (0x60UL) /*!< USB_RFWL (Bitfield-Mask: 0x03) */ +#define USB_USB_RXC2_REG_USB_FLUSH_Pos (3UL) /*!< USB_FLUSH (Bit 3) */ +#define USB_USB_RXC2_REG_USB_FLUSH_Msk (0x8UL) /*!< USB_FLUSH (Bitfield-Mask: 0x01) */ +#define USB_USB_RXC2_REG_USB_IGN_SETUP_Pos (2UL) /*!< USB_IGN_SETUP (Bit 2) */ +#define USB_USB_RXC2_REG_USB_IGN_SETUP_Msk (0x4UL) /*!< USB_IGN_SETUP (Bitfield-Mask: 0x01) */ +#define USB_USB_RXC2_REG_USB_RX_EN_Pos (0UL) /*!< USB_RX_EN (Bit 0) */ +#define USB_USB_RXC2_REG_USB_RX_EN_Msk (0x1UL) /*!< USB_RX_EN (Bitfield-Mask: 0x01) */ +/* ===================================================== USB_RXC3_REG ====================================================== */ +#define USB_USB_RXC3_REG_USB_RFWL_Pos (5UL) /*!< USB_RFWL (Bit 5) */ +#define USB_USB_RXC3_REG_USB_RFWL_Msk (0x60UL) /*!< USB_RFWL (Bitfield-Mask: 0x03) */ +#define USB_USB_RXC3_REG_USB_FLUSH_Pos (3UL) /*!< USB_FLUSH (Bit 3) */ +#define USB_USB_RXC3_REG_USB_FLUSH_Msk (0x8UL) /*!< USB_FLUSH (Bitfield-Mask: 0x01) */ +#define USB_USB_RXC3_REG_USB_IGN_SETUP_Pos (2UL) /*!< USB_IGN_SETUP (Bit 2) */ +#define USB_USB_RXC3_REG_USB_IGN_SETUP_Msk (0x4UL) /*!< USB_IGN_SETUP (Bitfield-Mask: 0x01) */ +#define USB_USB_RXC3_REG_USB_RX_EN_Pos (0UL) /*!< USB_RX_EN (Bit 0) */ +#define USB_USB_RXC3_REG_USB_RX_EN_Msk (0x1UL) /*!< USB_RX_EN (Bitfield-Mask: 0x01) */ +/* ===================================================== USB_RXD0_REG ====================================================== */ +#define USB_USB_RXD0_REG_USB_RXFD_Pos (0UL) /*!< USB_RXFD (Bit 0) */ +#define USB_USB_RXD0_REG_USB_RXFD_Msk (0xffUL) /*!< USB_RXFD (Bitfield-Mask: 0xff) */ +/* ===================================================== USB_RXD1_REG ====================================================== */ +#define USB_USB_RXD1_REG_USB_RXFD_Pos (0UL) /*!< USB_RXFD (Bit 0) */ +#define USB_USB_RXD1_REG_USB_RXFD_Msk (0xffUL) /*!< USB_RXFD (Bitfield-Mask: 0xff) */ +/* ===================================================== USB_RXD2_REG ====================================================== */ +#define USB_USB_RXD2_REG_USB_RXFD_Pos (0UL) /*!< USB_RXFD (Bit 0) */ +#define USB_USB_RXD2_REG_USB_RXFD_Msk (0xffUL) /*!< USB_RXFD (Bitfield-Mask: 0xff) */ +/* ===================================================== USB_RXD3_REG ====================================================== */ +#define USB_USB_RXD3_REG_USB_RXFD_Pos (0UL) /*!< USB_RXFD (Bit 0) */ +#define USB_USB_RXD3_REG_USB_RXFD_Msk (0xffUL) /*!< USB_RXFD (Bitfield-Mask: 0xff) */ +/* ===================================================== USB_RXEV_REG ====================================================== */ +#define USB_USB_RXEV_REG_USB_RXOVRRN31_Pos (4UL) /*!< USB_RXOVRRN31 (Bit 4) */ +#define USB_USB_RXEV_REG_USB_RXOVRRN31_Msk (0x70UL) /*!< USB_RXOVRRN31 (Bitfield-Mask: 0x07) */ +#define USB_USB_RXEV_REG_USB_RXFIFO31_Pos (0UL) /*!< USB_RXFIFO31 (Bit 0) */ +#define USB_USB_RXEV_REG_USB_RXFIFO31_Msk (0x7UL) /*!< USB_RXFIFO31 (Bitfield-Mask: 0x07) */ +/* ===================================================== USB_RXMSK_REG ===================================================== */ +#define USB_USB_RXMSK_REG_USB_M_RXOVRRN31_Pos (4UL) /*!< USB_M_RXOVRRN31 (Bit 4) */ +#define USB_USB_RXMSK_REG_USB_M_RXOVRRN31_Msk (0x70UL) /*!< USB_M_RXOVRRN31 (Bitfield-Mask: 0x07) */ +#define USB_USB_RXMSK_REG_USB_M_RXFIFO31_Pos (0UL) /*!< USB_M_RXFIFO31 (Bit 0) */ +#define USB_USB_RXMSK_REG_USB_M_RXFIFO31_Msk (0x7UL) /*!< USB_M_RXFIFO31 (Bitfield-Mask: 0x07) */ +/* ===================================================== USB_RXS0_REG ====================================================== */ +#define USB_USB_RXS0_REG_USB_SETUP_Pos (6UL) /*!< USB_SETUP (Bit 6) */ +#define USB_USB_RXS0_REG_USB_SETUP_Msk (0x40UL) /*!< USB_SETUP (Bitfield-Mask: 0x01) */ +#define USB_USB_RXS0_REG_USB_TOGGLE_RX0_Pos (5UL) /*!< USB_TOGGLE_RX0 (Bit 5) */ +#define USB_USB_RXS0_REG_USB_TOGGLE_RX0_Msk (0x20UL) /*!< USB_TOGGLE_RX0 (Bitfield-Mask: 0x01) */ +#define USB_USB_RXS0_REG_USB_RX_LAST_Pos (4UL) /*!< USB_RX_LAST (Bit 4) */ +#define USB_USB_RXS0_REG_USB_RX_LAST_Msk (0x10UL) /*!< USB_RX_LAST (Bitfield-Mask: 0x01) */ +#define USB_USB_RXS0_REG_USB_RCOUNT_Pos (0UL) /*!< USB_RCOUNT (Bit 0) */ +#define USB_USB_RXS0_REG_USB_RCOUNT_Msk (0xfUL) /*!< USB_RCOUNT (Bitfield-Mask: 0x0f) */ +/* ===================================================== USB_RXS1_REG ====================================================== */ +#define USB_USB_RXS1_REG_USB_RXCOUNT_Pos (8UL) /*!< USB_RXCOUNT (Bit 8) */ +#define USB_USB_RXS1_REG_USB_RXCOUNT_Msk (0x7f00UL) /*!< USB_RXCOUNT (Bitfield-Mask: 0x7f) */ +#define USB_USB_RXS1_REG_USB_RX_ERR_Pos (7UL) /*!< USB_RX_ERR (Bit 7) */ +#define USB_USB_RXS1_REG_USB_RX_ERR_Msk (0x80UL) /*!< USB_RX_ERR (Bitfield-Mask: 0x01) */ +#define USB_USB_RXS1_REG_USB_SETUP_Pos (6UL) /*!< USB_SETUP (Bit 6) */ +#define USB_USB_RXS1_REG_USB_SETUP_Msk (0x40UL) /*!< USB_SETUP (Bitfield-Mask: 0x01) */ +#define USB_USB_RXS1_REG_USB_TOGGLE_RX_Pos (5UL) /*!< USB_TOGGLE_RX (Bit 5) */ +#define USB_USB_RXS1_REG_USB_TOGGLE_RX_Msk (0x20UL) /*!< USB_TOGGLE_RX (Bitfield-Mask: 0x01) */ +#define USB_USB_RXS1_REG_USB_RX_LAST_Pos (4UL) /*!< USB_RX_LAST (Bit 4) */ +#define USB_USB_RXS1_REG_USB_RX_LAST_Msk (0x10UL) /*!< USB_RX_LAST (Bitfield-Mask: 0x01) */ +#define USB_USB_RXS1_REG_USB_RCOUNT_Pos (0UL) /*!< USB_RCOUNT (Bit 0) */ +#define USB_USB_RXS1_REG_USB_RCOUNT_Msk (0xfUL) /*!< USB_RCOUNT (Bitfield-Mask: 0x0f) */ +/* ===================================================== USB_RXS2_REG ====================================================== */ +#define USB_USB_RXS2_REG_USB_RXCOUNT_Pos (8UL) /*!< USB_RXCOUNT (Bit 8) */ +#define USB_USB_RXS2_REG_USB_RXCOUNT_Msk (0x7f00UL) /*!< USB_RXCOUNT (Bitfield-Mask: 0x7f) */ +#define USB_USB_RXS2_REG_USB_RX_ERR_Pos (7UL) /*!< USB_RX_ERR (Bit 7) */ +#define USB_USB_RXS2_REG_USB_RX_ERR_Msk (0x80UL) /*!< USB_RX_ERR (Bitfield-Mask: 0x01) */ +#define USB_USB_RXS2_REG_USB_SETUP_Pos (6UL) /*!< USB_SETUP (Bit 6) */ +#define USB_USB_RXS2_REG_USB_SETUP_Msk (0x40UL) /*!< USB_SETUP (Bitfield-Mask: 0x01) */ +#define USB_USB_RXS2_REG_USB_TOGGLE_RX_Pos (5UL) /*!< USB_TOGGLE_RX (Bit 5) */ +#define USB_USB_RXS2_REG_USB_TOGGLE_RX_Msk (0x20UL) /*!< USB_TOGGLE_RX (Bitfield-Mask: 0x01) */ +#define USB_USB_RXS2_REG_USB_RX_LAST_Pos (4UL) /*!< USB_RX_LAST (Bit 4) */ +#define USB_USB_RXS2_REG_USB_RX_LAST_Msk (0x10UL) /*!< USB_RX_LAST (Bitfield-Mask: 0x01) */ +#define USB_USB_RXS2_REG_USB_RCOUNT_Pos (0UL) /*!< USB_RCOUNT (Bit 0) */ +#define USB_USB_RXS2_REG_USB_RCOUNT_Msk (0xfUL) /*!< USB_RCOUNT (Bitfield-Mask: 0x0f) */ +/* ===================================================== USB_RXS3_REG ====================================================== */ +#define USB_USB_RXS3_REG_USB_RXCOUNT_Pos (8UL) /*!< USB_RXCOUNT (Bit 8) */ +#define USB_USB_RXS3_REG_USB_RXCOUNT_Msk (0x7f00UL) /*!< USB_RXCOUNT (Bitfield-Mask: 0x7f) */ +#define USB_USB_RXS3_REG_USB_RX_ERR_Pos (7UL) /*!< USB_RX_ERR (Bit 7) */ +#define USB_USB_RXS3_REG_USB_RX_ERR_Msk (0x80UL) /*!< USB_RX_ERR (Bitfield-Mask: 0x01) */ +#define USB_USB_RXS3_REG_USB_SETUP_Pos (6UL) /*!< USB_SETUP (Bit 6) */ +#define USB_USB_RXS3_REG_USB_SETUP_Msk (0x40UL) /*!< USB_SETUP (Bitfield-Mask: 0x01) */ +#define USB_USB_RXS3_REG_USB_TOGGLE_RX_Pos (5UL) /*!< USB_TOGGLE_RX (Bit 5) */ +#define USB_USB_RXS3_REG_USB_TOGGLE_RX_Msk (0x20UL) /*!< USB_TOGGLE_RX (Bitfield-Mask: 0x01) */ +#define USB_USB_RXS3_REG_USB_RX_LAST_Pos (4UL) /*!< USB_RX_LAST (Bit 4) */ +#define USB_USB_RXS3_REG_USB_RX_LAST_Msk (0x10UL) /*!< USB_RX_LAST (Bitfield-Mask: 0x01) */ +#define USB_USB_RXS3_REG_USB_RCOUNT_Pos (0UL) /*!< USB_RCOUNT (Bit 0) */ +#define USB_USB_RXS3_REG_USB_RCOUNT_Msk (0xfUL) /*!< USB_RCOUNT (Bitfield-Mask: 0x0f) */ +/* ====================================================== USB_TCR_REG ====================================================== */ +#define USB_USB_TCR_REG_USB_VADJ_Pos (5UL) /*!< USB_VADJ (Bit 5) */ +#define USB_USB_TCR_REG_USB_VADJ_Msk (0xe0UL) /*!< USB_VADJ (Bitfield-Mask: 0x07) */ +#define USB_USB_TCR_REG_USB_CADJ_Pos (0UL) /*!< USB_CADJ (Bit 0) */ +#define USB_USB_TCR_REG_USB_CADJ_Msk (0x1fUL) /*!< USB_CADJ (Bitfield-Mask: 0x1f) */ +/* ===================================================== USB_TXC0_REG ====================================================== */ +#define USB_USB_TXC0_REG_USB_IGN_IN_Pos (4UL) /*!< USB_IGN_IN (Bit 4) */ +#define USB_USB_TXC0_REG_USB_IGN_IN_Msk (0x10UL) /*!< USB_IGN_IN (Bitfield-Mask: 0x01) */ +#define USB_USB_TXC0_REG_USB_FLUSH_Pos (3UL) /*!< USB_FLUSH (Bit 3) */ +#define USB_USB_TXC0_REG_USB_FLUSH_Msk (0x8UL) /*!< USB_FLUSH (Bitfield-Mask: 0x01) */ +#define USB_USB_TXC0_REG_USB_TOGGLE_TX0_Pos (2UL) /*!< USB_TOGGLE_TX0 (Bit 2) */ +#define USB_USB_TXC0_REG_USB_TOGGLE_TX0_Msk (0x4UL) /*!< USB_TOGGLE_TX0 (Bitfield-Mask: 0x01) */ +#define USB_USB_TXC0_REG_USB_TX_EN_Pos (0UL) /*!< USB_TX_EN (Bit 0) */ +#define USB_USB_TXC0_REG_USB_TX_EN_Msk (0x1UL) /*!< USB_TX_EN (Bitfield-Mask: 0x01) */ +/* ===================================================== USB_TXC1_REG ====================================================== */ +#define USB_USB_TXC1_REG_USB_IGN_ISOMSK_Pos (7UL) /*!< USB_IGN_ISOMSK (Bit 7) */ +#define USB_USB_TXC1_REG_USB_IGN_ISOMSK_Msk (0x80UL) /*!< USB_IGN_ISOMSK (Bitfield-Mask: 0x01) */ +#define USB_USB_TXC1_REG_USB_TFWL_Pos (5UL) /*!< USB_TFWL (Bit 5) */ +#define USB_USB_TXC1_REG_USB_TFWL_Msk (0x60UL) /*!< USB_TFWL (Bitfield-Mask: 0x03) */ +#define USB_USB_TXC1_REG_USB_RFF_Pos (4UL) /*!< USB_RFF (Bit 4) */ +#define USB_USB_TXC1_REG_USB_RFF_Msk (0x10UL) /*!< USB_RFF (Bitfield-Mask: 0x01) */ +#define USB_USB_TXC1_REG_USB_FLUSH_Pos (3UL) /*!< USB_FLUSH (Bit 3) */ +#define USB_USB_TXC1_REG_USB_FLUSH_Msk (0x8UL) /*!< USB_FLUSH (Bitfield-Mask: 0x01) */ +#define USB_USB_TXC1_REG_USB_TOGGLE_TX_Pos (2UL) /*!< USB_TOGGLE_TX (Bit 2) */ +#define USB_USB_TXC1_REG_USB_TOGGLE_TX_Msk (0x4UL) /*!< USB_TOGGLE_TX (Bitfield-Mask: 0x01) */ +#define USB_USB_TXC1_REG_USB_LAST_Pos (1UL) /*!< USB_LAST (Bit 1) */ +#define USB_USB_TXC1_REG_USB_LAST_Msk (0x2UL) /*!< USB_LAST (Bitfield-Mask: 0x01) */ +#define USB_USB_TXC1_REG_USB_TX_EN_Pos (0UL) /*!< USB_TX_EN (Bit 0) */ +#define USB_USB_TXC1_REG_USB_TX_EN_Msk (0x1UL) /*!< USB_TX_EN (Bitfield-Mask: 0x01) */ +/* ===================================================== USB_TXC2_REG ====================================================== */ +#define USB_USB_TXC2_REG_USB_IGN_ISOMSK_Pos (7UL) /*!< USB_IGN_ISOMSK (Bit 7) */ +#define USB_USB_TXC2_REG_USB_IGN_ISOMSK_Msk (0x80UL) /*!< USB_IGN_ISOMSK (Bitfield-Mask: 0x01) */ +#define USB_USB_TXC2_REG_USB_TFWL_Pos (5UL) /*!< USB_TFWL (Bit 5) */ +#define USB_USB_TXC2_REG_USB_TFWL_Msk (0x60UL) /*!< USB_TFWL (Bitfield-Mask: 0x03) */ +#define USB_USB_TXC2_REG_USB_RFF_Pos (4UL) /*!< USB_RFF (Bit 4) */ +#define USB_USB_TXC2_REG_USB_RFF_Msk (0x10UL) /*!< USB_RFF (Bitfield-Mask: 0x01) */ +#define USB_USB_TXC2_REG_USB_FLUSH_Pos (3UL) /*!< USB_FLUSH (Bit 3) */ +#define USB_USB_TXC2_REG_USB_FLUSH_Msk (0x8UL) /*!< USB_FLUSH (Bitfield-Mask: 0x01) */ +#define USB_USB_TXC2_REG_USB_TOGGLE_TX_Pos (2UL) /*!< USB_TOGGLE_TX (Bit 2) */ +#define USB_USB_TXC2_REG_USB_TOGGLE_TX_Msk (0x4UL) /*!< USB_TOGGLE_TX (Bitfield-Mask: 0x01) */ +#define USB_USB_TXC2_REG_USB_LAST_Pos (1UL) /*!< USB_LAST (Bit 1) */ +#define USB_USB_TXC2_REG_USB_LAST_Msk (0x2UL) /*!< USB_LAST (Bitfield-Mask: 0x01) */ +#define USB_USB_TXC2_REG_USB_TX_EN_Pos (0UL) /*!< USB_TX_EN (Bit 0) */ +#define USB_USB_TXC2_REG_USB_TX_EN_Msk (0x1UL) /*!< USB_TX_EN (Bitfield-Mask: 0x01) */ +/* ===================================================== USB_TXC3_REG ====================================================== */ +#define USB_USB_TXC3_REG_USB_IGN_ISOMSK_Pos (7UL) /*!< USB_IGN_ISOMSK (Bit 7) */ +#define USB_USB_TXC3_REG_USB_IGN_ISOMSK_Msk (0x80UL) /*!< USB_IGN_ISOMSK (Bitfield-Mask: 0x01) */ +#define USB_USB_TXC3_REG_USB_TFWL_Pos (5UL) /*!< USB_TFWL (Bit 5) */ +#define USB_USB_TXC3_REG_USB_TFWL_Msk (0x60UL) /*!< USB_TFWL (Bitfield-Mask: 0x03) */ +#define USB_USB_TXC3_REG_USB_RFF_Pos (4UL) /*!< USB_RFF (Bit 4) */ +#define USB_USB_TXC3_REG_USB_RFF_Msk (0x10UL) /*!< USB_RFF (Bitfield-Mask: 0x01) */ +#define USB_USB_TXC3_REG_USB_FLUSH_Pos (3UL) /*!< USB_FLUSH (Bit 3) */ +#define USB_USB_TXC3_REG_USB_FLUSH_Msk (0x8UL) /*!< USB_FLUSH (Bitfield-Mask: 0x01) */ +#define USB_USB_TXC3_REG_USB_TOGGLE_TX_Pos (2UL) /*!< USB_TOGGLE_TX (Bit 2) */ +#define USB_USB_TXC3_REG_USB_TOGGLE_TX_Msk (0x4UL) /*!< USB_TOGGLE_TX (Bitfield-Mask: 0x01) */ +#define USB_USB_TXC3_REG_USB_LAST_Pos (1UL) /*!< USB_LAST (Bit 1) */ +#define USB_USB_TXC3_REG_USB_LAST_Msk (0x2UL) /*!< USB_LAST (Bitfield-Mask: 0x01) */ +#define USB_USB_TXC3_REG_USB_TX_EN_Pos (0UL) /*!< USB_TX_EN (Bit 0) */ +#define USB_USB_TXC3_REG_USB_TX_EN_Msk (0x1UL) /*!< USB_TX_EN (Bitfield-Mask: 0x01) */ +/* ===================================================== USB_TXD0_REG ====================================================== */ +#define USB_USB_TXD0_REG_USB_TXFD_Pos (0UL) /*!< USB_TXFD (Bit 0) */ +#define USB_USB_TXD0_REG_USB_TXFD_Msk (0xffUL) /*!< USB_TXFD (Bitfield-Mask: 0xff) */ +/* ===================================================== USB_TXD1_REG ====================================================== */ +#define USB_USB_TXD1_REG_USB_TXFD_Pos (0UL) /*!< USB_TXFD (Bit 0) */ +#define USB_USB_TXD1_REG_USB_TXFD_Msk (0xffUL) /*!< USB_TXFD (Bitfield-Mask: 0xff) */ +/* ===================================================== USB_TXD2_REG ====================================================== */ +#define USB_USB_TXD2_REG_USB_TXFD_Pos (0UL) /*!< USB_TXFD (Bit 0) */ +#define USB_USB_TXD2_REG_USB_TXFD_Msk (0xffUL) /*!< USB_TXFD (Bitfield-Mask: 0xff) */ +/* ===================================================== USB_TXD3_REG ====================================================== */ +#define USB_USB_TXD3_REG_USB_TXFD_Pos (0UL) /*!< USB_TXFD (Bit 0) */ +#define USB_USB_TXD3_REG_USB_TXFD_Msk (0xffUL) /*!< USB_TXFD (Bitfield-Mask: 0xff) */ +/* ===================================================== USB_TXEV_REG ====================================================== */ +#define USB_USB_TXEV_REG_USB_TXUDRRN31_Pos (4UL) /*!< USB_TXUDRRN31 (Bit 4) */ +#define USB_USB_TXEV_REG_USB_TXUDRRN31_Msk (0x70UL) /*!< USB_TXUDRRN31 (Bitfield-Mask: 0x07) */ +#define USB_USB_TXEV_REG_USB_TXFIFO31_Pos (0UL) /*!< USB_TXFIFO31 (Bit 0) */ +#define USB_USB_TXEV_REG_USB_TXFIFO31_Msk (0x7UL) /*!< USB_TXFIFO31 (Bitfield-Mask: 0x07) */ +/* ===================================================== USB_TXMSK_REG ===================================================== */ +#define USB_USB_TXMSK_REG_USB_M_TXUDRRN31_Pos (4UL) /*!< USB_M_TXUDRRN31 (Bit 4) */ +#define USB_USB_TXMSK_REG_USB_M_TXUDRRN31_Msk (0x70UL) /*!< USB_M_TXUDRRN31 (Bitfield-Mask: 0x07) */ +#define USB_USB_TXMSK_REG_USB_M_TXFIFO31_Pos (0UL) /*!< USB_M_TXFIFO31 (Bit 0) */ +#define USB_USB_TXMSK_REG_USB_M_TXFIFO31_Msk (0x7UL) /*!< USB_M_TXFIFO31 (Bitfield-Mask: 0x07) */ +/* ===================================================== USB_TXS0_REG ====================================================== */ +#define USB_USB_TXS0_REG_USB_ACK_STAT_Pos (6UL) /*!< USB_ACK_STAT (Bit 6) */ +#define USB_USB_TXS0_REG_USB_ACK_STAT_Msk (0x40UL) /*!< USB_ACK_STAT (Bitfield-Mask: 0x01) */ +#define USB_USB_TXS0_REG_USB_TX_DONE_Pos (5UL) /*!< USB_TX_DONE (Bit 5) */ +#define USB_USB_TXS0_REG_USB_TX_DONE_Msk (0x20UL) /*!< USB_TX_DONE (Bitfield-Mask: 0x01) */ +#define USB_USB_TXS0_REG_USB_TCOUNT_Pos (0UL) /*!< USB_TCOUNT (Bit 0) */ +#define USB_USB_TXS0_REG_USB_TCOUNT_Msk (0x1fUL) /*!< USB_TCOUNT (Bitfield-Mask: 0x1f) */ +/* ===================================================== USB_TXS1_REG ====================================================== */ +#define USB_USB_TXS1_REG_USB_TX_URUN_Pos (7UL) /*!< USB_TX_URUN (Bit 7) */ +#define USB_USB_TXS1_REG_USB_TX_URUN_Msk (0x80UL) /*!< USB_TX_URUN (Bitfield-Mask: 0x01) */ +#define USB_USB_TXS1_REG_USB_ACK_STAT_Pos (6UL) /*!< USB_ACK_STAT (Bit 6) */ +#define USB_USB_TXS1_REG_USB_ACK_STAT_Msk (0x40UL) /*!< USB_ACK_STAT (Bitfield-Mask: 0x01) */ +#define USB_USB_TXS1_REG_USB_TX_DONE_Pos (5UL) /*!< USB_TX_DONE (Bit 5) */ +#define USB_USB_TXS1_REG_USB_TX_DONE_Msk (0x20UL) /*!< USB_TX_DONE (Bitfield-Mask: 0x01) */ +#define USB_USB_TXS1_REG_USB_TCOUNT_Pos (0UL) /*!< USB_TCOUNT (Bit 0) */ +#define USB_USB_TXS1_REG_USB_TCOUNT_Msk (0x1fUL) /*!< USB_TCOUNT (Bitfield-Mask: 0x1f) */ +/* ===================================================== USB_TXS2_REG ====================================================== */ +#define USB_USB_TXS2_REG_USB_TX_URUN_Pos (7UL) /*!< USB_TX_URUN (Bit 7) */ +#define USB_USB_TXS2_REG_USB_TX_URUN_Msk (0x80UL) /*!< USB_TX_URUN (Bitfield-Mask: 0x01) */ +#define USB_USB_TXS2_REG_USB_ACK_STAT_Pos (6UL) /*!< USB_ACK_STAT (Bit 6) */ +#define USB_USB_TXS2_REG_USB_ACK_STAT_Msk (0x40UL) /*!< USB_ACK_STAT (Bitfield-Mask: 0x01) */ +#define USB_USB_TXS2_REG_USB_TX_DONE_Pos (5UL) /*!< USB_TX_DONE (Bit 5) */ +#define USB_USB_TXS2_REG_USB_TX_DONE_Msk (0x20UL) /*!< USB_TX_DONE (Bitfield-Mask: 0x01) */ +#define USB_USB_TXS2_REG_USB_TCOUNT_Pos (0UL) /*!< USB_TCOUNT (Bit 0) */ +#define USB_USB_TXS2_REG_USB_TCOUNT_Msk (0x1fUL) /*!< USB_TCOUNT (Bitfield-Mask: 0x1f) */ +/* ===================================================== USB_TXS3_REG ====================================================== */ +#define USB_USB_TXS3_REG_USB_TX_URUN_Pos (7UL) /*!< USB_TX_URUN (Bit 7) */ +#define USB_USB_TXS3_REG_USB_TX_URUN_Msk (0x80UL) /*!< USB_TX_URUN (Bitfield-Mask: 0x01) */ +#define USB_USB_TXS3_REG_USB_ACK_STAT_Pos (6UL) /*!< USB_ACK_STAT (Bit 6) */ +#define USB_USB_TXS3_REG_USB_ACK_STAT_Msk (0x40UL) /*!< USB_ACK_STAT (Bitfield-Mask: 0x01) */ +#define USB_USB_TXS3_REG_USB_TX_DONE_Pos (5UL) /*!< USB_TX_DONE (Bit 5) */ +#define USB_USB_TXS3_REG_USB_TX_DONE_Msk (0x20UL) /*!< USB_TX_DONE (Bitfield-Mask: 0x01) */ +#define USB_USB_TXS3_REG_USB_TCOUNT_Pos (0UL) /*!< USB_TCOUNT (Bit 0) */ +#define USB_USB_TXS3_REG_USB_TCOUNT_Msk (0x1fUL) /*!< USB_TCOUNT (Bitfield-Mask: 0x1f) */ +/* ====================================================== USB_UTR_REG ====================================================== */ +#define USB_USB_UTR_REG_USB_DIAG_Pos (7UL) /*!< USB_DIAG (Bit 7) */ +#define USB_USB_UTR_REG_USB_DIAG_Msk (0x80UL) /*!< USB_DIAG (Bitfield-Mask: 0x01) */ +#define USB_USB_UTR_REG_USB_NCRC_Pos (6UL) /*!< USB_NCRC (Bit 6) */ +#define USB_USB_UTR_REG_USB_NCRC_Msk (0x40UL) /*!< USB_NCRC (Bitfield-Mask: 0x01) */ +#define USB_USB_UTR_REG_USB_SF_Pos (5UL) /*!< USB_SF (Bit 5) */ +#define USB_USB_UTR_REG_USB_SF_Msk (0x20UL) /*!< USB_SF (Bitfield-Mask: 0x01) */ +#define USB_USB_UTR_REG_USB_UTR_RES_Pos (0UL) /*!< USB_UTR_RES (Bit 0) */ +#define USB_USB_UTR_REG_USB_UTR_RES_Msk (0x1fUL) /*!< USB_UTR_RES (Bitfield-Mask: 0x1f) */ +/* ==================================================== USB_UX20CDR_REG ==================================================== */ +#define USB_USB_UX20CDR_REG_RPU_TEST7_Pos (7UL) /*!< RPU_TEST7 (Bit 7) */ +#define USB_USB_UX20CDR_REG_RPU_TEST7_Msk (0x80UL) /*!< RPU_TEST7 (Bitfield-Mask: 0x01) */ +#define USB_USB_UX20CDR_REG_RPU_TEST_SW2_Pos (6UL) /*!< RPU_TEST_SW2 (Bit 6) */ +#define USB_USB_UX20CDR_REG_RPU_TEST_SW2_Msk (0x40UL) /*!< RPU_TEST_SW2 (Bitfield-Mask: 0x01) */ +#define USB_USB_UX20CDR_REG_RPU_TEST_SW1_Pos (5UL) /*!< RPU_TEST_SW1 (Bit 5) */ +#define USB_USB_UX20CDR_REG_RPU_TEST_SW1_Msk (0x20UL) /*!< RPU_TEST_SW1 (Bitfield-Mask: 0x01) */ +#define USB_USB_UX20CDR_REG_RPU_TEST_EN_Pos (4UL) /*!< RPU_TEST_EN (Bit 4) */ +#define USB_USB_UX20CDR_REG_RPU_TEST_EN_Msk (0x10UL) /*!< RPU_TEST_EN (Bitfield-Mask: 0x01) */ +#define USB_USB_UX20CDR_REG_RPU_TEST_SW1DM_Pos (2UL) /*!< RPU_TEST_SW1DM (Bit 2) */ +#define USB_USB_UX20CDR_REG_RPU_TEST_SW1DM_Msk (0x4UL) /*!< RPU_TEST_SW1DM (Bitfield-Mask: 0x01) */ +#define USB_USB_UX20CDR_REG_RPU_RCDELAY_Pos (1UL) /*!< RPU_RCDELAY (Bit 1) */ +#define USB_USB_UX20CDR_REG_RPU_RCDELAY_Msk (0x2UL) /*!< RPU_RCDELAY (Bitfield-Mask: 0x01) */ +#define USB_USB_UX20CDR_REG_RPU_SSPROTEN_Pos (0UL) /*!< RPU_SSPROTEN (Bit 0) */ +#define USB_USB_UX20CDR_REG_RPU_SSPROTEN_Msk (0x1UL) /*!< RPU_SSPROTEN (Bitfield-Mask: 0x01) */ +/* ==================================================== USB_XCVDIAG_REG ==================================================== */ +#define USB_USB_XCVDIAG_REG_USB_VPIN_Pos (7UL) /*!< USB_VPIN (Bit 7) */ +#define USB_USB_XCVDIAG_REG_USB_VPIN_Msk (0x80UL) /*!< USB_VPIN (Bitfield-Mask: 0x01) */ +#define USB_USB_XCVDIAG_REG_USB_VMIN_Pos (6UL) /*!< USB_VMIN (Bit 6) */ +#define USB_USB_XCVDIAG_REG_USB_VMIN_Msk (0x40UL) /*!< USB_VMIN (Bitfield-Mask: 0x01) */ +#define USB_USB_XCVDIAG_REG_USB_RCV_Pos (5UL) /*!< USB_RCV (Bit 5) */ +#define USB_USB_XCVDIAG_REG_USB_RCV_Msk (0x20UL) /*!< USB_RCV (Bitfield-Mask: 0x01) */ +#define USB_USB_XCVDIAG_REG_USB_XCV_TXEN_Pos (3UL) /*!< USB_XCV_TXEN (Bit 3) */ +#define USB_USB_XCVDIAG_REG_USB_XCV_TXEN_Msk (0x8UL) /*!< USB_XCV_TXEN (Bitfield-Mask: 0x01) */ +#define USB_USB_XCVDIAG_REG_USB_XCV_TXn_Pos (2UL) /*!< USB_XCV_TXn (Bit 2) */ +#define USB_USB_XCVDIAG_REG_USB_XCV_TXn_Msk (0x4UL) /*!< USB_XCV_TXn (Bitfield-Mask: 0x01) */ +#define USB_USB_XCVDIAG_REG_USB_XCV_TXp_Pos (1UL) /*!< USB_XCV_TXp (Bit 1) */ +#define USB_USB_XCVDIAG_REG_USB_XCV_TXp_Msk (0x2UL) /*!< USB_XCV_TXp (Bitfield-Mask: 0x01) */ +#define USB_USB_XCVDIAG_REG_USB_XCV_TEST_Pos (0UL) /*!< USB_XCV_TEST (Bit 0) */ +#define USB_USB_XCVDIAG_REG_USB_XCV_TEST_Msk (0x1UL) /*!< USB_XCV_TEST (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ WAKEUP ================ */ +/* =========================================================================================================================== */ + +/* =================================================== WKUP_CLEAR_P0_REG =================================================== */ +#define WAKEUP_WKUP_CLEAR_P0_REG_WKUP_CLEAR_P0_Pos (0UL) /*!< WKUP_CLEAR_P0 (Bit 0) */ +#define WAKEUP_WKUP_CLEAR_P0_REG_WKUP_CLEAR_P0_Msk (0xffffffffUL) /*!< WKUP_CLEAR_P0 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== WKUP_CLEAR_P1_REG =================================================== */ +#define WAKEUP_WKUP_CLEAR_P1_REG_WKUP_CLEAR_P1_Pos (0UL) /*!< WKUP_CLEAR_P1 (Bit 0) */ +#define WAKEUP_WKUP_CLEAR_P1_REG_WKUP_CLEAR_P1_Msk (0x7fffffUL) /*!< WKUP_CLEAR_P1 (Bitfield-Mask: 0x7fffff) */ +/* ===================================================== WKUP_CTRL_REG ===================================================== */ +#define WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Pos (7UL) /*!< WKUP_ENABLE_IRQ (Bit 7) */ +#define WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Msk (0x80UL) /*!< WKUP_ENABLE_IRQ (Bitfield-Mask: 0x01) */ +#define WAKEUP_WKUP_CTRL_REG_WKUP_SFT_KEYHIT_Pos (6UL) /*!< WKUP_SFT_KEYHIT (Bit 6) */ +#define WAKEUP_WKUP_CTRL_REG_WKUP_SFT_KEYHIT_Msk (0x40UL) /*!< WKUP_SFT_KEYHIT (Bitfield-Mask: 0x01) */ +#define WAKEUP_WKUP_CTRL_REG_WKUP_DEB_VALUE_Pos (0UL) /*!< WKUP_DEB_VALUE (Bit 0) */ +#define WAKEUP_WKUP_CTRL_REG_WKUP_DEB_VALUE_Msk (0x3fUL) /*!< WKUP_DEB_VALUE (Bitfield-Mask: 0x3f) */ +/* ==================================================== WKUP_POL_P0_REG ==================================================== */ +#define WAKEUP_WKUP_POL_P0_REG_WKUP_POL_P0_Pos (0UL) /*!< WKUP_POL_P0 (Bit 0) */ +#define WAKEUP_WKUP_POL_P0_REG_WKUP_POL_P0_Msk (0xffffffffUL) /*!< WKUP_POL_P0 (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== WKUP_POL_P1_REG ==================================================== */ +#define WAKEUP_WKUP_POL_P1_REG_WKUP_POL_P1_Pos (0UL) /*!< WKUP_POL_P1 (Bit 0) */ +#define WAKEUP_WKUP_POL_P1_REG_WKUP_POL_P1_Msk (0x7fffffUL) /*!< WKUP_POL_P1 (Bitfield-Mask: 0x7fffff) */ +/* ================================================== WKUP_RESET_IRQ_REG =================================================== */ +#define WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Pos (0UL) /*!< WKUP_IRQ_RST (Bit 0) */ +#define WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Msk (0xffffUL) /*!< WKUP_IRQ_RST (Bitfield-Mask: 0xffff) */ +/* ================================================== WKUP_SELECT_P0_REG =================================================== */ +#define WAKEUP_WKUP_SELECT_P0_REG_WKUP_SELECT_P0_Pos (0UL) /*!< WKUP_SELECT_P0 (Bit 0) */ +#define WAKEUP_WKUP_SELECT_P0_REG_WKUP_SELECT_P0_Msk (0xffffffffUL) /*!< WKUP_SELECT_P0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== WKUP_SELECT_P1_REG =================================================== */ +#define WAKEUP_WKUP_SELECT_P1_REG_WKUP_SELECT_P1_Pos (0UL) /*!< WKUP_SELECT_P1 (Bit 0) */ +#define WAKEUP_WKUP_SELECT_P1_REG_WKUP_SELECT_P1_Msk (0x7fffffUL) /*!< WKUP_SELECT_P1 (Bitfield-Mask: 0x7fffff) */ +/* ================================================= WKUP_SEL_GPIO_P0_REG ================================================== */ +#define WAKEUP_WKUP_SEL_GPIO_P0_REG_WKUP_SEL_GPIO_P0_Pos (0UL) /*!< WKUP_SEL_GPIO_P0 (Bit 0) */ +#define WAKEUP_WKUP_SEL_GPIO_P0_REG_WKUP_SEL_GPIO_P0_Msk (0xffffffffUL) /*!< WKUP_SEL_GPIO_P0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= WKUP_SEL_GPIO_P1_REG ================================================== */ +#define WAKEUP_WKUP_SEL_GPIO_P1_REG_WKUP_SEL_GPIO_P1_Pos (0UL) /*!< WKUP_SEL_GPIO_P1 (Bit 0) */ +#define WAKEUP_WKUP_SEL_GPIO_P1_REG_WKUP_SEL_GPIO_P1_Msk (0x7fffffUL) /*!< WKUP_SEL_GPIO_P1 (Bitfield-Mask: 0x7fffff) */ +/* ================================================== WKUP_STATUS_P0_REG =================================================== */ +#define WAKEUP_WKUP_STATUS_P0_REG_WKUP_STAT_P0_Pos (0UL) /*!< WKUP_STAT_P0 (Bit 0) */ +#define WAKEUP_WKUP_STATUS_P0_REG_WKUP_STAT_P0_Msk (0xffffffffUL) /*!< WKUP_STAT_P0 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== WKUP_STATUS_P1_REG =================================================== */ +#define WAKEUP_WKUP_STATUS_P1_REG_WKUP_STAT_P1_Pos (0UL) /*!< WKUP_STAT_P1 (Bit 0) */ +#define WAKEUP_WKUP_STATUS_P1_REG_WKUP_STAT_P1_Msk (0x7fffffUL) /*!< WKUP_STAT_P1 (Bitfield-Mask: 0x7fffff) */ + +/** @} */ /* End of group PosMask_peripherals */ + + +#ifdef __cplusplus +} +#endif + +#endif /* DA1469X_H */ + + +/** @} */ /* End of group DA1469x */ + +/** @} */ /* End of group PLA_BSP_REGISTERS */ diff --git a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_compiler.h b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_compiler.h new file mode 100755 index 00000000..fdb1a971 --- /dev/null +++ b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_compiler.h @@ -0,0 +1,271 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include <stdint.h> + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include <cmsis_iccarm.h> + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include <cmsis_ccs.h> + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include <cmsis_csm.h> + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_gcc.h b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_gcc.h new file mode 100755 index 00000000..47a4b59d --- /dev/null +++ b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_gcc.h @@ -0,0 +1,2102 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.1.0 + * @date 20. December 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + /* Copyright (c) 2019 Modified by Dialog Semiconductor */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] val Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] val Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_version.h b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_version.h new file mode 100755 index 00000000..660f612a --- /dev/null +++ b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm0.h b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm0.h new file mode 100755 index 00000000..e2cf6b96 --- /dev/null +++ b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm0.h @@ -0,0 +1,950 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + /* Copyright (c) 2019 Modified by Dialog Semiconductor */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include <stdint.h> + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.<br> + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.<br> + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + <strong>IO Type Qualifiers</strong> are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref __NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref __NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = 0x0U; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = 0x0U; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the + function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm33.h b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm33.h new file mode 100755 index 00000000..7249e133 --- /dev/null +++ b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm33.h @@ -0,0 +1,2908 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + /* Copyright (c) 2019 Modified by Dialog Semiconductor */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include <stdint.h> + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.<br> + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.<br> + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + <strong>IO Type Qualifiers</strong> are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref __NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with \ref __NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the + function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the + function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b> + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/mpu_armv8.h b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/mpu_armv8.h new file mode 100755 index 00000000..bc3b0510 --- /dev/null +++ b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/mpu_armv8.h @@ -0,0 +1,347 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + /* Copyright (c) 2019 Modified by Dialog Semiconductor */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \param XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/system_ARMCM0.h b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/system_ARMCM0.h new file mode 100755 index 00000000..7fe7e914 --- /dev/null +++ b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/system_ARMCM0.h @@ -0,0 +1,55 @@ +/**************************************************************************//** + * @file system_ARMCM0.h + * @brief CMSIS Device System Header File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef SYSTEM_ARMCM0_H +#define SYSTEM_ARMCM0_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_ARMCM0_H */ diff --git a/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/system_DA1469x.h b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/system_DA1469x.h new file mode 100755 index 00000000..6c53ee9a --- /dev/null +++ b/tinyusb/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/system_DA1469x.h @@ -0,0 +1,72 @@ +/**************************************************************************//** + * @file system_DA1469x.h + * @brief CMSIS Device System Header File for DA1469x Device + * @version V5.3.1 + * @date 17. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* Copyright (c) 2017 Modified by Dialog Semiconductor */ + + +#ifndef SYSTEM_DA1469x_H +#define SYSTEM_DA1469x_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <stdint.h> +#include <stdbool.h> + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +/** + * \brief Convert a CPU address to a physical address + * + * To calculate the physical address, the current remapping (SYS_CTRL_REG.REMAP_ADR0) + * is used. + * + * \param [in] addr address seen by CPU + * + * \return physical address (for DMA, AES/HASH etc.) -- can be same or different as addr + * + */ +extern uint32_t black_orca_phy_addr(uint32_t addr); + + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_DA1469x_H */ diff --git a/tinyusb/hw/mcu/dialog/da1469x/da1469x.ld b/tinyusb/hw/mcu/dialog/da1469x/da1469x.ld new file mode 100755 index 00000000..c91dea84 --- /dev/null +++ b/tinyusb/hw/mcu/dialog/da1469x/da1469x.ld @@ -0,0 +1,228 @@ +/* Linker script for Dialog DA1469x devices + * + * Version: Sourcery G++ 4.5-1 + * Support: https://support.codesourcery.com/GNUToolchain/ + * + * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __bssnz_start__ + * __bssnz_end__ + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .imghdr (NOLOAD): + { + . = . + _imghdr_size; + } > FLASH + + __text = .; + + .text : + { + __isr_vector_start = .; + KEEP(*(.isr_vector)) + /* ISR vector shall have exactly 512 bytes */ + . = __isr_vector_start + 0x200; + __isr_vector_end = .; + + *(.text) + *(.text.*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + *(.eh_frame*) + . = ALIGN(4); + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + . = ALIGN(4); + } > FLASH + __exidx_end = .; + + .intvect : + { + . = ALIGN(4); + __intvect_start__ = .; + . = . + (__isr_vector_end - __isr_vector_start); + . = ALIGN(4); + } > RAM + + .sleep_state (NOLOAD) : + { + . = ALIGN(4); + *(sleep_state) + } > RAM + + /* This section will be zeroed by RTT package init */ + .rtt (NOLOAD): + { + . = ALIGN(4); + *(.rtt) + . = ALIGN(4); + } > RAM + + __text_ram_addr = LOADADDR(.text_ram); + + .text_ram : + { + . = ALIGN(4); + __text_ram_start__ = .; + *(.text_ram*) + . = ALIGN(4); + __text_ram_end__ = .; + } > RAM AT > FLASH + + __etext = LOADADDR(.data); + + .data : + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + *(.preinit_array) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + *(SORT(.init_array.*)) + *(.init_array) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + *(SORT(.fini_array.*)) + *(.fini_array) + PROVIDE_HIDDEN (__fini_array_end = .); + + *(.jcr) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + } > RAM AT > FLASH + + .bssnz : + { + . = ALIGN(4); + __bssnz_start__ = .; + *(.bss.core.nz*) + . = ALIGN(4); + __bssnz_end__ = .; + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .cmac (NOLOAD) : + { + . = ALIGN(0x400); + *(.libcmac.ram) + } > RAM + + /* Heap starts after BSS */ + . = ALIGN(8); + __HeapBase = .; + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + _ram_start = ORIGIN(RAM); + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Top of head is the bottom of the stack */ + __HeapLimit = __StackLimit; + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__HeapBase <= __HeapLimit, "region RAM overflowed with stack") + + /* Check that intvect is at the beginning of RAM */ + ASSERT(__intvect_start__ == ORIGIN(RAM), "intvect is not at beginning of RAM") +} + diff --git a/tinyusb/hw/mcu/dialog/da1469x/include/hal/hal_gpio.h b/tinyusb/hw/mcu/dialog/da1469x/include/hal/hal_gpio.h new file mode 100755 index 00000000..67fc3c14 --- /dev/null +++ b/tinyusb/hw/mcu/dialog/da1469x/include/hal/hal_gpio.h @@ -0,0 +1,184 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + + +/** + * @addtogroup HAL + * @{ + * @defgroup HALGpio HAL GPIO + * @{ + */ + +#ifndef H_HAL_GPIO_ +#define H_HAL_GPIO_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * The "mode" of the gpio. The gpio is either an input, output, or it is + * "not connected" (the pin specified is not functioning as a gpio) + */ +enum hal_gpio_mode_e { + /** Not connected */ + HAL_GPIO_MODE_NC = -1, + /** Input */ + HAL_GPIO_MODE_IN = 0, + /** Output */ + HAL_GPIO_MODE_OUT = 1 +}; +typedef enum hal_gpio_mode_e hal_gpio_mode_t; + +/* + * The "pull" of the gpio. This is either an input or an output. + */ +enum hal_gpio_pull { + /** Pull-up/down not enabled */ + HAL_GPIO_PULL_NONE = 0, + /** Pull-up enabled */ + HAL_GPIO_PULL_UP = 1, + /** Pull-down enabled */ + HAL_GPIO_PULL_DOWN = 2 +}; +typedef enum hal_gpio_pull hal_gpio_pull_t; + +/* + * IRQ trigger type. + */ +enum hal_gpio_irq_trigger { + HAL_GPIO_TRIG_NONE = 0, + /** IRQ occurs on rising edge */ + HAL_GPIO_TRIG_RISING = 1, + /** IRQ occurs on falling edge */ + HAL_GPIO_TRIG_FALLING = 2, + /** IRQ occurs on either edge */ + HAL_GPIO_TRIG_BOTH = 3, + /** IRQ occurs when line is low */ + HAL_GPIO_TRIG_LOW = 4, + /** IRQ occurs when line is high */ + HAL_GPIO_TRIG_HIGH = 5 +}; +typedef enum hal_gpio_irq_trigger hal_gpio_irq_trig_t; + +/* Function proto for GPIO irq handler functions */ +typedef void (*hal_gpio_irq_handler_t)(void *arg); + +/** + * Initializes the specified pin as an input + * + * @param pin Pin number to set as input + * @param pull pull type + * + * @return int 0: no error; -1 otherwise. + */ +int hal_gpio_init_in(int pin, hal_gpio_pull_t pull); + +/** + * Initialize the specified pin as an output, setting the pin to the specified + * value. + * + * @param pin Pin number to set as output + * @param val Value to set pin + * + * @return int 0: no error; -1 otherwise. + */ +int hal_gpio_init_out(int pin, int val); + +/** + * Deinitialize the specified pin to revert the previous initialization + * + * @param pin Pin number to unset + * + * @return int 0: no error; -1 otherwise. + */ +int hal_gpio_deinit(int pin); + +/** + * Write a value (either high or low) to the specified pin. + * + * @param pin Pin to set + * @param val Value to set pin (0:low 1:high) + */ +void hal_gpio_write(int pin, int val); + +/** + * Reads the specified pin. + * + * @param pin Pin number to read + * + * @return int 0: low, 1: high + */ +int hal_gpio_read(int pin); + +/** + * Toggles the specified pin + * + * @param pin Pin number to toggle + * + * @return current gpio state int 0: low, 1: high + */ +int hal_gpio_toggle(int pin); + +/** + * Initialize a given pin to trigger a GPIO IRQ callback. + * + * @param pin The pin to trigger GPIO interrupt on + * @param handler The handler function to call + * @param arg The argument to provide to the IRQ handler + * @param trig The trigger mode (e.g. rising, falling) + * @param pull The mode of the pin (e.g. pullup, pulldown) + * + * @return 0 on success, non-zero error code on failure. + */ +int hal_gpio_irq_init(int pin, hal_gpio_irq_handler_t handler, void *arg, + hal_gpio_irq_trig_t trig, hal_gpio_pull_t pull); + +/** + * Release a pin from being configured to trigger IRQ on state change. + * + * @param pin The pin to release + */ +void hal_gpio_irq_release(int pin); + +/** + * Enable IRQs on the passed pin + * + * @param pin The pin to enable IRQs on + */ +void hal_gpio_irq_enable(int pin); + +/** + * Disable IRQs on the passed pin + * + * @param pin The pin to disable IRQs on + */ +void hal_gpio_irq_disable(int pin); + + +#ifdef __cplusplus +} +#endif + +#endif /* H_HAL_GPIO_ */ + +/** + * @} HALGpio + * @} HAL + */ diff --git a/tinyusb/hw/mcu/dialog/da1469x/include/mcu/da1469x_clock.h b/tinyusb/hw/mcu/dialog/da1469x/include/mcu/da1469x_clock.h new file mode 100755 index 00000000..3c697747 --- /dev/null +++ b/tinyusb/hw/mcu/dialog/da1469x/include/mcu/da1469x_clock.h @@ -0,0 +1,138 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef __MCU_DA1469X_CLOCK_H_ +#define __MCU_DA1469X_CLOCK_H_ + +#include <stdint.h> +#include "mcu/da1469x_hal.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Initialize XTAL32M + */ +void da1469x_clock_sys_xtal32m_init(void); + +/** + * Enable XTAL32M + */ +void da1469x_clock_sys_xtal32m_enable(void); + +/** + * Wait for XTAL32M to settle + */ +void da1469x_clock_sys_xtal32m_wait_to_settle(void); + +/** + * Switch sys_clk to XTAL32M + * + * Caller shall ensure that XTAL32M is already settled. + */ +void da1469x_clock_sys_xtal32m_switch(void); + +/** + * Switch sys_clk to XTAL32M + * + * Waits for XTAL32M to settle before switching. + */ +void da1469x_clock_sys_xtal32m_switch_safe(void); + +/** + * Disable RC32M + */ +void da1469x_clock_sys_rc32m_disable(void); + +/** + * Enable AMBA clock(s) + * + * @param mask + */ +static inline void +da1469x_clock_amba_enable(uint32_t mask) +{ + uint32_t primask; + + __HAL_DISABLE_INTERRUPTS(primask); + CRG_TOP->CLK_AMBA_REG |= mask; + __HAL_ENABLE_INTERRUPTS(primask); +} + +/** + * Disable AMBA clock(s) + * + * @param uint32_t mask + */ +static inline void +da1469x_clock_amba_disable(uint32_t mask) +{ + uint32_t primask; + + __HAL_DISABLE_INTERRUPTS(primask); + CRG_TOP->CLK_AMBA_REG &= ~mask; + __HAL_ENABLE_INTERRUPTS(primask); +} + +/** + * Enable PLL96 + */ +static inline void +da1469x_clock_sys_pll_enable(void) +{ + CRG_XTAL->PLL_SYS_CTRL1_REG |= CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_EN_Msk | + CRG_XTAL_PLL_SYS_CTRL1_REG_LDO_PLL_ENABLE_Msk; +} + +/** + * Disable PLL96 + * + * If PLL was used as SYS_CLOCK switches to XTAL32M. + */ +void da1469x_clock_sys_pll_disable(void); + +/** + * Checks whether PLL96 is locked and can be use as system clock or USB clock + * + * @return 0 if PLL is off, non-0 it its running + */ +static inline int +da1469x_clock_is_pll_locked(void) +{ + return 0 != (CRG_XTAL->PLL_SYS_STATUS_REG & CRG_XTAL_PLL_SYS_STATUS_REG_PLL_LOCK_FINE_Msk); +} + +/** + * Waits for PLL96 to lock. + */ +void da1469x_clock_pll_wait_to_lock(void); + +/** + * Switches system clock to PLL96 + * + * Caller shall ensure that PLL is already locked. + */ +void da1469x_clock_sys_pll_switch(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __MCU_DA1469X_CLOCK_H_ */ diff --git a/tinyusb/hw/mcu/dialog/da1469x/include/mcu/da1469x_hal.h b/tinyusb/hw/mcu/dialog/da1469x/include/mcu/da1469x_hal.h new file mode 100755 index 00000000..28fa1aa8 --- /dev/null +++ b/tinyusb/hw/mcu/dialog/da1469x/include/mcu/da1469x_hal.h @@ -0,0 +1,53 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef __MCU_DA1469X_HAL_H_ +#define __MCU_DA1469X_HAL_H_ + +#include <assert.h> +#include "mcu/mcu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Helper functions to enable/disable interrupts. */ +#define __HAL_DISABLE_INTERRUPTS(x) \ + do { \ + x = __get_PRIMASK(); \ + __disable_irq(); \ + } while (0) + +#define __HAL_ENABLE_INTERRUPTS(x) \ + do { \ + if (!x) { \ + __enable_irq(); \ + } \ + } while (0) + +#define __HAL_ASSERT_CRITICAL() \ + do { \ + assert(__get_PRIMASK() & 1); \ + } while (0) + +#ifdef __cplusplus +} +#endif + +#endif /* __MCU_DA1469X_HAL_H_ */ diff --git a/tinyusb/hw/mcu/dialog/da1469x/include/mcu/mcu.h b/tinyusb/hw/mcu/dialog/da1469x/include/mcu/mcu.h new file mode 100755 index 00000000..1e673678 --- /dev/null +++ b/tinyusb/hw/mcu/dialog/da1469x/include/mcu/mcu.h @@ -0,0 +1,165 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef __MCU_MCU_H_ +#define __MCU_MCU_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "DA1469xAB.h" + +#define sec_text_ram_core __attribute__((section(".text_ram"))) __attribute__((noinline)) + +#define MCU_SYSVIEW_INTERRUPTS \ + "I#1=Reset,I#2=MNI,I#3=HardFault,I#4=MemoryMgmt,I#5=BusFault,I#6=UsageFault," \ + "I#7=SecureFault,I#11=SVCall,I#12=DebugMonitor,I#14=PendSV,I#15=SysTick," \ + "I#16=SENSOR_NODE,I#17=DMA,I#18=CHARGER_STATE,I#19=CHARGER_ERROR," \ + "I#20=CMAC2SYS,I#21=UART,I#22=UART2,I#23=UART3,I#24=I2C,I#25=I2C2,I#26=SPI," \ + "I#27=SPI2,I#28=PCM,I#29=SRC_IN,I#30=SRC_OUT,I#31=USB,I#32=TIMER," \ + "I#33=TIMER2,I#34=RTC,I#35=KEY_WKUP_GPIO,I#36=PDC,I#37=VBUS,I#38=MRM," \ + "I#39=MOTOR_CONTROLLER,I#40=TRNG,I#41=DCDC,I#42=XTAL32M_RDY,I#43=ADC," \ + "I#44=ADC2,I#45=CRYPTO,I#46=CAPTIMER1,I#47=RFDIAG,I#48=LCD_CONTROLLER," \ + "I#49=PLL_LOCK,I#50=TIMER3,I#51=TIMER4,I#52=LRA,I#53=RTC_EVENT," \ + "I#54=GPIO_P0,I#55=GPIO_P1" + +/** +* \brief GPIO function +* +*/ +typedef enum { + MCU_GPIO_FUNC_GPIO = 0, /**< GPIO */ + MCU_GPIO_FUNC_UART_RX = 1, /**< GPIO as UART RX */ + MCU_GPIO_FUNC_UART_TX = 2, /**< GPIO as UART TX */ + MCU_GPIO_FUNC_UART2_RX = 3, /**< GPIO as UART2 RX */ + MCU_GPIO_FUNC_UART2_TX = 4, /**< GPIO as UART2 TX */ + MCU_GPIO_FUNC_UART2_CTSN = 5, /**< GPIO as UART2 CTSN */ + MCU_GPIO_FUNC_UART2_RTSN = 6, /**< GPIO as UART2 RTSN */ + MCU_GPIO_FUNC_UART3_RX = 7, /**< GPIO as UART3 RX */ + MCU_GPIO_FUNC_UART3_TX = 8, /**< GPIO as UART3 TX */ + MCU_GPIO_FUNC_UART3_CTSN = 9, /**< GPIO as UART3 CTSN */ + MCU_GPIO_FUNC_UART3_RTSN = 10, /**< GPIO as UART3 RTSN */ + MCU_GPIO_FUNC_ISO_CLK = 11, /**< GPIO as ISO CLK */ + MCU_GPIO_FUNC_ISO_DATA = 12, /**< GPIO as ISO DATA */ + MCU_GPIO_FUNC_SPI_DI = 13, /**< GPIO as SPI DI */ + MCU_GPIO_FUNC_SPI_DO = 14, /**< GPIO as SPI DO */ + MCU_GPIO_FUNC_SPI_CLK = 15, /**< GPIO as SPI CLK */ + MCU_GPIO_FUNC_SPI_EN = 16, /**< GPIO as SPI EN */ + MCU_GPIO_FUNC_SPI2_DI = 17, /**< GPIO as SPI2 DI */ + MCU_GPIO_FUNC_SPI2_DO = 18, /**< GPIO as SPI2 DO */ + MCU_GPIO_FUNC_SPI2_CLK = 19, /**< GPIO as SPI2 CLK */ + MCU_GPIO_FUNC_SPI2_EN = 20, /**< GPIO as SPI2 EN */ + MCU_GPIO_FUNC_I2C_SCL = 21, /**< GPIO as I2C SCL */ + MCU_GPIO_FUNC_I2C_SDA = 22, /**< GPIO as I2C SDA */ + MCU_GPIO_FUNC_I2C2_SCL = 23, /**< GPIO as I2C2 SCL */ + MCU_GPIO_FUNC_I2C2_SDA = 24, /**< GPIO as I2C2 SDA */ + MCU_GPIO_FUNC_USB_SOF = 25, /**< GPIO as USB SOF */ + MCU_GPIO_FUNC_ADC = 26, /**< GPIO as ADC (dedicated pin) */ + MCU_GPIO_FUNC_USB = 27, /**< GPIO as USB */ + MCU_GPIO_FUNC_PCM_DI = 28, /**< GPIO as PCM DI */ + MCU_GPIO_FUNC_PCM_DO = 29, /**< GPIO as PCM DO */ + MCU_GPIO_FUNC_PCM_FSC = 30, /**< GPIO as PCM FSC */ + MCU_GPIO_FUNC_PCM_CLK = 31, /**< GPIO as PCM CLK */ + MCU_GPIO_FUNC_PDM_DATA = 32, /**< GPIO as PDM DATA */ + MCU_GPIO_FUNC_PDM_CLK = 33, /**< GPIO as PDM CLK */ + MCU_GPIO_FUNC_COEX_EXT_ACT = 34, /**< GPIO as COEX EXT ACT0 */ + MCU_GPIO_FUNC_COEX_SMART_ACT = 35, /**< GPIO as COEX SMART ACT */ + MCU_GPIO_FUNC_COEX_SMART_PRI = 36, /**< GPIO as COEX SMART PRI */ + MCU_GPIO_FUNC_PORT0_DCF = 37, /**< GPIO as PORT0 DCF */ + MCU_GPIO_FUNC_PORT1_DCF = 38, /**< GPIO as PORT1 DCF */ + MCU_GPIO_FUNC_PORT2_DCF = 39, /**< GPIO as PORT2 DCF */ + MCU_GPIO_FUNC_PORT3_DCF = 40, /**< GPIO as PORT3 DCF */ + MCU_GPIO_FUNC_PORT4_DCF = 41, /**< GPIO as PORT4 DCF */ + MCU_GPIO_FUNC_CLOCK = 42, /**< GPIO as CLOCK */ + MCU_GPIO_FUNC_PG = 43, /**< GPIO as PG */ + MCU_GPIO_FUNC_LCD = 44, /**< GPIO as LCD */ + MCU_GPIO_FUNC_LCD_SPI_DC = 45, /**< GPIO as LCD SPI DC */ + MCU_GPIO_FUNC_LCD_SPI_DO = 46, /**< GPIO as LCD SPI DO */ + MCU_GPIO_FUNC_LCD_SPI_CLK = 47, /**< GPIO as LCD SPI CLK */ + MCU_GPIO_FUNC_LCD_SPI_EN = 48, /**< GPIO as LCD SPI EN */ + MCU_GPIO_FUNC_TIM_PWM = 49, /**< GPIO as TIM PWM */ + MCU_GPIO_FUNC_TIM2_PWM = 50, /**< GPIO as TIM2 PWM */ + MCU_GPIO_FUNC_TIM_1SHOT = 51, /**< GPIO as TIM 1SHOT */ + MCU_GPIO_FUNC_TIM2_1SHOT = 52, /**< GPIO as TIM2 1SHOT */ + MCU_GPIO_FUNC_TIM3_PWM = 53, /**< GPIO as TIM3 PWM */ + MCU_GPIO_FUNC_TIM4_PWM = 54, /**< GPIO as TIM4 PWM */ + MCU_GPIO_FUNC_AGC_EXT = 55, /**< GPIO as AGC EXT */ + MCU_GPIO_FUNC_CMAC_DIAG0 = 56, /**< GPIO as CMAC DIAG0 */ + MCU_GPIO_FUNC_CMAC_DIAG1 = 57, /**< GPIO as CMAC DIAG1 */ + MCU_GPIO_FUNC_CMAC_DIAG2 = 58, /**< GPIO as CMAC DIAG2 */ + MCU_GPIO_FUNC_CMAC_DIAGX = 59, /**< GPIO as CMAC DIAGX */ + MCU_GPIO_FUNC_LAST, +} mcu_gpio_func; + +#define MCU_GPIO_MODE_INPUT 0x000 /**< GPIO as an input */ +#define MCU_GPIO_MODE_INPUT_PULLUP 0x100 /**< GPIO as an input with pull-up */ +#define MCU_GPIO_MODE_INPUT_PULLDOWN 0x200 /**< GPIO as an input with pull-down */ +#define MCU_GPIO_MODE_OUTPUT 0x300 /**< GPIO as an output */ +#define MCU_GPIO_MODE_OUTPUT_OPEN_DRAIN 0x700 /**< GPIO as an open-drain output */ + +#define MCU_GPIO_PORT0_PIN_COUNT 32 +#define MCU_GPIO_PORT0(pin) ((0 * 32) + (pin)) +#define MCU_GPIO_PORT1(pin) ((1 * 32) + (pin)) +#define MCU_DMA_CHAN_MAX 8 + +#define MCU_PIN_GPADC_SEL0 MCU_GPIO_PORT1(9) +#define MCU_PIN_GPADC_SEL1 MCU_GPIO_PORT0(25) +#define MCU_PIN_GPADC_SEL2 MCU_GPIO_PORT0(8) +#define MCU_PIN_GPADC_SEL3 MCU_GPIO_PORT0(9) +#define MCU_PIN_GPADC_SEL16 MCU_GPIO_PORT1(13) +#define MCU_PIN_GPADC_SEL17 MCU_GPIO_PORT1(12) +#define MCU_PIN_GPADC_SEL18 MCU_GPIO_PORT1(18) +#define MCU_PIN_GPADC_SEL19 MCU_GPIO_PORT1(19) +#define MCU_PIN_GPADC_DIFF0_P0 MCU_GPIO_PORT1(9) +#define MCU_PIN_GPADC_DIFF0_P1 MCU_GPIO_PORT0(25) +#define MCU_PIN_GPADC_DIFF1_P0 MCU_GPIO_PORT0(8) +#define MCU_PIN_GPADC_DIFF1_P1 MCU_GPIO_PORT0(9) + +#define MCU_PIN_SDADC0 MCU_GPIO_PORT1(9) +#define MCU_PIN_SDADC1 MCU_GPIO_PORT0(25) +#define MCU_PIN_SDADC2 MCU_GPIO_PORT0(8) +#define MCU_PIN_SDADC3 MCU_GPIO_PORT0(9) +#define MCU_PIN_SDADC4 MCU_GPIO_PORT1(14) +#define MCU_PIN_SDADC5 MCU_GPIO_PORT1(20) +#define MCU_PIN_SDADC6 MCU_GPIO_PORT1(21) +#define MCU_PIN_SDADC7 MCU_GPIO_PORT1(22) + +void mcu_gpio_set_pin_function(int pin, int mode, mcu_gpio_func func); +void mcu_gpio_enter_sleep(void); +void mcu_gpio_exit_sleep(void); + +#define MCU_MEM_QSPIF_M_END_REMAP_ADDRESS (0x800000) +#define MCU_MEM_QSPIF_M_START_ADDRESS (0x16000000) +#define MCU_MEM_QSPIF_M_END_ADDRESS (0x18000000) +#define MCU_MEM_SYSRAM_START_ADDRESS (0x20000000) +#define MCU_MEM_SYSRAM_END_ADDRESS (0x20080000) + +#define MCU_OTPM_BASE 0x30080000UL +#define MCU_OTPM_SIZE 4096 + +/* Largest group id seen on a DA14699 was 18 so far */ +#define MCU_TRIMV_GROUP_ID_MAX (18) + +#ifdef __cplusplus +} +#endif + +#endif /* __MCU_MCU_H_ */ + diff --git a/tinyusb/hw/mcu/dialog/da1469x/src/da1469x_clock.c b/tinyusb/hw/mcu/dialog/da1469x/src/da1469x_clock.c new file mode 100755 index 00000000..6b4f0e6c --- /dev/null +++ b/tinyusb/hw/mcu/dialog/da1469x/src/da1469x_clock.c @@ -0,0 +1,159 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include <assert.h> +#include <stdbool.h> +#include <stdint.h> +#include "syscfg/syscfg.h" +#include "mcu/da1469x_hal.h" +#include "mcu/da1469x_clock.h" + +static inline bool +da1469x_clock_is_xtal32m_settled(void) +{ + return ((*(uint32_t *)0x5001001c & 0xff00) == 0) && + ((*(uint32_t *)0x50010054 & 0x000f) != 0xb); +} + +void +da1469x_clock_sys_xtal32m_init(void) +{ + uint32_t reg; + int xtalrdy_cnt; + + /* Number of lp_clk cycles (~30.5us) */ + xtalrdy_cnt = MYNEWT_VAL(MCU_CLOCK_XTAL32M_SETTLE_TIME_US) * 10 / 305; + + reg = CRG_XTAL->XTALRDY_CTRL_REG; + reg &= ~(CRG_XTAL_XTALRDY_CTRL_REG_XTALRDY_CLK_SEL_Msk | + CRG_XTAL_XTALRDY_CTRL_REG_XTALRDY_CNT_Msk); + reg |= xtalrdy_cnt; + CRG_XTAL->XTALRDY_CTRL_REG = reg; +} + +void +da1469x_clock_sys_xtal32m_enable(void) +{ + PDC->PDC_CTRL0_REG = (2 << PDC_PDC_CTRL0_REG_TRIG_SELECT_Pos) | + (15 << PDC_PDC_CTRL0_REG_TRIG_ID_Pos) | + (1 << PDC_PDC_CTRL0_REG_PDC_MASTER_Pos) | + (1 << PDC_PDC_CTRL0_REG_EN_XTAL_Pos); + + PDC->PDC_SET_PENDING_REG = 0; + PDC->PDC_ACKNOWLEDGE_REG = 0; +} + +void +da1469x_clock_sys_xtal32m_switch(void) +{ + if (CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC32M_Msk) { + CRG_TOP->CLK_SWITCH2XTAL_REG = CRG_TOP_CLK_SWITCH2XTAL_REG_SWITCH2XTAL_Msk; + } else { + CRG_TOP->CLK_CTRL_REG &= ~CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk; + } + + while (!(CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL32M_Msk)); +} + +void +da1469x_clock_sys_xtal32m_wait_to_settle(void) +{ + uint32_t primask; + + __HAL_DISABLE_INTERRUPTS(primask); + + NVIC_ClearPendingIRQ(XTAL32M_RDY_IRQn); + + if (!da1469x_clock_is_xtal32m_settled()) { + NVIC_EnableIRQ(XTAL32M_RDY_IRQn); + while (!NVIC_GetPendingIRQ(XTAL32M_RDY_IRQn)) { + __WFI(); + } + NVIC_DisableIRQ(XTAL32M_RDY_IRQn); + } + + __HAL_ENABLE_INTERRUPTS(primask); +} + +void +da1469x_clock_sys_xtal32m_switch_safe(void) +{ + da1469x_clock_sys_xtal32m_wait_to_settle(); + + da1469x_clock_sys_xtal32m_switch(); +} + +void +da1469x_clock_sys_rc32m_disable(void) +{ + CRG_TOP->CLK_RC32M_REG &= ~CRG_TOP_CLK_RC32M_REG_RC32M_ENABLE_Msk; +} + +void +da1469x_clock_lp_xtal32k_enable(void) +{ + CRG_TOP->CLK_XTAL32K_REG |= CRG_TOP_CLK_XTAL32K_REG_XTAL32K_ENABLE_Msk; +} + +void +da1469x_clock_lp_xtal32k_switch(void) +{ + CRG_TOP->CLK_CTRL_REG = (CRG_TOP->CLK_CTRL_REG & + ~CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk) | + (2 << CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos); +} + +void +da1469x_clock_pll_disable(void) +{ + while (CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Msk) { + CRG_TOP->CLK_SWITCH2XTAL_REG = CRG_TOP_CLK_SWITCH2XTAL_REG_SWITCH2XTAL_Msk; + } + + CRG_XTAL->PLL_SYS_CTRL1_REG &= ~CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_EN_Msk; +} + +void +da1469x_clock_pll_wait_to_lock(void) +{ + uint32_t primask; + + __HAL_DISABLE_INTERRUPTS(primask); + + NVIC_ClearPendingIRQ(PLL_LOCK_IRQn); + + if (!da1469x_clock_is_pll_locked()) { + NVIC_EnableIRQ(PLL_LOCK_IRQn); + while (!NVIC_GetPendingIRQ(PLL_LOCK_IRQn)) { + __WFI(); + } + NVIC_DisableIRQ(PLL_LOCK_IRQn); + } + + __HAL_ENABLE_INTERRUPTS(primask); +} + +void +da1469x_clock_sys_pll_switch(void) +{ + /* CLK_SEL_Msk == 3 means PLL */ + CRG_TOP->CLK_CTRL_REG |= CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk; + + while (!(CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Msk)); +} diff --git a/tinyusb/hw/mcu/dialog/da1469x/src/hal_gpio.c b/tinyusb/hw/mcu/dialog/da1469x/src/hal_gpio.c new file mode 100755 index 00000000..e105cf2b --- /dev/null +++ b/tinyusb/hw/mcu/dialog/da1469x/src/hal_gpio.c @@ -0,0 +1,478 @@ + +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include <assert.h> +#include <stddef.h> +#include "syscfg/syscfg.h" +#include "mcu/da1469x_hal.h" +#include <mcu/mcu.h> +#include "hal/hal_gpio.h" + +/* GPIO interrupts */ +#define HAL_GPIO_MAX_IRQ MYNEWT_VAL(MCU_GPIO_MAX_IRQ) + +#define GPIO_REG(name) ((__IO uint32_t *)(GPIO_BASE + offsetof(GPIO_Type, name))) +#define WAKEUP_REG(name) ((__IO uint32_t *)(WAKEUP_BASE + offsetof(WAKEUP_Type, name))) +#define CRG_TOP_REG(name) ((__IO uint32_t *)(CRG_TOP_BASE + offsetof(CRG_TOP_Type, name))) + +#ifndef MCU_GPIO_PORT0_PIN_COUNT +#define MCU_GPIO_PORT0_PIN_COUNT 32 +#endif + +#if (MCU_GPIO_PORT0_PIN_COUNT) == 32 +#define GPIO_PORT(pin) (((unsigned)(pin)) >> 5U) +#define GPIO_PORT_PIN(pin) (((unsigned)(pin)) & 31U) +#else +#define GPIO_PORT(pin) (((unsigned)(pin)) < MCU_GPIO_PORT0_PIN_COUNT ? 0 : 1) +#define GPIO_PORT_PIN(pin) ((unsigned)(pin) < MCU_GPIO_PORT0_PIN_COUNT ? \ + (pin) : (pin) - MCU_GPIO_PORT0_PIN_COUNT) +#endif + +#define GPIO_PIN_BIT(pin) (1 << GPIO_PORT_PIN(pin)) + +#define GPIO_PIN_DATA_REG_ADDR(pin) (GPIO_REG(P0_DATA_REG) + GPIO_PORT(pin)) +#define GPIO_PIN_DATA_REG(pin) *GPIO_PIN_DATA_REG_ADDR(pin) +#define GPIO_PIN_SET_DATA_REG_ADDR(pin) (GPIO_REG(P0_SET_DATA_REG) + GPIO_PORT(pin)) +#define GPIO_PIN_SET_DATA_REG(pin) *GPIO_PIN_SET_DATA_REG_ADDR(pin) +#define GPIO_PIN_RESET_DATA_REG_ADDR(pin) (GPIO_REG(P0_RESET_DATA_REG) + GPIO_PORT(pin)) +#define GPIO_PIN_RESET_DATA_REG(pin) *GPIO_PIN_RESET_DATA_REG_ADDR(pin) +#define GPIO_PIN_MODE_REG_ADDR(pin) (GPIO_REG(P0_00_MODE_REG) + (pin)) +#define GPIO_PIN_MODE_REG(pin) *GPIO_PIN_MODE_REG_ADDR(pin) +#define GPIO_PIN_PADPWR_CTRL_REG_ADDR(pin) (GPIO_REG(P0_PADPWR_CTRL_REG) + GPIO_PORT(pin)) +#define GPIO_PIN_PADPWR_CTRL_REG(pin) *GPIO_PIN_PADPWR_CTRL_REG_ADDR(pin) +#define GPIO_PIN_UNLATCH_ADDR(pin) (CRG_TOP_REG(P0_SET_PAD_LATCH_REG) + GPIO_PORT(pin) * 3) +#define GPIO_PIN_LATCH_ADDR(pin) (CRG_TOP_REG(P0_RESET_PAD_LATCH_REG) + GPIO_PORT(pin) * 3) + +#define WKUP_CTRL_REG_ADDR (WAKEUP_REG(WKUP_CTRL_REG)) +#define WKUP_RESET_IRQ_REG_ADDR (WAKEUP_REG(WKUP_RESET_IRQ_REG)) +#define WKUP_SELECT_PX_REG_ADDR(pin) (WAKEUP_REG(WKUP_SELECT_P0_REG) + GPIO_PORT(pin)) +#define WKUP_SELECT_PX_REG(pin) *(WKUP_SELECT_PX_REG_ADDR(pin)) +#define WKUP_POL_PX_REG_ADDR(pin) (WAKEUP_REG(WKUP_POL_P0_REG) + GPIO_PORT(pin)) +#define WKUP_POL_PX_SET_FALLING(pin) do { *(WKUP_POL_PX_REG_ADDR(pin)) |= GPIO_PIN_BIT(pin); } while (0) +#define WKUP_POL_PX_SET_RISING(pin) do { *(WKUP_POL_PX_REG_ADDR(pin)) &= ~GPIO_PIN_BIT(pin); } while (0) +#define WKUP_STAT_PX_REG_ADDR(pin) (WAKEUP_REG(WKUP_STATUS_P0_REG) + GPIO_PORT(pin)) +#define WKUP_STAT(pin) ((*(WKUP_STAT_PX_REG_ADDR(pin)) >> GPIO_PORT_PIN(pin)) & 1) +#define WKUP_CLEAR_PX_REG_ADDR(pin) (WAKEUP_REG(WKUP_CLEAR_P0_REG) + GPIO_PORT(pin)) +#define WKUP_CLEAR_PX(pin) do { (*(WKUP_CLEAR_PX_REG_ADDR(pin)) = GPIO_PIN_BIT(pin)); } while (0) +#define WKUP_SEL_GPIO_PX_REG_ADDR(pin) (WAKEUP_REG(WKUP_SEL_GPIO_P0_REG) + GPIO_PORT(pin)) +#define WKUP_SEL_GPIO_PX_REG(pin) *(WKUP_SEL_GPIO_PX_REG_ADDR(pin)) + +/* Storage for GPIO callbacks. */ +struct hal_gpio_irq { + int pin; + hal_gpio_irq_handler_t func; + void *arg; +}; + +static struct hal_gpio_irq hal_gpio_irqs[HAL_GPIO_MAX_IRQ]; + +#if MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM) >= 0 +static uint32_t g_mcu_gpio_latch_state[2]; +static uint8_t g_mcu_gpio_retained_num; +static struct da1469x_retreg g_mcu_gpio_retained[MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM)]; +#endif + +/* + * We assume that any latched pin has default configuration, i.e. was either + * not configured or was deinited. Any unlatched pin is considered to be used + * by someone. + * + * By default, all pins are assumed to have default configuration and are + * latched. This allows PD_COM to be disabled (if no other peripheral needs + * it) since we do not need GPIO mux to be active. + * + * Configuration of any pin shall be done as follows, with interrupts disabled: + * 1. call mcu_gpio_unlatch_prepare() to enable PD_COM if needed + * 2. configure pin + * 3. call mcu_gpio_unlatch() to actually unlatch pin + * + * Once pin is restored to default configuration it shall be latched again by + * calling mcu_gpio_latch(). + */ + +#if MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM) >= 0 +static void +mcu_gpio_retained_add_port(uint32_t latch_val, volatile uint32_t *base_reg) +{ + struct da1469x_retreg *retreg; + int pin; + + retreg = &g_mcu_gpio_retained[g_mcu_gpio_retained_num]; + + while (latch_val) { + assert(g_mcu_gpio_retained_num < MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM)); + + pin = __builtin_ctz(latch_val); + latch_val &= ~(1 << pin); + + da1469x_retreg_assign(retreg, &base_reg[pin]); + + g_mcu_gpio_retained_num++; + retreg++; + } +} +#endif + +static void +mcu_gpio_retained_refresh(void) +{ +#if MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM) >= 0 + g_mcu_gpio_retained_num = 0; + + mcu_gpio_retained_add_port(CRG_TOP->P0_PAD_LATCH_REG, &GPIO->P0_00_MODE_REG); + mcu_gpio_retained_add_port(CRG_TOP->P1_PAD_LATCH_REG, &GPIO->P1_00_MODE_REG); +#endif +} + +static inline void +mcu_gpio_unlatch_prepare(int pin) +{ + __HAL_ASSERT_CRITICAL(); + (void)pin; + + /* Acquire PD_COM if first pin will be unlatched */ +// if ((CRG_TOP->P0_PAD_LATCH_REG | CRG_TOP->P1_PAD_LATCH_REG) == 0) { +// da1469x_pd_acquire(MCU_PD_DOMAIN_COM); +// } +} + +static inline void +mcu_gpio_unlatch(int pin) +{ + __HAL_ASSERT_CRITICAL(); + + *GPIO_PIN_UNLATCH_ADDR(pin) = GPIO_PIN_BIT(pin); + mcu_gpio_retained_refresh(); +} + +static inline void +mcu_gpio_latch(int pin) +{ + (void)pin; +// uint32_t primask; +// uint32_t latch_pre; +// uint32_t latch_post; +// +// __HAL_DISABLE_INTERRUPTS(primask); +// +// latch_pre = CRG_TOP->P0_PAD_LATCH_REG | CRG_TOP->P1_PAD_LATCH_REG; +// +// *GPIO_PIN_LATCH_ADDR(pin) = GPIO_PIN_BIT(pin); +// mcu_gpio_retained_refresh(); +// +// latch_post = CRG_TOP->P0_PAD_LATCH_REG | CRG_TOP->P1_PAD_LATCH_REG; +// +// /* Release PD_COM if last pin was latched */ +// if (latch_pre && !latch_post) { +// da1469x_pd_release(MCU_PD_DOMAIN_COM); +// } +// +// __HAL_ENABLE_INTERRUPTS(primask); +} + +int +hal_gpio_init_in(int pin, hal_gpio_pull_t pull) +{ + volatile uint32_t *px_xx_mod_reg = GPIO_PIN_MODE_REG_ADDR(pin); + uint32_t regval; + uint32_t primask; + + switch (pull) { + case HAL_GPIO_PULL_UP: + regval = MCU_GPIO_FUNC_GPIO | MCU_GPIO_MODE_INPUT_PULLUP; + break; + case HAL_GPIO_PULL_DOWN: + regval = MCU_GPIO_FUNC_GPIO | MCU_GPIO_MODE_INPUT_PULLDOWN; + break; + case HAL_GPIO_PULL_NONE: + regval = MCU_GPIO_FUNC_GPIO | MCU_GPIO_MODE_INPUT; + break; + default: + return -1; + } + + __HAL_DISABLE_INTERRUPTS(primask); + + mcu_gpio_unlatch_prepare(pin); + + *px_xx_mod_reg = regval; + + mcu_gpio_unlatch(pin); + + __HAL_ENABLE_INTERRUPTS(primask); + + return 0; +} + +int +hal_gpio_init_out(int pin, int val) +{ + uint32_t primask; + + __HAL_DISABLE_INTERRUPTS(primask); + + mcu_gpio_unlatch_prepare(pin); + + GPIO_PIN_MODE_REG(pin) = MCU_GPIO_MODE_OUTPUT; + + if (val) { + GPIO_PIN_SET_DATA_REG(pin) = GPIO_PIN_BIT(pin); + } else { + GPIO_PIN_RESET_DATA_REG(pin) = GPIO_PIN_BIT(pin); + } + + mcu_gpio_unlatch(pin); + + __HAL_ENABLE_INTERRUPTS(primask); + + return 0; +} + +int +hal_gpio_deinit(int pin) +{ + /* Reset mode to default value and latch pin */ + GPIO_PIN_MODE_REG(pin) = 0x200; + GPIO_PIN_RESET_DATA_REG(pin) = GPIO_PIN_BIT(pin); + + mcu_gpio_latch(pin); + + return 0; +} + +void +hal_gpio_write(int pin, int val) +{ + if (val) { + GPIO_PIN_SET_DATA_REG(pin) = GPIO_PIN_BIT(pin); + } else { + GPIO_PIN_RESET_DATA_REG(pin) = GPIO_PIN_BIT(pin); + } +} + +int +hal_gpio_read(int pin) +{ + return (GPIO_PIN_DATA_REG(pin) >> GPIO_PORT_PIN(pin)) & 1; +} + +int +hal_gpio_toggle(int pin) +{ + int new_value = hal_gpio_read(pin) == 0; + + hal_gpio_write(pin, new_value); + + return new_value; +} + +static void +hal_gpio_irq_handler(void) +{ + struct hal_gpio_irq *irq; + uint32_t stat; + int i; + + *WKUP_RESET_IRQ_REG_ADDR = 1; + NVIC_ClearPendingIRQ(KEY_WKUP_GPIO_IRQn); + + for (i = 0; i < HAL_GPIO_MAX_IRQ; i++) { + irq = &hal_gpio_irqs[i]; + + /* Read latched status value from relevant GPIO port */ + stat = WKUP_STAT(irq->pin); + + if (irq->func && stat) { + irq->func(irq->arg); + } + + WKUP_CLEAR_PX(irq->pin); + } +} + +static void +hal_gpio_irq_setup(void) +{ + static uint8_t irq_setup; + int sr; + + if (!irq_setup) { + __HAL_DISABLE_INTERRUPTS(sr); + + irq_setup = 1; + + NVIC_ClearPendingIRQ(GPIO_P0_IRQn); + NVIC_ClearPendingIRQ(GPIO_P1_IRQn); + NVIC_SetVector(GPIO_P0_IRQn, (uint32_t)hal_gpio_irq_handler); + NVIC_SetVector(GPIO_P1_IRQn, (uint32_t)hal_gpio_irq_handler); + WAKEUP->WKUP_CTRL_REG = 0; + WAKEUP->WKUP_CLEAR_P0_REG = 0xFFFFFFFF; + WAKEUP->WKUP_CLEAR_P1_REG = 0x007FFFFF; + WAKEUP->WKUP_SELECT_P0_REG = 0; + WAKEUP->WKUP_SELECT_P1_REG = 0; + WAKEUP->WKUP_SEL_GPIO_P0_REG = 0; + WAKEUP->WKUP_SEL_GPIO_P1_REG = 0; + WAKEUP->WKUP_RESET_IRQ_REG = 0; + + CRG_TOP->CLK_TMR_REG |= CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Msk; + + __HAL_ENABLE_INTERRUPTS(sr); + NVIC_EnableIRQ(GPIO_P0_IRQn); + NVIC_EnableIRQ(GPIO_P1_IRQn); + } +} + +static int +hal_gpio_find_empty_slot(void) +{ + int i; + + for (i = 0; i < HAL_GPIO_MAX_IRQ; i++) { + if (hal_gpio_irqs[i].func == NULL) { + return i; + } + } + + return -1; +} + +int +hal_gpio_irq_init(int pin, hal_gpio_irq_handler_t handler, void *arg, + hal_gpio_irq_trig_t trig, hal_gpio_pull_t pull) +{ + int i; + + hal_gpio_irq_setup(); + + i = hal_gpio_find_empty_slot(); + /* If assert failed increase syscfg value MCU_GPIO_MAX_IRQ */ + assert(i >= 0); + if (i < 0) { + return -1; + } + + hal_gpio_init_in(pin, pull); + + switch (trig) { + case HAL_GPIO_TRIG_RISING: + WKUP_POL_PX_SET_RISING(pin); + break; + case HAL_GPIO_TRIG_FALLING: + WKUP_POL_PX_SET_FALLING(pin); + break; + case HAL_GPIO_TRIG_BOTH: + /* Not supported */ + default: + return -1; + } + + hal_gpio_irqs[i].pin = pin; + hal_gpio_irqs[i].func = handler; + hal_gpio_irqs[i].arg = arg; + + return 0; +} + +void +hal_gpio_irq_release(int pin) +{ + int i; + + hal_gpio_irq_disable(pin); + + for (i = 0; i < HAL_GPIO_MAX_IRQ; i++) { + if (hal_gpio_irqs[i].pin == pin && hal_gpio_irqs[i].func) { + hal_gpio_irqs[i].pin = -1; + hal_gpio_irqs[i].arg = NULL; + hal_gpio_irqs[i].func = NULL; + } + } +} + +void +hal_gpio_irq_enable(int pin) +{ + WKUP_SEL_GPIO_PX_REG(pin) |= GPIO_PIN_BIT(pin); +} + +void +hal_gpio_irq_disable(int pin) +{ + WKUP_SEL_GPIO_PX_REG(pin) &= ~GPIO_PIN_BIT(pin); + WKUP_CLEAR_PX(pin); +} + +void +mcu_gpio_set_pin_function(int pin, int mode, mcu_gpio_func func) +{ + uint32_t primask; + + __HAL_DISABLE_INTERRUPTS(primask); + + mcu_gpio_unlatch_prepare(pin); + + GPIO_PIN_MODE_REG(pin) = (func & GPIO_P0_00_MODE_REG_PID_Msk) | + (mode & (GPIO_P0_00_MODE_REG_PUPD_Msk | GPIO_P0_00_MODE_REG_PPOD_Msk)); + + mcu_gpio_unlatch(pin); + + __HAL_ENABLE_INTERRUPTS(primask); +} + +void +mcu_gpio_enter_sleep(void) +{ +#if MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM) >= 0 + if (g_mcu_gpio_retained_num == 0) { + return; + } + + g_mcu_gpio_latch_state[0] = CRG_TOP->P0_PAD_LATCH_REG; + g_mcu_gpio_latch_state[1] = CRG_TOP->P1_PAD_LATCH_REG; + + da1469x_retreg_update(g_mcu_gpio_retained, g_mcu_gpio_retained_num); + + CRG_TOP->P0_RESET_PAD_LATCH_REG = CRG_TOP_P0_PAD_LATCH_REG_P0_LATCH_EN_Msk; + CRG_TOP->P1_RESET_PAD_LATCH_REG = CRG_TOP_P1_PAD_LATCH_REG_P1_LATCH_EN_Msk; + + da1469x_pd_release(MCU_PD_DOMAIN_COM); +#endif +} + +void +mcu_gpio_exit_sleep(void) +{ +#if MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM) >= 0 + if (g_mcu_gpio_retained_num == 0) { + return; + } + + da1469x_pd_acquire(MCU_PD_DOMAIN_COM); + + da1469x_retreg_restore(g_mcu_gpio_retained, g_mcu_gpio_retained_num); + + /* Set pins states to their latched values */ + GPIO->P0_DATA_REG = GPIO->P0_DATA_REG; + GPIO->P1_DATA_REG = GPIO->P1_DATA_REG; + + CRG_TOP->P0_PAD_LATCH_REG = g_mcu_gpio_latch_state[0]; + CRG_TOP->P1_PAD_LATCH_REG = g_mcu_gpio_latch_state[1]; +#endif +} diff --git a/tinyusb/hw/mcu/dialog/da1469x/src/hal_system.c b/tinyusb/hw/mcu/dialog/da1469x/src/hal_system.c new file mode 100755 index 00000000..2841979f --- /dev/null +++ b/tinyusb/hw/mcu/dialog/da1469x/src/hal_system.c @@ -0,0 +1,136 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include <assert.h> +#include "syscfg/syscfg.h" +#include "mcu/da1469x_clock.h" +#include "mcu/da1469x_lpclk.h" +#include "mcu/da1469x_pd.h" +#include "mcu/da1469x_pdc.h" +#include "mcu/da1469x_prail.h" +#include "hal/hal_system.h" +#include "os/os_cputime.h" + +#if !MYNEWT_VAL(BOOT_LOADER) +static enum hal_reset_reason g_hal_reset_reason; +#endif + +void +hal_system_init(void) +{ +#if MYNEWT_VAL(MCU_DCDC_ENABLE) + da1469x_prail_dcdc_enable(); +#endif + + /* + * RESET_STAT_REG has to be cleared to allow HW set bits during next reset + * so we should read it now and keep result for application to check at any + * time. This does not happen for bootloader since reading reset reason in + * bootloader would prevent application from reading it. + */ + +#if !MYNEWT_VAL(BOOT_LOADER) + uint32_t reg; + + reg = CRG_TOP->RESET_STAT_REG; + CRG_TOP->RESET_STAT_REG = 0; + + if (reg & CRG_TOP_RESET_STAT_REG_PORESET_STAT_Msk) { + g_hal_reset_reason = HAL_RESET_POR; + } else if (reg & CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Msk) { + g_hal_reset_reason = HAL_RESET_WATCHDOG; + } else if (reg & CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Msk) { + g_hal_reset_reason = HAL_RESET_SOFT; + } else if (reg & CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Msk) { + g_hal_reset_reason = HAL_RESET_PIN; + } else { + g_hal_reset_reason = 0; + } +#endif +} + +void +hal_system_reset(void) +{ + +#if MYNEWT_VAL(HAL_SYSTEM_RESET_CB) + hal_system_reset_cb(); +#endif + + while (1) { + HAL_DEBUG_BREAK(); + CRG_TOP->SYS_CTRL_REG = 0x20; + NVIC_SystemReset(); + } +} + +int +hal_debugger_connected(void) +{ + return CRG_TOP->SYS_STAT_REG & CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Msk; +} + +void +hal_system_clock_start(void) +{ + /* Reset clock dividers to 0 */ + CRG_TOP->CLK_AMBA_REG &= ~(CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk | CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk); + + /* PD_TIM is already started in SystemInit */ + + da1469x_clock_sys_xtal32m_init(); + da1469x_clock_sys_xtal32m_enable(); +#if MYNEWT_VAL(MCU_PLL_ENABLE) + da1469x_clock_sys_pll_enable(); +#endif +#if MYNEWT_VAL_CHOICE(MCU_SYSCLK_SOURCE, PLL96) + da1469x_clock_pll_wait_to_lock(); + da1469x_clock_sys_pll_switch(); +#endif +#if MYNEWT_VAL_CHOICE(MCU_SYSCLK_SOURCE, XTAL32M) + /* Switch to XTAL32M and disable RC32M */ + da1469x_clock_sys_xtal32m_switch_safe(); +#endif + da1469x_clock_sys_rc32m_disable(); + +#if MYNEWT_VAL_CHOICE(MCU_LPCLK_SOURCE, RCX) + /* Switch to RCX and calibrate it */ + da1469x_clock_lp_rcx_enable(); + da1469x_clock_lp_rcx_switch(); + da1469x_clock_lp_rcx_calibrate(); + da1469x_lpclk_enabled(); +#else + /* + * We cannot switch lp_clk to XTAL32K here since it needs some time to + * settle, so we just disable RCX (we don't need it) and then we'll handle + * switch to XTAL32K from sysinit since we need os_cputime for this. + */ + da1469x_clock_lp_rcx_disable(); +#endif +} + +enum hal_reset_reason +hal_reset_cause(void) +{ +#if MYNEWT_VAL(BOOT_LOADER) + return 0; +#else + return g_hal_reset_reason; +#endif +} diff --git a/tinyusb/hw/mcu/dialog/da1469x/src/hal_system_start.c b/tinyusb/hw/mcu/dialog/da1469x/src/hal_system_start.c new file mode 100755 index 00000000..bd246504 --- /dev/null +++ b/tinyusb/hw/mcu/dialog/da1469x/src/hal_system_start.c @@ -0,0 +1,177 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include <assert.h> +#include <stdint.h> +#include "mcu/mcu.h" +#include "mcu/da1469x_hal.h" +#include <flash_map/flash_map.h> +#include <mcu/da1469x_clock.h> +#if MCUBOOT_MYNEWT +#include "bootutil/bootutil.h" +#include "bootutil/image.h" +#include "bootutil/bootutil_log.h" +#include "mcu/da1469x_dma.h" +#include "mcu/da1469x_otp.h" +#endif + +#if MYNEWT_VAL(BOOT_CUSTOM_START) && MCUBOOT_MYNEWT +sec_text_ram_core +#endif +void __attribute__((naked)) +hal_system_start(void *img_start) +{ + uint32_t img_data_addr; + uint32_t *img_data; + + img_data_addr = MCU_MEM_QSPIF_M_START_ADDRESS + (uint32_t)img_start; + + assert(img_data_addr < MCU_MEM_QSPIF_M_END_ADDRESS); + + img_data = (uint32_t *)img_data_addr; + + asm volatile (".syntax unified \n" + /* 1st word is stack pointer */ + " msr msp, %0 \n" + /* 2nd word is a reset handler (image entry) */ + " bx %1 \n" + : /* no output */ + : "r" (img_data[0]), "r" (img_data[1])); +} + +void +hal_system_restart(void *img_start) +{ + uint32_t primask __attribute__((unused)); + int i; + + /* + * Disable interrupts, and leave them disabled. + * They get re-enabled when system starts coming back again. + */ + __HAL_DISABLE_INTERRUPTS(primask); + + for (i = 0; i < sizeof(NVIC->ICER) / sizeof(NVIC->ICER[0]); i++) { + NVIC->ICER[i] = 0xffffffff; + } + + hal_system_start(img_start); +} + +#if MYNEWT_VAL(BOOT_CUSTOM_START) && MCUBOOT_MYNEWT +#define IMAGE_TLV_AES_NONCE 0x50 +#define IMAGE_TLV_SECRET_ID 0x60 + +sec_text_ram_core void +boot_custom_start(uintptr_t flash_base, struct boot_rsp *rsp) +{ + int rc; + struct image_tlv_iter it; + const struct flash_area *fap; + uint32_t off; + uint16_t len; + uint16_t type; + uint8_t buf[8]; + uint8_t key; + uint32_t nonce[2]; + bool has_aes_nonce; + bool has_secret_id; + DMA_Type *dma_regs = DMA; + uint32_t jump_offset = rsp->br_image_off + rsp->br_hdr->ih_hdr_size; + + BOOT_LOG_INF("Custom initialization"); + + /* skip to booting if we are running nonsecure mode */ + if (!(CRG_TOP->SECURE_BOOT_REG & 0x1)) { + hal_system_start((void *)(flash_base + jump_offset)); + } + + rc = flash_area_open(flash_area_id_from_image_slot(0), &fap); + assert(rc == 0); + + rc = bootutil_tlv_iter_begin(&it, rsp->br_hdr, fap, IMAGE_TLV_ANY, true); + assert(rc == 0); + + has_aes_nonce = has_secret_id = false; + while (true) { + rc = bootutil_tlv_iter_next(&it, &off, &len, &type); + assert(rc >= 0); + + if (rc > 0) { + break; + } + + if (type == IMAGE_TLV_AES_NONCE) { + assert(len == 8); + + rc = flash_area_read(fap, off, buf, len); + assert(rc == 0); + + nonce[0] = __builtin_bswap32(*(uint32_t *)buf); + nonce[1] = __builtin_bswap32(*(uint32_t *)(buf + 4)); + has_aes_nonce = true; + } else if (type == IMAGE_TLV_SECRET_ID) { + assert(len == 4); + + rc = flash_area_read(fap, off, buf, len); + assert(rc == 0); + + key = buf[0]; + has_secret_id = true; + } + } + + assert(has_aes_nonce && has_secret_id && key <= 7); + + /* enable OTP clock and set in read mode */ + da1469x_clock_amba_enable(CRG_TOP_CLK_AMBA_REG_OTP_ENABLE_Msk); + da1469x_otp_set_mode(OTPC_MODE_READ); + + /* disable decrypt on the fly and program start and end addresses */ + QSPIC->QSPIC_CTR_CTRL_REG = 0; + QSPIC->QSPIC_CTR_SADDR_REG = jump_offset; + QSPIC->QSPIC_CTR_EADDR_REG = QSPIC->QSPIC_CTR_SADDR_REG + + rsp->br_hdr->ih_img_size - 1; + + /* securely DMA hardware key from secret storage to QSPI decrypt engine */ + dma_regs->DMA_REQ_MUX_REG |= 0xf000; + dma_regs->DMA7_LEN_REG = 8; + dma_regs->DMA7_A_START_REG = MCU_OTPM_BASE + OTP_SEGMENT_QSPI_FW_KEYS + + (32 * key); + dma_regs->DMA7_B_START_REG = (uint32_t)&QSPIC->QSPIC_CTR_KEY_0_3_REG; + dma_regs->DMA7_CTRL_REG = DMA_DMA7_CTRL_REG_AINC_Msk | + DMA_DMA7_CTRL_REG_BINC_Msk | + (MCU_DMA_BUS_WIDTH_4B << DMA_DMA7_CTRL_REG_BW_Pos) | + DMA_DMA7_CTRL_REG_DMA_ON_Msk; + while (dma_regs->DMA7_IDX_REG != 8); + + /* program NONCE */ + QSPIC->QSPIC_CTR_NONCE_0_3_REG = nonce[0]; + QSPIC->QSPIC_CTR_NONCE_4_7_REG = nonce[1]; + + /* turn back on decrypt on the fly */ + QSPIC->QSPIC_CTR_CTRL_REG = 1; + + /* set OTP to standby and turn off clock */ + da1469x_otp_set_mode(OTPC_MODE_STBY); + da1469x_clock_amba_disable(CRG_TOP_CLK_AMBA_REG_OTP_ENABLE_Msk); + + hal_system_start((void *)(flash_base + jump_offset)); +} +#endif diff --git a/tinyusb/hw/mcu/dialog/da1469x/src/system_da1469x.c b/tinyusb/hw/mcu/dialog/da1469x/src/system_da1469x.c new file mode 100755 index 00000000..538bac79 --- /dev/null +++ b/tinyusb/hw/mcu/dialog/da1469x/src/system_da1469x.c @@ -0,0 +1,61 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include "mcu/mcu.h" +#include <mcu/da1469x_clock.h> + +extern uint8_t __StackLimit; + +uint32_t SystemCoreClock = 32000000; + +void +SystemInit(void) +{ + /* Enable FPU when using hard-float */ +#if (__FPU_USED == 1) + SCB->CPACR |= (3UL << 20) | (3UL << 22); + __DSB(); + __ISB(); +#endif + + /* Freez watchdog */ + GPREG->SET_FREEZE_REG |= GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Msk; + /* Initialize power domains (disable radio only) */ + CRG_TOP->PMU_CTRL_REG = CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Msk; + + CRG_TOP->P0_SET_PAD_LATCH_REG = CRG_TOP_P0_PAD_LATCH_REG_P0_LATCH_EN_Msk; + CRG_TOP->P1_SET_PAD_LATCH_REG = CRG_TOP_P1_PAD_LATCH_REG_P1_LATCH_EN_Msk; + + /* Reset clock dividers to 0 */ + CRG_TOP->CLK_AMBA_REG &= ~(CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk | CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk); + + /* PD_TIM is already started in SystemInit */ + + da1469x_clock_sys_xtal32m_init(); + da1469x_clock_sys_xtal32m_enable(); + da1469x_clock_sys_pll_enable(); + da1469x_clock_pll_wait_to_lock(); + /* Switch to XTAL32M and disable RC32M */ + da1469x_clock_sys_xtal32m_switch_safe(); + da1469x_clock_sys_rc32m_disable(); +} + +void _init(void) +{ +} diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble.h new file mode 100755 index 00000000..76a432bf --- /dev/null +++ b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble.h @@ -0,0 +1,685 @@ +/* + * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_COMMON BLE SoftDevice Common + @{ + @defgroup ble_api Events, type definitions and API calls + @{ + + @brief Module independent events, type definitions and API calls for the BLE SoftDevice. + + */ + +#ifndef BLE_H__ +#define BLE_H__ + +#include <stdint.h> +#include "nrf_svc.h" +#include "nrf_error.h" +#include "ble_err.h" +#include "ble_gap.h" +#include "ble_l2cap.h" +#include "ble_gatt.h" +#include "ble_gattc.h" +#include "ble_gatts.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup BLE_COMMON_ENUMERATIONS Enumerations + * @{ */ + +/** + * @brief Common API SVC numbers. + */ +enum BLE_COMMON_SVCS +{ + SD_BLE_ENABLE = BLE_SVC_BASE, /**< Enable and initialize the BLE stack */ + SD_BLE_EVT_GET, /**< Get an event from the pending events queue. */ + SD_BLE_UUID_VS_ADD, /**< Add a Vendor Specific base UUID. */ + SD_BLE_UUID_DECODE, /**< Decode UUID bytes. */ + SD_BLE_UUID_ENCODE, /**< Encode UUID bytes. */ + SD_BLE_VERSION_GET, /**< Get the local version information (company ID, Link Layer Version, Link Layer Subversion). */ + SD_BLE_USER_MEM_REPLY, /**< User Memory Reply. */ + SD_BLE_OPT_SET, /**< Set a BLE option. */ + SD_BLE_OPT_GET, /**< Get a BLE option. */ + SD_BLE_CFG_SET, /**< Add a configuration to the BLE stack. */ + SD_BLE_UUID_VS_REMOVE, /**< Remove a Vendor Specific base UUID. */ +}; + +/** + * @brief BLE Module Independent Event IDs. + */ +enum BLE_COMMON_EVTS +{ + BLE_EVT_USER_MEM_REQUEST = BLE_EVT_BASE + 0, /**< User Memory request. @ref ble_evt_user_mem_request_t */ + BLE_EVT_USER_MEM_RELEASE = BLE_EVT_BASE + 1, /**< User Memory release. @ref ble_evt_user_mem_release_t */ +}; + +/**@brief BLE Connection Configuration IDs. + * + * IDs that uniquely identify a connection configuration. + */ +enum BLE_CONN_CFGS +{ + BLE_CONN_CFG_GAP = BLE_CONN_CFG_BASE + 0, /**< BLE GAP specific connection configuration. */ + BLE_CONN_CFG_GATTC = BLE_CONN_CFG_BASE + 1, /**< BLE GATTC specific connection configuration. */ + BLE_CONN_CFG_GATTS = BLE_CONN_CFG_BASE + 2, /**< BLE GATTS specific connection configuration. */ + BLE_CONN_CFG_GATT = BLE_CONN_CFG_BASE + 3, /**< BLE GATT specific connection configuration. */ + BLE_CONN_CFG_L2CAP = BLE_CONN_CFG_BASE + 4, /**< BLE L2CAP specific connection configuration. */ +}; + +/**@brief BLE Common Configuration IDs. + * + * IDs that uniquely identify a common configuration. + */ +enum BLE_COMMON_CFGS +{ + BLE_COMMON_CFG_VS_UUID = BLE_CFG_BASE, /**< Vendor specific base UUID configuration */ +}; + +/**@brief Common Option IDs. + * IDs that uniquely identify a common option. + */ +enum BLE_COMMON_OPTS +{ + BLE_COMMON_OPT_PA_LNA = BLE_OPT_BASE + 0, /**< PA and LNA options */ + BLE_COMMON_OPT_CONN_EVT_EXT = BLE_OPT_BASE + 1, /**< Extended connection events option */ + BLE_COMMON_OPT_EXTENDED_RC_CAL = BLE_OPT_BASE + 2, /**< Extended RC calibration option */ + BLE_COMMON_OPT_ADV_SCHED_CFG = BLE_OPT_BASE + 3, /**< Advertiser role scheduling configuration option */ +}; + +/** @} */ + +/** @addtogroup BLE_COMMON_DEFINES Defines + * @{ */ + +/** @brief Required pointer alignment for BLE Events. +*/ +#define BLE_EVT_PTR_ALIGNMENT 4 + +/** @brief Leaves the maximum of the two arguments. +*/ +#define BLE_MAX(a, b) ((a) < (b) ? (b) : (a)) + +/** @brief Maximum possible length for BLE Events. + * @note The highest value used for @ref ble_gatt_conn_cfg_t::att_mtu in any connection configuration shall be used as a parameter. + * If that value has not been configured for any connections then @ref BLE_GATT_ATT_MTU_DEFAULT must be used instead. +*/ +#define BLE_EVT_LEN_MAX(ATT_MTU) ( \ + offsetof(ble_evt_t, evt.gattc_evt.params.prim_srvc_disc_rsp.services) + ((ATT_MTU) - 1) / 4 * sizeof(ble_gattc_service_t) \ +) + +/** @defgroup ADV_SCHED_CFG Advertiser Role Scheduling Configuration + * @{ */ +#define ADV_SCHED_CFG_DEFAULT 0 /**< Default advertiser role scheduling configuration. */ +#define ADV_SCHED_CFG_IMPROVED 1 /**< Improved advertiser role scheduling configuration in which the housekeeping time is reduced. */ +/** @} */ + +/** @defgroup BLE_USER_MEM_TYPES User Memory Types + * @{ */ +#define BLE_USER_MEM_TYPE_INVALID 0x00 /**< Invalid User Memory Types. */ +#define BLE_USER_MEM_TYPE_GATTS_QUEUED_WRITES 0x01 /**< User Memory for GATTS queued writes. */ +/** @} */ + +/** @defgroup BLE_UUID_VS_COUNTS Vendor Specific base UUID counts + * @{ + */ +#define BLE_UUID_VS_COUNT_DEFAULT 10 /**< Default VS UUID count. */ +#define BLE_UUID_VS_COUNT_MAX 254 /**< Maximum VS UUID count. */ +/** @} */ + +/** @defgroup BLE_COMMON_CFG_DEFAULTS Configuration defaults. + * @{ + */ +#define BLE_CONN_CFG_TAG_DEFAULT 0 /**< Default configuration tag, SoftDevice default connection configuration. */ + +/** @} */ + +/** @} */ + +/** @addtogroup BLE_COMMON_STRUCTURES Structures + * @{ */ + +/**@brief User Memory Block. */ +typedef struct +{ + uint8_t *p_mem; /**< Pointer to the start of the user memory block. */ + uint16_t len; /**< Length in bytes of the user memory block. */ +} ble_user_mem_block_t; + +/**@brief Event structure for @ref BLE_EVT_USER_MEM_REQUEST. */ +typedef struct +{ + uint8_t type; /**< User memory type, see @ref BLE_USER_MEM_TYPES. */ +} ble_evt_user_mem_request_t; + +/**@brief Event structure for @ref BLE_EVT_USER_MEM_RELEASE. */ +typedef struct +{ + uint8_t type; /**< User memory type, see @ref BLE_USER_MEM_TYPES. */ + ble_user_mem_block_t mem_block; /**< User memory block */ +} ble_evt_user_mem_release_t; + +/**@brief Event structure for events not associated with a specific function module. */ +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle on which this event occurred. */ + union + { + ble_evt_user_mem_request_t user_mem_request; /**< User Memory Request Event Parameters. */ + ble_evt_user_mem_release_t user_mem_release; /**< User Memory Release Event Parameters. */ + } params; /**< Event parameter union. */ +} ble_common_evt_t; + +/**@brief BLE Event header. */ +typedef struct +{ + uint16_t evt_id; /**< Value from a BLE_<module>_EVT series. */ + uint16_t evt_len; /**< Length in octets including this header. */ +} ble_evt_hdr_t; + +/**@brief Common BLE Event type, wrapping the module specific event reports. */ +typedef struct +{ + ble_evt_hdr_t header; /**< Event header. */ + union + { + ble_common_evt_t common_evt; /**< Common Event, evt_id in BLE_EVT_* series. */ + ble_gap_evt_t gap_evt; /**< GAP originated event, evt_id in BLE_GAP_EVT_* series. */ + ble_gattc_evt_t gattc_evt; /**< GATT client originated event, evt_id in BLE_GATTC_EVT* series. */ + ble_gatts_evt_t gatts_evt; /**< GATT server originated event, evt_id in BLE_GATTS_EVT* series. */ + ble_l2cap_evt_t l2cap_evt; /**< L2CAP originated event, evt_id in BLE_L2CAP_EVT* series. */ + } evt; /**< Event union. */ +} ble_evt_t; + + +/** + * @brief Version Information. + */ +typedef struct +{ + uint8_t version_number; /**< Link Layer Version number. See https://www.bluetooth.org/en-us/specification/assigned-numbers/link-layer for assigned values. */ + uint16_t company_id; /**< Company ID, Nordic Semiconductor's company ID is 89 (0x0059) (https://www.bluetooth.org/apps/content/Default.aspx?doc_id=49708). */ + uint16_t subversion_number; /**< Link Layer Sub Version number, corresponds to the SoftDevice Config ID or Firmware ID (FWID). */ +} ble_version_t; + +/** + * @brief Configuration parameters for the PA and LNA. + */ +typedef struct +{ + uint8_t enable :1; /**< Enable toggling for this amplifier */ + uint8_t active_high :1; /**< Set the pin to be active high */ + uint8_t gpio_pin :6; /**< The GPIO pin to toggle for this amplifier */ +} ble_pa_lna_cfg_t; + +/** + * @brief PA & LNA GPIO toggle configuration + * + * This option configures the SoftDevice to toggle pins when the radio is active for use with a power amplifier and/or + * a low noise amplifier. + * + * Toggling the pins is achieved by using two PPI channels and a GPIOTE channel. The hardware channel IDs are provided + * by the application and should be regarded as reserved as long as any PA/LNA toggling is enabled. + * + * @note @ref sd_ble_opt_get is not supported for this option. + * @note Setting this option while the radio is in use (i.e. any of the roles are active) may have undefined consequences + * and must be avoided by the application. + */ +typedef struct +{ + ble_pa_lna_cfg_t pa_cfg; /**< Power Amplifier configuration */ + ble_pa_lna_cfg_t lna_cfg; /**< Low Noise Amplifier configuration */ + + uint8_t ppi_ch_id_set; /**< PPI channel used for radio pin setting */ + uint8_t ppi_ch_id_clr; /**< PPI channel used for radio pin clearing */ + uint8_t gpiote_ch_id; /**< GPIOTE channel used for radio pin toggling */ +} ble_common_opt_pa_lna_t; + +/** + * @brief Configuration of extended BLE connection events. + * + * When enabled the SoftDevice will dynamically extend the connection event when possible. + * + * The connection event length is controlled by the connection configuration as set by @ref ble_gap_conn_cfg_t::event_length. + * The connection event can be extended if there is time to send another packet pair before the start of the next connection interval, + * and if there are no conflicts with other BLE roles requesting radio time. + * + * @note @ref sd_ble_opt_get is not supported for this option. + */ +typedef struct +{ + uint8_t enable : 1; /**< Enable extended BLE connection events, disabled by default. */ +} ble_common_opt_conn_evt_ext_t; + +/** + * @brief Enable/disable extended RC calibration. + * + * If extended RC calibration is enabled and the internal RC oscillator (@ref NRF_CLOCK_LF_SRC_RC) is used as the SoftDevice + * LFCLK source, the SoftDevice as a peripheral will by default try to increase the receive window if two consecutive packets + * are not received. If it turns out that the packets were not received due to clock drift, the RC calibration is started. + * This calibration comes in addition to the periodic calibration that is configured by @ref sd_softdevice_enable(). When + * using only peripheral connections, the periodic calibration can therefore be configured with a much longer interval as the + * peripheral will be able to detect and adjust automatically to clock drift, and calibrate on demand. + * + * If extended RC calibration is disabled and the internal RC oscillator is used as the SoftDevice LFCLK source, the + * RC oscillator is calibrated periodically as configured by @ref sd_softdevice_enable(). + * + * @note @ref sd_ble_opt_get is not supported for this option. + */ +typedef struct +{ + uint8_t enable : 1; /**< Enable extended RC calibration, enabled by default. */ +} ble_common_opt_extended_rc_cal_t; + +/** + * @brief Configuration of BLE advertiser role scheduling. + * + * @note @ref sd_ble_opt_get is not supported for this option. + */ +typedef struct +{ + uint8_t sched_cfg; /**< See @ref ADV_SCHED_CFG. */ +} ble_common_opt_adv_sched_cfg_t; + +/**@brief Option structure for common options. */ +typedef union +{ + ble_common_opt_pa_lna_t pa_lna; /**< Parameters for controlling PA and LNA pin toggling. */ + ble_common_opt_conn_evt_ext_t conn_evt_ext; /**< Parameters for enabling extended connection events. */ + ble_common_opt_extended_rc_cal_t extended_rc_cal; /**< Parameters for enabling extended RC calibration. */ + ble_common_opt_adv_sched_cfg_t adv_sched_cfg; /**< Parameters for configuring advertiser role scheduling. */ +} ble_common_opt_t; + +/**@brief Common BLE Option type, wrapping the module specific options. */ +typedef union +{ + ble_common_opt_t common_opt; /**< COMMON options, opt_id in @ref BLE_COMMON_OPTS series. */ + ble_gap_opt_t gap_opt; /**< GAP option, opt_id in @ref BLE_GAP_OPTS series. */ +} ble_opt_t; + +/**@brief BLE connection configuration type, wrapping the module specific configurations, set with + * @ref sd_ble_cfg_set. + * + * @note Connection configurations don't have to be set. + * In the case that no configurations has been set, or fewer connection configurations has been set than enabled connections, + * the default connection configuration will be automatically added for the remaining connections. + * When creating connections with the default configuration, @ref BLE_CONN_CFG_TAG_DEFAULT should be used in + * place of @ref ble_conn_cfg_t::conn_cfg_tag. + * + * @sa sd_ble_gap_adv_start() + * @sa sd_ble_gap_connect() + * + * @mscs + * @mmsc{@ref BLE_CONN_CFG} + * @endmscs + + */ +typedef struct +{ + uint8_t conn_cfg_tag; /**< The application chosen tag it can use with the + @ref sd_ble_gap_adv_start() and @ref sd_ble_gap_connect() calls + to select this configuration when creating a connection. + Must be different for all connection configurations added and not @ref BLE_CONN_CFG_TAG_DEFAULT. */ + union { + ble_gap_conn_cfg_t gap_conn_cfg; /**< GAP connection configuration, cfg_id is @ref BLE_CONN_CFG_GAP. */ + ble_gattc_conn_cfg_t gattc_conn_cfg; /**< GATTC connection configuration, cfg_id is @ref BLE_CONN_CFG_GATTC. */ + ble_gatts_conn_cfg_t gatts_conn_cfg; /**< GATTS connection configuration, cfg_id is @ref BLE_CONN_CFG_GATTS. */ + ble_gatt_conn_cfg_t gatt_conn_cfg; /**< GATT connection configuration, cfg_id is @ref BLE_CONN_CFG_GATT. */ + ble_l2cap_conn_cfg_t l2cap_conn_cfg; /**< L2CAP connection configuration, cfg_id is @ref BLE_CONN_CFG_L2CAP. */ + } params; /**< Connection configuration union. */ +} ble_conn_cfg_t; + +/** + * @brief Configuration of Vendor Specific base UUIDs, set with @ref sd_ble_cfg_set. + * + * @retval ::NRF_ERROR_INVALID_PARAM Too many UUIDs configured. + */ +typedef struct +{ + uint8_t vs_uuid_count; /**< Number of 128-bit Vendor Specific base UUID bases to allocate memory for. + Default value is @ref BLE_UUID_VS_COUNT_DEFAULT. Maximum value is + @ref BLE_UUID_VS_COUNT_MAX. */ +} ble_common_cfg_vs_uuid_t; + +/**@brief Common BLE Configuration type, wrapping the common configurations. */ +typedef union +{ + ble_common_cfg_vs_uuid_t vs_uuid_cfg; /**< Vendor Specific base UUID configuration, cfg_id is @ref BLE_COMMON_CFG_VS_UUID. */ +} ble_common_cfg_t; + +/**@brief BLE Configuration type, wrapping the module specific configurations. */ +typedef union +{ + ble_conn_cfg_t conn_cfg; /**< Connection specific configurations, cfg_id in @ref BLE_CONN_CFGS series. */ + ble_common_cfg_t common_cfg; /**< Global common configurations, cfg_id in @ref BLE_COMMON_CFGS series. */ + ble_gap_cfg_t gap_cfg; /**< Global GAP configurations, cfg_id in @ref BLE_GAP_CFGS series. */ + ble_gatts_cfg_t gatts_cfg; /**< Global GATTS configuration, cfg_id in @ref BLE_GATTS_CFGS series. */ +} ble_cfg_t; + +/** @} */ + +/** @addtogroup BLE_COMMON_FUNCTIONS Functions + * @{ */ + +/**@brief Enable the BLE stack + * + * @param[in, out] p_app_ram_base Pointer to a variable containing the start address of the + * application RAM region (APP_RAM_BASE). On return, this will + * contain the minimum start address of the application RAM region + * required by the SoftDevice for this configuration. + * + * @note The memory requirement for a specific configuration will not increase between SoftDevices + * with the same major version number. + * + * @note At runtime the IC's RAM is split into 2 regions: The SoftDevice RAM region is located + * between 0x20000000 and APP_RAM_BASE-1 and the application's RAM region is located between + * APP_RAM_BASE and the start of the call stack. + * + * @details This call initializes the BLE stack, no BLE related function other than @ref + * sd_ble_cfg_set can be called before this one. + * + * @mscs + * @mmsc{@ref BLE_COMMON_ENABLE} + * @endmscs + * + * @retval ::NRF_SUCCESS The BLE stack has been initialized successfully. + * @retval ::NRF_ERROR_INVALID_STATE The BLE stack had already been initialized and cannot be reinitialized. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid or not sufficiently aligned pointer supplied. + * @retval ::NRF_ERROR_NO_MEM One or more of the following is true: + * - The amount of memory assigned to the SoftDevice by *p_app_ram_base is not + * large enough to fit this configuration's memory requirement. Check *p_app_ram_base + * and set the start address of the application RAM region accordingly. + * - Dynamic part of the SoftDevice RAM region is larger then 64 kB which + * is currently not supported. + * @retval ::NRF_ERROR_RESOURCES The total number of L2CAP Channels configured using @ref sd_ble_cfg_set is too large. + */ +SVCALL(SD_BLE_ENABLE, uint32_t, sd_ble_enable(uint32_t * p_app_ram_base)); + +/**@brief Add configurations for the BLE stack + * + * @param[in] cfg_id Config ID, see @ref BLE_CONN_CFGS, @ref BLE_COMMON_CFGS, @ref + * BLE_GAP_CFGS or @ref BLE_GATTS_CFGS. + * @param[in] p_cfg Pointer to a ble_cfg_t structure containing the configuration value. + * @param[in] app_ram_base The start address of the application RAM region (APP_RAM_BASE). + * See @ref sd_ble_enable for details about APP_RAM_BASE. + * + * @note The memory requirement for a specific configuration will not increase between SoftDevices + * with the same major version number. + * + * @note If a configuration is set more than once, the last one set is the one that takes effect on + * @ref sd_ble_enable. + * + * @note Any part of the BLE stack that is NOT configured with @ref sd_ble_cfg_set will have default + * configuration. + * + * @note @ref sd_ble_cfg_set may be called at any time when the SoftDevice is enabled (see @ref + * sd_softdevice_enable) while the BLE part of the SoftDevice is not enabled (see @ref + * sd_ble_enable). + * + * @note Error codes for the configurations are described in the configuration structs. + * + * @mscs + * @mmsc{@ref BLE_COMMON_ENABLE} + * @endmscs + * + * @retval ::NRF_SUCCESS The configuration has been added successfully. + * @retval ::NRF_ERROR_INVALID_STATE The BLE stack had already been initialized. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid or not sufficiently aligned pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid cfg_id supplied. + * @retval ::NRF_ERROR_NO_MEM The amount of memory assigned to the SoftDevice by app_ram_base is not + * large enough to fit this configuration's memory requirement. + */ +SVCALL(SD_BLE_CFG_SET, uint32_t, sd_ble_cfg_set(uint32_t cfg_id, ble_cfg_t const * p_cfg, uint32_t app_ram_base)); + +/**@brief Get an event from the pending events queue. + * + * @param[out] p_dest Pointer to buffer to be filled in with an event, or NULL to retrieve the event length. + * This buffer <b>must be aligned to the extend defined by @ref BLE_EVT_PTR_ALIGNMENT</b>. + * The buffer should be interpreted as a @ref ble_evt_t struct. + * @param[in, out] p_len Pointer the length of the buffer, on return it is filled with the event length. + * + * @details This call allows the application to pull a BLE event from the BLE stack. The application is signaled that + * an event is available from the BLE stack by the triggering of the SD_EVT_IRQn interrupt. + * The application is free to choose whether to call this function from thread mode (main context) or directly from the + * Interrupt Service Routine that maps to SD_EVT_IRQn. In any case however, and because the BLE stack runs at a higher + * priority than the application, this function should be called in a loop (until @ref NRF_ERROR_NOT_FOUND is returned) + * every time SD_EVT_IRQn is raised to ensure that all available events are pulled from the BLE stack. Failure to do so + * could potentially leave events in the internal queue without the application being aware of this fact. + * + * Sizing the p_dest buffer is equally important, since the application needs to provide all the memory necessary for the event to + * be copied into application memory. If the buffer provided is not large enough to fit the entire contents of the event, + * @ref NRF_ERROR_DATA_SIZE will be returned and the application can then call again with a larger buffer size. + * The maximum possible event length is defined by @ref BLE_EVT_LEN_MAX. The application may also "peek" the event length + * by providing p_dest as a NULL pointer and inspecting the value of *p_len upon return: + * + * \code + * uint16_t len; + * errcode = sd_ble_evt_get(NULL, &len); + * \endcode + * + * @mscs + * @mmsc{@ref BLE_COMMON_IRQ_EVT_MSC} + * @mmsc{@ref BLE_COMMON_THREAD_EVT_MSC} + * @endmscs + * + * @retval ::NRF_SUCCESS Event pulled and stored into the supplied buffer. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid or not sufficiently aligned pointer supplied. + * @retval ::NRF_ERROR_NOT_FOUND No events ready to be pulled. + * @retval ::NRF_ERROR_DATA_SIZE Event ready but could not fit into the supplied buffer. + */ +SVCALL(SD_BLE_EVT_GET, uint32_t, sd_ble_evt_get(uint8_t *p_dest, uint16_t *p_len)); + + +/**@brief Add a Vendor Specific base UUID. + * + * @details This call enables the application to add a Vendor Specific base UUID to the BLE stack's table, for later + * use with all other modules and APIs. This then allows the application to use the shorter, 24-bit @ref ble_uuid_t + * format when dealing with both 16-bit and 128-bit UUIDs without having to check for lengths and having split code + * paths. This is accomplished by extending the grouping mechanism that the Bluetooth SIG standard base UUID uses + * for all other 128-bit UUIDs. The type field in the @ref ble_uuid_t structure is an index (relative to + * @ref BLE_UUID_TYPE_VENDOR_BEGIN) to the table populated by multiple calls to this function, and the UUID field + * in the same structure contains the 2 bytes at indexes 12 and 13. The number of possible 128-bit UUIDs available to + * the application is therefore the number of Vendor Specific UUIDs added with the help of this function times 65536, + * although restricted to modifying bytes 12 and 13 for each of the entries in the supplied array. + * + * @note Bytes 12 and 13 of the provided UUID will not be used internally, since those are always replaced by + * the 16-bit uuid field in @ref ble_uuid_t. + * + * @note If a UUID is already present in the BLE stack's internal table, the corresponding index will be returned in + * p_uuid_type along with an @ref NRF_SUCCESS error code. + * + * @param[in] p_vs_uuid Pointer to a 16-octet (128-bit) little endian Vendor Specific base UUID disregarding + * bytes 12 and 13. + * @param[out] p_uuid_type Pointer to a uint8_t where the type field in @ref ble_uuid_t corresponding to this UUID will be stored. + * + * @retval ::NRF_SUCCESS Successfully added the Vendor Specific base UUID. + * @retval ::NRF_ERROR_INVALID_ADDR If p_vs_uuid or p_uuid_type is NULL or invalid. + * @retval ::NRF_ERROR_NO_MEM If there are no more free slots for VS UUIDs. + */ +SVCALL(SD_BLE_UUID_VS_ADD, uint32_t, sd_ble_uuid_vs_add(ble_uuid128_t const *p_vs_uuid, uint8_t *p_uuid_type)); + + +/**@brief Remove a Vendor Specific base UUID. + * + * @details This call removes a Vendor Specific base UUID that has been added with @ref sd_ble_uuid_vs_add. This function allows + * the application to reuse memory allocated for Vendor Specific base UUIDs. + * + * @note Currently this function can only be called with a p_uuid_type set to @ref BLE_UUID_TYPE_UNKNOWN or the last added UUID type. + * + * @param[in] p_uuid_type Pointer to a uint8_t where the type field in @ref ble_uuid_t::type corresponds to the UUID type that + * shall be removed. If the type is set to @ref BLE_UUID_TYPE_UNKNOWN, or the pointer is NULL, the last + * Vendor Specific base UUID will be removed. + * @param[out] p_uuid_type Pointer to a uint8_t where the type field in @ref ble_uuid_t corresponds to the UUID type that was + * removed. If function returns with a failure, it contains the last type that is in use by the ATT Server. + * + * @retval ::NRF_SUCCESS Successfully removed the Vendor Specific base UUID. + * @retval ::NRF_ERROR_INVALID_ADDR If p_uuid_type is invalid. + * @retval ::NRF_ERROR_INVALID_PARAM If p_uuid_type points to a non-valid UUID type. + * @retval ::NRF_ERROR_FORBIDDEN If the Vendor Specific base UUID is in use by the ATT Server. + */ + +SVCALL(SD_BLE_UUID_VS_REMOVE, uint32_t, sd_ble_uuid_vs_remove(uint8_t *p_uuid_type)); + + +/** @brief Decode little endian raw UUID bytes (16-bit or 128-bit) into a 24 bit @ref ble_uuid_t structure. + * + * @details The raw UUID bytes excluding bytes 12 and 13 (i.e. bytes 0-11 and 14-15) of p_uuid_le are compared + * to the corresponding ones in each entry of the table of Vendor Specific base UUIDs populated with @ref sd_ble_uuid_vs_add + * to look for a match. If there is such a match, bytes 12 and 13 are returned as p_uuid->uuid and the index + * relative to @ref BLE_UUID_TYPE_VENDOR_BEGIN as p_uuid->type. + * + * @note If the UUID length supplied is 2, then the type set by this call will always be @ref BLE_UUID_TYPE_BLE. + * + * @param[in] uuid_le_len Length in bytes of the buffer pointed to by p_uuid_le (must be 2 or 16 bytes). + * @param[in] p_uuid_le Pointer pointing to little endian raw UUID bytes. + * @param[out] p_uuid Pointer to a @ref ble_uuid_t structure to be filled in. + * + * @retval ::NRF_SUCCESS Successfully decoded into the @ref ble_uuid_t structure. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_LENGTH Invalid UUID length. + * @retval ::NRF_ERROR_NOT_FOUND For a 128-bit UUID, no match in the populated table of UUIDs. + */ +SVCALL(SD_BLE_UUID_DECODE, uint32_t, sd_ble_uuid_decode(uint8_t uuid_le_len, uint8_t const *p_uuid_le, ble_uuid_t *p_uuid)); + + +/** @brief Encode a @ref ble_uuid_t structure into little endian raw UUID bytes (16-bit or 128-bit). + * + * @note The pointer to the destination buffer p_uuid_le may be NULL, in which case only the validity and size of p_uuid is computed. + * + * @param[in] p_uuid Pointer to a @ref ble_uuid_t structure that will be encoded into bytes. + * @param[out] p_uuid_le_len Pointer to a uint8_t that will be filled with the encoded length (2 or 16 bytes). + * @param[out] p_uuid_le Pointer to a buffer where the little endian raw UUID bytes (2 or 16) will be stored. + * + * @retval ::NRF_SUCCESS Successfully encoded into the buffer. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid UUID type. + */ +SVCALL(SD_BLE_UUID_ENCODE, uint32_t, sd_ble_uuid_encode(ble_uuid_t const *p_uuid, uint8_t *p_uuid_le_len, uint8_t *p_uuid_le)); + + +/**@brief Get Version Information. + * + * @details This call allows the application to get the BLE stack version information. + * + * @param[out] p_version Pointer to a ble_version_t structure to be filled in. + * + * @retval ::NRF_SUCCESS Version information stored successfully. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_BUSY The BLE stack is busy (typically doing a locally-initiated disconnection procedure). + */ +SVCALL(SD_BLE_VERSION_GET, uint32_t, sd_ble_version_get(ble_version_t *p_version)); + + +/**@brief Provide a user memory block. + * + * @note This call can only be used as a response to a @ref BLE_EVT_USER_MEM_REQUEST event issued to the application. + * + * @param[in] conn_handle Connection handle. + * @param[in] p_block Pointer to a user memory block structure or NULL if memory is managed by the application. + * + * @mscs + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_PEER_CANCEL_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_AUTH_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_NOAUTH_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_BUF_AUTH_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_BUF_NOAUTH_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_QUEUE_FULL_MSC} + * @endmscs + * + * @retval ::NRF_SUCCESS Successfully queued a response to the peer. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_LENGTH Invalid user memory block length supplied. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection state or no user memory request pending. + */ +SVCALL(SD_BLE_USER_MEM_REPLY, uint32_t, sd_ble_user_mem_reply(uint16_t conn_handle, ble_user_mem_block_t const *p_block)); + +/**@brief Set a BLE option. + * + * @details This call allows the application to set the value of an option. + * + * @mscs + * @mmsc{@ref BLE_GAP_PERIPH_BONDING_STATIC_PK_MSC} + * @endmscs + * + * @param[in] opt_id Option ID, see @ref BLE_COMMON_OPTS and @ref BLE_GAP_OPTS. + * @param[in] p_opt Pointer to a ble_opt_t structure containing the option value. + * + * @retval ::NRF_SUCCESS Option set successfully. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints. + * @retval ::NRF_ERROR_INVALID_STATE Unable to set the parameter at this time. + * @retval ::NRF_ERROR_BUSY The BLE stack is busy or the previous procedure has not completed. + */ +SVCALL(SD_BLE_OPT_SET, uint32_t, sd_ble_opt_set(uint32_t opt_id, ble_opt_t const *p_opt)); + + +/**@brief Get a BLE option. + * + * @details This call allows the application to retrieve the value of an option. + * + * @param[in] opt_id Option ID, see @ref BLE_COMMON_OPTS and @ref BLE_GAP_OPTS. + * @param[out] p_opt Pointer to a ble_opt_t structure to be filled in. + * + * @retval ::NRF_SUCCESS Option retrieved successfully. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints. + * @retval ::NRF_ERROR_INVALID_STATE Unable to retrieve the parameter at this time. + * @retval ::NRF_ERROR_BUSY The BLE stack is busy or the previous procedure has not completed. + * @retval ::NRF_ERROR_NOT_SUPPORTED This option is not supported. + * + */ +SVCALL(SD_BLE_OPT_GET, uint32_t, sd_ble_opt_get(uint32_t opt_id, ble_opt_t *p_opt)); + +/** @} */ +#ifdef __cplusplus +} +#endif +#endif /* BLE_H__ */ + +/** + @} + @} +*/ diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_err.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_err.h new file mode 100755 index 00000000..1b4820dc --- /dev/null +++ b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_err.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_COMMON + @{ + @addtogroup nrf_error + @{ + @ingroup BLE_COMMON + @} + + @defgroup ble_err General error codes + @{ + + @brief General error code definitions for the BLE API. + + @ingroup BLE_COMMON +*/ +#ifndef NRF_BLE_ERR_H__ +#define NRF_BLE_ERR_H__ + +#include "nrf_error.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* @defgroup BLE_ERRORS Error Codes + * @{ */ +#define BLE_ERROR_NOT_ENABLED (NRF_ERROR_STK_BASE_NUM+0x001) /**< @ref sd_ble_enable has not been called. */ +#define BLE_ERROR_INVALID_CONN_HANDLE (NRF_ERROR_STK_BASE_NUM+0x002) /**< Invalid connection handle. */ +#define BLE_ERROR_INVALID_ATTR_HANDLE (NRF_ERROR_STK_BASE_NUM+0x003) /**< Invalid attribute handle. */ +#define BLE_ERROR_INVALID_ADV_HANDLE (NRF_ERROR_STK_BASE_NUM+0x004) /**< Invalid advertising handle. */ +#define BLE_ERROR_INVALID_ROLE (NRF_ERROR_STK_BASE_NUM+0x005) /**< Invalid role. */ +#define BLE_ERROR_BLOCKED_BY_OTHER_LINKS (NRF_ERROR_STK_BASE_NUM+0x006) /**< The attempt to change link settings failed due to the scheduling of other links. */ +/** @} */ + + +/** @defgroup BLE_ERROR_SUBRANGES Module specific error code subranges + * @brief Assignment of subranges for module specific error codes. + * @note For specific error codes, see ble_<module>.h or ble_error_<module>.h. + * @{ */ +#define NRF_L2CAP_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x100) /**< L2CAP specific errors. */ +#define NRF_GAP_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x200) /**< GAP specific errors. */ +#define NRF_GATTC_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x300) /**< GATT client specific errors. */ +#define NRF_GATTS_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x400) /**< GATT server specific errors. */ +/** @} */ + +#ifdef __cplusplus +} +#endif +#endif + + +/** + @} + @} +*/ diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gap.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gap.h new file mode 100755 index 00000000..c434fefb --- /dev/null +++ b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gap.h @@ -0,0 +1,2696 @@ +/* + * Copyright (c) 2011 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_GAP Generic Access Profile (GAP) + @{ + @brief Definitions and prototypes for the GAP interface. + */ + +#ifndef BLE_GAP_H__ +#define BLE_GAP_H__ + +#include <stdint.h> +#include "nrf_svc.h" +#include "nrf_error.h" +#include "ble_hci.h" +#include "ble_ranges.h" +#include "ble_types.h" +#include "ble_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/**@addtogroup BLE_GAP_ENUMERATIONS Enumerations + * @{ */ + +/**@brief GAP API SVC numbers. + */ +enum BLE_GAP_SVCS +{ + SD_BLE_GAP_ADDR_SET = BLE_GAP_SVC_BASE, /**< Set own Bluetooth Address. */ + SD_BLE_GAP_ADDR_GET = BLE_GAP_SVC_BASE + 1, /**< Get own Bluetooth Address. */ + SD_BLE_GAP_WHITELIST_SET = BLE_GAP_SVC_BASE + 2, /**< Set active whitelist. */ + SD_BLE_GAP_DEVICE_IDENTITIES_SET = BLE_GAP_SVC_BASE + 3, /**< Set device identity list. */ + SD_BLE_GAP_PRIVACY_SET = BLE_GAP_SVC_BASE + 4, /**< Set Privacy settings*/ + SD_BLE_GAP_PRIVACY_GET = BLE_GAP_SVC_BASE + 5, /**< Get Privacy settings*/ + SD_BLE_GAP_ADV_SET_CONFIGURE = BLE_GAP_SVC_BASE + 6, /**< Configure an advertising set. */ + SD_BLE_GAP_ADV_START = BLE_GAP_SVC_BASE + 7, /**< Start Advertising. */ + SD_BLE_GAP_ADV_STOP = BLE_GAP_SVC_BASE + 8, /**< Stop Advertising. */ + SD_BLE_GAP_CONN_PARAM_UPDATE = BLE_GAP_SVC_BASE + 9, /**< Connection Parameter Update. */ + SD_BLE_GAP_DISCONNECT = BLE_GAP_SVC_BASE + 10, /**< Disconnect. */ + SD_BLE_GAP_TX_POWER_SET = BLE_GAP_SVC_BASE + 11, /**< Set TX Power. */ + SD_BLE_GAP_APPEARANCE_SET = BLE_GAP_SVC_BASE + 12, /**< Set Appearance. */ + SD_BLE_GAP_APPEARANCE_GET = BLE_GAP_SVC_BASE + 13, /**< Get Appearance. */ + SD_BLE_GAP_PPCP_SET = BLE_GAP_SVC_BASE + 14, /**< Set PPCP. */ + SD_BLE_GAP_PPCP_GET = BLE_GAP_SVC_BASE + 15, /**< Get PPCP. */ + SD_BLE_GAP_DEVICE_NAME_SET = BLE_GAP_SVC_BASE + 16, /**< Set Device Name. */ + SD_BLE_GAP_DEVICE_NAME_GET = BLE_GAP_SVC_BASE + 17, /**< Get Device Name. */ + SD_BLE_GAP_AUTHENTICATE = BLE_GAP_SVC_BASE + 18, /**< Initiate Pairing/Bonding. */ + SD_BLE_GAP_SEC_PARAMS_REPLY = BLE_GAP_SVC_BASE + 19, /**< Reply with Security Parameters. */ + SD_BLE_GAP_AUTH_KEY_REPLY = BLE_GAP_SVC_BASE + 20, /**< Reply with an authentication key. */ + SD_BLE_GAP_LESC_DHKEY_REPLY = BLE_GAP_SVC_BASE + 21, /**< Reply with an LE Secure Connections DHKey. */ + SD_BLE_GAP_KEYPRESS_NOTIFY = BLE_GAP_SVC_BASE + 22, /**< Notify of a keypress during an authentication procedure. */ + SD_BLE_GAP_LESC_OOB_DATA_GET = BLE_GAP_SVC_BASE + 23, /**< Get the local LE Secure Connections OOB data. */ + SD_BLE_GAP_LESC_OOB_DATA_SET = BLE_GAP_SVC_BASE + 24, /**< Set the remote LE Secure Connections OOB data. */ + SD_BLE_GAP_ENCRYPT = BLE_GAP_SVC_BASE + 25, /**< Initiate encryption procedure. */ + SD_BLE_GAP_SEC_INFO_REPLY = BLE_GAP_SVC_BASE + 26, /**< Reply with Security Information. */ + SD_BLE_GAP_CONN_SEC_GET = BLE_GAP_SVC_BASE + 27, /**< Obtain connection security level. */ + SD_BLE_GAP_RSSI_START = BLE_GAP_SVC_BASE + 28, /**< Start reporting of changes in RSSI. */ + SD_BLE_GAP_RSSI_STOP = BLE_GAP_SVC_BASE + 29, /**< Stop reporting of changes in RSSI. */ + SD_BLE_GAP_SCAN_START = BLE_GAP_SVC_BASE + 30, /**< Start Scanning. */ + SD_BLE_GAP_SCAN_STOP = BLE_GAP_SVC_BASE + 31, /**< Stop Scanning. */ + SD_BLE_GAP_CONNECT = BLE_GAP_SVC_BASE + 32, /**< Connect. */ + SD_BLE_GAP_CONNECT_CANCEL = BLE_GAP_SVC_BASE + 33, /**< Cancel ongoing connection procedure. */ + SD_BLE_GAP_RSSI_GET = BLE_GAP_SVC_BASE + 34, /**< Get the last RSSI sample. */ + SD_BLE_GAP_PHY_UPDATE = BLE_GAP_SVC_BASE + 35, /**< Initiate or respond to a PHY Update Procedure. */ + SD_BLE_GAP_DATA_LENGTH_UPDATE = BLE_GAP_SVC_BASE + 36, /**< Initiate or respond to a Data Length Update Procedure. */ + SD_BLE_GAP_QOS_CHANNEL_SURVEY_START = BLE_GAP_SVC_BASE + 37, /**< Start Quality of Service (QoS) channel survey module. */ + SD_BLE_GAP_QOS_CHANNEL_SURVEY_STOP = BLE_GAP_SVC_BASE + 38, /**< Stop Quality of Service (QoS) channel survey module. */ + SD_BLE_GAP_ADV_ADDR_GET = BLE_GAP_SVC_BASE + 39, /**< Get the Address used on air while Advertising. */ +}; + +/**@brief GAP Event IDs. + * IDs that uniquely identify an event coming from the stack to the application. + */ +enum BLE_GAP_EVTS +{ + BLE_GAP_EVT_CONNECTED = BLE_GAP_EVT_BASE, /**< Connected to peer. \n See @ref ble_gap_evt_connected_t */ + BLE_GAP_EVT_DISCONNECTED = BLE_GAP_EVT_BASE + 1, /**< Disconnected from peer. \n See @ref ble_gap_evt_disconnected_t. */ + BLE_GAP_EVT_CONN_PARAM_UPDATE = BLE_GAP_EVT_BASE + 2, /**< Connection Parameters updated. \n See @ref ble_gap_evt_conn_param_update_t. */ + BLE_GAP_EVT_SEC_PARAMS_REQUEST = BLE_GAP_EVT_BASE + 3, /**< Request to provide security parameters. \n Reply with @ref sd_ble_gap_sec_params_reply. \n See @ref ble_gap_evt_sec_params_request_t. */ + BLE_GAP_EVT_SEC_INFO_REQUEST = BLE_GAP_EVT_BASE + 4, /**< Request to provide security information. \n Reply with @ref sd_ble_gap_sec_info_reply. \n See @ref ble_gap_evt_sec_info_request_t. */ + BLE_GAP_EVT_PASSKEY_DISPLAY = BLE_GAP_EVT_BASE + 5, /**< Request to display a passkey to the user. \n In LESC Numeric Comparison, reply with @ref sd_ble_gap_auth_key_reply. \n See @ref ble_gap_evt_passkey_display_t. */ + BLE_GAP_EVT_KEY_PRESSED = BLE_GAP_EVT_BASE + 6, /**< Notification of a keypress on the remote device.\n See @ref ble_gap_evt_key_pressed_t */ + BLE_GAP_EVT_AUTH_KEY_REQUEST = BLE_GAP_EVT_BASE + 7, /**< Request to provide an authentication key. \n Reply with @ref sd_ble_gap_auth_key_reply. \n See @ref ble_gap_evt_auth_key_request_t. */ + BLE_GAP_EVT_LESC_DHKEY_REQUEST = BLE_GAP_EVT_BASE + 8, /**< Request to calculate an LE Secure Connections DHKey. \n Reply with @ref sd_ble_gap_lesc_dhkey_reply. \n See @ref ble_gap_evt_lesc_dhkey_request_t */ + BLE_GAP_EVT_AUTH_STATUS = BLE_GAP_EVT_BASE + 9, /**< Authentication procedure completed with status. \n See @ref ble_gap_evt_auth_status_t. */ + BLE_GAP_EVT_CONN_SEC_UPDATE = BLE_GAP_EVT_BASE + 10, /**< Connection security updated. \n See @ref ble_gap_evt_conn_sec_update_t. */ + BLE_GAP_EVT_TIMEOUT = BLE_GAP_EVT_BASE + 11, /**< Timeout expired. \n See @ref ble_gap_evt_timeout_t. */ + BLE_GAP_EVT_RSSI_CHANGED = BLE_GAP_EVT_BASE + 12, /**< RSSI report. \n See @ref ble_gap_evt_rssi_changed_t. */ + BLE_GAP_EVT_ADV_REPORT = BLE_GAP_EVT_BASE + 13, /**< Advertising report. \n See @ref ble_gap_evt_adv_report_t. */ + BLE_GAP_EVT_SEC_REQUEST = BLE_GAP_EVT_BASE + 14, /**< Security Request. \n See @ref ble_gap_evt_sec_request_t. */ + BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST = BLE_GAP_EVT_BASE + 15, /**< Connection Parameter Update Request. \n Reply with @ref sd_ble_gap_conn_param_update. \n See @ref ble_gap_evt_conn_param_update_request_t. */ + BLE_GAP_EVT_SCAN_REQ_REPORT = BLE_GAP_EVT_BASE + 16, /**< Scan request report. \n See @ref ble_gap_evt_scan_req_report_t. */ + BLE_GAP_EVT_PHY_UPDATE_REQUEST = BLE_GAP_EVT_BASE + 17, /**< PHY Update Request. \n Reply with @ref sd_ble_gap_phy_update. \n See @ref ble_gap_evt_phy_update_request_t. */ + BLE_GAP_EVT_PHY_UPDATE = BLE_GAP_EVT_BASE + 18, /**< PHY Update Procedure is complete. \n See @ref ble_gap_evt_phy_update_t. */ + BLE_GAP_EVT_DATA_LENGTH_UPDATE_REQUEST = BLE_GAP_EVT_BASE + 19, /**< Data Length Update Request. \n Reply with @ref sd_ble_gap_data_length_update.\n See @ref ble_gap_evt_data_length_update_request_t. */ + BLE_GAP_EVT_DATA_LENGTH_UPDATE = BLE_GAP_EVT_BASE + 20, /**< LL Data Channel PDU payload length updated. \n See @ref ble_gap_evt_data_length_update_t. */ + BLE_GAP_EVT_QOS_CHANNEL_SURVEY_REPORT = BLE_GAP_EVT_BASE + 21, /**< Channel survey report. \n See @ref ble_gap_evt_qos_channel_survey_report_t. */ + BLE_GAP_EVT_ADV_SET_TERMINATED = BLE_GAP_EVT_BASE + 22, /**< Advertising set terminated. \n See @ref ble_gap_evt_adv_set_terminated_t. */ +}; + +/**@brief GAP Option IDs. + * IDs that uniquely identify a GAP option. + */ +enum BLE_GAP_OPTS +{ + BLE_GAP_OPT_CH_MAP = BLE_GAP_OPT_BASE, /**< Channel Map. @ref ble_gap_opt_ch_map_t */ + BLE_GAP_OPT_LOCAL_CONN_LATENCY = BLE_GAP_OPT_BASE + 1, /**< Local connection latency. @ref ble_gap_opt_local_conn_latency_t */ + BLE_GAP_OPT_PASSKEY = BLE_GAP_OPT_BASE + 2, /**< Set passkey. @ref ble_gap_opt_passkey_t */ + BLE_GAP_OPT_COMPAT_MODE_1 = BLE_GAP_OPT_BASE + 3, /**< Compatibility mode. @ref ble_gap_opt_compat_mode_1_t */ + BLE_GAP_OPT_AUTH_PAYLOAD_TIMEOUT = BLE_GAP_OPT_BASE + 4, /**< Set Authenticated payload timeout. @ref ble_gap_opt_auth_payload_timeout_t */ + BLE_GAP_OPT_SLAVE_LATENCY_DISABLE = BLE_GAP_OPT_BASE + 5, /**< Disable slave latency. @ref ble_gap_opt_slave_latency_disable_t */ +}; + +/**@brief GAP Configuration IDs. + * + * IDs that uniquely identify a GAP configuration. + */ +enum BLE_GAP_CFGS +{ + BLE_GAP_CFG_ROLE_COUNT = BLE_GAP_CFG_BASE, /**< Role count configuration. */ + BLE_GAP_CFG_DEVICE_NAME = BLE_GAP_CFG_BASE + 1, /**< Device name configuration. */ +}; + +/**@brief GAP TX Power roles. + */ +enum BLE_GAP_TX_POWER_ROLES +{ + BLE_GAP_TX_POWER_ROLE_ADV = 1, /**< Advertiser role. */ + BLE_GAP_TX_POWER_ROLE_SCAN_INIT = 2, /**< Scanner and initiator role. */ + BLE_GAP_TX_POWER_ROLE_CONN = 3, /**< Connection role. */ +}; + +/** @} */ + +/**@addtogroup BLE_GAP_DEFINES Defines + * @{ */ + +/**@defgroup BLE_ERRORS_GAP SVC return values specific to GAP + * @{ */ +#define BLE_ERROR_GAP_UUID_LIST_MISMATCH (NRF_GAP_ERR_BASE + 0x000) /**< UUID list does not contain an integral number of UUIDs. */ +#define BLE_ERROR_GAP_DISCOVERABLE_WITH_WHITELIST (NRF_GAP_ERR_BASE + 0x001) /**< Use of Whitelist not permitted with discoverable advertising. */ +#define BLE_ERROR_GAP_INVALID_BLE_ADDR (NRF_GAP_ERR_BASE + 0x002) /**< The upper two bits of the address do not correspond to the specified address type. */ +#define BLE_ERROR_GAP_WHITELIST_IN_USE (NRF_GAP_ERR_BASE + 0x003) /**< Attempt to modify the whitelist while already in use by another operation. */ +#define BLE_ERROR_GAP_DEVICE_IDENTITIES_IN_USE (NRF_GAP_ERR_BASE + 0x004) /**< Attempt to modify the device identity list while already in use by another operation. */ +#define BLE_ERROR_GAP_DEVICE_IDENTITIES_DUPLICATE (NRF_GAP_ERR_BASE + 0x005) /**< The device identity list contains entries with duplicate identity addresses. */ +/**@} */ + + +/**@defgroup BLE_GAP_ROLES GAP Roles + * @{ */ +#define BLE_GAP_ROLE_INVALID 0x0 /**< Invalid Role. */ +#define BLE_GAP_ROLE_PERIPH 0x1 /**< Peripheral Role. */ +#define BLE_GAP_ROLE_CENTRAL 0x2 /**< Central Role. */ +/**@} */ + + +/**@defgroup BLE_GAP_TIMEOUT_SOURCES GAP Timeout sources + * @{ */ +#define BLE_GAP_TIMEOUT_SRC_SCAN 0x01 /**< Scanning timeout. */ +#define BLE_GAP_TIMEOUT_SRC_CONN 0x02 /**< Connection timeout. */ +#define BLE_GAP_TIMEOUT_SRC_AUTH_PAYLOAD 0x03 /**< Authenticated payload timeout. */ +/**@} */ + + +/**@defgroup BLE_GAP_ADDR_TYPES GAP Address types + * @{ */ +#define BLE_GAP_ADDR_TYPE_PUBLIC 0x00 /**< Public (identity) address.*/ +#define BLE_GAP_ADDR_TYPE_RANDOM_STATIC 0x01 /**< Random static (identity) address. */ +#define BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE 0x02 /**< Random private resolvable address. */ +#define BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE 0x03 /**< Random private non-resolvable address. */ +#define BLE_GAP_ADDR_TYPE_ANONYMOUS 0x7F /**< An advertiser may advertise without its address. + This type of advertising is called anonymous. */ +/**@} */ + + +/**@brief The default interval in seconds at which a private address is refreshed. */ +#define BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S (900) /* 15 minutes. */ +/**@brief The maximum interval in seconds at which a private address can be refreshed. */ +#define BLE_GAP_MAX_PRIVATE_ADDR_CYCLE_INTERVAL_S (41400) /* 11 hours 30 minutes. */ + + +/** @brief BLE address length. */ +#define BLE_GAP_ADDR_LEN (6) + +/**@defgroup BLE_GAP_PRIVACY_MODES Privacy modes + * @{ */ +#define BLE_GAP_PRIVACY_MODE_OFF 0x00 /**< Device will send and accept its identity address for its own address. */ +#define BLE_GAP_PRIVACY_MODE_DEVICE_PRIVACY 0x01 /**< Device will send and accept only private addresses for its own address. */ +#define BLE_GAP_PRIVACY_MODE_NETWORK_PRIVACY 0x02 /**< Device will send and accept only private addresses for its own address, + and will not accept a peer using identity address as sender address when + the peer IRK is exchanged, non-zero and added to the identity list. */ +/**@} */ + +/** @brief Invalid power level. */ +#define BLE_GAP_POWER_LEVEL_INVALID 127 + +/** @brief Advertising set handle not set. */ +#define BLE_GAP_ADV_SET_HANDLE_NOT_SET (0xFF) + +/** @brief The default number of advertising sets. */ +#define BLE_GAP_ADV_SET_COUNT_DEFAULT (1) + +/** @brief The maximum number of advertising sets supported by this SoftDevice. */ +#define BLE_GAP_ADV_SET_COUNT_MAX (1) + +/**@defgroup BLE_GAP_ADV_SET_DATA_SIZES Advertising data sizes. + * @{ */ +#define BLE_GAP_ADV_SET_DATA_SIZE_MAX (31) /**< Maximum data length for an advertising set. + If more advertising data is required, use extended advertising instead. */ +#define BLE_GAP_ADV_SET_DATA_SIZE_EXTENDED_MAX_SUPPORTED (255) /**< Maximum supported data length for an extended advertising set. */ + +#define BLE_GAP_ADV_SET_DATA_SIZE_EXTENDED_CONNECTABLE_MAX_SUPPORTED (238) /**< Maximum supported data length for an extended connectable advertising set. */ +/**@}. */ + +/** @brief Set ID not available in advertising report. */ +#define BLE_GAP_ADV_REPORT_SET_ID_NOT_AVAILABLE 0xFF + +/**@defgroup BLE_GAP_EVT_ADV_SET_TERMINATED_REASON GAP Advertising Set Terminated reasons + * @{ */ +#define BLE_GAP_EVT_ADV_SET_TERMINATED_REASON_TIMEOUT 0x01 /**< Timeout value reached. */ +#define BLE_GAP_EVT_ADV_SET_TERMINATED_REASON_LIMIT_REACHED 0x02 /**< @ref ble_gap_adv_params_t::max_adv_evts was reached. */ +/**@} */ + +/**@defgroup BLE_GAP_AD_TYPE_DEFINITIONS GAP Advertising and Scan Response Data format + * @note Found at https://www.bluetooth.org/Technical/AssignedNumbers/generic_access_profile.htm + * @{ */ +#define BLE_GAP_AD_TYPE_FLAGS 0x01 /**< Flags for discoverability. */ +#define BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_MORE_AVAILABLE 0x02 /**< Partial list of 16 bit service UUIDs. */ +#define BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_COMPLETE 0x03 /**< Complete list of 16 bit service UUIDs. */ +#define BLE_GAP_AD_TYPE_32BIT_SERVICE_UUID_MORE_AVAILABLE 0x04 /**< Partial list of 32 bit service UUIDs. */ +#define BLE_GAP_AD_TYPE_32BIT_SERVICE_UUID_COMPLETE 0x05 /**< Complete list of 32 bit service UUIDs. */ +#define BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_MORE_AVAILABLE 0x06 /**< Partial list of 128 bit service UUIDs. */ +#define BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_COMPLETE 0x07 /**< Complete list of 128 bit service UUIDs. */ +#define BLE_GAP_AD_TYPE_SHORT_LOCAL_NAME 0x08 /**< Short local device name. */ +#define BLE_GAP_AD_TYPE_COMPLETE_LOCAL_NAME 0x09 /**< Complete local device name. */ +#define BLE_GAP_AD_TYPE_TX_POWER_LEVEL 0x0A /**< Transmit power level. */ +#define BLE_GAP_AD_TYPE_CLASS_OF_DEVICE 0x0D /**< Class of device. */ +#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_HASH_C 0x0E /**< Simple Pairing Hash C. */ +#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_RANDOMIZER_R 0x0F /**< Simple Pairing Randomizer R. */ +#define BLE_GAP_AD_TYPE_SECURITY_MANAGER_TK_VALUE 0x10 /**< Security Manager TK Value. */ +#define BLE_GAP_AD_TYPE_SECURITY_MANAGER_OOB_FLAGS 0x11 /**< Security Manager Out Of Band Flags. */ +#define BLE_GAP_AD_TYPE_SLAVE_CONNECTION_INTERVAL_RANGE 0x12 /**< Slave Connection Interval Range. */ +#define BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_16BIT 0x14 /**< List of 16-bit Service Solicitation UUIDs. */ +#define BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_128BIT 0x15 /**< List of 128-bit Service Solicitation UUIDs. */ +#define BLE_GAP_AD_TYPE_SERVICE_DATA 0x16 /**< Service Data - 16-bit UUID. */ +#define BLE_GAP_AD_TYPE_PUBLIC_TARGET_ADDRESS 0x17 /**< Public Target Address. */ +#define BLE_GAP_AD_TYPE_RANDOM_TARGET_ADDRESS 0x18 /**< Random Target Address. */ +#define BLE_GAP_AD_TYPE_APPEARANCE 0x19 /**< Appearance. */ +#define BLE_GAP_AD_TYPE_ADVERTISING_INTERVAL 0x1A /**< Advertising Interval. */ +#define BLE_GAP_AD_TYPE_LE_BLUETOOTH_DEVICE_ADDRESS 0x1B /**< LE Bluetooth Device Address. */ +#define BLE_GAP_AD_TYPE_LE_ROLE 0x1C /**< LE Role. */ +#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_HASH_C256 0x1D /**< Simple Pairing Hash C-256. */ +#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_RANDOMIZER_R256 0x1E /**< Simple Pairing Randomizer R-256. */ +#define BLE_GAP_AD_TYPE_SERVICE_DATA_32BIT_UUID 0x20 /**< Service Data - 32-bit UUID. */ +#define BLE_GAP_AD_TYPE_SERVICE_DATA_128BIT_UUID 0x21 /**< Service Data - 128-bit UUID. */ +#define BLE_GAP_AD_TYPE_LESC_CONFIRMATION_VALUE 0x22 /**< LE Secure Connections Confirmation Value */ +#define BLE_GAP_AD_TYPE_LESC_RANDOM_VALUE 0x23 /**< LE Secure Connections Random Value */ +#define BLE_GAP_AD_TYPE_URI 0x24 /**< URI */ +#define BLE_GAP_AD_TYPE_3D_INFORMATION_DATA 0x3D /**< 3D Information Data. */ +#define BLE_GAP_AD_TYPE_MANUFACTURER_SPECIFIC_DATA 0xFF /**< Manufacturer Specific Data. */ +/**@} */ + + +/**@defgroup BLE_GAP_ADV_FLAGS GAP Advertisement Flags + * @{ */ +#define BLE_GAP_ADV_FLAG_LE_LIMITED_DISC_MODE (0x01) /**< LE Limited Discoverable Mode. */ +#define BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE (0x02) /**< LE General Discoverable Mode. */ +#define BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED (0x04) /**< BR/EDR not supported. */ +#define BLE_GAP_ADV_FLAG_LE_BR_EDR_CONTROLLER (0x08) /**< Simultaneous LE and BR/EDR, Controller. */ +#define BLE_GAP_ADV_FLAG_LE_BR_EDR_HOST (0x10) /**< Simultaneous LE and BR/EDR, Host. */ +#define BLE_GAP_ADV_FLAGS_LE_ONLY_LIMITED_DISC_MODE (BLE_GAP_ADV_FLAG_LE_LIMITED_DISC_MODE | BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED) /**< LE Limited Discoverable Mode, BR/EDR not supported. */ +#define BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE (BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE | BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED) /**< LE General Discoverable Mode, BR/EDR not supported. */ +/**@} */ + + +/**@defgroup BLE_GAP_ADV_INTERVALS GAP Advertising interval max and min + * @{ */ +#define BLE_GAP_ADV_INTERVAL_MIN 0x000020 /**< Minimum Advertising interval in 625 us units, i.e. 20 ms. */ +#define BLE_GAP_ADV_INTERVAL_MAX 0x004000 /**< Maximum Advertising interval in 625 us units, i.e. 10.24 s. */ + /**@} */ + + +/**@defgroup BLE_GAP_SCAN_INTERVALS GAP Scan interval max and min + * @{ */ +#define BLE_GAP_SCAN_INTERVAL_MIN 0x0004 /**< Minimum Scan interval in 625 us units, i.e. 2.5 ms. */ +#define BLE_GAP_SCAN_INTERVAL_MAX 0xFFFF /**< Maximum Scan interval in 625 us units, i.e. 40,959.375 s. */ + /** @} */ + + +/**@defgroup BLE_GAP_SCAN_WINDOW GAP Scan window max and min + * @{ */ +#define BLE_GAP_SCAN_WINDOW_MIN 0x0004 /**< Minimum Scan window in 625 us units, i.e. 2.5 ms. */ +#define BLE_GAP_SCAN_WINDOW_MAX 0xFFFF /**< Maximum Scan window in 625 us units, i.e. 40,959.375 s. */ + /** @} */ + + +/**@defgroup BLE_GAP_SCAN_TIMEOUT GAP Scan timeout max and min + * @{ */ +#define BLE_GAP_SCAN_TIMEOUT_MIN 0x0001 /**< Minimum Scan timeout in 10 ms units, i.e 10 ms. */ +#define BLE_GAP_SCAN_TIMEOUT_UNLIMITED 0x0000 /**< Continue to scan forever. */ + /** @} */ + +/**@defgroup BLE_GAP_SCAN_BUFFER_SIZE GAP Minimum scanner buffer size + * + * Scan buffers are used for storing advertising data received from an advertiser. + * If ble_gap_scan_params_t::extended is set to 0, @ref BLE_GAP_SCAN_BUFFER_MIN is the minimum scan buffer length. + * else the minimum scan buffer size is @ref BLE_GAP_SCAN_BUFFER_EXTENDED_MIN. + * @{ */ +#define BLE_GAP_SCAN_BUFFER_MIN (31) /**< Minimum data length for an + advertising set. */ +#define BLE_GAP_SCAN_BUFFER_MAX (31) /**< Maximum data length for an + advertising set. */ +#define BLE_GAP_SCAN_BUFFER_EXTENDED_MIN (255) /**< Minimum data length for an + extended advertising set. */ +#define BLE_GAP_SCAN_BUFFER_EXTENDED_MAX (1650) /**< Maximum data length for an + extended advertising set. */ +#define BLE_GAP_SCAN_BUFFER_EXTENDED_MAX_SUPPORTED (255) /**< Maximum supported data length for + an extended advertising set. */ +/** @} */ + +/**@defgroup BLE_GAP_ADV_TYPES GAP Advertising types + * + * Advertising types defined in Bluetooth Core Specification v5.0, Vol 6, Part B, Section 4.4.2. + * + * The maximum advertising data length is defined by @ref BLE_GAP_ADV_SET_DATA_SIZE_MAX. + * The maximum supported data length for an extended advertiser is defined by + * @ref BLE_GAP_ADV_SET_DATA_SIZE_EXTENDED_MAX_SUPPORTED + * Note that some of the advertising types do not support advertising data. Non-scannable types do not support + * scan response data. + * + * @{ */ +#define BLE_GAP_ADV_TYPE_CONNECTABLE_SCANNABLE_UNDIRECTED 0x01 /**< Connectable and scannable undirected + advertising events. */ +#define BLE_GAP_ADV_TYPE_CONNECTABLE_NONSCANNABLE_DIRECTED_HIGH_DUTY_CYCLE 0x02 /**< Connectable non-scannable directed advertising + events. Advertising interval is less that 3.75 ms. + Use this type for fast reconnections. + @note Advertising data is not supported. */ +#define BLE_GAP_ADV_TYPE_CONNECTABLE_NONSCANNABLE_DIRECTED 0x03 /**< Connectable non-scannable directed advertising + events. + @note Advertising data is not supported. */ +#define BLE_GAP_ADV_TYPE_NONCONNECTABLE_SCANNABLE_UNDIRECTED 0x04 /**< Non-connectable scannable undirected + advertising events. */ +#define BLE_GAP_ADV_TYPE_NONCONNECTABLE_NONSCANNABLE_UNDIRECTED 0x05 /**< Non-connectable non-scannable undirected + advertising events. */ +#define BLE_GAP_ADV_TYPE_EXTENDED_CONNECTABLE_NONSCANNABLE_UNDIRECTED 0x06 /**< Connectable non-scannable undirected advertising + events using extended advertising PDUs. */ +#define BLE_GAP_ADV_TYPE_EXTENDED_CONNECTABLE_NONSCANNABLE_DIRECTED 0x07 /**< Connectable non-scannable directed advertising + events using extended advertising PDUs. */ +#define BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_SCANNABLE_UNDIRECTED 0x08 /**< Non-connectable scannable undirected advertising + events using extended advertising PDUs. + @note Only scan response data is supported. */ +#define BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_SCANNABLE_DIRECTED 0x09 /**< Non-connectable scannable directed advertising + events using extended advertising PDUs. + @note Only scan response data is supported. */ +#define BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_NONSCANNABLE_UNDIRECTED 0x0A /**< Non-connectable non-scannable undirected advertising + events using extended advertising PDUs. */ +#define BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_NONSCANNABLE_DIRECTED 0x0B /**< Non-connectable non-scannable directed advertising + events using extended advertising PDUs. */ +/**@} */ + +/**@defgroup BLE_GAP_ADV_FILTER_POLICIES GAP Advertising filter policies + * @{ */ +#define BLE_GAP_ADV_FP_ANY 0x00 /**< Allow scan requests and connect requests from any device. */ +#define BLE_GAP_ADV_FP_FILTER_SCANREQ 0x01 /**< Filter scan requests with whitelist. */ +#define BLE_GAP_ADV_FP_FILTER_CONNREQ 0x02 /**< Filter connect requests with whitelist. */ +#define BLE_GAP_ADV_FP_FILTER_BOTH 0x03 /**< Filter both scan and connect requests with whitelist. */ +/**@} */ + +/**@defgroup BLE_GAP_ADV_DATA_STATUS GAP Advertising data status + * @{ */ +#define BLE_GAP_ADV_DATA_STATUS_COMPLETE 0x00 /**< All data in the advertising event have been received. */ +#define BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA 0x01 /**< More data to be received. + @note This value will only be used if + @ref ble_gap_scan_params_t::report_incomplete_evts and + @ref ble_gap_adv_report_type_t::extended_pdu are set to true. */ +#define BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_TRUNCATED 0x02 /**< Incomplete data. Buffer size insufficient to receive more. + @note This value will only be used if + @ref ble_gap_adv_report_type_t::extended_pdu is set to true. */ +#define BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MISSED 0x03 /**< Failed to receive the remaining data. + @note This value will only be used if + @ref ble_gap_adv_report_type_t::extended_pdu is set to true. */ +/**@} */ + +/**@defgroup BLE_GAP_SCAN_FILTER_POLICIES GAP Scanner filter policies + * @{ */ +#define BLE_GAP_SCAN_FP_ACCEPT_ALL 0x00 /**< Accept all advertising packets except directed advertising packets + not addressed to this device. */ +#define BLE_GAP_SCAN_FP_WHITELIST 0x01 /**< Accept advertising packets from devices in the whitelist except directed + packets not addressed to this device. */ +#define BLE_GAP_SCAN_FP_ALL_NOT_RESOLVED_DIRECTED 0x02 /**< Accept all advertising packets specified in @ref BLE_GAP_SCAN_FP_ACCEPT_ALL. + In addition, accept directed advertising packets, where the advertiser's + address is a resolvable private address that cannot be resolved. */ +#define BLE_GAP_SCAN_FP_WHITELIST_NOT_RESOLVED_DIRECTED 0x03 /**< Accept all advertising packets specified in @ref BLE_GAP_SCAN_FP_WHITELIST. + In addition, accept directed advertising packets, where the advertiser's + address is a resolvable private address that cannot be resolved. */ +/**@} */ + +/**@defgroup BLE_GAP_ADV_TIMEOUT_VALUES GAP Advertising timeout values in 10 ms units + * @{ */ +#define BLE_GAP_ADV_TIMEOUT_HIGH_DUTY_MAX (128) /**< Maximum high duty advertising time in 10 ms units. Corresponds to 1.28 s. */ +#define BLE_GAP_ADV_TIMEOUT_LIMITED_MAX (18000) /**< Maximum advertising time in 10 ms units corresponding to TGAP(lim_adv_timeout) = 180 s in limited discoverable mode. */ +#define BLE_GAP_ADV_TIMEOUT_GENERAL_UNLIMITED (0) /**< Unlimited advertising in general discoverable mode. + For high duty cycle advertising, this corresponds to @ref BLE_GAP_ADV_TIMEOUT_HIGH_DUTY_MAX. */ +/**@} */ + + +/**@defgroup BLE_GAP_DISC_MODES GAP Discovery modes + * @{ */ +#define BLE_GAP_DISC_MODE_NOT_DISCOVERABLE 0x00 /**< Not discoverable discovery Mode. */ +#define BLE_GAP_DISC_MODE_LIMITED 0x01 /**< Limited Discovery Mode. */ +#define BLE_GAP_DISC_MODE_GENERAL 0x02 /**< General Discovery Mode. */ +/**@} */ + + +/**@defgroup BLE_GAP_IO_CAPS GAP IO Capabilities + * @{ */ +#define BLE_GAP_IO_CAPS_DISPLAY_ONLY 0x00 /**< Display Only. */ +#define BLE_GAP_IO_CAPS_DISPLAY_YESNO 0x01 /**< Display and Yes/No entry. */ +#define BLE_GAP_IO_CAPS_KEYBOARD_ONLY 0x02 /**< Keyboard Only. */ +#define BLE_GAP_IO_CAPS_NONE 0x03 /**< No I/O capabilities. */ +#define BLE_GAP_IO_CAPS_KEYBOARD_DISPLAY 0x04 /**< Keyboard and Display. */ +/**@} */ + + +/**@defgroup BLE_GAP_AUTH_KEY_TYPES GAP Authentication Key Types + * @{ */ +#define BLE_GAP_AUTH_KEY_TYPE_NONE 0x00 /**< No key (may be used to reject). */ +#define BLE_GAP_AUTH_KEY_TYPE_PASSKEY 0x01 /**< 6-digit Passkey. */ +#define BLE_GAP_AUTH_KEY_TYPE_OOB 0x02 /**< Out Of Band data. */ +/**@} */ + + +/**@defgroup BLE_GAP_KP_NOT_TYPES GAP Keypress Notification Types + * @{ */ +#define BLE_GAP_KP_NOT_TYPE_PASSKEY_START 0x00 /**< Passkey entry started. */ +#define BLE_GAP_KP_NOT_TYPE_PASSKEY_DIGIT_IN 0x01 /**< Passkey digit entered. */ +#define BLE_GAP_KP_NOT_TYPE_PASSKEY_DIGIT_OUT 0x02 /**< Passkey digit erased. */ +#define BLE_GAP_KP_NOT_TYPE_PASSKEY_CLEAR 0x03 /**< Passkey cleared. */ +#define BLE_GAP_KP_NOT_TYPE_PASSKEY_END 0x04 /**< Passkey entry completed. */ +/**@} */ + + +/**@defgroup BLE_GAP_SEC_STATUS GAP Security status + * @{ */ +#define BLE_GAP_SEC_STATUS_SUCCESS 0x00 /**< Procedure completed with success. */ +#define BLE_GAP_SEC_STATUS_TIMEOUT 0x01 /**< Procedure timed out. */ +#define BLE_GAP_SEC_STATUS_PDU_INVALID 0x02 /**< Invalid PDU received. */ +#define BLE_GAP_SEC_STATUS_RFU_RANGE1_BEGIN 0x03 /**< Reserved for Future Use range #1 begin. */ +#define BLE_GAP_SEC_STATUS_RFU_RANGE1_END 0x80 /**< Reserved for Future Use range #1 end. */ +#define BLE_GAP_SEC_STATUS_PASSKEY_ENTRY_FAILED 0x81 /**< Passkey entry failed (user canceled or other). */ +#define BLE_GAP_SEC_STATUS_OOB_NOT_AVAILABLE 0x82 /**< Out of Band Key not available. */ +#define BLE_GAP_SEC_STATUS_AUTH_REQ 0x83 /**< Authentication requirements not met. */ +#define BLE_GAP_SEC_STATUS_CONFIRM_VALUE 0x84 /**< Confirm value failed. */ +#define BLE_GAP_SEC_STATUS_PAIRING_NOT_SUPP 0x85 /**< Pairing not supported. */ +#define BLE_GAP_SEC_STATUS_ENC_KEY_SIZE 0x86 /**< Encryption key size. */ +#define BLE_GAP_SEC_STATUS_SMP_CMD_UNSUPPORTED 0x87 /**< Unsupported SMP command. */ +#define BLE_GAP_SEC_STATUS_UNSPECIFIED 0x88 /**< Unspecified reason. */ +#define BLE_GAP_SEC_STATUS_REPEATED_ATTEMPTS 0x89 /**< Too little time elapsed since last attempt. */ +#define BLE_GAP_SEC_STATUS_INVALID_PARAMS 0x8A /**< Invalid parameters. */ +#define BLE_GAP_SEC_STATUS_DHKEY_FAILURE 0x8B /**< DHKey check failure. */ +#define BLE_GAP_SEC_STATUS_NUM_COMP_FAILURE 0x8C /**< Numeric Comparison failure. */ +#define BLE_GAP_SEC_STATUS_BR_EDR_IN_PROG 0x8D /**< BR/EDR pairing in progress. */ +#define BLE_GAP_SEC_STATUS_X_TRANS_KEY_DISALLOWED 0x8E /**< BR/EDR Link Key cannot be used for LE keys. */ +#define BLE_GAP_SEC_STATUS_RFU_RANGE2_BEGIN 0x8F /**< Reserved for Future Use range #2 begin. */ +#define BLE_GAP_SEC_STATUS_RFU_RANGE2_END 0xFF /**< Reserved for Future Use range #2 end. */ +/**@} */ + + +/**@defgroup BLE_GAP_SEC_STATUS_SOURCES GAP Security status sources + * @{ */ +#define BLE_GAP_SEC_STATUS_SOURCE_LOCAL 0x00 /**< Local failure. */ +#define BLE_GAP_SEC_STATUS_SOURCE_REMOTE 0x01 /**< Remote failure. */ +/**@} */ + + +/**@defgroup BLE_GAP_CP_LIMITS GAP Connection Parameters Limits + * @{ */ +#define BLE_GAP_CP_MIN_CONN_INTVL_NONE 0xFFFF /**< No new minimum connection interval specified in connect parameters. */ +#define BLE_GAP_CP_MIN_CONN_INTVL_MIN 0x0006 /**< Lowest minimum connection interval permitted, in units of 1.25 ms, i.e. 7.5 ms. */ +#define BLE_GAP_CP_MIN_CONN_INTVL_MAX 0x0C80 /**< Highest minimum connection interval permitted, in units of 1.25 ms, i.e. 4 s. */ +#define BLE_GAP_CP_MAX_CONN_INTVL_NONE 0xFFFF /**< No new maximum connection interval specified in connect parameters. */ +#define BLE_GAP_CP_MAX_CONN_INTVL_MIN 0x0006 /**< Lowest maximum connection interval permitted, in units of 1.25 ms, i.e. 7.5 ms. */ +#define BLE_GAP_CP_MAX_CONN_INTVL_MAX 0x0C80 /**< Highest maximum connection interval permitted, in units of 1.25 ms, i.e. 4 s. */ +#define BLE_GAP_CP_SLAVE_LATENCY_MAX 0x01F3 /**< Highest slave latency permitted, in connection events. */ +#define BLE_GAP_CP_CONN_SUP_TIMEOUT_NONE 0xFFFF /**< No new supervision timeout specified in connect parameters. */ +#define BLE_GAP_CP_CONN_SUP_TIMEOUT_MIN 0x000A /**< Lowest supervision timeout permitted, in units of 10 ms, i.e. 100 ms. */ +#define BLE_GAP_CP_CONN_SUP_TIMEOUT_MAX 0x0C80 /**< Highest supervision timeout permitted, in units of 10 ms, i.e. 32 s. */ +/**@} */ + + +/**@defgroup BLE_GAP_DEVNAME GAP device name defines. + * @{ */ +#define BLE_GAP_DEVNAME_DEFAULT "nRF5x" /**< Default device name value. */ +#define BLE_GAP_DEVNAME_DEFAULT_LEN 31 /**< Default number of octets in device name. */ +#define BLE_GAP_DEVNAME_MAX_LEN 248 /**< Maximum number of octets in device name. */ +/**@} */ + + +/**@brief Disable RSSI events for connections */ +#define BLE_GAP_RSSI_THRESHOLD_INVALID 0xFF + +/**@defgroup BLE_GAP_PHYS GAP PHYs + * @{ */ +#define BLE_GAP_PHY_AUTO 0x00 /**< Automatic PHY selection. Refer @ref sd_ble_gap_phy_update for more information.*/ +#define BLE_GAP_PHY_1MBPS 0x01 /**< 1 Mbps PHY. */ +#define BLE_GAP_PHY_2MBPS 0x02 /**< 2 Mbps PHY. */ +#define BLE_GAP_PHY_CODED 0x04 /**< Coded PHY. */ +#define BLE_GAP_PHY_NOT_SET 0xFF /**< PHY is not configured. */ + +/**@brief Supported PHYs in connections, for scanning, and for advertising. */ +#define BLE_GAP_PHYS_SUPPORTED (BLE_GAP_PHY_1MBPS | BLE_GAP_PHY_2MBPS | BLE_GAP_PHY_CODED) /**< All PHYs are supported. */ + +/**@} */ + +/**@defgroup BLE_GAP_CONN_SEC_MODE_SET_MACROS GAP attribute security requirement setters + * + * See @ref ble_gap_conn_sec_mode_t. + * @{ */ +/**@brief Set sec_mode pointed to by ptr to have no access rights.*/ +#define BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(ptr) do {(ptr)->sm = 0; (ptr)->lv = 0;} while(0) +/**@brief Set sec_mode pointed to by ptr to require no protection, open link.*/ +#define BLE_GAP_CONN_SEC_MODE_SET_OPEN(ptr) do {(ptr)->sm = 1; (ptr)->lv = 1;} while(0) +/**@brief Set sec_mode pointed to by ptr to require encryption, but no MITM protection.*/ +#define BLE_GAP_CONN_SEC_MODE_SET_ENC_NO_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 2;} while(0) +/**@brief Set sec_mode pointed to by ptr to require encryption and MITM protection.*/ +#define BLE_GAP_CONN_SEC_MODE_SET_ENC_WITH_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 3;} while(0) +/**@brief Set sec_mode pointed to by ptr to require LESC encryption and MITM protection.*/ +#define BLE_GAP_CONN_SEC_MODE_SET_LESC_ENC_WITH_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 4;} while(0) +/**@brief Set sec_mode pointed to by ptr to require signing or encryption, no MITM protection needed.*/ +#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_NO_MITM(ptr) do {(ptr)->sm = 2; (ptr)->lv = 1;} while(0) +/**@brief Set sec_mode pointed to by ptr to require signing or encryption with MITM protection.*/ +#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_WITH_MITM(ptr) do {(ptr)->sm = 2; (ptr)->lv = 2;} while(0) +/**@} */ + + +/**@brief GAP Security Random Number Length. */ +#define BLE_GAP_SEC_RAND_LEN 8 + + +/**@brief GAP Security Key Length. */ +#define BLE_GAP_SEC_KEY_LEN 16 + + +/**@brief GAP LE Secure Connections Elliptic Curve Diffie-Hellman P-256 Public Key Length. */ +#define BLE_GAP_LESC_P256_PK_LEN 64 + + +/**@brief GAP LE Secure Connections Elliptic Curve Diffie-Hellman DHKey Length. */ +#define BLE_GAP_LESC_DHKEY_LEN 32 + + +/**@brief GAP Passkey Length. */ +#define BLE_GAP_PASSKEY_LEN 6 + + +/**@brief Maximum amount of addresses in the whitelist. */ +#define BLE_GAP_WHITELIST_ADDR_MAX_COUNT (8) + + +/**@brief Maximum amount of identities in the device identities list. */ +#define BLE_GAP_DEVICE_IDENTITIES_MAX_COUNT (8) + + +/**@brief Default connection count for a configuration. */ +#define BLE_GAP_CONN_COUNT_DEFAULT (1) + + +/**@defgroup BLE_GAP_EVENT_LENGTH GAP event length defines. + * @{ */ +#define BLE_GAP_EVENT_LENGTH_MIN (2) /**< Minimum event length, in 1.25 ms units. */ +#define BLE_GAP_EVENT_LENGTH_CODED_PHY_MIN (6) /**< The shortest event length in 1.25 ms units supporting LE Coded PHY. */ +#define BLE_GAP_EVENT_LENGTH_DEFAULT (3) /**< Default event length, in 1.25 ms units. */ +/**@} */ + + +/**@defgroup BLE_GAP_ROLE_COUNT GAP concurrent connection count defines. + * @{ */ +#define BLE_GAP_ROLE_COUNT_PERIPH_DEFAULT (1) /**< Default maximum number of connections concurrently acting as peripherals. */ +#define BLE_GAP_ROLE_COUNT_CENTRAL_DEFAULT (3) /**< Default maximum number of connections concurrently acting as centrals. */ +#define BLE_GAP_ROLE_COUNT_CENTRAL_SEC_DEFAULT (1) /**< Default number of SMP instances shared between all connections acting as centrals. */ +#define BLE_GAP_ROLE_COUNT_COMBINED_MAX (20) /**< Maximum supported number of concurrent connections in the peripheral and central roles combined. */ + +/**@} */ + +/**@brief Automatic data length parameter. */ +#define BLE_GAP_DATA_LENGTH_AUTO 0 + +/**@defgroup BLE_GAP_AUTH_PAYLOAD_TIMEOUT Authenticated payload timeout defines. + * @{ */ +#define BLE_GAP_AUTH_PAYLOAD_TIMEOUT_MAX (48000) /**< Maximum authenticated payload timeout in 10 ms units, i.e. 8 minutes. */ +#define BLE_GAP_AUTH_PAYLOAD_TIMEOUT_MIN (1) /**< Minimum authenticated payload timeout in 10 ms units, i.e. 10 ms. */ +/**@} */ + +/**@defgroup GAP_SEC_MODES GAP Security Modes + * @{ */ +#define BLE_GAP_SEC_MODE 0x00 /**< No key (may be used to reject). */ +/**@} */ + +/**@brief The total number of channels in Bluetooth Low Energy. */ +#define BLE_GAP_CHANNEL_COUNT (40) + +/**@defgroup BLE_GAP_QOS_CHANNEL_SURVEY_INTERVALS Quality of Service (QoS) Channel survey interval defines + * @{ */ +#define BLE_GAP_QOS_CHANNEL_SURVEY_INTERVAL_CONTINUOUS (0) /**< Continuous channel survey. */ +#define BLE_GAP_QOS_CHANNEL_SURVEY_INTERVAL_MIN_US (7500) /**< Minimum channel survey interval in microseconds (7.5 ms). */ +#define BLE_GAP_QOS_CHANNEL_SURVEY_INTERVAL_MAX_US (4000000) /**< Maximum channel survey interval in microseconds (4 s). */ + /**@} */ + +/** @} */ + + +/**@addtogroup BLE_GAP_STRUCTURES Structures + * @{ */ + +/**@brief Advertising event properties. */ +typedef struct +{ + uint8_t type; /**< Advertising type. See @ref BLE_GAP_ADV_TYPES. */ + uint8_t anonymous : 1; /**< Omit advertiser's address from all PDUs. + @note Anonymous advertising is only available for + @ref BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_NONSCANNABLE_UNDIRECTED and + @ref BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_NONSCANNABLE_DIRECTED. */ + uint8_t include_tx_power : 1; /**< This feature is not supported on this SoftDevice. */ +} ble_gap_adv_properties_t; + + +/**@brief Advertising report type. */ +typedef struct +{ + uint16_t connectable : 1; /**< Connectable advertising event type. */ + uint16_t scannable : 1; /**< Scannable advertising event type. */ + uint16_t directed : 1; /**< Directed advertising event type. */ + uint16_t scan_response : 1; /**< Received a scan response. */ + uint16_t extended_pdu : 1; /**< Received an extended advertising set. */ + uint16_t status : 2; /**< Data status. See @ref BLE_GAP_ADV_DATA_STATUS. */ + uint16_t reserved : 9; /**< Reserved for future use. */ +} ble_gap_adv_report_type_t; + +/**@brief Advertising Auxiliary Pointer. */ +typedef struct +{ + uint16_t aux_offset; /**< Time offset from the beginning of advertising packet to the auxiliary packet in 100 us units. */ + uint8_t aux_phy; /**< Indicates the PHY on which the auxiliary advertising packet is sent. See @ref BLE_GAP_PHYS. */ +} ble_gap_aux_pointer_t; + +/**@brief Bluetooth Low Energy address. */ +typedef struct +{ + uint8_t addr_id_peer : 1; /**< Only valid for peer addresses. + This bit is set by the SoftDevice to indicate whether the address has been resolved from + a Resolvable Private Address (when the peer is using privacy). + If set to 1, @ref addr and @ref addr_type refer to the identity address of the resolved address. + + This bit is ignored when a variable of type @ref ble_gap_addr_t is used as input to API functions. */ + uint8_t addr_type : 7; /**< See @ref BLE_GAP_ADDR_TYPES. */ + uint8_t addr[BLE_GAP_ADDR_LEN]; /**< 48-bit address, LSB format. + @ref addr is not used if @ref addr_type is @ref BLE_GAP_ADDR_TYPE_ANONYMOUS. */ +} ble_gap_addr_t; + + +/**@brief GAP connection parameters. + * + * @note When ble_conn_params_t is received in an event, both min_conn_interval and + * max_conn_interval will be equal to the connection interval set by the central. + * + * @note If both conn_sup_timeout and max_conn_interval are specified, then the following constraint applies: + * conn_sup_timeout * 4 > (1 + slave_latency) * max_conn_interval + * that corresponds to the following Bluetooth Spec requirement: + * The Supervision_Timeout in milliseconds shall be larger than + * (1 + Conn_Latency) * Conn_Interval_Max * 2, where Conn_Interval_Max is given in milliseconds. + */ +typedef struct +{ + uint16_t min_conn_interval; /**< Minimum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/ + uint16_t max_conn_interval; /**< Maximum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/ + uint16_t slave_latency; /**< Slave Latency in number of connection events, see @ref BLE_GAP_CP_LIMITS.*/ + uint16_t conn_sup_timeout; /**< Connection Supervision Timeout in 10 ms units, see @ref BLE_GAP_CP_LIMITS.*/ +} ble_gap_conn_params_t; + + +/**@brief GAP connection security modes. + * + * Security Mode 0 Level 0: No access permissions at all (this level is not defined by the Bluetooth Core specification).\n + * Security Mode 1 Level 1: No security is needed (aka open link).\n + * Security Mode 1 Level 2: Encrypted link required, MITM protection not necessary.\n + * Security Mode 1 Level 3: MITM protected encrypted link required.\n + * Security Mode 1 Level 4: LESC MITM protected encrypted link using a 128-bit strength encryption key required.\n + * Security Mode 2 Level 1: Signing or encryption required, MITM protection not necessary.\n + * Security Mode 2 Level 2: MITM protected signing required, unless link is MITM protected encrypted.\n + */ +typedef struct +{ + uint8_t sm : 4; /**< Security Mode (1 or 2), 0 for no permissions at all. */ + uint8_t lv : 4; /**< Level (1, 2, 3 or 4), 0 for no permissions at all. */ + +} ble_gap_conn_sec_mode_t; + + +/**@brief GAP connection security status.*/ +typedef struct +{ + ble_gap_conn_sec_mode_t sec_mode; /**< Currently active security mode for this connection.*/ + uint8_t encr_key_size; /**< Length of currently active encryption key, 7 to 16 octets (only applicable for bonding procedures). */ +} ble_gap_conn_sec_t; + +/**@brief Identity Resolving Key. */ +typedef struct +{ + uint8_t irk[BLE_GAP_SEC_KEY_LEN]; /**< Array containing IRK. */ +} ble_gap_irk_t; + + +/**@brief Channel mask (40 bits). + * Every channel is represented with a bit positioned as per channel index defined in Bluetooth Core Specification v5.0, + * Vol 6, Part B, Section 1.4.1. The LSB contained in array element 0 represents channel index 0, and bit 39 represents + * channel index 39. If a bit is set to 1, the channel is not used. + */ +typedef uint8_t ble_gap_ch_mask_t[5]; + + +/**@brief GAP advertising parameters. */ +typedef struct +{ + ble_gap_adv_properties_t properties; /**< The properties of the advertising events. */ + ble_gap_addr_t const *p_peer_addr; /**< Address of a known peer. + @note ble_gap_addr_t::addr_type cannot be + @ref BLE_GAP_ADDR_TYPE_ANONYMOUS. + - When privacy is enabled and the local device uses + @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE addresses, + the device identity list is searched for a matching entry. If + the local IRK for that device identity is set, the local IRK + for that device will be used to generate the advertiser address + field in the advertising packet. + - If @ref ble_gap_adv_properties_t::type is directed, this must be + set to the targeted scanner or initiator. If the peer address is + in the device identity list, the peer IRK for that device will be + used to generate @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE + target addresses used in the advertising event PDUs. */ + uint32_t interval; /**< Advertising interval in 625 us units. @sa BLE_GAP_ADV_INTERVALS. + @note If @ref ble_gap_adv_properties_t::type is set to + @ref BLE_GAP_ADV_TYPE_CONNECTABLE_NONSCANNABLE_DIRECTED_HIGH_DUTY_CYCLE + advertising, this parameter is ignored. */ + uint16_t duration; /**< Advertising duration in 10 ms units. When timeout is reached, + an event of type @ref BLE_GAP_EVT_ADV_SET_TERMINATED is raised. + @sa BLE_GAP_ADV_TIMEOUT_VALUES. + @note The SoftDevice will always complete at least one advertising + event even if the duration is set too low. */ + uint8_t max_adv_evts; /**< Maximum advertising events that shall be sent prior to disabling + advertising. Setting the value to 0 disables the limitation. When + the count of advertising events specified by this parameter + (if not 0) is reached, advertising will be automatically stopped + and an event of type @ref BLE_GAP_EVT_ADV_SET_TERMINATED is raised + @note If @ref ble_gap_adv_properties_t::type is set to + @ref BLE_GAP_ADV_TYPE_CONNECTABLE_NONSCANNABLE_DIRECTED_HIGH_DUTY_CYCLE, + this parameter is ignored. */ + ble_gap_ch_mask_t channel_mask; /**< Channel mask for primary and secondary advertising channels. + At least one of the primary channels, that is channel index 37-39, must be used. + Masking away secondary advertising channels is not supported. */ + uint8_t filter_policy; /**< Filter Policy. @sa BLE_GAP_ADV_FILTER_POLICIES. */ + uint8_t primary_phy; /**< Indicates the PHY on which the primary advertising channel packets + are transmitted. If set to @ref BLE_GAP_PHY_AUTO, @ref BLE_GAP_PHY_1MBPS + will be used. + Valid values are @ref BLE_GAP_PHY_1MBPS and @ref BLE_GAP_PHY_CODED. + @note The primary_phy shall indicate @ref BLE_GAP_PHY_1MBPS if + @ref ble_gap_adv_properties_t::type is not an extended advertising type. */ + uint8_t secondary_phy; /**< Indicates the PHY on which the secondary advertising channel packets + are transmitted. + If set to @ref BLE_GAP_PHY_AUTO, @ref BLE_GAP_PHY_1MBPS will be used. + Valid values are + @ref BLE_GAP_PHY_1MBPS, @ref BLE_GAP_PHY_2MBPS, and @ref BLE_GAP_PHY_CODED. + If @ref ble_gap_adv_properties_t::type is an extended advertising type + and connectable, this is the PHY that will be used to establish a + connection and send AUX_ADV_IND packets on. + @note This parameter will be ignored when + @ref ble_gap_adv_properties_t::type is not an extended advertising type. */ + uint8_t set_id:4; /**< The advertising set identifier distinguishes this advertising set from other + advertising sets transmitted by this and other devices. + @note This parameter will be ignored when + @ref ble_gap_adv_properties_t::type is not an extended advertising type. */ + uint8_t scan_req_notification:1; /**< Enable scan request notifications for this advertising set. When a + scan request is received and the scanner address is allowed + by the filter policy, @ref BLE_GAP_EVT_SCAN_REQ_REPORT is raised. + @note This parameter will be ignored when + @ref ble_gap_adv_properties_t::type is a non-scannable + advertising type. */ +} ble_gap_adv_params_t; + + +/**@brief GAP advertising data buffers. + * + * The application must provide the buffers for advertisement. The memory shall reside in application RAM, and + * shall never be modified while advertising. The data shall be kept alive until either: + * - @ref BLE_GAP_EVT_ADV_SET_TERMINATED is raised. + * - @ref BLE_GAP_EVT_CONNECTED is raised with @ref ble_gap_evt_connected_t::adv_handle set to the corresponding + * advertising handle. + * - Advertising is stopped. + * - Advertising data is changed. + * To update advertising data while advertising, provide new buffers to @ref sd_ble_gap_adv_set_configure. */ +typedef struct +{ + ble_data_t adv_data; /**< Advertising data. + @note + Advertising data can only be specified for a @ref ble_gap_adv_properties_t::type + that is allowed to contain advertising data. */ + ble_data_t scan_rsp_data; /**< Scan response data. + @note + Scan response data can only be specified for a @ref ble_gap_adv_properties_t::type + that is scannable. */ +} ble_gap_adv_data_t; + + +/**@brief GAP scanning parameters. */ +typedef struct +{ + uint8_t extended : 1; /**< If 1, the scanner will accept extended advertising packets. + If set to 0, the scanner will not receive advertising packets + on secondary advertising channels, and will not be able + to receive long advertising PDUs. */ + uint8_t report_incomplete_evts : 1; /**< If 1, events of type @ref ble_gap_evt_adv_report_t may have + @ref ble_gap_adv_report_type_t::status set to + @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA. + This parameter is ignored when used with @ref sd_ble_gap_connect + @note This may be used to abort receiving more packets from an extended + advertising event, and is only available for extended + scanning, see @ref sd_ble_gap_scan_start. + @note This feature is not supported by this SoftDevice. */ + uint8_t active : 1; /**< If 1, perform active scanning by sending scan requests. + This parameter is ignored when used with @ref sd_ble_gap_connect. */ + uint8_t filter_policy : 2; /**< Scanning filter policy. @sa BLE_GAP_SCAN_FILTER_POLICIES. + @note Only @ref BLE_GAP_SCAN_FP_ACCEPT_ALL and + @ref BLE_GAP_SCAN_FP_WHITELIST are valid when used with + @ref sd_ble_gap_connect */ + uint8_t scan_phys; /**< Bitfield of PHYs to scan on. If set to @ref BLE_GAP_PHY_AUTO, + scan_phys will default to @ref BLE_GAP_PHY_1MBPS. + - If @ref ble_gap_scan_params_t::extended is set to 0, the only + supported PHY is @ref BLE_GAP_PHY_1MBPS. + - When used with @ref sd_ble_gap_scan_start, + the bitfield indicates the PHYs the scanner will use for scanning + on primary advertising channels. The scanner will accept + @ref BLE_GAP_PHYS_SUPPORTED as secondary advertising channel PHYs. + - When used with @ref sd_ble_gap_connect, the bitfield indicates + the PHYs the initiator will use for scanning on primary advertising + channels. The initiator will accept connections initiated on either + of the @ref BLE_GAP_PHYS_SUPPORTED PHYs. + If scan_phys contains @ref BLE_GAP_PHY_1MBPS and/or @ref BLE_GAP_PHY_2MBPS, + the primary scan PHY is @ref BLE_GAP_PHY_1MBPS. + If scan_phys also contains @ref BLE_GAP_PHY_CODED, the primary scan + PHY will also contain @ref BLE_GAP_PHY_CODED. If the only scan PHY is + @ref BLE_GAP_PHY_CODED, the primary scan PHY is + @ref BLE_GAP_PHY_CODED only. */ + uint16_t interval; /**< Scan interval in 625 us units. @sa BLE_GAP_SCAN_INTERVALS. */ + uint16_t window; /**< Scan window in 625 us units. @sa BLE_GAP_SCAN_WINDOW. + If scan_phys contains both @ref BLE_GAP_PHY_1MBPS and + @ref BLE_GAP_PHY_CODED interval shall be larger than or + equal to twice the scan window. */ + uint16_t timeout; /**< Scan timeout in 10 ms units. @sa BLE_GAP_SCAN_TIMEOUT. */ + ble_gap_ch_mask_t channel_mask; /**< Channel mask for primary and secondary advertising channels. + At least one of the primary channels, that is channel index 37-39, must be + set to 0. + Masking away secondary channels is not supported. */ +} ble_gap_scan_params_t; + + +/**@brief Privacy. + * + * The privacy feature provides a way for the device to avoid being tracked over a period of time. + * The privacy feature, when enabled, hides the local device identity and replaces it with a private address + * that is automatically refreshed at a specified interval. + * + * If a device still wants to be recognized by other peers, it needs to share it's Identity Resolving Key (IRK). + * With this key, a device can generate a random private address that can only be recognized by peers in possession of that key, + * and devices can establish connections without revealing their real identities. + * + * Both network privacy (@ref BLE_GAP_PRIVACY_MODE_NETWORK_PRIVACY) and device privacy (@ref BLE_GAP_PRIVACY_MODE_DEVICE_PRIVACY) + * are supported. + * + * @note If the device IRK is updated, the new IRK becomes the one to be distributed in all + * bonding procedures performed after @ref sd_ble_gap_privacy_set returns. + * The IRK distributed during bonding procedure is the device IRK that is active when @ref sd_ble_gap_sec_params_reply is called. + */ +typedef struct +{ + uint8_t privacy_mode; /**< Privacy mode, see @ref BLE_GAP_PRIVACY_MODES. Default is @ref BLE_GAP_PRIVACY_MODE_OFF. */ + uint8_t private_addr_type; /**< The private address type must be either @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE or @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE. */ + uint16_t private_addr_cycle_s; /**< Private address cycle interval in seconds. Providing an address cycle value of 0 will use the default value defined by @ref BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S. */ + ble_gap_irk_t *p_device_irk; /**< When used as input, pointer to IRK structure that will be used as the default IRK. If NULL, the device default IRK will be used. + When used as output, pointer to IRK structure where the current default IRK will be written to. If NULL, this argument is ignored. + By default, the default IRK is used to generate random private resolvable addresses for the local device unless instructed otherwise. */ +} ble_gap_privacy_params_t; + + +/**@brief PHY preferences for TX and RX + * @note tx_phys and rx_phys are bit fields. Multiple bits can be set in them to indicate multiple preferred PHYs for each direction. + * @code + * p_gap_phys->tx_phys = BLE_GAP_PHY_1MBPS | BLE_GAP_PHY_2MBPS; + * p_gap_phys->rx_phys = BLE_GAP_PHY_1MBPS | BLE_GAP_PHY_2MBPS; + * @endcode + * + */ +typedef struct +{ + uint8_t tx_phys; /**< Preferred transmit PHYs, see @ref BLE_GAP_PHYS. */ + uint8_t rx_phys; /**< Preferred receive PHYs, see @ref BLE_GAP_PHYS. */ +} ble_gap_phys_t; + +/** @brief Keys that can be exchanged during a bonding procedure. */ +typedef struct +{ + uint8_t enc : 1; /**< Long Term Key and Master Identification. */ + uint8_t id : 1; /**< Identity Resolving Key and Identity Address Information. */ + uint8_t sign : 1; /**< Connection Signature Resolving Key. */ + uint8_t link : 1; /**< Derive the Link Key from the LTK. */ +} ble_gap_sec_kdist_t; + + +/**@brief GAP security parameters. */ +typedef struct +{ + uint8_t bond : 1; /**< Perform bonding. */ + uint8_t mitm : 1; /**< Enable Man In The Middle protection. */ + uint8_t lesc : 1; /**< Enable LE Secure Connection pairing. */ + uint8_t keypress : 1; /**< Enable generation of keypress notifications. */ + uint8_t io_caps : 3; /**< IO capabilities, see @ref BLE_GAP_IO_CAPS. */ + uint8_t oob : 1; /**< The OOB data flag. + - In LE legacy pairing, this flag is set if a device has out of band authentication data. + The OOB method is used if both of the devices have out of band authentication data. + - In LE Secure Connections pairing, this flag is set if a device has the peer device's out of band authentication data. + The OOB method is used if at least one device has the peer device's OOB data available. */ + uint8_t min_key_size; /**< Minimum encryption key size in octets between 7 and 16. If 0 then not applicable in this instance. */ + uint8_t max_key_size; /**< Maximum encryption key size in octets between min_key_size and 16. */ + ble_gap_sec_kdist_t kdist_own; /**< Key distribution bitmap: keys that the local device will distribute. */ + ble_gap_sec_kdist_t kdist_peer; /**< Key distribution bitmap: keys that the remote device will distribute. */ +} ble_gap_sec_params_t; + + +/**@brief GAP Encryption Information. */ +typedef struct +{ + uint8_t ltk[BLE_GAP_SEC_KEY_LEN]; /**< Long Term Key. */ + uint8_t lesc : 1; /**< Key generated using LE Secure Connections. */ + uint8_t auth : 1; /**< Authenticated Key. */ + uint8_t ltk_len : 6; /**< LTK length in octets. */ +} ble_gap_enc_info_t; + + +/**@brief GAP Master Identification. */ +typedef struct +{ + uint16_t ediv; /**< Encrypted Diversifier. */ + uint8_t rand[BLE_GAP_SEC_RAND_LEN]; /**< Random Number. */ +} ble_gap_master_id_t; + + +/**@brief GAP Signing Information. */ +typedef struct +{ + uint8_t csrk[BLE_GAP_SEC_KEY_LEN]; /**< Connection Signature Resolving Key. */ +} ble_gap_sign_info_t; + + +/**@brief GAP LE Secure Connections P-256 Public Key. */ +typedef struct +{ + uint8_t pk[BLE_GAP_LESC_P256_PK_LEN]; /**< LE Secure Connections Elliptic Curve Diffie-Hellman P-256 Public Key. Stored in the standard SMP protocol format: {X,Y} both in little-endian. */ +} ble_gap_lesc_p256_pk_t; + + +/**@brief GAP LE Secure Connections DHKey. */ +typedef struct +{ + uint8_t key[BLE_GAP_LESC_DHKEY_LEN]; /**< LE Secure Connections Elliptic Curve Diffie-Hellman Key. Stored in little-endian. */ +} ble_gap_lesc_dhkey_t; + + +/**@brief GAP LE Secure Connections OOB data. */ +typedef struct +{ + ble_gap_addr_t addr; /**< Bluetooth address of the device. */ + uint8_t r[BLE_GAP_SEC_KEY_LEN]; /**< Random Number. */ + uint8_t c[BLE_GAP_SEC_KEY_LEN]; /**< Confirm Value. */ +} ble_gap_lesc_oob_data_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_CONNECTED. */ +typedef struct +{ + ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. If the peer_addr resolved: @ref ble_gap_addr_t::addr_id_peer is set to 1 + and the address is the device's identity address. */ + uint8_t role; /**< BLE role for this connection, see @ref BLE_GAP_ROLES */ + ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */ + uint8_t adv_handle; /**< Advertising handle in which advertising has ended. + This variable is only set if role is set to @ref BLE_GAP_ROLE_PERIPH. */ + ble_gap_adv_data_t adv_data; /**< Advertising buffers corresponding to the terminated + advertising set. The advertising buffers provided in + @ref sd_ble_gap_adv_set_configure are now released. + This variable is only set if role is set to @ref BLE_GAP_ROLE_PERIPH. */ +} ble_gap_evt_connected_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_DISCONNECTED. */ +typedef struct +{ + uint8_t reason; /**< HCI error code, see @ref BLE_HCI_STATUS_CODES. */ +} ble_gap_evt_disconnected_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_CONN_PARAM_UPDATE. */ +typedef struct +{ + ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */ +} ble_gap_evt_conn_param_update_t; + +/**@brief Event structure for @ref BLE_GAP_EVT_PHY_UPDATE_REQUEST. */ +typedef struct +{ + ble_gap_phys_t peer_preferred_phys; /**< The PHYs the peer prefers to use. */ +} ble_gap_evt_phy_update_request_t; + +/**@brief Event Structure for @ref BLE_GAP_EVT_PHY_UPDATE. */ +typedef struct +{ + uint8_t status; /**< Status of the procedure, see @ref BLE_HCI_STATUS_CODES.*/ + uint8_t tx_phy; /**< TX PHY for this connection, see @ref BLE_GAP_PHYS. */ + uint8_t rx_phy; /**< RX PHY for this connection, see @ref BLE_GAP_PHYS. */ +} ble_gap_evt_phy_update_t; + +/**@brief Event structure for @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST. */ +typedef struct +{ + ble_gap_sec_params_t peer_params; /**< Initiator Security Parameters. */ +} ble_gap_evt_sec_params_request_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_SEC_INFO_REQUEST. */ +typedef struct +{ + ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. */ + ble_gap_master_id_t master_id; /**< Master Identification for LTK lookup. */ + uint8_t enc_info : 1; /**< If 1, Encryption Information required. */ + uint8_t id_info : 1; /**< If 1, Identity Information required. */ + uint8_t sign_info : 1; /**< If 1, Signing Information required. */ +} ble_gap_evt_sec_info_request_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_PASSKEY_DISPLAY. */ +typedef struct +{ + uint8_t passkey[BLE_GAP_PASSKEY_LEN]; /**< 6-digit passkey in ASCII ('0'-'9' digits only). */ + uint8_t match_request : 1; /**< If 1 requires the application to report the match using @ref sd_ble_gap_auth_key_reply + with either @ref BLE_GAP_AUTH_KEY_TYPE_NONE if there is no match or + @ref BLE_GAP_AUTH_KEY_TYPE_PASSKEY if there is a match. */ +} ble_gap_evt_passkey_display_t; + +/**@brief Event structure for @ref BLE_GAP_EVT_KEY_PRESSED. */ +typedef struct +{ + uint8_t kp_not; /**< Keypress notification type, see @ref BLE_GAP_KP_NOT_TYPES. */ +} ble_gap_evt_key_pressed_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_AUTH_KEY_REQUEST. */ +typedef struct +{ + uint8_t key_type; /**< See @ref BLE_GAP_AUTH_KEY_TYPES. */ +} ble_gap_evt_auth_key_request_t; + +/**@brief Event structure for @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST. */ +typedef struct +{ + ble_gap_lesc_p256_pk_t *p_pk_peer; /**< LE Secure Connections remote P-256 Public Key. This will point to the application-supplied memory + inside the keyset during the call to @ref sd_ble_gap_sec_params_reply. */ + uint8_t oobd_req :1; /**< LESC OOB data required. A call to @ref sd_ble_gap_lesc_oob_data_set is required to complete the procedure. */ +} ble_gap_evt_lesc_dhkey_request_t; + + +/**@brief Security levels supported. + * @note See Bluetooth Specification Version 4.2 Volume 3, Part C, Chapter 10, Section 10.2.1. +*/ +typedef struct +{ + uint8_t lv1 : 1; /**< If 1: Level 1 is supported. */ + uint8_t lv2 : 1; /**< If 1: Level 2 is supported. */ + uint8_t lv3 : 1; /**< If 1: Level 3 is supported. */ + uint8_t lv4 : 1; /**< If 1: Level 4 is supported. */ +} ble_gap_sec_levels_t; + + +/**@brief Encryption Key. */ +typedef struct +{ + ble_gap_enc_info_t enc_info; /**< Encryption Information. */ + ble_gap_master_id_t master_id; /**< Master Identification. */ +} ble_gap_enc_key_t; + + +/**@brief Identity Key. */ +typedef struct +{ + ble_gap_irk_t id_info; /**< Identity Resolving Key. */ + ble_gap_addr_t id_addr_info; /**< Identity Address. */ +} ble_gap_id_key_t; + + +/**@brief Security Keys. */ +typedef struct +{ + ble_gap_enc_key_t *p_enc_key; /**< Encryption Key, or NULL. */ + ble_gap_id_key_t *p_id_key; /**< Identity Key, or NULL. */ + ble_gap_sign_info_t *p_sign_key; /**< Signing Key, or NULL. */ + ble_gap_lesc_p256_pk_t *p_pk; /**< LE Secure Connections P-256 Public Key. When in debug mode the application must use the value defined + in the Core Bluetooth Specification v4.2 Vol.3, Part H, Section 2.3.5.6.1 */ +} ble_gap_sec_keys_t; + + +/**@brief Security key set for both local and peer keys. */ +typedef struct +{ + ble_gap_sec_keys_t keys_own; /**< Keys distributed by the local device. For LE Secure Connections the encryption key will be generated locally and will always be stored if bonding. */ + ble_gap_sec_keys_t keys_peer; /**< Keys distributed by the remote device. For LE Secure Connections, p_enc_key must always be NULL. */ +} ble_gap_sec_keyset_t; + + +/**@brief Data Length Update Procedure parameters. */ +typedef struct +{ + uint16_t max_tx_octets; /**< Maximum number of payload octets that a Controller supports for transmission of a single Link Layer Data Channel PDU. */ + uint16_t max_rx_octets; /**< Maximum number of payload octets that a Controller supports for reception of a single Link Layer Data Channel PDU. */ + uint16_t max_tx_time_us; /**< Maximum time, in microseconds, that a Controller supports for transmission of a single Link Layer Data Channel PDU. */ + uint16_t max_rx_time_us; /**< Maximum time, in microseconds, that a Controller supports for reception of a single Link Layer Data Channel PDU. */ +} ble_gap_data_length_params_t; + + +/**@brief Data Length Update Procedure local limitation. */ +typedef struct +{ + uint16_t tx_payload_limited_octets; /**< If > 0, the requested TX packet length is too long by this many octets. */ + uint16_t rx_payload_limited_octets; /**< If > 0, the requested RX packet length is too long by this many octets. */ + uint16_t tx_rx_time_limited_us; /**< If > 0, the requested combination of TX and RX packet lengths is too long by this many microseconds. */ +} ble_gap_data_length_limitation_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_AUTH_STATUS. */ +typedef struct +{ + uint8_t auth_status; /**< Authentication status, see @ref BLE_GAP_SEC_STATUS. */ + uint8_t error_src : 2; /**< On error, source that caused the failure, see @ref BLE_GAP_SEC_STATUS_SOURCES. */ + uint8_t bonded : 1; /**< Procedure resulted in a bond. */ + uint8_t lesc : 1; /**< Procedure resulted in a LE Secure Connection. */ + ble_gap_sec_levels_t sm1_levels; /**< Levels supported in Security Mode 1. */ + ble_gap_sec_levels_t sm2_levels; /**< Levels supported in Security Mode 2. */ + ble_gap_sec_kdist_t kdist_own; /**< Bitmap stating which keys were exchanged (distributed) by the local device. If bonding with LE Secure Connections, the enc bit will be always set. */ + ble_gap_sec_kdist_t kdist_peer; /**< Bitmap stating which keys were exchanged (distributed) by the remote device. If bonding with LE Secure Connections, the enc bit will never be set. */ +} ble_gap_evt_auth_status_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_CONN_SEC_UPDATE. */ +typedef struct +{ + ble_gap_conn_sec_t conn_sec; /**< Connection security level. */ +} ble_gap_evt_conn_sec_update_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_TIMEOUT. */ +typedef struct +{ + uint8_t src; /**< Source of timeout event, see @ref BLE_GAP_TIMEOUT_SOURCES. */ + union + { + ble_data_t adv_report_buffer; /**< If source is set to @ref BLE_GAP_TIMEOUT_SRC_SCAN, the released + scan buffer is contained in this field. */ + } params; /**< Event Parameters. */ +} ble_gap_evt_timeout_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_RSSI_CHANGED. */ +typedef struct +{ + int8_t rssi; /**< Received Signal Strength Indication in dBm. + @note ERRATA-153 requires the rssi sample to be compensated based on a temperature measurement. */ + uint8_t ch_index; /**< Data Channel Index on which the Signal Strength is measured (0-36). */ +} ble_gap_evt_rssi_changed_t; + +/**@brief Event structure for @ref BLE_GAP_EVT_ADV_SET_TERMINATED */ +typedef struct +{ + uint8_t reason; /**< Reason for why the advertising set terminated. See + @ref BLE_GAP_EVT_ADV_SET_TERMINATED_REASON. */ + uint8_t adv_handle; /**< Advertising handle in which advertising has ended. */ + uint8_t num_completed_adv_events; /**< If @ref ble_gap_adv_params_t::max_adv_evts was not set to 0, + this field indicates the number of completed advertising events. */ + ble_gap_adv_data_t adv_data; /**< Advertising buffers corresponding to the terminated + advertising set. The advertising buffers provided in + @ref sd_ble_gap_adv_set_configure are now released. */ +} ble_gap_evt_adv_set_terminated_t; + +/**@brief Event structure for @ref BLE_GAP_EVT_ADV_REPORT. + * + * @note If @ref ble_gap_adv_report_type_t::status is set to @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA, + * not all fields in the advertising report may be available. + * + * @note When ble_gap_adv_report_type_t::status is not set to @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA, + * scanning will be paused. To continue scanning, call @ref sd_ble_gap_scan_start. + */ +typedef struct +{ + ble_gap_adv_report_type_t type; /**< Advertising report type. See @ref ble_gap_adv_report_type_t. */ + ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. If the peer_addr is resolved: + @ref ble_gap_addr_t::addr_id_peer is set to 1 and the address is the + peer's identity address. */ + ble_gap_addr_t direct_addr; /**< Contains the target address of the advertising event if + @ref ble_gap_adv_report_type_t::directed is set to 1. If the + SoftDevice was able to resolve the address, + @ref ble_gap_addr_t::addr_id_peer is set to 1 and the direct_addr + contains the local identity address. If the target address of the + advertising event is @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE, + and the SoftDevice was unable to resolve it, the application may try + to resolve this address to find out if the advertising event was + directed to us. */ + uint8_t primary_phy; /**< Indicates the PHY on which the primary advertising packet was received. + See @ref BLE_GAP_PHYS. */ + uint8_t secondary_phy; /**< Indicates the PHY on which the secondary advertising packet was received. + See @ref BLE_GAP_PHYS. This field is set to @ref BLE_GAP_PHY_NOT_SET if no packets + were received on a secondary advertising channel. */ + int8_t tx_power; /**< TX Power reported by the advertiser in the last packet header received. + This field is set to @ref BLE_GAP_POWER_LEVEL_INVALID if the + last received packet did not contain the Tx Power field. + @note TX Power is only included in extended advertising packets. */ + int8_t rssi; /**< Received Signal Strength Indication in dBm of the last packet received. + @note ERRATA-153 requires the rssi sample to be compensated based on a temperature measurement. */ + uint8_t ch_index; /**< Channel Index on which the last advertising packet is received (0-39). */ + uint8_t set_id; /**< Set ID of the received advertising data. Set ID is not present + if set to @ref BLE_GAP_ADV_REPORT_SET_ID_NOT_AVAILABLE. */ + uint16_t data_id:12; /**< The advertising data ID of the received advertising data. Data ID + is not present if @ref ble_gap_evt_adv_report_t::set_id is set to + @ref BLE_GAP_ADV_REPORT_SET_ID_NOT_AVAILABLE. */ + ble_data_t data; /**< Received advertising or scan response data. If + @ref ble_gap_adv_report_type_t::status is not set to + @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA, the data buffer provided + in @ref sd_ble_gap_scan_start is now released. */ + ble_gap_aux_pointer_t aux_pointer; /**< The offset and PHY of the next advertising packet in this extended advertising + event. @note This field is only set if @ref ble_gap_adv_report_type_t::status + is set to @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA. */ +} ble_gap_evt_adv_report_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_SEC_REQUEST. */ +typedef struct +{ + uint8_t bond : 1; /**< Perform bonding. */ + uint8_t mitm : 1; /**< Man In The Middle protection requested. */ + uint8_t lesc : 1; /**< LE Secure Connections requested. */ + uint8_t keypress : 1; /**< Generation of keypress notifications requested. */ +} ble_gap_evt_sec_request_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST. */ +typedef struct +{ + ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */ +} ble_gap_evt_conn_param_update_request_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_SCAN_REQ_REPORT. */ +typedef struct +{ + uint8_t adv_handle; /**< Advertising handle for the advertising set which received the Scan Request */ + int8_t rssi; /**< Received Signal Strength Indication in dBm. + @note ERRATA-153 requires the rssi sample to be compensated based on a temperature measurement. */ + ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. If the peer_addr resolved: @ref ble_gap_addr_t::addr_id_peer is set to 1 + and the address is the device's identity address. */ +} ble_gap_evt_scan_req_report_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_DATA_LENGTH_UPDATE_REQUEST. */ +typedef struct +{ + ble_gap_data_length_params_t peer_params; /**< Peer data length parameters. */ +} ble_gap_evt_data_length_update_request_t; + +/**@brief Event structure for @ref BLE_GAP_EVT_DATA_LENGTH_UPDATE. */ +typedef struct +{ + ble_gap_data_length_params_t effective_params; /**< The effective data length parameters. */ +} ble_gap_evt_data_length_update_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_QOS_CHANNEL_SURVEY_REPORT. */ +typedef struct +{ + int8_t channel_energy[BLE_GAP_CHANNEL_COUNT]; /**< The measured energy on the Bluetooth Low Energy + channels, in dBm, indexed by Channel Index. + If no measurement is available for the given channel, channel_energy is set to + @ref BLE_GAP_POWER_LEVEL_INVALID. */ +} ble_gap_evt_qos_channel_survey_report_t; + +/**@brief GAP event structure. */ +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle on which event occurred. */ + union /**< union alternative identified by evt_id in enclosing struct. */ + { + ble_gap_evt_connected_t connected; /**< Connected Event Parameters. */ + ble_gap_evt_disconnected_t disconnected; /**< Disconnected Event Parameters. */ + ble_gap_evt_conn_param_update_t conn_param_update; /**< Connection Parameter Update Parameters. */ + ble_gap_evt_sec_params_request_t sec_params_request; /**< Security Parameters Request Event Parameters. */ + ble_gap_evt_sec_info_request_t sec_info_request; /**< Security Information Request Event Parameters. */ + ble_gap_evt_passkey_display_t passkey_display; /**< Passkey Display Event Parameters. */ + ble_gap_evt_key_pressed_t key_pressed; /**< Key Pressed Event Parameters. */ + ble_gap_evt_auth_key_request_t auth_key_request; /**< Authentication Key Request Event Parameters. */ + ble_gap_evt_lesc_dhkey_request_t lesc_dhkey_request; /**< LE Secure Connections DHKey calculation request. */ + ble_gap_evt_auth_status_t auth_status; /**< Authentication Status Event Parameters. */ + ble_gap_evt_conn_sec_update_t conn_sec_update; /**< Connection Security Update Event Parameters. */ + ble_gap_evt_timeout_t timeout; /**< Timeout Event Parameters. */ + ble_gap_evt_rssi_changed_t rssi_changed; /**< RSSI Event Parameters. */ + ble_gap_evt_adv_report_t adv_report; /**< Advertising Report Event Parameters. */ + ble_gap_evt_adv_set_terminated_t adv_set_terminated; /**< Advertising Set Terminated Event Parameters. */ + ble_gap_evt_sec_request_t sec_request; /**< Security Request Event Parameters. */ + ble_gap_evt_conn_param_update_request_t conn_param_update_request; /**< Connection Parameter Update Parameters. */ + ble_gap_evt_scan_req_report_t scan_req_report; /**< Scan Request Report Parameters. */ + ble_gap_evt_phy_update_request_t phy_update_request; /**< PHY Update Request Event Parameters. */ + ble_gap_evt_phy_update_t phy_update; /**< PHY Update Parameters. */ + ble_gap_evt_data_length_update_request_t data_length_update_request; /**< Data Length Update Request Event Parameters. */ + ble_gap_evt_data_length_update_t data_length_update; /**< Data Length Update Event Parameters. */ + ble_gap_evt_qos_channel_survey_report_t qos_channel_survey_report; /**< Quality of Service (QoS) Channel Survey Report Parameters. */ + } params; /**< Event Parameters. */ +} ble_gap_evt_t; + + +/** + * @brief BLE GAP connection configuration parameters, set with @ref sd_ble_cfg_set. + * + * @retval ::NRF_ERROR_CONN_COUNT The connection count for the connection configurations is zero. + * @retval ::NRF_ERROR_INVALID_PARAM One or more of the following is true: + * - The sum of conn_count for all connection configurations combined exceeds UINT8_MAX. + * - The event length is smaller than @ref BLE_GAP_EVENT_LENGTH_MIN. + */ +typedef struct +{ + uint8_t conn_count; /**< The number of concurrent connections the application can create with this configuration. + The default and minimum value is @ref BLE_GAP_CONN_COUNT_DEFAULT. */ + uint16_t event_length; /**< The time set aside for this connection on every connection interval in 1.25 ms units. + The default value is @ref BLE_GAP_EVENT_LENGTH_DEFAULT, the minimum value is @ref BLE_GAP_EVENT_LENGTH_MIN. + The event length and the connection interval are the primary parameters + for setting the throughput of a connection. + See the SoftDevice Specification for details on throughput. */ +} ble_gap_conn_cfg_t; + + +/** + * @brief Configuration of maximum concurrent connections in the different connected roles, set with + * @ref sd_ble_cfg_set. + * + * @retval ::NRF_ERROR_CONN_COUNT The sum of periph_role_count and central_role_count is too + * large. The maximum supported sum of concurrent connections is + * @ref BLE_GAP_ROLE_COUNT_COMBINED_MAX. + * @retval ::NRF_ERROR_INVALID_PARAM central_sec_count is larger than central_role_count. + * @retval ::NRF_ERROR_RESOURCES The adv_set_count is too large. The maximum + * supported advertising handles is + * @ref BLE_GAP_ADV_SET_COUNT_MAX. + */ +typedef struct +{ + uint8_t adv_set_count; /**< Maximum number of advertising sets. Default value is @ref BLE_GAP_ADV_SET_COUNT_DEFAULT. */ + uint8_t periph_role_count; /**< Maximum number of connections concurrently acting as a peripheral. Default value is @ref BLE_GAP_ROLE_COUNT_PERIPH_DEFAULT. */ + uint8_t central_role_count; /**< Maximum number of connections concurrently acting as a central. Default value is @ref BLE_GAP_ROLE_COUNT_CENTRAL_DEFAULT. */ + uint8_t central_sec_count; /**< Number of SMP instances shared between all connections acting as a central. Default value is @ref BLE_GAP_ROLE_COUNT_CENTRAL_SEC_DEFAULT. */ + uint8_t qos_channel_survey_role_available:1; /**< If set, the Quality of Service (QoS) channel survey module is available to the + application using @ref sd_ble_gap_qos_channel_survey_start. */ +} ble_gap_cfg_role_count_t; + + +/** + * @brief Device name and its properties, set with @ref sd_ble_cfg_set. + * + * @note If the device name is not configured, the default device name will be + * @ref BLE_GAP_DEVNAME_DEFAULT, the maximum device name length will be + * @ref BLE_GAP_DEVNAME_DEFAULT_LEN, vloc will be set to @ref BLE_GATTS_VLOC_STACK and the device name + * will have no write access. + * + * @note If @ref max_len is more than @ref BLE_GAP_DEVNAME_DEFAULT_LEN and vloc is set to @ref BLE_GATTS_VLOC_STACK, + * the attribute table size must be increased to have room for the longer device name (see + * @ref sd_ble_cfg_set and @ref ble_gatts_cfg_attr_tab_size_t). + * + * @note If vloc is @ref BLE_GATTS_VLOC_STACK : + * - p_value must point to non-volatile memory (flash) or be NULL. + * - If p_value is NULL, the device name will initially be empty. + * + * @note If vloc is @ref BLE_GATTS_VLOC_USER : + * - p_value cannot be NULL. + * - If the device name is writable, p_value must point to volatile memory (RAM). + * + * @retval ::NRF_ERROR_INVALID_PARAM One or more of the following is true: + * - Invalid device name location (vloc). + * - Invalid device name security mode. + * @retval ::NRF_ERROR_INVALID_LENGTH One or more of the following is true: + * - The device name length is invalid (must be between 0 and @ref BLE_GAP_DEVNAME_MAX_LEN). + * - The device name length is too long for the given Attribute Table. + * @retval ::NRF_ERROR_NOT_SUPPORTED Device name security mode is not supported. + */ +typedef struct +{ + ble_gap_conn_sec_mode_t write_perm; /**< Write permissions. */ + uint8_t vloc:2; /**< Value location, see @ref BLE_GATTS_VLOCS.*/ + uint8_t *p_value; /**< Pointer to where the value (device name) is stored or will be stored. */ + uint16_t current_len; /**< Current length in bytes of the memory pointed to by p_value.*/ + uint16_t max_len; /**< Maximum length in bytes of the memory pointed to by p_value.*/ +} ble_gap_cfg_device_name_t; + + +/**@brief Configuration structure for GAP configurations. */ +typedef union +{ + ble_gap_cfg_role_count_t role_count_cfg; /**< Role count configuration, cfg_id is @ref BLE_GAP_CFG_ROLE_COUNT. */ + ble_gap_cfg_device_name_t device_name_cfg; /**< Device name configuration, cfg_id is @ref BLE_GAP_CFG_DEVICE_NAME. */ +} ble_gap_cfg_t; + + +/**@brief Channel Map option. + * + * @details Used with @ref sd_ble_opt_get to get the current channel map + * or @ref sd_ble_opt_set to set a new channel map. When setting the + * channel map, it applies to all current and future connections. When getting the + * current channel map, it applies to a single connection and the connection handle + * must be supplied. + * + * @note Setting the channel map may take some time, depending on connection parameters. + * The time taken may be different for each connection and the get operation will + * return the previous channel map until the new one has taken effect. + * + * @note After setting the channel map, by spec it can not be set again until at least 1 s has passed. + * See Bluetooth Specification Version 4.1 Volume 2, Part E, Section 7.3.46. + * + * @retval ::NRF_SUCCESS Get or set successful. + * @retval ::NRF_ERROR_INVALID_PARAM One or more of the following is true: + * - Less then two bits in @ref ch_map are set. + * - Bits for primary advertising channels (37-39) are set. + * @retval ::NRF_ERROR_BUSY Channel map was set again before enough time had passed. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied for get. + * + */ +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle (only applicable for get) */ + uint8_t ch_map[5]; /**< Channel Map (37-bit). */ +} ble_gap_opt_ch_map_t; + + +/**@brief Local connection latency option. + * + * @details Local connection latency is a feature which enables the slave to improve + * current consumption by ignoring the slave latency set by the peer. The + * local connection latency can only be set to a multiple of the slave latency, + * and cannot be longer than half of the supervision timeout. + * + * @details Used with @ref sd_ble_opt_set to set the local connection latency. The + * @ref sd_ble_opt_get is not supported for this option, but the actual + * local connection latency (unless set to NULL) is set as a return parameter + * when setting the option. + * + * @note The latency set will be truncated down to the closest slave latency event + * multiple, or the nearest multiple before half of the supervision timeout. + * + * @note The local connection latency is disabled by default, and needs to be enabled for new + * connections and whenever the connection is updated. + * + * @retval ::NRF_SUCCESS Set successfully. + * @retval ::NRF_ERROR_NOT_SUPPORTED Get is not supported. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle parameter. + */ +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle */ + uint16_t requested_latency; /**< Requested local connection latency. */ + uint16_t * p_actual_latency; /**< Pointer to storage for the actual local connection latency (can be set to NULL to skip return value). */ +} ble_gap_opt_local_conn_latency_t; + +/**@brief Disable slave latency + * + * @details Used with @ref sd_ble_opt_set to temporarily disable slave latency of a peripheral connection + * (see @ref ble_gap_conn_params_t::slave_latency). And to re-enable it again. When disabled, the + * peripheral will ignore the slave_latency set by the central. + * + * @note Shall only be called on peripheral links. + * + * @retval ::NRF_SUCCESS Set successfully. + * @retval ::NRF_ERROR_NOT_SUPPORTED Get is not supported. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle parameter. + */ +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle */ + uint8_t disable : 1; /**< Set to 1 to disable slave latency. Set to 0 enable it again.*/ +} ble_gap_opt_slave_latency_disable_t; + +/**@brief Passkey Option. + * + * @details Structure containing the passkey to be used during pairing. This can be used with @ref + * sd_ble_opt_set to make the SoftDevice use a preprogrammed passkey for authentication + * instead of generating a random one. + * + * @note Repeated pairing attempts using the same preprogrammed passkey makes pairing vulnerable to MITM attacks. + * + * @note @ref sd_ble_opt_get is not supported for this option. + * + */ +typedef struct +{ + uint8_t const * p_passkey; /**< Pointer to 6-digit ASCII string (digit 0..9 only, no NULL termination) passkey to be used during pairing. If this is NULL, the SoftDevice will generate a random passkey if required.*/ +} ble_gap_opt_passkey_t; + + +/**@brief Compatibility mode 1 option. + * + * @details This can be used with @ref sd_ble_opt_set to enable and disable + * compatibility mode 1. Compatibility mode 1 is disabled by default. + * + * @note Compatibility mode 1 enables interoperability with devices that do not support a value of + * 0 for the WinOffset parameter in the Link Layer CONNECT_IND packet. This applies to a + * limited set of legacy peripheral devices from another vendor. Enabling this compatibility + * mode will only have an effect if the local device will act as a central device and + * initiate a connection to a peripheral device. In that case it may lead to the connection + * creation taking up to one connection interval longer to complete for all connections. + * + * @retval ::NRF_SUCCESS Set successfully. + * @retval ::NRF_ERROR_INVALID_STATE When connection creation is ongoing while mode 1 is set. + */ +typedef struct +{ + uint8_t enable : 1; /**< Enable compatibility mode 1.*/ +} ble_gap_opt_compat_mode_1_t; + + +/**@brief Authenticated payload timeout option. + * + * @details This can be used with @ref sd_ble_opt_set to change the Authenticated payload timeout to a value other + * than the default of @ref BLE_GAP_AUTH_PAYLOAD_TIMEOUT_MAX. + * + * @note The authenticated payload timeout event ::BLE_GAP_TIMEOUT_SRC_AUTH_PAYLOAD will be generated + * if auth_payload_timeout time has elapsed without receiving a packet with a valid MIC on an encrypted + * link. + * + * @note The LE ping procedure will be initiated before the timer expires to give the peer a chance + * to reset the timer. In addition the stack will try to prioritize running of LE ping over other + * activities to increase chances of finishing LE ping before timer expires. To avoid side-effects + * on other activities, it is recommended to use high timeout values. + * Recommended timeout > 2*(connInterval * (6 + connSlaveLatency)). + * + * @retval ::NRF_SUCCESS Set successfully. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. auth_payload_timeout was outside of allowed range. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle parameter. + */ +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle */ + uint16_t auth_payload_timeout; /**< Requested timeout in 10 ms unit, see @ref BLE_GAP_AUTH_PAYLOAD_TIMEOUT. */ +} ble_gap_opt_auth_payload_timeout_t; + +/**@brief Option structure for GAP options. */ +typedef union +{ + ble_gap_opt_ch_map_t ch_map; /**< Parameters for the Channel Map option. */ + ble_gap_opt_local_conn_latency_t local_conn_latency; /**< Parameters for the Local connection latency option */ + ble_gap_opt_passkey_t passkey; /**< Parameters for the Passkey option.*/ + ble_gap_opt_compat_mode_1_t compat_mode_1; /**< Parameters for the compatibility mode 1 option.*/ + ble_gap_opt_auth_payload_timeout_t auth_payload_timeout; /**< Parameters for the authenticated payload timeout option.*/ + ble_gap_opt_slave_latency_disable_t slave_latency_disable; /**< Parameters for the Disable slave latency option */ +} ble_gap_opt_t; +/**@} */ + + +/**@addtogroup BLE_GAP_FUNCTIONS Functions + * @{ */ + +/**@brief Set the local Bluetooth identity address. + * + * The local Bluetooth identity address is the address that identifies this device to other peers. + * The address type must be either @ref BLE_GAP_ADDR_TYPE_PUBLIC or @ref BLE_GAP_ADDR_TYPE_RANDOM_STATIC. + * + * @note The identity address cannot be changed while advertising, scanning or creating a connection. + * + * @note This address will be distributed to the peer during bonding. + * If the address changes, the address stored in the peer device will not be valid and the ability to + * reconnect using the old address will be lost. + * + * @note By default the SoftDevice will set an address of type @ref BLE_GAP_ADDR_TYPE_RANDOM_STATIC upon being + * enabled. The address is a random number populated during the IC manufacturing process and remains unchanged + * for the lifetime of each IC. + * + * @mscs + * @mmsc{@ref BLE_GAP_ADV_MSC} + * @endmscs + * + * @param[in] p_addr Pointer to address structure. + * + * @retval ::NRF_SUCCESS Address successfully set. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid address. + * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. + * @retval ::NRF_ERROR_INVALID_STATE The identity address cannot be changed while advertising, + * scanning or creating a connection. + */ +SVCALL(SD_BLE_GAP_ADDR_SET, uint32_t, sd_ble_gap_addr_set(ble_gap_addr_t const *p_addr)); + + +/**@brief Get local Bluetooth identity address. + * + * @note This will always return the identity address irrespective of the privacy settings, + * i.e. the address type will always be either @ref BLE_GAP_ADDR_TYPE_PUBLIC or @ref BLE_GAP_ADDR_TYPE_RANDOM_STATIC. + * + * @param[out] p_addr Pointer to address structure to be filled in. + * + * @retval ::NRF_SUCCESS Address successfully retrieved. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid or NULL pointer supplied. + */ +SVCALL(SD_BLE_GAP_ADDR_GET, uint32_t, sd_ble_gap_addr_get(ble_gap_addr_t *p_addr)); + + +/**@brief Get the Bluetooth device address used by the advertiser. + * + * @note This function will return the local Bluetooth address used in advertising PDUs. When + * using privacy, the SoftDevice will generate a new private address every + * @ref ble_gap_privacy_params_t::private_addr_cycle_s configured using + * @ref sd_ble_gap_privacy_set. Hence depending on when the application calls this API, the + * address returned may not be the latest address that is used in the advertising PDUs. + * + * @param[in] adv_handle The advertising handle to get the address from. + * @param[out] p_addr Pointer to address structure to be filled in. + * + * @retval ::NRF_SUCCESS Address successfully retrieved. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid or NULL pointer supplied. + * @retval ::BLE_ERROR_INVALID_ADV_HANDLE The provided advertising handle was not found. + * @retval ::NRF_ERROR_INVALID_STATE The advertising set is currently not advertising. + */ +SVCALL(SD_BLE_GAP_ADV_ADDR_GET, uint32_t, sd_ble_gap_adv_addr_get(uint8_t adv_handle, ble_gap_addr_t *p_addr)); + + +/**@brief Set the active whitelist in the SoftDevice. + * + * @note Only one whitelist can be used at a time and the whitelist is shared between the BLE roles. + * The whitelist cannot be set if a BLE role is using the whitelist. + * + * @note If an address is resolved using the information in the device identity list, then the whitelist + * filter policy applies to the peer identity address and not the resolvable address sent on air. + * + * @mscs + * @mmsc{@ref BLE_GAP_WL_SHARE_MSC} + * @mmsc{@ref BLE_GAP_PRIVACY_SCAN_PRIVATE_SCAN_MSC} + * @endmscs + * + * @param[in] pp_wl_addrs Pointer to a whitelist of peer addresses, if NULL the whitelist will be cleared. + * @param[in] len Length of the whitelist, maximum @ref BLE_GAP_WHITELIST_ADDR_MAX_COUNT. + * + * @retval ::NRF_SUCCESS The whitelist is successfully set/cleared. + * @retval ::NRF_ERROR_INVALID_ADDR The whitelist (or one of its entries) provided is invalid. + * @retval ::BLE_ERROR_GAP_WHITELIST_IN_USE The whitelist is in use by a BLE role and cannot be set or cleared. + * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid address type is supplied. + * @retval ::NRF_ERROR_DATA_SIZE The given whitelist size is invalid (zero or too large); this can only return when + * pp_wl_addrs is not NULL. + */ +SVCALL(SD_BLE_GAP_WHITELIST_SET, uint32_t, sd_ble_gap_whitelist_set(ble_gap_addr_t const * const * pp_wl_addrs, uint8_t len)); + + +/**@brief Set device identity list. + * + * @note Only one device identity list can be used at a time and the list is shared between the BLE roles. + * The device identity list cannot be set if a BLE role is using the list. + * + * @param[in] pp_id_keys Pointer to an array of peer identity addresses and peer IRKs, if NULL the device identity list will be cleared. + * @param[in] pp_local_irks Pointer to an array of local IRKs. Each entry in the array maps to the entry in pp_id_keys at the same index. + * To fill in the list with the currently set device IRK for all peers, set to NULL. + * @param[in] len Length of the device identity list, maximum @ref BLE_GAP_DEVICE_IDENTITIES_MAX_COUNT. + * + * @mscs + * @mmsc{@ref BLE_GAP_PRIVACY_ADV_MSC} + * @mmsc{@ref BLE_GAP_PRIVACY_SCAN_MSC} + * @mmsc{@ref BLE_GAP_PRIVACY_SCAN_PRIVATE_SCAN_MSC} + * @mmsc{@ref BLE_GAP_PRIVACY_ADV_DIR_PRIV_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_CONN_PRIV_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_CONN_PRIV_MSC} + * @endmscs + * + * @retval ::NRF_SUCCESS The device identity list successfully set/cleared. + * @retval ::NRF_ERROR_INVALID_ADDR The device identity list (or one of its entries) provided is invalid. + * This code may be returned if the local IRK list also has an invalid entry. + * @retval ::BLE_ERROR_GAP_DEVICE_IDENTITIES_IN_USE The device identity list is in use and cannot be set or cleared. + * @retval ::BLE_ERROR_GAP_DEVICE_IDENTITIES_DUPLICATE The device identity list contains multiple entries with the same identity address. + * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid address type is supplied. + * @retval ::NRF_ERROR_DATA_SIZE The given device identity list size invalid (zero or too large); this can + * only return when pp_id_keys is not NULL. + */ +SVCALL(SD_BLE_GAP_DEVICE_IDENTITIES_SET, uint32_t, sd_ble_gap_device_identities_set(ble_gap_id_key_t const * const * pp_id_keys, ble_gap_irk_t const * const * pp_local_irks, uint8_t len)); + + +/**@brief Set privacy settings. + * + * @note Privacy settings cannot be changed while advertising, scanning or creating a connection. + * + * @param[in] p_privacy_params Privacy settings. + * + * @mscs + * @mmsc{@ref BLE_GAP_PRIVACY_ADV_MSC} + * @mmsc{@ref BLE_GAP_PRIVACY_SCAN_MSC} + * @mmsc{@ref BLE_GAP_PRIVACY_ADV_DIR_PRIV_MSC} + * @endmscs + * + * @retval ::NRF_SUCCESS Set successfully. + * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. + * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid address type is supplied. + * @retval ::NRF_ERROR_INVALID_ADDR The pointer to privacy settings is NULL or invalid. + * Otherwise, the p_device_irk pointer in privacy parameter is an invalid pointer. + * @retval ::NRF_ERROR_INVALID_PARAM Out of range parameters are provided. + * @retval ::NRF_ERROR_INVALID_STATE Privacy settings cannot be changed while advertising, scanning + * or creating a connection. + */ +SVCALL(SD_BLE_GAP_PRIVACY_SET, uint32_t, sd_ble_gap_privacy_set(ble_gap_privacy_params_t const *p_privacy_params)); + + +/**@brief Get privacy settings. + * + * @note ::ble_gap_privacy_params_t::p_device_irk must be initialized to NULL or a valid address before this function is called. + * If it is initialized to a valid address, the address pointed to will contain the current device IRK on return. + * + * @param[in,out] p_privacy_params Privacy settings. + * + * @retval ::NRF_SUCCESS Privacy settings read. + * @retval ::NRF_ERROR_INVALID_ADDR The pointer given for returning the privacy settings may be NULL or invalid. + * Otherwise, the p_device_irk pointer in privacy parameter is an invalid pointer. + */ +SVCALL(SD_BLE_GAP_PRIVACY_GET, uint32_t, sd_ble_gap_privacy_get(ble_gap_privacy_params_t *p_privacy_params)); + + +/**@brief Configure an advertising set. Set, clear or update advertising and scan response data. + * + * @note The format of the advertising data will be checked by this call to ensure interoperability. + * Limitations imposed by this API call to the data provided include having a flags data type in the scan response data and + * duplicating the local name in the advertising data and scan response data. + * + * @note In order to update advertising data while advertising, new advertising buffers must be provided. + * + * @mscs + * @mmsc{@ref BLE_GAP_ADV_MSC} + * @mmsc{@ref BLE_GAP_WL_SHARE_MSC} + * @endmscs + * + * @param[in,out] p_adv_handle Provide a pointer to a handle containing @ref BLE_GAP_ADV_SET_HANDLE_NOT_SET to configure + * a new advertising set. On success, a new handle is then returned through the pointer. + * Provide a pointer to an existing advertising handle to configure an existing advertising set. + * @param[in] p_adv_data Advertising data. If set to NULL, no advertising data will be used. See @ref ble_gap_adv_data_t. + * @param[in] p_adv_params Advertising parameters. When this function is used to update advertising data while advertising, + * this parameter must be NULL. See @ref ble_gap_adv_params_t. + * + * @retval ::NRF_SUCCESS Advertising set successfully configured. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied: + * - Invalid advertising data configuration specified. See @ref ble_gap_adv_data_t. + * - Invalid configuration of p_adv_params. See @ref ble_gap_adv_params_t. + * - Use of whitelist requested but whitelist has not been set, + * see @ref sd_ble_gap_whitelist_set. + * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR ble_gap_adv_params_t::p_peer_addr is invalid. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either: + * - It is invalid to provide non-NULL advertising set parameters while advertising. + * - It is invalid to provide the same data buffers while advertising. To update + * advertising data, provide new advertising buffers. + * @retval ::BLE_ERROR_GAP_DISCOVERABLE_WITH_WHITELIST Discoverable mode and whitelist incompatible. + * @retval ::BLE_ERROR_INVALID_ADV_HANDLE The provided advertising handle was not found. Use @ref BLE_GAP_ADV_SET_HANDLE_NOT_SET to + * configure a new advertising handle. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_FLAGS Invalid combination of advertising flags supplied. + * @retval ::NRF_ERROR_INVALID_DATA Invalid data type(s) supplied. Check the advertising data format specification + * given in Bluetooth Specification Version 5.0, Volume 3, Part C, Chapter 11. + * @retval ::NRF_ERROR_INVALID_LENGTH Invalid data length(s) supplied. + * @retval ::NRF_ERROR_NOT_SUPPORTED Unsupported data length or advertising parameter configuration. + * @retval ::NRF_ERROR_NO_MEM Not enough memory to configure a new advertising handle. Update an + * existing advertising handle instead. + * @retval ::BLE_ERROR_GAP_UUID_LIST_MISMATCH Invalid UUID list supplied. + */ +SVCALL(SD_BLE_GAP_ADV_SET_CONFIGURE, uint32_t, sd_ble_gap_adv_set_configure(uint8_t *p_adv_handle, ble_gap_adv_data_t const *p_adv_data, ble_gap_adv_params_t const *p_adv_params)); + + +/**@brief Start advertising (GAP Discoverable, Connectable modes, Broadcast Procedure). + * + * @note Only one advertiser may be active at any time. + * + * @events + * @event{@ref BLE_GAP_EVT_CONNECTED, Generated after connection has been established through connectable advertising.} + * @event{@ref BLE_GAP_EVT_ADV_SET_TERMINATED, Advertising set has terminated.} + * @event{@ref BLE_GAP_EVT_SCAN_REQ_REPORT, A scan request was received.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_ADV_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_CONN_PRIV_MSC} + * @mmsc{@ref BLE_GAP_PRIVACY_ADV_DIR_PRIV_MSC} + * @mmsc{@ref BLE_GAP_WL_SHARE_MSC} + * @endmscs + * + * @param[in] adv_handle Advertising handle to advertise on, received from @ref sd_ble_gap_adv_set_configure. + * @param[in] conn_cfg_tag Tag identifying a configuration set by @ref sd_ble_cfg_set or + * @ref BLE_CONN_CFG_TAG_DEFAULT to use the default connection configuration. For non-connectable + * advertising, this is ignored. + * + * @retval ::NRF_SUCCESS The BLE stack has started advertising. + * @retval ::NRF_ERROR_INVALID_STATE adv_handle is not configured or already advertising. + * @retval ::NRF_ERROR_CONN_COUNT The limit of available connections has been reached; connectable advertiser cannot be started. + * @retval ::BLE_ERROR_INVALID_ADV_HANDLE Advertising handle not found. Configure a new adveriting handle with @ref sd_ble_gap_adv_set_configure. + * @retval ::NRF_ERROR_NOT_FOUND conn_cfg_tag not found. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied: + * - Invalid configuration of p_adv_params. See @ref ble_gap_adv_params_t. + * - Use of whitelist requested but whitelist has not been set, see @ref sd_ble_gap_whitelist_set. + * @retval ::NRF_ERROR_RESOURCES Either: + * - adv_handle is configured with connectable advertising, but the event_length parameter + * associated with conn_cfg_tag is too small to be able to establish a connection on + * the selected advertising phys. Use @ref sd_ble_cfg_set to increase the event length. + * - Not enough BLE role slots available. + Stop one or more currently active roles (Central, Peripheral, Broadcaster or Observer) and try again. + * - p_adv_params is configured with connectable advertising, but the event_length parameter + * associated with conn_cfg_tag is too small to be able to establish a connection on + * the selected advertising phys. Use @ref sd_ble_cfg_set to increase the event length. + */ +SVCALL(SD_BLE_GAP_ADV_START, uint32_t, sd_ble_gap_adv_start(uint8_t adv_handle, uint8_t conn_cfg_tag)); + + +/**@brief Stop advertising (GAP Discoverable, Connectable modes, Broadcast Procedure). + * + * @mscs + * @mmsc{@ref BLE_GAP_ADV_MSC} + * @mmsc{@ref BLE_GAP_WL_SHARE_MSC} + * @endmscs + * + * @param[in] adv_handle The advertising handle that should stop advertising. + * + * @retval ::NRF_SUCCESS The BLE stack has stopped advertising. + * @retval ::BLE_ERROR_INVALID_ADV_HANDLE Invalid advertising handle. + * @retval ::NRF_ERROR_INVALID_STATE The advertising handle is not advertising. + */ +SVCALL(SD_BLE_GAP_ADV_STOP, uint32_t, sd_ble_gap_adv_stop(uint8_t adv_handle)); + + + +/**@brief Update connection parameters. + * + * @details In the central role this will initiate a Link Layer connection parameter update procedure, + * otherwise in the peripheral role, this will send the corresponding L2CAP request and wait for + * the central to perform the procedure. In both cases, and regardless of success or failure, the application + * will be informed of the result with a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE event. + * + * @details This function can be used as a central both to reply to a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST or to start the procedure unrequested. + * + * @events + * @event{@ref BLE_GAP_EVT_CONN_PARAM_UPDATE, Result of the connection parameter update procedure.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_CPU_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_ENC_AUTH_MUTEX_MSC} + * @mmsc{@ref BLE_GAP_MULTILINK_CPU_MSC} + * @mmsc{@ref BLE_GAP_MULTILINK_CTRL_PROC_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_CPU_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] p_conn_params Pointer to desired connection parameters. If NULL is provided on a peripheral role, + * the parameters in the PPCP characteristic of the GAP service will be used instead. + * If NULL is provided on a central role and in response to a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST, the peripheral request will be rejected + * + * @retval ::NRF_SUCCESS The Connection Update procedure has been started successfully. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints. + * @retval ::NRF_ERROR_INVALID_STATE Disconnection in progress or link has not been established. + * @retval ::NRF_ERROR_BUSY Procedure already in progress, wait for pending procedures to complete and retry. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. + */ +SVCALL(SD_BLE_GAP_CONN_PARAM_UPDATE, uint32_t, sd_ble_gap_conn_param_update(uint16_t conn_handle, ble_gap_conn_params_t const *p_conn_params)); + + +/**@brief Disconnect (GAP Link Termination). + * + * @details This call initiates the disconnection procedure, and its completion will be communicated to the application + * with a @ref BLE_GAP_EVT_DISCONNECTED event. + * + * @events + * @event{@ref BLE_GAP_EVT_DISCONNECTED, Generated when disconnection procedure is complete.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_CONN_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] hci_status_code HCI status code, see @ref BLE_HCI_STATUS_CODES (accepted values are @ref BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION and @ref BLE_HCI_CONN_INTERVAL_UNACCEPTABLE). + * + * @retval ::NRF_SUCCESS The disconnection procedure has been started successfully. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + * @retval ::NRF_ERROR_INVALID_STATE Disconnection in progress or link has not been established. + */ +SVCALL(SD_BLE_GAP_DISCONNECT, uint32_t, sd_ble_gap_disconnect(uint16_t conn_handle, uint8_t hci_status_code)); + + +/**@brief Set the radio's transmit power. + * + * @param[in] role The role to set the transmit power for, see @ref BLE_GAP_TX_POWER_ROLES for + * possible roles. + * @param[in] handle The handle parameter is interpreted depending on role: + * - If role is @ref BLE_GAP_TX_POWER_ROLE_CONN, this value is the specific connection handle. + * - If role is @ref BLE_GAP_TX_POWER_ROLE_ADV, the advertising set identified with the advertising handle, + * will use the specified transmit power, and include it in the advertising packet headers if + * @ref ble_gap_adv_properties_t::include_tx_power set. + * - For all other roles handle is ignored. + * @param[in] tx_power Radio transmit power in dBm (see note for accepted values). + * + * @note Supported tx_power values: -40dBm, -20dBm, -16dBm, -12dBm, -8dBm, -4dBm, 0dBm, +2dBm, +3dBm, +4dBm, +5dBm, +6dBm, +7dBm and +8dBm. + * @note The initiator will have the same transmit power as the scanner. + * @note When a connection is created it will inherit the transmit power from the initiator or + * advertiser leading to the connection. + * + * @retval ::NRF_SUCCESS Successfully changed the transmit power. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::BLE_ERROR_INVALID_ADV_HANDLE Advertising handle not found. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + */ +SVCALL(SD_BLE_GAP_TX_POWER_SET, uint32_t, sd_ble_gap_tx_power_set(uint8_t role, uint16_t handle, int8_t tx_power)); + + +/**@brief Set GAP Appearance value. + * + * @param[in] appearance Appearance (16-bit), see @ref BLE_APPEARANCES. + * + * @retval ::NRF_SUCCESS Appearance value set successfully. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + */ +SVCALL(SD_BLE_GAP_APPEARANCE_SET, uint32_t, sd_ble_gap_appearance_set(uint16_t appearance)); + + +/**@brief Get GAP Appearance value. + * + * @param[out] p_appearance Pointer to appearance (16-bit) to be filled in, see @ref BLE_APPEARANCES. + * + * @retval ::NRF_SUCCESS Appearance value retrieved successfully. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + */ +SVCALL(SD_BLE_GAP_APPEARANCE_GET, uint32_t, sd_ble_gap_appearance_get(uint16_t *p_appearance)); + + +/**@brief Set GAP Peripheral Preferred Connection Parameters. + * + * @param[in] p_conn_params Pointer to a @ref ble_gap_conn_params_t structure with the desired parameters. + * + * @retval ::NRF_SUCCESS Peripheral Preferred Connection Parameters set successfully. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + */ +SVCALL(SD_BLE_GAP_PPCP_SET, uint32_t, sd_ble_gap_ppcp_set(ble_gap_conn_params_t const *p_conn_params)); + + +/**@brief Get GAP Peripheral Preferred Connection Parameters. + * + * @param[out] p_conn_params Pointer to a @ref ble_gap_conn_params_t structure where the parameters will be stored. + * + * @retval ::NRF_SUCCESS Peripheral Preferred Connection Parameters retrieved successfully. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + */ +SVCALL(SD_BLE_GAP_PPCP_GET, uint32_t, sd_ble_gap_ppcp_get(ble_gap_conn_params_t *p_conn_params)); + + +/**@brief Set GAP device name. + * + * @note If the device name is located in application flash memory (see @ref ble_gap_cfg_device_name_t), + * it cannot be changed. Then @ref NRF_ERROR_FORBIDDEN will be returned. + * + * @param[in] p_write_perm Write permissions for the Device Name characteristic, see @ref ble_gap_conn_sec_mode_t. + * @param[in] p_dev_name Pointer to a UTF-8 encoded, <b>non NULL-terminated</b> string. + * @param[in] len Length of the UTF-8, <b>non NULL-terminated</b> string pointed to by p_dev_name in octets (must be smaller or equal than @ref BLE_GAP_DEVNAME_MAX_LEN). + * + * @retval ::NRF_SUCCESS GAP device name and permissions set successfully. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied. + * @retval ::NRF_ERROR_FORBIDDEN Device name is not writable. + */ +SVCALL(SD_BLE_GAP_DEVICE_NAME_SET, uint32_t, sd_ble_gap_device_name_set(ble_gap_conn_sec_mode_t const *p_write_perm, uint8_t const *p_dev_name, uint16_t len)); + + +/**@brief Get GAP device name. + * + * @note If the device name is longer than the size of the supplied buffer, + * p_len will return the complete device name length, + * and not the number of bytes actually returned in p_dev_name. + * The application may use this information to allocate a suitable buffer size. + * + * @param[out] p_dev_name Pointer to an empty buffer where the UTF-8 <b>non NULL-terminated</b> string will be placed. Set to NULL to obtain the complete device name length. + * @param[in,out] p_len Length of the buffer pointed by p_dev_name, complete device name length on output. + * + * @retval ::NRF_SUCCESS GAP device name retrieved successfully. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied. + */ +SVCALL(SD_BLE_GAP_DEVICE_NAME_GET, uint32_t, sd_ble_gap_device_name_get(uint8_t *p_dev_name, uint16_t *p_len)); + + +/**@brief Initiate the GAP Authentication procedure. + * + * @details In the central role, this function will send an SMP Pairing Request (or an SMP Pairing Failed if rejected), + * otherwise in the peripheral role, an SMP Security Request will be sent. + * + * @events + * @event{Depending on the security parameters set and the packet exchanges with the peer\, the following events may be generated:} + * @event{@ref BLE_GAP_EVT_SEC_PARAMS_REQUEST} + * @event{@ref BLE_GAP_EVT_SEC_INFO_REQUEST} + * @event{@ref BLE_GAP_EVT_PASSKEY_DISPLAY} + * @event{@ref BLE_GAP_EVT_KEY_PRESSED} + * @event{@ref BLE_GAP_EVT_AUTH_KEY_REQUEST} + * @event{@ref BLE_GAP_EVT_LESC_DHKEY_REQUEST} + * @event{@ref BLE_GAP_EVT_CONN_SEC_UPDATE} + * @event{@ref BLE_GAP_EVT_AUTH_STATUS} + * @event{@ref BLE_GAP_EVT_TIMEOUT} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_PERIPH_SEC_REQ_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_SEC_REQ_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_ENC_AUTH_MUTEX_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_PAIRING_JW_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_JW_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_OOB_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_PAIRING_JW_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_PD_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] p_sec_params Pointer to the @ref ble_gap_sec_params_t structure with the security parameters to be used during the pairing or bonding procedure. + * In the peripheral role, only the bond, mitm, lesc and keypress fields of this structure are used. + * In the central role, this pointer may be NULL to reject a Security Request. + * + * @retval ::NRF_SUCCESS Successfully initiated authentication procedure. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either: + * - No link has been established. + * - An encryption is already executing or queued. + * @retval ::NRF_ERROR_NO_MEM The maximum number of authentication procedures that can run in parallel for the given role is reached. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + * @retval ::NRF_ERROR_NOT_SUPPORTED Setting of sign or link fields in @ref ble_gap_sec_kdist_t not supported. + * @retval ::NRF_ERROR_TIMEOUT A SMP timeout has occurred, and further SMP operations on this link is prohibited. + */ +SVCALL(SD_BLE_GAP_AUTHENTICATE, uint32_t, sd_ble_gap_authenticate(uint16_t conn_handle, ble_gap_sec_params_t const *p_sec_params)); + + +/**@brief Reply with GAP security parameters. + * + * @details This function is only used to reply to a @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST, calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE. + * @note If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters. + * + * @events + * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_JW_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_BONDING_JW_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_BONDING_PK_PERIPH_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_BONDING_PK_CENTRAL_OOB_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_BONDING_STATIC_PK_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_CONFIRM_FAIL_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_PAIRING_JW_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_NC_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_PD_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_KS_TOO_SMALL_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_APP_ERROR_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_REMOTE_PAIRING_FAIL_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_TIMEOUT_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_PAIRING_JW_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_JW_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_OOB_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_PAIRING_JW_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_PD_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] sec_status Security status, see @ref BLE_GAP_SEC_STATUS. + * @param[in] p_sec_params Pointer to a @ref ble_gap_sec_params_t security parameters structure. In the central role this must be set to NULL, as the parameters have + * already been provided during a previous call to @ref sd_ble_gap_authenticate. + * @param[in,out] p_sec_keyset Pointer to a @ref ble_gap_sec_keyset_t security keyset structure. Any keys generated and/or distributed as a result of the ongoing security procedure + * will be stored into the memory referenced by the pointers inside this structure. The keys will be stored and available to the application + * upon reception of a @ref BLE_GAP_EVT_AUTH_STATUS event. + * Note that the SoftDevice expects the application to provide memory for storing the + * peer's keys. So it must be ensured that the relevant pointers inside this structure are not NULL. The pointers to the local key + * can, however, be NULL, in which case, the local key data will not be available to the application upon reception of the + * @ref BLE_GAP_EVT_AUTH_STATUS event. + * + * @retval ::NRF_SUCCESS Successfully accepted security parameter from the application. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_INVALID_STATE Security parameters has not been requested. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + * @retval ::NRF_ERROR_NOT_SUPPORTED Setting of sign or link fields in @ref ble_gap_sec_kdist_t not supported. + */ +SVCALL(SD_BLE_GAP_SEC_PARAMS_REPLY, uint32_t, sd_ble_gap_sec_params_reply(uint16_t conn_handle, uint8_t sec_status, ble_gap_sec_params_t const *p_sec_params, ble_gap_sec_keyset_t const *p_sec_keyset)); + + +/**@brief Reply with an authentication key. + * + * @details This function is only used to reply to a @ref BLE_GAP_EVT_AUTH_KEY_REQUEST or a @ref BLE_GAP_EVT_PASSKEY_DISPLAY, calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE. + * @note If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters. + * + * @events + * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_PERIPH_BONDING_PK_CENTRAL_OOB_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_NC_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_OOB_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] key_type See @ref BLE_GAP_AUTH_KEY_TYPES. + * @param[in] p_key If key type is @ref BLE_GAP_AUTH_KEY_TYPE_NONE, then NULL. + * If key type is @ref BLE_GAP_AUTH_KEY_TYPE_PASSKEY, then a 6-byte ASCII string (digit 0..9 only, no NULL termination) + * or NULL when confirming LE Secure Connections Numeric Comparison. + * If key type is @ref BLE_GAP_AUTH_KEY_TYPE_OOB, then a 16-byte OOB key value in little-endian format. + * + * @retval ::NRF_SUCCESS Authentication key successfully set. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_INVALID_STATE Authentication key has not been requested. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + */ +SVCALL(SD_BLE_GAP_AUTH_KEY_REPLY, uint32_t, sd_ble_gap_auth_key_reply(uint16_t conn_handle, uint8_t key_type, uint8_t const *p_key)); + + +/**@brief Reply with an LE Secure connections DHKey. + * + * @details This function is only used to reply to a @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST, calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE. + * @note If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters. + * + * @events + * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_PERIPH_LESC_PAIRING_JW_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_NC_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_PD_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_PAIRING_JW_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_PD_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] p_dhkey LE Secure Connections DHKey. + * + * @retval ::NRF_SUCCESS DHKey successfully set. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either: + * - The peer is not authenticated. + * - The application has not pulled a @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST event. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + */ +SVCALL(SD_BLE_GAP_LESC_DHKEY_REPLY, uint32_t, sd_ble_gap_lesc_dhkey_reply(uint16_t conn_handle, ble_gap_lesc_dhkey_t const *p_dhkey)); + + +/**@brief Notify the peer of a local keypress. + * + * @mscs + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] kp_not See @ref BLE_GAP_KP_NOT_TYPES. + * + * @retval ::NRF_SUCCESS Keypress notification successfully queued for transmission. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either: + * - Authentication key not requested. + * - Passkey has not been entered. + * - Keypresses have not been enabled by both peers. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + * @retval ::NRF_ERROR_BUSY The BLE stack is busy. Retry at later time. + */ +SVCALL(SD_BLE_GAP_KEYPRESS_NOTIFY, uint32_t, sd_ble_gap_keypress_notify(uint16_t conn_handle, uint8_t kp_not)); + + +/**@brief Generate a set of OOB data to send to a peer out of band. + * + * @note The @ref ble_gap_addr_t included in the OOB data returned will be the currently active one (or, if a connection has already been established, + * the one used during connection setup). The application may manually overwrite it with an updated value. + * + * @mscs + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. Can be @ref BLE_CONN_HANDLE_INVALID if a BLE connection has not been established yet. + * @param[in] p_pk_own LE Secure Connections local P-256 Public Key. + * @param[out] p_oobd_own The OOB data to be sent out of band to a peer. + * + * @retval ::NRF_SUCCESS OOB data successfully generated. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + */ +SVCALL(SD_BLE_GAP_LESC_OOB_DATA_GET, uint32_t, sd_ble_gap_lesc_oob_data_get(uint16_t conn_handle, ble_gap_lesc_p256_pk_t const *p_pk_own, ble_gap_lesc_oob_data_t *p_oobd_own)); + +/**@brief Provide the OOB data sent/received out of band. + * + * @note An authentication procedure with OOB selected as an algorithm must be in progress when calling this function. + * @note A @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST event with the oobd_req set to 1 must have been received prior to calling this function. + * + * @events + * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] p_oobd_own The OOB data sent out of band to a peer or NULL if the peer has not received OOB data. + * Must correspond to @ref ble_gap_sec_params_t::oob flag in @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST. + * @param[in] p_oobd_peer The OOB data received out of band from a peer or NULL if none received. + * Must correspond to @ref ble_gap_sec_params_t::oob flag + * in @ref sd_ble_gap_authenticate in the central role or + * in @ref sd_ble_gap_sec_params_reply in the peripheral role. + * + * @retval ::NRF_SUCCESS OOB data accepted. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either: + * - Authentication key not requested + * - Not expecting LESC OOB data + * - Have not actually exchanged passkeys. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + */ +SVCALL(SD_BLE_GAP_LESC_OOB_DATA_SET, uint32_t, sd_ble_gap_lesc_oob_data_set(uint16_t conn_handle, ble_gap_lesc_oob_data_t const *p_oobd_own, ble_gap_lesc_oob_data_t const *p_oobd_peer)); + + +/**@brief Initiate GAP Encryption procedure. + * + * @details In the central role, this function will initiate the encryption procedure using the encryption information provided. + * + * @events + * @event{@ref BLE_GAP_EVT_CONN_SEC_UPDATE, The connection security has been updated.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_CENTRAL_ENC_AUTH_MUTEX_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_ENC_MSC} + * @mmsc{@ref BLE_GAP_MULTILINK_CTRL_PROC_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_SEC_REQ_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] p_master_id Pointer to a @ref ble_gap_master_id_t master identification structure. + * @param[in] p_enc_info Pointer to a @ref ble_gap_enc_info_t encryption information structure. + * + * @retval ::NRF_SUCCESS Successfully initiated authentication procedure. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_STATE No link has been established. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + * @retval ::BLE_ERROR_INVALID_ROLE Operation is not supported in the Peripheral role. + * @retval ::NRF_ERROR_BUSY Procedure already in progress or not allowed at this time, wait for pending procedures to complete and retry. + */ +SVCALL(SD_BLE_GAP_ENCRYPT, uint32_t, sd_ble_gap_encrypt(uint16_t conn_handle, ble_gap_master_id_t const *p_master_id, ble_gap_enc_info_t const *p_enc_info)); + + +/**@brief Reply with GAP security information. + * + * @details This function is only used to reply to a @ref BLE_GAP_EVT_SEC_INFO_REQUEST, calling it at other times will result in @ref NRF_ERROR_INVALID_STATE. + * @note If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters. + * @note Data signing is not yet supported, and p_sign_info must therefore be NULL. + * + * @mscs + * @mmsc{@ref BLE_GAP_PERIPH_ENC_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] p_enc_info Pointer to a @ref ble_gap_enc_info_t encryption information structure. May be NULL to signal none is available. + * @param[in] p_id_info Pointer to a @ref ble_gap_irk_t identity information structure. May be NULL to signal none is available. + * @param[in] p_sign_info Pointer to a @ref ble_gap_sign_info_t signing information structure. May be NULL to signal none is available. + * + * @retval ::NRF_SUCCESS Successfully accepted security information. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either: + * - No link has been established. + * - No @ref BLE_GAP_EVT_SEC_REQUEST pending. + * - LE long term key requested command not allowed. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + */ +SVCALL(SD_BLE_GAP_SEC_INFO_REPLY, uint32_t, sd_ble_gap_sec_info_reply(uint16_t conn_handle, ble_gap_enc_info_t const *p_enc_info, ble_gap_irk_t const *p_id_info, ble_gap_sign_info_t const *p_sign_info)); + + +/**@brief Get the current connection security. + * + * @param[in] conn_handle Connection handle. + * @param[out] p_conn_sec Pointer to a @ref ble_gap_conn_sec_t structure to be filled in. + * + * @retval ::NRF_SUCCESS Current connection security successfully retrieved. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + */ +SVCALL(SD_BLE_GAP_CONN_SEC_GET, uint32_t, sd_ble_gap_conn_sec_get(uint16_t conn_handle, ble_gap_conn_sec_t *p_conn_sec)); + + +/**@brief Start reporting the received signal strength to the application. + * + * A new event is reported whenever the RSSI value changes, until @ref sd_ble_gap_rssi_stop is called. + * + * @events + * @event{@ref BLE_GAP_EVT_RSSI_CHANGED, New RSSI data available. How often the event is generated is + * dependent on the settings of the <code>threshold_dbm</code> + * and <code>skip_count</code> input parameters.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_CENTRAL_RSSI_READ_MSC} + * @mmsc{@ref BLE_GAP_RSSI_FILT_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] threshold_dbm Minimum change in dBm before triggering the @ref BLE_GAP_EVT_RSSI_CHANGED event. Events are disabled if threshold_dbm equals @ref BLE_GAP_RSSI_THRESHOLD_INVALID. + * @param[in] skip_count Number of RSSI samples with a change of threshold_dbm or more before sending a new @ref BLE_GAP_EVT_RSSI_CHANGED event. + * + * @retval ::NRF_SUCCESS Successfully activated RSSI reporting. + * @retval ::NRF_ERROR_INVALID_STATE RSSI reporting is already ongoing. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + */ +SVCALL(SD_BLE_GAP_RSSI_START, uint32_t, sd_ble_gap_rssi_start(uint16_t conn_handle, uint8_t threshold_dbm, uint8_t skip_count)); + + +/**@brief Stop reporting the received signal strength. + * + * @note An RSSI change detected before the call but not yet received by the application + * may be reported after @ref sd_ble_gap_rssi_stop has been called. + * + * @mscs + * @mmsc{@ref BLE_GAP_CENTRAL_RSSI_READ_MSC} + * @mmsc{@ref BLE_GAP_RSSI_FILT_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * + * @retval ::NRF_SUCCESS Successfully deactivated RSSI reporting. + * @retval ::NRF_ERROR_INVALID_STATE RSSI reporting is not ongoing. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + */ +SVCALL(SD_BLE_GAP_RSSI_STOP, uint32_t, sd_ble_gap_rssi_stop(uint16_t conn_handle)); + + +/**@brief Get the received signal strength for the last connection event. + * + * @ref sd_ble_gap_rssi_start must be called to start reporting RSSI before using this function. @ref NRF_ERROR_NOT_FOUND + * will be returned until RSSI was sampled for the first time after calling @ref sd_ble_gap_rssi_start. + * @note ERRATA-153 requires the rssi sample to be compensated based on a temperature measurement. + * @mscs + * @mmsc{@ref BLE_GAP_CENTRAL_RSSI_READ_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[out] p_rssi Pointer to the location where the RSSI measurement shall be stored. + * @param[out] p_ch_index Pointer to the location where Channel Index for the RSSI measurement shall be stored. + * + * @retval ::NRF_SUCCESS Successfully read the RSSI. + * @retval ::NRF_ERROR_NOT_FOUND No sample is available. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + * @retval ::NRF_ERROR_INVALID_STATE RSSI reporting is not ongoing. + */ +SVCALL(SD_BLE_GAP_RSSI_GET, uint32_t, sd_ble_gap_rssi_get(uint16_t conn_handle, int8_t *p_rssi, uint8_t *p_ch_index)); + + +/**@brief Start or continue scanning (GAP Discovery procedure, Observer Procedure). + * + * @note A call to this function will require the application to keep the memory pointed by + * p_adv_report_buffer alive until the buffer is released. The buffer is released when the scanner is stopped + * or when this function is called with another buffer. + * + * @note The scanner will automatically stop in the following cases: + * - @ref sd_ble_gap_scan_stop is called. + * - @ref sd_ble_gap_connect is called. + * - A @ref BLE_GAP_EVT_TIMEOUT with source set to @ref BLE_GAP_TIMEOUT_SRC_SCAN is received. + * - When a @ref BLE_GAP_EVT_ADV_REPORT event is received and @ref ble_gap_adv_report_type_t::status is not set to + * @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA. In this case scanning is only paused to let the application + * access received data. The application must call this function to continue scanning, or call @ref sd_ble_gap_scan_stop + * to stop scanning. + * + * @note If a @ref BLE_GAP_EVT_ADV_REPORT event is received with @ref ble_gap_adv_report_type_t::status set to + * @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA, the scanner will continue scanning, and the application will + * receive more reports from this advertising event. The following reports will include the old and new received data. + * + * @events + * @event{@ref BLE_GAP_EVT_ADV_REPORT, An advertising or scan response packet has been received.} + * @event{@ref BLE_GAP_EVT_TIMEOUT, Scanner has timed out.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_SCAN_MSC} + * @mmsc{@ref BLE_GAP_WL_SHARE_MSC} + * @endmscs + * + * @param[in] p_scan_params Pointer to scan parameters structure. When this function is used to continue + * scanning, this parameter must be NULL. + * @param[in] p_adv_report_buffer Pointer to buffer used to store incoming advertising data. + * The memory pointed to should be kept alive until the scanning is stopped. + * See @ref BLE_GAP_SCAN_BUFFER_SIZE for minimum and maximum buffer size. + * If the scanner receives advertising data larger than can be stored in the buffer, + * a @ref BLE_GAP_EVT_ADV_REPORT will be raised with @ref ble_gap_adv_report_type_t::status + * set to @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_TRUNCATED. + * + * @retval ::NRF_SUCCESS Successfully initiated scanning procedure. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either: + * - Scanning is already ongoing and p_scan_params was not NULL + * - Scanning is not running and p_scan_params was NULL. + * - The scanner has timed out when this function is called to continue scanning. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. See @ref ble_gap_scan_params_t. + * @retval ::NRF_ERROR_NOT_SUPPORTED Unsupported parameters supplied. See @ref ble_gap_scan_params_t. + * @retval ::NRF_ERROR_INVALID_LENGTH The provided buffer length is invalid. See @ref BLE_GAP_SCAN_BUFFER_MIN. + * @retval ::NRF_ERROR_RESOURCES Not enough BLE role slots available. + * Stop one or more currently active roles (Central, Peripheral or Broadcaster) and try again + */ +SVCALL(SD_BLE_GAP_SCAN_START, uint32_t, sd_ble_gap_scan_start(ble_gap_scan_params_t const *p_scan_params, ble_data_t const * p_adv_report_buffer)); + + +/**@brief Stop scanning (GAP Discovery procedure, Observer Procedure). + * + * @note The buffer provided in @ref sd_ble_gap_scan_start is released. + * + * @mscs + * @mmsc{@ref BLE_GAP_SCAN_MSC} + * @mmsc{@ref BLE_GAP_WL_SHARE_MSC} + * @endmscs + * + * @retval ::NRF_SUCCESS Successfully stopped scanning procedure. + * @retval ::NRF_ERROR_INVALID_STATE Not in the scanning state. + */ +SVCALL(SD_BLE_GAP_SCAN_STOP, uint32_t, sd_ble_gap_scan_stop(void)); + + +/**@brief Create a connection (GAP Link Establishment). + * + * @note If a scanning procedure is currently in progress it will be automatically stopped when calling this function. + * The scanning procedure will be stopped even if the function returns an error. + * + * @events + * @event{@ref BLE_GAP_EVT_CONNECTED, A connection was established.} + * @event{@ref BLE_GAP_EVT_TIMEOUT, Failed to establish a connection.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_WL_SHARE_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_CONN_PRIV_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_CONN_MSC} + * @endmscs + * + * @param[in] p_peer_addr Pointer to peer identity address. If @ref ble_gap_scan_params_t::filter_policy is set to use + * whitelist, then p_peer_addr is ignored. + * @param[in] p_scan_params Pointer to scan parameters structure. + * @param[in] p_conn_params Pointer to desired connection parameters. + * @param[in] conn_cfg_tag Tag identifying a configuration set by @ref sd_ble_cfg_set or + * @ref BLE_CONN_CFG_TAG_DEFAULT to use the default connection configuration. + * + * @retval ::NRF_SUCCESS Successfully initiated connection procedure. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid parameter(s) pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * - Invalid parameter(s) in p_scan_params or p_conn_params. + * - Use of whitelist requested but whitelist has not been set, see @ref sd_ble_gap_whitelist_set. + * - Peer address was not present in the device identity list, see @ref sd_ble_gap_device_identities_set. + * @retval ::NRF_ERROR_NOT_FOUND conn_cfg_tag not found. + * @retval ::NRF_ERROR_INVALID_STATE The SoftDevice is in an invalid state to perform this operation. This may be due to an + * existing locally initiated connect procedure, which must complete before initiating again. + * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid Peer address. + * @retval ::NRF_ERROR_CONN_COUNT The limit of available connections has been reached. + * @retval ::NRF_ERROR_RESOURCES Either: + * - Not enough BLE role slots available. + * Stop one or more currently active roles (Central, Peripheral or Observer) and try again. + * - The event_length parameter associated with conn_cfg_tag is too small to be able to + * establish a connection on the selected @ref ble_gap_scan_params_t::scan_phys. + * Use @ref sd_ble_cfg_set to increase the event length. + */ +SVCALL(SD_BLE_GAP_CONNECT, uint32_t, sd_ble_gap_connect(ble_gap_addr_t const *p_peer_addr, ble_gap_scan_params_t const *p_scan_params, ble_gap_conn_params_t const *p_conn_params, uint8_t conn_cfg_tag)); + + +/**@brief Cancel a connection establishment. + * + * @mscs + * @mmsc{@ref BLE_GAP_CENTRAL_CONN_MSC} + * @endmscs + * + * @retval ::NRF_SUCCESS Successfully canceled an ongoing connection procedure. + * @retval ::NRF_ERROR_INVALID_STATE No locally initiated connect procedure started or connection + * completed occurred. + */ +SVCALL(SD_BLE_GAP_CONNECT_CANCEL, uint32_t, sd_ble_gap_connect_cancel(void)); + + +/**@brief Initiate or respond to a PHY Update Procedure + * + * @details This function is used to initiate or respond to a PHY Update Procedure. It will always + * generate a @ref BLE_GAP_EVT_PHY_UPDATE event if successfully executed. + * If this function is used to initiate a PHY Update procedure and the only option + * provided in @ref ble_gap_phys_t::tx_phys and @ref ble_gap_phys_t::rx_phys is the + * currently active PHYs in the respective directions, the SoftDevice will generate a + * @ref BLE_GAP_EVT_PHY_UPDATE with the current PHYs set and will not initiate the + * procedure in the Link Layer. + * + * If @ref ble_gap_phys_t::tx_phys or @ref ble_gap_phys_t::rx_phys is @ref BLE_GAP_PHY_AUTO, + * then the stack will select PHYs based on the peer's PHY preferences and the local link + * configuration. The PHY Update procedure will for this case result in a PHY combination + * that respects the time constraints configured with @ref sd_ble_cfg_set and the current + * link layer data length. + * + * When acting as a central, the SoftDevice will select the fastest common PHY in each direction. + * + * If the peer does not support the PHY Update Procedure, then the resulting + * @ref BLE_GAP_EVT_PHY_UPDATE event will have a status set to + * @ref BLE_HCI_UNSUPPORTED_REMOTE_FEATURE. + * + * If the PHY procedure was rejected by the peer due to a procedure collision, the status + * will be @ref BLE_HCI_STATUS_CODE_LMP_ERROR_TRANSACTION_COLLISION or + * @ref BLE_HCI_DIFFERENT_TRANSACTION_COLLISION. + * If the peer responds to the PHY Update procedure with invalid parameters, the status + * will be @ref BLE_HCI_STATUS_CODE_INVALID_LMP_PARAMETERS. + * If the PHY procedure was rejected by the peer for a different reason, the status will + * contain the reason as specified by the peer. + * + * @events + * @event{@ref BLE_GAP_EVT_PHY_UPDATE, Result of the PHY Update Procedure.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_CENTRAL_PHY_UPDATE} + * @mmsc{@ref BLE_GAP_PERIPHERAL_PHY_UPDATE} + * @endmscs + * + * @param[in] conn_handle Connection handle to indicate the connection for which the PHY Update is requested. + * @param[in] p_gap_phys Pointer to PHY structure. + * + * @retval ::NRF_SUCCESS Successfully requested a PHY Update. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_INVALID_STATE No link has been established. + * @retval ::NRF_ERROR_RESOURCES The connection event length configured for this link is not sufficient for the combination of + * @ref ble_gap_phys_t::tx_phys, @ref ble_gap_phys_t::rx_phys, and @ref ble_gap_data_length_params_t. + * The connection event length is configured with @ref BLE_CONN_CFG_GAP using @ref sd_ble_cfg_set. + * @retval ::NRF_ERROR_BUSY Procedure is already in progress or not allowed at this time. Process pending events and wait for the pending procedure to complete and retry. + * + */ +SVCALL(SD_BLE_GAP_PHY_UPDATE, uint32_t, sd_ble_gap_phy_update(uint16_t conn_handle, ble_gap_phys_t const *p_gap_phys)); + + +/**@brief Initiate or respond to a Data Length Update Procedure. + * + * @note If the application uses @ref BLE_GAP_DATA_LENGTH_AUTO for one or more members of + * p_dl_params, the SoftDevice will choose the highest value supported in current + * configuration and connection parameters. + * @note If the link PHY is Coded, the SoftDevice will ensure that the MaxTxTime and/or MaxRxTime + * used in the Data Length Update procedure is at least 2704 us. Otherwise, MaxTxTime and + * MaxRxTime will be limited to maximum 2120 us. + * + * @param[in] conn_handle Connection handle. + * @param[in] p_dl_params Pointer to local parameters to be used in Data Length Update + * Procedure. Set any member to @ref BLE_GAP_DATA_LENGTH_AUTO to let + * the SoftDevice automatically decide the value for that member. + * Set to NULL to use automatic values for all members. + * @param[out] p_dl_limitation Pointer to limitation to be written when local device does not + * have enough resources or does not support the requested Data Length + * Update parameters. Ignored if NULL. + * + * @mscs + * @mmsc{@ref BLE_GAP_DATA_LENGTH_UPDATE_PROCEDURE_MSC} + * @endmscs + * + * @retval ::NRF_SUCCESS Successfully set Data Length Extension initiation/response parameters. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle parameter supplied. + * @retval ::NRF_ERROR_INVALID_STATE No link has been established. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameters supplied. + * @retval ::NRF_ERROR_NOT_SUPPORTED The requested parameters are not supported by the SoftDevice. Inspect + * p_dl_limitation to see which parameter is not supported. + * @retval ::NRF_ERROR_RESOURCES The connection event length configured for this link is not sufficient for the requested parameters. + * Use @ref sd_ble_cfg_set with @ref BLE_CONN_CFG_GAP to increase the connection event length. + * Inspect p_dl_limitation to see where the limitation is. + * @retval ::NRF_ERROR_BUSY Peer has already initiated a Data Length Update Procedure. Process the + * pending @ref BLE_GAP_EVT_DATA_LENGTH_UPDATE_REQUEST event to respond. + */ +SVCALL(SD_BLE_GAP_DATA_LENGTH_UPDATE, uint32_t, sd_ble_gap_data_length_update(uint16_t conn_handle, ble_gap_data_length_params_t const *p_dl_params, ble_gap_data_length_limitation_t *p_dl_limitation)); + +/**@brief Start the Quality of Service (QoS) channel survey module. + * + * @details The channel survey module provides measurements of the energy levels on + * the Bluetooth Low Energy channels. When the module is enabled, @ref BLE_GAP_EVT_QOS_CHANNEL_SURVEY_REPORT + * events will periodically report the measured energy levels for each channel. + * + * @note The measurements are scheduled with lower priority than other Bluetooth Low Energy roles, + * Radio Timeslot API events and Flash API events. + * + * @note The channel survey module will attempt to do measurements so that the average interval + * between measurements will be interval_us. However due to the channel survey module + * having the lowest priority of all roles and modules, this may not be possible. In that + * case fewer than expected channel survey reports may be given. + * + * @note In order to use the channel survey module, @ref ble_gap_cfg_role_count_t::qos_channel_survey_role_available + * must be set. This is done using @ref sd_ble_cfg_set. + * + * @param[in] interval_us Requested average interval for the measurements and reports. See + * @ref BLE_GAP_QOS_CHANNEL_SURVEY_INTERVALS for valid ranges. If set + * to @ref BLE_GAP_QOS_CHANNEL_SURVEY_INTERVAL_CONTINUOUS, the channel + * survey role will be scheduled at every available opportunity. + * + * @retval ::NRF_SUCCESS The module is successfully started. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter supplied. interval_us is out of the + * allowed range. + * @retval ::NRF_ERROR_INVALID_STATE Trying to start the module when already running. + * @retval ::NRF_ERROR_RESOURCES The channel survey module is not available to the application. + * Set @ref ble_gap_cfg_role_count_t::qos_channel_survey_role_available using + * @ref sd_ble_cfg_set. + */ +SVCALL(SD_BLE_GAP_QOS_CHANNEL_SURVEY_START, uint32_t, sd_ble_gap_qos_channel_survey_start(uint32_t interval_us)); + +/**@brief Stop the Quality of Service (QoS) channel survey module. + * + * @retval ::NRF_SUCCESS The module is successfully stopped. + * @retval ::NRF_ERROR_INVALID_STATE Trying to stop the module when it is not running. + */ +SVCALL(SD_BLE_GAP_QOS_CHANNEL_SURVEY_STOP, uint32_t, sd_ble_gap_qos_channel_survey_stop(void)); + + +/** @} */ + +#ifdef __cplusplus +} +#endif +#endif // BLE_GAP_H__ + +/** + @} +*/ diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gatt.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gatt.h new file mode 100755 index 00000000..9cb577cc --- /dev/null +++ b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gatt.h @@ -0,0 +1,229 @@ +/* + * Copyright (c) 2013 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_GATT Generic Attribute Profile (GATT) Common + @{ + @brief Common definitions and prototypes for the GATT interfaces. + */ + +#ifndef BLE_GATT_H__ +#define BLE_GATT_H__ + +#include <stdint.h> +#include "nrf_svc.h" +#include "nrf_error.h" +#include "ble_hci.h" +#include "ble_ranges.h" +#include "ble_types.h" +#include "ble_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup BLE_GATT_DEFINES Defines + * @{ */ + +/** @brief Default ATT MTU, in bytes. */ +#define BLE_GATT_ATT_MTU_DEFAULT 23 + +/**@brief Invalid Attribute Handle. */ +#define BLE_GATT_HANDLE_INVALID 0x0000 + +/**@brief First Attribute Handle. */ +#define BLE_GATT_HANDLE_START 0x0001 + +/**@brief Last Attribute Handle. */ +#define BLE_GATT_HANDLE_END 0xFFFF + +/** @defgroup BLE_GATT_TIMEOUT_SOURCES GATT Timeout sources + * @{ */ +#define BLE_GATT_TIMEOUT_SRC_PROTOCOL 0x00 /**< ATT Protocol timeout. */ +/** @} */ + +/** @defgroup BLE_GATT_WRITE_OPS GATT Write operations + * @{ */ +#define BLE_GATT_OP_INVALID 0x00 /**< Invalid Operation. */ +#define BLE_GATT_OP_WRITE_REQ 0x01 /**< Write Request. */ +#define BLE_GATT_OP_WRITE_CMD 0x02 /**< Write Command. */ +#define BLE_GATT_OP_SIGN_WRITE_CMD 0x03 /**< Signed Write Command. */ +#define BLE_GATT_OP_PREP_WRITE_REQ 0x04 /**< Prepare Write Request. */ +#define BLE_GATT_OP_EXEC_WRITE_REQ 0x05 /**< Execute Write Request. */ +/** @} */ + +/** @defgroup BLE_GATT_EXEC_WRITE_FLAGS GATT Execute Write flags + * @{ */ +#define BLE_GATT_EXEC_WRITE_FLAG_PREPARED_CANCEL 0x00 /**< Cancel prepared write. */ +#define BLE_GATT_EXEC_WRITE_FLAG_PREPARED_WRITE 0x01 /**< Execute prepared write. */ +/** @} */ + +/** @defgroup BLE_GATT_HVX_TYPES GATT Handle Value operations + * @{ */ +#define BLE_GATT_HVX_INVALID 0x00 /**< Invalid Operation. */ +#define BLE_GATT_HVX_NOTIFICATION 0x01 /**< Handle Value Notification. */ +#define BLE_GATT_HVX_INDICATION 0x02 /**< Handle Value Indication. */ +/** @} */ + +/** @defgroup BLE_GATT_STATUS_CODES GATT Status Codes + * @{ */ +#define BLE_GATT_STATUS_SUCCESS 0x0000 /**< Success. */ +#define BLE_GATT_STATUS_UNKNOWN 0x0001 /**< Unknown or not applicable status. */ +#define BLE_GATT_STATUS_ATTERR_INVALID 0x0100 /**< ATT Error: Invalid Error Code. */ +#define BLE_GATT_STATUS_ATTERR_INVALID_HANDLE 0x0101 /**< ATT Error: Invalid Attribute Handle. */ +#define BLE_GATT_STATUS_ATTERR_READ_NOT_PERMITTED 0x0102 /**< ATT Error: Read not permitted. */ +#define BLE_GATT_STATUS_ATTERR_WRITE_NOT_PERMITTED 0x0103 /**< ATT Error: Write not permitted. */ +#define BLE_GATT_STATUS_ATTERR_INVALID_PDU 0x0104 /**< ATT Error: Used in ATT as Invalid PDU. */ +#define BLE_GATT_STATUS_ATTERR_INSUF_AUTHENTICATION 0x0105 /**< ATT Error: Authenticated link required. */ +#define BLE_GATT_STATUS_ATTERR_REQUEST_NOT_SUPPORTED 0x0106 /**< ATT Error: Used in ATT as Request Not Supported. */ +#define BLE_GATT_STATUS_ATTERR_INVALID_OFFSET 0x0107 /**< ATT Error: Offset specified was past the end of the attribute. */ +#define BLE_GATT_STATUS_ATTERR_INSUF_AUTHORIZATION 0x0108 /**< ATT Error: Used in ATT as Insufficient Authorization. */ +#define BLE_GATT_STATUS_ATTERR_PREPARE_QUEUE_FULL 0x0109 /**< ATT Error: Used in ATT as Prepare Queue Full. */ +#define BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_FOUND 0x010A /**< ATT Error: Used in ATT as Attribute not found. */ +#define BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_LONG 0x010B /**< ATT Error: Attribute cannot be read or written using read/write blob requests. */ +#define BLE_GATT_STATUS_ATTERR_INSUF_ENC_KEY_SIZE 0x010C /**< ATT Error: Encryption key size used is insufficient. */ +#define BLE_GATT_STATUS_ATTERR_INVALID_ATT_VAL_LENGTH 0x010D /**< ATT Error: Invalid value size. */ +#define BLE_GATT_STATUS_ATTERR_UNLIKELY_ERROR 0x010E /**< ATT Error: Very unlikely error. */ +#define BLE_GATT_STATUS_ATTERR_INSUF_ENCRYPTION 0x010F /**< ATT Error: Encrypted link required. */ +#define BLE_GATT_STATUS_ATTERR_UNSUPPORTED_GROUP_TYPE 0x0110 /**< ATT Error: Attribute type is not a supported grouping attribute. */ +#define BLE_GATT_STATUS_ATTERR_INSUF_RESOURCES 0x0111 /**< ATT Error: Encrypted link required. */ +#define BLE_GATT_STATUS_ATTERR_RFU_RANGE1_BEGIN 0x0112 /**< ATT Error: Reserved for Future Use range #1 begin. */ +#define BLE_GATT_STATUS_ATTERR_RFU_RANGE1_END 0x017F /**< ATT Error: Reserved for Future Use range #1 end. */ +#define BLE_GATT_STATUS_ATTERR_APP_BEGIN 0x0180 /**< ATT Error: Application range begin. */ +#define BLE_GATT_STATUS_ATTERR_APP_END 0x019F /**< ATT Error: Application range end. */ +#define BLE_GATT_STATUS_ATTERR_RFU_RANGE2_BEGIN 0x01A0 /**< ATT Error: Reserved for Future Use range #2 begin. */ +#define BLE_GATT_STATUS_ATTERR_RFU_RANGE2_END 0x01DF /**< ATT Error: Reserved for Future Use range #2 end. */ +#define BLE_GATT_STATUS_ATTERR_RFU_RANGE3_BEGIN 0x01E0 /**< ATT Error: Reserved for Future Use range #3 begin. */ +#define BLE_GATT_STATUS_ATTERR_RFU_RANGE3_END 0x01FC /**< ATT Error: Reserved for Future Use range #3 end. */ +#define BLE_GATT_STATUS_ATTERR_CPS_WRITE_REQ_REJECTED 0x01FC /**< ATT Common Profile and Service Error: Write request rejected. */ +#define BLE_GATT_STATUS_ATTERR_CPS_CCCD_CONFIG_ERROR 0x01FD /**< ATT Common Profile and Service Error: Client Characteristic Configuration Descriptor improperly configured. */ +#define BLE_GATT_STATUS_ATTERR_CPS_PROC_ALR_IN_PROG 0x01FE /**< ATT Common Profile and Service Error: Procedure Already in Progress. */ +#define BLE_GATT_STATUS_ATTERR_CPS_OUT_OF_RANGE 0x01FF /**< ATT Common Profile and Service Error: Out Of Range. */ +/** @} */ + + +/** @defgroup BLE_GATT_CPF_FORMATS Characteristic Presentation Formats + * @note Found at http://developer.bluetooth.org/gatt/descriptors/Pages/DescriptorViewer.aspx?u=org.bluetooth.descriptor.gatt.characteristic_presentation_format.xml + * @{ */ +#define BLE_GATT_CPF_FORMAT_RFU 0x00 /**< Reserved For Future Use. */ +#define BLE_GATT_CPF_FORMAT_BOOLEAN 0x01 /**< Boolean. */ +#define BLE_GATT_CPF_FORMAT_2BIT 0x02 /**< Unsigned 2-bit integer. */ +#define BLE_GATT_CPF_FORMAT_NIBBLE 0x03 /**< Unsigned 4-bit integer. */ +#define BLE_GATT_CPF_FORMAT_UINT8 0x04 /**< Unsigned 8-bit integer. */ +#define BLE_GATT_CPF_FORMAT_UINT12 0x05 /**< Unsigned 12-bit integer. */ +#define BLE_GATT_CPF_FORMAT_UINT16 0x06 /**< Unsigned 16-bit integer. */ +#define BLE_GATT_CPF_FORMAT_UINT24 0x07 /**< Unsigned 24-bit integer. */ +#define BLE_GATT_CPF_FORMAT_UINT32 0x08 /**< Unsigned 32-bit integer. */ +#define BLE_GATT_CPF_FORMAT_UINT48 0x09 /**< Unsigned 48-bit integer. */ +#define BLE_GATT_CPF_FORMAT_UINT64 0x0A /**< Unsigned 64-bit integer. */ +#define BLE_GATT_CPF_FORMAT_UINT128 0x0B /**< Unsigned 128-bit integer. */ +#define BLE_GATT_CPF_FORMAT_SINT8 0x0C /**< Signed 2-bit integer. */ +#define BLE_GATT_CPF_FORMAT_SINT12 0x0D /**< Signed 12-bit integer. */ +#define BLE_GATT_CPF_FORMAT_SINT16 0x0E /**< Signed 16-bit integer. */ +#define BLE_GATT_CPF_FORMAT_SINT24 0x0F /**< Signed 24-bit integer. */ +#define BLE_GATT_CPF_FORMAT_SINT32 0x10 /**< Signed 32-bit integer. */ +#define BLE_GATT_CPF_FORMAT_SINT48 0x11 /**< Signed 48-bit integer. */ +#define BLE_GATT_CPF_FORMAT_SINT64 0x12 /**< Signed 64-bit integer. */ +#define BLE_GATT_CPF_FORMAT_SINT128 0x13 /**< Signed 128-bit integer. */ +#define BLE_GATT_CPF_FORMAT_FLOAT32 0x14 /**< IEEE-754 32-bit floating point. */ +#define BLE_GATT_CPF_FORMAT_FLOAT64 0x15 /**< IEEE-754 64-bit floating point. */ +#define BLE_GATT_CPF_FORMAT_SFLOAT 0x16 /**< IEEE-11073 16-bit SFLOAT. */ +#define BLE_GATT_CPF_FORMAT_FLOAT 0x17 /**< IEEE-11073 32-bit FLOAT. */ +#define BLE_GATT_CPF_FORMAT_DUINT16 0x18 /**< IEEE-20601 format. */ +#define BLE_GATT_CPF_FORMAT_UTF8S 0x19 /**< UTF-8 string. */ +#define BLE_GATT_CPF_FORMAT_UTF16S 0x1A /**< UTF-16 string. */ +#define BLE_GATT_CPF_FORMAT_STRUCT 0x1B /**< Opaque Structure. */ +/** @} */ + +/** @defgroup BLE_GATT_CPF_NAMESPACES GATT Bluetooth Namespaces + * @{ + */ +#define BLE_GATT_CPF_NAMESPACE_BTSIG 0x01 /**< Bluetooth SIG defined Namespace. */ +#define BLE_GATT_CPF_NAMESPACE_DESCRIPTION_UNKNOWN 0x0000 /**< Namespace Description Unknown. */ +/** @} */ + +/** @} */ + +/** @addtogroup BLE_GATT_STRUCTURES Structures + * @{ */ + +/** + * @brief BLE GATT connection configuration parameters, set with @ref sd_ble_cfg_set. + * + * @retval ::NRF_ERROR_INVALID_PARAM att_mtu is smaller than @ref BLE_GATT_ATT_MTU_DEFAULT. + */ +typedef struct +{ + uint16_t att_mtu; /**< Maximum size of ATT packet the SoftDevice can send or receive. + The default and minimum value is @ref BLE_GATT_ATT_MTU_DEFAULT. + @mscs + @mmsc{@ref BLE_GATTC_MTU_EXCHANGE} + @mmsc{@ref BLE_GATTS_MTU_EXCHANGE} + @endmscs + */ +} ble_gatt_conn_cfg_t; + +/**@brief GATT Characteristic Properties. */ +typedef struct +{ + /* Standard properties */ + uint8_t broadcast :1; /**< Broadcasting of the value permitted. */ + uint8_t read :1; /**< Reading the value permitted. */ + uint8_t write_wo_resp :1; /**< Writing the value with Write Command permitted. */ + uint8_t write :1; /**< Writing the value with Write Request permitted. */ + uint8_t notify :1; /**< Notification of the value permitted. */ + uint8_t indicate :1; /**< Indications of the value permitted. */ + uint8_t auth_signed_wr :1; /**< Writing the value with Signed Write Command permitted. */ +} ble_gatt_char_props_t; + +/**@brief GATT Characteristic Extended Properties. */ +typedef struct +{ + /* Extended properties */ + uint8_t reliable_wr :1; /**< Writing the value with Queued Write operations permitted. */ + uint8_t wr_aux :1; /**< Writing the Characteristic User Description descriptor permitted. */ +} ble_gatt_char_ext_props_t; + +/** @} */ + +#ifdef __cplusplus +} +#endif +#endif // BLE_GATT_H__ + +/** @} */ diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gattc.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gattc.h new file mode 100755 index 00000000..7fb39202 --- /dev/null +++ b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gattc.h @@ -0,0 +1,715 @@ +/* + * Copyright (c) 2011 - 2017, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_GATTC Generic Attribute Profile (GATT) Client + @{ + @brief Definitions and prototypes for the GATT Client interface. + */ + +#ifndef BLE_GATTC_H__ +#define BLE_GATTC_H__ + +#include <stdint.h> +#include "nrf.h" +#include "nrf_svc.h" +#include "nrf_error.h" +#include "ble_ranges.h" +#include "ble_types.h" +#include "ble_err.h" +#include "ble_gatt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup BLE_GATTC_ENUMERATIONS Enumerations + * @{ */ + +/**@brief GATTC API SVC numbers. */ +enum BLE_GATTC_SVCS +{ + SD_BLE_GATTC_PRIMARY_SERVICES_DISCOVER = BLE_GATTC_SVC_BASE, /**< Primary Service Discovery. */ + SD_BLE_GATTC_RELATIONSHIPS_DISCOVER, /**< Relationship Discovery. */ + SD_BLE_GATTC_CHARACTERISTICS_DISCOVER, /**< Characteristic Discovery. */ + SD_BLE_GATTC_DESCRIPTORS_DISCOVER, /**< Characteristic Descriptor Discovery. */ + SD_BLE_GATTC_ATTR_INFO_DISCOVER, /**< Attribute Information Discovery. */ + SD_BLE_GATTC_CHAR_VALUE_BY_UUID_READ, /**< Read Characteristic Value by UUID. */ + SD_BLE_GATTC_READ, /**< Generic read. */ + SD_BLE_GATTC_CHAR_VALUES_READ, /**< Read multiple Characteristic Values. */ + SD_BLE_GATTC_WRITE, /**< Generic write. */ + SD_BLE_GATTC_HV_CONFIRM, /**< Handle Value Confirmation. */ + SD_BLE_GATTC_EXCHANGE_MTU_REQUEST, /**< Exchange MTU Request. */ +}; + +/** + * @brief GATT Client Event IDs. + */ +enum BLE_GATTC_EVTS +{ + BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP = BLE_GATTC_EVT_BASE, /**< Primary Service Discovery Response event. \n See @ref ble_gattc_evt_prim_srvc_disc_rsp_t. */ + BLE_GATTC_EVT_REL_DISC_RSP, /**< Relationship Discovery Response event. \n See @ref ble_gattc_evt_rel_disc_rsp_t. */ + BLE_GATTC_EVT_CHAR_DISC_RSP, /**< Characteristic Discovery Response event. \n See @ref ble_gattc_evt_char_disc_rsp_t. */ + BLE_GATTC_EVT_DESC_DISC_RSP, /**< Descriptor Discovery Response event. \n See @ref ble_gattc_evt_desc_disc_rsp_t. */ + BLE_GATTC_EVT_ATTR_INFO_DISC_RSP, /**< Attribute Information Response event. \n See @ref ble_gattc_evt_attr_info_disc_rsp_t. */ + BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP, /**< Read By UUID Response event. \n See @ref ble_gattc_evt_char_val_by_uuid_read_rsp_t. */ + BLE_GATTC_EVT_READ_RSP, /**< Read Response event. \n See @ref ble_gattc_evt_read_rsp_t. */ + BLE_GATTC_EVT_CHAR_VALS_READ_RSP, /**< Read multiple Response event. \n See @ref ble_gattc_evt_char_vals_read_rsp_t. */ + BLE_GATTC_EVT_WRITE_RSP, /**< Write Response event. \n See @ref ble_gattc_evt_write_rsp_t. */ + BLE_GATTC_EVT_HVX, /**< Handle Value Notification or Indication event. \n Confirm indication with @ref sd_ble_gattc_hv_confirm. \n See @ref ble_gattc_evt_hvx_t. */ + BLE_GATTC_EVT_EXCHANGE_MTU_RSP, /**< Exchange MTU Response event. \n See @ref ble_gattc_evt_exchange_mtu_rsp_t. */ + BLE_GATTC_EVT_TIMEOUT, /**< Timeout event. \n See @ref ble_gattc_evt_timeout_t. */ + BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE /**< Write without Response transmission complete. \n See @ref ble_gattc_evt_write_cmd_tx_complete_t. */ +}; + +/** @} */ + +/** @addtogroup BLE_GATTC_DEFINES Defines + * @{ */ + +/** @defgroup BLE_ERRORS_GATTC SVC return values specific to GATTC + * @{ */ +#define BLE_ERROR_GATTC_PROC_NOT_PERMITTED (NRF_GATTC_ERR_BASE + 0x000) /**< Procedure not Permitted. */ +/** @} */ + +/** @defgroup BLE_GATTC_ATTR_INFO_FORMAT Attribute Information Formats + * @{ */ +#define BLE_GATTC_ATTR_INFO_FORMAT_16BIT 1 /**< 16-bit Attribute Information Format. */ +#define BLE_GATTC_ATTR_INFO_FORMAT_128BIT 2 /**< 128-bit Attribute Information Format. */ +/** @} */ + +/** @defgroup BLE_GATTC_DEFAULTS GATT Client defaults + * @{ */ +#define BLE_GATTC_WRITE_CMD_TX_QUEUE_SIZE_DEFAULT 1 /**< Default number of Write without Response that can be queued for transmission. */ +/** @} */ + +/** @} */ + +/** @addtogroup BLE_GATTC_STRUCTURES Structures + * @{ */ + +/** + * @brief BLE GATTC connection configuration parameters, set with @ref sd_ble_cfg_set. + */ +typedef struct +{ + uint8_t write_cmd_tx_queue_size; /**< The guaranteed minimum number of Write without Response that can be queued for transmission. + The default value is @ref BLE_GATTC_WRITE_CMD_TX_QUEUE_SIZE_DEFAULT */ +} ble_gattc_conn_cfg_t; + +/**@brief Operation Handle Range. */ +typedef struct +{ + uint16_t start_handle; /**< Start Handle. */ + uint16_t end_handle; /**< End Handle. */ +} ble_gattc_handle_range_t; + + +/**@brief GATT service. */ +typedef struct +{ + ble_uuid_t uuid; /**< Service UUID. */ + ble_gattc_handle_range_t handle_range; /**< Service Handle Range. */ +} ble_gattc_service_t; + + +/**@brief GATT include. */ +typedef struct +{ + uint16_t handle; /**< Include Handle. */ + ble_gattc_service_t included_srvc; /**< Handle of the included service. */ +} ble_gattc_include_t; + + +/**@brief GATT characteristic. */ +typedef struct +{ + ble_uuid_t uuid; /**< Characteristic UUID. */ + ble_gatt_char_props_t char_props; /**< Characteristic Properties. */ + uint8_t char_ext_props : 1; /**< Extended properties present. */ + uint16_t handle_decl; /**< Handle of the Characteristic Declaration. */ + uint16_t handle_value; /**< Handle of the Characteristic Value. */ +} ble_gattc_char_t; + + +/**@brief GATT descriptor. */ +typedef struct +{ + uint16_t handle; /**< Descriptor Handle. */ + ble_uuid_t uuid; /**< Descriptor UUID. */ +} ble_gattc_desc_t; + + +/**@brief Write Parameters. */ +typedef struct +{ + uint8_t write_op; /**< Write Operation to be performed, see @ref BLE_GATT_WRITE_OPS. */ + uint8_t flags; /**< Flags, see @ref BLE_GATT_EXEC_WRITE_FLAGS. */ + uint16_t handle; /**< Handle to the attribute to be written. */ + uint16_t offset; /**< Offset in bytes. @note For WRITE_CMD and WRITE_REQ, offset must be 0. */ + uint16_t len; /**< Length of data in bytes. */ + uint8_t const *p_value; /**< Pointer to the value data. */ +} ble_gattc_write_params_t; + +/**@brief Attribute Information for 16-bit Attribute UUID. */ +typedef struct +{ + uint16_t handle; /**< Attribute handle. */ + ble_uuid_t uuid; /**< 16-bit Attribute UUID. */ +} ble_gattc_attr_info16_t; + +/**@brief Attribute Information for 128-bit Attribute UUID. */ +typedef struct +{ + uint16_t handle; /**< Attribute handle. */ + ble_uuid128_t uuid; /**< 128-bit Attribute UUID. */ +} ble_gattc_attr_info128_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP. */ +typedef struct +{ + uint16_t count; /**< Service count. */ + ble_gattc_service_t services[1]; /**< Service data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gattc_evt_prim_srvc_disc_rsp_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_REL_DISC_RSP. */ +typedef struct +{ + uint16_t count; /**< Include count. */ + ble_gattc_include_t includes[1]; /**< Include data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gattc_evt_rel_disc_rsp_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_DISC_RSP. */ +typedef struct +{ + uint16_t count; /**< Characteristic count. */ + ble_gattc_char_t chars[1]; /**< Characteristic data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gattc_evt_char_disc_rsp_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_DESC_DISC_RSP. */ +typedef struct +{ + uint16_t count; /**< Descriptor count. */ + ble_gattc_desc_t descs[1]; /**< Descriptor data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gattc_evt_desc_disc_rsp_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_ATTR_INFO_DISC_RSP. */ +typedef struct +{ + uint16_t count; /**< Attribute count. */ + uint8_t format; /**< Attribute information format, see @ref BLE_GATTC_ATTR_INFO_FORMAT. */ + union { + ble_gattc_attr_info16_t attr_info16[1]; /**< Attribute information for 16-bit Attribute UUID. + @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ + ble_gattc_attr_info128_t attr_info128[1]; /**< Attribute information for 128-bit Attribute UUID. + @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ + } info; /**< Attribute information union. */ +} ble_gattc_evt_attr_info_disc_rsp_t; + +/**@brief GATT read by UUID handle value pair. */ +typedef struct +{ + uint16_t handle; /**< Attribute Handle. */ + uint8_t *p_value; /**< Pointer to the Attribute Value, length is available in @ref ble_gattc_evt_char_val_by_uuid_read_rsp_t::value_len. */ +} ble_gattc_handle_value_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP. */ +typedef struct +{ + uint16_t count; /**< Handle-Value Pair Count. */ + uint16_t value_len; /**< Length of the value in Handle-Value(s) list. */ + uint8_t handle_value[1]; /**< Handle-Value(s) list. To iterate through the list use @ref sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter. + @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gattc_evt_char_val_by_uuid_read_rsp_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_READ_RSP. */ +typedef struct +{ + uint16_t handle; /**< Attribute Handle. */ + uint16_t offset; /**< Offset of the attribute data. */ + uint16_t len; /**< Attribute data length. */ + uint8_t data[1]; /**< Attribute data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gattc_evt_read_rsp_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_VALS_READ_RSP. */ +typedef struct +{ + uint16_t len; /**< Concatenated Attribute values length. */ + uint8_t values[1]; /**< Attribute values. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gattc_evt_char_vals_read_rsp_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_WRITE_RSP. */ +typedef struct +{ + uint16_t handle; /**< Attribute Handle. */ + uint8_t write_op; /**< Type of write operation, see @ref BLE_GATT_WRITE_OPS. */ + uint16_t offset; /**< Data offset. */ + uint16_t len; /**< Data length. */ + uint8_t data[1]; /**< Data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gattc_evt_write_rsp_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_HVX. */ +typedef struct +{ + uint16_t handle; /**< Handle to which the HVx operation applies. */ + uint8_t type; /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */ + uint16_t len; /**< Attribute data length. */ + uint8_t data[1]; /**< Attribute data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gattc_evt_hvx_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_EXCHANGE_MTU_RSP. */ +typedef struct +{ + uint16_t server_rx_mtu; /**< Server RX MTU size. */ +} ble_gattc_evt_exchange_mtu_rsp_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_TIMEOUT. */ +typedef struct +{ + uint8_t src; /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */ +} ble_gattc_evt_timeout_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE. */ +typedef struct +{ + uint8_t count; /**< Number of write without response transmissions completed. */ +} ble_gattc_evt_write_cmd_tx_complete_t; + +/**@brief GATTC event structure. */ +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle on which event occurred. */ + uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ + uint16_t error_handle; /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */ + union + { + ble_gattc_evt_prim_srvc_disc_rsp_t prim_srvc_disc_rsp; /**< Primary Service Discovery Response Event Parameters. */ + ble_gattc_evt_rel_disc_rsp_t rel_disc_rsp; /**< Relationship Discovery Response Event Parameters. */ + ble_gattc_evt_char_disc_rsp_t char_disc_rsp; /**< Characteristic Discovery Response Event Parameters. */ + ble_gattc_evt_desc_disc_rsp_t desc_disc_rsp; /**< Descriptor Discovery Response Event Parameters. */ + ble_gattc_evt_char_val_by_uuid_read_rsp_t char_val_by_uuid_read_rsp; /**< Characteristic Value Read by UUID Response Event Parameters. */ + ble_gattc_evt_read_rsp_t read_rsp; /**< Read Response Event Parameters. */ + ble_gattc_evt_char_vals_read_rsp_t char_vals_read_rsp; /**< Characteristic Values Read Response Event Parameters. */ + ble_gattc_evt_write_rsp_t write_rsp; /**< Write Response Event Parameters. */ + ble_gattc_evt_hvx_t hvx; /**< Handle Value Notification/Indication Event Parameters. */ + ble_gattc_evt_exchange_mtu_rsp_t exchange_mtu_rsp; /**< Exchange MTU Response Event Parameters. */ + ble_gattc_evt_timeout_t timeout; /**< Timeout Event Parameters. */ + ble_gattc_evt_attr_info_disc_rsp_t attr_info_disc_rsp; /**< Attribute Information Discovery Event Parameters. */ + ble_gattc_evt_write_cmd_tx_complete_t write_cmd_tx_complete; /**< Write without Response transmission complete Event Parameters. */ + } params; /**< Event Parameters. @note Only valid if @ref gatt_status == @ref BLE_GATT_STATUS_SUCCESS. */ +} ble_gattc_evt_t; +/** @} */ + +/** @addtogroup BLE_GATTC_FUNCTIONS Functions + * @{ */ + +/**@brief Initiate or continue a GATT Primary Service Discovery procedure. + * + * @details This function initiates or resumes a Primary Service discovery procedure, starting from the supplied handle. + * If the last service has not been reached, this function must be called again with an updated start handle value to continue the search. + * + * @note If any of the discovered services have 128-bit UUIDs which are not present in the table provided to ble_vs_uuids_assign, a UUID structure with + * type @ref BLE_UUID_TYPE_UNKNOWN will be received in the corresponding event. + * + * @events + * @event{@ref BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTC_PRIM_SRVC_DISC_MSC} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] start_handle Handle to start searching from. + * @param[in] p_srvc_uuid Pointer to the service UUID to be found. If it is NULL, all primary services will be returned. + * + * @retval ::NRF_SUCCESS Successfully started or resumed the Primary Service Discovery procedure. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_BUSY Client procedure already in progress. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_PRIMARY_SERVICES_DISCOVER, uint32_t, sd_ble_gattc_primary_services_discover(uint16_t conn_handle, uint16_t start_handle, ble_uuid_t const *p_srvc_uuid)); + + +/**@brief Initiate or continue a GATT Relationship Discovery procedure. + * + * @details This function initiates or resumes the Find Included Services sub-procedure. If the last included service has not been reached, + * this must be called again with an updated handle range to continue the search. + * + * @events + * @event{@ref BLE_GATTC_EVT_REL_DISC_RSP} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTC_REL_DISC_MSC} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] p_handle_range A pointer to the range of handles of the Service to perform this procedure on. + * + * @retval ::NRF_SUCCESS Successfully started or resumed the Relationship Discovery procedure. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_BUSY Client procedure already in progress. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_RELATIONSHIPS_DISCOVER, uint32_t, sd_ble_gattc_relationships_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range)); + + +/**@brief Initiate or continue a GATT Characteristic Discovery procedure. + * + * @details This function initiates or resumes a Characteristic discovery procedure. If the last Characteristic has not been reached, + * this must be called again with an updated handle range to continue the discovery. + * + * @note If any of the discovered characteristics have 128-bit UUIDs which are not present in the table provided to ble_vs_uuids_assign, a UUID structure with + * type @ref BLE_UUID_TYPE_UNKNOWN will be received in the corresponding event. + * + * @events + * @event{@ref BLE_GATTC_EVT_CHAR_DISC_RSP} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTC_CHAR_DISC_MSC} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] p_handle_range A pointer to the range of handles of the Service to perform this procedure on. + * + * @retval ::NRF_SUCCESS Successfully started or resumed the Characteristic Discovery procedure. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_BUSY Client procedure already in progress. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_CHARACTERISTICS_DISCOVER, uint32_t, sd_ble_gattc_characteristics_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range)); + + +/**@brief Initiate or continue a GATT Characteristic Descriptor Discovery procedure. + * + * @details This function initiates or resumes a Characteristic Descriptor discovery procedure. If the last Descriptor has not been reached, + * this must be called again with an updated handle range to continue the discovery. + * + * @events + * @event{@ref BLE_GATTC_EVT_DESC_DISC_RSP} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTC_DESC_DISC_MSC} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] p_handle_range A pointer to the range of handles of the Characteristic to perform this procedure on. + * + * @retval ::NRF_SUCCESS Successfully started or resumed the Descriptor Discovery procedure. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_BUSY Client procedure already in progress. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_DESCRIPTORS_DISCOVER, uint32_t, sd_ble_gattc_descriptors_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range)); + + +/**@brief Initiate or continue a GATT Read using Characteristic UUID procedure. + * + * @details This function initiates or resumes a Read using Characteristic UUID procedure. If the last Characteristic has not been reached, + * this must be called again with an updated handle range to continue the discovery. + * + * @events + * @event{@ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTC_READ_UUID_MSC} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] p_uuid Pointer to a Characteristic value UUID to read. + * @param[in] p_handle_range A pointer to the range of handles to perform this procedure on. + * + * @retval ::NRF_SUCCESS Successfully started or resumed the Read using Characteristic UUID procedure. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_BUSY Client procedure already in progress. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_CHAR_VALUE_BY_UUID_READ, uint32_t, sd_ble_gattc_char_value_by_uuid_read(uint16_t conn_handle, ble_uuid_t const *p_uuid, ble_gattc_handle_range_t const *p_handle_range)); + + +/**@brief Initiate or continue a GATT Read (Long) Characteristic or Descriptor procedure. + * + * @details This function initiates or resumes a GATT Read (Long) Characteristic or Descriptor procedure. If the Characteristic or Descriptor + * to be read is longer than ATT_MTU - 1, this function must be called multiple times with appropriate offset to read the + * complete value. + * + * @events + * @event{@ref BLE_GATTC_EVT_READ_RSP} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTC_VALUE_READ_MSC} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] handle The handle of the attribute to be read. + * @param[in] offset Offset into the attribute value to be read. + * + * @retval ::NRF_SUCCESS Successfully started or resumed the Read (Long) procedure. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. + * @retval ::NRF_ERROR_BUSY Client procedure already in progress. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_READ, uint32_t, sd_ble_gattc_read(uint16_t conn_handle, uint16_t handle, uint16_t offset)); + + +/**@brief Initiate a GATT Read Multiple Characteristic Values procedure. + * + * @details This function initiates a GATT Read Multiple Characteristic Values procedure. + * + * @events + * @event{@ref BLE_GATTC_EVT_CHAR_VALS_READ_RSP} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTC_READ_MULT_MSC} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] p_handles A pointer to the handle(s) of the attribute(s) to be read. + * @param[in] handle_count The number of handles in p_handles. + * + * @retval ::NRF_SUCCESS Successfully started the Read Multiple Characteristic Values procedure. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_BUSY Client procedure already in progress. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_CHAR_VALUES_READ, uint32_t, sd_ble_gattc_char_values_read(uint16_t conn_handle, uint16_t const *p_handles, uint16_t handle_count)); + + +/**@brief Perform a Write (Characteristic Value or Descriptor, with or without response, signed or not, long or reliable) procedure. + * + * @details This function can perform all write procedures described in GATT. + * + * @note Only one write with response procedure can be ongoing per connection at a time. + * If the application tries to write with response while another write with response procedure is ongoing, + * the function call will return @ref NRF_ERROR_BUSY. + * A @ref BLE_GATTC_EVT_WRITE_RSP event will be issued as soon as the write response arrives from the peer. + * + * @note The number of Write without Response that can be queued is configured by @ref ble_gattc_conn_cfg_t::write_cmd_tx_queue_size + * When the queue is full, the function call will return @ref NRF_ERROR_RESOURCES. + * A @ref BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE event will be issued as soon as the transmission of the write without response is complete. + * + * @note The application can keep track of the available queue element count for writes without responses by following the procedure below: + * - Store initial queue element count in a variable. + * - Decrement the variable, which stores the currently available queue element count, by one when a call to this function returns @ref NRF_SUCCESS. + * - Increment the variable, which stores the current available queue element count, by the count variable in @ref BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE event. + * + * @events + * @event{@ref BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE, Write without response transmission complete.} + * @event{@ref BLE_GATTC_EVT_WRITE_RSP, Write response received from the peer.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTC_VALUE_WRITE_WITHOUT_RESP_MSC} + * @mmsc{@ref BLE_GATTC_VALUE_WRITE_MSC} + * @mmsc{@ref BLE_GATTC_VALUE_LONG_WRITE_MSC} + * @mmsc{@ref BLE_GATTC_VALUE_RELIABLE_WRITE_MSC} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] p_write_params A pointer to a write parameters structure. + * + * @retval ::NRF_SUCCESS Successfully started the Write procedure. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied. + * @retval ::NRF_ERROR_BUSY For write with response, procedure already in progress. Wait for a @ref BLE_GATTC_EVT_WRITE_RSP event and retry. + * @retval ::NRF_ERROR_RESOURCES Too many writes without responses queued. + * Wait for a @ref BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE event and retry. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_WRITE, uint32_t, sd_ble_gattc_write(uint16_t conn_handle, ble_gattc_write_params_t const *p_write_params)); + + +/**@brief Send a Handle Value Confirmation to the GATT Server. + * + * @mscs + * @mmsc{@ref BLE_GATTC_HVI_MSC} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] handle The handle of the attribute in the indication. + * + * @retval ::NRF_SUCCESS Successfully queued the Handle Value Confirmation for transmission. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State or no Indication pending to be confirmed. + * @retval ::BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_HV_CONFIRM, uint32_t, sd_ble_gattc_hv_confirm(uint16_t conn_handle, uint16_t handle)); + +/**@brief Discovers information about a range of attributes on a GATT server. + * + * @events + * @event{@ref BLE_GATTC_EVT_ATTR_INFO_DISC_RSP, Generated when information about a range of attributes has been received.} + * @endevents + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] p_handle_range The range of handles to request information about. + * + * @retval ::NRF_SUCCESS Successfully started an attribute information discovery procedure. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid connection state + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_BUSY Client procedure already in progress. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_ATTR_INFO_DISCOVER, uint32_t, sd_ble_gattc_attr_info_discover(uint16_t conn_handle, ble_gattc_handle_range_t const * p_handle_range)); + +/**@brief Start an ATT_MTU exchange by sending an Exchange MTU Request to the server. + * + * @details The SoftDevice sets ATT_MTU to the minimum of: + * - The Client RX MTU value, and + * - The Server RX MTU value from @ref BLE_GATTC_EVT_EXCHANGE_MTU_RSP. + * + * However, the SoftDevice never sets ATT_MTU lower than @ref BLE_GATT_ATT_MTU_DEFAULT. + * + * @events + * @event{@ref BLE_GATTC_EVT_EXCHANGE_MTU_RSP} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTC_MTU_EXCHANGE} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] client_rx_mtu Client RX MTU size. + * - The minimum value is @ref BLE_GATT_ATT_MTU_DEFAULT. + * - The maximum value is @ref ble_gatt_conn_cfg_t::att_mtu in the connection configuration + used for this connection. + * - The value must be equal to Server RX MTU size given in @ref sd_ble_gatts_exchange_mtu_reply + * if an ATT_MTU exchange has already been performed in the other direction. + * + * @retval ::NRF_SUCCESS Successfully sent request to the server. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid connection state or an ATT_MTU exchange was already requested once. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid Client RX MTU size supplied. + * @retval ::NRF_ERROR_BUSY Client procedure already in progress. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_EXCHANGE_MTU_REQUEST, uint32_t, sd_ble_gattc_exchange_mtu_request(uint16_t conn_handle, uint16_t client_rx_mtu)); + +/**@brief Iterate through Handle-Value(s) list in @ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP event. + * + * @param[in] p_gattc_evt Pointer to event buffer containing @ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP event. + * @note If the buffer contains different event, behavior is undefined. + * @param[in,out] p_iter Iterator, points to @ref ble_gattc_handle_value_t structure that will be filled in with + * the next Handle-Value pair in each iteration. If the function returns other than + * @ref NRF_SUCCESS, it will not be changed. + * - To start iteration, initialize the structure to zero. + * - To continue, pass the value from previous iteration. + * + * \code + * ble_gattc_handle_value_t iter; + * memset(&iter, 0, sizeof(ble_gattc_handle_value_t)); + * while (sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter(&ble_evt.evt.gattc_evt, &iter) == NRF_SUCCESS) + * { + * app_handle = iter.handle; + * memcpy(app_value, iter.p_value, ble_evt.evt.gattc_evt.params.char_val_by_uuid_read_rsp.value_len); + * } + * \endcode + * + * @retval ::NRF_SUCCESS Successfully retrieved the next Handle-Value pair. + * @retval ::NRF_ERROR_NOT_FOUND No more Handle-Value pairs available in the list. + */ +__STATIC_INLINE uint32_t sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter(ble_gattc_evt_t *p_gattc_evt, ble_gattc_handle_value_t *p_iter); + +/** @} */ + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE uint32_t sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter(ble_gattc_evt_t *p_gattc_evt, ble_gattc_handle_value_t *p_iter) +{ + uint32_t value_len = p_gattc_evt->params.char_val_by_uuid_read_rsp.value_len; + uint8_t *p_first = p_gattc_evt->params.char_val_by_uuid_read_rsp.handle_value; + uint8_t *p_next = p_iter->p_value ? p_iter->p_value + value_len : p_first; + + if ((p_next - p_first) / (sizeof(uint16_t) + value_len) < p_gattc_evt->params.char_val_by_uuid_read_rsp.count) + { + p_iter->handle = (uint16_t)p_next[1] << 8 | p_next[0]; + p_iter->p_value = p_next + sizeof(uint16_t); + return NRF_SUCCESS; + } + else + { + return NRF_ERROR_NOT_FOUND; + } +} + +#endif /* SUPPRESS_INLINE_IMPLEMENTATION */ + +#ifdef __cplusplus +} +#endif +#endif /* BLE_GATTC_H__ */ + +/** + @} +*/ diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gatts.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gatts.h new file mode 100755 index 00000000..394d8d18 --- /dev/null +++ b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gatts.h @@ -0,0 +1,845 @@ +/* + * Copyright (c) 2011 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_GATTS Generic Attribute Profile (GATT) Server + @{ + @brief Definitions and prototypes for the GATTS interface. + */ + +#ifndef BLE_GATTS_H__ +#define BLE_GATTS_H__ + +#include <stdint.h> +#include "nrf_svc.h" +#include "nrf_error.h" +#include "ble_hci.h" +#include "ble_ranges.h" +#include "ble_types.h" +#include "ble_err.h" +#include "ble_gatt.h" +#include "ble_gap.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup BLE_GATTS_ENUMERATIONS Enumerations + * @{ */ + +/** + * @brief GATTS API SVC numbers. + */ +enum BLE_GATTS_SVCS +{ + SD_BLE_GATTS_SERVICE_ADD = BLE_GATTS_SVC_BASE, /**< Add a service. */ + SD_BLE_GATTS_INCLUDE_ADD, /**< Add an included service. */ + SD_BLE_GATTS_CHARACTERISTIC_ADD, /**< Add a characteristic. */ + SD_BLE_GATTS_DESCRIPTOR_ADD, /**< Add a generic attribute. */ + SD_BLE_GATTS_VALUE_SET, /**< Set an attribute value. */ + SD_BLE_GATTS_VALUE_GET, /**< Get an attribute value. */ + SD_BLE_GATTS_HVX, /**< Handle Value Notification or Indication. */ + SD_BLE_GATTS_SERVICE_CHANGED, /**< Perform a Service Changed Indication to one or more peers. */ + SD_BLE_GATTS_RW_AUTHORIZE_REPLY, /**< Reply to an authorization request for a read or write operation on one or more attributes. */ + SD_BLE_GATTS_SYS_ATTR_SET, /**< Set the persistent system attributes for a connection. */ + SD_BLE_GATTS_SYS_ATTR_GET, /**< Retrieve the persistent system attributes. */ + SD_BLE_GATTS_INITIAL_USER_HANDLE_GET, /**< Retrieve the first valid user handle. */ + SD_BLE_GATTS_ATTR_GET, /**< Retrieve the UUID and/or metadata of an attribute. */ + SD_BLE_GATTS_EXCHANGE_MTU_REPLY /**< Reply to Exchange MTU Request. */ +}; + +/** + * @brief GATT Server Event IDs. + */ +enum BLE_GATTS_EVTS +{ + BLE_GATTS_EVT_WRITE = BLE_GATTS_EVT_BASE, /**< Write operation performed. \n See @ref ble_gatts_evt_write_t. */ + BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST, /**< Read/Write Authorization request. \n Reply with @ref sd_ble_gatts_rw_authorize_reply. \n See @ref ble_gatts_evt_rw_authorize_request_t. */ + BLE_GATTS_EVT_SYS_ATTR_MISSING, /**< A persistent system attribute access is pending. \n Respond with @ref sd_ble_gatts_sys_attr_set. \n See @ref ble_gatts_evt_sys_attr_missing_t. */ + BLE_GATTS_EVT_HVC, /**< Handle Value Confirmation. \n See @ref ble_gatts_evt_hvc_t. */ + BLE_GATTS_EVT_SC_CONFIRM, /**< Service Changed Confirmation. \n No additional event structure applies. */ + BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST, /**< Exchange MTU Request. \n Reply with @ref sd_ble_gatts_exchange_mtu_reply. \n See @ref ble_gatts_evt_exchange_mtu_request_t. */ + BLE_GATTS_EVT_TIMEOUT, /**< Peer failed to respond to an ATT request in time. \n See @ref ble_gatts_evt_timeout_t. */ + BLE_GATTS_EVT_HVN_TX_COMPLETE /**< Handle Value Notification transmission complete. \n See @ref ble_gatts_evt_hvn_tx_complete_t. */ +}; + +/**@brief GATTS Configuration IDs. + * + * IDs that uniquely identify a GATTS configuration. + */ +enum BLE_GATTS_CFGS +{ + BLE_GATTS_CFG_SERVICE_CHANGED = BLE_GATTS_CFG_BASE, /**< Service changed configuration. */ + BLE_GATTS_CFG_ATTR_TAB_SIZE, /**< Attribute table size configuration. */ +}; + +/** @} */ + +/** @addtogroup BLE_GATTS_DEFINES Defines + * @{ */ + +/** @defgroup BLE_ERRORS_GATTS SVC return values specific to GATTS + * @{ */ +#define BLE_ERROR_GATTS_INVALID_ATTR_TYPE (NRF_GATTS_ERR_BASE + 0x000) /**< Invalid attribute type. */ +#define BLE_ERROR_GATTS_SYS_ATTR_MISSING (NRF_GATTS_ERR_BASE + 0x001) /**< System Attributes missing. */ +/** @} */ + +/** @defgroup BLE_GATTS_ATTR_LENS_MAX Maximum attribute lengths + * @{ */ +#define BLE_GATTS_FIX_ATTR_LEN_MAX (510) /**< Maximum length for fixed length Attribute Values. */ +#define BLE_GATTS_VAR_ATTR_LEN_MAX (512) /**< Maximum length for variable length Attribute Values. */ +/** @} */ + +/** @defgroup BLE_GATTS_SRVC_TYPES GATT Server Service Types + * @{ */ +#define BLE_GATTS_SRVC_TYPE_INVALID 0x00 /**< Invalid Service Type. */ +#define BLE_GATTS_SRVC_TYPE_PRIMARY 0x01 /**< Primary Service. */ +#define BLE_GATTS_SRVC_TYPE_SECONDARY 0x02 /**< Secondary Type. */ +/** @} */ + + +/** @defgroup BLE_GATTS_ATTR_TYPES GATT Server Attribute Types + * @{ */ +#define BLE_GATTS_ATTR_TYPE_INVALID 0x00 /**< Invalid Attribute Type. */ +#define BLE_GATTS_ATTR_TYPE_PRIM_SRVC_DECL 0x01 /**< Primary Service Declaration. */ +#define BLE_GATTS_ATTR_TYPE_SEC_SRVC_DECL 0x02 /**< Secondary Service Declaration. */ +#define BLE_GATTS_ATTR_TYPE_INC_DECL 0x03 /**< Include Declaration. */ +#define BLE_GATTS_ATTR_TYPE_CHAR_DECL 0x04 /**< Characteristic Declaration. */ +#define BLE_GATTS_ATTR_TYPE_CHAR_VAL 0x05 /**< Characteristic Value. */ +#define BLE_GATTS_ATTR_TYPE_DESC 0x06 /**< Descriptor. */ +#define BLE_GATTS_ATTR_TYPE_OTHER 0x07 /**< Other, non-GATT specific type. */ +/** @} */ + + +/** @defgroup BLE_GATTS_OPS GATT Server Operations + * @{ */ +#define BLE_GATTS_OP_INVALID 0x00 /**< Invalid Operation. */ +#define BLE_GATTS_OP_WRITE_REQ 0x01 /**< Write Request. */ +#define BLE_GATTS_OP_WRITE_CMD 0x02 /**< Write Command. */ +#define BLE_GATTS_OP_SIGN_WRITE_CMD 0x03 /**< Signed Write Command. */ +#define BLE_GATTS_OP_PREP_WRITE_REQ 0x04 /**< Prepare Write Request. */ +#define BLE_GATTS_OP_EXEC_WRITE_REQ_CANCEL 0x05 /**< Execute Write Request: Cancel all prepared writes. */ +#define BLE_GATTS_OP_EXEC_WRITE_REQ_NOW 0x06 /**< Execute Write Request: Immediately execute all prepared writes. */ +/** @} */ + +/** @defgroup BLE_GATTS_VLOCS GATT Value Locations + * @{ */ +#define BLE_GATTS_VLOC_INVALID 0x00 /**< Invalid Location. */ +#define BLE_GATTS_VLOC_STACK 0x01 /**< Attribute Value is located in stack memory, no user memory is required. */ +#define BLE_GATTS_VLOC_USER 0x02 /**< Attribute Value is located in user memory. This requires the user to maintain a valid buffer through the lifetime of the attribute, since the stack + will read and write directly to the memory using the pointer provided in the APIs. There are no alignment requirements for the buffer. */ +/** @} */ + +/** @defgroup BLE_GATTS_AUTHORIZE_TYPES GATT Server Authorization Types + * @{ */ +#define BLE_GATTS_AUTHORIZE_TYPE_INVALID 0x00 /**< Invalid Type. */ +#define BLE_GATTS_AUTHORIZE_TYPE_READ 0x01 /**< Authorize a Read Operation. */ +#define BLE_GATTS_AUTHORIZE_TYPE_WRITE 0x02 /**< Authorize a Write Request Operation. */ +/** @} */ + +/** @defgroup BLE_GATTS_SYS_ATTR_FLAGS System Attribute Flags + * @{ */ +#define BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS (1 << 0) /**< Restrict system attributes to system services only. */ +#define BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS (1 << 1) /**< Restrict system attributes to user services only. */ +/** @} */ + +/** @defgroup BLE_GATTS_SERVICE_CHANGED Service Changed Inclusion Values + * @{ + */ +#define BLE_GATTS_SERVICE_CHANGED_DEFAULT (1) /**< Default is to include the Service Changed characteristic in the Attribute Table. */ +/** @} */ + +/** @defgroup BLE_GATTS_ATTR_TAB_SIZE Attribute Table size + * @{ + */ +#define BLE_GATTS_ATTR_TAB_SIZE_MIN (248) /**< Minimum Attribute Table size */ +#define BLE_GATTS_ATTR_TAB_SIZE_DEFAULT (1408) /**< Default Attribute Table size. */ +/** @} */ + +/** @defgroup BLE_GATTS_DEFAULTS GATT Server defaults + * @{ + */ +#define BLE_GATTS_HVN_TX_QUEUE_SIZE_DEFAULT 1 /**< Default number of Handle Value Notifications that can be queued for transmission. */ +/** @} */ + +/** @} */ + +/** @addtogroup BLE_GATTS_STRUCTURES Structures + * @{ */ + +/** + * @brief BLE GATTS connection configuration parameters, set with @ref sd_ble_cfg_set. + */ +typedef struct +{ + uint8_t hvn_tx_queue_size; /**< Minimum guaranteed number of Handle Value Notifications that can be queued for transmission. + The default value is @ref BLE_GATTS_HVN_TX_QUEUE_SIZE_DEFAULT */ +} ble_gatts_conn_cfg_t; + +/**@brief Attribute metadata. */ +typedef struct +{ + ble_gap_conn_sec_mode_t read_perm; /**< Read permissions. */ + ble_gap_conn_sec_mode_t write_perm; /**< Write permissions. */ + uint8_t vlen :1; /**< Variable length attribute. */ + uint8_t vloc :2; /**< Value location, see @ref BLE_GATTS_VLOCS.*/ + uint8_t rd_auth :1; /**< Read authorization and value will be requested from the application on every read operation. */ + uint8_t wr_auth :1; /**< Write authorization will be requested from the application on every Write Request operation (but not Write Command). */ +} ble_gatts_attr_md_t; + + +/**@brief GATT Attribute. */ +typedef struct +{ + ble_uuid_t const *p_uuid; /**< Pointer to the attribute UUID. */ + ble_gatts_attr_md_t const *p_attr_md; /**< Pointer to the attribute metadata structure. */ + uint16_t init_len; /**< Initial attribute value length in bytes. */ + uint16_t init_offs; /**< Initial attribute value offset in bytes. If different from zero, the first init_offs bytes of the attribute value will be left uninitialized. */ + uint16_t max_len; /**< Maximum attribute value length in bytes, see @ref BLE_GATTS_ATTR_LENS_MAX for maximum values. */ + uint8_t *p_value; /**< Pointer to the attribute data. Please note that if the @ref BLE_GATTS_VLOC_USER value location is selected in the attribute metadata, this will have to point to a buffer + that remains valid through the lifetime of the attribute. This excludes usage of automatic variables that may go out of scope or any other temporary location. + The stack may access that memory directly without the application's knowledge. For writable characteristics, this value must not be a location in flash memory.*/ +} ble_gatts_attr_t; + +/**@brief GATT Attribute Value. */ +typedef struct +{ + uint16_t len; /**< Length in bytes to be written or read. Length in bytes written or read after successful return.*/ + uint16_t offset; /**< Attribute value offset. */ + uint8_t *p_value; /**< Pointer to where value is stored or will be stored. + If value is stored in user memory, only the attribute length is updated when p_value == NULL. + Set to NULL when reading to obtain the complete length of the attribute value */ +} ble_gatts_value_t; + + +/**@brief GATT Characteristic Presentation Format. */ +typedef struct +{ + uint8_t format; /**< Format of the value, see @ref BLE_GATT_CPF_FORMATS. */ + int8_t exponent; /**< Exponent for integer data types. */ + uint16_t unit; /**< Unit from Bluetooth Assigned Numbers. */ + uint8_t name_space; /**< Namespace from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */ + uint16_t desc; /**< Namespace description from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */ +} ble_gatts_char_pf_t; + + +/**@brief GATT Characteristic metadata. */ +typedef struct +{ + ble_gatt_char_props_t char_props; /**< Characteristic Properties. */ + ble_gatt_char_ext_props_t char_ext_props; /**< Characteristic Extended Properties. */ + uint8_t const *p_char_user_desc; /**< Pointer to a UTF-8 encoded string (non-NULL terminated), NULL if the descriptor is not required. */ + uint16_t char_user_desc_max_size; /**< The maximum size in bytes of the user description descriptor. */ + uint16_t char_user_desc_size; /**< The size of the user description, must be smaller or equal to char_user_desc_max_size. */ + ble_gatts_char_pf_t const *p_char_pf; /**< Pointer to a presentation format structure or NULL if the CPF descriptor is not required. */ + ble_gatts_attr_md_t const *p_user_desc_md; /**< Attribute metadata for the User Description descriptor, or NULL for default values. */ + ble_gatts_attr_md_t const *p_cccd_md; /**< Attribute metadata for the Client Characteristic Configuration Descriptor, or NULL for default values. */ + ble_gatts_attr_md_t const *p_sccd_md; /**< Attribute metadata for the Server Characteristic Configuration Descriptor, or NULL for default values. */ +} ble_gatts_char_md_t; + + +/**@brief GATT Characteristic Definition Handles. */ +typedef struct +{ + uint16_t value_handle; /**< Handle to the characteristic value. */ + uint16_t user_desc_handle; /**< Handle to the User Description descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */ + uint16_t cccd_handle; /**< Handle to the Client Characteristic Configuration Descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */ + uint16_t sccd_handle; /**< Handle to the Server Characteristic Configuration Descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */ +} ble_gatts_char_handles_t; + + +/**@brief GATT HVx parameters. */ +typedef struct +{ + uint16_t handle; /**< Characteristic Value Handle. */ + uint8_t type; /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */ + uint16_t offset; /**< Offset within the attribute value. */ + uint16_t *p_len; /**< Length in bytes to be written, length in bytes written after return. */ + uint8_t const *p_data; /**< Actual data content, use NULL to use the current attribute value. */ +} ble_gatts_hvx_params_t; + +/**@brief GATT Authorization parameters. */ +typedef struct +{ + uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ + uint8_t update : 1; /**< If set, data supplied in p_data will be used to update the attribute value. + Please note that for @ref BLE_GATTS_AUTHORIZE_TYPE_WRITE operations this bit must always be set, + as the data to be written needs to be stored and later provided by the application. */ + uint16_t offset; /**< Offset of the attribute value being updated. */ + uint16_t len; /**< Length in bytes of the value in p_data pointer, see @ref BLE_GATTS_ATTR_LENS_MAX. */ + uint8_t const *p_data; /**< Pointer to new value used to update the attribute value. */ +} ble_gatts_authorize_params_t; + +/**@brief GATT Read or Write Authorize Reply parameters. */ +typedef struct +{ + uint8_t type; /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */ + union { + ble_gatts_authorize_params_t read; /**< Read authorization parameters. */ + ble_gatts_authorize_params_t write; /**< Write authorization parameters. */ + } params; /**< Reply Parameters. */ +} ble_gatts_rw_authorize_reply_params_t; + +/**@brief Service Changed Inclusion configuration parameters, set with @ref sd_ble_cfg_set. */ +typedef struct +{ + uint8_t service_changed : 1; /**< If 1, include the Service Changed characteristic in the Attribute Table. Default is @ref BLE_GATTS_SERVICE_CHANGED_DEFAULT. */ +} ble_gatts_cfg_service_changed_t; + +/**@brief Attribute table size configuration parameters, set with @ref sd_ble_cfg_set. + * + * @retval ::NRF_ERROR_INVALID_LENGTH One or more of the following is true: + * - The specified Attribute Table size is too small. + * The minimum acceptable size is defined by @ref BLE_GATTS_ATTR_TAB_SIZE_MIN. + * - The specified Attribute Table size is not a multiple of 4. + */ +typedef struct +{ + uint32_t attr_tab_size; /**< Attribute table size. Default is @ref BLE_GATTS_ATTR_TAB_SIZE_DEFAULT, minimum is @ref BLE_GATTS_ATTR_TAB_SIZE_MIN. */ +} ble_gatts_cfg_attr_tab_size_t; + +/**@brief Config structure for GATTS configurations. */ +typedef union +{ + ble_gatts_cfg_service_changed_t service_changed; /**< Include service changed characteristic, cfg_id is @ref BLE_GATTS_CFG_SERVICE_CHANGED. */ + ble_gatts_cfg_attr_tab_size_t attr_tab_size; /**< Attribute table size, cfg_id is @ref BLE_GATTS_CFG_ATTR_TAB_SIZE. */ +} ble_gatts_cfg_t; + + +/**@brief Event structure for @ref BLE_GATTS_EVT_WRITE. */ +typedef struct +{ + uint16_t handle; /**< Attribute Handle. */ + ble_uuid_t uuid; /**< Attribute UUID. */ + uint8_t op; /**< Type of write operation, see @ref BLE_GATTS_OPS. */ + uint8_t auth_required; /**< Writing operation deferred due to authorization requirement. Application may use @ref sd_ble_gatts_value_set to finalize the writing operation. */ + uint16_t offset; /**< Offset for the write operation. */ + uint16_t len; /**< Length of the received data. */ + uint8_t data[1]; /**< Received data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gatts_evt_write_t; + +/**@brief Event substructure for authorized read requests, see @ref ble_gatts_evt_rw_authorize_request_t. */ +typedef struct +{ + uint16_t handle; /**< Attribute Handle. */ + ble_uuid_t uuid; /**< Attribute UUID. */ + uint16_t offset; /**< Offset for the read operation. */ +} ble_gatts_evt_read_t; + +/**@brief Event structure for @ref BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST. */ +typedef struct +{ + uint8_t type; /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */ + union { + ble_gatts_evt_read_t read; /**< Attribute Read Parameters. */ + ble_gatts_evt_write_t write; /**< Attribute Write Parameters. */ + } request; /**< Request Parameters. */ +} ble_gatts_evt_rw_authorize_request_t; + +/**@brief Event structure for @ref BLE_GATTS_EVT_SYS_ATTR_MISSING. */ +typedef struct +{ + uint8_t hint; /**< Hint (currently unused). */ +} ble_gatts_evt_sys_attr_missing_t; + + +/**@brief Event structure for @ref BLE_GATTS_EVT_HVC. */ +typedef struct +{ + uint16_t handle; /**< Attribute Handle. */ +} ble_gatts_evt_hvc_t; + +/**@brief Event structure for @ref BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST. */ +typedef struct +{ + uint16_t client_rx_mtu; /**< Client RX MTU size. */ +} ble_gatts_evt_exchange_mtu_request_t; + +/**@brief Event structure for @ref BLE_GATTS_EVT_TIMEOUT. */ +typedef struct +{ + uint8_t src; /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */ +} ble_gatts_evt_timeout_t; + +/**@brief Event structure for @ref BLE_GATTS_EVT_HVN_TX_COMPLETE. */ +typedef struct +{ + uint8_t count; /**< Number of notification transmissions completed. */ +} ble_gatts_evt_hvn_tx_complete_t; + +/**@brief GATTS event structure. */ +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle on which the event occurred. */ + union + { + ble_gatts_evt_write_t write; /**< Write Event Parameters. */ + ble_gatts_evt_rw_authorize_request_t authorize_request; /**< Read or Write Authorize Request Parameters. */ + ble_gatts_evt_sys_attr_missing_t sys_attr_missing; /**< System attributes missing. */ + ble_gatts_evt_hvc_t hvc; /**< Handle Value Confirmation Event Parameters. */ + ble_gatts_evt_exchange_mtu_request_t exchange_mtu_request; /**< Exchange MTU Request Event Parameters. */ + ble_gatts_evt_timeout_t timeout; /**< Timeout Event. */ + ble_gatts_evt_hvn_tx_complete_t hvn_tx_complete; /**< Handle Value Notification transmission complete Event Parameters. */ + } params; /**< Event Parameters. */ +} ble_gatts_evt_t; + +/** @} */ + +/** @addtogroup BLE_GATTS_FUNCTIONS Functions + * @{ */ + +/**@brief Add a service declaration to the Attribute Table. + * + * @note Secondary Services are only relevant in the context of the entity that references them, it is therefore forbidden to + * add a secondary service declaration that is not referenced by another service later in the Attribute Table. + * + * @mscs + * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC} + * @endmscs + * + * @param[in] type Toggles between primary and secondary services, see @ref BLE_GATTS_SRVC_TYPES. + * @param[in] p_uuid Pointer to service UUID. + * @param[out] p_handle Pointer to a 16-bit word where the assigned handle will be stored. + * + * @retval ::NRF_SUCCESS Successfully added a service declaration. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, Vendor Specific UUIDs need to be present in the table. + * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack. + * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. + */ +SVCALL(SD_BLE_GATTS_SERVICE_ADD, uint32_t, sd_ble_gatts_service_add(uint8_t type, ble_uuid_t const *p_uuid, uint16_t *p_handle)); + + +/**@brief Add an include declaration to the Attribute Table. + * + * @note It is currently only possible to add an include declaration to the last added service (i.e. only sequential population is supported at this time). + * + * @note The included service must already be present in the Attribute Table prior to this call. + * + * @mscs + * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC} + * @endmscs + * + * @param[in] service_handle Handle of the service where the included service is to be placed, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially. + * @param[in] inc_srvc_handle Handle of the included service. + * @param[out] p_include_handle Pointer to a 16-bit word where the assigned handle will be stored. + * + * @retval ::NRF_SUCCESS Successfully added an include declaration. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, handle values need to match previously added services. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation, a service context is required. + * @retval ::NRF_ERROR_NOT_SUPPORTED Feature is not supported, service_handle must be that of the last added service. + * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, self inclusions are not allowed. + * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. + * @retval ::NRF_ERROR_NOT_FOUND Attribute not found. + */ +SVCALL(SD_BLE_GATTS_INCLUDE_ADD, uint32_t, sd_ble_gatts_include_add(uint16_t service_handle, uint16_t inc_srvc_handle, uint16_t *p_include_handle)); + + +/**@brief Add a characteristic declaration, a characteristic value declaration and optional characteristic descriptor declarations to the Attribute Table. + * + * @note It is currently only possible to add a characteristic to the last added service (i.e. only sequential population is supported at this time). + * + * @note Several restrictions apply to the parameters, such as matching permissions between the user description descriptor and the writable auxiliaries bits, + * readable (no security) and writable (selectable) CCCDs and SCCDs and valid presentation format values. + * + * @note If no metadata is provided for the optional descriptors, their permissions will be derived from the characteristic permissions. + * + * @mscs + * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC} + * @endmscs + * + * @param[in] service_handle Handle of the service where the characteristic is to be placed, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially. + * @param[in] p_char_md Characteristic metadata. + * @param[in] p_attr_char_value Pointer to the attribute structure corresponding to the characteristic value. + * @param[out] p_handles Pointer to the structure where the assigned handles will be stored. + * + * @retval ::NRF_SUCCESS Successfully added a characteristic. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, service handle, Vendor Specific UUIDs, lengths, and permissions need to adhere to the constraints. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation, a service context is required. + * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack. + * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. + * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX. + */ +SVCALL(SD_BLE_GATTS_CHARACTERISTIC_ADD, uint32_t, sd_ble_gatts_characteristic_add(uint16_t service_handle, ble_gatts_char_md_t const *p_char_md, ble_gatts_attr_t const *p_attr_char_value, ble_gatts_char_handles_t *p_handles)); + + +/**@brief Add a descriptor to the Attribute Table. + * + * @note It is currently only possible to add a descriptor to the last added characteristic (i.e. only sequential population is supported at this time). + * + * @mscs + * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC} + * @endmscs + * + * @param[in] char_handle Handle of the characteristic where the descriptor is to be placed, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially. + * @param[in] p_attr Pointer to the attribute structure. + * @param[out] p_handle Pointer to a 16-bit word where the assigned handle will be stored. + * + * @retval ::NRF_SUCCESS Successfully added a descriptor. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, characteristic handle, Vendor Specific UUIDs, lengths, and permissions need to adhere to the constraints. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation, a characteristic context is required. + * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack. + * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. + * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX. + */ +SVCALL(SD_BLE_GATTS_DESCRIPTOR_ADD, uint32_t, sd_ble_gatts_descriptor_add(uint16_t char_handle, ble_gatts_attr_t const *p_attr, uint16_t *p_handle)); + +/**@brief Set the value of a given attribute. + * + * @note Values other than system attributes can be set at any time, regardless of whether any active connections exist. + * + * @mscs + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_QUEUE_FULL_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_NOAUTH_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. Ignored if the value does not belong to a system attribute. + * @param[in] handle Attribute handle. + * @param[in,out] p_value Attribute value information. + * + * @retval ::NRF_SUCCESS Successfully set the value of the attribute. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_NOT_FOUND Attribute not found. + * @retval ::NRF_ERROR_FORBIDDEN Forbidden handle supplied, certain attributes are not modifiable by the application. + * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied on a system attribute. + */ +SVCALL(SD_BLE_GATTS_VALUE_SET, uint32_t, sd_ble_gatts_value_set(uint16_t conn_handle, uint16_t handle, ble_gatts_value_t *p_value)); + +/**@brief Get the value of a given attribute. + * + * @note If the attribute value is longer than the size of the supplied buffer, + * @ref ble_gatts_value_t::len will return the total attribute value length (excluding offset), + * and not the number of bytes actually returned in @ref ble_gatts_value_t::p_value. + * The application may use this information to allocate a suitable buffer size. + * + * @note When retrieving system attribute values with this function, the connection handle + * may refer to an already disconnected connection. Refer to the documentation of + * @ref sd_ble_gatts_sys_attr_get for further information. + * + * @param[in] conn_handle Connection handle. Ignored if the value does not belong to a system attribute. + * @param[in] handle Attribute handle. + * @param[in,out] p_value Attribute value information. + * + * @retval ::NRF_SUCCESS Successfully retrieved the value of the attribute. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_NOT_FOUND Attribute not found. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid attribute offset supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied on a system attribute. + * @retval ::BLE_ERROR_GATTS_SYS_ATTR_MISSING System attributes missing, use @ref sd_ble_gatts_sys_attr_set to set them to a known value. + */ +SVCALL(SD_BLE_GATTS_VALUE_GET, uint32_t, sd_ble_gatts_value_get(uint16_t conn_handle, uint16_t handle, ble_gatts_value_t *p_value)); + +/**@brief Notify or Indicate an attribute value. + * + * @details This function checks for the relevant Client Characteristic Configuration descriptor value to verify that the relevant operation + * (notification or indication) has been enabled by the client. It is also able to update the attribute value before issuing the PDU, so that + * the application can atomically perform a value update and a server initiated transaction with a single API call. + * + * @note The local attribute value may be updated even if an outgoing packet is not sent to the peer due to an error during execution. + * The Attribute Table has been updated if one of the following error codes is returned: @ref NRF_ERROR_INVALID_STATE, @ref NRF_ERROR_BUSY, + * @ref NRF_ERROR_FORBIDDEN, @ref BLE_ERROR_GATTS_SYS_ATTR_MISSING and @ref NRF_ERROR_RESOURCES. + * The caller can check whether the value has been updated by looking at the contents of *(@ref ble_gatts_hvx_params_t::p_len). + * + * @note Only one indication procedure can be ongoing per connection at a time. + * If the application tries to indicate an attribute value while another indication procedure is ongoing, + * the function call will return @ref NRF_ERROR_BUSY. + * A @ref BLE_GATTS_EVT_HVC event will be issued as soon as the confirmation arrives from the peer. + * + * @note The number of Handle Value Notifications that can be queued is configured by @ref ble_gatts_conn_cfg_t::hvn_tx_queue_size + * When the queue is full, the function call will return @ref NRF_ERROR_RESOURCES. + * A @ref BLE_GATTS_EVT_HVN_TX_COMPLETE event will be issued as soon as the transmission of the notification is complete. + * + * @note The application can keep track of the available queue element count for notifications by following the procedure below: + * - Store initial queue element count in a variable. + * - Decrement the variable, which stores the currently available queue element count, by one when a call to this function returns @ref NRF_SUCCESS. + * - Increment the variable, which stores the current available queue element count, by the count variable in @ref BLE_GATTS_EVT_HVN_TX_COMPLETE event. + * + * @events + * @event{@ref BLE_GATTS_EVT_HVN_TX_COMPLETE, Notification transmission complete.} + * @event{@ref BLE_GATTS_EVT_HVC, Confirmation received from the peer.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTS_HVX_SYS_ATTRS_MISSING_MSC} + * @mmsc{@ref BLE_GATTS_HVN_MSC} + * @mmsc{@ref BLE_GATTS_HVI_MSC} + * @mmsc{@ref BLE_GATTS_HVX_DISABLED_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in,out] p_hvx_params Pointer to an HVx parameters structure. If @ref ble_gatts_hvx_params_t::p_data + * contains a non-NULL pointer the attribute value will be updated with the contents + * pointed by it before sending the notification or indication. If the attribute value + * is updated, @ref ble_gatts_hvx_params_t::p_len is updated by the SoftDevice to + * contain the number of actual bytes written, else it will be set to 0. + * + * @retval ::NRF_SUCCESS Successfully queued a notification or indication for transmission, and optionally updated the attribute value. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE One or more of the following is true: + * - Invalid Connection State + * - Notifications and/or indications not enabled in the CCCD + * - An ATT_MTU exchange is ongoing + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle(s) supplied. Only attributes added directly by the application are available to notify and indicate. + * @retval ::BLE_ERROR_GATTS_INVALID_ATTR_TYPE Invalid attribute type(s) supplied, only characteristic values may be notified and indicated. + * @retval ::NRF_ERROR_NOT_FOUND Attribute not found. + * @retval ::NRF_ERROR_FORBIDDEN The connection's current security level is lower than the one required by the write permissions of the CCCD associated with this characteristic. + * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied. + * @retval ::NRF_ERROR_BUSY For @ref BLE_GATT_HVX_INDICATION Procedure already in progress. Wait for a @ref BLE_GATTS_EVT_HVC event and retry. + * @retval ::BLE_ERROR_GATTS_SYS_ATTR_MISSING System attributes missing, use @ref sd_ble_gatts_sys_attr_set to set them to a known value. + * @retval ::NRF_ERROR_RESOURCES Too many notifications queued. + * Wait for a @ref BLE_GATTS_EVT_HVN_TX_COMPLETE event and retry. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTS_HVX, uint32_t, sd_ble_gatts_hvx(uint16_t conn_handle, ble_gatts_hvx_params_t const *p_hvx_params)); + +/**@brief Indicate the Service Changed attribute value. + * + * @details This call will send a Handle Value Indication to one or more peers connected to inform them that the Attribute + * Table layout has changed. As soon as the peer has confirmed the indication, a @ref BLE_GATTS_EVT_SC_CONFIRM event will + * be issued. + * + * @note Some of the restrictions and limitations that apply to @ref sd_ble_gatts_hvx also apply here. + * + * @events + * @event{@ref BLE_GATTS_EVT_SC_CONFIRM, Confirmation of attribute table change received from peer.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTS_SC_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] start_handle Start of affected attribute handle range. + * @param[in] end_handle End of affected attribute handle range. + * + * @retval ::NRF_SUCCESS Successfully queued the Service Changed indication for transmission. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_NOT_SUPPORTED Service Changed not enabled at initialization. See @ref + * sd_ble_cfg_set and @ref ble_gatts_cfg_service_changed_t. + * @retval ::NRF_ERROR_INVALID_STATE One or more of the following is true: + * - Invalid Connection State + * - Notifications and/or indications not enabled in the CCCD + * - An ATT_MTU exchange is ongoing + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle(s) supplied, handles must be in the range populated by the application. + * @retval ::NRF_ERROR_BUSY Procedure already in progress. + * @retval ::BLE_ERROR_GATTS_SYS_ATTR_MISSING System attributes missing, use @ref sd_ble_gatts_sys_attr_set to set them to a known value. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTS_SERVICE_CHANGED, uint32_t, sd_ble_gatts_service_changed(uint16_t conn_handle, uint16_t start_handle, uint16_t end_handle)); + +/**@brief Respond to a Read/Write authorization request. + * + * @note This call should only be used as a response to a @ref BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST event issued to the application. + * + * @mscs + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_AUTH_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_BUF_AUTH_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_NOAUTH_MSC} + * @mmsc{@ref BLE_GATTS_READ_REQ_AUTH_MSC} + * @mmsc{@ref BLE_GATTS_WRITE_REQ_AUTH_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_QUEUE_FULL_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_PEER_CANCEL_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] p_rw_authorize_reply_params Pointer to a structure with the attribute provided by the application. + * + * @note @ref ble_gatts_authorize_params_t::p_data is ignored when this function is used to respond + * to a @ref BLE_GATTS_AUTHORIZE_TYPE_READ event if @ref ble_gatts_authorize_params_t::update + * is set to 0. + * + * @retval ::NRF_SUCCESS Successfully queued a response to the peer, and in the case of a write operation, Attribute Table updated. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State or no authorization request pending. + * @retval ::NRF_ERROR_INVALID_PARAM Authorization op invalid, + * handle supplied does not match requested handle, + * or invalid data to be written provided by the application. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTS_RW_AUTHORIZE_REPLY, uint32_t, sd_ble_gatts_rw_authorize_reply(uint16_t conn_handle, ble_gatts_rw_authorize_reply_params_t const *p_rw_authorize_reply_params)); + + +/**@brief Update persistent system attribute information. + * + * @details Supply information about persistent system attributes to the stack, + * previously obtained using @ref sd_ble_gatts_sys_attr_get. + * This call is only allowed for active connections, and is usually + * made immediately after a connection is established with an known bonded device, + * often as a response to a @ref BLE_GATTS_EVT_SYS_ATTR_MISSING. + * + * p_sysattrs may point directly to the application's stored copy of the system attributes + * obtained using @ref sd_ble_gatts_sys_attr_get. + * If the pointer is NULL, the system attribute info is initialized, assuming that + * the application does not have any previously saved system attribute data for this device. + * + * @note The state of persistent system attributes is reset upon connection establishment and then remembered for its duration. + * + * @note If this call returns with an error code different from @ref NRF_SUCCESS, the storage of persistent system attributes may have been completed only partially. + * This means that the state of the attribute table is undefined, and the application should either provide a new set of attributes using this same call or + * reset the SoftDevice to return to a known state. + * + * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS is used with this function, only the system attributes included in system services will be modified. + * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS is used with this function, only the system attributes included in user services will be modified. + * + * @mscs + * @mmsc{@ref BLE_GATTS_HVX_SYS_ATTRS_MISSING_MSC} + * @mmsc{@ref BLE_GATTS_SYS_ATTRS_UNK_PEER_MSC} + * @mmsc{@ref BLE_GATTS_SYS_ATTRS_BONDED_PEER_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] p_sys_attr_data Pointer to a saved copy of system attributes supplied to the stack, or NULL. + * @param[in] len Size of data pointed by p_sys_attr_data, in octets. + * @param[in] flags Optional additional flags, see @ref BLE_GATTS_SYS_ATTR_FLAGS + * + * @retval ::NRF_SUCCESS Successfully set the system attribute information. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid flags supplied. + * @retval ::NRF_ERROR_INVALID_DATA Invalid data supplied, the data should be exactly the same as retrieved with @ref sd_ble_gatts_sys_attr_get. + * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. + */ +SVCALL(SD_BLE_GATTS_SYS_ATTR_SET, uint32_t, sd_ble_gatts_sys_attr_set(uint16_t conn_handle, uint8_t const *p_sys_attr_data, uint16_t len, uint32_t flags)); + + +/**@brief Retrieve persistent system attribute information from the stack. + * + * @details This call is used to retrieve information about values to be stored persistently by the application + * during the lifetime of a connection or after it has been terminated. When a new connection is established with the same bonded device, + * the system attribute information retrieved with this function should be restored using using @ref sd_ble_gatts_sys_attr_set. + * If retrieved after disconnection, the data should be read before a new connection established. The connection handle for + * the previous, now disconnected, connection will remain valid until a new one is created to allow this API call to refer to it. + * Connection handles belonging to active connections can be used as well, but care should be taken since the system attributes + * may be written to at any time by the peer during a connection's lifetime. + * + * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS is used with this function, only the system attributes included in system services will be returned. + * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS is used with this function, only the system attributes included in user services will be returned. + * + * @mscs + * @mmsc{@ref BLE_GATTS_SYS_ATTRS_BONDED_PEER_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle of the recently terminated connection. + * @param[out] p_sys_attr_data Pointer to a buffer where updated information about system attributes will be filled in. The format of the data is described + * in @ref BLE_GATTS_SYS_ATTRS_FORMAT. NULL can be provided to obtain the length of the data. + * @param[in,out] p_len Size of application buffer if p_sys_attr_data is not NULL. Unconditionally updated to actual length of system attribute data. + * @param[in] flags Optional additional flags, see @ref BLE_GATTS_SYS_ATTR_FLAGS + * + * @retval ::NRF_SUCCESS Successfully retrieved the system attribute information. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid flags supplied. + * @retval ::NRF_ERROR_DATA_SIZE The system attribute information did not fit into the provided buffer. + * @retval ::NRF_ERROR_NOT_FOUND No system attributes found. + */ +SVCALL(SD_BLE_GATTS_SYS_ATTR_GET, uint32_t, sd_ble_gatts_sys_attr_get(uint16_t conn_handle, uint8_t *p_sys_attr_data, uint16_t *p_len, uint32_t flags)); + + +/**@brief Retrieve the first valid user attribute handle. + * + * @param[out] p_handle Pointer to an integer where the handle will be stored. + * + * @retval ::NRF_SUCCESS Successfully retrieved the handle. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + */ +SVCALL(SD_BLE_GATTS_INITIAL_USER_HANDLE_GET, uint32_t, sd_ble_gatts_initial_user_handle_get(uint16_t *p_handle)); + +/**@brief Retrieve the attribute UUID and/or metadata. + * + * @param[in] handle Attribute handle + * @param[out] p_uuid UUID of the attribute. Use NULL to omit this field. + * @param[out] p_md Metadata of the attribute. Use NULL to omit this field. + * + * @retval ::NRF_SUCCESS Successfully retrieved the attribute metadata, + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameters supplied. Returned when both @c p_uuid and @c p_md are NULL. + * @retval ::NRF_ERROR_NOT_FOUND Attribute was not found. + */ +SVCALL(SD_BLE_GATTS_ATTR_GET, uint32_t, sd_ble_gatts_attr_get(uint16_t handle, ble_uuid_t * p_uuid, ble_gatts_attr_md_t * p_md)); + +/**@brief Reply to an ATT_MTU exchange request by sending an Exchange MTU Response to the client. + * + * @details This function is only used to reply to a @ref BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST event. + * + * @details The SoftDevice sets ATT_MTU to the minimum of: + * - The Client RX MTU value from @ref BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST, and + * - The Server RX MTU value. + * + * However, the SoftDevice never sets ATT_MTU lower than @ref BLE_GATT_ATT_MTU_DEFAULT. + * + * @mscs + * @mmsc{@ref BLE_GATTS_MTU_EXCHANGE} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] server_rx_mtu Server RX MTU size. + * - The minimum value is @ref BLE_GATT_ATT_MTU_DEFAULT. + * - The maximum value is @ref ble_gatt_conn_cfg_t::att_mtu in the connection configuration + * used for this connection. + * - The value must be equal to Client RX MTU size given in @ref sd_ble_gattc_exchange_mtu_request + * if an ATT_MTU exchange has already been performed in the other direction. + * + * @retval ::NRF_SUCCESS Successfully sent response to the client. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State or no ATT_MTU exchange request pending. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid Server RX MTU size supplied. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTS_EXCHANGE_MTU_REPLY, uint32_t, sd_ble_gatts_exchange_mtu_reply(uint16_t conn_handle, uint16_t server_rx_mtu)); +/** @} */ + +#ifdef __cplusplus +} +#endif +#endif // BLE_GATTS_H__ + +/** + @} +*/ diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_hci.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_hci.h new file mode 100755 index 00000000..f0dde9a0 --- /dev/null +++ b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_hci.h @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2012 - 2017, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_COMMON + @{ +*/ + + +#ifndef BLE_HCI_H__ +#define BLE_HCI_H__ +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup BLE_HCI_STATUS_CODES Bluetooth status codes + * @{ */ + +#define BLE_HCI_STATUS_CODE_SUCCESS 0x00 /**< Success. */ +#define BLE_HCI_STATUS_CODE_UNKNOWN_BTLE_COMMAND 0x01 /**< Unknown BLE Command. */ +#define BLE_HCI_STATUS_CODE_UNKNOWN_CONNECTION_IDENTIFIER 0x02 /**< Unknown Connection Identifier. */ +/*0x03 Hardware Failure +0x04 Page Timeout +*/ +#define BLE_HCI_AUTHENTICATION_FAILURE 0x05 /**< Authentication Failure. */ +#define BLE_HCI_STATUS_CODE_PIN_OR_KEY_MISSING 0x06 /**< Pin or Key missing. */ +#define BLE_HCI_MEMORY_CAPACITY_EXCEEDED 0x07 /**< Memory Capacity Exceeded. */ +#define BLE_HCI_CONNECTION_TIMEOUT 0x08 /**< Connection Timeout. */ +/*0x09 Connection Limit Exceeded +0x0A Synchronous Connection Limit To A Device Exceeded +0x0B ACL Connection Already Exists*/ +#define BLE_HCI_STATUS_CODE_COMMAND_DISALLOWED 0x0C /**< Command Disallowed. */ +/*0x0D Connection Rejected due to Limited Resources +0x0E Connection Rejected Due To Security Reasons +0x0F Connection Rejected due to Unacceptable BD_ADDR +0x10 Connection Accept Timeout Exceeded +0x11 Unsupported Feature or Parameter Value*/ +#define BLE_HCI_STATUS_CODE_INVALID_BTLE_COMMAND_PARAMETERS 0x12 /**< Invalid BLE Command Parameters. */ +#define BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION 0x13 /**< Remote User Terminated Connection. */ +#define BLE_HCI_REMOTE_DEV_TERMINATION_DUE_TO_LOW_RESOURCES 0x14 /**< Remote Device Terminated Connection due to low resources.*/ +#define BLE_HCI_REMOTE_DEV_TERMINATION_DUE_TO_POWER_OFF 0x15 /**< Remote Device Terminated Connection due to power off. */ +#define BLE_HCI_LOCAL_HOST_TERMINATED_CONNECTION 0x16 /**< Local Host Terminated Connection. */ +/* +0x17 Repeated Attempts +0x18 Pairing Not Allowed +0x19 Unknown LMP PDU +*/ +#define BLE_HCI_UNSUPPORTED_REMOTE_FEATURE 0x1A /**< Unsupported Remote Feature. */ +/* +0x1B SCO Offset Rejected +0x1C SCO Interval Rejected +0x1D SCO Air Mode Rejected*/ +#define BLE_HCI_STATUS_CODE_INVALID_LMP_PARAMETERS 0x1E /**< Invalid LMP Parameters. */ +#define BLE_HCI_STATUS_CODE_UNSPECIFIED_ERROR 0x1F /**< Unspecified Error. */ +/*0x20 Unsupported LMP Parameter Value +0x21 Role Change Not Allowed +*/ +#define BLE_HCI_STATUS_CODE_LMP_RESPONSE_TIMEOUT 0x22 /**< LMP Response Timeout. */ +#define BLE_HCI_STATUS_CODE_LMP_ERROR_TRANSACTION_COLLISION 0x23 /**< LMP Error Transaction Collision/LL Procedure Collision. */ +#define BLE_HCI_STATUS_CODE_LMP_PDU_NOT_ALLOWED 0x24 /**< LMP PDU Not Allowed. */ +/*0x25 Encryption Mode Not Acceptable +0x26 Link Key Can Not be Changed +0x27 Requested QoS Not Supported +*/ +#define BLE_HCI_INSTANT_PASSED 0x28 /**< Instant Passed. */ +#define BLE_HCI_PAIRING_WITH_UNIT_KEY_UNSUPPORTED 0x29 /**< Pairing with Unit Key Unsupported. */ +#define BLE_HCI_DIFFERENT_TRANSACTION_COLLISION 0x2A /**< Different Transaction Collision. */ +/* +0x2B Reserved +0x2C QoS Unacceptable Parameter +0x2D QoS Rejected +0x2E Channel Classification Not Supported +0x2F Insufficient Security +*/ +#define BLE_HCI_PARAMETER_OUT_OF_MANDATORY_RANGE 0x30 /**< Parameter Out Of Mandatory Range. */ +/* +0x31 Reserved +0x32 Role Switch Pending +0x33 Reserved +0x34 Reserved Slot Violation +0x35 Role Switch Failed +0x36 Extended Inquiry Response Too Large +0x37 Secure Simple Pairing Not Supported By Host. +0x38 Host Busy - Pairing +0x39 Connection Rejected due to No Suitable Channel Found*/ +#define BLE_HCI_CONTROLLER_BUSY 0x3A /**< Controller Busy. */ +#define BLE_HCI_CONN_INTERVAL_UNACCEPTABLE 0x3B /**< Connection Interval Unacceptable. */ +#define BLE_HCI_DIRECTED_ADVERTISER_TIMEOUT 0x3C /**< Directed Advertisement Timeout. */ +#define BLE_HCI_CONN_TERMINATED_DUE_TO_MIC_FAILURE 0x3D /**< Connection Terminated due to MIC Failure. */ +#define BLE_HCI_CONN_FAILED_TO_BE_ESTABLISHED 0x3E /**< Connection Failed to be Established. */ + +/** @} */ + + +#ifdef __cplusplus +} +#endif +#endif // BLE_HCI_H__ + +/** @} */ diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_l2cap.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_l2cap.h new file mode 100755 index 00000000..edaf6641 --- /dev/null +++ b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_l2cap.h @@ -0,0 +1,506 @@ +/* + * Copyright (c) 2011 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_L2CAP Logical Link Control and Adaptation Protocol (L2CAP) + @{ + @brief Definitions and prototypes for the L2CAP interface. + */ + +#ifndef BLE_L2CAP_H__ +#define BLE_L2CAP_H__ + +#include <stdint.h> +#include "nrf_svc.h" +#include "nrf_error.h" +#include "ble_ranges.h" +#include "ble_types.h" +#include "ble_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/**@addtogroup BLE_L2CAP_TERMINOLOGY Terminology + * @{ + * @details + * + * L2CAP SDU + * - A data unit that the application can send/receive to/from a peer. + * + * L2CAP PDU + * - A data unit that is exchanged between local and remote L2CAP entities. + * It consists of L2CAP protocol control information and payload fields. + * The payload field can contain an L2CAP SDU or a part of an L2CAP SDU. + * + * L2CAP MTU + * - The maximum length of an L2CAP SDU. + * + * L2CAP MPS + * - The maximum length of an L2CAP PDU payload field. + * + * Credits + * - A value indicating the number of L2CAP PDUs that the receiver of the credit can send to the peer. + * @} */ + +/**@addtogroup BLE_L2CAP_ENUMERATIONS Enumerations + * @{ */ + +/**@brief L2CAP API SVC numbers. */ +enum BLE_L2CAP_SVCS +{ + SD_BLE_L2CAP_CH_SETUP = BLE_L2CAP_SVC_BASE + 0, /**< Set up an L2CAP channel. */ + SD_BLE_L2CAP_CH_RELEASE = BLE_L2CAP_SVC_BASE + 1, /**< Release an L2CAP channel. */ + SD_BLE_L2CAP_CH_RX = BLE_L2CAP_SVC_BASE + 2, /**< Receive an SDU on an L2CAP channel. */ + SD_BLE_L2CAP_CH_TX = BLE_L2CAP_SVC_BASE + 3, /**< Transmit an SDU on an L2CAP channel. */ + SD_BLE_L2CAP_CH_FLOW_CONTROL = BLE_L2CAP_SVC_BASE + 4, /**< Advanced SDU reception flow control. */ +}; + +/**@brief L2CAP Event IDs. */ +enum BLE_L2CAP_EVTS +{ + BLE_L2CAP_EVT_CH_SETUP_REQUEST = BLE_L2CAP_EVT_BASE + 0, /**< L2CAP Channel Setup Request event. + \n See @ref ble_l2cap_evt_ch_setup_request_t. */ + BLE_L2CAP_EVT_CH_SETUP_REFUSED = BLE_L2CAP_EVT_BASE + 1, /**< L2CAP Channel Setup Refused event. + \n See @ref ble_l2cap_evt_ch_setup_refused_t. */ + BLE_L2CAP_EVT_CH_SETUP = BLE_L2CAP_EVT_BASE + 2, /**< L2CAP Channel Setup Completed event. + \n See @ref ble_l2cap_evt_ch_setup_t. */ + BLE_L2CAP_EVT_CH_RELEASED = BLE_L2CAP_EVT_BASE + 3, /**< L2CAP Channel Released event. + \n No additional event structure applies. */ + BLE_L2CAP_EVT_CH_SDU_BUF_RELEASED = BLE_L2CAP_EVT_BASE + 4, /**< L2CAP Channel SDU data buffer released event. + \n See @ref ble_l2cap_evt_ch_sdu_buf_released_t. */ + BLE_L2CAP_EVT_CH_CREDIT = BLE_L2CAP_EVT_BASE + 5, /**< L2CAP Channel Credit received. + \n See @ref ble_l2cap_evt_ch_credit_t. */ + BLE_L2CAP_EVT_CH_RX = BLE_L2CAP_EVT_BASE + 6, /**< L2CAP Channel SDU received. + \n See @ref ble_l2cap_evt_ch_rx_t. */ + BLE_L2CAP_EVT_CH_TX = BLE_L2CAP_EVT_BASE + 7, /**< L2CAP Channel SDU transmitted. + \n See @ref ble_l2cap_evt_ch_tx_t. */ +}; + +/** @} */ + +/**@addtogroup BLE_L2CAP_DEFINES Defines + * @{ */ + +/**@brief Maximum number of L2CAP channels per connection. */ +#define BLE_L2CAP_CH_COUNT_MAX (64) + +/**@brief Minimum L2CAP MTU, in bytes. */ +#define BLE_L2CAP_MTU_MIN (23) + +/**@brief Minimum L2CAP MPS, in bytes. */ +#define BLE_L2CAP_MPS_MIN (23) + +/**@brief Invalid CID. */ +#define BLE_L2CAP_CID_INVALID (0x0000) + +/**@brief Default number of credits for @ref sd_ble_l2cap_ch_flow_control. */ +#define BLE_L2CAP_CREDITS_DEFAULT (1) + +/**@defgroup BLE_L2CAP_CH_SETUP_REFUSED_SRCS L2CAP channel setup refused sources + * @{ */ +#define BLE_L2CAP_CH_SETUP_REFUSED_SRC_LOCAL (0x01) /**< Local. */ +#define BLE_L2CAP_CH_SETUP_REFUSED_SRC_REMOTE (0x02) /**< Remote. */ + /** @} */ + + /** @defgroup BLE_L2CAP_CH_STATUS_CODES L2CAP channel status codes + * @{ */ +#define BLE_L2CAP_CH_STATUS_CODE_SUCCESS (0x0000) /**< Success. */ +#define BLE_L2CAP_CH_STATUS_CODE_LE_PSM_NOT_SUPPORTED (0x0002) /**< LE_PSM not supported. */ +#define BLE_L2CAP_CH_STATUS_CODE_NO_RESOURCES (0x0004) /**< No resources available. */ +#define BLE_L2CAP_CH_STATUS_CODE_INSUFF_AUTHENTICATION (0x0005) /**< Insufficient authentication. */ +#define BLE_L2CAP_CH_STATUS_CODE_INSUFF_AUTHORIZATION (0x0006) /**< Insufficient authorization. */ +#define BLE_L2CAP_CH_STATUS_CODE_INSUFF_ENC_KEY_SIZE (0x0007) /**< Insufficient encryption key size. */ +#define BLE_L2CAP_CH_STATUS_CODE_INSUFF_ENC (0x0008) /**< Insufficient encryption. */ +#define BLE_L2CAP_CH_STATUS_CODE_INVALID_SCID (0x0009) /**< Invalid Source CID. */ +#define BLE_L2CAP_CH_STATUS_CODE_SCID_ALLOCATED (0x000A) /**< Source CID already allocated. */ +#define BLE_L2CAP_CH_STATUS_CODE_UNACCEPTABLE_PARAMS (0x000B) /**< Unacceptable parameters. */ +#define BLE_L2CAP_CH_STATUS_CODE_NOT_UNDERSTOOD (0x8000) /**< Command Reject received instead of LE Credit Based Connection Response. */ +#define BLE_L2CAP_CH_STATUS_CODE_TIMEOUT (0xC000) /**< Operation timed out. */ +/** @} */ + +/** @} */ + +/**@addtogroup BLE_L2CAP_STRUCTURES Structures + * @{ */ + +/** + * @brief BLE L2CAP connection configuration parameters, set with @ref sd_ble_cfg_set. + * + * @note These parameters are set per connection, so all L2CAP channels created on this connection + * will have the same parameters. + * + * @retval ::NRF_ERROR_INVALID_PARAM One or more of the following is true: + * - rx_mps is smaller than @ref BLE_L2CAP_MPS_MIN. + * - tx_mps is smaller than @ref BLE_L2CAP_MPS_MIN. + * - ch_count is greater than @ref BLE_L2CAP_CH_COUNT_MAX. + * @retval ::NRF_ERROR_NO_MEM rx_mps or tx_mps is set too high. + */ +typedef struct +{ + uint16_t rx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP shall + be able to receive on L2CAP channels on connections with this + configuration. The minimum value is @ref BLE_L2CAP_MPS_MIN. */ + uint16_t tx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP shall + be able to transmit on L2CAP channels on connections with this + configuration. The minimum value is @ref BLE_L2CAP_MPS_MIN. */ + uint8_t rx_queue_size; /**< Number of SDU data buffers that can be queued for reception per + L2CAP channel. The minimum value is one. */ + uint8_t tx_queue_size; /**< Number of SDU data buffers that can be queued for transmission + per L2CAP channel. The minimum value is one. */ + uint8_t ch_count; /**< Number of L2CAP channels the application can create per connection + with this configuration. The default value is zero, the maximum + value is @ref BLE_L2CAP_CH_COUNT_MAX. + @note if this parameter is set to zero, all other parameters in + @ref ble_l2cap_conn_cfg_t are ignored. */ +} ble_l2cap_conn_cfg_t; + +/**@brief L2CAP channel RX parameters. */ +typedef struct +{ + uint16_t rx_mtu; /**< The maximum L2CAP SDU size, in bytes, that L2CAP shall be able to + receive on this L2CAP channel. + - Must be equal to or greater than @ref BLE_L2CAP_MTU_MIN. */ + uint16_t rx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP shall be + able to receive on this L2CAP channel. + - Must be equal to or greater than @ref BLE_L2CAP_MPS_MIN. + - Must be equal to or less than @ref ble_l2cap_conn_cfg_t::rx_mps. */ + ble_data_t sdu_buf; /**< SDU data buffer for reception. + - If @ref ble_data_t::p_data is non-NULL, initial credits are + issued to the peer. + - If @ref ble_data_t::p_data is NULL, no initial credits are + issued to the peer. */ +} ble_l2cap_ch_rx_params_t; + +/**@brief L2CAP channel setup parameters. */ +typedef struct +{ + ble_l2cap_ch_rx_params_t rx_params; /**< L2CAP channel RX parameters. */ + uint16_t le_psm; /**< LE Protocol/Service Multiplexer. Used when requesting + setup of an L2CAP channel, ignored otherwise. */ + uint16_t status; /**< Status code, see @ref BLE_L2CAP_CH_STATUS_CODES. + Used when replying to a setup request of an L2CAP + channel, ignored otherwise. */ +} ble_l2cap_ch_setup_params_t; + +/**@brief L2CAP channel TX parameters. */ +typedef struct +{ + uint16_t tx_mtu; /**< The maximum L2CAP SDU size, in bytes, that L2CAP is able to + transmit on this L2CAP channel. */ + uint16_t peer_mps; /**< The maximum L2CAP PDU payload size, in bytes, that the peer is + able to receive on this L2CAP channel. */ + uint16_t tx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP is able + to transmit on this L2CAP channel. This is effective tx_mps, + selected by the SoftDevice as + MIN( @ref ble_l2cap_ch_tx_params_t::peer_mps, @ref ble_l2cap_conn_cfg_t::tx_mps ) */ + uint16_t credits; /**< Initial credits given by the peer. */ +} ble_l2cap_ch_tx_params_t; + +/**@brief L2CAP Channel Setup Request event. */ +typedef struct +{ + ble_l2cap_ch_tx_params_t tx_params; /**< L2CAP channel TX parameters. */ + uint16_t le_psm; /**< LE Protocol/Service Multiplexer. */ +} ble_l2cap_evt_ch_setup_request_t; + +/**@brief L2CAP Channel Setup Refused event. */ +typedef struct +{ + uint8_t source; /**< Source, see @ref BLE_L2CAP_CH_SETUP_REFUSED_SRCS */ + uint16_t status; /**< Status code, see @ref BLE_L2CAP_CH_STATUS_CODES */ +} ble_l2cap_evt_ch_setup_refused_t; + +/**@brief L2CAP Channel Setup Completed event. */ +typedef struct +{ + ble_l2cap_ch_tx_params_t tx_params; /**< L2CAP channel TX parameters. */ +} ble_l2cap_evt_ch_setup_t; + +/**@brief L2CAP Channel SDU Data Buffer Released event. */ +typedef struct +{ + ble_data_t sdu_buf; /**< Returned reception or transmission SDU data buffer. The SoftDevice + returns SDU data buffers supplied by the application, which have + not yet been returned previously via a @ref BLE_L2CAP_EVT_CH_RX or + @ref BLE_L2CAP_EVT_CH_TX event. */ +} ble_l2cap_evt_ch_sdu_buf_released_t; + +/**@brief L2CAP Channel Credit received event. */ +typedef struct +{ + uint16_t credits; /**< Additional credits given by the peer. */ +} ble_l2cap_evt_ch_credit_t; + +/**@brief L2CAP Channel received SDU event. */ +typedef struct +{ + uint16_t sdu_len; /**< Total SDU length, in bytes. */ + ble_data_t sdu_buf; /**< SDU data buffer. + @note If there is not enough space in the buffer + (sdu_buf.len < sdu_len) then the rest of the SDU will be + silently discarded by the SoftDevice. */ +} ble_l2cap_evt_ch_rx_t; + +/**@brief L2CAP Channel transmitted SDU event. */ +typedef struct +{ + ble_data_t sdu_buf; /**< SDU data buffer. */ +} ble_l2cap_evt_ch_tx_t; + +/**@brief L2CAP event structure. */ +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle on which the event occured. */ + uint16_t local_cid; /**< Local Channel ID of the L2CAP channel, or + @ref BLE_L2CAP_CID_INVALID if not present. */ + union + { + ble_l2cap_evt_ch_setup_request_t ch_setup_request; /**< L2CAP Channel Setup Request Event Parameters. */ + ble_l2cap_evt_ch_setup_refused_t ch_setup_refused; /**< L2CAP Channel Setup Refused Event Parameters. */ + ble_l2cap_evt_ch_setup_t ch_setup; /**< L2CAP Channel Setup Completed Event Parameters. */ + ble_l2cap_evt_ch_sdu_buf_released_t ch_sdu_buf_released;/**< L2CAP Channel SDU Data Buffer Released Event Parameters. */ + ble_l2cap_evt_ch_credit_t credit; /**< L2CAP Channel Credit Received Event Parameters. */ + ble_l2cap_evt_ch_rx_t rx; /**< L2CAP Channel SDU Received Event Parameters. */ + ble_l2cap_evt_ch_tx_t tx; /**< L2CAP Channel SDU Transmitted Event Parameters. */ + } params; /**< Event Parameters. */ +} ble_l2cap_evt_t; + +/** @} */ + +/**@addtogroup BLE_L2CAP_FUNCTIONS Functions + * @{ */ + +/**@brief Set up an L2CAP channel. + * + * @details This function is used to: + * - Request setup of an L2CAP channel: sends an LE Credit Based Connection Request packet to a peer. + * - Reply to a setup request of an L2CAP channel (if called in response to a + * @ref BLE_L2CAP_EVT_CH_SETUP_REQUEST event): sends an LE Credit Based Connection + * Response packet to a peer. + * + * @note A call to this function will require the application to keep the SDU data buffer alive + * until the SDU data buffer is returned in @ref BLE_L2CAP_EVT_CH_RX or + * @ref BLE_L2CAP_EVT_CH_SDU_BUF_RELEASED event. + * + * @events + * @event{@ref BLE_L2CAP_EVT_CH_SETUP, Setup successful.} + * @event{@ref BLE_L2CAP_EVT_CH_SETUP_REFUSED, Setup failed.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_L2CAP_CH_SETUP_MSC} + * @endmscs + * + * @param[in] conn_handle Connection Handle. + * @param[in,out] p_local_cid Pointer to a uint16_t containing Local Channel ID of the L2CAP channel: + * - As input: @ref BLE_L2CAP_CID_INVALID when requesting setup of an L2CAP + * channel or local_cid provided in the @ref BLE_L2CAP_EVT_CH_SETUP_REQUEST + * event when replying to a setup request of an L2CAP channel. + * - As output: local_cid for this channel. + * @param[in] p_params L2CAP channel parameters. + * + * @retval ::NRF_SUCCESS Successfully queued request or response for transmission. + * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_INVALID_LENGTH Supplied higher rx_mps than has been configured on this link. + * @retval ::NRF_ERROR_INVALID_STATE Invalid State to perform operation (L2CAP channel already set up). + * @retval ::NRF_ERROR_NOT_FOUND CID not found. + * @retval ::NRF_ERROR_RESOURCES The limit has been reached for available L2CAP channels, + * see @ref ble_l2cap_conn_cfg_t::ch_count. + */ +SVCALL(SD_BLE_L2CAP_CH_SETUP, uint32_t, sd_ble_l2cap_ch_setup(uint16_t conn_handle, uint16_t *p_local_cid, ble_l2cap_ch_setup_params_t const *p_params)); + +/**@brief Release an L2CAP channel. + * + * @details This sends a Disconnection Request packet to a peer. + * + * @events + * @event{@ref BLE_L2CAP_EVT_CH_RELEASED, Release complete.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_L2CAP_CH_RELEASE_MSC} + * @endmscs + * + * @param[in] conn_handle Connection Handle. + * @param[in] local_cid Local Channel ID of the L2CAP channel. + * + * @retval ::NRF_SUCCESS Successfully queued request for transmission. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid State to perform operation (Setup or release is + * in progress for the L2CAP channel). + * @retval ::NRF_ERROR_NOT_FOUND CID not found. + */ +SVCALL(SD_BLE_L2CAP_CH_RELEASE, uint32_t, sd_ble_l2cap_ch_release(uint16_t conn_handle, uint16_t local_cid)); + +/**@brief Receive an SDU on an L2CAP channel. + * + * @details This may issue additional credits to the peer using an LE Flow Control Credit packet. + * + * @note A call to this function will require the application to keep the memory pointed by + * @ref ble_data_t::p_data alive until the SDU data buffer is returned in @ref BLE_L2CAP_EVT_CH_RX + * or @ref BLE_L2CAP_EVT_CH_SDU_BUF_RELEASED event. + * + * @note The SoftDevice can queue up to @ref ble_l2cap_conn_cfg_t::rx_queue_size SDU data buffers + * for reception per L2CAP channel. + * + * @events + * @event{@ref BLE_L2CAP_EVT_CH_RX, The SDU is received.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_L2CAP_CH_RX_MSC} + * @endmscs + * + * @param[in] conn_handle Connection Handle. + * @param[in] local_cid Local Channel ID of the L2CAP channel. + * @param[in] p_sdu_buf Pointer to the SDU data buffer. + * + * @retval ::NRF_SUCCESS Buffer accepted. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid State to perform operation (Setup or release is + * in progress for an L2CAP channel). + * @retval ::NRF_ERROR_NOT_FOUND CID not found. + * @retval ::NRF_ERROR_RESOURCES Too many SDU data buffers supplied. Wait for a + * @ref BLE_L2CAP_EVT_CH_RX event and retry. + */ +SVCALL(SD_BLE_L2CAP_CH_RX, uint32_t, sd_ble_l2cap_ch_rx(uint16_t conn_handle, uint16_t local_cid, ble_data_t const *p_sdu_buf)); + +/**@brief Transmit an SDU on an L2CAP channel. + * + * @note A call to this function will require the application to keep the memory pointed by + * @ref ble_data_t::p_data alive until the SDU data buffer is returned in @ref BLE_L2CAP_EVT_CH_TX + * or @ref BLE_L2CAP_EVT_CH_SDU_BUF_RELEASED event. + * + * @note The SoftDevice can queue up to @ref ble_l2cap_conn_cfg_t::tx_queue_size SDUs for + * transmission per L2CAP channel. + * + * @note The application can keep track of the available credits for transmission by following + * the procedure below: + * - Store initial credits given by the peer in a variable. + * (Initial credits are provided in a @ref BLE_L2CAP_EVT_CH_SETUP event.) + * - Decrement the variable, which stores the currently available credits, by + * ceiling((@ref ble_data_t::len + 2) / tx_mps) when a call to this function returns + * @ref NRF_SUCCESS. (tx_mps is provided in a @ref BLE_L2CAP_EVT_CH_SETUP event.) + * - Increment the variable, which stores the currently available credits, by additional + * credits given by the peer in a @ref BLE_L2CAP_EVT_CH_CREDIT event. + * + * @events + * @event{@ref BLE_L2CAP_EVT_CH_TX, The SDU is transmitted.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_L2CAP_CH_TX_MSC} + * @endmscs + * + * @param[in] conn_handle Connection Handle. + * @param[in] local_cid Local Channel ID of the L2CAP channel. + * @param[in] p_sdu_buf Pointer to the SDU data buffer. + * + * @retval ::NRF_SUCCESS Successfully queued L2CAP SDU for transmission. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid State to perform operation (Setup or release is + * in progress for the L2CAP channel). + * @retval ::NRF_ERROR_NOT_FOUND CID not found. + * @retval ::NRF_ERROR_DATA_SIZE Invalid SDU length supplied, must not be more than + * @ref ble_l2cap_ch_tx_params_t::tx_mtu provided in + * @ref BLE_L2CAP_EVT_CH_SETUP event. + * @retval ::NRF_ERROR_RESOURCES Too many SDUs queued for transmission. Wait for a + * @ref BLE_L2CAP_EVT_CH_TX event and retry. + */ +SVCALL(SD_BLE_L2CAP_CH_TX, uint32_t, sd_ble_l2cap_ch_tx(uint16_t conn_handle, uint16_t local_cid, ble_data_t const *p_sdu_buf)); + +/**@brief Advanced SDU reception flow control. + * + * @details Adjust the way the SoftDevice issues credits to the peer. + * This may issue additional credits to the peer using an LE Flow Control Credit packet. + * + * @mscs + * @mmsc{@ref BLE_L2CAP_CH_FLOW_CONTROL_MSC} + * @endmscs + * + * @param[in] conn_handle Connection Handle. + * @param[in] local_cid Local Channel ID of the L2CAP channel or @ref BLE_L2CAP_CID_INVALID to set + * the value that will be used for newly created channels. + * @param[in] credits Number of credits that the SoftDevice will make sure the peer has every + * time it starts using a new reception buffer. + * - @ref BLE_L2CAP_CREDITS_DEFAULT is the default value the SoftDevice will + * use if this function is not called. + * - If set to zero, the SoftDevice will stop issuing credits for new reception + * buffers the application provides or has provided. SDU reception that is + * currently ongoing will be allowed to complete. + * @param[out] p_credits NULL or pointer to a uint16_t. If a valid pointer is provided, it will be + * written by the SoftDevice with the number of credits that is or will be + * available to the peer. If the value written by the SoftDevice is 0 when + * credits parameter was set to 0, the peer will not be able to send more + * data until more credits are provided by calling this function again with + * credits > 0. This parameter is ignored when local_cid is set to + * @ref BLE_L2CAP_CID_INVALID. + * + * @note Application should take care when setting number of credits higher than default value. In + * this case the application must make sure that the SoftDevice always has reception buffers + * available (see @ref sd_ble_l2cap_ch_rx) for that channel. If the SoftDevice does not have + * such buffers available, packets may be NACKed on the Link Layer and all Bluetooth traffic + * on the connection handle may be stalled until the SoftDevice again has an available + * reception buffer. This applies even if the application has used this call to set the + * credits back to default, or zero. + * + * @retval ::NRF_SUCCESS Flow control parameters accepted. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid State to perform operation (Setup or release is + * in progress for an L2CAP channel). + * @retval ::NRF_ERROR_NOT_FOUND CID not found. + */ +SVCALL(SD_BLE_L2CAP_CH_FLOW_CONTROL, uint32_t, sd_ble_l2cap_ch_flow_control(uint16_t conn_handle, uint16_t local_cid, uint16_t credits, uint16_t *p_credits)); + +/** @} */ + +#ifdef __cplusplus +} +#endif +#endif // BLE_L2CAP_H__ + +/** + @} +*/ diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_ranges.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_ranges.h new file mode 100755 index 00000000..0935bca0 --- /dev/null +++ b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_ranges.h @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_COMMON + @{ + @defgroup ble_ranges Module specific SVC, event and option number subranges + @{ + + @brief Definition of SVC, event and option number subranges for each API module. + + @note + SVCs, event and option numbers are split into subranges for each API module. + Each module receives its entire allocated range of SVC calls, whether implemented or not, + but return BLE_ERROR_NOT_SUPPORTED for unimplemented or undefined calls in its range. + + Note that the symbols BLE_<module>_SVC_LAST is the end of the allocated SVC range, + rather than the last SVC function call actually defined and implemented. + + Specific SVC, event and option values are defined in each module's ble_<module>.h file, + which defines names of each individual SVC code based on the range start value. +*/ + +#ifndef BLE_RANGES_H__ +#define BLE_RANGES_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define BLE_SVC_BASE 0x60 /**< Common BLE SVC base. */ +#define BLE_SVC_LAST 0x6B /**< Common BLE SVC last. */ + +#define BLE_GAP_SVC_BASE 0x6C /**< GAP BLE SVC base. */ +#define BLE_GAP_SVC_LAST 0x9A /**< GAP BLE SVC last. */ + +#define BLE_GATTC_SVC_BASE 0x9B /**< GATTC BLE SVC base. */ +#define BLE_GATTC_SVC_LAST 0xA7 /**< GATTC BLE SVC last. */ + +#define BLE_GATTS_SVC_BASE 0xA8 /**< GATTS BLE SVC base. */ +#define BLE_GATTS_SVC_LAST 0xB7 /**< GATTS BLE SVC last. */ + +#define BLE_L2CAP_SVC_BASE 0xB8 /**< L2CAP BLE SVC base. */ +#define BLE_L2CAP_SVC_LAST 0xBF /**< L2CAP BLE SVC last. */ + + +#define BLE_EVT_INVALID 0x00 /**< Invalid BLE Event. */ + +#define BLE_EVT_BASE 0x01 /**< Common BLE Event base. */ +#define BLE_EVT_LAST 0x0F /**< Common BLE Event last. */ + +#define BLE_GAP_EVT_BASE 0x10 /**< GAP BLE Event base. */ +#define BLE_GAP_EVT_LAST 0x2F /**< GAP BLE Event last. */ + +#define BLE_GATTC_EVT_BASE 0x30 /**< GATTC BLE Event base. */ +#define BLE_GATTC_EVT_LAST 0x4F /**< GATTC BLE Event last. */ + +#define BLE_GATTS_EVT_BASE 0x50 /**< GATTS BLE Event base. */ +#define BLE_GATTS_EVT_LAST 0x6F /**< GATTS BLE Event last. */ + +#define BLE_L2CAP_EVT_BASE 0x70 /**< L2CAP BLE Event base. */ +#define BLE_L2CAP_EVT_LAST 0x8F /**< L2CAP BLE Event last. */ + + +#define BLE_OPT_INVALID 0x00 /**< Invalid BLE Option. */ + +#define BLE_OPT_BASE 0x01 /**< Common BLE Option base. */ +#define BLE_OPT_LAST 0x1F /**< Common BLE Option last. */ + +#define BLE_GAP_OPT_BASE 0x20 /**< GAP BLE Option base. */ +#define BLE_GAP_OPT_LAST 0x3F /**< GAP BLE Option last. */ + +#define BLE_GATT_OPT_BASE 0x40 /**< GATT BLE Option base. */ +#define BLE_GATT_OPT_LAST 0x5F /**< GATT BLE Option last. */ + +#define BLE_GATTC_OPT_BASE 0x60 /**< GATTC BLE Option base. */ +#define BLE_GATTC_OPT_LAST 0x7F /**< GATTC BLE Option last. */ + +#define BLE_GATTS_OPT_BASE 0x80 /**< GATTS BLE Option base. */ +#define BLE_GATTS_OPT_LAST 0x9F /**< GATTS BLE Option last. */ + +#define BLE_L2CAP_OPT_BASE 0xA0 /**< L2CAP BLE Option base. */ +#define BLE_L2CAP_OPT_LAST 0xBF /**< L2CAP BLE Option last. */ + + +#define BLE_CFG_INVALID 0x00 /**< Invalid BLE configuration. */ + +#define BLE_CFG_BASE 0x01 /**< Common BLE configuration base. */ +#define BLE_CFG_LAST 0x1F /**< Common BLE configuration last. */ + +#define BLE_CONN_CFG_BASE 0x20 /**< BLE connection configuration base. */ +#define BLE_CONN_CFG_LAST 0x3F /**< BLE connection configuration last. */ + +#define BLE_GAP_CFG_BASE 0x40 /**< GAP BLE configuration base. */ +#define BLE_GAP_CFG_LAST 0x5F /**< GAP BLE configuration last. */ + +#define BLE_GATT_CFG_BASE 0x60 /**< GATT BLE configuration base. */ +#define BLE_GATT_CFG_LAST 0x7F /**< GATT BLE configuration last. */ + +#define BLE_GATTC_CFG_BASE 0x80 /**< GATTC BLE configuration base. */ +#define BLE_GATTC_CFG_LAST 0x9F /**< GATTC BLE configuration last. */ + +#define BLE_GATTS_CFG_BASE 0xA0 /**< GATTS BLE configuration base. */ +#define BLE_GATTS_CFG_LAST 0xBF /**< GATTS BLE configuration last. */ + +#define BLE_L2CAP_CFG_BASE 0xC0 /**< L2CAP BLE configuration base. */ +#define BLE_L2CAP_CFG_LAST 0xDF /**< L2CAP BLE configuration last. */ + + + + + +#ifdef __cplusplus +} +#endif +#endif /* BLE_RANGES_H__ */ + +/** + @} + @} +*/ diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_types.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_types.h new file mode 100755 index 00000000..88c93180 --- /dev/null +++ b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_types.h @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2012 - 2017, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_COMMON + @{ + @defgroup ble_types Common types and macro definitions + @{ + + @brief Common types and macro definitions for the BLE SoftDevice. + */ + +#ifndef BLE_TYPES_H__ +#define BLE_TYPES_H__ + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup BLE_TYPES_DEFINES Defines + * @{ */ + +/** @defgroup BLE_CONN_HANDLES BLE Connection Handles + * @{ */ +#define BLE_CONN_HANDLE_INVALID 0xFFFF /**< Invalid Connection Handle. */ +#define BLE_CONN_HANDLE_ALL 0xFFFE /**< Applies to all Connection Handles. */ +/** @} */ + + +/** @defgroup BLE_UUID_VALUES Assigned Values for BLE UUIDs + * @{ */ +/* Generic UUIDs, applicable to all services */ +#define BLE_UUID_UNKNOWN 0x0000 /**< Reserved UUID. */ +#define BLE_UUID_SERVICE_PRIMARY 0x2800 /**< Primary Service. */ +#define BLE_UUID_SERVICE_SECONDARY 0x2801 /**< Secondary Service. */ +#define BLE_UUID_SERVICE_INCLUDE 0x2802 /**< Include. */ +#define BLE_UUID_CHARACTERISTIC 0x2803 /**< Characteristic. */ +#define BLE_UUID_DESCRIPTOR_CHAR_EXT_PROP 0x2900 /**< Characteristic Extended Properties Descriptor. */ +#define BLE_UUID_DESCRIPTOR_CHAR_USER_DESC 0x2901 /**< Characteristic User Description Descriptor. */ +#define BLE_UUID_DESCRIPTOR_CLIENT_CHAR_CONFIG 0x2902 /**< Client Characteristic Configuration Descriptor. */ +#define BLE_UUID_DESCRIPTOR_SERVER_CHAR_CONFIG 0x2903 /**< Server Characteristic Configuration Descriptor. */ +#define BLE_UUID_DESCRIPTOR_CHAR_PRESENTATION_FORMAT 0x2904 /**< Characteristic Presentation Format Descriptor. */ +#define BLE_UUID_DESCRIPTOR_CHAR_AGGREGATE_FORMAT 0x2905 /**< Characteristic Aggregate Format Descriptor. */ +/* GATT specific UUIDs */ +#define BLE_UUID_GATT 0x1801 /**< Generic Attribute Profile. */ +#define BLE_UUID_GATT_CHARACTERISTIC_SERVICE_CHANGED 0x2A05 /**< Service Changed Characteristic. */ +/* GAP specific UUIDs */ +#define BLE_UUID_GAP 0x1800 /**< Generic Access Profile. */ +#define BLE_UUID_GAP_CHARACTERISTIC_DEVICE_NAME 0x2A00 /**< Device Name Characteristic. */ +#define BLE_UUID_GAP_CHARACTERISTIC_APPEARANCE 0x2A01 /**< Appearance Characteristic. */ +#define BLE_UUID_GAP_CHARACTERISTIC_RECONN_ADDR 0x2A03 /**< Reconnection Address Characteristic. */ +#define BLE_UUID_GAP_CHARACTERISTIC_PPCP 0x2A04 /**< Peripheral Preferred Connection Parameters Characteristic. */ +#define BLE_UUID_GAP_CHARACTERISTIC_CAR 0x2AA6 /**< Central Address Resolution Characteristic. */ +#define BLE_UUID_GAP_CHARACTERISTIC_RPA_ONLY 0x2AC9 /**< Resolvable Private Address Only Characteristic. */ +/** @} */ + + +/** @defgroup BLE_UUID_TYPES Types of UUID + * @{ */ +#define BLE_UUID_TYPE_UNKNOWN 0x00 /**< Invalid UUID type. */ +#define BLE_UUID_TYPE_BLE 0x01 /**< Bluetooth SIG UUID (16-bit). */ +#define BLE_UUID_TYPE_VENDOR_BEGIN 0x02 /**< Vendor UUID types start at this index (128-bit). */ +/** @} */ + + +/** @defgroup BLE_APPEARANCES Bluetooth Appearance values + * @note Retrieved from http://developer.bluetooth.org/gatt/characteristics/Pages/CharacteristicViewer.aspx?u=org.bluetooth.characteristic.gap.appearance.xml + * @{ */ +#define BLE_APPEARANCE_UNKNOWN 0 /**< Unknown. */ +#define BLE_APPEARANCE_GENERIC_PHONE 64 /**< Generic Phone. */ +#define BLE_APPEARANCE_GENERIC_COMPUTER 128 /**< Generic Computer. */ +#define BLE_APPEARANCE_GENERIC_WATCH 192 /**< Generic Watch. */ +#define BLE_APPEARANCE_WATCH_SPORTS_WATCH 193 /**< Watch: Sports Watch. */ +#define BLE_APPEARANCE_GENERIC_CLOCK 256 /**< Generic Clock. */ +#define BLE_APPEARANCE_GENERIC_DISPLAY 320 /**< Generic Display. */ +#define BLE_APPEARANCE_GENERIC_REMOTE_CONTROL 384 /**< Generic Remote Control. */ +#define BLE_APPEARANCE_GENERIC_EYE_GLASSES 448 /**< Generic Eye-glasses. */ +#define BLE_APPEARANCE_GENERIC_TAG 512 /**< Generic Tag. */ +#define BLE_APPEARANCE_GENERIC_KEYRING 576 /**< Generic Keyring. */ +#define BLE_APPEARANCE_GENERIC_MEDIA_PLAYER 640 /**< Generic Media Player. */ +#define BLE_APPEARANCE_GENERIC_BARCODE_SCANNER 704 /**< Generic Barcode Scanner. */ +#define BLE_APPEARANCE_GENERIC_THERMOMETER 768 /**< Generic Thermometer. */ +#define BLE_APPEARANCE_THERMOMETER_EAR 769 /**< Thermometer: Ear. */ +#define BLE_APPEARANCE_GENERIC_HEART_RATE_SENSOR 832 /**< Generic Heart rate Sensor. */ +#define BLE_APPEARANCE_HEART_RATE_SENSOR_HEART_RATE_BELT 833 /**< Heart Rate Sensor: Heart Rate Belt. */ +#define BLE_APPEARANCE_GENERIC_BLOOD_PRESSURE 896 /**< Generic Blood Pressure. */ +#define BLE_APPEARANCE_BLOOD_PRESSURE_ARM 897 /**< Blood Pressure: Arm. */ +#define BLE_APPEARANCE_BLOOD_PRESSURE_WRIST 898 /**< Blood Pressure: Wrist. */ +#define BLE_APPEARANCE_GENERIC_HID 960 /**< Human Interface Device (HID). */ +#define BLE_APPEARANCE_HID_KEYBOARD 961 /**< Keyboard (HID Subtype). */ +#define BLE_APPEARANCE_HID_MOUSE 962 /**< Mouse (HID Subtype). */ +#define BLE_APPEARANCE_HID_JOYSTICK 963 /**< Joystick (HID Subtype). */ +#define BLE_APPEARANCE_HID_GAMEPAD 964 /**< Gamepad (HID Subtype). */ +#define BLE_APPEARANCE_HID_DIGITIZERSUBTYPE 965 /**< Digitizer Tablet (HID Subtype). */ +#define BLE_APPEARANCE_HID_CARD_READER 966 /**< Card Reader (HID Subtype). */ +#define BLE_APPEARANCE_HID_DIGITAL_PEN 967 /**< Digital Pen (HID Subtype). */ +#define BLE_APPEARANCE_HID_BARCODE 968 /**< Barcode Scanner (HID Subtype). */ +#define BLE_APPEARANCE_GENERIC_GLUCOSE_METER 1024 /**< Generic Glucose Meter. */ +#define BLE_APPEARANCE_GENERIC_RUNNING_WALKING_SENSOR 1088 /**< Generic Running Walking Sensor. */ +#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_IN_SHOE 1089 /**< Running Walking Sensor: In-Shoe. */ +#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_ON_SHOE 1090 /**< Running Walking Sensor: On-Shoe. */ +#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_ON_HIP 1091 /**< Running Walking Sensor: On-Hip. */ +#define BLE_APPEARANCE_GENERIC_CYCLING 1152 /**< Generic Cycling. */ +#define BLE_APPEARANCE_CYCLING_CYCLING_COMPUTER 1153 /**< Cycling: Cycling Computer. */ +#define BLE_APPEARANCE_CYCLING_SPEED_SENSOR 1154 /**< Cycling: Speed Sensor. */ +#define BLE_APPEARANCE_CYCLING_CADENCE_SENSOR 1155 /**< Cycling: Cadence Sensor. */ +#define BLE_APPEARANCE_CYCLING_POWER_SENSOR 1156 /**< Cycling: Power Sensor. */ +#define BLE_APPEARANCE_CYCLING_SPEED_CADENCE_SENSOR 1157 /**< Cycling: Speed and Cadence Sensor. */ +#define BLE_APPEARANCE_GENERIC_PULSE_OXIMETER 3136 /**< Generic Pulse Oximeter. */ +#define BLE_APPEARANCE_PULSE_OXIMETER_FINGERTIP 3137 /**< Fingertip (Pulse Oximeter subtype). */ +#define BLE_APPEARANCE_PULSE_OXIMETER_WRIST_WORN 3138 /**< Wrist Worn(Pulse Oximeter subtype). */ +#define BLE_APPEARANCE_GENERIC_WEIGHT_SCALE 3200 /**< Generic Weight Scale. */ +#define BLE_APPEARANCE_GENERIC_OUTDOOR_SPORTS_ACT 5184 /**< Generic Outdoor Sports Activity. */ +#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_DISP 5185 /**< Location Display Device (Outdoor Sports Activity subtype). */ +#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_AND_NAV_DISP 5186 /**< Location and Navigation Display Device (Outdoor Sports Activity subtype). */ +#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_POD 5187 /**< Location Pod (Outdoor Sports Activity subtype). */ +#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_AND_NAV_POD 5188 /**< Location and Navigation Pod (Outdoor Sports Activity subtype). */ +/** @} */ + +/** @brief Set .type and .uuid fields of ble_uuid_struct to specified UUID value. */ +#define BLE_UUID_BLE_ASSIGN(instance, value) do {\ + instance.type = BLE_UUID_TYPE_BLE; \ + instance.uuid = value;} while(0) + +/** @brief Copy type and uuid members from src to dst ble_uuid_t pointer. Both pointers must be valid/non-null. */ +#define BLE_UUID_COPY_PTR(dst, src) do {\ + (dst)->type = (src)->type; \ + (dst)->uuid = (src)->uuid;} while(0) + +/** @brief Copy type and uuid members from src to dst ble_uuid_t struct. */ +#define BLE_UUID_COPY_INST(dst, src) do {\ + (dst).type = (src).type; \ + (dst).uuid = (src).uuid;} while(0) + +/** @brief Compare for equality both type and uuid members of two (valid, non-null) ble_uuid_t pointers. */ +#define BLE_UUID_EQ(p_uuid1, p_uuid2) \ + (((p_uuid1)->type == (p_uuid2)->type) && ((p_uuid1)->uuid == (p_uuid2)->uuid)) + +/** @brief Compare for difference both type and uuid members of two (valid, non-null) ble_uuid_t pointers. */ +#define BLE_UUID_NEQ(p_uuid1, p_uuid2) \ + (((p_uuid1)->type != (p_uuid2)->type) || ((p_uuid1)->uuid != (p_uuid2)->uuid)) + +/** @} */ + +/** @addtogroup BLE_TYPES_STRUCTURES Structures + * @{ */ + +/** @brief 128 bit UUID values. */ +typedef struct +{ + uint8_t uuid128[16]; /**< Little-Endian UUID bytes. */ +} ble_uuid128_t; + +/** @brief Bluetooth Low Energy UUID type, encapsulates both 16-bit and 128-bit UUIDs. */ +typedef struct +{ + uint16_t uuid; /**< 16-bit UUID value or octets 12-13 of 128-bit UUID. */ + uint8_t type; /**< UUID type, see @ref BLE_UUID_TYPES. If type is @ref BLE_UUID_TYPE_UNKNOWN, the value of uuid is undefined. */ +} ble_uuid_t; + +/**@brief Data structure. */ +typedef struct +{ + uint8_t *p_data; /**< Pointer to the data buffer provided to/from the application. */ + uint16_t len; /**< Length of the data buffer, in bytes. */ +} ble_data_t; + +/** @} */ +#ifdef __cplusplus +} +#endif + +#endif /* BLE_TYPES_H__ */ + +/** + @} + @} +*/ diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf52/nrf_mbr.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf52/nrf_mbr.h new file mode 100755 index 00000000..42e09fc8 --- /dev/null +++ b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf52/nrf_mbr.h @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2014 - 2017, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @defgroup nrf_mbr_api Master Boot Record API + @{ + + @brief APIs for updating SoftDevice and BootLoader + +*/ + +#ifndef NRF_MBR_H__ +#define NRF_MBR_H__ + +#include "nrf_svc.h" +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup NRF_MBR_DEFINES Defines + * @{ */ + +/**@brief MBR SVC Base number. */ +#define MBR_SVC_BASE (0x18) + +/**@brief Page size in words. */ +#define MBR_PAGE_SIZE_IN_WORDS (1024) + +/** @brief The size that must be reserved for the MBR when a SoftDevice is written to flash. +This is the offset where the first byte of the SoftDevice hex file is written. */ +#define MBR_SIZE (0x1000) + +/** @brief Location (in the flash memory) of the bootloader address. */ +#define MBR_BOOTLOADER_ADDR (0xFF8) + +/** @brief Location (in UICR) of the bootloader address. */ +#define MBR_UICR_BOOTLOADER_ADDR (&(NRF_UICR->NRFFW[0])) + +/** @brief Location (in the flash memory) of the address of the MBR parameter page. */ +#define MBR_PARAM_PAGE_ADDR (0xFFC) + +/** @brief Location (in UICR) of the address of the MBR parameter page. */ +#define MBR_UICR_PARAM_PAGE_ADDR (&(NRF_UICR->NRFFW[1])) + + +/** @} */ + +/** @addtogroup NRF_MBR_ENUMS Enumerations + * @{ */ + +/**@brief nRF Master Boot Record API SVC numbers. */ +enum NRF_MBR_SVCS +{ + SD_MBR_COMMAND = MBR_SVC_BASE, /**< ::sd_mbr_command */ +}; + +/**@brief Possible values for ::sd_mbr_command_t.command */ +enum NRF_MBR_COMMANDS +{ + SD_MBR_COMMAND_COPY_BL, /**< Copy a new BootLoader. @see ::sd_mbr_command_copy_bl_t*/ + SD_MBR_COMMAND_COPY_SD, /**< Copy a new SoftDevice. @see ::sd_mbr_command_copy_sd_t*/ + SD_MBR_COMMAND_INIT_SD, /**< Initialize forwarding interrupts to SD, and run reset function in SD. Does not require any parameters in ::sd_mbr_command_t params.*/ + SD_MBR_COMMAND_COMPARE, /**< This command works like memcmp. @see ::sd_mbr_command_compare_t*/ + SD_MBR_COMMAND_VECTOR_TABLE_BASE_SET, /**< Change the address the MBR starts after a reset. @see ::sd_mbr_command_vector_table_base_set_t*/ + SD_MBR_COMMAND_RESERVED, + SD_MBR_COMMAND_IRQ_FORWARD_ADDRESS_SET, /**< Start forwarding all interrupts to this address. @see ::sd_mbr_command_irq_forward_address_set_t*/ +}; + +/** @} */ + +/** @addtogroup NRF_MBR_TYPES Types + * @{ */ + +/**@brief This command copies part of a new SoftDevice + * + * The destination area is erased before copying. + * If dst is in the middle of a flash page, that whole flash page will be erased. + * If (dst+len) is in the middle of a flash page, that whole flash page will be erased. + * + * The user of this function is responsible for setting the BPROT registers. + * + * @retval ::NRF_SUCCESS indicates that the contents of the memory blocks where copied correctly. + * @retval ::NRF_ERROR_INTERNAL indicates that the contents of the memory blocks where not verified correctly after copying. + */ +typedef struct +{ + uint32_t *src; /**< Pointer to the source of data to be copied.*/ + uint32_t *dst; /**< Pointer to the destination where the content is to be copied.*/ + uint32_t len; /**< Number of 32 bit words to copy. Must be a multiple of @ref MBR_PAGE_SIZE_IN_WORDS words.*/ +} sd_mbr_command_copy_sd_t; + + +/**@brief This command works like memcmp, but takes the length in words. + * + * @retval ::NRF_SUCCESS indicates that the contents of both memory blocks are equal. + * @retval ::NRF_ERROR_NULL indicates that the contents of the memory blocks are not equal. + */ +typedef struct +{ + uint32_t *ptr1; /**< Pointer to block of memory. */ + uint32_t *ptr2; /**< Pointer to block of memory. */ + uint32_t len; /**< Number of 32 bit words to compare.*/ +} sd_mbr_command_compare_t; + + +/**@brief This command copies a new BootLoader. + * + * The MBR assumes that either @ref MBR_BOOTLOADER_ADDR or @ref MBR_UICR_BOOTLOADER_ADDR is set to + * the address where the bootloader will be copied. If both addresses are set, the MBR will prioritize + * @ref MBR_BOOTLOADER_ADDR. + * + * The bootloader destination is erased by this function. + * If (destination+bl_len) is in the middle of a flash page, that whole flash page will be erased. + * + * This command requires that @ref MBR_PARAM_PAGE_ADDR or @ref MBR_UICR_PARAM_PAGE_ADDR is set, + * see @ref sd_mbr_command. + * + * This command will use the flash protect peripheral (BPROT or ACL) to protect the flash that is + * not intended to be written. + * + * On success, this function will not return. It will start the new bootloader from reset-vector as normal. + * + * @retval ::NRF_ERROR_INTERNAL indicates an internal error that should not happen. + * @retval ::NRF_ERROR_FORBIDDEN if the bootloader address is not set. + * @retval ::NRF_ERROR_INVALID_LENGTH if parameters attempts to read or write outside flash area. + * @retval ::NRF_ERROR_NO_MEM No MBR parameter page is provided. See @ref sd_mbr_command. + */ +typedef struct +{ + uint32_t *bl_src; /**< Pointer to the source of the bootloader to be be copied.*/ + uint32_t bl_len; /**< Number of 32 bit words to copy for BootLoader. */ +} sd_mbr_command_copy_bl_t; + +/**@brief Change the address the MBR starts after a reset + * + * Once this function has been called, this address is where the MBR will start to forward + * interrupts to after a reset. + * + * To restore default forwarding, this function should be called with @ref address set to 0. If a + * bootloader is present, interrupts will be forwarded to the bootloader. If not, interrupts will + * be forwarded to the SoftDevice. + * + * The location of a bootloader can be specified in @ref MBR_BOOTLOADER_ADDR or + * @ref MBR_UICR_BOOTLOADER_ADDR. If both addresses are set, the MBR will prioritize + * @ref MBR_BOOTLOADER_ADDR. + * + * This command requires that @ref MBR_PARAM_PAGE_ADDR or @ref MBR_UICR_PARAM_PAGE_ADDR is set, + * see @ref sd_mbr_command. + * + * On success, this function will not return. It will reset the device. + * + * @retval ::NRF_ERROR_INTERNAL indicates an internal error that should not happen. + * @retval ::NRF_ERROR_INVALID_ADDR if parameter address is outside of the flash size. + * @retval ::NRF_ERROR_NO_MEM No MBR parameter page is provided. See @ref sd_mbr_command. + */ +typedef struct +{ + uint32_t address; /**< The base address of the interrupt vector table for forwarded interrupts.*/ +} sd_mbr_command_vector_table_base_set_t; + +/**@brief Sets the base address of the interrupt vector table for interrupts forwarded from the MBR + * + * Unlike sd_mbr_command_vector_table_base_set_t, this function does not reset, and it does not + * change where the MBR starts after reset. + * + * @retval ::NRF_SUCCESS + */ +typedef struct +{ + uint32_t address; /**< The base address of the interrupt vector table for forwarded interrupts.*/ +} sd_mbr_command_irq_forward_address_set_t; + +/**@brief Input structure containing data used when calling ::sd_mbr_command + * + * Depending on what command value that is set, the corresponding params value type must also be + * set. See @ref NRF_MBR_COMMANDS for command types and corresponding params value type. If command + * @ref SD_MBR_COMMAND_INIT_SD is set, it is not necessary to set any values under params. + */ +typedef struct +{ + uint32_t command; /**< Type of command to be issued. See @ref NRF_MBR_COMMANDS. */ + union + { + sd_mbr_command_copy_sd_t copy_sd; /**< Parameters for copy SoftDevice.*/ + sd_mbr_command_compare_t compare; /**< Parameters for verify.*/ + sd_mbr_command_copy_bl_t copy_bl; /**< Parameters for copy BootLoader. Requires parameter page. */ + sd_mbr_command_vector_table_base_set_t base_set; /**< Parameters for vector table base set. Requires parameter page.*/ + sd_mbr_command_irq_forward_address_set_t irq_forward_address_set; /**< Parameters for irq forward address set*/ + } params; /**< Command parameters. */ +} sd_mbr_command_t; + +/** @} */ + +/** @addtogroup NRF_MBR_FUNCTIONS Functions + * @{ */ + +/**@brief Issue Master Boot Record commands + * + * Commands used when updating a SoftDevice and bootloader. + * + * The @ref SD_MBR_COMMAND_COPY_BL and @ref SD_MBR_COMMAND_VECTOR_TABLE_BASE_SET requires + * parameters to be retained by the MBR when resetting the IC. This is done in a separate flash + * page. The location of the flash page should be provided by the application in either + * @ref MBR_PARAM_PAGE_ADDR or @ref MBR_UICR_PARAM_PAGE_ADDR. If both addresses are set, the MBR + * will prioritize @ref MBR_PARAM_PAGE_ADDR. This page will be cleared by the MBR and is used to + * store the command before reset. When an address is specified, the page it refers to must not be + * used by the application. If no address is provided by the application, i.e. both + * @ref MBR_PARAM_PAGE_ADDR and @ref MBR_UICR_PARAM_PAGE_ADDR is 0xFFFFFFFF, MBR commands which use + * flash will be unavailable and return @ref NRF_ERROR_NO_MEM. + * + * @param[in] param Pointer to a struct describing the command. + * + * @note For a complete set of return values, see ::sd_mbr_command_copy_sd_t, + * ::sd_mbr_command_copy_bl_t, ::sd_mbr_command_compare_t, + * ::sd_mbr_command_vector_table_base_set_t, ::sd_mbr_command_irq_forward_address_set_t + * + * @retval ::NRF_ERROR_NO_MEM No MBR parameter page provided + * @retval ::NRF_ERROR_INVALID_PARAM if an invalid command is given. +*/ +SVCALL(SD_MBR_COMMAND, uint32_t, sd_mbr_command(sd_mbr_command_t* param)); + +/** @} */ + +#ifdef __cplusplus +} +#endif +#endif // NRF_MBR_H__ + +/** + @} +*/ diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_error.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_error.h new file mode 100755 index 00000000..6badee98 --- /dev/null +++ b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_error.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2014 - 2017, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** + @defgroup nrf_error SoftDevice Global Error Codes + @{ + + @brief Global Error definitions +*/ + +/* Header guard */ +#ifndef NRF_ERROR_H__ +#define NRF_ERROR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup NRF_ERRORS_BASE Error Codes Base number definitions + * @{ */ +#define NRF_ERROR_BASE_NUM (0x0) ///< Global error base +#define NRF_ERROR_SDM_BASE_NUM (0x1000) ///< SDM error base +#define NRF_ERROR_SOC_BASE_NUM (0x2000) ///< SoC error base +#define NRF_ERROR_STK_BASE_NUM (0x3000) ///< STK error base +/** @} */ + +#define NRF_SUCCESS (NRF_ERROR_BASE_NUM + 0) ///< Successful command +#define NRF_ERROR_SVC_HANDLER_MISSING (NRF_ERROR_BASE_NUM + 1) ///< SVC handler is missing +#define NRF_ERROR_SOFTDEVICE_NOT_ENABLED (NRF_ERROR_BASE_NUM + 2) ///< SoftDevice has not been enabled +#define NRF_ERROR_INTERNAL (NRF_ERROR_BASE_NUM + 3) ///< Internal Error +#define NRF_ERROR_NO_MEM (NRF_ERROR_BASE_NUM + 4) ///< No Memory for operation +#define NRF_ERROR_NOT_FOUND (NRF_ERROR_BASE_NUM + 5) ///< Not found +#define NRF_ERROR_NOT_SUPPORTED (NRF_ERROR_BASE_NUM + 6) ///< Not supported +#define NRF_ERROR_INVALID_PARAM (NRF_ERROR_BASE_NUM + 7) ///< Invalid Parameter +#define NRF_ERROR_INVALID_STATE (NRF_ERROR_BASE_NUM + 8) ///< Invalid state, operation disallowed in this state +#define NRF_ERROR_INVALID_LENGTH (NRF_ERROR_BASE_NUM + 9) ///< Invalid Length +#define NRF_ERROR_INVALID_FLAGS (NRF_ERROR_BASE_NUM + 10) ///< Invalid Flags +#define NRF_ERROR_INVALID_DATA (NRF_ERROR_BASE_NUM + 11) ///< Invalid Data +#define NRF_ERROR_DATA_SIZE (NRF_ERROR_BASE_NUM + 12) ///< Invalid Data size +#define NRF_ERROR_TIMEOUT (NRF_ERROR_BASE_NUM + 13) ///< Operation timed out +#define NRF_ERROR_NULL (NRF_ERROR_BASE_NUM + 14) ///< Null Pointer +#define NRF_ERROR_FORBIDDEN (NRF_ERROR_BASE_NUM + 15) ///< Forbidden Operation +#define NRF_ERROR_INVALID_ADDR (NRF_ERROR_BASE_NUM + 16) ///< Bad Memory Address +#define NRF_ERROR_BUSY (NRF_ERROR_BASE_NUM + 17) ///< Busy +#define NRF_ERROR_CONN_COUNT (NRF_ERROR_BASE_NUM + 18) ///< Maximum connection count exceeded. +#define NRF_ERROR_RESOURCES (NRF_ERROR_BASE_NUM + 19) ///< Not enough resources for operation + +#ifdef __cplusplus +} +#endif +#endif // NRF_ERROR_H__ + +/** + @} +*/ diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_error_sdm.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_error_sdm.h new file mode 100755 index 00000000..530959b9 --- /dev/null +++ b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_error_sdm.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2012 - 2017, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** + @addtogroup nrf_sdm_api + @{ + @defgroup nrf_sdm_error SoftDevice Manager Error Codes + @{ + + @brief Error definitions for the SDM API +*/ + +/* Header guard */ +#ifndef NRF_ERROR_SDM_H__ +#define NRF_ERROR_SDM_H__ + +#include "nrf_error.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NRF_ERROR_SDM_LFCLK_SOURCE_UNKNOWN (NRF_ERROR_SDM_BASE_NUM + 0) ///< Unknown LFCLK source. +#define NRF_ERROR_SDM_INCORRECT_INTERRUPT_CONFIGURATION (NRF_ERROR_SDM_BASE_NUM + 1) ///< Incorrect interrupt configuration (can be caused by using illegal priority levels, or having enabled SoftDevice interrupts). +#define NRF_ERROR_SDM_INCORRECT_CLENR0 (NRF_ERROR_SDM_BASE_NUM + 2) ///< Incorrect CLENR0 (can be caused by erroneous SoftDevice flashing). + +#ifdef __cplusplus +} +#endif +#endif // NRF_ERROR_SDM_H__ + +/** + @} + @} +*/ diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_error_soc.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_error_soc.h new file mode 100755 index 00000000..1e784b8d --- /dev/null +++ b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_error_soc.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2012 - 2017, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup nrf_soc_api + @{ + @defgroup nrf_soc_error SoC Library Error Codes + @{ + + @brief Error definitions for the SoC library + +*/ + +/* Header guard */ +#ifndef NRF_ERROR_SOC_H__ +#define NRF_ERROR_SOC_H__ + +#include "nrf_error.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* Mutex Errors */ +#define NRF_ERROR_SOC_MUTEX_ALREADY_TAKEN (NRF_ERROR_SOC_BASE_NUM + 0) ///< Mutex already taken + +/* NVIC errors */ +#define NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE (NRF_ERROR_SOC_BASE_NUM + 1) ///< NVIC interrupt not available +#define NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED (NRF_ERROR_SOC_BASE_NUM + 2) ///< NVIC interrupt priority not allowed +#define NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN (NRF_ERROR_SOC_BASE_NUM + 3) ///< NVIC should not return + +/* Power errors */ +#define NRF_ERROR_SOC_POWER_MODE_UNKNOWN (NRF_ERROR_SOC_BASE_NUM + 4) ///< Power mode unknown +#define NRF_ERROR_SOC_POWER_POF_THRESHOLD_UNKNOWN (NRF_ERROR_SOC_BASE_NUM + 5) ///< Power POF threshold unknown +#define NRF_ERROR_SOC_POWER_OFF_SHOULD_NOT_RETURN (NRF_ERROR_SOC_BASE_NUM + 6) ///< Power off should not return + +/* Rand errors */ +#define NRF_ERROR_SOC_RAND_NOT_ENOUGH_VALUES (NRF_ERROR_SOC_BASE_NUM + 7) ///< RAND not enough values + +/* PPI errors */ +#define NRF_ERROR_SOC_PPI_INVALID_CHANNEL (NRF_ERROR_SOC_BASE_NUM + 8) ///< Invalid PPI Channel +#define NRF_ERROR_SOC_PPI_INVALID_GROUP (NRF_ERROR_SOC_BASE_NUM + 9) ///< Invalid PPI Group + +#ifdef __cplusplus +} +#endif +#endif // NRF_ERROR_SOC_H__ +/** + @} + @} +*/ diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_nvic.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_nvic.h new file mode 100755 index 00000000..1f79cc3c --- /dev/null +++ b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_nvic.h @@ -0,0 +1,491 @@ +/* + * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @defgroup nrf_nvic_api SoftDevice NVIC API + * @{ + * + * @note In order to use this module, the following code has to be added to a .c file: + * \code + * nrf_nvic_state_t nrf_nvic_state = {0}; + * \endcode + * + * @note Definitions and declarations starting with __ (double underscore) in this header file are + * not intended for direct use by the application. + * + * @brief APIs for the accessing NVIC when using a SoftDevice. + * + */ + +#ifndef NRF_NVIC_H__ +#define NRF_NVIC_H__ + +#include <stdint.h> +#include "nrf.h" +#include "nrf_svc.h" +#include "nrf_error.h" +#include "nrf_error_soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/**@addtogroup NRF_NVIC_DEFINES Defines + * @{ */ + +/**@defgroup NRF_NVIC_ISER_DEFINES SoftDevice NVIC internal definitions + * @{ */ + +#define __NRF_NVIC_NVMC_IRQn (30) /**< The peripheral ID of the NVMC. IRQ numbers are used to identify peripherals, but the NVMC doesn't have an IRQ number in the MDK. */ + +#define __NRF_NVIC_ISER_COUNT (2) /**< The number of ISER/ICER registers in the NVIC that are used. */ + +/**@brief Interrupt priority levels used by the SoftDevice. */ +#define __NRF_NVIC_SD_IRQ_PRIOS ((uint8_t)( \ + (1U << 0) /**< Priority level high .*/ \ + | (1U << 1) /**< Priority level medium. */ \ + | (1U << 4) /**< Priority level low. */ \ + )) + +/**@brief Interrupt priority levels available to the application. */ +#define __NRF_NVIC_APP_IRQ_PRIOS ((uint8_t)~__NRF_NVIC_SD_IRQ_PRIOS) + +/**@brief Interrupts used by the SoftDevice, with IRQn in the range 0-31. */ +#define __NRF_NVIC_SD_IRQS_0 ((uint32_t)( \ + (1U << POWER_CLOCK_IRQn) \ + | (1U << RADIO_IRQn) \ + | (1U << RTC0_IRQn) \ + | (1U << TIMER0_IRQn) \ + | (1U << RNG_IRQn) \ + | (1U << ECB_IRQn) \ + | (1U << CCM_AAR_IRQn) \ + | (1U << TEMP_IRQn) \ + | (1U << __NRF_NVIC_NVMC_IRQn) \ + | (1U << (uint32_t)SWI5_IRQn) \ + )) + +/**@brief Interrupts used by the SoftDevice, with IRQn in the range 32-63. */ +#define __NRF_NVIC_SD_IRQS_1 ((uint32_t)0) + +/**@brief Interrupts available for to application, with IRQn in the range 0-31. */ +#define __NRF_NVIC_APP_IRQS_0 (~__NRF_NVIC_SD_IRQS_0) + +/**@brief Interrupts available for to application, with IRQn in the range 32-63. */ +#define __NRF_NVIC_APP_IRQS_1 (~__NRF_NVIC_SD_IRQS_1) + +/**@} */ + +/**@} */ + +/**@addtogroup NRF_NVIC_VARIABLES Variables + * @{ */ + +/**@brief Type representing the state struct for the SoftDevice NVIC module. */ +typedef struct +{ + uint32_t volatile __irq_masks[__NRF_NVIC_ISER_COUNT]; /**< IRQs enabled by the application in the NVIC. */ + uint32_t volatile __cr_flag; /**< Non-zero if already in a critical region */ +} nrf_nvic_state_t; + +/**@brief Variable keeping the state for the SoftDevice NVIC module. This must be declared in an + * application source file. */ +extern nrf_nvic_state_t nrf_nvic_state; + +/**@} */ + +/**@addtogroup NRF_NVIC_INTERNAL_FUNCTIONS SoftDevice NVIC internal functions + * @{ */ + +/**@brief Disables IRQ interrupts globally, including the SoftDevice's interrupts. + * + * @retval The value of PRIMASK prior to disabling the interrupts. + */ +__STATIC_INLINE int __sd_nvic_irq_disable(void); + +/**@brief Enables IRQ interrupts globally, including the SoftDevice's interrupts. + */ +__STATIC_INLINE void __sd_nvic_irq_enable(void); + +/**@brief Checks if IRQn is available to application + * @param[in] IRQn IRQ to check + * + * @retval 1 (true) if the IRQ to check is available to the application + */ +__STATIC_INLINE uint32_t __sd_nvic_app_accessible_irq(IRQn_Type IRQn); + +/**@brief Checks if priority is available to application + * @param[in] priority priority to check + * + * @retval 1 (true) if the priority to check is available to the application + */ +__STATIC_INLINE uint32_t __sd_nvic_is_app_accessible_priority(uint32_t priority); + +/**@} */ + +/**@addtogroup NRF_NVIC_FUNCTIONS SoftDevice NVIC public functions + * @{ */ + +/**@brief Enable External Interrupt. + * @note Corresponds to NVIC_EnableIRQ in CMSIS. + * + * @pre IRQn is valid and not reserved by the stack. + * + * @param[in] IRQn See the NVIC_EnableIRQ documentation in CMSIS. + * + * @retval ::NRF_SUCCESS The interrupt was enabled. + * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE The interrupt is not available for the application. + * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED The interrupt has a priority not available for the application. + */ +__STATIC_INLINE uint32_t sd_nvic_EnableIRQ(IRQn_Type IRQn); + +/**@brief Disable External Interrupt. + * @note Corresponds to NVIC_DisableIRQ in CMSIS. + * + * @pre IRQn is valid and not reserved by the stack. + * + * @param[in] IRQn See the NVIC_DisableIRQ documentation in CMSIS. + * + * @retval ::NRF_SUCCESS The interrupt was disabled. + * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE The interrupt is not available for the application. + */ +__STATIC_INLINE uint32_t sd_nvic_DisableIRQ(IRQn_Type IRQn); + +/**@brief Get Pending Interrupt. + * @note Corresponds to NVIC_GetPendingIRQ in CMSIS. + * + * @pre IRQn is valid and not reserved by the stack. + * + * @param[in] IRQn See the NVIC_GetPendingIRQ documentation in CMSIS. + * @param[out] p_pending_irq Return value from NVIC_GetPendingIRQ. + * + * @retval ::NRF_SUCCESS The interrupt is available for the application. + * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application. + */ +__STATIC_INLINE uint32_t sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t * p_pending_irq); + +/**@brief Set Pending Interrupt. + * @note Corresponds to NVIC_SetPendingIRQ in CMSIS. + * + * @pre IRQn is valid and not reserved by the stack. + * + * @param[in] IRQn See the NVIC_SetPendingIRQ documentation in CMSIS. + * + * @retval ::NRF_SUCCESS The interrupt is set pending. + * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application. + */ +__STATIC_INLINE uint32_t sd_nvic_SetPendingIRQ(IRQn_Type IRQn); + +/**@brief Clear Pending Interrupt. + * @note Corresponds to NVIC_ClearPendingIRQ in CMSIS. + * + * @pre IRQn is valid and not reserved by the stack. + * + * @param[in] IRQn See the NVIC_ClearPendingIRQ documentation in CMSIS. + * + * @retval ::NRF_SUCCESS The interrupt pending flag is cleared. + * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application. + */ +__STATIC_INLINE uint32_t sd_nvic_ClearPendingIRQ(IRQn_Type IRQn); + +/**@brief Set Interrupt Priority. + * @note Corresponds to NVIC_SetPriority in CMSIS. + * + * @pre IRQn is valid and not reserved by the stack. + * @pre Priority is valid and not reserved by the stack. + * + * @param[in] IRQn See the NVIC_SetPriority documentation in CMSIS. + * @param[in] priority A valid IRQ priority for use by the application. + * + * @retval ::NRF_SUCCESS The interrupt and priority level is available for the application. + * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application. + * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED The interrupt priority is not available for the application. + */ +__STATIC_INLINE uint32_t sd_nvic_SetPriority(IRQn_Type IRQn, uint32_t priority); + +/**@brief Get Interrupt Priority. + * @note Corresponds to NVIC_GetPriority in CMSIS. + * + * @pre IRQn is valid and not reserved by the stack. + * + * @param[in] IRQn See the NVIC_GetPriority documentation in CMSIS. + * @param[out] p_priority Return value from NVIC_GetPriority. + * + * @retval ::NRF_SUCCESS The interrupt priority is returned in p_priority. + * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE - IRQn is not available for the application. + */ +__STATIC_INLINE uint32_t sd_nvic_GetPriority(IRQn_Type IRQn, uint32_t * p_priority); + +/**@brief System Reset. + * @note Corresponds to NVIC_SystemReset in CMSIS. + * + * @retval ::NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN + */ +__STATIC_INLINE uint32_t sd_nvic_SystemReset(void); + +/**@brief Enter critical region. + * + * @post Application interrupts will be disabled. + * @note sd_nvic_critical_region_enter() and ::sd_nvic_critical_region_exit() must be called in matching pairs inside each + * execution context + * @sa sd_nvic_critical_region_exit + * + * @param[out] p_is_nested_critical_region If 1, the application is now in a nested critical region. + * + * @retval ::NRF_SUCCESS + */ +__STATIC_INLINE uint32_t sd_nvic_critical_region_enter(uint8_t * p_is_nested_critical_region); + +/**@brief Exit critical region. + * + * @pre Application has entered a critical region using ::sd_nvic_critical_region_enter. + * @post If not in a nested critical region, the application interrupts will restored to the state before ::sd_nvic_critical_region_enter was called. + * + * @param[in] is_nested_critical_region If this is set to 1, the critical region won't be exited. @sa sd_nvic_critical_region_enter. + * + * @retval ::NRF_SUCCESS + */ +__STATIC_INLINE uint32_t sd_nvic_critical_region_exit(uint8_t is_nested_critical_region); + +/**@} */ + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE int __sd_nvic_irq_disable(void) +{ + int pm = __get_PRIMASK(); + __disable_irq(); + return pm; +} + +__STATIC_INLINE void __sd_nvic_irq_enable(void) +{ + __enable_irq(); +} + +__STATIC_INLINE uint32_t __sd_nvic_app_accessible_irq(IRQn_Type IRQn) +{ + if (IRQn < 32) + { + return ((1UL<<IRQn) & __NRF_NVIC_APP_IRQS_0) != 0; + } + else if (IRQn < 64) + { + return ((1UL<<(IRQn-32)) & __NRF_NVIC_APP_IRQS_1) != 0; + } + else + { + return 1; + } +} + +__STATIC_INLINE uint32_t __sd_nvic_is_app_accessible_priority(uint32_t priority) +{ + if( (priority >= (1 << __NVIC_PRIO_BITS)) + || (((1 << priority) & __NRF_NVIC_APP_IRQ_PRIOS) == 0) + ) + { + return 0; + } + return 1; +} + + +__STATIC_INLINE uint32_t sd_nvic_EnableIRQ(IRQn_Type IRQn) +{ + if (!__sd_nvic_app_accessible_irq(IRQn)) + { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } + if (!__sd_nvic_is_app_accessible_priority(NVIC_GetPriority(IRQn))) + { + return NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED; + } + + if (nrf_nvic_state.__cr_flag) + { + nrf_nvic_state.__irq_masks[(uint32_t)((int32_t)IRQn) >> 5] |= (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); + } + else + { + NVIC_EnableIRQ(IRQn); + } + return NRF_SUCCESS; +} + +__STATIC_INLINE uint32_t sd_nvic_DisableIRQ(IRQn_Type IRQn) +{ + if (!__sd_nvic_app_accessible_irq(IRQn)) + { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } + + if (nrf_nvic_state.__cr_flag) + { + nrf_nvic_state.__irq_masks[(uint32_t)((int32_t)IRQn) >> 5] &= ~(1UL << ((uint32_t)(IRQn) & 0x1F)); + } + else + { + NVIC_DisableIRQ(IRQn); + } + + return NRF_SUCCESS; +} + +__STATIC_INLINE uint32_t sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t * p_pending_irq) +{ + if (__sd_nvic_app_accessible_irq(IRQn)) + { + *p_pending_irq = NVIC_GetPendingIRQ(IRQn); + return NRF_SUCCESS; + } + else + { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } +} + +__STATIC_INLINE uint32_t sd_nvic_SetPendingIRQ(IRQn_Type IRQn) +{ + if (__sd_nvic_app_accessible_irq(IRQn)) + { + NVIC_SetPendingIRQ(IRQn); + return NRF_SUCCESS; + } + else + { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } +} + +__STATIC_INLINE uint32_t sd_nvic_ClearPendingIRQ(IRQn_Type IRQn) +{ + if (__sd_nvic_app_accessible_irq(IRQn)) + { + NVIC_ClearPendingIRQ(IRQn); + return NRF_SUCCESS; + } + else + { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } +} + +__STATIC_INLINE uint32_t sd_nvic_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if (!__sd_nvic_app_accessible_irq(IRQn)) + { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } + + if (!__sd_nvic_is_app_accessible_priority(priority)) + { + return NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED; + } + + NVIC_SetPriority(IRQn, (uint32_t)priority); + return NRF_SUCCESS; +} + +__STATIC_INLINE uint32_t sd_nvic_GetPriority(IRQn_Type IRQn, uint32_t * p_priority) +{ + if (__sd_nvic_app_accessible_irq(IRQn)) + { + *p_priority = (NVIC_GetPriority(IRQn) & 0xFF); + return NRF_SUCCESS; + } + else + { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } +} + +__STATIC_INLINE uint32_t sd_nvic_SystemReset(void) +{ + NVIC_SystemReset(); + return NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN; +} + +__STATIC_INLINE uint32_t sd_nvic_critical_region_enter(uint8_t * p_is_nested_critical_region) +{ + int was_masked = __sd_nvic_irq_disable(); + if (!nrf_nvic_state.__cr_flag) + { + nrf_nvic_state.__cr_flag = 1; + nrf_nvic_state.__irq_masks[0] = ( NVIC->ICER[0] & __NRF_NVIC_APP_IRQS_0 ); + NVIC->ICER[0] = __NRF_NVIC_APP_IRQS_0; + nrf_nvic_state.__irq_masks[1] = ( NVIC->ICER[1] & __NRF_NVIC_APP_IRQS_1 ); + NVIC->ICER[1] = __NRF_NVIC_APP_IRQS_1; + *p_is_nested_critical_region = 0; + } + else + { + *p_is_nested_critical_region = 1; + } + if (!was_masked) + { + __sd_nvic_irq_enable(); + } + return NRF_SUCCESS; +} + +__STATIC_INLINE uint32_t sd_nvic_critical_region_exit(uint8_t is_nested_critical_region) +{ + if (nrf_nvic_state.__cr_flag && (is_nested_critical_region == 0)) + { + int was_masked = __sd_nvic_irq_disable(); + NVIC->ISER[0] = nrf_nvic_state.__irq_masks[0]; + NVIC->ISER[1] = nrf_nvic_state.__irq_masks[1]; + nrf_nvic_state.__cr_flag = 0; + if (!was_masked) + { + __sd_nvic_irq_enable(); + } + } + + return NRF_SUCCESS; +} + +#endif /* SUPPRESS_INLINE_IMPLEMENTATION */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_NVIC_H__ + +/**@} */ diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_sdm.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_sdm.h new file mode 100755 index 00000000..5dfbb287 --- /dev/null +++ b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_sdm.h @@ -0,0 +1,367 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @defgroup nrf_sdm_api SoftDevice Manager API + @{ + + @brief APIs for SoftDevice management. + +*/ + +#ifndef NRF_SDM_H__ +#define NRF_SDM_H__ + +#include <stdint.h> +#include "nrf.h" +#include "nrf_svc.h" +#include "nrf_error.h" +#include "nrf_error_sdm.h" +#include "nrf_soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup NRF_SDM_DEFINES Defines + * @{ */ +#ifdef NRFSOC_DOXYGEN +/// Declared in nrf_mbr.h +#define MBR_SIZE 0 +#warning test +#endif + +/** @brief The major version for the SoftDevice binary distributed with this header file. */ +#define SD_MAJOR_VERSION (6) + +/** @brief The minor version for the SoftDevice binary distributed with this header file. */ +#define SD_MINOR_VERSION (1) + +/** @brief The bugfix version for the SoftDevice binary distributed with this header file. */ +#define SD_BUGFIX_VERSION (1) + +/** @brief The SoftDevice variant of this firmware. */ +#define SD_VARIANT_ID 140 + +/** @brief The full version number for the SoftDevice binary this header file was distributed + * with, as a decimal number in the form Mmmmbbb, where: + * - M is major version (one or more digits) + * - mmm is minor version (three digits) + * - bbb is bugfix version (three digits). */ +#define SD_VERSION (SD_MAJOR_VERSION * 1000000 + SD_MINOR_VERSION * 1000 + SD_BUGFIX_VERSION) + +/** @brief SoftDevice Manager SVC Base number. */ +#define SDM_SVC_BASE 0x10 + +/** @brief SoftDevice unique string size in bytes. */ +#define SD_UNIQUE_STR_SIZE 20 + +/** @brief Invalid info field. Returned when an info field does not exist. */ +#define SDM_INFO_FIELD_INVALID (0) + +/** @brief Defines the SoftDevice Information Structure location (address) as an offset from +the start of the SoftDevice (without MBR)*/ +#define SOFTDEVICE_INFO_STRUCT_OFFSET (0x2000) + +/** @brief Defines the absolute SoftDevice Information Structure location (address) when the + * SoftDevice is installed just above the MBR (the usual case). */ +#define SOFTDEVICE_INFO_STRUCT_ADDRESS (SOFTDEVICE_INFO_STRUCT_OFFSET + MBR_SIZE) + +/** @brief Defines the offset for the SoftDevice Information Structure size value relative to the + * SoftDevice base address. The size value is of type uint8_t. */ +#define SD_INFO_STRUCT_SIZE_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET) + +/** @brief Defines the offset for the SoftDevice size value relative to the SoftDevice base address. + * The size value is of type uint32_t. */ +#define SD_SIZE_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x08) + +/** @brief Defines the offset for FWID value relative to the SoftDevice base address. The FWID value + * is of type uint16_t. */ +#define SD_FWID_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x0C) + +/** @brief Defines the offset for the SoftDevice ID relative to the SoftDevice base address. The ID + * is of type uint32_t. */ +#define SD_ID_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x10) + +/** @brief Defines the offset for the SoftDevice version relative to the SoftDevice base address in + * the same format as @ref SD_VERSION, stored as an uint32_t. */ +#define SD_VERSION_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x14) + +/** @brief Defines the offset for the SoftDevice unique string relative to the SoftDevice base address. + * The SD_UNIQUE_STR is stored as an array of uint8_t. The size of array is @ref SD_UNIQUE_STR_SIZE. + */ +#define SD_UNIQUE_STR_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x18) + +/** @brief Defines a macro for retrieving the actual SoftDevice Information Structure size value + * from a given base address. Use @ref MBR_SIZE as the argument when the SoftDevice is + * installed just above the MBR (the usual case). */ +#define SD_INFO_STRUCT_SIZE_GET(baseaddr) (*((uint8_t *) ((baseaddr) + SD_INFO_STRUCT_SIZE_OFFSET))) + +/** @brief Defines a macro for retrieving the actual SoftDevice size value from a given base + * address. Use @ref MBR_SIZE as the argument when the SoftDevice is installed just above + * the MBR (the usual case). */ +#define SD_SIZE_GET(baseaddr) (*((uint32_t *) ((baseaddr) + SD_SIZE_OFFSET))) + +/** @brief Defines the amount of flash that is used by the SoftDevice. + * Add @ref MBR_SIZE to find the first available flash address when the SoftDevice is installed + * just above the MBR (the usual case). + */ +#define SD_FLASH_SIZE 0x25000 + +/** @brief Defines a macro for retrieving the actual FWID value from a given base address. Use + * @ref MBR_SIZE as the argument when the SoftDevice is installed just above the MBR (the usual + * case). */ +#define SD_FWID_GET(baseaddr) (*((uint16_t *) ((baseaddr) + SD_FWID_OFFSET))) + +/** @brief Defines a macro for retrieving the actual SoftDevice ID from a given base address. Use + * @ref MBR_SIZE as the argument when the SoftDevice is installed just above the MBR (the + * usual case). */ +#define SD_ID_GET(baseaddr) ((SD_INFO_STRUCT_SIZE_GET(baseaddr) > (SD_ID_OFFSET - SOFTDEVICE_INFO_STRUCT_OFFSET)) \ + ? (*((uint32_t *) ((baseaddr) + SD_ID_OFFSET))) : SDM_INFO_FIELD_INVALID) + +/** @brief Defines a macro for retrieving the actual SoftDevice version from a given base address. + * Use @ref MBR_SIZE as the argument when the SoftDevice is installed just above the MBR + * (the usual case). */ +#define SD_VERSION_GET(baseaddr) ((SD_INFO_STRUCT_SIZE_GET(baseaddr) > (SD_VERSION_OFFSET - SOFTDEVICE_INFO_STRUCT_OFFSET)) \ + ? (*((uint32_t *) ((baseaddr) + SD_VERSION_OFFSET))) : SDM_INFO_FIELD_INVALID) + +/** @brief Defines a macro for retrieving the address of SoftDevice unique str based on a given base address. + * Use @ref MBR_SIZE as the argument when the SoftDevice is installed just above the MBR + * (the usual case). */ +#define SD_UNIQUE_STR_ADDR_GET(baseaddr) ((SD_INFO_STRUCT_SIZE_GET(baseaddr) > (SD_UNIQUE_STR_OFFSET - SOFTDEVICE_INFO_STRUCT_OFFSET)) \ + ? (((uint8_t *) ((baseaddr) + SD_UNIQUE_STR_OFFSET))) : SDM_INFO_FIELD_INVALID) + +/**@defgroup NRF_FAULT_ID_RANGES Fault ID ranges + * @{ */ +#define NRF_FAULT_ID_SD_RANGE_START 0x00000000 /**< SoftDevice ID range start. */ +#define NRF_FAULT_ID_APP_RANGE_START 0x00001000 /**< Application ID range start. */ +/**@} */ + +/**@defgroup NRF_FAULT_IDS Fault ID types + * @{ */ +#define NRF_FAULT_ID_SD_ASSERT (NRF_FAULT_ID_SD_RANGE_START + 1) /**< SoftDevice assertion. The info parameter is reserved for future used. */ +#define NRF_FAULT_ID_APP_MEMACC (NRF_FAULT_ID_APP_RANGE_START + 1) /**< Application invalid memory access. The info parameter will contain 0x00000000, + in case of SoftDevice RAM access violation. In case of SoftDevice peripheral + register violation the info parameter will contain the sub-region number of + PREGION[0], on whose address range the disallowed write access caused the + memory access fault. */ +/**@} */ + +/** @} */ + +/** @addtogroup NRF_SDM_ENUMS Enumerations + * @{ */ + +/**@brief nRF SoftDevice Manager API SVC numbers. */ +enum NRF_SD_SVCS +{ + SD_SOFTDEVICE_ENABLE = SDM_SVC_BASE, /**< ::sd_softdevice_enable */ + SD_SOFTDEVICE_DISABLE, /**< ::sd_softdevice_disable */ + SD_SOFTDEVICE_IS_ENABLED, /**< ::sd_softdevice_is_enabled */ + SD_SOFTDEVICE_VECTOR_TABLE_BASE_SET, /**< ::sd_softdevice_vector_table_base_set */ + SVC_SDM_LAST /**< Placeholder for last SDM SVC */ +}; + +/** @} */ + +/** @addtogroup NRF_SDM_DEFINES Defines + * @{ */ + +/**@defgroup NRF_CLOCK_LF_ACCURACY Clock accuracy + * @{ */ + +#define NRF_CLOCK_LF_ACCURACY_250_PPM (0) /**< Default: 250 ppm */ +#define NRF_CLOCK_LF_ACCURACY_500_PPM (1) /**< 500 ppm */ +#define NRF_CLOCK_LF_ACCURACY_150_PPM (2) /**< 150 ppm */ +#define NRF_CLOCK_LF_ACCURACY_100_PPM (3) /**< 100 ppm */ +#define NRF_CLOCK_LF_ACCURACY_75_PPM (4) /**< 75 ppm */ +#define NRF_CLOCK_LF_ACCURACY_50_PPM (5) /**< 50 ppm */ +#define NRF_CLOCK_LF_ACCURACY_30_PPM (6) /**< 30 ppm */ +#define NRF_CLOCK_LF_ACCURACY_20_PPM (7) /**< 20 ppm */ +#define NRF_CLOCK_LF_ACCURACY_10_PPM (8) /**< 10 ppm */ +#define NRF_CLOCK_LF_ACCURACY_5_PPM (9) /**< 5 ppm */ +#define NRF_CLOCK_LF_ACCURACY_2_PPM (10) /**< 2 ppm */ +#define NRF_CLOCK_LF_ACCURACY_1_PPM (11) /**< 1 ppm */ + +/** @} */ + +/**@defgroup NRF_CLOCK_LF_SRC Possible LFCLK oscillator sources + * @{ */ + +#define NRF_CLOCK_LF_SRC_RC (0) /**< LFCLK RC oscillator. */ +#define NRF_CLOCK_LF_SRC_XTAL (1) /**< LFCLK crystal oscillator. */ +#define NRF_CLOCK_LF_SRC_SYNTH (2) /**< LFCLK Synthesized from HFCLK. */ + +/** @} */ + +/** @} */ + +/** @addtogroup NRF_SDM_TYPES Types + * @{ */ + +/**@brief Type representing LFCLK oscillator source. */ +typedef struct +{ + uint8_t source; /**< LF oscillator clock source, see @ref NRF_CLOCK_LF_SRC. */ + uint8_t rc_ctiv; /**< Only for ::NRF_CLOCK_LF_SRC_RC: Calibration timer interval in 1/4 second + units (nRF52: 1-32). + @note To avoid excessive clock drift, 0.5 degrees Celsius is the + maximum temperature change allowed in one calibration timer + interval. The interval should be selected to ensure this. + + @note Must be 0 if source is not ::NRF_CLOCK_LF_SRC_RC. */ + uint8_t rc_temp_ctiv; /**< Only for ::NRF_CLOCK_LF_SRC_RC: How often (in number of calibration + intervals) the RC oscillator shall be calibrated if the temperature + hasn't changed. + 0: Always calibrate even if the temperature hasn't changed. + 1: Only calibrate if the temperature has changed (legacy - nRF51 only). + 2-33: Check the temperature and only calibrate if it has changed, + however calibration will take place every rc_temp_ctiv + intervals in any case. + + @note Must be 0 if source is not ::NRF_CLOCK_LF_SRC_RC. + + @note For nRF52, the application must ensure calibration at least once + every 8 seconds to ensure +/-500 ppm clock stability. The + recommended configuration for ::NRF_CLOCK_LF_SRC_RC on nRF52 is + rc_ctiv=16 and rc_temp_ctiv=2. This will ensure calibration at + least once every 8 seconds and for temperature changes of 0.5 + degrees Celsius every 4 seconds. See the Product Specification + for the nRF52 device being used for more information.*/ + uint8_t accuracy; /**< External clock accuracy used in the LL to compute timing + windows, see @ref NRF_CLOCK_LF_ACCURACY.*/ +} nrf_clock_lf_cfg_t; + +/**@brief Fault Handler type. + * + * When certain unrecoverable errors occur within the application or SoftDevice the fault handler will be called back. + * The protocol stack will be in an undefined state when this happens and the only way to recover will be to + * perform a reset, using e.g. CMSIS NVIC_SystemReset(). + * If the application returns from the fault handler the SoftDevice will call NVIC_SystemReset(). + * + * @note This callback is executed in HardFault context, thus SVC functions cannot be called from the fault callback. + * + * @param[in] id Fault identifier. See @ref NRF_FAULT_IDS. + * @param[in] pc The program counter of the instruction that triggered the fault. + * @param[in] info Optional additional information regarding the fault. Refer to each Fault identifier for details. + * + * @note When id is set to @ref NRF_FAULT_ID_APP_MEMACC, pc will contain the address of the instruction being executed at the time when + * the fault is detected by the CPU. The CPU program counter may have advanced up to 2 instructions (no branching) after the one that triggered the fault. + */ +typedef void (*nrf_fault_handler_t)(uint32_t id, uint32_t pc, uint32_t info); + +/** @} */ + +/** @addtogroup NRF_SDM_FUNCTIONS Functions + * @{ */ + +/**@brief Enables the SoftDevice and by extension the protocol stack. + * + * @note Some care must be taken if a low frequency clock source is already running when calling this function: + * If the LF clock has a different source then the one currently running, it will be stopped. Then, the new + * clock source will be started. + * + * @note This function has no effect when returning with an error. + * + * @post If return code is ::NRF_SUCCESS + * - SoC library and protocol stack APIs are made available. + * - A portion of RAM will be unavailable (see relevant SDS documentation). + * - Some peripherals will be unavailable or available only through the SoC API (see relevant SDS documentation). + * - Interrupts will not arrive from protected peripherals or interrupts. + * - nrf_nvic_ functions must be used instead of CMSIS NVIC_ functions for reliable usage of the SoftDevice. + * - Interrupt latency may be affected by the SoftDevice (see relevant SDS documentation). + * - Chosen low frequency clock source will be running. + * + * @param p_clock_lf_cfg Low frequency clock source and accuracy. + If NULL the clock will be configured as an RC source with rc_ctiv = 16 and .rc_temp_ctiv = 2 + In the case of XTAL source, the PPM accuracy of the chosen clock source must be greater than or equal to the actual characteristics of your XTAL clock. + * @param fault_handler Callback to be invoked in case of fault, cannot be NULL. + * + * @retval ::NRF_SUCCESS + * @retval ::NRF_ERROR_INVALID_ADDR Invalid or NULL pointer supplied. + * @retval ::NRF_ERROR_INVALID_STATE SoftDevice is already enabled, and the clock source and fault handler cannot be updated. + * @retval ::NRF_ERROR_SDM_INCORRECT_INTERRUPT_CONFIGURATION SoftDevice interrupt is already enabled, or an enabled interrupt has an illegal priority level. + * @retval ::NRF_ERROR_SDM_LFCLK_SOURCE_UNKNOWN Unknown low frequency clock source selected. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid clock source configuration supplied in p_clock_lf_cfg. + */ +SVCALL(SD_SOFTDEVICE_ENABLE, uint32_t, sd_softdevice_enable(nrf_clock_lf_cfg_t const * p_clock_lf_cfg, nrf_fault_handler_t fault_handler)); + + +/**@brief Disables the SoftDevice and by extension the protocol stack. + * + * Idempotent function to disable the SoftDevice. + * + * @post SoC library and protocol stack APIs are made unavailable. + * @post All interrupts that was protected by the SoftDevice will be disabled and initialized to priority 0 (highest). + * @post All peripherals used by the SoftDevice will be reset to default values. + * @post All of RAM become available. + * @post All interrupts are forwarded to the application. + * @post LFCLK source chosen in ::sd_softdevice_enable will be left running. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_SOFTDEVICE_DISABLE, uint32_t, sd_softdevice_disable(void)); + +/**@brief Check if the SoftDevice is enabled. + * + * @param[out] p_softdevice_enabled If the SoftDevice is enabled: 1 else 0. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_SOFTDEVICE_IS_ENABLED, uint32_t, sd_softdevice_is_enabled(uint8_t * p_softdevice_enabled)); + +/**@brief Sets the base address of the interrupt vector table for interrupts forwarded from the SoftDevice + * + * This function is only intended to be called when a bootloader is enabled. + * + * @param[in] address The base address of the interrupt vector table for forwarded interrupts. + + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_SOFTDEVICE_VECTOR_TABLE_BASE_SET, uint32_t, sd_softdevice_vector_table_base_set(uint32_t address)); + +/** @} */ + +#ifdef __cplusplus +} +#endif +#endif // NRF_SDM_H__ + +/** + @} +*/ diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_soc.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_soc.h new file mode 100755 index 00000000..beb4d3a5 --- /dev/null +++ b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_soc.h @@ -0,0 +1,1079 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @defgroup nrf_soc_api SoC Library API + * @{ + * + * @brief APIs for the SoC library. + * + */ + +#ifndef NRF_SOC_H__ +#define NRF_SOC_H__ + +#include <stdint.h> +#include "nrf.h" +#include "nrf_svc.h" +#include "nrf_error.h" +#include "nrf_error_soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/**@addtogroup NRF_SOC_DEFINES Defines + * @{ */ + +/**@brief The number of the lowest SVC number reserved for the SoC library. */ +#define SOC_SVC_BASE (0x20) /**< Base value for SVCs that are available when the SoftDevice is disabled. */ +#define SOC_SVC_BASE_NOT_AVAILABLE (0x2C) /**< Base value for SVCs that are not available when the SoftDevice is disabled. */ + +/**@brief Guaranteed time for application to process radio inactive notification. */ +#define NRF_RADIO_NOTIFICATION_INACTIVE_GUARANTEED_TIME_US (62) + +/**@brief The minimum allowed timeslot extension time. */ +#define NRF_RADIO_MINIMUM_TIMESLOT_LENGTH_EXTENSION_TIME_US (200) + +/**@brief The maximum processing time to handle a timeslot extension. */ +#define NRF_RADIO_MAX_EXTENSION_PROCESSING_TIME_US (17) + +/**@brief The latest time before the end of a timeslot the timeslot can be extended. */ +#define NRF_RADIO_MIN_EXTENSION_MARGIN_US (79) + +#define SOC_ECB_KEY_LENGTH (16) /**< ECB key length. */ +#define SOC_ECB_CLEARTEXT_LENGTH (16) /**< ECB cleartext length. */ +#define SOC_ECB_CIPHERTEXT_LENGTH (SOC_ECB_CLEARTEXT_LENGTH) /**< ECB ciphertext length. */ + +#define SD_EVT_IRQn (SWI2_IRQn) /**< SoftDevice Event IRQ number. Used for both protocol events and SoC events. */ +#define SD_EVT_IRQHandler (SWI2_IRQHandler) /**< SoftDevice Event IRQ handler. Used for both protocol events and SoC events. + The default interrupt priority for this handler is set to 6 */ +#define RADIO_NOTIFICATION_IRQn (SWI1_IRQn) /**< The radio notification IRQ number. */ +#define RADIO_NOTIFICATION_IRQHandler (SWI1_IRQHandler) /**< The radio notification IRQ handler. + The default interrupt priority for this handler is set to 6 */ +#define NRF_RADIO_LENGTH_MIN_US (100) /**< The shortest allowed radio timeslot, in microseconds. */ +#define NRF_RADIO_LENGTH_MAX_US (100000) /**< The longest allowed radio timeslot, in microseconds. */ + +#define NRF_RADIO_DISTANCE_MAX_US (128000000UL - 1UL) /**< The longest timeslot distance, in microseconds, allowed for the distance parameter (see @ref nrf_radio_request_normal_t) in the request. */ + +#define NRF_RADIO_EARLIEST_TIMEOUT_MAX_US (128000000UL - 1UL) /**< The longest timeout, in microseconds, allowed when requesting the earliest possible timeslot. */ + +#define NRF_RADIO_START_JITTER_US (2) /**< The maximum jitter in @ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START relative to the requested start time. */ + +/**@brief Mask of PPI channels reserved by the SoftDevice when the SoftDevice is disabled. */ +#define NRF_SOC_SD_PPI_CHANNELS_SD_DISABLED_MSK ((uint32_t)(0)) + +/**@brief Mask of PPI channels reserved by the SoftDevice when the SoftDevice is enabled. */ +#define NRF_SOC_SD_PPI_CHANNELS_SD_ENABLED_MSK ((uint32_t)( \ + (1U << 17) \ + | (1U << 18) \ + | (1U << 19) \ + | (1U << 20) \ + | (1U << 21) \ + | (1U << 22) \ + | (1U << 23) \ + | (1U << 24) \ + | (1U << 25) \ + | (1U << 26) \ + | (1U << 27) \ + | (1U << 28) \ + | (1U << 29) \ + | (1U << 30) \ + | (1U << 31) \ + )) + +/**@brief Mask of PPI channels available to the application when the SoftDevice is disabled. */ +#define NRF_SOC_APP_PPI_CHANNELS_SD_DISABLED_MSK (~NRF_SOC_SD_PPI_CHANNELS_SD_DISABLED_MSK) + +/**@brief Mask of PPI channels available to the application when the SoftDevice is enabled. */ +#define NRF_SOC_APP_PPI_CHANNELS_SD_ENABLED_MSK (~NRF_SOC_SD_PPI_CHANNELS_SD_ENABLED_MSK) + +/**@brief Mask of PPI groups reserved by the SoftDevice when the SoftDevice is disabled. */ +#define NRF_SOC_SD_PPI_GROUPS_SD_DISABLED_MSK ((uint32_t)(0)) + +/**@brief Mask of PPI groups reserved by the SoftDevice when the SoftDevice is enabled. */ +#define NRF_SOC_SD_PPI_GROUPS_SD_ENABLED_MSK ((uint32_t)( \ + (1U << 4) \ + | (1U << 5) \ + )) + +/**@brief Mask of PPI groups available to the application when the SoftDevice is disabled. */ +#define NRF_SOC_APP_PPI_GROUPS_SD_DISABLED_MSK (~NRF_SOC_SD_PPI_GROUPS_SD_DISABLED_MSK) + +/**@brief Mask of PPI groups available to the application when the SoftDevice is enabled. */ +#define NRF_SOC_APP_PPI_GROUPS_SD_ENABLED_MSK (~NRF_SOC_SD_PPI_GROUPS_SD_ENABLED_MSK) + +/**@} */ + +/**@addtogroup NRF_SOC_ENUMS Enumerations + * @{ */ + +/**@brief The SVC numbers used by the SVC functions in the SoC library. */ +enum NRF_SOC_SVCS +{ + SD_PPI_CHANNEL_ENABLE_GET = SOC_SVC_BASE, + SD_PPI_CHANNEL_ENABLE_SET = SOC_SVC_BASE + 1, + SD_PPI_CHANNEL_ENABLE_CLR = SOC_SVC_BASE + 2, + SD_PPI_CHANNEL_ASSIGN = SOC_SVC_BASE + 3, + SD_PPI_GROUP_TASK_ENABLE = SOC_SVC_BASE + 4, + SD_PPI_GROUP_TASK_DISABLE = SOC_SVC_BASE + 5, + SD_PPI_GROUP_ASSIGN = SOC_SVC_BASE + 6, + SD_PPI_GROUP_GET = SOC_SVC_BASE + 7, + SD_FLASH_PAGE_ERASE = SOC_SVC_BASE + 8, + SD_FLASH_WRITE = SOC_SVC_BASE + 9, + SD_PROTECTED_REGISTER_WRITE = SOC_SVC_BASE + 11, + SD_MUTEX_NEW = SOC_SVC_BASE_NOT_AVAILABLE, + SD_MUTEX_ACQUIRE = SOC_SVC_BASE_NOT_AVAILABLE + 1, + SD_MUTEX_RELEASE = SOC_SVC_BASE_NOT_AVAILABLE + 2, + SD_RAND_APPLICATION_POOL_CAPACITY_GET = SOC_SVC_BASE_NOT_AVAILABLE + 3, + SD_RAND_APPLICATION_BYTES_AVAILABLE_GET = SOC_SVC_BASE_NOT_AVAILABLE + 4, + SD_RAND_APPLICATION_VECTOR_GET = SOC_SVC_BASE_NOT_AVAILABLE + 5, + SD_POWER_MODE_SET = SOC_SVC_BASE_NOT_AVAILABLE + 6, + SD_POWER_SYSTEM_OFF = SOC_SVC_BASE_NOT_AVAILABLE + 7, + SD_POWER_RESET_REASON_GET = SOC_SVC_BASE_NOT_AVAILABLE + 8, + SD_POWER_RESET_REASON_CLR = SOC_SVC_BASE_NOT_AVAILABLE + 9, + SD_POWER_POF_ENABLE = SOC_SVC_BASE_NOT_AVAILABLE + 10, + SD_POWER_POF_THRESHOLD_SET = SOC_SVC_BASE_NOT_AVAILABLE + 11, + SD_POWER_POF_THRESHOLDVDDH_SET = SOC_SVC_BASE_NOT_AVAILABLE + 12, + SD_POWER_RAM_POWER_SET = SOC_SVC_BASE_NOT_AVAILABLE + 13, + SD_POWER_RAM_POWER_CLR = SOC_SVC_BASE_NOT_AVAILABLE + 14, + SD_POWER_RAM_POWER_GET = SOC_SVC_BASE_NOT_AVAILABLE + 15, + SD_POWER_GPREGRET_SET = SOC_SVC_BASE_NOT_AVAILABLE + 16, + SD_POWER_GPREGRET_CLR = SOC_SVC_BASE_NOT_AVAILABLE + 17, + SD_POWER_GPREGRET_GET = SOC_SVC_BASE_NOT_AVAILABLE + 18, + SD_POWER_DCDC_MODE_SET = SOC_SVC_BASE_NOT_AVAILABLE + 19, + SD_POWER_DCDC0_MODE_SET = SOC_SVC_BASE_NOT_AVAILABLE + 20, + SD_APP_EVT_WAIT = SOC_SVC_BASE_NOT_AVAILABLE + 21, + SD_CLOCK_HFCLK_REQUEST = SOC_SVC_BASE_NOT_AVAILABLE + 22, + SD_CLOCK_HFCLK_RELEASE = SOC_SVC_BASE_NOT_AVAILABLE + 23, + SD_CLOCK_HFCLK_IS_RUNNING = SOC_SVC_BASE_NOT_AVAILABLE + 24, + SD_RADIO_NOTIFICATION_CFG_SET = SOC_SVC_BASE_NOT_AVAILABLE + 25, + SD_ECB_BLOCK_ENCRYPT = SOC_SVC_BASE_NOT_AVAILABLE + 26, + SD_ECB_BLOCKS_ENCRYPT = SOC_SVC_BASE_NOT_AVAILABLE + 27, + SD_RADIO_SESSION_OPEN = SOC_SVC_BASE_NOT_AVAILABLE + 28, + SD_RADIO_SESSION_CLOSE = SOC_SVC_BASE_NOT_AVAILABLE + 29, + SD_RADIO_REQUEST = SOC_SVC_BASE_NOT_AVAILABLE + 30, + SD_EVT_GET = SOC_SVC_BASE_NOT_AVAILABLE + 31, + SD_TEMP_GET = SOC_SVC_BASE_NOT_AVAILABLE + 32, + SD_POWER_USBPWRRDY_ENABLE = SOC_SVC_BASE_NOT_AVAILABLE + 33, + SD_POWER_USBDETECTED_ENABLE = SOC_SVC_BASE_NOT_AVAILABLE + 34, + SD_POWER_USBREMOVED_ENABLE = SOC_SVC_BASE_NOT_AVAILABLE + 35, + SD_POWER_USBREGSTATUS_GET = SOC_SVC_BASE_NOT_AVAILABLE + 36, + SVC_SOC_LAST = SOC_SVC_BASE_NOT_AVAILABLE + 37 +}; + +/**@brief Possible values of a ::nrf_mutex_t. */ +enum NRF_MUTEX_VALUES +{ + NRF_MUTEX_FREE, + NRF_MUTEX_TAKEN +}; + +/**@brief Power modes. */ +enum NRF_POWER_MODES +{ + NRF_POWER_MODE_CONSTLAT, /**< Constant latency mode. See power management in the reference manual. */ + NRF_POWER_MODE_LOWPWR /**< Low power mode. See power management in the reference manual. */ +}; + + +/**@brief Power failure thresholds */ +enum NRF_POWER_THRESHOLDS +{ + NRF_POWER_THRESHOLD_V17 = 4UL, /**< 1.7 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V18, /**< 1.8 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V19, /**< 1.9 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V20, /**< 2.0 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V21, /**< 2.1 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V22, /**< 2.2 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V23, /**< 2.3 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V24, /**< 2.4 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V25, /**< 2.5 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V26, /**< 2.6 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V27, /**< 2.7 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V28 /**< 2.8 Volts power failure threshold. */ +}; + +/**@brief Power failure thresholds for high voltage */ +enum NRF_POWER_THRESHOLDVDDHS +{ + NRF_POWER_THRESHOLDVDDH_V27, /**< 2.7 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V28, /**< 2.8 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V29, /**< 2.9 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V30, /**< 3.0 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V31, /**< 3.1 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V32, /**< 3.2 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V33, /**< 3.3 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V34, /**< 3.4 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V35, /**< 3.5 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V36, /**< 3.6 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V37, /**< 3.7 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V38, /**< 3.8 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V39, /**< 3.9 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V40, /**< 4.0 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V41, /**< 4.1 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V42 /**< 4.2 Volts power failure threshold. */ +}; + + +/**@brief DC/DC converter modes. */ +enum NRF_POWER_DCDC_MODES +{ + NRF_POWER_DCDC_DISABLE, /**< The DCDC is disabled. */ + NRF_POWER_DCDC_ENABLE /**< The DCDC is enabled. */ +}; + +/**@brief Radio notification distances. */ +enum NRF_RADIO_NOTIFICATION_DISTANCES +{ + NRF_RADIO_NOTIFICATION_DISTANCE_NONE = 0, /**< The event does not have a notification. */ + NRF_RADIO_NOTIFICATION_DISTANCE_800US, /**< The distance from the active notification to start of radio activity. */ + NRF_RADIO_NOTIFICATION_DISTANCE_1740US, /**< The distance from the active notification to start of radio activity. */ + NRF_RADIO_NOTIFICATION_DISTANCE_2680US, /**< The distance from the active notification to start of radio activity. */ + NRF_RADIO_NOTIFICATION_DISTANCE_3620US, /**< The distance from the active notification to start of radio activity. */ + NRF_RADIO_NOTIFICATION_DISTANCE_4560US, /**< The distance from the active notification to start of radio activity. */ + NRF_RADIO_NOTIFICATION_DISTANCE_5500US /**< The distance from the active notification to start of radio activity. */ +}; + + +/**@brief Radio notification types. */ +enum NRF_RADIO_NOTIFICATION_TYPES +{ + NRF_RADIO_NOTIFICATION_TYPE_NONE = 0, /**< The event does not have a radio notification signal. */ + NRF_RADIO_NOTIFICATION_TYPE_INT_ON_ACTIVE, /**< Using interrupt for notification when the radio will be enabled. */ + NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE, /**< Using interrupt for notification when the radio has been disabled. */ + NRF_RADIO_NOTIFICATION_TYPE_INT_ON_BOTH, /**< Using interrupt for notification both when the radio will be enabled and disabled. */ +}; + +/**@brief The Radio signal callback types. */ +enum NRF_RADIO_CALLBACK_SIGNAL_TYPE +{ + NRF_RADIO_CALLBACK_SIGNAL_TYPE_START, /**< This signal indicates the start of the radio timeslot. */ + NRF_RADIO_CALLBACK_SIGNAL_TYPE_TIMER0, /**< This signal indicates the NRF_TIMER0 interrupt. */ + NRF_RADIO_CALLBACK_SIGNAL_TYPE_RADIO, /**< This signal indicates the NRF_RADIO interrupt. */ + NRF_RADIO_CALLBACK_SIGNAL_TYPE_EXTEND_FAILED, /**< This signal indicates extend action failed. */ + NRF_RADIO_CALLBACK_SIGNAL_TYPE_EXTEND_SUCCEEDED /**< This signal indicates extend action succeeded. */ +}; + +/**@brief The actions requested by the signal callback. + * + * This code gives the SOC instructions about what action to take when the signal callback has + * returned. + */ +enum NRF_RADIO_SIGNAL_CALLBACK_ACTION +{ + NRF_RADIO_SIGNAL_CALLBACK_ACTION_NONE, /**< Return without action. */ + NRF_RADIO_SIGNAL_CALLBACK_ACTION_EXTEND, /**< Request an extension of the current + timeslot. Maximum execution time for this action: + @ref NRF_RADIO_MAX_EXTENSION_PROCESSING_TIME_US. + This action must be started at least + @ref NRF_RADIO_MIN_EXTENSION_MARGIN_US before + the end of the timeslot. */ + NRF_RADIO_SIGNAL_CALLBACK_ACTION_END, /**< End the current radio timeslot. */ + NRF_RADIO_SIGNAL_CALLBACK_ACTION_REQUEST_AND_END /**< Request a new radio timeslot and end the current timeslot. */ +}; + +/**@brief Radio timeslot high frequency clock source configuration. */ +enum NRF_RADIO_HFCLK_CFG +{ + NRF_RADIO_HFCLK_CFG_XTAL_GUARANTEED, /**< The SoftDevice will guarantee that the high frequency clock source is the + external crystal for the whole duration of the timeslot. This should be the + preferred option for events that use the radio or require high timing accuracy. + @note The SoftDevice will automatically turn on and off the external crystal, + at the beginning and end of the timeslot, respectively. The crystal may also + intentionally be left running after the timeslot, in cases where it is needed + by the SoftDevice shortly after the end of the timeslot. */ + NRF_RADIO_HFCLK_CFG_NO_GUARANTEE /**< This configuration allows for earlier and tighter scheduling of timeslots. + The RC oscillator may be the clock source in part or for the whole duration of the timeslot. + The RC oscillator's accuracy must therefore be taken into consideration. + @note If the application will use the radio peripheral in timeslots with this configuration, + it must make sure that the crystal is running and stable before starting the radio. */ +}; + +/**@brief Radio timeslot priorities. */ +enum NRF_RADIO_PRIORITY +{ + NRF_RADIO_PRIORITY_HIGH, /**< High (equal priority as the normal connection priority of the SoftDevice stack(s)). */ + NRF_RADIO_PRIORITY_NORMAL, /**< Normal (equal priority as the priority of secondary activities of the SoftDevice stack(s)). */ +}; + +/**@brief Radio timeslot request type. */ +enum NRF_RADIO_REQUEST_TYPE +{ + NRF_RADIO_REQ_TYPE_EARLIEST, /**< Request radio timeslot as early as possible. This should always be used for the first request in a session. */ + NRF_RADIO_REQ_TYPE_NORMAL /**< Normal radio timeslot request. */ +}; + +/**@brief SoC Events. */ +enum NRF_SOC_EVTS +{ + NRF_EVT_HFCLKSTARTED, /**< Event indicating that the HFCLK has started. */ + NRF_EVT_POWER_FAILURE_WARNING, /**< Event indicating that a power failure warning has occurred. */ + NRF_EVT_FLASH_OPERATION_SUCCESS, /**< Event indicating that the ongoing flash operation has completed successfully. */ + NRF_EVT_FLASH_OPERATION_ERROR, /**< Event indicating that the ongoing flash operation has timed out with an error. */ + NRF_EVT_RADIO_BLOCKED, /**< Event indicating that a radio timeslot was blocked. */ + NRF_EVT_RADIO_CANCELED, /**< Event indicating that a radio timeslot was canceled by SoftDevice. */ + NRF_EVT_RADIO_SIGNAL_CALLBACK_INVALID_RETURN, /**< Event indicating that a radio timeslot signal callback handler return was invalid. */ + NRF_EVT_RADIO_SESSION_IDLE, /**< Event indicating that a radio timeslot session is idle. */ + NRF_EVT_RADIO_SESSION_CLOSED, /**< Event indicating that a radio timeslot session is closed. */ + NRF_EVT_POWER_USB_POWER_READY, /**< Event indicating that a USB 3.3 V supply is ready. */ + NRF_EVT_POWER_USB_DETECTED, /**< Event indicating that voltage supply is detected on VBUS. */ + NRF_EVT_POWER_USB_REMOVED, /**< Event indicating that voltage supply is removed from VBUS. */ + NRF_EVT_NUMBER_OF_EVTS +}; + +/**@} */ + + +/**@addtogroup NRF_SOC_STRUCTURES Structures + * @{ */ + +/**@brief Represents a mutex for use with the nrf_mutex functions. + * @note Accessing the value directly is not safe, use the mutex functions! + */ +typedef volatile uint8_t nrf_mutex_t; + +/**@brief Parameters for a request for a timeslot as early as possible. */ +typedef struct +{ + uint8_t hfclk; /**< High frequency clock source, see @ref NRF_RADIO_HFCLK_CFG. */ + uint8_t priority; /**< The radio timeslot priority, see @ref NRF_RADIO_PRIORITY. */ + uint32_t length_us; /**< The radio timeslot length (in the range 100 to 100,000] microseconds). */ + uint32_t timeout_us; /**< Longest acceptable delay until the start of the requested timeslot (up to @ref NRF_RADIO_EARLIEST_TIMEOUT_MAX_US microseconds). */ +} nrf_radio_request_earliest_t; + +/**@brief Parameters for a normal radio timeslot request. */ +typedef struct +{ + uint8_t hfclk; /**< High frequency clock source, see @ref NRF_RADIO_HFCLK_CFG. */ + uint8_t priority; /**< The radio timeslot priority, see @ref NRF_RADIO_PRIORITY. */ + uint32_t distance_us; /**< Distance from the start of the previous radio timeslot (up to @ref NRF_RADIO_DISTANCE_MAX_US microseconds). */ + uint32_t length_us; /**< The radio timeslot length (in the range [100..100,000] microseconds). */ +} nrf_radio_request_normal_t; + +/**@brief Radio timeslot request parameters. */ +typedef struct +{ + uint8_t request_type; /**< Type of request, see @ref NRF_RADIO_REQUEST_TYPE. */ + union + { + nrf_radio_request_earliest_t earliest; /**< Parameters for requesting a radio timeslot as early as possible. */ + nrf_radio_request_normal_t normal; /**< Parameters for requesting a normal radio timeslot. */ + } params; /**< Parameter union. */ +} nrf_radio_request_t; + +/**@brief Return parameters of the radio timeslot signal callback. */ +typedef struct +{ + uint8_t callback_action; /**< The action requested by the application when returning from the signal callback, see @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION. */ + union + { + struct + { + nrf_radio_request_t * p_next; /**< The request parameters for the next radio timeslot. */ + } request; /**< Additional parameters for return_code @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION_REQUEST_AND_END. */ + struct + { + uint32_t length_us; /**< Requested extension of the radio timeslot duration (microseconds) (for minimum time see @ref NRF_RADIO_MINIMUM_TIMESLOT_LENGTH_EXTENSION_TIME_US). */ + } extend; /**< Additional parameters for return_code @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION_EXTEND. */ + } params; /**< Parameter union. */ +} nrf_radio_signal_callback_return_param_t; + +/**@brief The radio timeslot signal callback type. + * + * @note In case of invalid return parameters, the radio timeslot will automatically end + * immediately after returning from the signal callback and the + * @ref NRF_EVT_RADIO_SIGNAL_CALLBACK_INVALID_RETURN event will be sent. + * @note The returned struct pointer must remain valid after the signal callback + * function returns. For instance, this means that it must not point to a stack variable. + * + * @param[in] signal_type Type of signal, see @ref NRF_RADIO_CALLBACK_SIGNAL_TYPE. + * + * @return Pointer to structure containing action requested by the application. + */ +typedef nrf_radio_signal_callback_return_param_t * (*nrf_radio_signal_callback_t) (uint8_t signal_type); + +/**@brief AES ECB parameter typedefs */ +typedef uint8_t soc_ecb_key_t[SOC_ECB_KEY_LENGTH]; /**< Encryption key type. */ +typedef uint8_t soc_ecb_cleartext_t[SOC_ECB_CLEARTEXT_LENGTH]; /**< Cleartext data type. */ +typedef uint8_t soc_ecb_ciphertext_t[SOC_ECB_CIPHERTEXT_LENGTH]; /**< Ciphertext data type. */ + +/**@brief AES ECB data structure */ +typedef struct +{ + soc_ecb_key_t key; /**< Encryption key. */ + soc_ecb_cleartext_t cleartext; /**< Cleartext data. */ + soc_ecb_ciphertext_t ciphertext; /**< Ciphertext data. */ +} nrf_ecb_hal_data_t; + +/**@brief AES ECB block. Used to provide multiple blocks in a single call + to @ref sd_ecb_blocks_encrypt.*/ +typedef struct +{ + soc_ecb_key_t const * p_key; /**< Pointer to the Encryption key. */ + soc_ecb_cleartext_t const * p_cleartext; /**< Pointer to the Cleartext data. */ + soc_ecb_ciphertext_t * p_ciphertext; /**< Pointer to the Ciphertext data. */ +} nrf_ecb_hal_data_block_t; + +/**@} */ + +/**@addtogroup NRF_SOC_FUNCTIONS Functions + * @{ */ + +/**@brief Initialize a mutex. + * + * @param[in] p_mutex Pointer to the mutex to initialize. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_MUTEX_NEW, uint32_t, sd_mutex_new(nrf_mutex_t * p_mutex)); + +/**@brief Attempt to acquire a mutex. + * + * @param[in] p_mutex Pointer to the mutex to acquire. + * + * @retval ::NRF_SUCCESS The mutex was successfully acquired. + * @retval ::NRF_ERROR_SOC_MUTEX_ALREADY_TAKEN The mutex could not be acquired. + */ +SVCALL(SD_MUTEX_ACQUIRE, uint32_t, sd_mutex_acquire(nrf_mutex_t * p_mutex)); + +/**@brief Release a mutex. + * + * @param[in] p_mutex Pointer to the mutex to release. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_MUTEX_RELEASE, uint32_t, sd_mutex_release(nrf_mutex_t * p_mutex)); + +/**@brief Query the capacity of the application random pool. + * + * @param[out] p_pool_capacity The capacity of the pool. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_RAND_APPLICATION_POOL_CAPACITY_GET, uint32_t, sd_rand_application_pool_capacity_get(uint8_t * p_pool_capacity)); + +/**@brief Get number of random bytes available to the application. + * + * @param[out] p_bytes_available The number of bytes currently available in the pool. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_RAND_APPLICATION_BYTES_AVAILABLE_GET, uint32_t, sd_rand_application_bytes_available_get(uint8_t * p_bytes_available)); + +/**@brief Get random bytes from the application pool. + * + * @param[out] p_buff Pointer to unit8_t buffer for storing the bytes. + * @param[in] length Number of bytes to take from pool and place in p_buff. + * + * @retval ::NRF_SUCCESS The requested bytes were written to p_buff. + * @retval ::NRF_ERROR_SOC_RAND_NOT_ENOUGH_VALUES No bytes were written to the buffer, because there were not enough bytes available. +*/ +SVCALL(SD_RAND_APPLICATION_VECTOR_GET, uint32_t, sd_rand_application_vector_get(uint8_t * p_buff, uint8_t length)); + +/**@brief Gets the reset reason register. + * + * @param[out] p_reset_reason Contents of the NRF_POWER->RESETREAS register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_RESET_REASON_GET, uint32_t, sd_power_reset_reason_get(uint32_t * p_reset_reason)); + +/**@brief Clears the bits of the reset reason register. + * + * @param[in] reset_reason_clr_msk Contains the bits to clear from the reset reason register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_RESET_REASON_CLR, uint32_t, sd_power_reset_reason_clr(uint32_t reset_reason_clr_msk)); + +/**@brief Sets the power mode when in CPU sleep. + * + * @param[in] power_mode The power mode to use when in CPU sleep, see @ref NRF_POWER_MODES. @sa sd_app_evt_wait + * + * @retval ::NRF_SUCCESS The power mode was set. + * @retval ::NRF_ERROR_SOC_POWER_MODE_UNKNOWN The power mode was unknown. + */ +SVCALL(SD_POWER_MODE_SET, uint32_t, sd_power_mode_set(uint8_t power_mode)); + +/**@brief Puts the chip in System OFF mode. + * + * @retval ::NRF_ERROR_SOC_POWER_OFF_SHOULD_NOT_RETURN + */ +SVCALL(SD_POWER_SYSTEM_OFF, uint32_t, sd_power_system_off(void)); + +/**@brief Enables or disables the power-fail comparator. + * + * Enabling this will give a SoftDevice event (NRF_EVT_POWER_FAILURE_WARNING) when the power failure warning occurs. + * The event can be retrieved with sd_evt_get(); + * + * @param[in] pof_enable True if the power-fail comparator should be enabled, false if it should be disabled. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_POF_ENABLE, uint32_t, sd_power_pof_enable(uint8_t pof_enable)); + +/**@brief Enables or disables the USB power ready event. + * + * Enabling this will give a SoftDevice event (NRF_EVT_POWER_USB_POWER_READY) when a USB 3.3 V supply is ready. + * The event can be retrieved with sd_evt_get(); + * + * @param[in] usbpwrrdy_enable True if the power ready event should be enabled, false if it should be disabled. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_USBPWRRDY_ENABLE, uint32_t, sd_power_usbpwrrdy_enable(uint8_t usbpwrrdy_enable)); + +/**@brief Enables or disables the power USB-detected event. + * + * Enabling this will give a SoftDevice event (NRF_EVT_POWER_USB_DETECTED) when a voltage supply is detected on VBUS. + * The event can be retrieved with sd_evt_get(); + * + * @param[in] usbdetected_enable True if the power ready event should be enabled, false if it should be disabled. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_USBDETECTED_ENABLE, uint32_t, sd_power_usbdetected_enable(uint8_t usbdetected_enable)); + +/**@brief Enables or disables the power USB-removed event. + * + * Enabling this will give a SoftDevice event (NRF_EVT_POWER_USB_REMOVED) when a voltage supply is removed from VBUS. + * The event can be retrieved with sd_evt_get(); + * + * @param[in] usbremoved_enable True if the power ready event should be enabled, false if it should be disabled. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_USBREMOVED_ENABLE, uint32_t, sd_power_usbremoved_enable(uint8_t usbremoved_enable)); + +/**@brief Get USB supply status register content. + * + * @param[out] usbregstatus The content of USBREGSTATUS register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_USBREGSTATUS_GET, uint32_t, sd_power_usbregstatus_get(uint32_t * usbregstatus)); + +/**@brief Sets the power failure comparator threshold value. + * + * @note: Power failure comparator threshold setting. This setting applies both for normal voltage + * mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to + * VDDH only). + * + * @param[in] threshold The power-fail threshold value to use, see @ref NRF_POWER_THRESHOLDS. + * + * @retval ::NRF_SUCCESS The power failure threshold was set. + * @retval ::NRF_ERROR_SOC_POWER_POF_THRESHOLD_UNKNOWN The power failure threshold is unknown. + */ +SVCALL(SD_POWER_POF_THRESHOLD_SET, uint32_t, sd_power_pof_threshold_set(uint8_t threshold)); + +/**@brief Sets the power failure comparator threshold value for high voltage. + * + * @note: Power failure comparator threshold setting for high voltage mode (supply connected to + * VDDH only). This setting does not apply for normal voltage mode (supply connected to both + * VDD and VDDH). + * + * @param[in] threshold The power-fail threshold value to use, see @ref NRF_POWER_THRESHOLDVDDHS. + * + * @retval ::NRF_SUCCESS The power failure threshold was set. + * @retval ::NRF_ERROR_SOC_POWER_POF_THRESHOLD_UNKNOWN The power failure threshold is unknown. + */ +SVCALL(SD_POWER_POF_THRESHOLDVDDH_SET, uint32_t, sd_power_pof_thresholdvddh_set(uint8_t threshold)); + +/**@brief Writes the NRF_POWER->RAM[index].POWERSET register. + * + * @param[in] index Contains the index in the NRF_POWER->RAM[index].POWERSET register to write to. + * @param[in] ram_powerset Contains the word to write to the NRF_POWER->RAM[index].POWERSET register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_RAM_POWER_SET, uint32_t, sd_power_ram_power_set(uint8_t index, uint32_t ram_powerset)); + +/**@brief Writes the NRF_POWER->RAM[index].POWERCLR register. + * + * @param[in] index Contains the index in the NRF_POWER->RAM[index].POWERCLR register to write to. + * @param[in] ram_powerclr Contains the word to write to the NRF_POWER->RAM[index].POWERCLR register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_RAM_POWER_CLR, uint32_t, sd_power_ram_power_clr(uint8_t index, uint32_t ram_powerclr)); + +/**@brief Get contents of NRF_POWER->RAM[index].POWER register, indicates power status of RAM[index] blocks. + * + * @param[in] index Contains the index in the NRF_POWER->RAM[index].POWER register to read from. + * @param[out] p_ram_power Content of NRF_POWER->RAM[index].POWER register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_RAM_POWER_GET, uint32_t, sd_power_ram_power_get(uint8_t index, uint32_t * p_ram_power)); + +/**@brief Set bits in the general purpose retention registers (NRF_POWER->GPREGRET*). + * + * @param[in] gpregret_id 0 for GPREGRET, 1 for GPREGRET2. + * @param[in] gpregret_msk Bits to be set in the GPREGRET register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_GPREGRET_SET, uint32_t, sd_power_gpregret_set(uint32_t gpregret_id, uint32_t gpregret_msk)); + +/**@brief Clear bits in the general purpose retention registers (NRF_POWER->GPREGRET*). + * + * @param[in] gpregret_id 0 for GPREGRET, 1 for GPREGRET2. + * @param[in] gpregret_msk Bits to be clear in the GPREGRET register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_GPREGRET_CLR, uint32_t, sd_power_gpregret_clr(uint32_t gpregret_id, uint32_t gpregret_msk)); + +/**@brief Get contents of the general purpose retention registers (NRF_POWER->GPREGRET*). + * + * @param[in] gpregret_id 0 for GPREGRET, 1 for GPREGRET2. + * @param[out] p_gpregret Contents of the GPREGRET register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_GPREGRET_GET, uint32_t, sd_power_gpregret_get(uint32_t gpregret_id, uint32_t *p_gpregret)); + +/**@brief Enable or disable the DC/DC regulator for the regulator stage 1 (REG1). + * + * @param[in] dcdc_mode The mode of the DCDC, see @ref NRF_POWER_DCDC_MODES. + * + * @retval ::NRF_SUCCESS + * @retval ::NRF_ERROR_INVALID_PARAM The DCDC mode is invalid. + */ +SVCALL(SD_POWER_DCDC_MODE_SET, uint32_t, sd_power_dcdc_mode_set(uint8_t dcdc_mode)); + +/**@brief Enable or disable the DC/DC regulator for the regulator stage 0 (REG0). + * + * For more details on the REG0 stage, please see product specification. + * + * @param[in] dcdc_mode The mode of the DCDC0, see @ref NRF_POWER_DCDC_MODES. + * + * @retval ::NRF_SUCCESS + * @retval ::NRF_ERROR_INVALID_PARAM The dcdc_mode is invalid. + */ +SVCALL(SD_POWER_DCDC0_MODE_SET, uint32_t, sd_power_dcdc0_mode_set(uint8_t dcdc_mode)); + +/**@brief Request the high frequency crystal oscillator. + * + * Will start the high frequency crystal oscillator, the startup time of the crystal varies + * and the ::sd_clock_hfclk_is_running function can be polled to check if it has started. + * + * @see sd_clock_hfclk_is_running + * @see sd_clock_hfclk_release + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_CLOCK_HFCLK_REQUEST, uint32_t, sd_clock_hfclk_request(void)); + +/**@brief Releases the high frequency crystal oscillator. + * + * Will stop the high frequency crystal oscillator, this happens immediately. + * + * @see sd_clock_hfclk_is_running + * @see sd_clock_hfclk_request + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_CLOCK_HFCLK_RELEASE, uint32_t, sd_clock_hfclk_release(void)); + +/**@brief Checks if the high frequency crystal oscillator is running. + * + * @see sd_clock_hfclk_request + * @see sd_clock_hfclk_release + * + * @param[out] p_is_running 1 if the external crystal oscillator is running, 0 if not. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_CLOCK_HFCLK_IS_RUNNING, uint32_t, sd_clock_hfclk_is_running(uint32_t * p_is_running)); + +/**@brief Waits for an application event. + * + * An application event is either an application interrupt or a pended interrupt when the interrupt + * is disabled. + * + * When the application waits for an application event by calling this function, an interrupt that + * is enabled will be taken immediately on pending since this function will wait in thread mode, + * then the execution will return in the application's main thread. + * + * In order to wake up from disabled interrupts, the SEVONPEND flag has to be set in the Cortex-M + * MCU's System Control Register (SCR), CMSIS_SCB. In that case, when a disabled interrupt gets + * pended, this function will return to the application's main thread. + * + * @note The application must ensure that the pended flag is cleared using ::sd_nvic_ClearPendingIRQ + * in order to sleep using this function. This is only necessary for disabled interrupts, as + * the interrupt handler will clear the pending flag automatically for enabled interrupts. + * + * @note If an application interrupt has happened since the last time sd_app_evt_wait was + * called this function will return immediately and not go to sleep. This is to avoid race + * conditions that can occur when a flag is updated in the interrupt handler and processed + * in the main loop. + * + * @post An application interrupt has happened or a interrupt pending flag is set. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_APP_EVT_WAIT, uint32_t, sd_app_evt_wait(void)); + +/**@brief Get PPI channel enable register contents. + * + * @param[out] p_channel_enable The contents of the PPI CHEN register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_PPI_CHANNEL_ENABLE_GET, uint32_t, sd_ppi_channel_enable_get(uint32_t * p_channel_enable)); + +/**@brief Set PPI channel enable register. + * + * @param[in] channel_enable_set_msk Mask containing the bits to set in the PPI CHEN register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_PPI_CHANNEL_ENABLE_SET, uint32_t, sd_ppi_channel_enable_set(uint32_t channel_enable_set_msk)); + +/**@brief Clear PPI channel enable register. + * + * @param[in] channel_enable_clr_msk Mask containing the bits to clear in the PPI CHEN register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_PPI_CHANNEL_ENABLE_CLR, uint32_t, sd_ppi_channel_enable_clr(uint32_t channel_enable_clr_msk)); + +/**@brief Assign endpoints to a PPI channel. + * + * @param[in] channel_num Number of the PPI channel to assign. + * @param[in] evt_endpoint Event endpoint of the PPI channel. + * @param[in] task_endpoint Task endpoint of the PPI channel. + * + * @retval ::NRF_ERROR_SOC_PPI_INVALID_CHANNEL The channel number is invalid. + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_PPI_CHANNEL_ASSIGN, uint32_t, sd_ppi_channel_assign(uint8_t channel_num, const volatile void * evt_endpoint, const volatile void * task_endpoint)); + +/**@brief Task to enable a channel group. + * + * @param[in] group_num Number of the channel group. + * + * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_PPI_GROUP_TASK_ENABLE, uint32_t, sd_ppi_group_task_enable(uint8_t group_num)); + +/**@brief Task to disable a channel group. + * + * @param[in] group_num Number of the PPI group. + * + * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid. + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_PPI_GROUP_TASK_DISABLE, uint32_t, sd_ppi_group_task_disable(uint8_t group_num)); + +/**@brief Assign PPI channels to a channel group. + * + * @param[in] group_num Number of the channel group. + * @param[in] channel_msk Mask of the channels to assign to the group. + * + * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid. + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_PPI_GROUP_ASSIGN, uint32_t, sd_ppi_group_assign(uint8_t group_num, uint32_t channel_msk)); + +/**@brief Gets the PPI channels of a channel group. + * + * @param[in] group_num Number of the channel group. + * @param[out] p_channel_msk Mask of the channels assigned to the group. + * + * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid. + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_PPI_GROUP_GET, uint32_t, sd_ppi_group_get(uint8_t group_num, uint32_t * p_channel_msk)); + +/**@brief Configures the Radio Notification signal. + * + * @note + * - The notification signal latency depends on the interrupt priority settings of SWI used + * for notification signal. + * - To ensure that the radio notification signal behaves in a consistent way, the radio + * notifications must be configured when there is no protocol stack or other SoftDevice + * activity in progress. It is recommended that the radio notification signal is + * configured directly after the SoftDevice has been enabled. + * - In the period between the ACTIVE signal and the start of the Radio Event, the SoftDevice + * will interrupt the application to do Radio Event preparation. + * - Using the Radio Notification feature may limit the bandwidth, as the SoftDevice may have + * to shorten the connection events to have time for the Radio Notification signals. + * + * @param[in] type Type of notification signal, see @ref NRF_RADIO_NOTIFICATION_TYPES. + * @ref NRF_RADIO_NOTIFICATION_TYPE_NONE shall be used to turn off radio + * notification. Using @ref NRF_RADIO_NOTIFICATION_DISTANCE_NONE is + * recommended (but not required) to be used with + * @ref NRF_RADIO_NOTIFICATION_TYPE_NONE. + * + * @param[in] distance Distance between the notification signal and start of radio activity, see @ref NRF_RADIO_NOTIFICATION_DISTANCES. + * This parameter is ignored when @ref NRF_RADIO_NOTIFICATION_TYPE_NONE or + * @ref NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE is used. + * + * @retval ::NRF_ERROR_INVALID_PARAM The group number is invalid. + * @retval ::NRF_ERROR_INVALID_STATE A protocol stack or other SoftDevice is running. Stop all + * running activities and retry. + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_RADIO_NOTIFICATION_CFG_SET, uint32_t, sd_radio_notification_cfg_set(uint8_t type, uint8_t distance)); + +/**@brief Encrypts a block according to the specified parameters. + * + * 128-bit AES encryption. + * + * @note: + * - The application may set the SEVONPEND bit in the SCR to 1 to make the SoftDevice sleep while + * the ECB is running. The SEVONPEND bit should only be cleared (set to 0) from application + * main or low interrupt level. + * + * @param[in, out] p_ecb_data Pointer to the ECB parameters' struct (two input + * parameters and one output parameter). + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_ECB_BLOCK_ENCRYPT, uint32_t, sd_ecb_block_encrypt(nrf_ecb_hal_data_t * p_ecb_data)); + +/**@brief Encrypts multiple data blocks provided as an array of data block structures. + * + * @details: Performs 128-bit AES encryption on multiple data blocks + * + * @note: + * - The application may set the SEVONPEND bit in the SCR to 1 to make the SoftDevice sleep while + * the ECB is running. The SEVONPEND bit should only be cleared (set to 0) from application + * main or low interrupt level. + * + * @param[in] block_count Count of blocks in the p_data_blocks array. + * @param[in,out] p_data_blocks Pointer to the first entry in a contiguous array of + * @ref nrf_ecb_hal_data_block_t structures. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_ECB_BLOCKS_ENCRYPT, uint32_t, sd_ecb_blocks_encrypt(uint8_t block_count, nrf_ecb_hal_data_block_t * p_data_blocks)); + +/**@brief Gets any pending events generated by the SoC API. + * + * The application should keep calling this function to get events, until ::NRF_ERROR_NOT_FOUND is returned. + * + * @param[out] p_evt_id Set to one of the values in @ref NRF_SOC_EVTS, if any events are pending. + * + * @retval ::NRF_SUCCESS An event was pending. The event id is written in the p_evt_id parameter. + * @retval ::NRF_ERROR_NOT_FOUND No pending events. + */ +SVCALL(SD_EVT_GET, uint32_t, sd_evt_get(uint32_t * p_evt_id)); + +/**@brief Get the temperature measured on the chip + * + * This function will block until the temperature measurement is done. + * It takes around 50 us from call to return. + * + * @param[out] p_temp Result of temperature measurement. Die temperature in 0.25 degrees Celsius. + * + * @retval ::NRF_SUCCESS A temperature measurement was done, and the temperature was written to temp + */ +SVCALL(SD_TEMP_GET, uint32_t, sd_temp_get(int32_t * p_temp)); + +/**@brief Flash Write +* +* Commands to write a buffer to flash +* +* If the SoftDevice is enabled: +* This call initiates the flash access command, and its completion will be communicated to the +* application with exactly one of the following events: +* - @ref NRF_EVT_FLASH_OPERATION_SUCCESS - The command was successfully completed. +* - @ref NRF_EVT_FLASH_OPERATION_ERROR - The command could not be started. +* +* If the SoftDevice is not enabled no event will be generated, and this call will return @ref NRF_SUCCESS when the + * write has been completed +* +* @note +* - This call takes control over the radio and the CPU during flash erase and write to make sure that +* they will not interfere with the flash access. This means that all interrupts will be blocked +* for a predictable time (depending on the NVMC specification in the device's Product Specification +* and the command parameters). +* - The data in the p_src buffer should not be modified before the @ref NRF_EVT_FLASH_OPERATION_SUCCESS +* or the @ref NRF_EVT_FLASH_OPERATION_ERROR have been received if the SoftDevice is enabled. +* - This call will make the SoftDevice trigger a hardfault when the page is written, if it is +* protected. +* +* +* @param[in] p_dst Pointer to start of flash location to be written. +* @param[in] p_src Pointer to buffer with data to be written. +* @param[in] size Number of 32-bit words to write. Maximum size is the number of words in one +* flash page. See the device's Product Specification for details. +* +* @retval ::NRF_ERROR_INVALID_ADDR Tried to write to a non existing flash address, or p_dst or p_src was unaligned. +* @retval ::NRF_ERROR_BUSY The previous command has not yet completed. +* @retval ::NRF_ERROR_INVALID_LENGTH Size was 0, or higher than the maximum allowed size. +* @retval ::NRF_ERROR_FORBIDDEN Tried to write to an address outside the application flash area. +* @retval ::NRF_SUCCESS The command was accepted. +*/ +SVCALL(SD_FLASH_WRITE, uint32_t, sd_flash_write(uint32_t * p_dst, uint32_t const * p_src, uint32_t size)); + + +/**@brief Flash Erase page +* +* Commands to erase a flash page +* If the SoftDevice is enabled: +* This call initiates the flash access command, and its completion will be communicated to the +* application with exactly one of the following events: +* - @ref NRF_EVT_FLASH_OPERATION_SUCCESS - The command was successfully completed. +* - @ref NRF_EVT_FLASH_OPERATION_ERROR - The command could not be started. +* +* If the SoftDevice is not enabled no event will be generated, and this call will return @ref NRF_SUCCESS when the +* erase has been completed +* +* @note +* - This call takes control over the radio and the CPU during flash erase and write to make sure that +* they will not interfere with the flash access. This means that all interrupts will be blocked +* for a predictable time (depending on the NVMC specification in the device's Product Specification +* and the command parameters). +* - This call will make the SoftDevice trigger a hardfault when the page is erased, if it is +* protected. +* +* +* @param[in] page_number Page number of the page to erase +* +* @retval ::NRF_ERROR_INTERNAL If a new session could not be opened due to an internal error. +* @retval ::NRF_ERROR_INVALID_ADDR Tried to erase to a non existing flash page. +* @retval ::NRF_ERROR_BUSY The previous command has not yet completed. +* @retval ::NRF_ERROR_FORBIDDEN Tried to erase a page outside the application flash area. +* @retval ::NRF_SUCCESS The command was accepted. +*/ +SVCALL(SD_FLASH_PAGE_ERASE, uint32_t, sd_flash_page_erase(uint32_t page_number)); + + + +/**@brief Opens a session for radio timeslot requests. + * + * @note Only one session can be open at a time. + * @note p_radio_signal_callback(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START) will be called when the radio timeslot + * starts. From this point the NRF_RADIO and NRF_TIMER0 peripherals can be freely accessed + * by the application. + * @note p_radio_signal_callback(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_TIMER0) is called whenever the NRF_TIMER0 + * interrupt occurs. + * @note p_radio_signal_callback(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_RADIO) is called whenever the NRF_RADIO + * interrupt occurs. + * @note p_radio_signal_callback() will be called at ARM interrupt priority level 0. This + * implies that none of the sd_* API calls can be used from p_radio_signal_callback(). + * + * @param[in] p_radio_signal_callback The signal callback. + * + * @retval ::NRF_ERROR_INVALID_ADDR p_radio_signal_callback is an invalid function pointer. + * @retval ::NRF_ERROR_BUSY If session cannot be opened. + * @retval ::NRF_ERROR_INTERNAL If a new session could not be opened due to an internal error. + * @retval ::NRF_SUCCESS Otherwise. + */ + SVCALL(SD_RADIO_SESSION_OPEN, uint32_t, sd_radio_session_open(nrf_radio_signal_callback_t p_radio_signal_callback)); + +/**@brief Closes a session for radio timeslot requests. + * + * @note Any current radio timeslot will be finished before the session is closed. + * @note If a radio timeslot is scheduled when the session is closed, it will be canceled. + * @note The application cannot consider the session closed until the @ref NRF_EVT_RADIO_SESSION_CLOSED + * event is received. + * + * @retval ::NRF_ERROR_FORBIDDEN If session not opened. + * @retval ::NRF_ERROR_BUSY If session is currently being closed. + * @retval ::NRF_SUCCESS Otherwise. + */ + SVCALL(SD_RADIO_SESSION_CLOSE, uint32_t, sd_radio_session_close(void)); + +/**@brief Requests a radio timeslot. + * + * @note The request type is determined by p_request->request_type, and can be one of @ref NRF_RADIO_REQ_TYPE_EARLIEST + * and @ref NRF_RADIO_REQ_TYPE_NORMAL. The first request in a session must always be of type @ref NRF_RADIO_REQ_TYPE_EARLIEST. + * @note For a normal request (@ref NRF_RADIO_REQ_TYPE_NORMAL), the start time of a radio timeslot is specified by + * p_request->distance_us and is given relative to the start of the previous timeslot. + * @note A too small p_request->distance_us will lead to a @ref NRF_EVT_RADIO_BLOCKED event. + * @note Timeslots scheduled too close will lead to a @ref NRF_EVT_RADIO_BLOCKED event. + * @note See the SoftDevice Specification for more on radio timeslot scheduling, distances and lengths. + * @note If an opportunity for the first radio timeslot is not found before 100 ms after the call to this + * function, it is not scheduled, and instead a @ref NRF_EVT_RADIO_BLOCKED event is sent. + * The application may then try to schedule the first radio timeslot again. + * @note Successful requests will result in nrf_radio_signal_callback_t(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START). + * Unsuccessful requests will result in a @ref NRF_EVT_RADIO_BLOCKED event, see @ref NRF_SOC_EVTS. + * @note The jitter in the start time of the radio timeslots is +/- @ref NRF_RADIO_START_JITTER_US us. + * @note The nrf_radio_signal_callback_t(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START) call has a latency relative to the + * specified radio timeslot start, but this does not affect the actual start time of the timeslot. + * @note NRF_TIMER0 is reset at the start of the radio timeslot, and is clocked at 1MHz from the high frequency + * (16 MHz) clock source. If p_request->hfclk_force_xtal is true, the high frequency clock is + * guaranteed to be clocked from the external crystal. + * @note The SoftDevice will neither access the NRF_RADIO peripheral nor the NRF_TIMER0 peripheral + * during the radio timeslot. + * + * @param[in] p_request Pointer to the request parameters. + * + * @retval ::NRF_ERROR_FORBIDDEN If session not opened or the session is not IDLE. + * @retval ::NRF_ERROR_INVALID_ADDR If the p_request pointer is invalid. + * @retval ::NRF_ERROR_INVALID_PARAM If the parameters of p_request are not valid. + * @retval ::NRF_SUCCESS Otherwise. + */ + SVCALL(SD_RADIO_REQUEST, uint32_t, sd_radio_request(nrf_radio_request_t const * p_request)); + +/**@brief Write register protected by the SoftDevice + * + * This function writes to a register that is write-protected by the SoftDevice. Please refer to your + * SoftDevice Specification for more details about which registers that are protected by SoftDevice. + * This function can write to the following protected peripheral: + * - ACL + * + * @note Protected registers may be read directly. + * @note Register that are write-once will return @ref NRF_SUCCESS on second set, even the value in + * the register has not changed. See the Product Specification for more details about register + * properties. + * + * @param[in] p_register Pointer to register to be written. + * @param[in] value Value to be written to the register. + * + * @retval ::NRF_ERROR_INVALID_ADDR This function can not write to the reguested register. + * @retval ::NRF_SUCCESS Value successfully written to register. + * + */ +SVCALL(SD_PROTECTED_REGISTER_WRITE, uint32_t, sd_protected_register_write(volatile uint32_t * p_register, uint32_t value)); + +/**@} */ + +#ifdef __cplusplus +} +#endif +#endif // NRF_SOC_H__ + +/**@} */ diff --git a/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_svc.h b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_svc.h new file mode 100755 index 00000000..292c6929 --- /dev/null +++ b/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_svc.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2012 - 2017, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_SVC__ +#define NRF_SVC__ + +#include "stdint.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef SVCALL_AS_NORMAL_FUNCTION +#define SVCALL(number, return_type, signature) return_type signature +#else + +#ifndef SVCALL +#if defined (__CC_ARM) +#define SVCALL(number, return_type, signature) return_type __svc(number) signature +#elif defined (__GNUC__) +#ifdef __cplusplus +#define GCC_CAST_CPP (uint16_t) +#else +#define GCC_CAST_CPP +#endif +#define SVCALL(number, return_type, signature) \ + _Pragma("GCC diagnostic push") \ + _Pragma("GCC diagnostic ignored \"-Wreturn-type\"") \ + __attribute__((naked)) \ + __attribute__((unused)) \ + static return_type signature \ + { \ + __asm( \ + "svc %0\n" \ + "bx r14" : : "I" (GCC_CAST_CPP number) : "r0" \ + ); \ + } \ + _Pragma("GCC diagnostic pop") + +#elif defined (__ICCARM__) +#define PRAGMA(x) _Pragma(#x) +#define SVCALL(number, return_type, signature) \ +PRAGMA(swi_number = (number)) \ + __swi return_type signature; +#else +#define SVCALL(number, return_type, signature) return_type signature +#endif +#endif // SVCALL + +#endif // SVCALL_AS_NORMAL_FUNCTION + +#ifdef __cplusplus +} +#endif +#endif // NRF_SVC__ diff --git a/tinyusb/hw/mcu/nordic/nrfx_config.h b/tinyusb/hw/mcu/nordic/nrfx_config.h new file mode 100755 index 00000000..6a974ba7 --- /dev/null +++ b/tinyusb/hw/mcu/nordic/nrfx_config.h @@ -0,0 +1,18 @@ +#ifndef NRFX_CONFIG_H__ +#define NRFX_CONFIG_H__ + +#define NRFX_POWER_ENABLED 1 +#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY 7 + +#define NRFX_CLOCK_ENABLED 0 + +#define NRFX_UARTE_ENABLED 1 +#define NRFX_UARTE0_ENABLED 1 + +#define NRFX_UARTE1_ENABLED 0 +#define NRFX_UARTE2_ENABLED 0 +#define NRFX_UARTE3_ENABLED 0 + +#define NRFX_PRS_ENABLED 0 + +#endif // NRFX_CONFIG_H__ diff --git a/tinyusb/hw/mcu/nordic/nrfx_glue.h b/tinyusb/hw/mcu/nordic/nrfx_glue.h new file mode 100755 index 00000000..cdf49b4a --- /dev/null +++ b/tinyusb/hw/mcu/nordic/nrfx_glue.h @@ -0,0 +1,227 @@ +/* + * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_GLUE_H__ +#define NRFX_GLUE_H__ + +// THIS IS A TEMPLATE FILE. +// It should be copied to a suitable location within the host environment into +// which nrfx is integrated, and the following macros should be provided with +// appropriate implementations. +// And this comment should be removed from the customized file. + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_glue nrfx_glue.h + * @{ + * @ingroup nrfx + * + * @brief This file contains macros that should be implemented according to + * the needs of the host environment into which @em nrfx is integrated. + */ + +// Uncomment this line to use the standard MDK way of binding IRQ handlers +// at linking time. +#include <soc/nrfx_irqs.h> + +//------------------------------------------------------------------------------ + +/** + * @brief Macro for placing a runtime assertion. + * + * @param expression Expression to evaluate. + */ +#define NRFX_ASSERT(expression) + +/** + * @brief Macro for placing a compile time assertion. + * + * @param expression Expression to evaluate. + */ +#define NRFX_STATIC_ASSERT(expression) + +//------------------------------------------------------------------------------ + +/** + * @brief Macro for setting the priority of a specific IRQ. + * + * @param irq_number IRQ number. + * @param priority Priority to set. + */ +#define NRFX_IRQ_PRIORITY_SET(irq_number, priority) _NRFX_IRQ_PRIORITY_SET(irq_number, priority) +static inline void _NRFX_IRQ_PRIORITY_SET(IRQn_Type irq_number, + uint8_t priority) +{ + NRFX_ASSERT(INTERRUPT_PRIORITY_IS_VALID(priority)); + NVIC_SetPriority(irq_number, priority); +} + +/** + * @brief Macro for enabling a specific IRQ. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_ENABLE(irq_number) _NRFX_IRQ_ENABLE(irq_number) +static inline void _NRFX_IRQ_ENABLE(IRQn_Type irq_number) +{ + NVIC_ClearPendingIRQ(irq_number); + NVIC_EnableIRQ(irq_number); +} + +/** + * @brief Macro for checking if a specific IRQ is enabled. + * + * @param irq_number IRQ number. + * + * @retval true If the IRQ is enabled. + * @retval false Otherwise. + */ +#define NRFX_IRQ_IS_ENABLED(irq_number) _NRFX_IRQ_IS_ENABLED(irq_number) +static inline bool _NRFX_IRQ_IS_ENABLED(IRQn_Type irq_number) +{ + return 0 != (NVIC->ISER[irq_number / 32] & (1UL << (irq_number % 32))); +} + +/** + * @brief Macro for disabling a specific IRQ. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_DISABLE(irq_number) _NRFX_IRQ_DISABLE(irq_number) +static inline void _NRFX_IRQ_DISABLE(IRQn_Type irq_number) +{ + NVIC_DisableIRQ(irq_number); +} + +/** + * @brief Macro for setting a specific IRQ as pending. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_PENDING_SET(irq_number) _NRFX_IRQ_PENDING_SET(irq_number) +static inline void _NRFX_IRQ_PENDING_SET(IRQn_Type irq_number) +{ + NVIC_SetPendingIRQ(irq_number); +} + +/** + * @brief Macro for clearing the pending status of a specific IRQ. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_PENDING_CLEAR(irq_number) _NRFX_IRQ_PENDING_CLEAR(irq_number) +static inline void _NRFX_IRQ_PENDING_CLEAR(IRQn_Type irq_number) +{ + NVIC_ClearPendingIRQ(irq_number); +} + +/** + * @brief Macro for checking the pending status of a specific IRQ. + * + * @retval true If the IRQ is pending. + * @retval false Otherwise. + */ +#define NRFX_IRQ_IS_PENDING(irq_number) _NRFX_IRQ_IS_PENDING(irq_number) +static inline bool _NRFX_IRQ_IS_PENDING(IRQn_Type irq_number) +{ + return (NVIC_GetPendingIRQ(irq_number) == 1); +} + +/** + * @brief Macro for entering into a critical section. + */ +#define NRFX_CRITICAL_SECTION_ENTER() + +/** + * @brief Macro for exiting from a critical section. + */ +#define NRFX_CRITICAL_SECTION_EXIT() + +//------------------------------------------------------------------------------ + +/** + * @brief When set to a non-zero value, this macro specifies that + * @ref nrfx_coredep_delay_us uses a precise DWT-based solution. + * A compilation error is generated if the DWT unit is not present + * in the SoC used. + */ +#define NRFX_DELAY_DWT_BASED 0 + +/** + * @brief Macro for delaying the code execution for at least the specified time. + * + * @param us_time Number of microseconds to wait. + */ +#include <soc/nrfx_coredep.h> +#define NRFX_DELAY_US(us_time) nrfx_coredep_delay_us(us_time) + +//------------------------------------------------------------------------------ + +/** + * @brief When set to a non-zero value, this macro specifies that the + * @ref nrfx_error_codes and the @ref nrfx_err_t type itself are defined + * in a customized way and the default definitions from @c <nrfx_error.h> + * should not be used. + */ +#define NRFX_CUSTOM_ERROR_CODES 0 + +//------------------------------------------------------------------------------ + +/** + * @brief Bitmask defining PPI channels reserved to be used outside of nrfx. + */ +#define NRFX_PPI_CHANNELS_USED 0 + +/** + * @brief Bitmask defining PPI groups reserved to be used outside of nrfx. + */ +#define NRFX_PPI_GROUPS_USED 0 + +/** + * @brief Bitmask defining SWI instances reserved to be used outside of nrfx. + */ +#define NRFX_SWI_USED 0 + +/** + * @brief Bitmask defining TIMER instances reserved to be used outside of nrfx. + */ +#define NRFX_TIMERS_USED 0 + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_GLUE_H__ diff --git a/tinyusb/hw/mcu/nordic/nrfx_log.h b/tinyusb/hw/mcu/nordic/nrfx_log.h new file mode 100755 index 00000000..3bc1b424 --- /dev/null +++ b/tinyusb/hw/mcu/nordic/nrfx_log.h @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_LOG_H__ +#define NRFX_LOG_H__ + +// THIS IS A TEMPLATE FILE. +// It should be copied to a suitable location within the host environment into +// which nrfx is integrated, and the following macros should be provided with +// appropriate implementations. +// And this comment should be removed from the customized file. + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_log nrfx_log.h + * @{ + * @ingroup nrfx + * + * @brief This file contains macros that should be implemented according to + * the needs of the host environment into which @em nrfx is integrated. + */ + +/** + * @brief Macro for logging a message with the severity level ERROR. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_ERROR(format, ...) + +/** + * @brief Macro for logging a message with the severity level WARNING. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_WARNING(format, ...) + +/** + * @brief Macro for logging a message with the severity level INFO. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_INFO(format, ...) + +/** + * @brief Macro for logging a message with the severity level DEBUG. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_DEBUG(format, ...) + + +/** + * @brief Macro for logging a memory dump with the severity level ERROR. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_ERROR(p_memory, length) + +/** + * @brief Macro for logging a memory dump with the severity level WARNING. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_WARNING(p_memory, length) + +/** + * @brief Macro for logging a memory dump with the severity level INFO. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_INFO(p_memory, length) + +/** + * @brief Macro for logging a memory dump with the severity level DEBUG. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_DEBUG(p_memory, length) + + +/** + * @brief Macro for getting the textual representation of a given error code. + * + * @param[in] error_code Error code. + * + * @return String containing the textual representation of the error code. + */ +#define NRFX_LOG_ERROR_STRING_GET(error_code) + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_LOG_H__ diff --git a/tinyusb/hw/mcu/sony/cxd56/mkspk/.gitignore b/tinyusb/hw/mcu/sony/cxd56/mkspk/.gitignore new file mode 100755 index 00000000..4c3d12e3 --- /dev/null +++ b/tinyusb/hw/mcu/sony/cxd56/mkspk/.gitignore @@ -0,0 +1,2 @@ +/mkspk +/mkspk.exe diff --git a/tinyusb/hw/mcu/sony/cxd56/mkspk/Makefile b/tinyusb/hw/mcu/sony/cxd56/mkspk/Makefile new file mode 100755 index 00000000..d91d17a3 --- /dev/null +++ b/tinyusb/hw/mcu/sony/cxd56/mkspk/Makefile @@ -0,0 +1,51 @@ +############################################################################ +# tools/mkspk/Makefile +# +# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt <gnutt@nuttx.org> +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +all: mkspk +default: mkspk +.PHONY: clean + +# Add CFLAGS=-g on the make command line to build debug versions + +CFLAGS = -O2 -Wall -I. + +# mkspk - Convert nuttx.hex image to nuttx.spk image + +mkspk: + @gcc $(CFLAGS) -o mkspk mkspk.c clefia.c + +clean: + @rm -f *.o *.a *.dSYM *~ .*.swp + @rm -f mkspk mkspk.exe diff --git a/tinyusb/hw/mcu/sony/cxd56/mkspk/clefia.c b/tinyusb/hw/mcu/sony/cxd56/mkspk/clefia.c new file mode 100755 index 00000000..02a17550 --- /dev/null +++ b/tinyusb/hw/mcu/sony/cxd56/mkspk/clefia.c @@ -0,0 +1,517 @@ +/**************************************************************************** + * tools/cxd56/clefia.c + * + * Copyright (C) 2007, 2008 Sony Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <stdint.h> +#include <assert.h> + +#include "clefia.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define clefiamul4(_x) (clefiamul2(clefiamul2((_x)))) +#define clefiamul6(_x) (clefiamul2((_x)) ^ clefiamul4((_x))) +#define clefiamul8(_x) (clefiamul2(clefiamul4((_x)))) +#define clefiamula(_x) (clefiamul2((_x)) ^ clefiamul8((_x))) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* S0 (8-bit S-box based on four 4-bit S-boxes) */ + +static const unsigned char clefia_s0[256] = +{ + 0x57u, 0x49u, 0xd1u, 0xc6u, 0x2fu, 0x33u, 0x74u, 0xfbu, + 0x95u, 0x6du, 0x82u, 0xeau, 0x0eu, 0xb0u, 0xa8u, 0x1cu, + 0x28u, 0xd0u, 0x4bu, 0x92u, 0x5cu, 0xeeu, 0x85u, 0xb1u, + 0xc4u, 0x0au, 0x76u, 0x3du, 0x63u, 0xf9u, 0x17u, 0xafu, + 0xbfu, 0xa1u, 0x19u, 0x65u, 0xf7u, 0x7au, 0x32u, 0x20u, + 0x06u, 0xceu, 0xe4u, 0x83u, 0x9du, 0x5bu, 0x4cu, 0xd8u, + 0x42u, 0x5du, 0x2eu, 0xe8u, 0xd4u, 0x9bu, 0x0fu, 0x13u, + 0x3cu, 0x89u, 0x67u, 0xc0u, 0x71u, 0xaau, 0xb6u, 0xf5u, + 0xa4u, 0xbeu, 0xfdu, 0x8cu, 0x12u, 0x00u, 0x97u, 0xdau, + 0x78u, 0xe1u, 0xcfu, 0x6bu, 0x39u, 0x43u, 0x55u, 0x26u, + 0x30u, 0x98u, 0xccu, 0xddu, 0xebu, 0x54u, 0xb3u, 0x8fu, + 0x4eu, 0x16u, 0xfau, 0x22u, 0xa5u, 0x77u, 0x09u, 0x61u, + 0xd6u, 0x2au, 0x53u, 0x37u, 0x45u, 0xc1u, 0x6cu, 0xaeu, + 0xefu, 0x70u, 0x08u, 0x99u, 0x8bu, 0x1du, 0xf2u, 0xb4u, + 0xe9u, 0xc7u, 0x9fu, 0x4au, 0x31u, 0x25u, 0xfeu, 0x7cu, + 0xd3u, 0xa2u, 0xbdu, 0x56u, 0x14u, 0x88u, 0x60u, 0x0bu, + 0xcdu, 0xe2u, 0x34u, 0x50u, 0x9eu, 0xdcu, 0x11u, 0x05u, + 0x2bu, 0xb7u, 0xa9u, 0x48u, 0xffu, 0x66u, 0x8au, 0x73u, + 0x03u, 0x75u, 0x86u, 0xf1u, 0x6au, 0xa7u, 0x40u, 0xc2u, + 0xb9u, 0x2cu, 0xdbu, 0x1fu, 0x58u, 0x94u, 0x3eu, 0xedu, + 0xfcu, 0x1bu, 0xa0u, 0x04u, 0xb8u, 0x8du, 0xe6u, 0x59u, + 0x62u, 0x93u, 0x35u, 0x7eu, 0xcau, 0x21u, 0xdfu, 0x47u, + 0x15u, 0xf3u, 0xbau, 0x7fu, 0xa6u, 0x69u, 0xc8u, 0x4du, + 0x87u, 0x3bu, 0x9cu, 0x01u, 0xe0u, 0xdeu, 0x24u, 0x52u, + 0x7bu, 0x0cu, 0x68u, 0x1eu, 0x80u, 0xb2u, 0x5au, 0xe7u, + 0xadu, 0xd5u, 0x23u, 0xf4u, 0x46u, 0x3fu, 0x91u, 0xc9u, + 0x6eu, 0x84u, 0x72u, 0xbbu, 0x0du, 0x18u, 0xd9u, 0x96u, + 0xf0u, 0x5fu, 0x41u, 0xacu, 0x27u, 0xc5u, 0xe3u, 0x3au, + 0x81u, 0x6fu, 0x07u, 0xa3u, 0x79u, 0xf6u, 0x2du, 0x38u, + 0x1au, 0x44u, 0x5eu, 0xb5u, 0xd2u, 0xecu, 0xcbu, 0x90u, + 0x9au, 0x36u, 0xe5u, 0x29u, 0xc3u, 0x4fu, 0xabu, 0x64u, + 0x51u, 0xf8u, 0x10u, 0xd7u, 0xbcu, 0x02u, 0x7du, 0x8eu +}; + +/* S1 (8-bit S-box based on inverse function) */ + +static const unsigned char clefia_s1[256] = +{ + 0x6cu, 0xdau, 0xc3u, 0xe9u, 0x4eu, 0x9du, 0x0au, 0x3du, + 0xb8u, 0x36u, 0xb4u, 0x38u, 0x13u, 0x34u, 0x0cu, 0xd9u, + 0xbfu, 0x74u, 0x94u, 0x8fu, 0xb7u, 0x9cu, 0xe5u, 0xdcu, + 0x9eu, 0x07u, 0x49u, 0x4fu, 0x98u, 0x2cu, 0xb0u, 0x93u, + 0x12u, 0xebu, 0xcdu, 0xb3u, 0x92u, 0xe7u, 0x41u, 0x60u, + 0xe3u, 0x21u, 0x27u, 0x3bu, 0xe6u, 0x19u, 0xd2u, 0x0eu, + 0x91u, 0x11u, 0xc7u, 0x3fu, 0x2au, 0x8eu, 0xa1u, 0xbcu, + 0x2bu, 0xc8u, 0xc5u, 0x0fu, 0x5bu, 0xf3u, 0x87u, 0x8bu, + 0xfbu, 0xf5u, 0xdeu, 0x20u, 0xc6u, 0xa7u, 0x84u, 0xceu, + 0xd8u, 0x65u, 0x51u, 0xc9u, 0xa4u, 0xefu, 0x43u, 0x53u, + 0x25u, 0x5du, 0x9bu, 0x31u, 0xe8u, 0x3eu, 0x0du, 0xd7u, + 0x80u, 0xffu, 0x69u, 0x8au, 0xbau, 0x0bu, 0x73u, 0x5cu, + 0x6eu, 0x54u, 0x15u, 0x62u, 0xf6u, 0x35u, 0x30u, 0x52u, + 0xa3u, 0x16u, 0xd3u, 0x28u, 0x32u, 0xfau, 0xaau, 0x5eu, + 0xcfu, 0xeau, 0xedu, 0x78u, 0x33u, 0x58u, 0x09u, 0x7bu, + 0x63u, 0xc0u, 0xc1u, 0x46u, 0x1eu, 0xdfu, 0xa9u, 0x99u, + 0x55u, 0x04u, 0xc4u, 0x86u, 0x39u, 0x77u, 0x82u, 0xecu, + 0x40u, 0x18u, 0x90u, 0x97u, 0x59u, 0xddu, 0x83u, 0x1fu, + 0x9au, 0x37u, 0x06u, 0x24u, 0x64u, 0x7cu, 0xa5u, 0x56u, + 0x48u, 0x08u, 0x85u, 0xd0u, 0x61u, 0x26u, 0xcau, 0x6fu, + 0x7eu, 0x6au, 0xb6u, 0x71u, 0xa0u, 0x70u, 0x05u, 0xd1u, + 0x45u, 0x8cu, 0x23u, 0x1cu, 0xf0u, 0xeeu, 0x89u, 0xadu, + 0x7au, 0x4bu, 0xc2u, 0x2fu, 0xdbu, 0x5au, 0x4du, 0x76u, + 0x67u, 0x17u, 0x2du, 0xf4u, 0xcbu, 0xb1u, 0x4au, 0xa8u, + 0xb5u, 0x22u, 0x47u, 0x3au, 0xd5u, 0x10u, 0x4cu, 0x72u, + 0xccu, 0x00u, 0xf9u, 0xe0u, 0xfdu, 0xe2u, 0xfeu, 0xaeu, + 0xf8u, 0x5fu, 0xabu, 0xf1u, 0x1bu, 0x42u, 0x81u, 0xd6u, + 0xbeu, 0x44u, 0x29u, 0xa6u, 0x57u, 0xb9u, 0xafu, 0xf2u, + 0xd4u, 0x75u, 0x66u, 0xbbu, 0x68u, 0x9fu, 0x50u, 0x02u, + 0x01u, 0x3cu, 0x7fu, 0x8du, 0x1au, 0x88u, 0xbdu, 0xacu, + 0xf7u, 0xe4u, 0x79u, 0x96u, 0xa2u, 0xfcu, 0x6du, 0xb2u, + 0x6bu, 0x03u, 0xe1u, 0x2eu, 0x7du, 0x14u, 0x95u, 0x1du +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void bytecpy(unsigned char *dst, const unsigned char *src, int bytelen) +{ + while (bytelen-- > 0) + { + *dst++ = *src++; + } +} + +static unsigned char clefiamul2(unsigned char x) +{ + /* multiplication over GF(2^8) (p(x) = '11d') */ + + if (x & 0x80u) + { + x ^= 0x0eu; + } + + return ((x << 1) | (x >> 7)); +} + +static void clefiaf0xor(unsigned char *dst, const unsigned char *src, + const unsigned char *rk) +{ + unsigned char x[4]; + unsigned char y[4]; + unsigned char z[4]; + + /* F0 */ + + /* Key addition */ + + bytexor(x, src, rk, 4); + + /* Substitution layer */ + + z[0] = clefia_s0[x[0]]; + z[1] = clefia_s1[x[1]]; + z[2] = clefia_s0[x[2]]; + z[3] = clefia_s1[x[3]]; + + /* Diffusion layer (M0) */ + + y[0] = z[0] ^ clefiamul2(z[1]) ^ clefiamul4(z[2]) ^ clefiamul6(z[3]); + y[1] = clefiamul2(z[0]) ^ z[1] ^ clefiamul6(z[2]) ^ clefiamul4(z[3]); + y[2] = clefiamul4(z[0]) ^ clefiamul6(z[1]) ^ z[2] ^ clefiamul2(z[3]); + y[3] = clefiamul6(z[0]) ^ clefiamul4(z[1]) ^ clefiamul2(z[2]) ^ z[3]; + + /* Xoring after F0 */ + + bytecpy(dst + 0, src + 0, 4); + bytexor(dst + 4, src + 4, y, 4); +} + +static void clefiaf1xor(unsigned char *dst, const unsigned char *src, + const unsigned char *rk) +{ + unsigned char x[4]; + unsigned char y[4]; + unsigned char z[4]; + + /* F1 */ + + /* Key addition */ + + bytexor(x, src, rk, 4); + + /* Substitution layer */ + + z[0] = clefia_s1[x[0]]; + z[1] = clefia_s0[x[1]]; + z[2] = clefia_s1[x[2]]; + z[3] = clefia_s0[x[3]]; + + /* Diffusion layer (M1) */ + + y[0] = z[0] ^ clefiamul8(z[1]) ^ clefiamul2(z[2]) ^ clefiamula(z[3]); + y[1] = clefiamul8(z[0]) ^ z[1] ^ clefiamula(z[2]) ^ clefiamul2(z[3]); + y[2] = clefiamul2(z[0]) ^ clefiamula(z[1]) ^ z[2] ^ clefiamul8(z[3]); + y[3] = clefiamula(z[0]) ^ clefiamul2(z[1]) ^ clefiamul8(z[2]) ^ z[3]; + + /* Xoring after F1 */ + + bytecpy(dst + 0, src + 0, 4); + bytexor(dst + 4, src + 4, y, 4); +} + +static void clefiagfn4(unsigned char *y, const unsigned char *x, + const unsigned char *rk, int r) +{ + unsigned char fin[16]; + unsigned char fout[16]; + + bytecpy(fin, x, 16); + while (r-- > 0) + { + clefiaf0xor(fout + 0, fin + 0, rk + 0); + clefiaf1xor(fout + 8, fin + 8, rk + 4); + rk += 8; + if (r) + { + /* swapping for encryption */ + + bytecpy(fin + 0, fout + 4, 12); + bytecpy(fin + 12, fout + 0, 4); + } + } + + bytecpy(y, fout, 16); +} + +#if 0 /* Not used */ +static void clefiagfn8(unsigned char *y, const unsigned char *x, + const unsigned char *rk, int r) +{ + unsigned char fin[32]; + unsigned char fout[32]; + + bytecpy(fin, x, 32); + while (r-- > 0) + { + clefiaf0xor(fout + 0, fin + 0, rk + 0); + clefiaf1xor(fout + 8, fin + 8, rk + 4); + clefiaf0xor(fout + 16, fin + 16, rk + 8); + clefiaf1xor(fout + 24, fin + 24, rk + 12); + rk += 16; + if (r) + { + /* swapping for encryption */ + + bytecpy(fin + 0, fout + 4, 28); + bytecpy(fin + 28, fout + 0, 4); + } + } + + bytecpy(y, fout, 32); +} +#endif + +#if 0 /* Not used */ +static void clefiagfn4inv(unsigned char *y, const unsigned char *x, + const unsigned char *rk, int r) +{ + unsigned char fin[16]; + unsigned char fout[16]; + + rk += (r - 1) * 8; + bytecpy(fin, x, 16); + while (r-- > 0) + { + clefiaf0xor(fout + 0, fin + 0, rk + 0); + clefiaf1xor(fout + 8, fin + 8, rk + 4); + rk -= 8; + if (r) + { + /* swapping for decryption */ + + bytecpy(fin + 0, fout + 12, 4); + bytecpy(fin + 4, fout + 0, 12); + } + } + + bytecpy(y, fout, 16); +} +#endif + +static void clefiadoubleswap(unsigned char *lk) +{ + unsigned char t[16]; + + t[0] = (lk[0] << 7) | (lk[1] >> 1); + t[1] = (lk[1] << 7) | (lk[2] >> 1); + t[2] = (lk[2] << 7) | (lk[3] >> 1); + t[3] = (lk[3] << 7) | (lk[4] >> 1); + t[4] = (lk[4] << 7) | (lk[5] >> 1); + t[5] = (lk[5] << 7) | (lk[6] >> 1); + t[6] = (lk[6] << 7) | (lk[7] >> 1); + t[7] = (lk[7] << 7) | (lk[15] & 0x7fu); + + t[8] = (lk[8] >> 7) | (lk[0] & 0xfeu); + t[9] = (lk[9] >> 7) | (lk[8] << 1); + t[10] = (lk[10] >> 7) | (lk[9] << 1); + t[11] = (lk[11] >> 7) | (lk[10] << 1); + t[12] = (lk[12] >> 7) | (lk[11] << 1); + t[13] = (lk[13] >> 7) | (lk[12] << 1); + t[14] = (lk[14] >> 7) | (lk[13] << 1); + t[15] = (lk[15] >> 7) | (lk[14] << 1); + + bytecpy(lk, t, 16); +} + +static void clefiaconset(unsigned char *con, const unsigned char *iv, int lk) +{ + unsigned char t[2]; + unsigned char tmp; + + bytecpy(t, iv, 2); + while (lk-- > 0) + { + con[0] = t[0] ^ 0xb7u; /* P_16 = 0xb7e1 (natural logarithm) */ + con[1] = t[1] ^ 0xe1u; + con[2] = ~((t[0] << 1) | (t[1] >> 7)); + con[3] = ~((t[1] << 1) | (t[0] >> 7)); + con[4] = ~t[0] ^ 0x24u; /* Q_16 = 0x243f (circle ratio) */ + con[5] = ~t[1] ^ 0x3fu; + con[6] = t[1]; + con[7] = t[0]; + con += 8; + + /* updating T */ + + if (t[1] & 0x01u) + { + t[0] ^= 0xa8u; + t[1] ^= 0x30u; + } + + tmp = t[0] << 7; + t[0] = (t[0] >> 1) | (t[1] << 7); + t[1] = (t[1] >> 1) | tmp; + } +} + +static void left_shift_one(uint8_t * in, uint8_t * out) +{ + int i; + int overflow; + + overflow = 0; + for (i = 15; i >= 0; i--) + { + out[i] = in[i] << 1; + out[i] |= overflow; + overflow = (in[i] >> 7) & 1; + } +} + +static void gen_subkey(struct cipher *c) +{ + uint8_t L[16]; + + memset(L, 0, 16); + clefiaencrypt(L, L, c->rk, c->round); + + left_shift_one(L, c->k1); + if (L[0] & 0x80) + { + c->k1[15] = c->k1[15] ^ 0x87; + } + + left_shift_one(c->k1, c->k2); + if (c->k1[0] & 0x80) + { + c->k2[15] = c->k2[15] ^ 0x87; + } + + memset(L, 0, 16); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +struct cipher *cipher_init(uint8_t * key, uint8_t * iv) +{ + struct cipher *c; + + c = (struct cipher *)malloc(sizeof(*c)); + if (!c) + { + return NULL; + } + + c->round = clefiakeyset(c->rk, key); + + gen_subkey(c); + memset(c->vector, 0, 16); + + return c; +} + +void cipher_deinit(struct cipher *c) +{ + memset(c, 0, sizeof(*c)); + free(c); +} + +int cipher_calc_cmac(struct cipher *c, void *data, int size, void *cmac) +{ + uint8_t m[16]; + uint8_t *p; + + if (size & 0xf) + { + return -1; + } + + p = (uint8_t *) data; + while (size) + { + bytexor(m, c->vector, p, 16); + clefiaencrypt(c->vector, m, c->rk, c->round); + size -= 16; + p += 16; + } + + bytexor(cmac, m, c->k1, 16); + clefiaencrypt(cmac, cmac, c->rk, c->round); + memset(m, 0, 16); + + return 0; +} + +void bytexor(unsigned char *dst, const unsigned char *a, + const unsigned char *b, int bytelen) +{ + while (bytelen-- > 0) + { + *dst++ = *a++ ^ *b++; + } +} + +int clefiakeyset(unsigned char *rk, const unsigned char *skey) +{ + const unsigned char iv[2] = + { + 0x42u, 0x8au /* cubic root of 2 */ + }; + + unsigned char lk[16]; + unsigned char con128[4 * 60]; + int i; + + /* generating CONi^(128) (0 <= i < 60, lk = 30) */ + + clefiaconset(con128, iv, 30); + + /* GFN_{4,12} (generating L from K) */ + + clefiagfn4(lk, skey, con128, 12); + + bytecpy(rk, skey, 8); /* initial whitening key (WK0, WK1) */ + rk += 8; + for (i = 0; i < 9; i++) + { + /* round key (RKi (0 <= i < 36)) */ + + bytexor(rk, lk, con128 + i * 16 + (4 * 24), 16); + if (i % 2) + { + bytexor(rk, rk, skey, 16); /* Xoring K */ + } + + clefiadoubleswap(lk); /* Updating L (DoubleSwap function) */ + rk += 16; + } + + bytecpy(rk, skey + 8, 8); /* final whitening key (WK2, WK3) */ + + return 18; +} + +void clefiaencrypt(unsigned char *ct, const unsigned char *pt, + const unsigned char *rk, const int r) +{ + unsigned char rin[16]; + unsigned char rout[16]; + + bytecpy(rin, pt, 16); + + bytexor(rin + 4, rin + 4, rk + 0, 4); /* initial key whitening */ + bytexor(rin + 12, rin + 12, rk + 4, 4); + rk += 8; + + clefiagfn4(rout, rin, rk, r); /* GFN_{4,r} */ + + bytecpy(ct, rout, 16); + bytexor(ct + 4, ct + 4, rk + r * 8 + 0, 4); /* final key whitening */ + bytexor(ct + 12, ct + 12, rk + r * 8 + 4, 4); +} diff --git a/tinyusb/hw/mcu/sony/cxd56/mkspk/clefia.h b/tinyusb/hw/mcu/sony/cxd56/mkspk/clefia.h new file mode 100755 index 00000000..a0e02587 --- /dev/null +++ b/tinyusb/hw/mcu/sony/cxd56/mkspk/clefia.h @@ -0,0 +1,65 @@ +/**************************************************************************** + * tools/cxd56/clefia.h + * + * Copyright (C) 2007, 2008 Sony Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *****************************************************************************/ + +#ifndef _TOOLS_CXD56_CLEFIA_H_ +#define _TOOLS_CXD56_CLEFIA_H_ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +struct cipher + { + int mode; + int dir; + uint8_t rk[8 * 26 + 16]; + uint8_t vector[16]; + int round; + uint8_t k1[16]; + uint8_t k2[16]; + }; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +struct cipher *cipher_init(uint8_t * key, uint8_t * iv); +void cipher_deinit(struct cipher *c); +int cipher_calc_cmac(struct cipher *c, void *data, int size, void *cmac); +void bytexor(unsigned char *dst, const unsigned char *a, + const unsigned char *b, int bytelen); +int clefiakeyset(unsigned char *rk, const unsigned char *skey); +void clefiaencrypt(unsigned char *ct, const unsigned char *pt, + const unsigned char *rk, const int r); + +#endif diff --git a/tinyusb/hw/mcu/sony/cxd56/mkspk/elf32.h b/tinyusb/hw/mcu/sony/cxd56/mkspk/elf32.h new file mode 100755 index 00000000..94a9c81b --- /dev/null +++ b/tinyusb/hw/mcu/sony/cxd56/mkspk/elf32.h @@ -0,0 +1,175 @@ +/**************************************************************************** + * include/elf32.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Reference: System V Application Binary Interface, Edition 4.1, March 18, + * 1997, The Santa Cruz Operation, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __INCLUDE_ELF32_H +#define __INCLUDE_ELF32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <stdint.h> + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define EI_NIDENT 16 /* Size of e_ident[] */ + +#define ELF32_ST_BIND(i) ((i) >> 4) +#define ELF32_ST_TYPE(i) ((i) & 0xf) +#define ELF32_ST_INFO(b,t) (((b) << 4) | ((t) & 0xf)) + +/* Definitions for Elf32_Rel*::r_info */ + +#define ELF32_R_SYM(i) ((i) >> 8) +#define ELF32_R_TYPE(i) ((i) & 0xff) +#define ELF32_R_INFO(s,t) (((s)<< 8) | ((t) & 0xff)) + +#define ELF_R_SYM(i) ELF32_R_SYM(i) + +/**************************************************************************** + * Public Type Definitions + ****************************************************************************/ + +/* Figure 4.2: 32-Bit Data Types */ + +typedef uint32_t Elf32_Addr; /* Unsigned program address */ +typedef uint16_t Elf32_Half; /* Unsigned medium integer */ +typedef uint32_t Elf32_Off; /* Unsigned file offset */ +typedef int32_t Elf32_Sword; /* Signed large integer */ +typedef uint32_t Elf32_Word; /* Unsigned large integer */ + +/* Figure 4-3: ELF Header */ + +typedef struct +{ + unsigned char e_ident[EI_NIDENT]; + Elf32_Half e_type; + Elf32_Half e_machine; + Elf32_Word e_version; + Elf32_Addr e_entry; + Elf32_Off e_phoff; + Elf32_Off e_shoff; + Elf32_Word e_flags; + Elf32_Half e_ehsize; + Elf32_Half e_phentsize; + Elf32_Half e_phnum; + Elf32_Half e_shentsize; + Elf32_Half e_shnum; + Elf32_Half e_shstrndx; +} Elf32_Ehdr; + +/* Figure 4-8: Section Header */ + +typedef struct +{ + Elf32_Word sh_name; + Elf32_Word sh_type; + Elf32_Word sh_flags; + Elf32_Addr sh_addr; + Elf32_Off sh_offset; + Elf32_Word sh_size; + Elf32_Word sh_link; + Elf32_Word sh_info; + Elf32_Word sh_addralign; + Elf32_Word sh_entsize; +} Elf32_Shdr; + +/* Figure 4-15: Symbol Table Entry */ + +typedef struct +{ + Elf32_Word st_name; + Elf32_Addr st_value; + Elf32_Word st_size; + unsigned char st_info; + unsigned char st_other; + Elf32_Half st_shndx; +} Elf32_Sym; + +/* Figure 4-19: Relocation Entries */ + +typedef struct +{ + Elf32_Addr r_offset; + Elf32_Word r_info; +} Elf32_Rel; + +typedef struct +{ + Elf32_Addr r_offset; + Elf32_Word r_info; + Elf32_Sword r_addend; +} Elf32_Rela; + +/* Figure 5-1: Program Header */ + +typedef struct +{ + Elf32_Word p_type; + Elf32_Off p_offset; + Elf32_Addr p_vaddr; + Elf32_Addr p_paddr; + Elf32_Word p_filesz; + Elf32_Word p_memsz; + Elf32_Word p_flags; + Elf32_Word p_align; +} Elf32_Phdr; + +/* Figure 5-9: Dynamic Structure */ + +typedef struct +{ + Elf32_Sword d_tag; + union + { + Elf32_Word d_val; + Elf32_Addr d_ptr; + } d_un; +} Elf32_Dyn; + +typedef Elf32_Addr Elf_Addr; +typedef Elf32_Ehdr Elf_Ehdr; +typedef Elf32_Rel Elf_Rel; +typedef Elf32_Rela Elf_Rela; +typedef Elf32_Sym Elf_Sym; +typedef Elf32_Shdr Elf_Shdr; +typedef Elf32_Word Elf_Word; + +#endif /* __INCLUDE_ELF32_H */ diff --git a/tinyusb/hw/mcu/sony/cxd56/mkspk/mkspk.c b/tinyusb/hw/mcu/sony/cxd56/mkspk/mkspk.c new file mode 100755 index 00000000..c447ad7d --- /dev/null +++ b/tinyusb/hw/mcu/sony/cxd56/mkspk/mkspk.c @@ -0,0 +1,383 @@ +/**************************************************************************** + * tools/cxd56/mkspk.c + * + * Copyright (C) 2007, 2008 Sony Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <sys/types.h> +#include <sys/stat.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <unistd.h> +#include <stdint.h> +#include <stdbool.h> +#include <assert.h> + +#include "mkspk.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct args +{ + int core; + char *elffile; + char *savename; + char *outputfile; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint8_t vmk[16] = + "\x27\xc0\xaf\x1b\x5d\xcb\xc6\xc5\x58\x22\x1c\xdd\xaf\xf3\x20\x21"; + +static struct args g_options = +{ + 0 +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static struct args *parse_args(int argc, char **argv) +{ + int opt; + int show_help; + struct args *args = &g_options; + char *endp; + + show_help = 0; + + if (argc < 2) + { + show_help = 1; + } + + memset(args, 0, sizeof(*args)); + args->core = -1; + + while ((opt = getopt(argc, argv, "h:c:")) != -1) + { + switch (opt) + { + case 'c': + args->core = strtol(optarg, &endp, 0); + if (*endp) + { + fprintf(stderr, "Invalid core number \"%s\"\n", optarg); + show_help = 1; + } + break; + + case 'h': + default: + show_help = 1; + } + } + + argc -= optind; + argv += optind; + + args->elffile = argv[0]; + args->savename = argv[1]; + argc -= 2; + argv += 2; + + if (argc > 0) + { + args->outputfile = strdup(argv[0]); + } + else + { + show_help = 1; + } + + /* Sanity checks for options */ + + if (show_help == 1) + { + fprintf(stderr, + "mkspk [-c <number>] <filename> <save name> [<output file>]\n"); + exit(EXIT_FAILURE); + } + + if (args->core < 0) + { + fprintf(stderr, "Core number is not set. Please use -c option.\n"); + exit(EXIT_FAILURE); + } + + if (strlen(args->savename) > 63) + { + fprintf(stderr, "savename too long.\n"); + exit(EXIT_FAILURE); + } + + return args; +} + +static struct elf_file *load_elf(const char *filename) +{ + size_t fsize; + int pos; + char *buf; + FILE *fp; + struct elf_file *ef; + Elf32_Shdr *sh; + uint16_t i; + int ret; + + fp = fopen(filename, "rb"); + if (!fp) + { + return NULL; + } + + ef = (struct elf_file *)malloc(sizeof(*ef)); + if (!ef) + { + return NULL; + } + + pos = fseek(fp, 0, SEEK_END); + fsize = (size_t) ftell(fp); + fseek(fp, pos, SEEK_SET); + + buf = (char *)malloc(fsize); + if (!buf) + { + return NULL; + } + + ret = fread(buf, fsize, 1, fp); + fclose(fp); + if (ret != 1) + { + return NULL; + } + + ef->data = buf; + + ef->ehdr = (Elf32_Ehdr *) buf; + + Elf32_Ehdr *h = (Elf32_Ehdr *) buf; + + if (!(h->e_ident[EI_MAG0] == 0x7f && + h->e_ident[EI_MAG1] == 'E' && + h->e_ident[EI_MAG2] == 'L' && h->e_ident[EI_MAG3] == 'F')) + { + free(ef); + free(buf); + return NULL; + } + + ef->phdr = (Elf32_Phdr *) (buf + ef->ehdr->e_phoff); + ef->shdr = (Elf32_Shdr *) (buf + ef->ehdr->e_shoff); + ef->shstring = buf + ef->shdr[ef->ehdr->e_shstrndx].sh_offset; + + for (i = 0, sh = ef->shdr; i < ef->ehdr->e_shnum; i++, sh++) + { + if (sh->sh_type == SHT_SYMTAB) + { + ef->symtab = (Elf32_Sym *) (buf + sh->sh_offset); + ef->nsyms = sh->sh_size / sh->sh_entsize; + continue; + } + + if (sh->sh_type == SHT_STRTAB) + { + if (!strcmp(".strtab", ef->shstring + sh->sh_name)) + { + ef->string = buf + sh->sh_offset; + } + } + } + + return ef; +} + +static void *create_image(struct elf_file *elf, int core, char *savename, + int *image_size) +{ + char *img; + struct spk_header *header; + struct spk_prog_info *pi; + Elf32_Phdr *ph; + Elf32_Sym *sym; + char *name; + int snlen; + int nphs, psize, imgsize; + int i; + int j; + uint32_t offset; + uint32_t sp; + + snlen = alignup(strlen(savename) + 1, 16); + + nphs = 0; + psize = 0; + for (i = 0, ph = elf->phdr; i < elf->ehdr->e_phnum; i++, ph++) + { + if (ph->p_type != PT_LOAD || ph->p_filesz == 0) + { + continue; + } + + nphs++; + psize += alignup(ph->p_filesz, 16); + } + + imgsize = sizeof(*header) + snlen + (nphs * 16) + psize; + + img = (char *)malloc(imgsize + 32); + if (!img) + { + return NULL; + } + + *image_size = imgsize; + sym = elf->symtab; + name = elf->string; + sp = 0; + + for (j = 0; j < elf->nsyms; j++, sym++) + { + if (!strcmp("__stack", name + sym->st_name)) + { + sp = sym->st_value; + } + } + + memset(img, 0, imgsize); + + header = (struct spk_header *)img; + header->magic[0] = 0xef; + header->magic[1] = 'M'; + header->magic[2] = 'O'; + header->magic[3] = 'D'; + header->cpu = core; + + header->entry = elf->ehdr->e_entry; + header->stack = sp; + header->core = core; + + header->binaries = nphs; + header->phoffs = sizeof(*header) + snlen; + header->mode = 0777; + + strncpy(img + sizeof(*header), savename, 63); + + ph = elf->phdr; + pi = (struct spk_prog_info *)(img + header->phoffs); + offset = ((char *)pi - img) + (nphs * sizeof(*pi)); + for (i = 0; i < elf->ehdr->e_phnum; i++, ph++) + { + if (ph->p_type != PT_LOAD || ph->p_filesz == 0) + continue; + pi->load_address = ph->p_paddr; + pi->offset = offset; + pi->size = alignup(ph->p_filesz, 16); /* need 16 bytes align for + * decryption */ + pi->memsize = ph->p_memsz; + + memcpy(img + pi->offset, elf->data + ph->p_offset, ph->p_filesz); + + offset += alignup(ph->p_filesz, 16); + pi++; + } + + return img; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int main(int argc, char **argv) +{ + struct args *args; + struct elf_file *elf; + struct cipher *c; + uint8_t *spkimage; + int size = 0; + FILE *fp; + char footer[16]; + + args = parse_args(argc, argv); + + elf = load_elf(args->elffile); + if (!elf) + { + fprintf(stderr, "Loading ELF %s failure.\n", args->elffile); + exit(EXIT_FAILURE); + } + + spkimage = create_image(elf, args->core, args->savename, &size); + free(elf); + + c = cipher_init(vmk, NULL); + cipher_calc_cmac(c, spkimage, size, (uint8_t *) spkimage + size); + cipher_deinit(c); + + size += 16; /* Extend CMAC size */ + + snprintf(footer, 16, "MKSPK_BN_HOOTER"); + footer[15] = '\0'; + + fp = fopen(args->outputfile, "wb"); + if (!fp) + { + fprintf(stderr, "Output file open error.\n"); + free(spkimage); + exit(EXIT_FAILURE); + } + + fwrite(spkimage, size, 1, fp); + fwrite(footer, 16, 1, fp); + + fclose(fp); + + printf("File %s is successfully created.\n", args->outputfile); + free(args->outputfile); + + memset(spkimage, 0, size); + free(spkimage); + + exit(EXIT_SUCCESS); +} diff --git a/tinyusb/hw/mcu/sony/cxd56/mkspk/mkspk.h b/tinyusb/hw/mcu/sony/cxd56/mkspk/mkspk.h new file mode 100755 index 00000000..5c1b979c --- /dev/null +++ b/tinyusb/hw/mcu/sony/cxd56/mkspk/mkspk.h @@ -0,0 +1,93 @@ +/**************************************************************************** + * tools/cxd56/mkspk.h + * + * Copyright (C) 2007, 2008 Sony Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "clefia.h" +#include "elf32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define EI_MAG0 0 /* File identification */ +#define EI_MAG1 1 +#define EI_MAG2 2 +#define EI_MAG3 3 + +#define SHT_SYMTAB 2 +#define SHT_STRTAB 3 + +#define PT_LOAD 1 + +#define alignup(x, a) (((x) + ((a) - 1)) & ~((a) - 1)) +#define swap(a, b) { (a) ^= (b); (b) ^= (a); (a) ^= (b); } + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +struct spk_header + { + uint8_t magic[4]; + uint8_t cpu; + uint8_t reserved[11]; + uint32_t entry; + uint32_t stack; + uint16_t core; + uint16_t binaries; + uint16_t phoffs; + uint16_t mode; + }; + +struct spk_prog_info + { + uint32_t load_address; + uint32_t offset; + uint32_t size; + uint32_t memsize; + }; + +struct elf_file + { + Elf32_Ehdr *ehdr; + Elf32_Phdr *phdr; + Elf32_Shdr *shdr; + Elf32_Sym *symtab; + int nsyms; + char *shstring; + char *string; + char *data; + }; diff --git a/tinyusb/hw/mcu/sony/cxd56/tools/__pycache__/xmodem.cpython-36.pyc b/tinyusb/hw/mcu/sony/cxd56/tools/__pycache__/xmodem.cpython-36.pyc Binary files differnew file mode 100755 index 00000000..cfa917f7 --- /dev/null +++ b/tinyusb/hw/mcu/sony/cxd56/tools/__pycache__/xmodem.cpython-36.pyc diff --git a/tinyusb/hw/mcu/sony/cxd56/tools/flash_writer.py b/tinyusb/hw/mcu/sony/cxd56/tools/flash_writer.py new file mode 100755 index 00000000..840f10c3 --- /dev/null +++ b/tinyusb/hw/mcu/sony/cxd56/tools/flash_writer.py @@ -0,0 +1,580 @@ +#! /usr/bin/env python3 + +# Copyright (C) 2018 Sony Semiconductor Solutions Corp. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +import time +import sys +import os +import struct +import glob +import fnmatch +import errno +import telnetlib +import argparse +import shutil +import subprocess +import re +import xmodem + +import_serial_module = True + +# When SDK release, plase set SDK_RELEASE as True. +SDK_RELEASE = False + +if SDK_RELEASE : + PRINT_RAW_COMMAND = False + REBOOT_AT_END = True +else : + PRINT_RAW_COMMAND = True + REBOOT_AT_END = True + +try: + import serial +except: + import_serial_module = False + +# supported environment various +# CXD56_PORT +# CXD56_TELNETSRV_PORT +# CXD56_TELNETSRV_IP + +PROTOCOL_SERIAL = 0 +PROTOCOL_TELNET = 1 + +MAX_DOT_COUNT = 70 + +# configure parameters and default value +class ConfigArgs: + PROTOCOL_TYPE = None + SERIAL_PORT = "COM1" + SERVER_PORT = 4569 + SERVER_IP = "localhost" + EOL = bytes([10]) + WAIT_RESET = True + AUTO_RESET = False + DTR_RESET = False + XMODEM_BAUD = 0 + NO_SET_BOOTABLE = False + PACKAGE_NAME = [] + FILE_NAME = [] + ERASE_NAME = [] + PKGSYS_NAME = [] + PKGAPP_NAME = [] + PKGUPD_NAME = [] + +ROM_MSG = [b"Welcome to nash"] +XMDM_MSG = "Waiting for XMODEM (CRC or 1K) transfer. Ctrl-X to cancel." + +class ConfigArgsLoader(): + def __init__(self): + self.parser = argparse.ArgumentParser(formatter_class=argparse.RawTextHelpFormatter) + self.parser.add_argument("package_name", help="the name of the package to install", nargs='*') + self.parser.add_argument("-f", "--file", dest="file_name", help="save file", action='append') + self.parser.add_argument("-e", "--erase", dest="erase_name", help="erase file", action='append') + + self.parser.add_argument("-S", "--sys", dest="pkgsys_name", help="the name of the system package to install", action='append') + self.parser.add_argument("-A", "--app", dest="pkgapp_name", help="the name of the application package to install", action='append') + self.parser.add_argument("-U", "--upd", dest="pkgupd_name", help="the name of the updater package to install", action='append') + + self.parser.add_argument("-a", "--auto-reset", dest="auto_reset", + action="store_true", default=None, + help="try to auto reset develop board if possible") + self.parser.add_argument("-d", "--dtr-reset", dest="dtr_reset", + action="store_true", default=None, + help="try to auto reset develop board if possible") + self.parser.add_argument("-n", "--no-set-bootable", dest="no_set_bootable", + action="store_true", default=None, + help="not to set bootable") + + group = self.parser.add_argument_group() + group.add_argument("-i", "--server-ip", dest="server_ip", + help="the ip address connected to the telnet server") + group.add_argument("-p", "--server-port", dest="server_port", type=int, + help="the port connected to the telnet server") + + group = self.parser.add_argument_group() + group.add_argument("-c", "--serial-port", dest="serial_port", help="the serial port") + group.add_argument("-b", "--xmodem-baudrate", dest="xmodem_baud", help="Use the faster baudrate in xmodem") + + mutually_group = self.parser.add_mutually_exclusive_group() + mutually_group.add_argument("-t", "--telnet-protocol", dest="telnet_protocol", + action="store_true", default=None, + help="use the telnet protocol for binary transmission") + mutually_group.add_argument("-s", "--serial-protocol", dest="serial_protocol", + action="store_true", default=None, + help="use the serial port for binary transmission, default options") + + mutually_group2 = self.parser.add_mutually_exclusive_group() + mutually_group2.add_argument("-F", "--force-wait-reset", dest="wait_reset", + action="store_true", default=None, + help="force wait for pressing RESET button") + mutually_group2.add_argument("-N", "--no-wait-reset", dest="wait_reset", + action="store_false", default=None, + help="if possible, skip to wait for pressing RESET button") + + def update_config(self): + args = self.parser.parse_args() + + ConfigArgs.PACKAGE_NAME = args.package_name + ConfigArgs.FILE_NAME = args.file_name + ConfigArgs.ERASE_NAME = args.erase_name + ConfigArgs.PKGSYS_NAME = args.pkgsys_name + ConfigArgs.PKGAPP_NAME = args.pkgapp_name + ConfigArgs.PKGUPD_NAME = args.pkgupd_name + + # Get serial port or telnet server ip etc + if args.serial_protocol == True: + ConfigArgs.PROTOCOL_TYPE = PROTOCOL_SERIAL + elif args.telnet_protocol == True: + ConfigArgs.PROTOCOL_TYPE = PROTOCOL_TELNET + + if ConfigArgs.PROTOCOL_TYPE == None: + proto = os.environ.get("CXD56_PROTOCOL") + if proto is not None: + if 's' in proto: + ConfigArgs.PROTOCOL_TYPE = PROTOCOL_SERIAL + elif 't' in proto: + ConfigArgs.PROTOCOL_TYPE = PROTOCOL_TELNET + + if ConfigArgs.PROTOCOL_TYPE == None: + ConfigArgs.PROTOCOL_TYPE = PROTOCOL_SERIAL + + if ConfigArgs.PROTOCOL_TYPE == PROTOCOL_SERIAL: + if args.serial_port is not None: + ConfigArgs.SERIAL_PORT = args.serial_port + else: + # Get serial port from the environment + port = os.environ.get("CXD56_PORT") + if port is not None: + ConfigArgs.SERIAL_PORT = port + else: + print("CXD56_PORT is not set, Use " + ConfigArgs.SERIAL_PORT + ".") + else: + ConfigArgs.PROTOCOL_TYPE = PROTOCOL_TELNET + if args.server_port is not None: + ConfigArgs.SERVER_PORT = args.server_port + else: + port = os.environ.get("CXD56_TELNETSRV_PORT") + if port is not None: + ConfigArgs.SERVER_PORT = port + else: + print("CXD56_TELNETSRV_PORT is not set, Use " + str(ConfigArgs.SERVER_PORT) + ".") + if args.server_ip is not None: + ConfigArgs.SERVER_IP = args.server_ip + else: + ip = os.environ.get("CXD56_TELNETSRV_IP") + if ip is not None: + ConfigArgs.SERVER_IP = ip + else: + print("CXD56_TELNETSRV_IP is not set, Use " + ConfigArgs.SERVER_IP + ".") + + if args.xmodem_baud is not None: + ConfigArgs.XMODEM_BAUD = args.xmodem_baud + + if args.auto_reset is not None: + ConfigArgs.AUTO_RESET = args.auto_reset + + if args.dtr_reset is not None: + ConfigArgs.DTR_RESET = args.dtr_reset + + if args.no_set_bootable is not None: + ConfigArgs.NO_SET_BOOTABLE = args.no_set_bootable + + if args.wait_reset is not None: + ConfigArgs.WAIT_RESET = args.wait_reset + +class TelnetDev: + def __init__(self): + srv_ipaddr = ConfigArgs.SERVER_IP + srv_port = ConfigArgs.SERVER_PORT + self.recvbuf = b''; + try: + self.telnet = telnetlib.Telnet(host=srv_ipaddr, port=srv_port, timeout=10) + # There is a ack to be sent after connecting to the telnet server. + self.telnet.write(b"\xff") + except Exception as e: + print("Cannot connect to the server %s:%d" % (srv_ipaddr, srv_port)) + sys.exit(e.args[0]) + + def readline(self, size=None): + res = b'' + ch = b'' + while ch != ConfigArgs.EOL: + ch = self.getc_raw(1, timeout=0.1) + if ch == b'': + return res + res += ch + return res + + def getc_raw(self, size, timeout=1): + res = b'' + tm = time.monotonic() + while size > 0: + while self.recvbuf == b'': + self.recvbuf = self.telnet.read_eager() + if self.recvbuf == b'': + if (time.monotonic() - tm) > timeout: + return res + time.sleep(0.1) + res += self.recvbuf[0:1] + self.recvbuf = self.recvbuf[1:] + size -= 1 + return res + + def write(self, buffer): + self.telnet.write(buffer) + + def discard_inputs(self, timeout=1.0): + while True: + ch = self.getc_raw(1, timeout=timeout) + if ch == b'': + break + + def getc(self, size, timeout=1): + c = self.getc_raw(size, timeout) + return c + + def putc(self, buffer, timeout=1): + self.telnet.write(buffer) + self.show_progress(len(buffer)) + + def reboot(self): + # no-op + pass + + def set_file_size(self, filesize): + self.bytes_transfered = 0 + self.filesize = filesize + self.count = 0 + + def show_progress(self, sendsize): + if PRINT_RAW_COMMAND: + if self.count < MAX_DOT_COUNT: + self.bytes_transfered = self.bytes_transfered + sendsize + cur_count = int(self.bytes_transfered * MAX_DOT_COUNT / self.filesize) + if MAX_DOT_COUNT < cur_count: + cur_count = MAX_DOT_COUNT + for idx in range(cur_count - self.count): + print('#',end='') + sys.stdout.flush() + self.count = cur_count + if self.count == MAX_DOT_COUNT: + print("\n") + +class SerialDev: + def __init__(self): + if import_serial_module is False: + print("Cannot import serial module, maybe it's not install yet.") + print("\n", end="") + print("Please install python-setuptool by Cygwin installer.") + print("After that use easy_intall command to install serial module") + print(" $ cd tool/") + print(" $ python3 -m easy_install pyserial-2.7.tar.gz") + quit() + else: + port = ConfigArgs.SERIAL_PORT + try: + self.serial = serial.Serial(port, baudrate=115200, + parity=serial.PARITY_NONE, stopbits=serial.STOPBITS_ONE, + bytesize=serial.EIGHTBITS, timeout=0.1) + except Exception as e: + print("Cannot open port : " + port) + sys.exit(e.args[0]) + + def readline(self, size=None): + return self.serial.readline(size) + + def write(self, buffer): + self.serial.write(buffer) + self.serial.flush() + + def discard_inputs(self, timeout=1.0): + time.sleep(timeout) + self.serial.flushInput() + + def getc(self, size, timeout=1): + self.serial.timeout = timeout + c = self.serial.read(size) + self.serial.timeout = 0.1 + return c + + def putc(self, buffer, timeout=1): + self.serial.timeout = timeout + self.serial.write(buffer) + self.serial.flush() + self.serial.timeout = 0.1 + self.show_progress(len(buffer)) + + # Note: windows platform dependent code + def putc_win(self, buffer, timeout=1): + self.serial.write(buffer) + self.show_progress(len(buffer)) + while True: + if self.serial.out_waiting == 0: + break + + def setBaudrate(self, baudrate): +# self.serial.setBaudrate(baudrate) + self.serial.baudrate = baudrate + + def reboot(self): + # Target Reset by DTR + self.serial.setDTR(False) + self.serial.setDTR(True) + self.serial.setDTR(False) + + def set_file_size(self, filesize): + self.bytes_transfered = 0 + self.filesize = filesize + self.count = 0 + + def show_progress(self, sendsize): + if PRINT_RAW_COMMAND: + if self.count < MAX_DOT_COUNT: + self.bytes_transfered = self.bytes_transfered + sendsize + cur_count = int(self.bytes_transfered * MAX_DOT_COUNT / self.filesize) + if MAX_DOT_COUNT < cur_count: + cur_count = MAX_DOT_COUNT + for idx in range(cur_count - self.count): + print('#',end='') + sys.stdout.flush() + self.count = cur_count + if self.count == MAX_DOT_COUNT: + print("\n") + +class FlashWriter: + def __init__(self, protocol_sel=PROTOCOL_SERIAL): + if protocol_sel == PROTOCOL_TELNET: + self.serial = TelnetDev() + else: + self.serial = SerialDev() + + def cancel_autoboot(self) : + boot_msg = '' + self.serial.reboot() # Target reboot before send 'r' + while boot_msg == '' : + rx = self.serial.readline().strip() + self.serial.write(b"r") # Send "r" key to avoid auto boot + for msg in ROM_MSG : + if msg in rx : + boot_msg = msg + break + while True : + rx = self.serial.readline().decode(errors="replace").strip() + if "updater" in rx : + # Workaround : Sometime first character is dropped. + # Send line feed as air shot before actual command. + self.serial.write(b"\n") # Send line feed + self.serial.discard_inputs()# Clear input buffer to sync + return boot_msg.decode(errors="ignore") + + def recv(self): + rx = self.serial.readline() + if PRINT_RAW_COMMAND : + serial_line = rx.decode(errors="replace") + if serial_line.strip() != "" and not serial_line.startswith(XMDM_MSG): + print(serial_line, end="") + return rx + + def wait(self, string): + while True: + rx = self.recv() + if string.encode() in rx: + time.sleep(0.1) + break + + def wait_for_prompt(self): + prompt_pat = re.compile(b"updater") + while True: + rx = self.recv() + if prompt_pat.search(rx): + time.sleep(0.1) + break + + def send(self, string): + self.serial.write(str(string).encode() + b"\n") + rx = self.serial.readline() + if PRINT_RAW_COMMAND : + print(rx.decode(errors="replace"), end="") + + def read_output(self, prompt_text) : + output = [] + while True : + rx = self.serial.readline() + if prompt_text.encode() in rx : + time.sleep(0.1) + break + if rx != "" : + output.append(rx.decode(errors="ignore").rstrip()) + return output + + def install_files(self, files, command) : + if ConfigArgs.XMODEM_BAUD: + command += " -b " + ConfigArgs.XMODEM_BAUD + if os.name == 'nt': + modem = xmodem.XMODEM(self.serial.getc, self.serial.putc_win, 'xmodem1k') + else: + modem = xmodem.XMODEM(self.serial.getc, self.serial.putc, 'xmodem1k') + for file in files: + with open(file, "rb") as bin : + self.send(command) + print("Install " + file) + self.wait(XMDM_MSG) + print("|0%" + + "-" * (int(MAX_DOT_COUNT / 2) - 6) + + "50%" + + "-" * (MAX_DOT_COUNT - int(MAX_DOT_COUNT / 2) - 5) + + "100%|") + if ConfigArgs.XMODEM_BAUD: + self.serial.setBaudrate(ConfigArgs.XMODEM_BAUD) + self.serial.discard_inputs() # Clear input buffer to sync + self.serial.set_file_size(os.path.getsize(file)) + modem.send(bin) + if ConfigArgs.XMODEM_BAUD: + self.serial.setBaudrate(115200) + self.wait_for_prompt() + + def save_files(self, files) : + if ConfigArgs.XMODEM_BAUD: + command = "save_file -b " + ConfigArgs.XMODEM_BAUD + " -x " + else: + command = "save_file -x " + if os.name == 'nt': + modem = xmodem.XMODEM(self.serial.getc, self.serial.putc_win, 'xmodem1k') + else: + modem = xmodem.XMODEM(self.serial.getc, self.serial.putc, 'xmodem1k') + for file in files: + with open(file, "rb") as bin : + self.send(command + os.path.basename(file)) + print("Save " + file) + self.wait(XMDM_MSG) + if ConfigArgs.XMODEM_BAUD: + self.serial.setBaudrate(ConfigArgs.XMODEM_BAUD) + self.serial.discard_inputs() # Clear input buffer to sync + self.serial.set_file_size(os.path.getsize(file)) + modem.send(bin) + if ConfigArgs.XMODEM_BAUD: + self.serial.setBaudrate(115200) + self.wait_for_prompt() + self.send("chmod d+rw " + os.path.basename(file)) + self.wait_for_prompt() + + def delete_files(self, files) : + for file in files : + self.delete_binary(file) + + def delete_binary(self, bin_name) : + self.send("rm " + bin_name) + self.wait_for_prompt() + +def main(): + try: + config_loader = ConfigArgsLoader() + config_loader.update_config() + except: + return errno.EINVAL + + # Wait to reset the board + writer = FlashWriter(ConfigArgs.PROTOCOL_TYPE) + + do_wait_reset = True + if ConfigArgs.AUTO_RESET: + if subprocess.call("cd " + sys.path[0] + "; ./reset_board.sh", shell=True) == 0: + print("auto reset board sucess!!") + do_wait_reset = False + bootrom_msg = writer.cancel_autoboot() + + if ConfigArgs.DTR_RESET: + do_wait_reset = False + bootrom_msg = writer.cancel_autoboot() + + if ConfigArgs.WAIT_RESET == False and do_wait_reset == True: + rx = writer.recv() + time.sleep(1) + for i in range(3): + writer.send("") + rx = writer.recv() + if "updater".encode() in rx: + # No need to wait for reset + do_wait_reset = False + break + time.sleep(1) + + if do_wait_reset: + # Wait to reset the board + print('Please press RESET button on target board') + sys.stdout.flush() + bootrom_msg = writer.cancel_autoboot() + + # Remove files + if ConfigArgs.ERASE_NAME : + print(">>> Remove exisiting files ...") + writer.delete_files(ConfigArgs.ERASE_NAME) + + # Install files + if ConfigArgs.PACKAGE_NAME or ConfigArgs.PKGSYS_NAME or ConfigArgs.PKGAPP_NAME or ConfigArgs.PKGUPD_NAME: + print(">>> Install files ...") + if ConfigArgs.PACKAGE_NAME : + writer.install_files(ConfigArgs.PACKAGE_NAME, "install") + if ConfigArgs.PKGSYS_NAME : + writer.install_files(ConfigArgs.PKGSYS_NAME, "install") + if ConfigArgs.PKGAPP_NAME : + writer.install_files(ConfigArgs.PKGAPP_NAME, "install") + if ConfigArgs.PKGUPD_NAME : + writer.install_files(ConfigArgs.PKGUPD_NAME, "install -k updater.key") + + # Save files + if ConfigArgs.FILE_NAME : + print(">>> Save files ...") + writer.save_files(ConfigArgs.FILE_NAME) + + # Set auto boot + if not ConfigArgs.NO_SET_BOOTABLE: + print(">>> Save Configuration to FlashROM ...") + writer.send("set bootable M0P") + writer.wait_for_prompt() + + # Sync all cached data to flash + writer.send("sync") + writer.wait_for_prompt() + + if REBOOT_AT_END : + print("Restarting the board ...") + writer.send("reboot") + + return 0 + +if __name__ == "__main__": + try: + sys.exit(main()) + except KeyboardInterrupt: + print("Canceled by keyboard interrupt.") + pass diff --git a/tinyusb/hw/mcu/sony/cxd56/tools/xmodem.py b/tinyusb/hw/mcu/sony/cxd56/tools/xmodem.py new file mode 100755 index 00000000..c9343005 --- /dev/null +++ b/tinyusb/hw/mcu/sony/cxd56/tools/xmodem.py @@ -0,0 +1,590 @@ +''' +=============================== + XMODEM file transfer protocol +=============================== + +.. $Id$ + +This is a literal implementation of XMODEM.TXT_, XMODEM1K.TXT_ and +XMODMCRC.TXT_, support for YMODEM and ZMODEM is pending. YMODEM should +be fairly easy to implement as it is a hack on top of the XMODEM +protocol using sequence bytes ``0x00`` for sending file names (and some +meta data). + +.. _XMODEM.TXT: doc/XMODEM.TXT +.. _XMODEM1K.TXT: doc/XMODEM1K.TXT +.. _XMODMCRC.TXT: doc/XMODMCRC.TXT + +Data flow example including error recovery +========================================== + +Here is a sample of the data flow, sending a 3-block message. +It includes the two most common line hits - a garbaged block, +and an ``ACK`` reply getting garbaged. ``CRC`` or ``CSUM`` represents +the checksum bytes. + +XMODEM 128 byte blocks +---------------------- + +:: + + SENDER RECEIVER + + <-- NAK + SOH 01 FE Data[128] CSUM --> + <-- ACK + SOH 02 FD Data[128] CSUM --> + <-- ACK + SOH 03 FC Data[128] CSUM --> + <-- ACK + SOH 04 FB Data[128] CSUM --> + <-- ACK + SOH 05 FA Data[100] CPMEOF[28] CSUM --> + <-- ACK + EOT --> + <-- ACK + +XMODEM-1k blocks, CRC mode +-------------------------- + +:: + + SENDER RECEIVER + + <-- C + STX 01 FE Data[1024] CRC CRC --> + <-- ACK + STX 02 FD Data[1024] CRC CRC --> + <-- ACK + STX 03 FC Data[1000] CPMEOF[24] CRC CRC --> + <-- ACK + EOT --> + <-- ACK + +Mixed 1024 and 128 byte Blocks +------------------------------ + +:: + + SENDER RECEIVER + + <-- C + STX 01 FE Data[1024] CRC CRC --> + <-- ACK + STX 02 FD Data[1024] CRC CRC --> + <-- ACK + SOH 03 FC Data[128] CRC CRC --> + <-- ACK + SOH 04 FB Data[100] CPMEOF[28] CRC CRC --> + <-- ACK + EOT --> + <-- ACK + +YMODEM Batch Transmission Session (1 file) +------------------------------------------ + +:: + + SENDER RECEIVER + <-- C (command:rb) + SOH 00 FF foo.c NUL[123] CRC CRC --> + <-- ACK + <-- C + SOH 01 FE Data[128] CRC CRC --> + <-- ACK + SOH 02 FC Data[128] CRC CRC --> + <-- ACK + SOH 03 FB Data[100] CPMEOF[28] CRC CRC --> + <-- ACK + EOT --> + <-- NAK + EOT --> + <-- ACK + <-- C + SOH 00 FF NUL[128] CRC CRC --> + <-- ACK + + +''' + +__author__ = 'Wijnand Modderman <maze@pyth0n.org>' +__copyright__ = ['Copyright (c) 2010 Wijnand Modderman', + 'Copyright (c) 1981 Chuck Forsberg'] +__license__ = 'MIT' +__version__ = '0.3.2' + +import logging +import time +import sys +from functools import partial +import collections + +# Loggerr +log = logging.getLogger('xmodem') + +# Protocol bytes +SOH = bytes([0x01]) +STX = bytes([0x02]) +EOT = bytes([0x04]) +ACK = bytes([0x06]) +DLE = bytes([0x10]) +NAK = bytes([0x15]) +CAN = bytes([0x18]) +CRC = bytes([0x43]) # C + + +class XMODEM(object): + ''' + XMODEM Protocol handler, expects an object to read from and an object to + write to. + + >>> def getc(size, timeout=1): + ... return data or None + ... + >>> def putc(data, timeout=1): + ... return size or None + ... + >>> modem = XMODEM(getc, putc) + + + :param getc: Function to retreive bytes from a stream + :type getc: callable + :param putc: Function to transmit bytes to a stream + :type putc: callable + :param mode: XMODEM protocol mode + :type mode: string + :param pad: Padding character to make the packets match the packet size + :type pad: char + + ''' + + # crctab calculated by Mark G. Mendel, Network Systems Corporation + crctable = [ + 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, + 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, + 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, + 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, + 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, + 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, + 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, + 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, + 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, + 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, + 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, + 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, + 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, + 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, + 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, + 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, + 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, + 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, + 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, + 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, + 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, + 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, + 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, + 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, + 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, + 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, + 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, + 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, + 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, + 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, + 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0, + ] + + def __init__(self, getc, putc, mode='xmodem', pad=b'\x1a'): + self.getc = getc + self.putc = putc + self.mode = mode + self.pad = pad + + def abort(self, count=2, timeout=60): + ''' + Send an abort sequence using CAN bytes. + ''' + for counter in range(0, count): + self.putc(CAN, timeout) + + def send(self, stream, retry=32, timeout=360, quiet=0, callback=None): + ''' + Send a stream via the XMODEM protocol. + + >>> stream = file('/etc/issue', 'rb') + >>> print modem.send(stream) + True + + Returns ``True`` upon succesful transmission or ``False`` in case of + failure. + + :param stream: The stream object to send data from. + :type stream: stream (file, etc.) + :param retry: The maximum number of times to try to resend a failed + packet before failing. + :type retry: int + :param timeout: The number of seconds to wait for a response before + timing out. + :type timeout: int + :param quiet: If 0, it prints info to stderr. If 1, it does not print any info. + :type quiet: int + :param callback: Reference to a callback function that has the + following signature. This is useful for + getting status updates while a xmodem + transfer is underway. + Expected callback signature: + def callback(total_packets, success_count, error_count) + :type callback: callable + ''' + + # initialize protocol + try: + packet_size = dict( + xmodem = 128, + xmodem1k = 1024, + )[self.mode] + except AttributeError: + raise ValueError("An invalid mode was supplied") + + error_count = 0 + crc_mode = 0 + cancel = 0 + while True: + char = self.getc(1) + if char: + if char == NAK: + crc_mode = 0 + break + elif char == CRC: + crc_mode = 1 + break + elif char == CAN: + if not quiet: + print('received CAN', file=sys.stderr) + if cancel: + return False + else: + cancel = 1 + else: + log.error('send ERROR expected NAK/CRC, got %s' % \ + (ord(char),)) + + error_count += 1 + if error_count >= retry: + self.abort(timeout=timeout) + return False + + # send data + error_count = 0 + success_count = 0 + total_packets = 0 + sequence = 1 + while True: + data = stream.read(packet_size) + if not data: + log.info('sending EOT') + # end of stream + break + total_packets += 1 + data = data.ljust(packet_size, self.pad) + if crc_mode: + crc = self.calc_crc(data) + else: + crc = self.calc_checksum(data) + + # emit packet + while True: + if packet_size == 128: + self.putc(SOH) + else: # packet_size == 1024 + self.putc(STX) + self.putc(bytes([sequence])) + self.putc(bytes([0xff - sequence])) + self.putc(data) + if crc_mode: + self.putc(bytes([crc >> 8])) + self.putc(bytes([crc & 0xff])) + else: + self.putc(bytes([crc])) + + char = self.getc(1, timeout) + if char == ACK: + success_count += 1 + if isinstance(callback, collections.Callable): + callback(total_packets, success_count, error_count) + break + if char == NAK: + error_count += 1 + if isinstance(callback, collections.Callable): + callback(total_packets, success_count, error_count) + if error_count >= retry: + # excessive amounts of retransmissions requested, + # abort transfer + self.abort(timeout=timeout) + log.warning('excessive NAKs, transfer aborted') + return False + + # return to loop and resend + continue + else: + log.error('Not ACK, Not NAK') + error_count += 1 + if isinstance(callback, collections.Callable): + callback(total_packets, success_count, error_count) + if error_count >= retry: + # excessive amounts of retransmissions requested, + # abort transfer + self.abort(timeout=timeout) + log.warning('excessive protocol errors, transfer aborted') + return False + + # return to loop and resend + continue + + # protocol error + self.abort(timeout=timeout) + log.error('protocol error') + return False + + # keep track of sequence + sequence = (sequence + 1) % 0x100 + + while True: + # end of transmission + self.putc(EOT) + + #An ACK should be returned + char = self.getc(1, timeout) + if char == ACK: + break + else: + error_count += 1 + if error_count >= retry: + self.abort(timeout=timeout) + log.warning('EOT was not ACKd, transfer aborted') + return False + + return True + + def recv(self, stream, crc_mode=1, retry=16, timeout=60, delay=1, quiet=0): + ''' + Receive a stream via the XMODEM protocol. + + >>> stream = file('/etc/issue', 'wb') + >>> print modem.recv(stream) + 2342 + + Returns the number of bytes received on success or ``None`` in case of + failure. + ''' + + # initiate protocol + error_count = 0 + char = 0 + cancel = 0 + while True: + # first try CRC mode, if this fails, + # fall back to checksum mode + if error_count >= retry: + self.abort(timeout=timeout) + return None + elif crc_mode and error_count < (retry / 2): + if not self.putc(CRC): + time.sleep(delay) + error_count += 1 + else: + crc_mode = 0 + if not self.putc(NAK): + time.sleep(delay) + error_count += 1 + + char = self.getc(1, timeout) + if not char: + error_count += 1 + continue + elif char == SOH: + #crc_mode = 0 + break + elif char == STX: + break + elif char == CAN: + if cancel: + return None + else: + cancel = 1 + else: + error_count += 1 + + # read data + error_count = 0 + income_size = 0 + packet_size = 128 + sequence = 1 + cancel = 0 + while True: + while True: + if char == SOH: + packet_size = 128 + break + elif char == STX: + packet_size = 1024 + break + elif char == EOT: + # We received an EOT, so send an ACK and return the received + # data length + self.putc(ACK) + return income_size + elif char == CAN: + # cancel at two consecutive cancels + if cancel: + return None + else: + cancel = 1 + else: + if not quiet: + print('recv ERROR expected SOH/EOT, got', ord(char), file=sys.stderr) + error_count += 1 + if error_count >= retry: + self.abort() + return None + # read sequence + error_count = 0 + cancel = 0 + seq1 = ord(self.getc(1)) + seq2 = 0xff - ord(self.getc(1)) + if seq1 == sequence and seq2 == sequence: + # sequence is ok, read packet + # packet_size + checksum + data = self.getc(packet_size + 1 + crc_mode, timeout) + if crc_mode: + csum = (ord(data[-2]) << 8) + ord(data[-1]) + data = data[:-2] + log.debug('CRC (%04x <> %04x)' % \ + (csum, self.calc_crc(data))) + valid = csum == self.calc_crc(data) + else: + csum = data[-1] + data = data[:-1] + log.debug('checksum (checksum(%02x <> %02x)' % \ + (ord(csum), self.calc_checksum(data))) + valid = ord(csum) == self.calc_checksum(data) + + # valid data, append chunk + if valid: + income_size += len(data) + stream.write(data) + self.putc(ACK) + sequence = (sequence + 1) % 0x100 + char = self.getc(1, timeout) + continue + else: + # consume data + self.getc(packet_size + 1 + crc_mode) + self.debug('expecting sequence %d, got %d/%d' % \ + (sequence, seq1, seq2)) + + # something went wrong, request retransmission + self.putc(NAK) + + def calc_checksum(self, data, checksum=0): + ''' + Calculate the checksum for a given block of data, can also be used to + update a checksum. + + >>> csum = modem.calc_checksum('hello') + >>> csum = modem.calc_checksum('world', csum) + >>> hex(csum) + '0x3c' + + ''' + return (sum(map(ord, data)) + checksum) % 256 + + def calc_crc(self, data, crc=0): + ''' + Calculate the Cyclic Redundancy Check for a given block of data, can + also be used to update a CRC. + + >>> crc = modem.calc_crc('hello') + >>> crc = modem.calc_crc('world', crc) + >>> hex(crc) + '0xd5e3' + + ''' + for char in data: + crc = (crc << 8) ^ self.crctable[((crc >> 8) ^ int(char)) & 0xff] + return crc & 0xffff + + +XMODEM1k = partial(XMODEM, mode='xmodem1k') + + +def run(): + import optparse + import subprocess + + parser = optparse.OptionParser(usage='%prog [<options>] <send|recv> filename filename') + parser.add_option('-m', '--mode', default='xmodem', + help='XMODEM mode (xmodem, xmodem1k)') + + options, args = parser.parse_args() + if len(args) != 3: + parser.error('invalid arguments') + return 1 + + elif args[0] not in ('send', 'recv'): + parser.error('invalid mode') + return 1 + + def _func(so, si): + import select + import subprocess + + print('si', si) + print('so', so) + + def getc(size, timeout=3): + w,t,f = select.select([so], [], [], timeout) + if w: + data = so.read(size) + else: + data = None + + print('getc(', repr(data), ')') + return data + + def putc(data, timeout=3): + w,t,f = select.select([], [si], [], timeout) + if t: + si.write(data) + si.flush() + size = len(data) + else: + size = None + + print('putc(', repr(data), repr(size), ')') + return size + + return getc, putc + + def _pipe(*command): + pipe = subprocess.Popen(command, + stdout=subprocess.PIPE, stdin=subprocess.PIPE) + return pipe.stdout, pipe.stdin + + if args[0] == 'recv': + import io + getc, putc = _func(*_pipe('sz', '--xmodem', args[2])) + stream = open(args[1], 'wb') + xmodem = XMODEM(getc, putc, mode=options.mode) + status = xmodem.recv(stream, retry=8) + stream.close() + + elif args[0] == 'send': + getc, putc = _func(*_pipe('rz', '--xmodem', args[2])) + stream = open(args[1], 'rb') + xmodem = XMODEM(getc, putc, mode=options.mode) + status = xmodem.send(stream, retry=8) + stream.close() + +if __name__ == '__main__': + sys.exit(run()) |