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authorJoey Castillo <jose.castillo@gmail.com>2021-10-23 16:44:20 -0400
committerJoey Castillo <jose.castillo@gmail.com>2021-10-23 16:44:20 -0400
commitee1b3c8780c5573a11cdd21620243ef4b0bd8488 (patch)
treef771c722f6ddc2357d1e76e734fb525592c13751 /boards
parent0b4d0de15b487b84dbd9b0dbebc4cd75ca64c93c (diff)
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fix typo
Diffstat (limited to 'boards')
-rw-r--r--boards/OSO-FEAL-A1-00/pins.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/boards/OSO-FEAL-A1-00/pins.h b/boards/OSO-FEAL-A1-00/pins.h
index 47d925cc..c860911f 100644
--- a/boards/OSO-FEAL-A1-00/pins.h
+++ b/boards/OSO-FEAL-A1-00/pins.h
@@ -65,7 +65,7 @@
// This board uses a slightly different pin mapping from the standard watch, and it's not enough to
// just declare the pins. We also have to set the LCD Pin Enable register with the SLCD pins we're
// using. These numbers are not port/pin numbers, but the "SLCD/LP[x]" numbers in the pinmux table.
-// If not defined in pins.h, the LCD drover will fall back to the pin mapping in hpl_slcd_config.h.
+// If not defined in pins.h, the LCD driver will fall back to the pin mapping in hpl_slcd_config.h.
// LPENL is for pins SLCD/LP[0..31].
#define CONF_SLCD_LPENL (\
(uint32_t)1 << 0 | \