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authorJoey Castillo <joeycastillo@utexas.edu>2022-02-23 10:04:19 -0500
committerJoey Castillo <joeycastillo@utexas.edu>2022-02-23 10:04:19 -0500
commita01ae5a232eeb9ea81ccc18a78595cd2f4ebbc2f (patch)
treee11ede658fdb5f0cf06638290c43b5b6a63d1f9f /PCB
parent24ff22df8a0982b70a4ab56d6a5da4142c591222 (diff)
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fatten GND wire to USB port
Diffstat (limited to 'PCB')
-rw-r--r--PCB/Main Boards/OSO-SWAT-A1-05.brd4
1 files changed, 4 insertions, 0 deletions
diff --git a/PCB/Main Boards/OSO-SWAT-A1-05.brd b/PCB/Main Boards/OSO-SWAT-A1-05.brd
index b6bbda2c..9712ae5a 100644
--- a/PCB/Main Boards/OSO-SWAT-A1-05.brd
+++ b/PCB/Main Boards/OSO-SWAT-A1-05.brd
@@ -3302,6 +3302,10 @@ Please make sure your boards conform to these design rules.
<via x="19.4056" y="7.4803" extent="1-16" drill="0.3048"/>
<via x="19.9136" y="5.1943" extent="1-16" drill="0.3048"/>
<via x="17.907" y="10.2235" extent="1-16" drill="0.3048"/>
+<wire x1="13.492" y1="22.836440625" x2="13.492" y2="21.4249" width="0.254" layer="1"/>
+<wire x1="13.492" y1="21.4249" x2="13.2334" y2="21.4249" width="0.254" layer="1"/>
+<wire x1="13.2334" y1="21.4249" x2="13.1826" y2="21.3741" width="0.254" layer="1"/>
+<wire x1="13.1826" y1="21.3741" x2="13.1826" y2="21.2725" width="0.254" layer="1"/>
</signal>
<signal name="!RESET">
<contactref element="!RST" pad="P$1"/>