From b3c6320899d6b27899ab3c67c745e8d3b29af3a2 Mon Sep 17 00:00:00 2001 From: root Date: Tue, 19 Feb 2019 13:46:18 +0000 Subject: working ethernet --- app/steth.c | 255 +++++++++++++++++++++++++++++++++++++----------------------- 1 file changed, 157 insertions(+), 98 deletions(-) (limited to 'app/steth.c') diff --git a/app/steth.c b/app/steth.c index d7eea7e..8672163 100644 --- a/app/steth.c +++ b/app/steth.c @@ -3,6 +3,9 @@ #define PHY PHY0 +#define RXER GPIO10 +#define RXER_PORT GPIOB + #define TXEN GPIO11 #define TXEN_PORT GPIOB @@ -53,6 +56,80 @@ extern uint32_t TxBD; extern uint32_t RxBD; +static void mac_stat(void) +{ + uint32_t d, s; + + printf ("Net:\r\n"); + printf (" ETH_MACCR: %08" PRIx32 "\r\n", ETH_MACCR); +#if 0 + printf (" ETH_MACFFR: %08" PRIx32 "\r\n", ETH_MACFFR); + printf (" ETH_MACFCR: %08" PRIx32 "\r\n", ETH_MACFCR); + printf (" ETH_MACDBGR: %08" PRIx32 "\r\n", ETH_MACDBGR); + printf (" ETH_MACSR: %08" PRIx32 "\r\n", ETH_MACSR); +#endif + printf (" ETH_DMAOMR: %08" PRIx32 "\r\n", ETH_DMAOMR); + printf (" ETH_DMASR: %08" PRIx32 " ebs=%x tps=%x rps=%x\r\n", ETH_DMASR, + (ETH_DMASR >>23) & 7 , + (ETH_DMASR >>20) & 7 , + (ETH_DMASR >>17) & 7 ); + printf (" ETH_DMAIER: %08" PRIx32 "\r\n", ETH_DMAIER); + printf (" ETH_DMACHTDR: %08" PRIx32 "\r\n", ETH_DMACHTDR); + printf (" ETH_DMACHRDR: %08" PRIx32 "\r\n", ETH_DMACHRDR); + printf (" ETH_DMAOMR: %08" PRIx32 "\r\n", ETH_DMAOMR); + printf (" ETH_DMATDLAR: %08" PRIx32 "\r\n", ETH_DMATDLAR); + printf (" ETH_DMARDLAR: %08" PRIx32 "\r\n", ETH_DMARDLAR); + printf (" ETH_DMABMR: %08" PRIx32 "\r\n", ETH_DMABMR); + + s = d = RxBD; + + +if (running) + do { + printf (" %08" PRIx32 ": %08" PRIx32 " %08" PRIx32 " %08" PRIx32 " %08" + PRIx32 "\r\n", d, ETH_DES0 (d), ETH_DES1 (d), ETH_DES2 (d), + ETH_DES3 (d)); + + d = ETH_DES3 (d); + + } while (d != s); + +} + +static void phy_stat_reg(unsigned i) +{ +static uint16_t last_phy[0x20]; +uint16_t cur=eth_smi_read(PHY,i); + +if (cur==last_phy[i]) return; + +printf(" phy:%02x %4x (was %4x +%4x -%4x)\r\n", + i,(unsigned) cur,(unsigned) last_phy[i], + (unsigned) ((last_phy[i] ^ cur) & cur), + (unsigned) ((last_phy[i] ^ cur) & last_phy[i])); + +last_phy[i]=cur; +} + +static void phy_stat(void) +{ + phy_stat_reg(0x0); + phy_stat_reg(0x1); + phy_stat_reg(0x4); + phy_stat_reg(0x5); + phy_stat_reg(0x6); + phy_stat_reg(0x11); + phy_stat_reg(0x12); + phy_stat_reg(0x1f); + + + + + +} + + + bool phy_link_an_done (uint8_t phy) @@ -110,6 +187,8 @@ steth_rx (void) struct pbuf *p; uint32_t len; +//printf("Packet\r\n"); + #if 0 struct pbuf *q; static uint8_t rx_buf[FRAME_SZ]; @@ -236,94 +315,112 @@ steth_init (void) { unsigned i; - MAP_AF (TXEN, GPIO_AF11); - MAP_AF (TXD0, GPIO_AF11); - MAP_AF (TXD1, GPIO_AF11); - - MAP_AF (RXD0, GPIO_AF11); - MAP_AF (RXD1, GPIO_AF11); - - MAP_AF (CRS_DV, GPIO_AF11); + rcc_periph_clock_enable (RCC_GPIOA); + rcc_periph_clock_enable (RCC_GPIOB); + rcc_periph_clock_enable (RCC_GPIOC); + rcc_periph_clock_enable (RCC_SYSCFG); + rcc_periph_clock_enable (RCC_ETHMAC); + rcc_periph_clock_enable (RCC_ETHMACTX); + rcc_periph_clock_enable (RCC_ETHMACRX); + rcc_periph_clock_enable (RCC_ETHMACPTP); - MAP_INPUT_PU(MDC); + rcc_periph_reset_hold(RST_ETHMAC); + delay_ms(1); - MAP_AF_PU (MDIO, GPIO_AF11); - MAP_AF_PU (MDC, GPIO_AF11); +#ifndef SYSCFG_PMC_MII_RMII_SEL +#define SYSCFG_PMC_MII_RMII_SEL (1UL << 23) +#endif - MAP_AF (REF_CLK, GPIO_AF11); + SYSCFG_PMC |= SYSCFG_PMC_MII_RMII_SEL; + delay_ms(1); + rcc_periph_reset_release(RST_ETHMAC); MAP_OUTPUT_PP (NRST); + MAP_OUTPUT_PP (RXD0 ); + MAP_OUTPUT_PP (RXD1 ); + MAP_OUTPUT_PP (CRS_DV ); + + SET(RXD0); + SET(RXD1); + SET(CRS_DV); CLEAR(NRST); delay_ms(1); SET (NRST); -TRACE; + MAP_AF_100 (REF_CLK, GPIO_AF11); + MAP_AF_100 (MDIO, GPIO_AF11); + MAP_AF_100 (CRS_DV, GPIO_AF11); - /* The switch to RMII has be done with steth under reset, with no clock */ + MAP_AF_100(RXER,GPIO_AF11); + MAP_AF_100(TXEN,GPIO_AF11); + MAP_AF_100(TXD0,GPIO_AF11); + MAP_AF_100(TXD1,GPIO_AF11); - rcc_periph_clock_enable (RCC_APB2ENR_SYSCFGEN); + MAP_AF_100 (MDC, GPIO_AF11); + MAP_AF_100 (RXD0, GPIO_AF11); + MAP_AF_100 (RXD1, GPIO_AF11); - RCC_AHB1RSTR |= RCC_AHB1RSTR_ETHMACRST; /*Assert RESET */ -#if 0 - rcc_periph_clock_disable (RCC_ETHMACPTP); - rcc_periph_clock_disable (RCC_ETHMACRX); - rcc_periph_clock_disable (RCC_ETHMACTX); - rcc_periph_clock_disable (RCC_ETHMAC); -#endif + /* The switch to RMII has be done with steth under reset, with no clock */ - delay_us (1); + rcc_periph_reset_hold(RST_ETHMAC); + delay_ms(1); #ifndef SYSCFG_PMC_MII_RMII_SEL #define SYSCFG_PMC_MII_RMII_SEL (1UL << 23) #endif SYSCFG_PMC |= SYSCFG_PMC_MII_RMII_SEL; + delay_ms(1); + rcc_periph_reset_release(RST_ETHMAC); -TRACE; - RCC_AHB1RSTR &= ~RCC_AHB1RSTR_ETHMACRST; /*De-sssert RESET */ - - - rcc_periph_clock_enable (RCC_ETHMAC); - rcc_periph_clock_enable (RCC_ETHMACTX); - rcc_periph_clock_enable (RCC_ETHMACRX); - rcc_periph_clock_enable (RCC_ETHMACPTP); - - delay_ms (10); ETH_DMABMR|=1; - delay_ms (10); - -TRACE; - eth_desc_init (eth_buf, TX_BUFS, RX_BUFS, FRAME_SZ, FRAME_SZ, 1); -TRACE; - for (i=0;i<32;++i) { - printf("phy:%x %x\r\n",i,eth_smi_read(PHY,i)); + TRACE; + while (ETH_DMABMR & 1) { + mac_stat(); + delay_ms(1000); } +TRACE; /*MDC = HCLK / 102 (0b100) => 1.6MHz */ - eth_init (PHY, 0x4); TRACE; -// eth_init (PHY, 0x14); -TRACE; - eth_enable_checksum_offload(); -TRACE; - - eth_set_mac (sa); + phy_stat(); +#if 0 +// eth_smi_write (PHY, PHY_REG_BCR, 0x2100); printf ("Waiting for link\r\n"); - while (!phy_link_isup (PHY)); - + while (!phy_link_isup (PHY)) { + phy_stat(); + delay_ms(1000); + } +#else + eth_smi_write (PHY, PHY_REG_ANTX, 0x1e1); phy_autoneg_enable (PHY); printf ("Waiting for autonegociation\r\n"); - while (!phy_link_an_done (PHY)); +i=0; + while (!phy_link_an_done (PHY)) { + phy_stat(); + delay_ms(1000); + + +#if 0 +if (i>4) { + phy_autoneg_enable (PHY); + i=0; +} +#endif +i++; + + } +#endif switch (phy_link_status (PHY)) { case LINK_HD_10M: @@ -353,6 +450,15 @@ TRACE; ; } +TRACE; + eth_set_mac (sa); +TRACE; + eth_enable_checksum_offload(); +TRACE; + eth_desc_init (eth_buf, TX_BUFS, RX_BUFS, FRAME_SZ, FRAME_SZ, 1); +TRACE; + + ETH_MACCR &= ~ETH_MACCR_RD; @@ -367,6 +473,7 @@ TRACE; running++; + nvic_enable_irq (NVIC_ETH_IRQ); printf ("Running\r\n"); @@ -376,57 +483,9 @@ TRACE; void steth_dispatch (void) { -#if 1 - uint32_t d, s; -#endif if (!running) return; -#if 1 - printf ("Net:\r\n"); - printf (" ETH_MACCR: %08" PRIx32 "\r\n", ETH_MACCR); -#if 0 - printf (" ETH_MACFFR: %08" PRIx32 "\r\n", ETH_MACFFR); - printf (" ETH_MACFCR: %08" PRIx32 "\r\n", ETH_MACFCR); - printf (" ETH_MACDBGR: %08" PRIx32 "\r\n", ETH_MACDBGR); - printf (" ETH_MACSR: %08" PRIx32 "\r\n", ETH_MACSR); -#endif - printf (" ETH_DMAOMR: %08" PRIx32 "\r\n", ETH_DMAOMR); - printf (" ETH_DMASR: %08" PRIx32 " ebs=%x tps=%x rps=%x\r\n", ETH_DMASR, - (ETH_DMASR >>23) & 7 , - (ETH_DMASR >>20) & 7 , - (ETH_DMASR >>17) & 7 ); - printf (" ETH_DMAIER: %08" PRIx32 "\r\n", ETH_DMAIER); - printf (" ETH_DMACHTDR: %08" PRIx32 "\r\n", ETH_DMACHTDR); - printf (" ETH_DMACHRDR: %08" PRIx32 "\r\n", ETH_DMACHRDR); - printf (" ETH_DMAOMR: %08" PRIx32 "\r\n", ETH_DMAOMR); - printf (" ETH_DMATDLAR: %08" PRIx32 "\r\n", ETH_DMATDLAR); - printf (" ETH_DMARDLAR: %08" PRIx32 "\r\n", ETH_DMARDLAR); - printf (" ETH_DMABMR: %08" PRIx32 "\r\n", ETH_DMABMR); - - - s = d = RxBD; - - - do { - printf (" %08" PRIx32 ": %08" PRIx32 " %08" PRIx32 " %08" PRIx32 " %08" - PRIx32 "\r\n", d, ETH_DES0 (d), ETH_DES1 (d), ETH_DES2 (d), - ETH_DES3 (d)); - - d = ETH_DES3 (d); - - } while (d != s); - -#endif - -{ -int i; -for (i=0;i<1000;++i) { -delay_ms(1); - steth_isr(); -} - -} } -- cgit v1.2.3