From 8c7ee88332652e7e79f6c1e4baacabe2183f7e8e Mon Sep 17 00:00:00 2001
From: root <root@ka-ata-killa.ourano.james.local>
Date: Tue, 2 Mar 2021 12:54:03 +0000
Subject: working, with hybrid FLL/PLL, new refclk input and support for
 max7219 displays, neo 5 and neo 7 and a bazillion other fixes

---
 app/clockv2.ld | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 app/clockv2.ld

(limited to 'app/clockv2.ld')

diff --git a/app/clockv2.ld b/app/clockv2.ld
new file mode 100644
index 0000000..325e7ce
--- /dev/null
+++ b/app/clockv2.ld
@@ -0,0 +1,20 @@
+/* Linker script for STM32F407VET6, 512K flash, 192K RAM. */
+
+/* Define memory regions. */
+MEMORY
+{
+  rom (rx) : ORIGIN = 0x08004000, LENGTH = 496K
+  ram (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
+}
+
+/* Include the common ld script. */
+INCLUDE libopencm3_stm32f4.ld
+
+dfu_shared_location = ORIGIN(ram) + LENGTH(ram) - 1024;
+
+SECTIONS
+{
+        .dfu_shared dfu_shared_location :{
+                dfu_flag = .;
+        }
+}
-- 
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