From 379b0ec3e5eacdde822966c84062bea41da7ae89 Mon Sep 17 00:00:00 2001
From: root <root@lab.panaceas.james.local>
Date: Tue, 19 Feb 2019 19:47:19 +0000
Subject: Working

---
 app/ATTIC/debug_eth.c | 105 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 105 insertions(+)
 create mode 100644 app/ATTIC/debug_eth.c

(limited to 'app/ATTIC/debug_eth.c')

diff --git a/app/ATTIC/debug_eth.c b/app/ATTIC/debug_eth.c
new file mode 100644
index 0000000..2742eeb
--- /dev/null
+++ b/app/ATTIC/debug_eth.c
@@ -0,0 +1,105 @@
+#include "project.h"
+
+/*---------------------------------------------------------------------------*/
+/** @brief Process pending SMI transaction and wait to be done.
+ */
+static void my_eth_smi_transact(void)
+{
+TRACE;
+	/* Begin transaction. */
+	ETH_MACMIIAR |= ETH_MACMIIAR_MB;
+TRACE;
+
+	/* Wait for not busy. */
+	while (ETH_MACMIIAR & ETH_MACMIIAR_MB);
+TRACE;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Write 16-bit register to the PHY
+ *
+ * @param[in] phy uint8_t ID of the PHY (defaults to 1)
+ * @param[in] reg uint8_t Register address
+ * @param[in] data uint16_t Data to write
+ */
+void my_eth_smi_write(uint8_t phy, uint8_t reg, uint16_t data)
+{
+	/* Write operation MW=1*/
+	ETH_MACMIIAR = (ETH_MACMIIAR & ETH_MACMIIAR_CR) | /* save clocks */
+			(phy << ETH_MACMIIAR_PA_SHIFT) |
+			(reg << ETH_MACMIIAR_MR_SHIFT) |
+			ETH_MACMIIAR_MW;
+
+	ETH_MACMIIDR = data & ETH_MACMIIDR_MD;
+TRACE;
+
+	my_eth_smi_transact();
+TRACE;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Read the 16-bit register from the PHY
+ *
+ * @param[in] phy uint8_t ID of the PHY (defaults to 1)
+ * @param[in] reg uint8_t Register address
+ * @returns uint16_t Readed data
+ */
+uint16_t my_eth_smi_read(uint8_t phy, uint8_t reg)
+{
+	/* Read operation MW=0*/
+	ETH_MACMIIAR = (ETH_MACMIIAR & ETH_MACMIIAR_CR) | /* save clocks */
+			(phy << ETH_MACMIIAR_PA_SHIFT) |
+			(reg << ETH_MACMIIAR_MR_SHIFT);
+
+TRACE;
+	my_eth_smi_transact();
+TRACE;
+
+	return (uint16_t)(ETH_MACMIIDR & ETH_MACMIIDR_MD);
+}
+
+
+void my_phy_reset(uint8_t phy)
+{
+unsigned i;
+TRACE;
+	my_eth_smi_write(phy, PHY_REG_BCR, PHY_REG_BCR_RESET);
+
+
+for (i=0;i<0x20;++i){
+printf("%x %x\n",i,my_eth_smi_read(phy,i));
+}
+
+	
+TRACE;
+
+	while (my_eth_smi_read(phy, PHY_REG_BCR) & PHY_REG_BCR_RESET);
+TRACE;
+
+delay_ms(100);
+}
+
+
+void my_eth_init(uint8_t phy, enum eth_clk clock)
+{
+	ETH_MACMIIAR = clock;
+TRACE;
+	my_phy_reset(phy);
+TRACE;
+
+	ETH_MACCR = ETH_MACCR_CSTF | ETH_MACCR_FES | ETH_MACCR_DM |
+		ETH_MACCR_APCS | ETH_MACCR_RD;
+	ETH_MACFFR = ETH_MACFFR_RA | ETH_MACFFR_PM;
+	ETH_MACHTHR = 0; /* pass all frames */
+	ETH_MACHTLR = 0;
+	ETH_MACFCR = (0x100 << ETH_MACFCR_PT_SHIFT);
+	ETH_MACVLANTR = 0;
+	ETH_DMAOMR = ETH_DMAOMR_DTCEFD | ETH_DMAOMR_RSF | ETH_DMAOMR_DFRF |
+		ETH_DMAOMR_TSF | ETH_DMAOMR_FEF | ETH_DMAOMR_OSF;
+	ETH_DMABMR = ETH_DMABMR_AAB | ETH_DMABMR_FB |
+		(32 << ETH_DMABMR_RDP_SHIFT) | (32 << ETH_DMABMR_PBL_SHIFT) |
+		ETH_DMABMR_PM_2_1 | ETH_DMABMR_USP;
+TRACE;
+}
+
+
-- 
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