From 0548136a4c886830414fb575d9d0daa7f1a7d170 Mon Sep 17 00:00:00 2001 From: fishsoupisgood Date: Wed, 8 May 2019 23:17:01 +0100 Subject: sysclk back to 168MHz, 10Mhz -> TIM2 --- app/Makefile | 2 +- app/abs.c | 62 +++++++++++++- app/dcf77.c | 2 +- app/events.h | 2 +- app/gps.c | 33 +++++--- app/gps_neo8.c | 8 +- app/main.c | 241 ++++++++++++++++++++++++++++++++++++++++++------------- app/max7219.c | 2 +- app/msf.c | 2 +- app/ntp.c | 4 +- app/project.h | 17 +++- app/prototypes.h | 4 + app/steth.c | 7 +- 13 files changed, 300 insertions(+), 86 deletions(-) diff --git a/app/Makefile b/app/Makefile index c0bbf4c..d4c56c5 100644 --- a/app/Makefile +++ b/app/Makefile @@ -25,7 +25,7 @@ PROG=msf V=1 default: ${PROG}.elf -CSRCS=led.c ticker.c ring.c usart.c stdio.c lwip_glue.c steth.c msf.c abs.c pll.c main.c time_fn.c ntp.c dcf77.c util.c stats.c gps.c hexdump.c bits.c max7219.c report.c +CSRCS=led.c ticker.c ring.c usart.c stdio.c lwip_glue.c steth.c msf.c abs.c pll.c main.c time_fn.c ntp.c dcf77.c util.c stats.c gps.c hexdump.c bits.c max7219.c report.c sysclk.c HSRCS= events.h gps.h project.h ring.h steth.h time_fn.h ubx.h diff --git a/app/abs.c b/app/abs.c index 2ed8dd4..7a6b5d5 100644 --- a/app/abs.c +++ b/app/abs.c @@ -3,11 +3,14 @@ static uint32_t high_tick; +#if HW_CLOCK_LEN == 32 + #define QUARTER (1UL << 29) #define HALF (1UL << 30) #define THREE_QUARTERS (HALF+QUARTER) #define ONE (~(uint32_t)0) + uint64_t abs_extend (uint32_t now) { static int m; @@ -25,9 +28,7 @@ uint64_t abs_extend (uint32_t now) m = 1; } - } else { - if (now < HALF) { ret = high_tick; ret <<= 32; @@ -44,6 +45,61 @@ uint64_t abs_extend (uint32_t now) return ret; } +#elif HW_CLOCK_LEN == 31 + +#define QUARTER (1UL << 28) +#define HALF (1UL << 29) +#define THREE_QUARTERS (HALF+QUARTER) +#define ONE (0x7fffffff) + + +uint64_t abs_extend (uint32_t now) +{ + static int m; + uint64_t ret; + + + if (!m) { + ret = high_tick; + ret <<= 31; + ret |= now; + + if ((now > THREE_QUARTERS) && (now <= ONE)) { + high_tick++; + m = 1; + } + + } else { + if (now < HALF) { + ret = high_tick; + ret <<= 31; + ret |= now; + } else { + ret = high_tick - 1; + ret <<= 31; + ret |= now; + } + + if ((now > QUARTER) && (now < HALF)) + m = 0; + } + + return ret; +} + + + + + +#else +#error unknown hardware clock length +#endif + + + + + + void abs_meh (void) @@ -57,7 +113,7 @@ void abs_meh (void) uint64_t abs_get (void) { - uint32_t now = SCS_DWT_CYCCNT; + uint32_t now = HW_CLOCK_REG; return abs_extend (now); } diff --git a/app/dcf77.c b/app/dcf77.c index e55fcfc..fc2dcda 100644 --- a/app/dcf77.c +++ b/app/dcf77.c @@ -33,7 +33,7 @@ static char dcf77_info[40]; void exti_t_isr (void) { - uint32_t now = SCS_DWT_CYCCNT; + uint32_t now = HW_CLOCK_REG; int v; v = !!gpio_get (T_PORT, T); diff --git a/app/events.h b/app/events.h index 8468851..550277d 100644 --- a/app/events.h +++ b/app/events.h @@ -3,7 +3,7 @@ typedef struct { uint32_t when; - int value; + uint32_t value; } Event; diff --git a/app/gps.c b/app/gps.c index 9d5a992..c3ac2d1 100644 --- a/app/gps.c +++ b/app/gps.c @@ -1,8 +1,11 @@ #include "project.h" -#define PPS (GPIO9) +#define PPS (GPIO7) #define PPS_PORT GPIOC +#define NRESET (GPIO8) +#define NRESET_PORT GPIOC + #define UBX_BUF_LEN 256 #define TIMEOUT 4000 @@ -23,27 +26,28 @@ uint64_t gps_last_happy; static char fix, fix2; static int32_t freq = 0; -static const int fish[] = { 1, 2, 3, 4, 5, 6, 7 }; +//static const int fish[] = { 1, 2, 3, 4, 5, 6, 7 }; static Event_ring gps_ring; static char gps_info[60]; - void exti9_5_isr (void) { - uint32_t now = SCS_DWT_CYCCNT; + uint32_t now = HW_CLOCK_REG; int v; v = !!gpio_get (PPS_PORT, PPS); nvic_disable_irq (NVIC_EXTI9_5_IRQ); - exti_reset_request (EXTI9); + exti_reset_request (EXTI7); gps_ring.events[gps_ring.tx_ptr].when = now; gps_ring.events[gps_ring.tx_ptr].value = v; gps_ring.tx_ptr = (gps_ring.tx_ptr + 1) & ERING_MASK; + if (v) sysclk_event(); + nvic_enable_irq (NVIC_EXTI9_5_IRQ); } @@ -270,7 +274,7 @@ ubx_recv_utc (uint8_t *ptr, unsigned len) next_sec = gps_time; - now = SCS_DWT_CYCCNT; + now = HW_CLOCK_REG; abs = abs_extend (now); gps_last_happy = make_happy (abs, 180); @@ -578,7 +582,7 @@ static void gps_pps_dispatch (void) uint32_t now; uint64_t abs; int v; - EPOCH e; + //EPOCH e; //UTC u; if (gps_ring.rx_ptr == gps_ring.tx_ptr) return; @@ -601,7 +605,7 @@ static void gps_pps_dispatch (void) if (gps_happy > 30) pll_dispatch (gps_last_happy, abs, "GPS"); - e = pll_decompose (abs); + //e = pll_decompose (abs); //u = time_epoch_to_utc (e); @@ -957,12 +961,17 @@ gps_init (void) // printf ("GPS ready\r\n"); // ubx_get_clock_stats(); + // + + + SET (NRESET); MAP_INPUT (PPS); + MAP_OUTPUT_PP (NRESET); - exti_select_source (EXTI9, PPS_PORT); - exti_set_trigger (EXTI9, EXTI_TRIGGER_BOTH); - exti_enable_request (EXTI9); + exti_select_source (EXTI7, PPS_PORT); + exti_set_trigger (EXTI7, EXTI_TRIGGER_BOTH); + exti_enable_request (EXTI7); nvic_enable_irq (NVIC_EXTI9_5_IRQ); return 0; @@ -1009,7 +1018,7 @@ void gps_dump_almanac (void) #if 1 int gps_bs (void) { - uint32_t now = SCS_DWT_CYCCNT; + uint32_t now = HW_CLOCK_REG; uint64_t abs = abs_extend (now); EPOCH e = pll_decompose (abs); UTC u = time_epoch_to_utc (e); diff --git a/app/gps_neo8.c b/app/gps_neo8.c index ea5d984..9da5438 100644 --- a/app/gps_neo8.c +++ b/app/gps_neo8.c @@ -29,7 +29,7 @@ static char gps_info[60]; void exti9_5_isr (void) { - uint32_t now = SCS_DWT_CYCCNT; + uint32_t now = HW_CLOCK_REG; int v; v = !!gpio_get (PPS_PORT, PPS); @@ -266,7 +266,7 @@ ubx_recv_utc (uint8_t *ptr, unsigned len) gps_time = time_utc_to_epoch (u); - now = SCS_DWT_CYCCNT; + now = HW_CLOCK_REG; abs = abs_extend (now); gps_last_happy = make_happy (abs, 180); @@ -1040,7 +1040,7 @@ void gps_dump_almanac(void) #if 0 int gps_bs(void) { - uint32_t now = SCS_DWT_CYCCNT; + uint32_t now = HW_CLOCK_REG; uint64_t abs = abs_extend (now); EPOCH e = pll_decompose (abs); UTC u = time_epoch_to_utc (e); @@ -1103,7 +1103,7 @@ int gps_bs(void) int gps_bs(void) { - uint32_t now = SCS_DWT_CYCCNT; + uint32_t now = HW_CLOCK_REG; uint64_t abs = abs_extend (now); EPOCH e = pll_decompose (abs); UTC u = time_epoch_to_utc (e); diff --git a/app/main.c b/app/main.c index 4793f78..e3e3f63 100644 --- a/app/main.c +++ b/app/main.c @@ -78,7 +78,7 @@ static void pd_set (uint32_t g, uint32_t b) } -static void pd(void) +static void pd (void) { pd_port (GPIOA); pd_port (GPIOB); @@ -138,6 +138,7 @@ static const clock_scale_t hse_10mhz_3v3_168 = { .apb2_frequency = 84000000, }; +#if 0 static const clock_scale_t hse_10mhz_3v3_120 = { /* 120 */ .pllm = 10, @@ -194,82 +195,200 @@ static const clock_scale_t hse_10mhz_3v3_10 = { .ppre1 = RCC_CFGR_PPRE_DIV_NONE, .ppre2 = RCC_CFGR_PPRE_DIV_NONE, .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_0WS, -// .ahb_frequency = 10000000, + // .ahb_frequency = 10000000, .apb1_frequency = 10000000, .apb2_frequency = 10000000, }; +#endif + /* - * Erugh the STM32F4's PLL is shite, we need - * to drive the entire clock tree from the 10MHz - * input, we use the PLL only to drive the 48MHz - * clock tree. + * Erugh the STM32F4's PLL is shite, we need + * to drive the entire clock tree from the 10MHz + * input, we use the PLL only to drive the 48MHz + * clock tree. * - * So PTP, AHB, APB1, APB2 all are directly from - * the HSE input + * So PTP, AHB, APB1, APB2 all are directly from + * the HSE input */ -void rcc_clock_setup_hse_3v3_no_pll(const clock_scale_t *clock) +void rcc_clock_setup_hse_3v3_no_pll (const clock_scale_t *clock) { - /* Enable internal high-speed oscillator. */ - rcc_osc_on(HSI); - rcc_wait_for_osc_ready(HSI); - - /* Select HSI as SYSCLK source. */ - rcc_set_sysclk_source(RCC_CFGR_SW_HSI); - - /* Enable external high-speed oscillator 8MHz. */ - rcc_osc_on(HSE); - rcc_wait_for_osc_ready(HSE); - - /* Enable/disable high performance mode */ - if (!clock->power_save) { - pwr_set_vos_scale(SCALE1); - } else { - pwr_set_vos_scale(SCALE2); - } - - /* - * Set prescalers for AHB, ADC, ABP1, ABP2. - * Do this before touching the PLL (TODO: why?). - */ - rcc_set_hpre(clock->hpre); - rcc_set_ppre1(clock->ppre1); - rcc_set_ppre2(clock->ppre2); - - rcc_set_main_pll_hse(clock->pllm, clock->plln, + /* Enable internal high-speed oscillator. */ + rcc_osc_on (HSI); + rcc_wait_for_osc_ready (HSI); + + /* Select HSI as SYSCLK source. */ + rcc_set_sysclk_source (RCC_CFGR_SW_HSI); + + /* receive the 10MHz external oscillator */ + rcc_osc_bypass_enable (HSE); + rcc_osc_on (HSE); + rcc_wait_for_osc_ready (HSE); + + /* Enable/disable high performance mode */ + if (!clock->power_save) + pwr_set_vos_scale (SCALE1); + else + pwr_set_vos_scale (SCALE2); + + /* + * Set prescalers for AHB, ADC, ABP1, ABP2. + * Do this before touching the PLL (TODO: why?). + */ + rcc_set_hpre (clock->hpre); + rcc_set_ppre1 (clock->ppre1); + rcc_set_ppre2 (clock->ppre2); + + rcc_set_main_pll_hse (clock->pllm, clock->plln, clock->pllp, clock->pllq); - /* Enable PLL oscillator and wait for it to stabilize. */ - rcc_osc_on(PLL); - rcc_wait_for_osc_ready(PLL); + /* Enable PLL oscillator and wait for it to stabilize. */ + rcc_osc_on (PLL); + rcc_wait_for_osc_ready (PLL); - /* Configure flash settings. */ - flash_set_ws(clock->flash_config); + /* Configure flash settings. */ + flash_set_ws (clock->flash_config); - /* Select PLL as SYSCLK source. */ - rcc_set_sysclk_source(RCC_CFGR_SW_HSE); + /* Select HSE as SYSCLK source. */ + rcc_set_sysclk_source (RCC_CFGR_SW_HSE); - /* Wait for PLL clock to be selected. */ - rcc_wait_for_sysclk_status(HSE); + /* Wait for HSE clock to be selected. */ + rcc_wait_for_sysclk_status (HSE); - /* Set the peripheral clock frequencies used. */ - rcc_apb1_frequency = clock->apb1_frequency; - rcc_apb2_frequency = clock->apb2_frequency; + /* Set the peripheral clock frequencies used. */ + rcc_apb1_frequency = clock->apb1_frequency; + rcc_apb2_frequency = clock->apb2_frequency; - /* Disable internal high-speed oscillator. */ - rcc_osc_off(HSI); + /* Disable internal high-speed oscillator. */ + rcc_osc_off (HSI); } +static void ptp_clock_start (void) +{ + /* Get the PTP clock running early */ + ETH_PTPTSCR |= ETH_PTPTSCR_TSE; + ETH_PTPSSIR = 1; -static void -board_setup (void) + ETH_PTPTSCR &= ~ETH_PTPTSCR_TSFCU; + ETH_PTPTSCR &= ~ETH_PTPTSCR_TSSSR; + + ETH_PTPTSHUR = 0; + ETH_PTPTSLUR = 0; + + ETH_PTPTSCR |= ETH_PTPTSCR_TSSTI; +} + + +static void clock_setup (void) { + /* + * Caution, The PLL is somewhat rubbish, and causes all sorts of misery + * so sysclk isn't really a reference, if we use it, however not using it + * means sysclk is 10MHz which is too slow to do ntp and ptp, instead + * we route HSE out through MCO1 (as it's not necessarily LVTTL at the + * input) and connect that to TIM1_ETR + * + */ + + /* confiure HSE as input not oscillator */ rcc_osc_bypass_enable (HSE); + + /* turn off SSC */ RCC_SSCGR = 0; -// rcc_clock_setup_hse_3v3 (&hse_10mhz_3v3_168); - rcc_clock_setup_hse_3v3_no_pll (&hse_10mhz_3v3_10); + + /* Route HSE out through MCO1 (PA8) which we connect to TIM1_ETR (PE7)*/ + + RCC_CFGR &= ~ (RCC_CFGR_MCO1_PLL << RCC_CFGR_MCO1_SHIFT); + RCC_CFGR |= RCC_CFGR_MCO1_HSE << RCC_CFGR_MCO1_SHIFT; + + RCC_CFGR &= ~ (RCC_CFGR_MCOPRE_DIV_5 << RCC_CFGR_MCO1PRE_SHIFT); + RCC_CFGR |= RCC_CFGR_MCOPRE_DIV_NONE << RCC_CFGR_MCO1PRE_SHIFT; + + rcc_clock_setup_hse_3v3 (&hse_10mhz_3v3_168); + /* rcc_clock_setup_hse_3v3_no_pll (&hse_10mhz_3v3_10); */ + + +} +#define REFCLK_OUT (GPIO8) +#define REFCLK_OUT_PORT GPIOA + +#define REFCLK_IN (GPIO7) +#define REFCLK_IN_PORT GPIOE + +static void timer_setup (void) +{ + MAP_INPUT (REFCLK_OUT); + MAP_INPUT (REFCLK_IN); + MAP_AF (REFCLK_OUT, GPIO_AF0); + MAP_AF (REFCLK_IN, GPIO_AF1); + + +#if 0 + /* Divide by 2 to trigger TIM2 */ + timer_reset (TIM1); + timer_set_mode (TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); + timer_set_master_mode (TIM1, TIM_CR2_MMS_UPDATE); + timer_set_period (TIM1, 1); + timer_slave_set_filter (TIM1, TIM_SMCR_ETF_OFF); + timer_slave_set_prescaler (TIM1, TIM_SMCR_ETPS_OFF); + TIM1_SMCR |= TIM_SMCR_ECE; + timer_enable_counter (TIM1); + + timer_reset (TIM2); + timer_set_mode (TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); + timer_slave_set_filter (TIM2, TIM_SMCR_ETF_OFF); /*no filter*/ + timer_slave_set_prescaler (TIM2, TIM_SMCR_ETPS_OFF); /*no prescaler */ + timer_slave_set_polarity (TIM2, TIM_ET_RISING); /*rising edge */ + timer_slave_set_mode (TIM2, TIM_SMCR_SMS_ECM1); /*external clock mode 1*/ + timer_slave_set_trigger (TIM2, TIM_SMCR_TS_ITR0); /*clock from timer 1*/ + timer_enable_counter (TIM2); +#endif + + + + /* + * so TIM1 which I wired the 10MHz in to turns out to be only 16 bit + * so it's a chocolate teapot for this application + * + * after much faffing what works is the following, configure + * the TIM1_ETR to synchronously reset TIM1 + * connect the TIM1_RESET line to the TIM1_TRGO line + * use TIM1_TRGO as TIM2_TRGI, and set TIM2 to upcount + * on each rising edge of TRGI + * + * there's a promising tim2 ETRF input on one of the unused jtag pins + * but that requires going up a ladder... + * + */ + + + timer_reset (TIM1); + timer_set_mode (TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); /* meh */ + timer_slave_set_filter (TIM1, TIM_SMCR_ETF_OFF); /* No filter */ + timer_slave_set_prescaler (TIM1, TIM_SMCR_ETPS_OFF); /* no prescaler */ + timer_slave_set_trigger (TIM1, TIM_SMCR_TS_ETRF); /* Trigger from ETR input */ + timer_slave_set_mode (TIM1, TIM_SMCR_SMS_RM); /* trigger resets timer */ + timer_set_master_mode (TIM1, TIM_CR2_MMS_RESET); /* output reset on TRGO */ + timer_enable_counter (TIM1); /* go */ + + timer_reset (TIM2); + timer_set_mode (TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); /* count up with clock*/ + timer_slave_set_filter (TIM2, TIM_SMCR_ETF_OFF); /*no filter*/ + timer_slave_set_prescaler (TIM2, TIM_SMCR_ETPS_OFF); /*no prescaler */ + timer_slave_set_polarity (TIM2, TIM_ET_RISING); /*rising edge */ + timer_slave_set_mode (TIM2, TIM_SMCR_SMS_ECM1); /*external clock mode 1*/ + timer_slave_set_trigger (TIM2, TIM_SMCR_TS_ITR0); /*clock from timer 1*/ + timer_enable_counter (TIM2); + + +} + +static void +board_setup (void) +{ + clock_setup(); rcc_periph_clock_enable (RCC_SYSCFG); rcc_periph_clock_enable (RCC_GPIOA); @@ -285,6 +404,8 @@ board_setup (void) rcc_periph_clock_enable (RCC_ETHMACTX); rcc_periph_clock_enable (RCC_ETHMACRX); rcc_periph_clock_enable (RCC_ETHMACPTP); + rcc_periph_clock_enable (RCC_TIM1); + rcc_periph_clock_enable (RCC_TIM2); nvic_set_priority (NVIC_EXTI9_5_IRQ, 0x00); nvic_set_priority (NVIC_EXTI3_IRQ, 0x10); @@ -294,6 +415,7 @@ board_setup (void) nvic_set_priority (NVIC_ETH_IRQ, 0x40); nvic_set_priority (NVIC_SYSTICK_IRQ, 0x50); + // nvic_enable_irq (NVIC_EXTI15_10_IRQ); } @@ -303,6 +425,9 @@ system_init (void) { board_setup(); + + timer_setup(); + led_init(); ticker_init(); @@ -316,6 +441,8 @@ system_init (void) printf ("STETH\r\n"); steth_init(); + ptp_clock_start(); + max7219_init (1); gps_init(); @@ -335,7 +462,7 @@ main (void) #if 0 while (1) { - uint32_t now = SCS_DWT_CYCCNT; + uint32_t now = HW_CLOCK_REG; uint64_t abs = abs_extend (now); EPOCH e = pll_decompose (abs); time_print_epoch ("TEST: ", e); @@ -349,7 +476,7 @@ main (void) while (1) { #if 0 { - uint32_t now = SCS_DWT_CYCCNT; + uint32_t now = HW_CLOCK_REG; uint64_t abs = abs_extend (now); EPOCH e = pll_decompose (abs); time_print_epoch ("TEST: ", e); @@ -362,8 +489,8 @@ main (void) msf_dispatch(); dcf77_dispatch(); - gps_dispatch(); + sysclk_dispatch(); cmd_dispatch(); dispatch_lwip(); diff --git a/app/max7219.c b/app/max7219.c index fbba10d..bebfa50 100644 --- a/app/max7219.c +++ b/app/max7219.c @@ -103,7 +103,7 @@ void max7219_write (int d, int h, int m, int s) void max7219_dispatch (void) { - uint32_t now = SCS_DWT_CYCCNT; + uint32_t now = HW_CLOCK_REG; uint64_t abs = abs_extend (now); EPOCH e = pll_decompose (abs); UTC u = time_epoch_to_utc (e); diff --git a/app/msf.c b/app/msf.c index 954e57f..9d8db3f 100644 --- a/app/msf.c +++ b/app/msf.c @@ -32,7 +32,7 @@ static EPOCH msf_time; void exti_t_isr (void) { - uint32_t now = SCS_DWT_CYCCNT; + uint32_t now = HW_CLOCK_REG; int v; v = !!gpio_get (T_PORT, T); diff --git a/app/ntp.c b/app/ntp.c index f8ca357..0bdda4d 100644 --- a/app/ntp.c +++ b/app/ntp.c @@ -69,7 +69,7 @@ static uint64_t ntp_ts (uint64_t v) static void ntp_rx (void *arg, struct udp_pcb *s, struct pbuf *p, struct ip_addr *src_addr, u16_t port) { - uint32_t now = SCS_DWT_CYCCNT; + uint32_t now = HW_CLOCK_REG; struct ip_addr dst_addr = *src_addr; ntp_packet_t pkt; @@ -102,7 +102,7 @@ static void ntp_rx (void *arg, struct udp_pcb *s, struct pbuf *p, struct ip_addr pkt.receive_ts = ntp_ts (abs_extend (now)); pkt.reference_ts = ntp_ts (pll_last_update); - now = SCS_DWT_CYCCNT; + now = HW_CLOCK_REG; pkt.transmit_ts = ntp_ts (abs_extend (now)); memcpy (p->payload, &pkt, sizeof (ntp_packet_t)); diff --git a/app/project.h b/app/project.h index 47eecb3..d060a81 100644 --- a/app/project.h +++ b/app/project.h @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -45,12 +46,26 @@ #include "prototypes.h" -#define HZ 10000000 +//#define HZ 10000000 +#define HZ 10000000 + //#define HZ 167999973 //#define HZ 168000000 //#define HZ 167968615 //#define HZ 165925490 //#define HZ 167996682 +// + +#if 0 +#define HW_CLOCK_REG SCS_DWT_CYCCNT +#define HW_CLOCK_LEN 32 +#elif 0 +#define HW_CLOCK_REG ETH_PTPTSLR +#define HW_CLOCK_LEN 31 +#else +#define HW_CLOCK_REG TIM2_CNT +#define HW_CLOCK_LEN 32 +#endif #define TRACE do { stdio_drain(); printf("%s:%d\r\n",__FUNCTION__,__LINE__); } while (0) diff --git a/app/prototypes.h b/app/prototypes.h index 667262b..8779f8d 100644 --- a/app/prototypes.h +++ b/app/prototypes.h @@ -117,3 +117,7 @@ extern void max7219_dispatch(void); extern void max7219_init(int on); /* report.c */ extern void report_time(const char *src, EPOCH e, uint64_t abs, const char *info); +/* sysclk.c */ +extern void sysclk_event(void); +extern uint64_t sysclk_extend(uint32_t now); +extern void sysclk_dispatch(void); diff --git a/app/steth.c b/app/steth.c index 7b23b3c..26429aa 100644 --- a/app/steth.c +++ b/app/steth.c @@ -215,6 +215,7 @@ static void my_eth_init (uint8_t phy, enum eth_clk clock) +#if 0 static void phy_set_ignore_address (void) { unsigned i; @@ -241,7 +242,7 @@ static void phy_set_ignore_address (void) eth_smi_write (PHY1, 0x11, 0x8); } - +#endif static void eth_reset (void) { @@ -423,7 +424,8 @@ void steth_slow_tick (void) if ((!phy_link_isup (PHY) || !an_happy) && running) { printf ("stopping nic\r\n"); - eth_reset(); + //eth_reset(); + ETH_MACCR |= ETH_MACCR_RD; running = 0; @@ -453,6 +455,7 @@ void steth_slow_tick (void) switch (phy_link_status (PHY)) { case LINK_HD_10M: TRACE; + break; case LINK_HD_100M: TRACE; -- cgit v1.2.3