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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#define STRINGIZE(s) #s
#define LAN_LABEL(p, s) STRINGIZE(p ## s)
#define SWITCH_PORT_LABEL(n) LAN_LABEL(lan, n)
#define INTERNAL_PHY(n) \
phy##n: ethernet-phy@##n { \
reg = <##n>; \
compatible = "ethernet-phy-ieee802.3-c22"; \
phy-is-integrated; \
};
#define EXTERNAL_PHY(n) \
phy##n: ethernet-phy@##n { \
reg = <##n>; \
compatible = "ethernet-phy-ieee802.3-c22"; \
};
#define EXTERNAL_SFP_PHY(n) \
phy##n: ethernet-phy@##n { \
compatible = "ethernet-phy-ieee802.3-c22"; \
sfp; \
media = "fibre"; \
reg = <##n>; \
};
#define SWITCH_PORT(n, s, m) \
port@##n { \
reg = <##n>; \
label = SWITCH_PORT_LABEL(s) ; \
phy-handle = <&phy##n>; \
phy-mode = #m ; \
};
#define SWITCH_SFP_PORT(n, s, m) \
port@##n { \
reg = <##n>; \
label = SWITCH_PORT_LABEL(s) ; \
phy-handle = <&phy##n>; \
phy-mode = #m ; \
fixed-link { \
speed = <1000>; \
full-duplex; \
}; \
};
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "realtek,rtl838x-soc";
cpus {
#address-cells = <1>;
#size-cells = <0>;
frequency = <800000000>;
cpu@0 {
compatible = "mips,mips34Kc";
reg = <0>;
};
};
memory@0 {
device_type = "memory";
reg = <0x0 0x8000000>;
};
chosen {
bootargs = "console=ttyS0,38400";
};
cpuintc: cpuintc {
compatible = "mti,cpu-interrupt-controller";
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
intc: rtlintc {
compatible = "realtek,rt9300-intc";
reg = <0xb8003000 0x20>;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
osc: oscillator {
compatible = "fixed-clock";
#clock-cells = <1>;
clock-frequency = <175000000>;
clock-output-names = "osc";
};
timer: timer@b8003200 {
compatible = "realtek,rtl9300-timer";
reg = <0xb8003200 0x60>;
interrupt-parent = <&intc>;
interrupts = <8>;
interrupt-names = "ostimer";
clocks = <&osc 0>;
};
spi0: spi@b8001200 {
compatible = "realtek,rtl838x-nor";
reg = <0xb8001200 0x100>;
#address-cells = <1>;
#size-cells = <0>;
};
uart0: uart@b8002000 {
compatible = "ns16550a";
reg = <0xb8002000 0x100>;
clock-frequency = <175000000>;
interrupt-parent = <&intc>;
interrupts = <30>;
reg-io-width = <1>;
reg-shift = <2>;
fifo-size = <1>;
no-loopback-test;
};
uart1: uart@b8002100 {
compatible = "ns16550a";
reg = <0xb8002100 0x100>;
clock-frequency = <175000000>;
interrupt-parent = <&intc>;
interrupts = <31>;
reg-io-width = <1>;
reg-shift = <2>;
fifo-size = <1>;
no-loopback-test;
};
gpio0: gpio-controller@b8003500 {
compatible = "realtek,rtl838x-gpio";
reg = <0xb8003500 0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <31>;
};
ethernet0: ethernet@bb00a300 {
compatible = "realtek,rtl838x-eth";
reg = <0xbb00a300 0x100>;
interrupt-parent = <&intc>;
interrupts = <24>;
#interrupt-cells = <1>;
phy-mode = "internal";
fixed-link {
speed = <1000>;
full-duplex;
};
};
switch0: switch@bb000000 {
compatible = "realtek,rtl83xx-switch";
interrupt-parent = <&intc>;
interrupts = <20>;
};
};
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