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--- a/arch/mips/ralink/common/intc.c
+++ b/arch/mips/ralink/common/intc.c
@@ -44,23 +44,25 @@ static inline u32 ramips_intc_rr(unsigne
return __raw_readl(ramips_intc_base + reg);
}
-static void ramips_intc_irq_unmask(unsigned int irq)
+static void ramips_intc_irq_unmask(struct irq_data *d)
{
- irq -= ramips_intc_irq_base;
+ unsigned int irq = d->irq - ramips_intc_irq_base;
+
ramips_intc_wr((1 << irq), INTC_REG_ENABLE);
}
-static void ramips_intc_irq_mask(unsigned int irq)
+static void ramips_intc_irq_mask(struct irq_data *d)
{
- irq -= ramips_intc_irq_base;
+ unsigned int irq = d->irq - ramips_intc_irq_base;
+
ramips_intc_wr((1 << irq), INTC_REG_DISABLE);
}
static struct irq_chip ramips_intc_irq_chip = {
.name = "INTC",
- .unmask = ramips_intc_irq_unmask,
- .mask = ramips_intc_irq_mask,
- .mask_ack = ramips_intc_irq_mask,
+ .irq_unmask = ramips_intc_irq_unmask,
+ .irq_mask = ramips_intc_irq_mask,
+ .irq_mask_ack = ramips_intc_irq_mask,
};
static struct irqaction ramips_intc_irqaction = {
@@ -83,10 +85,9 @@ void __init ramips_intc_irq_init(unsigne
ramips_intc_wr(0, INTC_REG_TYPE);
for (i = ramips_intc_irq_base;
- i < ramips_intc_irq_base + INTC_IRQ_COUNT; i++) {
- set_irq_chip_and_handler(i, &ramips_intc_irq_chip,
+ i < ramips_intc_irq_base + INTC_IRQ_COUNT; i++)
+ irq_set_chip_and_handler(i, &ramips_intc_irq_chip,
handle_level_irq);
- }
setup_irq(irq, &ramips_intc_irqaction);
ramips_intc_wr(INTC_INT_GLOBAL, INTC_REG_ENABLE);
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