/* * Driver for Zarlink DVB-T MT352 demodulator * * Written by Holger Waechtler * and Daniel Mack * * AVerMedia AVerTV DVB-T 771 support by * Wolfram Joost * * Support for Samsung TDTC9251DH01C(M) tuner * Copyright (C) 2004 Antonio Mancuso * Amauri Celani * * DVICO FusionHDTV DVB-T1 and DVICO FusionHDTV DVB-T Lite support by * Christopher Pascoe * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.= */ #include #include #include #include #include #include #include "dvb_frontend.h" #include "mt352_priv.h" #include "mt352.h" struct mt352_state { struct i2c_adapter* i2c; struct dvb_frontend frontend; /* configuration settings */ struct mt352_config config; }; static int debug; #define dprintk(args...) \ do { \ if (debug) printk(KERN_DEBUG "mt352: " args); \ } while (0) static int mt352_single_write(struct dvb_frontend *fe, u8 reg, u8 val) { struct mt352_state* state = fe->demodulator_priv; u8 buf[2] = { reg, val }; struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0, .buf = buf, .len = 2 }; int err = i2c_transfer(state->i2c, &msg, 1); if (err != 1) { printk("mt352_write() to reg %x failed (err = %d)!\n", reg, err); return err; } return 0; } static int _mt352_write(struct dvb_frontend* fe, const u8 ibuf[], int ilen) { int err,i; for (i=0; i < ilen-1; i++) if ((err = mt352_single_write(fe,ibuf[0]+i,ibuf[i+1]))) return err; return 0; } static int mt352_read_register(struct mt352_state* state, u8 reg) { int ret; u8 b0 [] = { reg }; u8 b1 [] = { 0 }; struct i2c_msg msg [] = { { .addr = state->config.demod_address, .flags = 0, .buf = b0, .len = 1 }, { .addr = state->config.demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } }; ret = i2c_transfer(state->i2c, msg, 2); if (ret != 2) { printk("%s: readreg error (reg=%d, ret==%i)\n", __func__, reg, ret); return ret; } return b1[0]; } static int mt352_sleep(struct dvb_frontend* fe) { static u8 mt352_softdown[] = { CLOCK_CTL, 0x20, 0x08 }; _mt352_write(fe, mt352_softdown, sizeof(mt352_softdown)); return 0; } static void mt352_calc_nominal_rate(struct mt352_state* state, enum fe_bandwidth bandwidth, unsigned char *buf) { u32 adc_clock = 20480; /* 20.340 MHz */ u32 bw,value; switch (bandwidth) { case BANDWIDTH_6_MHZ: bw = 6; break; case BANDWIDTH_7_MHZ: bw = 7; break; case BANDWIDTH_8_MHZ: default: bw = 8; break; } if (state->config.adc_clock) adc_clock = state->config.adc_clock; value = 64 * bw * (1<<16) / (7 * 8); value = value * 1000 / adc_clock; dprintk("%s: bw %d, adc_clock %d => 0x%x\n", __func__, bw, adc_clock, value); buf[0] = msb(value); buf[1] = lsb(value); } static void mt352_calc_input_freq(struct mt352_state* state, unsigned char *buf) { int adc_clock = 20480; /* 20.480000 MHz */ int if2 = 36167; /* 36.166667 MHz */ int ife,value; if (state->config.adc_clock) adc_clock = state->config.adc_clock; if (state->config.if2) if2 = state->config.if2; if (adc_clock >= if2 * 2) ife = if2; else { ife = adc_clock - (if2 % adc_clock); if (ife > adc_clock / 2) ife = adc_clock - ife; } value = -16374 * ife / adc_clock; dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n", __func__, if2, ife, adc_clock, value, value & 0x3fff); buf[0] = msb(value); buf[1] = lsb(value); } static int mt352_set_parameters(struct dvb_frontend* fe, struct dvb_frontend_parameters *param) { struct mt352_state* state = fe->demodulator_priv; unsigned char buf[13]; static unsigned char tuner_go[] = { 0x5d, 0x01 }; static unsigned char fsm_go[] = { 0x5e, 0x01 }; unsigned int tps = 0; struct dvb_ofdm_parameters *op = ¶m->u.ofdm; switch (op->code_rate_HP) { case FEC_2_3: tps |= (1 << 7); break; case FEC_3_4: tps |= (2 << 7); break; case FEC_5_6: tps |= (3 << 7); break; case FEC_7_8: tps |= (4 << 7); break; case FEC_1_2: case FEC_AUTO: break; default: return -EINVAL; } switch (op->code_rate_LP) { case FEC_2_3: tps |= (1 << 4); break; case FEC_3_4: tps |= (2 << 4); break; case FEC_5_6: tps |= (3 << 4); break; case FEC_7_8: tps |= (4 << 4); break; case FEC_1_2: case FEC_AUTO: br
/*
 * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards
 *
 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
 *
 * The cache manipulation routine has been taken from the U-Boot project.
 *	(C) Copyright 2003
 *	Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 *
 */

#include "cache.h"
#include "cacheops.h"
#include "config.h"

#define cache_op(op,addr)						\
	__asm__ __volatile__(						\
	"	.set	push					\n"	\
	"	.set	noreorder				\n"	\
	"	.set	mips3\n\t				\n"	\
	"	cache	%0, %1					\n"	\
	"	.set	pop					\n"	\
	:								\
	: "i" (op), "R" (*(unsigned char *)(addr)))

void flush_cache(unsigned long start_addr, unsigned long size)
{
	unsigned long lsize = CONFIG_CACHELINE_SIZE;
	unsigned long addr = start_addr & ~(lsize - 1);
	unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);

	while (1) {
		cache_op(Hit_Writeback_Inv_D, addr);
		cache_op(Hit_Invalidate_I, addr);
		if (addr == aend)
			break;
		addr += lsize;
	}
}