1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
|
From 1d5819e90f2ef6dead11809744372a9863227a92 Mon Sep 17 00:00:00 2001
From: Zhanyong Wang <zhanyong.wang@mediatek.com>
Date: Tue, 25 Jan 2022 19:03:34 +0800
Subject: [PATCH 5/5] phy: phy-mtk-tphy: add auto-load-valid check mechanism
support
add auto-load-valid check mechanism support
Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
---
drivers/phy/mediatek/phy-mtk-tphy.c | 67 +++++++++++++++++++++++++++--
1 file changed, 64 insertions(+), 3 deletions(-)
--- a/drivers/phy/mediatek/phy-mtk-tphy.c
+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
@@ -376,9 +376,13 @@ struct mtk_phy_instance {
u32 type_sw_reg;
u32 type_sw_index;
u32 efuse_sw_en;
+ bool efuse_alv_en;
+ u32 efuse_autoloadvalid;
u32 efuse_intr;
u32 efuse_tx_imp;
u32 efuse_rx_imp;
+ bool efuse_alv_ln1_en;
+ u32 efuse_ln1_autoloadvalid;
u32 efuse_intr_ln1;
u32 efuse_tx_imp_ln1;
u32 efuse_rx_imp_ln1;
@@ -1125,6 +1129,7 @@ static int phy_efuse_get(struct mtk_tphy
{
struct device *dev = &instance->phy->dev;
int ret = 0;
+ bool alv = false;
/* tphy v1 doesn't support sw efuse, skip it */
if (!tphy->pdata->sw_efuse_supported) {
@@ -1139,6 +1144,20 @@ static int phy_efuse_get(struct mtk_tphy
switch (instance->type) {
case PHY_TYPE_USB2:
+ alv = of_property_read_bool(dev->of_node, "auto_load_valid");
+ if (alv) {
+ instance->efuse_alv_en = alv;
+ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid",
+ &instance->efuse_autoloadvalid);
+ if (ret) {
+ dev_err(dev, "fail to get u2 alv efuse, %d\n", ret);
+ break;
+ }
+ dev_info(dev,
+ "u2 auto load valid efuse: ENABLE with value: %u\n",
+ instance->efuse_autoloadvalid);
+ }
+
ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
if (ret) {
dev_err(dev, "fail to get u2 intr efuse, %d\n", ret);
@@ -1157,6 +1176,20 @@ static int phy_efuse_get(struct mtk_tphy
case PHY_TYPE_USB3:
case PHY_TYPE_PCIE:
+ alv = of_property_read_bool(dev->of_node, "auto_load_valid");
+ if (alv) {
+ instance->efuse_alv_en = alv;
+ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid",
+ &instance->efuse_autoloadvalid);
+ if (ret) {
+ dev_err(dev, "fail to get u3(pcei) alv efuse, %d\n", ret);
+ break;
+ }
+ dev_info(dev,
+ "u3 auto load valid efuse: ENABLE with value: %u\n",
+ instance->efuse_autoloadvalid);
+ }
+
ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
if (ret) {
dev_err(dev, "fail to get u3 intr efuse, %d\n", ret);
@@ -1190,6 +1223,20 @@ static int phy_efuse_get(struct mtk_tphy
if (tphy->pdata->version != MTK_PHY_V4)
break;
+ alv = of_property_read_bool(dev->of_node, "auto_load_valid_ln1");
+ if (alv) {
+ instance->efuse_alv_ln1_en = alv;
+ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid_ln1",
+ &instance->efuse_ln1_autoloadvalid);
+ if (ret) {
+ dev_err(dev, "fail to get pcie auto_load_valid efuse, %d\n", ret);
+ break;
+ }
+ dev_info(dev,
+ "pcie auto load valid efuse: ENABLE with value: %u\n",
+ instance->efuse_ln1_autoloadvalid);
+ }
+
ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1);
if (ret) {
dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret);
@@ -1241,6 +1288,10 @@ static void phy_efuse_set(struct mtk_phy
switch (instance->type) {
case PHY_TYPE_USB2:
+ if (instance->efuse_alv_en &&
+ instance->efuse_autoloadvalid == 1)
+ break;
+
tmp = readl(u2_banks->misc + U3P_MISC_REG1);
tmp |= MR1_EFUSE_AUTO_LOAD_DIS;
writel(tmp, u2_banks->misc + U3P_MISC_REG1);
@@ -1251,6 +1302,10 @@ static void phy_efuse_set(struct mtk_phy
writel(tmp, u2_banks->com + U3P_USBPHYACR1);
break;
case PHY_TYPE_USB3:
+ if (instance->efuse_alv_en &&
+ instance->efuse_autoloadvalid == 1)
+ break;
+
tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
@@ -1277,6 +1332,10 @@ static void phy_efuse_set(struct mtk_phy
break;
case PHY_TYPE_PCIE:
+ if (instance->efuse_alv_en &&
+ instance->efuse_autoloadvalid == 1)
+ break;
+
tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
@@ -1297,9 +1356,12 @@ static void phy_efuse_set(struct mtk_phy
tmp &= ~P3A_RG_IEXT_INTR;
tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr);
writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
- if (!instance->efuse_intr_ln1 &&
- !instance->efuse_rx_imp_ln1 &&
- !instance->efuse_tx_imp_ln1)
+
+ if ((!instance->efuse_intr_ln1 &&
+ !instance->efuse_rx_imp_ln1 &&
+ !instance->efuse_tx_imp_ln1) ||
+ (instance->efuse_alv_ln1_en &&
+ instance->efuse_ln1_autoloadvalid == 1))
break;
tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV);
|
