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--- a/drivers/iio/adc/mt6577_auxadc.c
+++ b/drivers/iio/adc/mt6577_auxadc.c
@@ -42,6 +42,7 @@ struct mtk_auxadc_compatible {
struct mt6577_auxadc_device {
void __iomem *reg_base;
struct clk *adc_clk;
+ struct clk *adc_32k_clk;
struct mutex lock;
const struct mtk_auxadc_compatible *dev_comp;
};
@@ -222,6 +223,14 @@ static int __maybe_unused mt6577_auxadc_
return ret;
}
+ if (!IS_ERR(adc_dev->adc_32k_clk)) {
+ ret = clk_prepare_enable(adc_dev->adc_32k_clk);
+ if (ret) {
+ pr_err("failed to enable auxadc clock\n");
+ return ret;
+ }
+ }
+
mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
MT6577_AUXADC_PDN_EN, 0);
mdelay(MT6577_AUXADC_POWER_READY_MS);
@@ -236,6 +243,8 @@ static int __maybe_unused mt6577_auxadc_
mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
0, MT6577_AUXADC_PDN_EN);
+
+ clk_disable_unprepare(adc_dev->adc_32k_clk);
clk_disable_unprepare(adc_dev->adc_clk);
return 0;
@@ -277,6 +286,17 @@ static int mt6577_auxadc_probe(struct pl
return ret;
}
+ adc_dev->adc_32k_clk = devm_clk_get(&pdev->dev, "32k");
+ if (IS_ERR(adc_dev->adc_32k_clk)) {
+ dev_err(&pdev->dev, "failed to get auxadc 32k clock\n");
+ } else {
+ ret = clk_prepare_enable(adc_dev->adc_32k_clk);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to enable auxadc 32k clock\n");
+ return ret;
+ }
+ }
+
adc_clk_rate = clk_get_rate(adc_dev->adc_clk);
if (!adc_clk_rate) {
ret = -EINVAL;
@@ -306,6 +326,7 @@ err_power_off:
mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
0, MT6577_AUXADC_PDN_EN);
err_disable_clk:
+ clk_disable_unprepare(adc_dev->adc_32k_clk);
clk_disable_unprepare(adc_dev->adc_clk);
return ret;
}
@@ -320,6 +341,7 @@ static int mt6577_auxadc_remove(struct p
mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
0, MT6577_AUXADC_PDN_EN);
+ clk_disable_unprepare(adc_dev->adc_32k_clk);
clk_disable_unprepare(adc_dev->adc_clk);
return 0;
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