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From patchwork Wed Mar 29 09:38:21 2017
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [net-next, v3,
3/5] net-next: ethernet: mediatek: add CDM able to recognize the tag
for DSA
From: sean.wang@mediatek.com
X-Patchwork-Id: 9651091
Message-Id: <1490780303-18598-4-git-send-email-sean.wang@mediatek.com>
To: <andrew@lunn.ch>, <f.fainelli@gmail.com>,
<vivien.didelot@savoirfairelinux.com>, <matthias.bgg@gmail.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org, Landen.Chao@mediatek.com, keyhaede@gmail.com,
netdev@vger.kernel.org, sean.wang@mediatek.com,
linux-kernel@vger.kernel.org,
linux-mediatek@lists.infradead.org, objelf@gmail.com, davem@davemloft.net
Date: Wed, 29 Mar 2017 17:38:21 +0800
From: Sean Wang <sean.wang@mediatek.com>
The patch adds the setup for allowing CDM can recognize these packets with
carrying port-distinguishing tag. Otherwise, these tagging packets will be
handled incorrectly by CDM. The setup is also working out for general
untag packets as well.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Landen Chao <Landen.Chao@mediatek.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 6 ++++++
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++++
2 files changed, 10 insertions(+)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -1855,6 +1855,12 @@ static int mtk_hw_init(struct mtk_eth *e
/* GE2, Force 1000M/FD, FC ON */
mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1));
+ /* Indicates CDM to parse the MTK special tag from CPU
+ * which also is working out for untag packets.
+ */
+ val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
+ mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
+
/* Enable RX VLan Offloading */
mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -70,6 +70,10 @@
/* Frame Engine Interrupt Grouping Register */
#define MTK_FE_INT_GRP 0x20
+/* CDMP Ingress Control Register */
+#define MTK_CDMQ_IG_CTRL 0x1400
+#define MTK_CDMQ_STAG_EN BIT(0)
+
/* CDMP Exgress Control Register */
#define MTK_CDMP_EG_CTRL 0x404
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