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From 5b51a1e93ccaaec4cd90b73ee20cea219af2f151 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 6 Jan 2016 21:55:10 +0100
Subject: [PATCH 24/53] dt-bindings: add MediaTek PCIe binding documentation
Signed-off-by: John Crispin <blogic@openwrt.org>
---
.../devicetree/bindings/pci/mediatek-pcie.txt | 140 ++++++++++++++++++++
1 file changed, 140 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
new file mode 100644
index 0000000..8fea3ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
@@ -0,0 +1,140 @@
+Mediatek PCIe controller
+
+Required properties:
+- compatible: Should be one of:
+ - "mediatek,mt2701-pcie"
+ - "mediatek,mt7623-pcie"
+- device_type: Must be "pci"
+- reg: A list of physical base address and length for each set of controller
+ registers. A list of register ranges to use. Must contain an
+ entry for each entry in the reg-names property.
+- reg-names: Must include the following entries:
+ "pcie": PCIe registers
+ "pcie phy0": PCIe PHY0 registers
+ "pcie phy1": PCIe PHY0 registers
+ "pcie phy2": PCIe PHY0 registers
+- interrupts: A list of interrupt outputs of the controller. Must contain an
+ entry for each entry in the interrupt-names property.
+- interrupt-names: Must include the following entries:
+ "pcie0": The interrupt that is asserted for port0
+ "pcie1": The interrupt that is asserted for port1
+ "pcie2": The interrupt that is asserted for port2
+- bus-range: Range of bus numbers associated with this controller
+- #address-cells: Address representation for root ports (must be 3)
+- #size-cells: Size representation for root ports (must be 2)
+- ranges: Describes the translation of addresses for root ports and standard
+ PCI regions. The entries must be 6 cells each.
+ Please refer to the standard PCI bus binding document for a more detailed
+ explanation.
+- #interrupt-cells: Size representation for interrupts (must be 1)
+- clocks: Must contain an entry for each entry in clock-names.
+ See ../clocks/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+ - pcie0
+ - pcie1
+ - pcie2
+- resets: Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+- reset-names: Must include the following entries:
+ - pcie0
+ - pcie1
+ - pcie2
+- mediatek,hifsys: Must contain a phandle to the HIFSYS syscon range.
+Root ports are defined as subnodes of the PCIe controller node.
+
+Required properties:
+- device_type: Must be "pci"
+- assigned-addresses: Address and size of the port configuration registers
+- reg: PCI bus address of the root port
+- #address-cells: Must be 3
+- #size-cells: Must be 2
+- ranges: Sub-ranges distributed from the PCIe controller node. An empty
+ property is sufficient.
+
+Example:
+
+SoC DTSI:
+
+ hifsys: clock-controller@1a000000 {
+ compatible = "mediatek,mt7623-hifsys",
+ "mediatek,mt2701-hifsys",
+ "syscon";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pcie-controller@1a140000 {
+ compatible = "mediatek,mt7623-pcie";
+ device_type = "pci";
+ reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */
+ <0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */
+ <0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */
+ <0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */
+ reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2";
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "pcie0", "pcie1", "pcie2";
+ clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
+ clock-names = "pcie";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
+ resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
+ <&hifsys MT2701_HIFSYS_PCIE1_RST>,
+ <&hifsys MT2701_HIFSYS_PCIE2_RST>;
+ reset-names = "pcie0", "pice1", "pcie2";
+
+ bus-range = <0x00 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ mediatek,hifsys = <&hifsys>;
+
+ ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */
+ 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */
+
+ status = "disabled";
+
+ pcie@1,0 {
+ device_type = "pci";
+ reg = <0x0800 0 0 0 0>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+ };
+
+ pcie@2,0{
+ device_type = "pci";
+ reg = <0x1000 0 0 0 0>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+ };
+
+ pcie@3,0{
+ device_type = "pci";
+ reg = <0x1800 0 0 0 0>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+ };
+ };
+
+Board DTS:
+
+ pcie-controller {
+ status = "okay";
+
+ pci@1,0 {
+ status = "okay";
+ };
+ };
--
1.7.10.4
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