aboutsummaryrefslogtreecommitdiffstats
path: root/target/linux/lantiq/patches-3.3/100-falcon_bsp_header.patch
blob: 61105504c0baa8a336bd3325ea02d2bb0920d38f (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056
4057
4058
4059
4060
4061
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072
4073
4074
4075
4076
4077
4078
4079
4080
4081
4082
4083
4084
4085
4086
4087
4088
4089
4090
4091
4092
4093
4094
4095
4096
4097
4098
4099
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
4120
4121
4122
4123
4124
4125
4126
4127
4128
4129
4130
4131
4132
4133
4134
4135
4136
4137
4138
4139
4140
4141
4142
4143
4144
4145
4146
4147
4148
4149
4150
4151
4152
4153
4154
4155
4156
4157
4158
4159
4160
4161
4162
4163
4164
4165
4166
4167
4168
4169
4170
4171
4172
4173
4174
4175
4176
4177
4178
4179
4180
4181
4182
4183
4184
4185
4186
4187
4188
4189
4190
4191
4192
4193
4194
4195
4196
4197
4198
4199
4200
4201
4202
4203
4204
4205
4206
4207
4208
4209
4210
4211
4212
4213
4214
4215
4216
4217
4218
4219
4220
4221
4222
4223
4224
4225
4226
4227
4228
4229
4230
4231
4232
4233
4234
4235
4236
4237
4238
4239
4240
4241
4242
4243
4244
4245
4246
4247
4248
4249
4250
4251
4252
4253
4254
4255
4256
4257
4258
4259
4260
4261
4262
4263
4264
4265
4266
4267
4268
4269
4270
4271
4272
4273
4274
4275
4276
4277
4278
4279
4280
4281
4282
4283
4284
4285
4286
4287
4288
4289
4290
4291
4292
4293
4294
4295
4296
4297
4298
4299
4300
4301
4302
4303
4304
4305
4306
4307
4308
4309
4310
4311
4312
4313
4314
4315
4316
4317
4318
4319
4320
4321
4322
4323
4324
4325
4326
4327
4328
4329
4330
4331
4332
4333
4334
4335
4336
4337
4338
4339
4340
4341
4342
4343
4344
4345
4346
4347
4348
4349
4350
4351
4352
4353
4354
4355
4356
4357
4358
4359
4360
4361
4362
4363
4364
4365
4366
4367
4368
4369
4370
4371
4372
4373
4374
4375
4376
4377
4378
4379
4380
4381
4382
4383
4384
4385
4386
4387
4388
4389
4390
4391
4392
4393
4394
4395
4396
4397
4398
4399
4400
4401
4402
4403
4404
4405
4406
4407
4408
4409
4410
4411
4412
4413
4414
4415
4416
4417
4418
4419
4420
4421
4422
4423
4424
4425
4426
4427
4428
4429
4430
4431
4432
4433
4434
4435
4436
4437
4438
4439
4440
4441
4442
4443
4444
4445
4446
4447
4448
4449
4450
4451
4452
4453
4454
4455
4456
4457
4458
4459
4460
4461
4462
4463
4464
4465
4466
4467
4468
4469
4470
4471
4472
4473
4474
4475
4476
4477
4478
4479
4480
4481
4482
4483
4484
4485
4486
4487
4488
4489
4490
4491
4492
4493
4494
4495
4496
4497
4498
4499
4500
4501
4502
4503
4504
4505
4506
4507
4508
4509
4510
4511
4512
4513
4514
4515
4516
4517
4518
4519
4520
4521
4522
4523
4524
4525
4526
4527
4528
4529
4530
4531
4532
4533
4534
4535
4536
4537
4538
4539
4540
4541
4542
4543
4544
4545
4546
4547
4548
4549
4550
4551
4552
4553
4554
4555
4556
4557
4558
4559
4560
4561
4562
4563
4564
4565
4566
4567
4568
4569
4570
4571
4572
4573
4574
4575
4576
4577
4578
4579
4580
4581
4582
4583
4584
4585
4586
4587
4588
4589
4590
4591
4592
4593
4594
4595
4596
4597
4598
4599
4600
4601
4602
4603
4604
4605
4606
4607
4608
4609
4610
4611
4612
4613
4614
4615
4616
4617
4618
4619
4620
4621
4622
4623
4624
4625
4626
4627
4628
4629
4630
4631
4632
4633
4634
4635
4636
4637
4638
4639
4640
4641
4642
4643
4644
4645
4646
4647
4648
4649
4650
4651
4652
4653
4654
4655
4656
4657
4658
4659
4660
4661
4662
4663
4664
4665
4666
4667
4668
4669
4670
4671
4672
4673
4674
4675
4676
4677
4678
4679
4680
4681
4682
4683
4684
4685
4686
4687
4688
4689
4690
4691
4692
4693
4694
4695
4696
4697
4698
4699
4700
4701
4702
4703
4704
4705
4706
4707
4708
4709
4710
4711
4712
4713
4714
4715
4716
4717
4718
4719
4720
4721
4722
4723
4724
4725
4726
4727
4728
4729
4730
4731
4732
4733
4734
4735
4736
4737
4738
4739
4740
4741
4742
4743
4744
4745
4746
4747
4748
4749
4750
4751
4752
4753
4754
4755
4756
4757
4758
4759
4760
4761
4762
4763
4764
4765
4766
4767
4768
4769
4770
4771
4772
4773
4774
4775
4776
4777
4778
4779
4780
4781
4782
4783
4784
4785
4786
4787
4788
4789
4790
4791
4792
4793
4794
4795
4796
4797
4798
4799
4800
4801
4802
4803
4804
4805
4806
4807
4808
4809
4810
4811
4812
4813
4814
4815
4816
4817
4818
4819
4820
4821
4822
4823
4824
4825
4826
4827
4828
4829
4830
4831
4832
4833
4834
4835
4836
4837
4838
4839
4840
4841
4842
4843
4844
4845
4846
4847
4848
4849
4850
4851
4852
4853
4854
4855
4856
4857
4858
4859
4860
4861
4862
4863
4864
4865
4866
4867
4868
4869
4870
4871
4872
4873
4874
4875
4876
4877
4878
4879
4880
4881
4882
4883
4884
4885
4886
4887
4888
4889
4890
4891
4892
4893
4894
4895
4896
4897
4898
4899
4900
4901
4902
4903
4904
4905
4906
4907
4908
4909
4910
4911
4912
4913
4914
4915
4916
4917
4918
4919
4920
4921
4922
4923
4924
4925
4926
4927
4928
4929
4930
4931
4932
4933
4934
4935
4936
4937
4938
4939
4940
4941
4942
4943
4944
4945
4946
4947
4948
4949
4950
4951
4952
4953
4954
4955
4956
4957
4958
4959
4960
4961
4962
4963
4964
4965
4966
4967
4968
4969
4970
4971
4972
4973
4974
4975
4976
4977
4978
4979
4980
4981
4982
4983
4984
4985
4986
4987
4988
4989
4990
4991
4992
4993
4994
4995
4996
4997
4998
4999
5000
5001
5002
5003
5004
5005
5006
5007
5008
5009
5010
5011
5012
5013
5014
5015
5016
5017
5018
5019
5020
5021
5022
5023
5024
5025
5026
5027
5028
5029
5030
5031
5032
5033
5034
5035
5036
5037
5038
5039
5040
5041
5042
5043
5044
5045
5046
5047
5048
5049
5050
5051
5052
5053
5054
5055
5056
5057
5058
5059
5060
5061
5062
5063
5064
5065
5066
5067
5068
5069
5070
5071
5072
5073
5074
5075
5076
5077
5078
5079
5080
5081
5082
5083
5084
5085
5086
5087
5088
5089
5090
5091
5092
5093
5094
5095
5096
5097
5098
5099
5100
5101
5102
5103
5104
5105
5106
5107
5108
5109
5110
5111
5112
5113
5114
5115
5116
5117
5118
5119
5120
5121
5122
5123
5124
5125
5126
5127
5128
5129
5130
5131
5132
5133
5134
5135
5136
5137
5138
5139
5140
5141
5142
5143
5144
5145
5146
5147
5148
5149
5150
5151
5152
5153
5154
5155
5156
5157
5158
5159
5160
5161
5162
5163
5164
5165
5166
5167
5168
5169
5170
5171
5172
5173
5174
5175
5176
5177
5178
5179
5180
5181
5182
5183
5184
5185
5186
5187
5188
5189
5190
5191
5192
5193
5194
5195
5196
5197
5198
5199
5200
5201
5202
5203
5204
5205
5206
5207
5208
5209
5210
5211
5212
5213
5214
5215
5216
5217
5218
5219
5220
5221
5222
5223
5224
5225
5226
5227
5228
5229
5230
5231
5232
5233
5234
5235
5236
5237
5238
5239
5240
5241
5242
5243
5244
5245
5246
5247
5248
5249
5250
5251
5252
5253
5254
5255
5256
5257
5258
5259
5260
5261
5262
5263
5264
5265
5266
5267
5268
5269
5270
5271
5272
5273
5274
5275
5276
5277
5278
5279
5280
5281
5282
5283
5284
5285
5286
5287
5288
5289
5290
5291
5292
5293
5294
5295
5296
5297
5298
5299
5300
5301
5302
5303
5304
5305
5306
5307
5308
5309
5310
5311
5312
5313
5314
5315
5316
5317
5318
5319
5320
5321
5322
5323
5324
5325
5326
5327
5328
5329
5330
5331
5332
5333
5334
5335
5336
5337
5338
5339
5340
5341
5342
5343
5344
5345
5346
5347
5348
5349
5350
5351
5352
5353
5354
5355
5356
5357
5358
5359
5360
5361
5362
5363
5364
5365
5366
5367
5368
5369
5370
5371
5372
5373
5374
5375
5376
5377
5378
5379
5380
5381
5382
5383
5384
5385
5386
5387
5388
5389
5390
5391
5392
5393
5394
5395
5396
5397
5398
5399
5400
5401
5402
5403
5404
5405
5406
5407
5408
5409
5410
5411
5412
5413
5414
5415
5416
5417
5418
5419
5420
5421
5422
5423
5424
5425
5426
5427
5428
5429
5430
5431
5432
5433
5434
5435
5436
5437
5438
5439
5440
5441
5442
5443
5444
5445
5446
5447
5448
5449
5450
5451
5452
5453
5454
5455
5456
5457
5458
5459
5460
5461
5462
5463
5464
5465
5466
5467
5468
5469
5470
5471
5472
5473
5474
5475
5476
5477
5478
5479
5480
5481
5482
5483
5484
5485
5486
5487
5488
5489
5490
5491
5492
5493
5494
5495
5496
5497
5498
5499
5500
5501
5502
5503
5504
5505
5506
5507
5508
5509
5510
5511
5512
5513
5514
5515
5516
5517
5518
5519
5520
5521
5522
5523
5524
5525
5526
5527
5528
5529
5530
5531
5532
5533
5534
5535
5536
5537
5538
5539
5540
5541
5542
5543
5544
5545
5546
5547
5548
5549
5550
5551
5552
5553
5554
5555
5556
5557
5558
5559
5560
5561
5562
5563
5564
5565
5566
5567
5568
5569
5570
5571
5572
5573
5574
5575
5576
5577
5578
5579
5580
5581
5582
5583
5584
5585
5586
5587
5588
5589
5590
5591
5592
5593
5594
5595
5596
5597
5598
5599
5600
5601
5602
5603
5604
5605
5606
5607
5608
5609
5610
5611
5612
5613
5614
5615
5616
5617
5618
5619
5620
5621
5622
5623
5624
5625
5626
5627
5628
5629
5630
5631
5632
5633
5634
5635
5636
5637
5638
5639
5640
5641
5642
5643
5644
5645
5646
5647
5648
5649
5650
5651
5652
5653
5654
5655
5656
5657
5658
5659
5660
5661
5662
5663
5664
5665
5666
5667
5668
5669
5670
5671
5672
5673
5674
5675
5676
5677
5678
5679
5680
5681
5682
5683
5684
5685
5686
5687
5688
5689
5690
5691
5692
5693
5694
5695
5696
5697
5698
5699
5700
5701
5702
5703
5704
5705
5706
5707
5708
5709
5710
5711
5712
5713
5714
5715
5716
5717
5718
5719
5720
5721
5722
5723
5724
5725
5726
5727
5728
5729
5730
5731
5732
5733
5734
5735
5736
5737
5738
5739
5740
5741
5742
5743
5744
5745
5746
5747
5748
5749
5750
5751
5752
5753
5754
5755
5756
5757
5758
5759
5760
5761
5762
5763
5764
5765
5766
5767
5768
5769
5770
5771
5772
5773
5774
5775
5776
5777
5778
5779
5780
5781
5782
5783
5784
5785
5786
5787
5788
5789
5790
5791
5792
5793
5794
5795
5796
5797
5798
5799
5800
5801
5802
5803
5804
5805
5806
5807
5808
5809
5810
5811
5812
5813
5814
5815
5816
5817
5818
5819
5820
5821
5822
5823
5824
5825
5826
5827
5828
5829
5830
5831
5832
5833
5834
5835
5836
5837
5838
5839
5840
5841
5842
5843
5844
5845
5846
5847
5848
5849
5850
5851
5852
5853
5854
5855
5856
5857
5858
5859
5860
5861
5862
5863
5864
5865
5866
5867
5868
5869
5870
5871
5872
5873
5874
5875
5876
5877
5878
5879
5880
5881
5882
5883
5884
5885
5886
5887
5888
5889
5890
5891
5892
5893
5894
5895
5896
5897
5898
5899
5900
5901
5902
5903
5904
5905
5906
5907
5908
5909
5910
5911
5912
5913
5914
5915
5916
5917
5918
5919
5920
5921
5922
5923
5924
5925
5926
5927
5928
5929
5930
5931
5932
5933
5934
5935
5936
5937
5938
5939
5940
5941
5942
5943
5944
5945
5946
5947
5948
5949
5950
5951
5952
5953
5954
5955
5956
5957
5958
5959
5960
5961
5962
5963
5964
5965
5966
5967
5968
5969
5970
5971
5972
5973
5974
5975
5976
5977
5978
5979
5980
5981
5982
5983
5984
5985
5986
5987
5988
5989
5990
5991
5992
5993
5994
5995
5996
5997
5998
5999
6000
6001
6002
6003
6004
6005
6006
6007
6008
6009
6010
6011
6012
6013
6014
6015
6016
6017
6018
6019
6020
6021
6022
6023
6024
6025
6026
6027
6028
6029
6030
6031
6032
6033
6034
6035
6036
6037
6038
6039
6040
6041
6042
6043
6044
6045
6046
6047
6048
6049
6050
6051
6052
6053
6054
6055
6056
6057
6058
6059
6060
6061
6062
6063
6064
6065
6066
6067
6068
6069
6070
6071
6072
6073
6074
6075
6076
6077
6078
6079
6080
6081
6082
6083
6084
6085
6086
6087
6088
6089
6090
6091
6092
6093
6094
6095
6096
6097
6098
6099
6100
6101
6102
6103
6104
6105
6106
6107
6108
6109
6110
6111
6112
6113
6114
6115
6116
6117
6118
6119
6120
6121
6122
6123
6124
6125
6126
6127
6128
6129
6130
6131
6132
6133
6134
6135
6136
6137
6138
6139
6140
6141
6142
6143
6144
6145
6146
6147
6148
6149
6150
6151
6152
6153
6154
6155
6156
6157
6158
6159
6160
6161
6162
6163
6164
6165
6166
6167
6168
6169
6170
6171
6172
6173
6174
6175
6176
6177
6178
6179
6180
6181
6182
6183
6184
6185
6186
6187
6188
6189
6190
6191
6192
6193
6194
6195
6196
6197
6198
6199
6200
6201
6202
6203
6204
6205
6206
6207
6208
6209
6210
6211
6212
6213
6214
6215
6216
6217
6218
6219
6220
6221
6222
6223
6224
6225
6226
6227
6228
6229
6230
6231
6232
6233
6234
6235
6236
6237
6238
6239
6240
6241
6242
6243
6244
6245
6246
6247
6248
6249
6250
6251
6252
6253
6254
6255
6256
6257
6258
6259
6260
6261
6262
6263
6264
6265
6266
6267
6268
6269
6270
6271
6272
6273
6274
6275
6276
6277
6278
6279
6280
6281
6282
6283
6284
6285
6286
6287
6288
6289
6290
6291
6292
6293
6294
6295
6296
6297
6298
6299
6300
6301
6302
6303
6304
6305
6306
6307
6308
6309
6310
6311
6312
6313
6314
6315
6316
6317
6318
6319
6320
6321
6322
6323
6324
6325
6326
6327
6328
6329
6330
6331
6332
6333
6334
6335
6336
6337
6338
6339
6340
6341
6342
6343
6344
6345
6346
6347
6348
6349
6350
6351
6352
6353
6354
6355
6356
6357
6358
6359
6360
6361
6362
6363
6364
6365
6366
6367
6368
6369
6370
6371
6372
6373
6374
6375
6376
6377
6378
6379
6380
6381
6382
6383
6384
6385
6386
6387
6388
6389
6390
6391
6392
6393
6394
6395
6396
6397
6398
6399
6400
6401
6402
6403
6404
6405
6406
6407
6408
6409
6410
6411
6412
6413
6414
6415
6416
6417
6418
6419
6420
6421
6422
6423
6424
6425
6426
6427
6428
6429
6430
6431
6432
6433
6434
6435
6436
6437
6438
6439
6440
6441
6442
6443
6444
6445
6446
6447
6448
6449
6450
6451
6452
6453
6454
6455
6456
6457
6458
6459
6460
6461
6462
6463
6464
6465
6466
6467
6468
6469
6470
6471
6472
6473
6474
6475
6476
6477
6478
6479
6480
6481
6482
6483
6484
6485
6486
6487
6488
6489
6490
6491
6492
6493
6494
6495
6496
6497
6498
6499
6500
6501
6502
6503
6504
6505
6506
6507
6508
6509
6510
6511
6512
6513
6514
6515
6516
6517
6518
6519
6520
6521
6522
6523
6524
6525
6526
6527
6528
6529
6530
6531
6532
6533
6534
6535
6536
6537
6538
6539
6540
6541
6542
6543
6544
6545
6546
6547
6548
6549
6550
6551
6552
6553
6554
6555
6556
6557
6558
6559
6560
6561
6562
6563
6564
6565
6566
6567
6568
6569
6570
6571
6572
6573
6574
6575
6576
6577
6578
6579
6580
6581
6582
6583
6584
6585
6586
6587
6588
6589
6590
6591
6592
6593
6594
6595
6596
6597
6598
6599
6600
6601
6602
6603
6604
6605
6606
6607
6608
6609
6610
6611
6612
6613
6614
6615
6616
6617
6618
6619
6620
6621
6622
6623
6624
6625
6626
6627
6628
6629
6630
6631
6632
6633
6634
6635
6636
6637
6638
6639
6640
6641
6642
6643
6644
6645
6646
6647
6648
6649
6650
6651
6652
6653
6654
6655
6656
6657
6658
6659
6660
6661
6662
6663
6664
6665
6666
6667
6668
6669
6670
6671
6672
6673
6674
6675
6676
6677
6678
6679
6680
6681
6682
6683
6684
6685
6686
6687
6688
6689
6690
6691
6692
6693
6694
6695
6696
6697
6698
6699
6700
6701
6702
6703
6704
6705
6706
6707
6708
6709
6710
6711
6712
6713
6714
6715
6716
6717
6718
6719
6720
6721
6722
6723
6724
6725
6726
6727
6728
6729
6730
6731
6732
6733
6734
6735
6736
6737
6738
6739
6740
6741
6742
6743
6744
6745
6746
6747
6748
6749
6750
6751
6752
6753
6754
6755
6756
6757
6758
6759
6760
6761
6762
6763
6764
6765
6766
6767
6768
6769
6770
6771
6772
6773
6774
6775
6776
6777
6778
6779
6780
6781
6782
6783
6784
6785
6786
6787
6788
6789
6790
6791
6792
6793
6794
6795
6796
6797
6798
6799
6800
6801
6802
6803
6804
6805
6806
6807
6808
6809
6810
6811
6812
6813
6814
6815
6816
6817
6818
6819
6820
6821
6822
6823
6824
6825
6826
6827
6828
6829
6830
6831
6832
6833
6834
6835
6836
6837
6838
6839
6840
6841
6842
6843
6844
6845
6846
6847
6848
6849
6850
6851
6852
6853
6854
6855
6856
6857
6858
6859
6860
6861
6862
6863
6864
6865
6866
6867
6868
6869
6870
6871
6872
6873
6874
6875
6876
6877
6878
6879
6880
6881
6882
6883
6884
6885
6886
6887
6888
6889
6890
6891
6892
6893
6894
6895
6896
6897
6898
6899
6900
6901
6902
6903
6904
6905
6906
6907
6908
6909
6910
6911
6912
6913
6914
6915
6916
6917
6918
6919
6920
6921
6922
6923
6924
6925
6926
6927
6928
6929
6930
6931
6932
6933
6934
6935
6936
6937
6938
6939
6940
6941
6942
6943
6944
6945
6946
6947
6948
6949
6950
6951
6952
6953
6954
6955
6956
6957
6958
6959
6960
6961
6962
6963
6964
6965
6966
6967
6968
6969
6970
6971
6972
6973
6974
6975
6976
6977
6978
6979
6980
6981
6982
6983
6984
6985
6986
6987
6988
6989
6990
6991
6992
6993
6994
6995
6996
6997
6998
6999
7000
7001
7002
7003
7004
7005
7006
7007
7008
7009
7010
7011
7012
7013
7014
7015
7016
7017
7018
7019
7020
7021
7022
7023
7024
7025
7026
7027
7028
7029
7030
7031
7032
7033
7034
7035
7036
7037
7038
7039
7040
7041
7042
7043
7044
7045
7046
7047
7048
7049
7050
7051
7052
7053
7054
7055
7056
7057
7058
7059
7060
7061
7062
7063
7064
7065
7066
7067
7068
7069
7070
7071
7072
7073
7074
7075
7076
7077
7078
7079
7080
7081
7082
7083
7084
7085
7086
7087
7088
7089
7090
7091
7092
7093
7094
7095
7096
7097
7098
7099
7100
7101
7102
7103
7104
7105
7106
7107
7108
7109
7110
7111
7112
7113
7114
7115
7116
7117
7118
7119
7120
7121
7122
7123
7124
7125
7126
7127
7128
7129
7130
7131
7132
7133
7134
7135
7136
7137
7138
7139
7140
7141
7142
7143
7144
7145
7146
7147
7148
7149
7150
7151
7152
7153
7154
7155
7156
7157
7158
7159
7160
7161
7162
7163
7164
7165
7166
7167
7168
7169
7170
7171
7172
7173
7174
7175
7176
7177
7178
7179
7180
7181
7182
7183
7184
7185
7186
7187
7188
7189
7190
7191
7192
7193
7194
7195
7196
7197
7198
7199
7200
7201
7202
7203
7204
7205
7206
7207
7208
7209
7210
7211
7212
7213
7214
7215
7216
7217
7218
7219
7220
7221
7222
7223
7224
7225
7226
7227
7228
7229
7230
7231
7232
7233
7234
7235
7236
7237
7238
7239
7240
7241
7242
7243
7244
7245
7246
7247
7248
7249
7250
7251
7252
7253
7254
7255
7256
7257
7258
7259
7260
7261
7262
7263
7264
7265
7266
7267
7268
7269
7270
7271
7272
7273
7274
7275
7276
7277
7278
7279
7280
7281
7282
7283
7284
7285
7286
7287
7288
7289
7290
7291
7292
7293
7294
7295
7296
7297
7298
7299
7300
7301
7302
7303
7304
7305
7306
7307
7308
7309
7310
7311
7312
7313
7314
7315
7316
7317
7318
7319
7320
7321
7322
7323
7324
7325
7326
7327
7328
7329
7330
7331
7332
7333
7334
7335
7336
7337
7338
7339
7340
7341
7342
7343
7344
7345
7346
7347
7348
7349
7350
7351
7352
7353
7354
7355
7356
7357
7358
7359
7360
7361
7362
7363
7364
7365
7366
7367
7368
7369
7370
7371
7372
7373
7374
7375
7376
7377
7378
7379
7380
7381
7382
7383
7384
7385
7386
7387
7388
7389
7390
7391
7392
7393
7394
7395
7396
7397
7398
7399
7400
7401
7402
7403
7404
7405
7406
7407
7408
7409
7410
7411
7412
7413
7414
7415
7416
7417
7418
7419
7420
7421
7422
7423
7424
7425
7426
7427
7428
7429
7430
7431
7432
7433
7434
7435
7436
7437
7438
7439
7440
7441
7442
7443
7444
7445
7446
7447
7448
7449
7450
7451
7452
7453
7454
7455
7456
7457
7458
7459
7460
7461
7462
7463
7464
7465
7466
7467
7468
7469
7470
7471
7472
7473
7474
7475
7476
7477
7478
7479
7480
7481
7482
7483
7484
7485
7486
7487
7488
7489
7490
7491
7492
7493
7494
7495
7496
7497
7498
7499
7500
7501
7502
7503
7504
7505
7506
7507
7508
7509
7510
7511
7512
7513
7514
7515
7516
7517
7518
7519
7520
7521
7522
7523
7524
7525
7526
7527
7528
7529
7530
7531
7532
7533
7534
7535
7536
7537
7538
7539
7540
7541
7542
7543
7544
7545
7546
7547
7548
7549
7550
7551
7552
7553
7554
7555
7556
7557
7558
7559
7560
7561
7562
7563
7564
7565
7566
7567
7568
7569
7570
7571
7572
7573
7574
7575
7576
7577
7578
7579
7580
7581
7582
7583
7584
7585
7586
7587
7588
7589
7590
7591
7592
7593
7594
7595
7596
7597
7598
7599
7600
7601
7602
7603
7604
7605
7606
7607
7608
7609
7610
7611
7612
7613
7614
7615
7616
7617
7618
7619
7620
7621
7622
7623
7624
7625
7626
7627
7628
7629
7630
7631
7632
7633
7634
7635
7636
7637
7638
7639
7640
7641
7642
7643
7644
7645
7646
7647
7648
7649
7650
7651
7652
7653
7654
7655
7656
7657
7658
7659
7660
7661
7662
7663
7664
7665
7666
7667
7668
7669
7670
7671
7672
7673
7674
7675
7676
7677
7678
7679
7680
7681
7682
7683
7684
7685
7686
7687
7688
7689
7690
7691
7692
7693
7694
7695
7696
7697
7698
7699
7700
7701
7702
7703
7704
7705
7706
7707
7708
7709
7710
7711
7712
7713
7714
7715
7716
7717
7718
7719
7720
7721
7722
7723
7724
7725
7726
7727
7728
7729
7730
7731
7732
7733
7734
7735
7736
7737
7738
7739
7740
7741
7742
7743
7744
7745
7746
7747
7748
7749
7750
7751
7752
7753
7754
7755
7756
7757
7758
7759
7760
7761
7762
7763
7764
7765
7766
7767
7768
7769
7770
7771
7772
7773
7774
7775
7776
7777
7778
7779
7780
7781
7782
7783
7784
7785
7786
7787
7788
7789
7790
7791
7792
7793
7794
7795
7796
7797
7798
7799
7800
7801
7802
7803
7804
7805
7806
7807
7808
7809
7810
7811
7812
7813
7814
7815
7816
7817
7818
7819
7820
7821
7822
7823
7824
7825
7826
7827
7828
7829
7830
7831
7832
7833
7834
7835
7836
7837
7838
7839
7840
7841
7842
7843
7844
7845
7846
7847
7848
7849
7850
7851
7852
7853
7854
7855
7856
7857
7858
7859
7860
7861
7862
7863
7864
7865
7866
7867
7868
7869
7870
7871
7872
7873
7874
7875
7876
7877
7878
7879
7880
7881
7882
7883
7884
7885
7886
7887
7888
7889
7890
7891
7892
7893
7894
7895
7896
7897
7898
7899
7900
7901
7902
7903
7904
7905
7906
7907
7908
7909
7910
7911
7912
7913
7914
7915
7916
7917
7918
7919
7920
7921
7922
7923
7924
7925
7926
7927
7928
7929
7930
7931
7932
7933
7934
7935
7936
7937
7938
7939
7940
7941
7942
7943
7944
7945
7946
7947
7948
7949
7950
7951
7952
7953
7954
7955
7956
7957
7958
7959
7960
7961
7962
7963
7964
7965
7966
7967
7968
7969
7970
7971
7972
7973
7974
7975
7976
7977
7978
7979
7980
7981
7982
7983
7984
7985
7986
7987
7988
7989
7990
7991
7992
7993
7994
7995
7996
7997
7998
7999
8000
8001
8002
8003
8004
8005
8006
8007
8008
8009
8010
8011
8012
8013
8014
8015
8016
8017
8018
8019
8020
8021
8022
8023
8024
8025
8026
8027
8028
8029
8030
8031
8032
8033
8034
8035
8036
8037
8038
8039
8040
8041
8042
8043
8044
8045
8046
8047
8048
8049
8050
8051
8052
8053
8054
8055
8056
8057
8058
8059
8060
8061
8062
8063
8064
8065
8066
8067
8068
8069
8070
8071
8072
8073
8074
8075
8076
8077
8078
8079
8080
8081
8082
8083
8084
8085
8086
8087
8088
8089
8090
8091
8092
8093
8094
8095
8096
8097
8098
8099
8100
8101
8102
8103
8104
8105
8106
8107
8108
8109
8110
8111
8112
8113
8114
8115
8116
8117
8118
8119
8120
8121
8122
8123
8124
8125
8126
8127
8128
8129
8130
8131
8132
8133
8134
8135
8136
8137
8138
8139
8140
8141
8142
8143
8144
8145
8146
8147
8148
8149
8150
8151
8152
8153
8154
8155
8156
8157
8158
8159
8160
8161
8162
8163
8164
8165
8166
8167
8168
8169
8170
8171
8172
8173
8174
8175
8176
8177
8178
8179
8180
8181
8182
8183
8184
8185
8186
8187
8188
8189
8190
8191
8192
8193
8194
8195
8196
8197
8198
8199
8200
8201
8202
8203
8204
8205
8206
8207
8208
8209
8210
8211
8212
8213
8214
8215
8216
8217
8218
8219
8220
8221
8222
8223
8224
8225
8226
8227
8228
8229
8230
8231
8232
8233
8234
8235
8236
8237
8238
8239
8240
8241
8242
8243
8244
8245
8246
8247
8248
8249
8250
8251
8252
8253
8254
8255
8256
8257
8258
8259
8260
8261
8262
8263
8264
8265
8266
8267
8268
8269
8270
8271
8272
8273
8274
8275
8276
8277
8278
8279
8280
8281
8282
8283
8284
8285
8286
8287
8288
8289
8290
8291
8292
8293
8294
8295
8296
8297
8298
8299
8300
8301
8302
8303
8304
8305
8306
8307
8308
8309
8310
8311
8312
8313
8314
8315
8316
8317
8318
8319
8320
8321
8322
8323
8324
8325
8326
8327
8328
8329
8330
8331
8332
8333
8334
8335
8336
8337
8338
8339
8340
8341
8342
8343
8344
8345
8346
8347
8348
8349
8350
8351
8352
8353
8354
8355
8356
8357
8358
8359
8360
8361
8362
8363
8364
8365
8366
8367
8368
8369
8370
8371
8372
8373
8374
8375
8376
8377
8378
8379
8380
8381
8382
8383
8384
8385
8386
8387
8388
8389
8390
8391
8392
8393
8394
8395
8396
8397
8398
8399
8400
8401
8402
8403
8404
8405
8406
8407
8408
8409
8410
8411
8412
8413
8414
8415
8416
8417
8418
8419
8420
8421
8422
8423
8424
8425
8426
8427
8428
8429
8430
8431
8432
8433
8434
8435
8436
8437
8438
8439
8440
8441
8442
8443
8444
8445
8446
8447
8448
8449
8450
8451
8452
8453
8454
8455
8456
8457
8458
8459
8460
8461
8462
8463
8464
8465
8466
8467
8468
8469
8470
8471
8472
8473
8474
8475
8476
8477
8478
8479
8480
8481
8482
8483
8484
8485
8486
8487
8488
8489
8490
8491
8492
8493
8494
8495
8496
8497
8498
8499
8500
8501
8502
8503
8504
8505
8506
8507
8508
8509
8510
8511
8512
8513
8514
8515
8516
8517
8518
8519
8520
8521
8522
8523
8524
8525
8526
8527
8528
8529
8530
8531
8532
8533
8534
8535
8536
8537
8538
8539
8540
8541
8542
8543
8544
8545
8546
8547
8548
8549
8550
8551
8552
8553
8554
8555
8556
8557
8558
8559
8560
8561
8562
8563
8564
8565
8566
8567
8568
8569
8570
8571
8572
8573
8574
8575
8576
8577
8578
8579
8580
8581
8582
8583
8584
8585
8586
8587
8588
8589
8590
8591
8592
8593
8594
8595
8596
8597
8598
8599
8600
8601
8602
8603
8604
8605
8606
8607
8608
8609
8610
8611
8612
8613
8614
8615
8616
8617
8618
8619
8620
8621
8622
8623
8624
8625
8626
8627
8628
8629
8630
8631
8632
8633
8634
8635
8636
8637
8638
8639
8640
8641
8642
8643
8644
8645
8646
8647
8648
8649
8650
8651
8652
8653
8654
8655
8656
8657
8658
8659
8660
8661
8662
8663
8664
8665
8666
8667
8668
8669
8670
8671
8672
8673
8674
8675
8676
8677
8678
8679
8680
8681
8682
8683
8684
8685
8686
8687
8688
8689
8690
8691
8692
8693
8694
8695
8696
8697
8698
8699
8700
8701
8702
8703
8704
8705
8706
8707
8708
8709
8710
8711
8712
8713
8714
8715
8716
8717
8718
8719
8720
8721
8722
8723
8724
8725
8726
8727
8728
8729
8730
8731
8732
8733
8734
8735
8736
8737
8738
8739
8740
8741
8742
8743
8744
8745
8746
8747
8748
8749
8750
8751
8752
8753
8754
8755
8756
8757
8758
8759
8760
8761
8762
8763
8764
8765
8766
8767
8768
8769
8770
8771
8772
8773
8774
8775
8776
8777
8778
8779
8780
8781
8782
8783
8784
8785
8786
8787
8788
8789
8790
8791
8792
8793
8794
8795
8796
8797
8798
8799
8800
8801
8802
8803
8804
8805
8806
8807
8808
8809
8810
8811
8812
8813
8814
8815
8816
8817
8818
8819
8820
8821
8822
8823
8824
8825
8826
8827
8828
8829
8830
8831
8832
8833
8834
8835
8836
8837
8838
8839
8840
8841
8842
8843
8844
8845
8846
8847
8848
8849
8850
8851
8852
8853
8854
8855
8856
8857
8858
8859
8860
8861
8862
8863
8864
8865
8866
8867
8868
8869
8870
8871
8872
8873
8874
8875
8876
8877
8878
8879
8880
8881
8882
8883
8884
8885
8886
8887
8888
8889
8890
8891
8892
8893
8894
8895
8896
8897
8898
8899
8900
8901
8902
8903
8904
8905
8906
8907
8908
8909
8910
8911
8912
8913
8914
8915
8916
8917
8918
8919
8920
8921
8922
8923
8924
8925
8926
8927
8928
8929
8930
8931
8932
8933
8934
8935
8936
8937
8938
8939
8940
8941
8942
8943
8944
8945
8946
8947
8948
8949
8950
8951
8952
8953
8954
8955
8956
8957
8958
8959
8960
8961
8962
8963
8964
8965
8966
8967
8968
8969
8970
8971
8972
8973
8974
8975
8976
8977
8978
8979
8980
8981
8982
8983
8984
8985
8986
8987
8988
8989
8990
8991
8992
8993
8994
8995
8996
8997
8998
8999
9000
9001
9002
9003
9004
9005
9006
9007
9008
9009
9010
9011
9012
9013
9014
9015
9016
9017
9018
9019
9020
9021
9022
9023
9024
9025
9026
9027
9028
9029
9030
9031
9032
9033
9034
9035
9036
9037
9038
9039
9040
9041
9042
9043
9044
9045
9046
9047
9048
9049
9050
9051
9052
9053
9054
9055
9056
9057
9058
9059
9060
9061
9062
9063
9064
9065
9066
9067
9068
9069
9070
9071
9072
9073
9074
9075
9076
9077
9078
9079
9080
9081
9082
9083
9084
9085
9086
9087
9088
9089
9090
9091
9092
9093
9094
9095
9096
9097
9098
9099
9100
9101
9102
9103
9104
9105
9106
9107
9108
9109
9110
9111
9112
9113
9114
9115
9116
9117
9118
9119
9120
9121
9122
9123
9124
9125
9126
9127
9128
9129
9130
9131
9132
9133
9134
9135
9136
9137
9138
9139
9140
9141
9142
9143
9144
9145
9146
9147
9148
9149
9150
9151
9152
9153
9154
9155
9156
9157
9158
9159
9160
9161
9162
9163
9164
9165
9166
9167
9168
9169
9170
9171
9172
9173
9174
9175
9176
9177
9178
9179
9180
9181
9182
9183
9184
9185
9186
9187
9188
9189
9190
9191
9192
9193
9194
9195
9196
9197
9198
9199
9200
9201
9202
9203
9204
9205
9206
9207
9208
9209
9210
9211
9212
9213
9214
9215
9216
9217
9218
9219
9220
9221
9222
9223
9224
9225
9226
9227
9228
9229
9230
9231
9232
9233
9234
9235
9236
9237
9238
9239
9240
9241
9242
9243
9244
9245
9246
9247
9248
9249
9250
9251
9252
9253
9254
9255
9256
9257
9258
9259
9260
9261
9262
9263
9264
9265
9266
9267
9268
9269
9270
9271
9272
9273
9274
9275
9276
9277
9278
9279
9280
9281
9282
9283
9284
9285
9286
9287
9288
9289
9290
9291
9292
9293
9294
9295
9296
9297
9298
9299
9300
9301
9302
9303
9304
9305
9306
9307
9308
9309
9310
9311
9312
9313
9314
9315
9316
9317
9318
9319
9320
9321
9322
9323
9324
9325
9326
9327
9328
9329
9330
9331
9332
9333
9334
9335
9336
9337
9338
9339
9340
9341
9342
9343
9344
9345
9346
9347
9348
9349
9350
9351
9352
9353
9354
9355
9356
9357
9358
9359
9360
9361
9362
9363
9364
9365
9366
9367
9368
9369
9370
9371
9372
9373
9374
9375
9376
9377
9378
9379
9380
9381
9382
9383
9384
9385
9386
9387
9388
9389
9390
9391
9392
9393
9394
9395
9396
9397
9398
9399
9400
9401
9402
9403
9404
9405
9406
9407
9408
9409
9410
9411
9412
9413
9414
9415
9416
9417
9418
9419
9420
9421
9422
9423
9424
9425
9426
9427
9428
9429
9430
9431
9432
9433
9434
9435
9436
9437
9438
9439
9440
9441
9442
9443
9444
9445
9446
9447
9448
9449
9450
9451
9452
9453
9454
9455
9456
9457
9458
9459
9460
9461
9462
9463
9464
9465
9466
9467
9468
9469
9470
9471
9472
9473
9474
9475
9476
9477
9478
9479
9480
9481
9482
9483
9484
9485
9486
9487
9488
9489
9490
9491
9492
9493
9494
9495
9496
9497
9498
9499
9500
9501
9502
9503
9504
9505
9506
9507
9508
9509
9510
9511
9512
9513
9514
9515
9516
9517
9518
9519
9520
9521
9522
9523
9524
9525
9526
9527
9528
9529
9530
9531
9532
9533
9534
9535
9536
9537
9538
9539
9540
9541
9542
9543
9544
9545
9546
9547
9548
9549
9550
9551
9552
9553
9554
9555
9556
9557
9558
9559
9560
9561
9562
9563
9564
9565
9566
9567
9568
9569
9570
9571
9572
9573
9574
9575
9576
9577
9578
9579
9580
9581
9582
9583
9584
9585
9586
9587
9588
9589
9590
9591
9592
9593
9594
9595
9596
9597
9598
9599
9600
9601
9602
9603
9604
9605
9606
9607
9608
9609
9610
9611
9612
9613
9614
9615
9616
9617
9618
9619
9620
9621
9622
9623
9624
9625
9626
9627
9628
9629
9630
9631
9632
9633
9634
9635
9636
9637
9638
9639
9640
9641
9642
9643
9644
9645
9646
9647
9648
9649
9650
9651
9652
9653
9654
9655
9656
9657
9658
9659
9660
9661
9662
9663
9664
9665
9666
9667
9668
9669
9670
9671
9672
9673
9674
9675
9676
9677
9678
9679
9680
9681
9682
9683
9684
9685
9686
9687
9688
9689
9690
9691
9692
9693
9694
9695
9696
9697
9698
9699
9700
9701
9702
9703
9704
9705
9706
9707
9708
9709
9710
9711
9712
9713
9714
9715
9716
9717
9718
9719
9720
9721
9722
9723
9724
9725
9726
9727
9728
9729
9730
9731
9732
9733
9734
9735
9736
9737
9738
9739
9740
9741
9742
9743
9744
9745
9746
9747
9748
9749
9750
9751
9752
9753
9754
9755
9756
9757
9758
9759
9760
9761
9762
9763
9764
9765
9766
9767
9768
9769
9770
9771
9772
9773
9774
9775
9776
9777
9778
9779
9780
9781
9782
9783
9784
9785
9786
9787
9788
9789
9790
9791
9792
9793
9794
9795
9796
9797
9798
9799
9800
9801
9802
9803
9804
9805
9806
9807
9808
9809
9810
9811
9812
9813
9814
9815
9816
9817
9818
9819
9820
9821
9822
9823
9824
9825
9826
9827
9828
9829
9830
9831
9832
9833
9834
9835
9836
9837
9838
9839
9840
9841
9842
9843
9844
9845
9846
9847
9848
9849
9850
9851
9852
9853
9854
9855
9856
9857
9858
9859
9860
9861
9862
9863
9864
9865
9866
9867
9868
9869
9870
9871
9872
9873
9874
9875
9876
9877
9878
9879
9880
9881
9882
9883
9884
9885
9886
9887
9888
9889
9890
9891
9892
9893
9894
9895
9896
9897
9898
9899
9900
9901
9902
9903
9904
9905
9906
9907
9908
9909
9910
9911
9912
9913
9914
9915
9916
9917
9918
9919
9920
9921
9922
9923
9924
9925
9926
9927
9928
9929
9930
9931
9932
9933
9934
9935
9936
9937
9938
9939
9940
9941
9942
9943
9944
9945
9946
9947
9948
9949
9950
9951
9952
9953
9954
9955
9956
9957
9958
9959
9960
9961
9962
9963
9964
9965
9966
9967
9968
9969
9970
9971
9972
9973
9974
9975
9976
9977
9978
9979
9980
9981
9982
9983
9984
9985
9986
9987
9988
9989
9990
9991
9992
9993
9994
9995
9996
9997
9998
9999
10000
10001
10002
10003
10004
10005
10006
10007
10008
10009
10010
10011
10012
10013
10014
10015
10016
10017
10018
10019
10020
10021
10022
10023
10024
10025
10026
10027
10028
10029
10030
10031
10032
10033
10034
10035
10036
10037
10038
10039
10040
10041
10042
10043
10044
10045
10046
10047
10048
10049
10050
10051
10052
10053
10054
10055
10056
10057
10058
10059
10060
10061
10062
10063
10064
10065
10066
10067
10068
10069
10070
10071
10072
10073
10074
10075
10076
10077
10078
10079
10080
10081
10082
10083
10084
10085
10086
10087
10088
10089
10090
10091
10092
10093
10094
10095
10096
10097
10098
10099
10100
10101
10102
10103
10104
10105
10106
10107
10108
10109
10110
10111
10112
10113
10114
10115
10116
10117
10118
10119
10120
10121
10122
10123
10124
10125
10126
10127
10128
10129
10130
10131
10132
10133
10134
10135
10136
10137
10138
10139
10140
10141
10142
10143
10144
10145
10146
10147
10148
10149
10150
10151
10152
10153
10154
10155
10156
10157
10158
10159
10160
10161
10162
10163
10164
10165
10166
10167
10168
10169
10170
10171
10172
10173
10174
10175
10176
10177
10178
10179
10180
10181
10182
10183
10184
10185
10186
10187
10188
10189
10190
10191
10192
10193
10194
10195
10196
10197
10198
10199
10200
10201
10202
10203
10204
10205
10206
10207
10208
10209
10210
10211
10212
10213
10214
10215
10216
10217
10218
10219
10220
10221
10222
10223
10224
10225
10226
10227
10228
10229
10230
10231
10232
10233
10234
10235
10236
10237
10238
10239
10240
10241
10242
10243
10244
10245
10246
10247
10248
10249
10250
10251
10252
10253
10254
10255
10256
10257
10258
10259
10260
10261
10262
10263
10264
10265
10266
10267
10268
10269
10270
10271
10272
10273
10274
10275
10276
10277
10278
10279
10280
10281
10282
10283
10284
10285
10286
10287
10288
10289
10290
10291
10292
10293
10294
10295
10296
10297
10298
10299
10300
10301
10302
10303
10304
10305
10306
10307
10308
10309
10310
10311
10312
10313
10314
10315
10316
10317
10318
10319
10320
10321
10322
10323
10324
10325
10326
10327
10328
10329
10330
10331
10332
10333
10334
10335
10336
10337
10338
10339
10340
10341
10342
10343
10344
10345
10346
10347
10348
10349
10350
10351
10352
10353
10354
10355
10356
10357
10358
10359
10360
10361
10362
10363
10364
10365
10366
10367
10368
10369
10370
10371
10372
10373
10374
10375
10376
10377
10378
10379
10380
10381
10382
10383
10384
10385
10386
10387
10388
10389
10390
10391
10392
10393
10394
10395
10396
10397
10398
10399
10400
10401
10402
10403
10404
10405
10406
10407
10408
10409
10410
10411
10412
10413
10414
10415
10416
10417
10418
10419
10420
10421
10422
10423
10424
10425
10426
10427
10428
10429
10430
10431
10432
10433
10434
10435
10436
10437
10438
10439
10440
10441
10442
10443
10444
10445
10446
10447
10448
10449
10450
10451
10452
10453
10454
10455
10456
10457
10458
10459
10460
10461
10462
10463
10464
10465
10466
10467
10468
10469
10470
10471
10472
10473
10474
10475
10476
10477
10478
10479
10480
10481
10482
10483
10484
10485
10486
10487
10488
10489
10490
10491
10492
10493
10494
10495
10496
10497
10498
10499
10500
10501
10502
10503
10504
10505
10506
10507
10508
10509
10510
10511
10512
10513
10514
10515
10516
10517
10518
10519
10520
10521
10522
10523
10524
10525
10526
10527
10528
10529
10530
10531
10532
10533
10534
10535
10536
10537
10538
10539
10540
10541
10542
10543
10544
10545
10546
10547
10548
10549
10550
10551
10552
10553
10554
10555
10556
10557
10558
10559
10560
10561
10562
10563
10564
10565
10566
10567
10568
10569
10570
10571
10572
10573
10574
10575
10576
10577
10578
10579
10580
10581
10582
10583
10584
10585
10586
10587
10588
10589
10590
10591
10592
10593
10594
10595
10596
10597
10598
10599
10600
10601
10602
10603
10604
10605
10606
10607
10608
10609
10610
10611
10612
10613
10614
10615
10616
10617
10618
10619
10620
10621
10622
10623
10624
10625
10626
10627
10628
10629
10630
10631
10632
10633
10634
10635
10636
10637
10638
10639
10640
10641
10642
10643
10644
10645
10646
10647
10648
10649
10650
10651
10652
10653
10654
10655
10656
10657
10658
10659
10660
10661
10662
10663
10664
10665
10666
10667
10668
10669
10670
10671
10672
10673
10674
10675
10676
10677
10678
10679
10680
10681
10682
10683
10684
10685
10686
10687
10688
10689
10690
10691
10692
10693
10694
10695
10696
10697
10698
10699
10700
10701
10702
10703
10704
10705
10706
10707
10708
10709
10710
10711
10712
10713
10714
10715
10716
10717
10718
10719
10720
10721
10722
10723
10724
10725
10726
10727
10728
10729
10730
10731
10732
10733
10734
10735
10736
10737
10738
10739
10740
10741
10742
10743
10744
10745
10746
10747
10748
10749
10750
10751
10752
10753
10754
10755
10756
10757
10758
10759
10760
10761
10762
10763
10764
10765
10766
10767
10768
10769
10770
10771
10772
10773
10774
10775
10776
10777
10778
10779
10780
10781
10782
10783
10784
10785
10786
10787
10788
10789
10790
10791
10792
10793
10794
10795
10796
10797
10798
10799
10800
10801
10802
10803
10804
10805
10806
10807
10808
10809
10810
10811
10812
10813
10814
10815
10816
10817
10818
10819
10820
10821
10822
10823
10824
10825
10826
10827
10828
10829
10830
10831
10832
10833
10834
10835
10836
10837
10838
10839
10840
10841
10842
10843
10844
10845
10846
10847
10848
10849
10850
10851
10852
10853
10854
10855
10856
10857
10858
10859
10860
10861
10862
10863
10864
10865
10866
10867
10868
10869
10870
10871
10872
10873
10874
10875
10876
10877
10878
10879
10880
10881
10882
10883
10884
10885
10886
10887
10888
10889
10890
10891
10892
10893
10894
10895
10896
10897
10898
10899
10900
10901
10902
10903
10904
10905
10906
10907
10908
10909
10910
10911
10912
10913
10914
10915
10916
10917
10918
10919
10920
10921
10922
10923
10924
10925
10926
10927
10928
10929
10930
10931
10932
10933
10934
10935
10936
10937
10938
10939
10940
10941
10942
10943
10944
10945
10946
10947
10948
10949
10950
10951
10952
10953
10954
10955
10956
10957
10958
10959
10960
10961
10962
10963
10964
10965
10966
10967
10968
10969
10970
10971
10972
10973
10974
10975
10976
10977
10978
10979
10980
10981
10982
10983
10984
10985
10986
10987
10988
10989
10990
10991
10992
10993
10994
10995
10996
10997
10998
10999
11000
11001
11002
11003
11004
11005
11006
11007
11008
11009
11010
11011
11012
11013
11014
11015
11016
11017
11018
11019
11020
11021
11022
11023
11024
11025
11026
11027
11028
11029
11030
11031
11032
11033
11034
11035
11036
11037
11038
11039
11040
11041
11042
11043
11044
11045
11046
11047
11048
11049
11050
11051
11052
11053
11054
11055
11056
11057
11058
11059
11060
11061
11062
11063
11064
11065
11066
11067
11068
11069
11070
11071
11072
11073
11074
11075
11076
11077
11078
11079
11080
11081
11082
11083
11084
11085
11086
11087
11088
11089
11090
11091
11092
11093
11094
11095
11096
11097
11098
11099
11100
11101
11102
11103
11104
11105
11106
11107
11108
11109
11110
11111
11112
11113
11114
11115
11116
11117
11118
11119
11120
11121
11122
11123
11124
11125
11126
11127
11128
11129
11130
11131
11132
11133
11134
11135
11136
11137
11138
11139
11140
11141
11142
11143
11144
11145
11146
11147
11148
11149
11150
11151
11152
11153
11154
11155
11156
11157
11158
11159
11160
11161
11162
11163
11164
11165
11166
11167
11168
11169
11170
11171
11172
11173
11174
11175
11176
11177
11178
11179
11180
11181
11182
11183
11184
11185
11186
11187
11188
11189
11190
11191
11192
11193
11194
11195
11196
11197
11198
11199
11200
11201
11202
11203
11204
11205
11206
11207
11208
11209
11210
11211
11212
11213
11214
11215
11216
11217
11218
11219
11220
11221
11222
11223
11224
11225
11226
11227
11228
11229
11230
11231
11232
11233
11234
11235
11236
11237
11238
11239
11240
11241
11242
11243
11244
11245
11246
11247
11248
11249
11250
11251
11252
11253
11254
11255
11256
11257
11258
11259
11260
11261
11262
11263
11264
11265
11266
11267
11268
11269
11270
11271
11272
11273
11274
11275
11276
11277
11278
11279
11280
11281
11282
11283
11284
11285
11286
11287
11288
11289
11290
11291
11292
11293
11294
11295
11296
11297
11298
11299
11300
11301
11302
11303
11304
11305
11306
11307
11308
11309
11310
11311
11312
11313
11314
11315
11316
11317
11318
11319
11320
11321
11322
11323
11324
11325
11326
11327
11328
11329
11330
11331
11332
11333
11334
11335
11336
11337
11338
11339
11340
11341
11342
11343
11344
11345
11346
11347
11348
11349
11350
11351
11352
11353
11354
11355
11356
11357
11358
11359
11360
11361
11362
11363
11364
11365
11366
11367
11368
11369
11370
11371
11372
11373
11374
11375
11376
11377
11378
11379
11380
11381
11382
11383
11384
11385
11386
11387
11388
11389
11390
11391
11392
11393
11394
11395
11396
11397
11398
11399
11400
11401
11402
11403
11404
11405
11406
11407
11408
11409
11410
11411
11412
11413
11414
11415
11416
11417
11418
11419
11420
11421
11422
11423
11424
11425
11426
11427
11428
11429
11430
11431
11432
11433
11434
11435
11436
11437
11438
11439
11440
11441
11442
11443
11444
11445
11446
11447
11448
11449
11450
11451
11452
11453
11454
11455
11456
11457
11458
11459
11460
11461
11462
11463
11464
11465
11466
11467
11468
11469
11470
11471
11472
11473
11474
11475
11476
11477
11478
11479
11480
11481
11482
11483
11484
11485
11486
11487
11488
11489
11490
11491
11492
11493
11494
11495
11496
11497
11498
11499
11500
11501
11502
11503
11504
11505
11506
11507
11508
11509
11510
11511
11512
11513
11514
11515
11516
11517
11518
11519
11520
11521
11522
11523
11524
11525
11526
11527
11528
11529
11530
11531
11532
11533
11534
11535
11536
11537
11538
11539
11540
11541
11542
11543
11544
11545
11546
11547
11548
11549
11550
11551
11552
11553
11554
11555
11556
11557
11558
11559
11560
11561
11562
11563
11564
11565
11566
11567
11568
11569
11570
11571
11572
11573
11574
11575
11576
11577
11578
11579
11580
11581
11582
11583
11584
11585
11586
11587
11588
11589
11590
11591
11592
11593
11594
11595
11596
11597
11598
11599
11600
11601
11602
11603
11604
11605
11606
11607
11608
11609
11610
11611
11612
11613
11614
11615
11616
11617
11618
11619
11620
11621
11622
11623
11624
11625
11626
11627
11628
11629
11630
11631
11632
11633
11634
11635
11636
11637
11638
11639
11640
11641
11642
11643
11644
11645
11646
11647
11648
11649
11650
11651
11652
11653
11654
11655
11656
11657
11658
11659
11660
11661
11662
11663
11664
11665
11666
11667
11668
11669
11670
11671
11672
11673
11674
11675
11676
11677
11678
11679
11680
11681
11682
11683
11684
11685
11686
11687
11688
11689
11690
11691
11692
11693
11694
11695
11696
11697
11698
11699
11700
11701
11702
11703
11704
11705
11706
11707
11708
11709
11710
11711
11712
11713
11714
11715
11716
11717
11718
11719
11720
11721
11722
11723
11724
11725
11726
11727
11728
11729
11730
11731
11732
11733
11734
11735
11736
11737
11738
11739
11740
11741
11742
11743
11744
11745
11746
11747
11748
11749
11750
11751
11752
11753
11754
11755
11756
11757
11758
11759
11760
11761
11762
11763
11764
11765
11766
11767
11768
11769
11770
11771
11772
11773
11774
11775
11776
11777
11778
11779
11780
11781
11782
11783
11784
11785
11786
11787
11788
11789
11790
11791
11792
11793
11794
11795
11796
11797
11798
11799
11800
11801
11802
11803
11804
11805
11806
11807
11808
11809
11810
11811
11812
11813
11814
11815
11816
11817
11818
11819
11820
11821
11822
11823
11824
11825
11826
11827
11828
11829
11830
11831
11832
11833
11834
11835
11836
11837
11838
11839
11840
11841
11842
11843
11844
11845
11846
11847
11848
11849
11850
11851
11852
11853
11854
11855
11856
11857
11858
11859
11860
11861
11862
11863
11864
11865
11866
11867
11868
11869
11870
11871
11872
11873
11874
11875
11876
11877
11878
11879
11880
11881
11882
11883
11884
11885
11886
11887
11888
11889
11890
11891
11892
11893
11894
11895
11896
11897
11898
11899
11900
11901
11902
11903
11904
11905
11906
11907
11908
11909
11910
11911
11912
11913
11914
11915
11916
11917
11918
11919
11920
11921
11922
11923
11924
11925
11926
11927
11928
11929
11930
11931
11932
11933
11934
11935
11936
11937
11938
11939
11940
11941
11942
11943
11944
11945
11946
11947
11948
11949
11950
11951
11952
11953
11954
11955
11956
11957
11958
11959
11960
11961
11962
11963
11964
11965
11966
11967
11968
11969
11970
11971
11972
11973
11974
11975
11976
11977
11978
11979
11980
11981
11982
11983
11984
11985
11986
11987
11988
11989
11990
11991
11992
11993
11994
11995
11996
11997
11998
11999
12000
12001
12002
12003
12004
12005
12006
12007
12008
12009
12010
12011
12012
12013
12014
12015
12016
12017
12018
12019
12020
12021
12022
12023
12024
12025
12026
12027
12028
12029
12030
12031
12032
12033
12034
12035
12036
12037
12038
12039
12040
12041
12042
12043
12044
12045
12046
12047
12048
12049
12050
12051
12052
12053
12054
12055
12056
12057
12058
12059
12060
12061
12062
12063
12064
12065
12066
12067
12068
12069
12070
12071
12072
12073
12074
12075
12076
12077
12078
12079
12080
12081
12082
12083
12084
12085
12086
12087
12088
12089
12090
12091
12092
12093
12094
12095
12096
12097
12098
12099
12100
12101
12102
12103
12104
12105
12106
12107
12108
12109
12110
12111
12112
12113
12114
12115
12116
12117
12118
12119
12120
12121
12122
12123
12124
12125
12126
12127
12128
12129
12130
12131
12132
12133
12134
12135
12136
12137
12138
12139
12140
12141
12142
12143
12144
12145
12146
12147
12148
12149
12150
12151
12152
12153
12154
12155
12156
12157
12158
12159
12160
12161
12162
12163
12164
12165
12166
12167
12168
12169
12170
12171
12172
12173
12174
12175
12176
12177
12178
12179
12180
12181
12182
12183
12184
12185
12186
12187
12188
12189
12190
12191
12192
12193
12194
12195
12196
12197
12198
12199
12200
12201
12202
12203
12204
12205
12206
12207
12208
12209
12210
12211
12212
12213
12214
12215
12216
12217
12218
12219
12220
12221
12222
12223
12224
12225
12226
12227
12228
12229
12230
12231
12232
12233
12234
12235
12236
12237
12238
12239
12240
12241
12242
12243
12244
12245
12246
12247
12248
12249
12250
12251
12252
12253
12254
12255
12256
12257
12258
12259
12260
12261
12262
12263
12264
12265
12266
12267
12268
12269
12270
12271
12272
12273
12274
12275
12276
12277
12278
12279
12280
12281
12282
12283
12284
12285
12286
12287
12288
12289
12290
12291
12292
12293
12294
12295
12296
12297
12298
12299
12300
12301
12302
12303
12304
12305
12306
12307
12308
12309
12310
12311
12312
12313
12314
12315
12316
12317
12318
12319
12320
12321
12322
12323
12324
12325
12326
12327
12328
12329
12330
12331
12332
12333
12334
12335
12336
12337
12338
12339
12340
12341
12342
12343
12344
12345
12346
12347
12348
12349
12350
12351
12352
12353
12354
12355
12356
12357
12358
12359
12360
12361
12362
12363
12364
12365
12366
12367
12368
12369
12370
12371
12372
12373
12374
12375
12376
12377
12378
12379
12380
12381
12382
12383
12384
12385
12386
12387
12388
12389
12390
12391
12392
12393
12394
12395
12396
12397
12398
12399
12400
12401
12402
12403
12404
12405
12406
12407
12408
12409
12410
12411
12412
12413
12414
12415
12416
12417
12418
12419
12420
12421
12422
12423
12424
12425
12426
12427
12428
12429
12430
12431
12432
12433
12434
12435
12436
12437
12438
12439
12440
12441
12442
12443
12444
12445
12446
12447
12448
12449
12450
12451
12452
12453
12454
12455
12456
12457
12458
12459
12460
12461
12462
12463
12464
12465
12466
12467
12468
12469
12470
12471
12472
12473
12474
12475
12476
12477
12478
12479
12480
12481
12482
12483
12484
12485
12486
12487
12488
12489
12490
12491
12492
12493
12494
12495
12496
12497
12498
12499
12500
12501
12502
12503
12504
12505
12506
12507
12508
12509
12510
12511
12512
12513
12514
12515
12516
12517
12518
12519
12520
12521
12522
12523
12524
12525
12526
12527
12528
12529
12530
12531
12532
12533
12534
12535
12536
12537
12538
12539
12540
12541
12542
12543
12544
12545
12546
12547
12548
12549
12550
12551
12552
12553
12554
12555
12556
12557
12558
12559
12560
12561
12562
12563
12564
12565
12566
12567
12568
12569
12570
12571
12572
12573
12574
12575
12576
12577
12578
12579
12580
12581
12582
12583
12584
12585
12586
12587
12588
12589
12590
12591
12592
12593
12594
12595
12596
12597
12598
12599
12600
12601
12602
12603
12604
12605
12606
12607
12608
12609
12610
12611
12612
12613
12614
12615
12616
12617
12618
12619
12620
12621
12622
12623
12624
12625
12626
12627
12628
12629
12630
12631
12632
12633
12634
12635
12636
12637
12638
12639
12640
12641
12642
12643
12644
12645
12646
12647
12648
12649
12650
12651
12652
12653
12654
12655
12656
12657
12658
12659
12660
12661
12662
12663
12664
12665
12666
12667
12668
12669
12670
12671
12672
12673
12674
12675
12676
12677
12678
12679
12680
12681
12682
12683
12684
12685
12686
12687
12688
12689
12690
12691
12692
12693
12694
12695
12696
12697
12698
12699
12700
12701
12702
12703
12704
12705
12706
12707
12708
12709
12710
12711
12712
12713
12714
12715
12716
12717
12718
12719
12720
12721
12722
12723
12724
12725
12726
12727
12728
12729
12730
12731
12732
12733
12734
12735
12736
12737
12738
12739
12740
12741
12742
12743
12744
12745
12746
12747
12748
12749
12750
12751
12752
12753
12754
12755
12756
12757
12758
12759
12760
12761
12762
12763
12764
12765
12766
12767
12768
12769
12770
12771
12772
12773
12774
12775
12776
12777
12778
12779
12780
12781
12782
12783
12784
12785
12786
12787
12788
12789
12790
12791
12792
12793
12794
12795
12796
12797
12798
12799
12800
12801
12802
12803
12804
12805
12806
12807
12808
12809
12810
12811
12812
12813
12814
12815
12816
12817
12818
12819
12820
12821
12822
12823
12824
12825
12826
12827
12828
12829
12830
12831
12832
12833
12834
12835
12836
12837
12838
12839
12840
12841
12842
12843
12844
12845
12846
12847
12848
12849
12850
12851
12852
12853
12854
12855
12856
12857
12858
12859
12860
12861
12862
12863
12864
12865
12866
12867
12868
12869
12870
12871
12872
12873
12874
12875
12876
12877
12878
12879
12880
12881
12882
12883
12884
12885
12886
12887
12888
12889
12890
12891
12892
12893
12894
12895
12896
12897
12898
12899
12900
12901
12902
12903
12904
12905
12906
12907
12908
12909
12910
12911
12912
12913
12914
12915
12916
12917
12918
12919
12920
12921
12922
12923
12924
12925
12926
12927
12928
12929
12930
12931
12932
12933
12934
12935
12936
12937
12938
12939
12940
12941
12942
12943
12944
12945
12946
12947
12948
12949
12950
12951
12952
12953
12954
12955
12956
12957
12958
12959
12960
12961
12962
12963
12964
12965
12966
12967
12968
12969
12970
12971
12972
12973
12974
12975
12976
12977
12978
12979
12980
12981
12982
12983
12984
12985
12986
12987
12988
12989
12990
12991
12992
12993
12994
12995
12996
12997
12998
12999
13000
13001
13002
13003
13004
13005
13006
13007
13008
13009
13010
13011
13012
13013
13014
13015
13016
13017
13018
13019
13020
13021
13022
13023
13024
13025
13026
13027
13028
13029
13030
13031
13032
13033
13034
13035
13036
13037
13038
13039
13040
13041
13042
13043
13044
13045
13046
13047
13048
13049
13050
13051
13052
13053
13054
13055
13056
13057
13058
13059
13060
13061
13062
13063
13064
13065
13066
13067
13068
13069
13070
13071
13072
13073
13074
13075
13076
13077
13078
13079
13080
13081
13082
13083
13084
13085
13086
13087
13088
13089
13090
13091
13092
13093
13094
13095
13096
13097
13098
13099
13100
13101
13102
13103
13104
13105
13106
13107
13108
13109
13110
13111
13112
13113
13114
13115
13116
13117
13118
13119
13120
13121
13122
13123
13124
13125
13126
13127
13128
13129
13130
13131
13132
13133
13134
13135
13136
13137
13138
13139
13140
13141
13142
13143
13144
13145
13146
13147
13148
13149
13150
13151
13152
13153
13154
13155
13156
13157
13158
13159
13160
13161
13162
13163
13164
13165
13166
13167
13168
13169
13170
13171
13172
13173
13174
13175
13176
13177
13178
13179
13180
13181
13182
13183
13184
13185
13186
13187
13188
13189
13190
13191
13192
13193
13194
13195
13196
13197
13198
13199
13200
13201
13202
13203
13204
13205
13206
13207
13208
13209
13210
13211
13212
13213
13214
13215
13216
13217
13218
13219
13220
13221
13222
13223
13224
13225
13226
13227
13228
13229
13230
13231
13232
13233
13234
13235
13236
13237
13238
13239
13240
13241
13242
13243
13244
13245
13246
13247
13248
13249
13250
13251
13252
13253
13254
13255
13256
13257
13258
13259
13260
13261
13262
13263
13264
13265
13266
13267
13268
13269
13270
13271
13272
13273
13274
13275
13276
13277
13278
13279
13280
13281
13282
13283
13284
13285
13286
13287
13288
13289
13290
13291
13292
13293
13294
13295
13296
13297
13298
13299
13300
13301
13302
13303
13304
13305
13306
13307
13308
13309
13310
13311
13312
13313
13314
13315
13316
13317
13318
13319
13320
13321
13322
13323
13324
13325
13326
13327
13328
13329
13330
13331
13332
13333
13334
13335
13336
13337
13338
13339
13340
13341
13342
13343
13344
13345
13346
13347
13348
13349
13350
13351
13352
13353
13354
13355
13356
13357
13358
13359
13360
13361
13362
13363
13364
13365
13366
13367
13368
13369
13370
13371
13372
13373
13374
13375
13376
13377
13378
13379
13380
13381
13382
13383
13384
13385
13386
13387
13388
13389
13390
13391
13392
13393
13394
13395
13396
13397
13398
13399
13400
13401
13402
13403
13404
13405
13406
13407
13408
13409
13410
13411
13412
13413
13414
13415
13416
13417
13418
13419
13420
13421
13422
13423
13424
13425
13426
13427
13428
13429
13430
13431
13432
13433
13434
13435
13436
13437
13438
13439
13440
13441
13442
13443
13444
13445
13446
13447
13448
13449
13450
13451
13452
13453
13454
13455
13456
13457
13458
13459
13460
13461
13462
13463
13464
13465
13466
13467
13468
13469
13470
13471
13472
13473
13474
13475
13476
13477
13478
13479
13480
13481
13482
13483
13484
13485
13486
13487
13488
13489
13490
13491
13492
13493
13494
13495
13496
13497
13498
13499
13500
13501
13502
13503
13504
13505
13506
13507
13508
13509
13510
13511
13512
13513
13514
13515
13516
13517
13518
13519
13520
13521
13522
13523
13524
13525
13526
13527
13528
13529
13530
13531
13532
13533
13534
13535
13536
13537
13538
13539
13540
13541
13542
13543
13544
13545
13546
13547
13548
13549
13550
13551
13552
13553
13554
13555
13556
13557
13558
13559
13560
13561
13562
13563
13564
13565
13566
13567
13568
13569
13570
13571
13572
13573
13574
13575
13576
13577
13578
13579
13580
13581
13582
13583
13584
13585
13586
13587
13588
13589
13590
13591
13592
13593
13594
13595
13596
13597
13598
13599
13600
13601
13602
13603
13604
13605
13606
13607
13608
13609
13610
13611
13612
13613
13614
13615
13616
13617
13618
13619
13620
13621
13622
13623
13624
13625
13626
13627
13628
13629
13630
13631
13632
13633
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/falcon/gpon_reg_base.h
@@ -0,0 +1,376 @@
+/******************************************************************************
+
+                               Copyright (c) 2010
+                            Lantiq Deutschland GmbH
+
+  For licensing information, see the file 'LICENSE' in the root folder of
+  this software module.
+
+******************************************************************************/
+
+#ifndef _gpon_reg_base_h
+#define _gpon_reg_base_h
+
+/** \addtogroup GPON_BASE
+   @{
+*/
+
+#ifndef KSEG1
+#define KSEG1 0xA0000000
+#endif
+
+/** address range for ebu
+    0x18000000--0x180000FF */
+#define GPON_EBU_BASE		(KSEG1 | 0x18000000)
+#define GPON_EBU_END		(KSEG1 | 0x180000FF)
+#define GPON_EBU_SIZE		0x00000100
+/** address range for gpearb
+    0x1D400100--0x1D4001FF */
+#define GPON_GPEARB_BASE		(KSEG1 | 0x1D400100)
+#define GPON_GPEARB_END		(KSEG1 | 0x1D4001FF)
+#define GPON_GPEARB_SIZE		0x00000100
+/** address range for tmu
+    0x1D404000--0x1D404FFF */
+#define GPON_TMU_BASE		(KSEG1 | 0x1D404000)
+#define GPON_TMU_END		(KSEG1 | 0x1D404FFF)
+#define GPON_TMU_SIZE		0x00001000
+/** address range for iqm
+    0x1D410000--0x1D41FFFF */
+#define GPON_IQM_BASE		(KSEG1 | 0x1D410000)
+#define GPON_IQM_END		(KSEG1 | 0x1D41FFFF)
+#define GPON_IQM_SIZE		0x00010000
+/** address range for octrlg
+    0x1D420000--0x1D42FFFF */
+#define GPON_OCTRLG_BASE		(KSEG1 | 0x1D420000)
+#define GPON_OCTRLG_END		(KSEG1 | 0x1D42FFFF)
+#define GPON_OCTRLG_SIZE		0x00010000
+/** address range for octrll0
+    0x1D440000--0x1D4400FF */
+#define GPON_OCTRLL0_BASE		(KSEG1 | 0x1D440000)
+#define GPON_OCTRLL0_END		(KSEG1 | 0x1D4400FF)
+#define GPON_OCTRLL0_SIZE		0x00000100
+/** address range for octrll1
+    0x1D440100--0x1D4401FF */
+#define GPON_OCTRLL1_BASE		(KSEG1 | 0x1D440100)
+#define GPON_OCTRLL1_END		(KSEG1 | 0x1D4401FF)
+#define GPON_OCTRLL1_SIZE		0x00000100
+/** address range for octrll2
+    0x1D440200--0x1D4402FF */
+#define GPON_OCTRLL2_BASE		(KSEG1 | 0x1D440200)
+#define GPON_OCTRLL2_END		(KSEG1 | 0x1D4402FF)
+#define GPON_OCTRLL2_SIZE		0x00000100
+/** address range for octrll3
+    0x1D440300--0x1D4403FF */
+#define GPON_OCTRLL3_BASE		(KSEG1 | 0x1D440300)
+#define GPON_OCTRLL3_END		(KSEG1 | 0x1D4403FF)
+#define GPON_OCTRLL3_SIZE		0x00000100
+/** address range for octrlc
+    0x1D441000--0x1D4410FF */
+#define GPON_OCTRLC_BASE		(KSEG1 | 0x1D441000)
+#define GPON_OCTRLC_END		(KSEG1 | 0x1D4410FF)
+#define GPON_OCTRLC_SIZE		0x00000100
+/** address range for ictrlg
+    0x1D450000--0x1D45FFFF */
+#define GPON_ICTRLG_BASE		(KSEG1 | 0x1D450000)
+#define GPON_ICTRLG_END		(KSEG1 | 0x1D45FFFF)
+#define GPON_ICTRLG_SIZE		0x00010000
+/** address range for ictrll0
+    0x1D460000--0x1D4601FF */
+#define GPON_ICTRLL0_BASE		(KSEG1 | 0x1D460000)
+#define GPON_ICTRLL0_END		(KSEG1 | 0x1D4601FF)
+#define GPON_ICTRLL0_SIZE		0x00000200
+/** address range for ictrll1
+    0x1D460200--0x1D4603FF */
+#define GPON_ICTRLL1_BASE		(KSEG1 | 0x1D460200)
+#define GPON_ICTRLL1_END		(KSEG1 | 0x1D4603FF)
+#define GPON_ICTRLL1_SIZE		0x00000200
+/** address range for ictrll2
+    0x1D460400--0x1D4605FF */
+#define GPON_ICTRLL2_BASE		(KSEG1 | 0x1D460400)
+#define GPON_ICTRLL2_END		(KSEG1 | 0x1D4605FF)
+#define GPON_ICTRLL2_SIZE		0x00000200
+/** address range for ictrll3
+    0x1D460600--0x1D4607FF */
+#define GPON_ICTRLL3_BASE		(KSEG1 | 0x1D460600)
+#define GPON_ICTRLL3_END		(KSEG1 | 0x1D4607FF)
+#define GPON_ICTRLL3_SIZE		0x00000200
+/** address range for ictrlc0
+    0x1D461000--0x1D4610FF */
+#define GPON_ICTRLC0_BASE		(KSEG1 | 0x1D461000)
+#define GPON_ICTRLC0_END		(KSEG1 | 0x1D4610FF)
+#define GPON_ICTRLC0_SIZE		0x00000100
+/** address range for ictrlc1
+    0x1D461100--0x1D4611FF */
+#define GPON_ICTRLC1_BASE		(KSEG1 | 0x1D461100)
+#define GPON_ICTRLC1_END		(KSEG1 | 0x1D4611FF)
+#define GPON_ICTRLC1_SIZE		0x00000100
+/** address range for fsqm
+    0x1D500000--0x1D5FFFFF */
+#define GPON_FSQM_BASE		(KSEG1 | 0x1D500000)
+#define GPON_FSQM_END		(KSEG1 | 0x1D5FFFFF)
+#define GPON_FSQM_SIZE		0x00100000
+/** address range for pctrl
+    0x1D600000--0x1D6001FF */
+#define GPON_PCTRL_BASE		(KSEG1 | 0x1D600000)
+#define GPON_PCTRL_END		(KSEG1 | 0x1D6001FF)
+#define GPON_PCTRL_SIZE		0x00000200
+/** address range for link0
+    0x1D600200--0x1D6002FF */
+#define GPON_LINK0_BASE		(KSEG1 | 0x1D600200)
+#define GPON_LINK0_END		(KSEG1 | 0x1D6002FF)
+#define GPON_LINK0_SIZE		0x00000100
+/** address range for link1
+    0x1D600300--0x1D6003FF */
+#define GPON_LINK1_BASE		(KSEG1 | 0x1D600300)
+#define GPON_LINK1_END		(KSEG1 | 0x1D6003FF)
+#define GPON_LINK1_SIZE		0x00000100
+/** address range for link2
+    0x1D600400--0x1D6004FF */
+#define GPON_LINK2_BASE		(KSEG1 | 0x1D600400)
+#define GPON_LINK2_END		(KSEG1 | 0x1D6004FF)
+#define GPON_LINK2_SIZE		0x00000100
+/** address range for disp
+    0x1D600500--0x1D6005FF */
+#define GPON_DISP_BASE		(KSEG1 | 0x1D600500)
+#define GPON_DISP_END		(KSEG1 | 0x1D6005FF)
+#define GPON_DISP_SIZE		0x00000100
+/** address range for merge
+    0x1D600600--0x1D6006FF */
+#define GPON_MERGE_BASE		(KSEG1 | 0x1D600600)
+#define GPON_MERGE_END		(KSEG1 | 0x1D6006FF)
+#define GPON_MERGE_SIZE		0x00000100
+/** address range for tbm
+    0x1D600700--0x1D6007FF */
+#define GPON_TBM_BASE		(KSEG1 | 0x1D600700)
+#define GPON_TBM_END		(KSEG1 | 0x1D6007FF)
+#define GPON_TBM_SIZE		0x00000100
+/** address range for pe0
+    0x1D610000--0x1D61FFFF */
+#define GPON_PE0_BASE		(KSEG1 | 0x1D610000)
+#define GPON_PE0_END		(KSEG1 | 0x1D61FFFF)
+#define GPON_PE0_SIZE		0x00010000
+/** address range for pe1
+    0x1D620000--0x1D62FFFF */
+#define GPON_PE1_BASE		(KSEG1 | 0x1D620000)
+#define GPON_PE1_END		(KSEG1 | 0x1D62FFFF)
+#define GPON_PE1_SIZE		0x00010000
+/** address range for pe2
+    0x1D630000--0x1D63FFFF */
+#define GPON_PE2_BASE		(KSEG1 | 0x1D630000)
+#define GPON_PE2_END		(KSEG1 | 0x1D63FFFF)
+#define GPON_PE2_SIZE		0x00010000
+/** address range for pe3
+    0x1D640000--0x1D64FFFF */
+#define GPON_PE3_BASE		(KSEG1 | 0x1D640000)
+#define GPON_PE3_END		(KSEG1 | 0x1D64FFFF)
+#define GPON_PE3_SIZE		0x00010000
+/** address range for pe4
+    0x1D650000--0x1D65FFFF */
+#define GPON_PE4_BASE		(KSEG1 | 0x1D650000)
+#define GPON_PE4_END		(KSEG1 | 0x1D65FFFF)
+#define GPON_PE4_SIZE		0x00010000
+/** address range for pe5
+    0x1D660000--0x1D66FFFF */
+#define GPON_PE5_BASE		(KSEG1 | 0x1D660000)
+#define GPON_PE5_END		(KSEG1 | 0x1D66FFFF)
+#define GPON_PE5_SIZE		0x00010000
+/** address range for sys_gpe
+    0x1D700000--0x1D7000FF */
+#define GPON_SYS_GPE_BASE		(KSEG1 | 0x1D700000)
+#define GPON_SYS_GPE_END		(KSEG1 | 0x1D7000FF)
+#define GPON_SYS_GPE_SIZE		0x00000100
+/** address range for eim
+    0x1D800000--0x1D800FFF */
+#define GPON_EIM_BASE		(KSEG1 | 0x1D800000)
+#define GPON_EIM_END		(KSEG1 | 0x1D800FFF)
+#define GPON_EIM_SIZE		0x00001000
+/** address range for sxgmii
+    0x1D808800--0x1D8088FF */
+#define GPON_SXGMII_BASE		(KSEG1 | 0x1D808800)
+#define GPON_SXGMII_END		(KSEG1 | 0x1D8088FF)
+#define GPON_SXGMII_SIZE		0x00000100
+/** address range for sgmii
+    0x1D808C00--0x1D808CFF */
+#define GPON_SGMII_BASE		(KSEG1 | 0x1D808C00)
+#define GPON_SGMII_END		(KSEG1 | 0x1D808CFF)
+#define GPON_SGMII_SIZE		0x00000100
+/** address range for gpio0
+    0x1D810000--0x1D81007F */
+#define GPON_GPIO0_BASE		(KSEG1 | 0x1D810000)
+#define GPON_GPIO0_END		(KSEG1 | 0x1D81007F)
+#define GPON_GPIO0_SIZE		0x00000080
+/** address range for gpio2
+    0x1D810100--0x1D81017F */
+#define GPON_GPIO2_BASE		(KSEG1 | 0x1D810100)
+#define GPON_GPIO2_END		(KSEG1 | 0x1D81017F)
+#define GPON_GPIO2_SIZE		0x00000080
+/** address range for sys_eth
+    0x1DB00000--0x1DB000FF */
+#define GPON_SYS_ETH_BASE		(KSEG1 | 0x1DB00000)
+#define GPON_SYS_ETH_END		(KSEG1 | 0x1DB000FF)
+#define GPON_SYS_ETH_SIZE		0x00000100
+/** address range for padctrl0
+    0x1DB01000--0x1DB010FF */
+#define GPON_PADCTRL0_BASE		(KSEG1 | 0x1DB01000)
+#define GPON_PADCTRL0_END		(KSEG1 | 0x1DB010FF)
+#define GPON_PADCTRL0_SIZE		0x00000100
+/** address range for padctrl2
+    0x1DB02000--0x1DB020FF */
+#define GPON_PADCTRL2_BASE		(KSEG1 | 0x1DB02000)
+#define GPON_PADCTRL2_END		(KSEG1 | 0x1DB020FF)
+#define GPON_PADCTRL2_SIZE		0x00000100
+/** address range for gtc
+    0x1DC05000--0x1DC052D4 */
+#define GPON_GTC_BASE		(KSEG1 | 0x1DC05000)
+#define GPON_GTC_END		(KSEG1 | 0x1DC052D4)
+#define GPON_GTC_SIZE		0x000002D5
+/** address range for pma
+    0x1DD00000--0x1DD003FF */
+#define GPON_PMA_BASE		(KSEG1 | 0x1DD00000)
+#define GPON_PMA_END		(KSEG1 | 0x1DD003FF)
+#define GPON_PMA_SIZE		0x00000400
+/** address range for fcsic
+    0x1DD00600--0x1DD0061F */
+#define GPON_FCSIC_BASE		(KSEG1 | 0x1DD00600)
+#define GPON_FCSIC_END		(KSEG1 | 0x1DD0061F)
+#define GPON_FCSIC_SIZE		0x00000020
+/** address range for pma_int200
+    0x1DD00700--0x1DD0070F */
+#define GPON_PMA_INT200_BASE		(KSEG1 | 0x1DD00700)
+#define GPON_PMA_INT200_END		(KSEG1 | 0x1DD0070F)
+#define GPON_PMA_INT200_SIZE		0x00000010
+/** address range for pma_inttx
+    0x1DD00720--0x1DD0072F */
+#define GPON_PMA_INTTX_BASE		(KSEG1 | 0x1DD00720)
+#define GPON_PMA_INTTX_END		(KSEG1 | 0x1DD0072F)
+#define GPON_PMA_INTTX_SIZE		0x00000010
+/** address range for pma_intrx
+    0x1DD00740--0x1DD0074F */
+#define GPON_PMA_INTRX_BASE		(KSEG1 | 0x1DD00740)
+#define GPON_PMA_INTRX_END		(KSEG1 | 0x1DD0074F)
+#define GPON_PMA_INTRX_SIZE		0x00000010
+/** address range for gtc_pma
+    0x1DEFFF00--0x1DEFFFFF */
+#define GPON_GTC_PMA_BASE		(KSEG1 | 0x1DEFFF00)
+#define GPON_GTC_PMA_END		(KSEG1 | 0x1DEFFFFF)
+#define GPON_GTC_PMA_SIZE		0x00000100
+/** address range for sys
+    0x1DF00000--0x1DF000FF */
+#define GPON_SYS_BASE		(KSEG1 | 0x1DF00000)
+#define GPON_SYS_END		(KSEG1 | 0x1DF000FF)
+#define GPON_SYS_SIZE		0x00000100
+/** address range for asc1
+    0x1E100B00--0x1E100BFF */
+#define GPON_ASC1_BASE		(KSEG1 | 0x1E100B00)
+#define GPON_ASC1_END		(KSEG1 | 0x1E100BFF)
+#define GPON_ASC1_SIZE		0x00000100
+/** address range for asc0
+    0x1E100C00--0x1E100CFF */
+#define GPON_ASC0_BASE		(KSEG1 | 0x1E100C00)
+#define GPON_ASC0_END		(KSEG1 | 0x1E100CFF)
+#define GPON_ASC0_SIZE		0x00000100
+/** address range for i2c
+    0x1E200000--0x1E20FFFF */
+#define GPON_I2C_BASE		(KSEG1 | 0x1E200000)
+#define GPON_I2C_END		(KSEG1 | 0x1E20FFFF)
+#define GPON_I2C_SIZE		0x00010000
+/** address range for gpio1
+    0x1E800100--0x1E80017F */
+#define GPON_GPIO1_BASE		(KSEG1 | 0x1E800100)
+#define GPON_GPIO1_END		(KSEG1 | 0x1E80017F)
+#define GPON_GPIO1_SIZE		0x00000080
+/** address range for gpio3
+    0x1E800200--0x1E80027F */
+#define GPON_GPIO3_BASE		(KSEG1 | 0x1E800200)
+#define GPON_GPIO3_END		(KSEG1 | 0x1E80027F)
+#define GPON_GPIO3_SIZE		0x00000080
+/** address range for gpio4
+    0x1E800300--0x1E80037F */
+#define GPON_GPIO4_BASE		(KSEG1 | 0x1E800300)
+#define GPON_GPIO4_END		(KSEG1 | 0x1E80037F)
+#define GPON_GPIO4_SIZE		0x00000080
+/** address range for padctrl1
+    0x1E800400--0x1E8004FF */
+#define GPON_PADCTRL1_BASE		(KSEG1 | 0x1E800400)
+#define GPON_PADCTRL1_END		(KSEG1 | 0x1E8004FF)
+#define GPON_PADCTRL1_SIZE		0x00000100
+/** address range for padctrl3
+    0x1E800500--0x1E8005FF */
+#define GPON_PADCTRL3_BASE		(KSEG1 | 0x1E800500)
+#define GPON_PADCTRL3_END		(KSEG1 | 0x1E8005FF)
+#define GPON_PADCTRL3_SIZE		0x00000100
+/** address range for padctrl4
+    0x1E800600--0x1E8006FF */
+#define GPON_PADCTRL4_BASE		(KSEG1 | 0x1E800600)
+#define GPON_PADCTRL4_END		(KSEG1 | 0x1E8006FF)
+#define GPON_PADCTRL4_SIZE		0x00000100
+/** address range for status
+    0x1E802000--0x1E80207F */
+#define GPON_STATUS_BASE		(KSEG1 | 0x1E802000)
+#define GPON_STATUS_END		(KSEG1 | 0x1E80207F)
+#define GPON_STATUS_SIZE		0x00000080
+/** address range for dcdc_1v0
+    0x1E803000--0x1E8033FF */
+#define GPON_DCDC_1V0_BASE		(KSEG1 | 0x1E803000)
+#define GPON_DCDC_1V0_END		(KSEG1 | 0x1E8033FF)
+#define GPON_DCDC_1V0_SIZE		0x00000400
+/** address range for dcdc_ddr
+    0x1E804000--0x1E8043FF */
+#define GPON_DCDC_DDR_BASE		(KSEG1 | 0x1E804000)
+#define GPON_DCDC_DDR_END		(KSEG1 | 0x1E8043FF)
+#define GPON_DCDC_DDR_SIZE		0x00000400
+/** address range for dcdc_apd
+    0x1E805000--0x1E8053FF */
+#define GPON_DCDC_APD_BASE		(KSEG1 | 0x1E805000)
+#define GPON_DCDC_APD_END		(KSEG1 | 0x1E8053FF)
+#define GPON_DCDC_APD_SIZE		0x00000400
+/** address range for sys1
+    0x1EF00000--0x1EF000FF */
+#define GPON_SYS1_BASE		(KSEG1 | 0x1EF00000)
+#define GPON_SYS1_END		(KSEG1 | 0x1EF000FF)
+#define GPON_SYS1_SIZE		0x00000100
+/** address range for sbs0ctrl
+    0x1F080000--0x1F0801FF */
+#define GPON_SBS0CTRL_BASE		(KSEG1 | 0x1F080000)
+#define GPON_SBS0CTRL_END		(KSEG1 | 0x1F0801FF)
+#define GPON_SBS0CTRL_SIZE		0x00000200
+/** address range for sbs0red
+    0x1F080200--0x1F08027F */
+#define GPON_SBS0RED_BASE		(KSEG1 | 0x1F080200)
+#define GPON_SBS0RED_END		(KSEG1 | 0x1F08027F)
+#define GPON_SBS0RED_SIZE		0x00000080
+/** address range for sbs0ram
+    0x1F200000--0x1F32FFFF */
+#define GPON_SBS0RAM_BASE		(KSEG1 | 0x1F200000)
+#define GPON_SBS0RAM_END		(KSEG1 | 0x1F32FFFF)
+#define GPON_SBS0RAM_SIZE		0x00130000
+/** address range for ddrdb
+    0x1F701000--0x1F701FFF */
+#define GPON_DDRDB_BASE		(KSEG1 | 0x1F701000)
+#define GPON_DDRDB_END		(KSEG1 | 0x1F701FFF)
+#define GPON_DDRDB_SIZE		0x00001000
+/** address range for sbiu
+    0x1F880000--0x1F8800FF */
+#define GPON_SBIU_BASE		(KSEG1 | 0x1F880000)
+#define GPON_SBIU_END		(KSEG1 | 0x1F8800FF)
+#define GPON_SBIU_SIZE		0x00000100
+/** address range for icu0
+    0x1F880200--0x1F8802DF */
+#define GPON_ICU0_BASE		(KSEG1 | 0x1F880200)
+#define GPON_ICU0_END		(KSEG1 | 0x1F8802DF)
+#define GPON_ICU0_SIZE		0x000000E0
+/** address range for icu1
+    0x1F880300--0x1F8803DF */
+#define GPON_ICU1_BASE		(KSEG1 | 0x1F880300)
+#define GPON_ICU1_END		(KSEG1 | 0x1F8803DF)
+#define GPON_ICU1_SIZE		0x000000E0
+/** address range for wdt
+    0x1F8803F0--0x1F8803FF */
+#define GPON_WDT_BASE		(KSEG1 | 0x1F8803F0)
+#define GPON_WDT_END		(KSEG1 | 0x1F8803FF)
+#define GPON_WDT_SIZE		0x00000010
+
+/*! @} */ /* GPON_BASE */
+
+#endif /* _gpon_reg_base_h */
+
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/falcon/i2c_reg.h
@@ -0,0 +1,830 @@
+/******************************************************************************
+
+                               Copyright (c) 2010
+                            Lantiq Deutschland GmbH
+
+  For licensing information, see the file 'LICENSE' in the root folder of
+  this software module.
+
+******************************************************************************/
+
+#ifndef _i2c_reg_h
+#define _i2c_reg_h
+
+/** \addtogroup I2C_REGISTER
+   @{
+*/
+/* access macros */
+#define i2c_r32(reg) reg_r32(&i2c->reg)
+#define i2c_w32(val, reg) reg_w32(val, &i2c->reg)
+#define i2c_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &i2c->reg)
+#define i2c_r32_table(reg, idx) reg_r32_table(i2c->reg, idx)
+#define i2c_w32_table(val, reg, idx) reg_w32_table(val, i2c->reg, idx)
+#define i2c_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, i2c->reg, idx)
+#define i2c_adr_table(reg, idx) adr_table(i2c->reg, idx)
+
+
+/** I2C register structure */
+struct gpon_reg_i2c
+{
+   /** I2C Kernel Clock Control Register */
+   unsigned int clc; /* 0x00000000 */
+   /** Reserved */
+   unsigned int res_0; /* 0x00000004 */
+   /** I2C Identification Register */
+   unsigned int id; /* 0x00000008 */
+   /** Reserved */
+   unsigned int res_1; /* 0x0000000C */
+   /** I2C RUN Control Register
+       This register enables and disables the I2C peripheral. Before enabling, the I2C has to be configured properly. After enabling no configuration is possible */
+   unsigned int run_ctrl; /* 0x00000010 */
+   /** I2C End Data Control Register
+       This register is used to either turn around the data transmission direction or to address another slave without sending a stop condition. Also the software can stop the slave-transmitter by sending a not-accolade when working as master-receiver or even stop data transmission immediately when operating as master-transmitter. The writing to the bits of this control register is only effective when in MASTER RECEIVES BYTES, MASTER TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state */
+   unsigned int endd_ctrl; /* 0x00000014 */
+   /** I2C Fractional Divider Configuration Register
+       These register is used to program the fractional divider of the I2C bus. Before the peripheral is switched on by setting the RUN-bit the two (fixed) values for the two operating frequencies are programmed into these (configuration) registers. The Register FDIV_HIGH_CFG has the same layout as I2C_FDIV_CFG. */
+   unsigned int fdiv_cfg; /* 0x00000018 */
+   /** I2C Fractional Divider (highspeed mode) Configuration Register
+       These register is used to program the fractional divider of the I2C bus. Before the peripheral is switched on by setting the RUN-bit the two (fixed) values for the two operating frequencies are programmed into these (configuration) registers. The Register FDIV_CFG has the same layout as I2C_FDIV_CFG. */
+   unsigned int fdiv_high_cfg; /* 0x0000001C */
+   /** I2C Address Configuration Register */
+   unsigned int addr_cfg; /* 0x00000020 */
+   /** I2C Bus Status Register
+       This register gives a status information of the I2C. This additional information can be used by the software to start proper actions. */
+   unsigned int bus_stat; /* 0x00000024 */
+   /** I2C FIFO Configuration Register */
+   unsigned int fifo_cfg; /* 0x00000028 */
+   /** I2C Maximum Received Packet Size Register */
+   unsigned int mrps_ctrl; /* 0x0000002C */
+   /** I2C Received Packet Size Status Register */
+   unsigned int rps_stat; /* 0x00000030 */
+   /** I2C Transmit Packet Size Register */
+   unsigned int tps_ctrl; /* 0x00000034 */
+   /** I2C Filled FIFO Stages Status Register */
+   unsigned int ffs_stat; /* 0x00000038 */
+   /** Reserved */
+   unsigned int res_2; /* 0x0000003C */
+   /** I2C Timing Configuration Register */
+   unsigned int tim_cfg; /* 0x00000040 */
+   /** Reserved */
+   unsigned int res_3[7]; /* 0x00000044 */
+   /** I2C Error Interrupt Request Source Mask Register */
+   unsigned int err_irqsm; /* 0x00000060 */
+   /** I2C Error Interrupt Request Source Status Register */
+   unsigned int err_irqss; /* 0x00000064 */
+   /** I2C Error Interrupt Request Source Clear Register */
+   unsigned int err_irqsc; /* 0x00000068 */
+   /** Reserved */
+   unsigned int res_4; /* 0x0000006C */
+   /** I2C Protocol Interrupt Request Source Mask Register */
+   unsigned int p_irqsm; /* 0x00000070 */
+   /** I2C Protocol Interrupt Request Source Status Register */
+   unsigned int p_irqss; /* 0x00000074 */
+   /** I2C Protocol Interrupt Request Source Clear Register */
+   unsigned int p_irqsc; /* 0x00000078 */
+   /** Reserved */
+   unsigned int res_5; /* 0x0000007C */
+   /** I2C Raw Interrupt Status Register */
+   unsigned int ris; /* 0x00000080 */
+   /** I2C Interrupt Mask Control Register */
+   unsigned int imsc; /* 0x00000084 */
+   /** I2C Masked Interrupt Status Register */
+   unsigned int mis; /* 0x00000088 */
+   /** I2C Interrupt Clear Register */
+   unsigned int icr; /* 0x0000008C */
+   /** I2C Interrupt Set Register */
+   unsigned int isr; /* 0x00000090 */
+   /** I2C DMA Enable Register */
+   unsigned int dmae; /* 0x00000094 */
+   /** Reserved */
+   unsigned int res_6[8154]; /* 0x00000098 */
+   /** I2C Transmit Data Register */
+   unsigned int txd; /* 0x00008000 */
+   /** Reserved */
+   unsigned int res_7[4095]; /* 0x00008004 */
+   /** I2C Receive Data Register */
+   unsigned int rxd; /* 0x0000C000 */
+   /** Reserved */
+   unsigned int res_8[4095]; /* 0x0000C004 */
+};
+
+
+/* Fields of "I2C Kernel Clock Control Register" */
+/** Clock Divider for Optional Run Mode (AHB peripherals)
+    Max 8-bit divider value. Note: As long as the new divider value ORMC is not valid, the register returns 0x0000 00xx on reading. */
+#define I2C_CLC_ORMC_MASK 0x00FF0000
+/** field offset */
+#define I2C_CLC_ORMC_OFFSET 16
+/** Clock Divider for Normal Run Mode
+    Max 8-bit divider value. IF RMC is 0 the module is disabled. Note: As long as the new divider value RMC is not valid, the register returns 0x0000 00xx on reading. */
+#define I2C_CLC_RMC_MASK 0x0000FF00
+/** field offset */
+#define I2C_CLC_RMC_OFFSET 8
+/** Fast Shut-Off Enable Bit */
+#define I2C_CLC_FSOE 0x00000020
+/* Disable
+#define I2C_CLC_FSOE_DIS 0x00000000 */
+/** Enable */
+#define I2C_CLC_FSOE_EN 0x00000020
+/** Suspend Bit Write Enable for OCDS */
+#define I2C_CLC_SBWE 0x00000010
+/* Disable
+#define I2C_CLC_SBWE_DIS 0x00000000 */
+/** Enable */
+#define I2C_CLC_SBWE_EN 0x00000010
+/** Disable External Request Disable */
+#define I2C_CLC_EDIS 0x00000008
+/* Enable
+#define I2C_CLC_EDIS_EN 0x00000000 */
+/** Disable */
+#define I2C_CLC_EDIS_DIS 0x00000008
+/** Suspend Enable Bit for OCDS */
+#define I2C_CLC_SPEN 0x00000004
+/* Disable
+#define I2C_CLC_SPEN_DIS 0x00000000 */
+/** Enable */
+#define I2C_CLC_SPEN_EN 0x00000004
+/** Disable Status Bit
+    Bit DISS can be modified only by writing to bit DISR */
+#define I2C_CLC_DISS 0x00000002
+/* Enable
+#define I2C_CLC_DISS_EN 0x00000000 */
+/** Disable */
+#define I2C_CLC_DISS_DIS 0x00000002
+/** Disable Request Bit */
+#define I2C_CLC_DISR 0x00000001
+/* Module disable not requested
+#define I2C_CLC_DISR_OFF 0x00000000 */
+/** Module disable requested */
+#define I2C_CLC_DISR_ON 0x00000001
+
+/* Fields of "I2C Identification Register" */
+/** Module ID */
+#define I2C_ID_ID_MASK 0x0000FF00
+/** field offset */
+#define I2C_ID_ID_OFFSET 8
+/** Revision */
+#define I2C_ID_REV_MASK 0x000000FF
+/** field offset */
+#define I2C_ID_REV_OFFSET 0
+
+/* Fields of "I2C RUN Control Register" */
+/** Enabling I2C Interface
+    Only when this bit is set to zero, the configuration registers of the I2C peripheral are writable by SW. */
+#define I2C_RUN_CTRL_RUN 0x00000001
+/* Disable
+#define I2C_RUN_CTRL_RUN_DIS 0x00000000 */
+/** Enable */
+#define I2C_RUN_CTRL_RUN_EN 0x00000001
+
+/* Fields of "I2C End Data Control Register" */
+/** Set End of Transmission
+    Note:Do not write '1' to this bit when bus is free. This will cause an abort after the first byte when a new transfer is started. */
+#define I2C_ENDD_CTRL_SETEND 0x00000002
+/* No-Operation
+#define I2C_ENDD_CTRL_SETEND_NOP 0x00000000 */
+/** Master Receives Bytes */
+#define I2C_ENDD_CTRL_SETEND_MRB 0x00000002
+/** Set Restart Condition */
+#define I2C_ENDD_CTRL_SETRSC 0x00000001
+/* No-Operation
+#define I2C_ENDD_CTRL_SETRSC_NOP 0x00000000 */
+/** Master Restart */
+#define I2C_ENDD_CTRL_SETRSC_RESTART 0x00000001
+
+/* Fields of "I2C Fractional Divider Configuration Register" */
+/** Decrement Value of fractional divider */
+#define I2C_FDIV_CFG_INC_MASK 0x00FF0000
+/** field offset */
+#define I2C_FDIV_CFG_INC_OFFSET 16
+/** Increment Value of fractional divider */
+#define I2C_FDIV_CFG_DEC_MASK 0x000007FF
+/** field offset */
+#define I2C_FDIV_CFG_DEC_OFFSET 0
+
+/* Fields of "I2C Fractional Divider (highspeed mode) Configuration Register" */
+/** Decrement Value of fractional divider */
+#define I2C_FDIV_HIGH_CFG_INC_MASK 0x00FF0000
+/** field offset */
+#define I2C_FDIV_HIGH_CFG_INC_OFFSET 16
+/** Increment Value of fractional divider */
+#define I2C_FDIV_HIGH_CFG_DEC_MASK 0x000007FF
+/** field offset */
+#define I2C_FDIV_HIGH_CFG_DEC_OFFSET 0
+
+/* Fields of "I2C Address Configuration Register" */
+/** Stop on Packet End
+    If device works as receiver a not acknowledge is generated in both cases. After successful transmission of a master code (during high speed mode) SOPE is not considered till a stop condition is manually generated by SETEND. */
+#define I2C_ADDR_CFG_SOPE 0x00200000
+/* Disable
+#define I2C_ADDR_CFG_SOPE_DIS 0x00000000 */
+/** Enable */
+#define I2C_ADDR_CFG_SOPE_EN 0x00200000
+/** Stop on Not Acknowledge
+    After successful transmission of a master code (during high speed mode) SONA is not considered till a stop condition is manually generated by SETEND. */
+#define I2C_ADDR_CFG_SONA 0x00100000
+/* Disable
+#define I2C_ADDR_CFG_SONA_DIS 0x00000000 */
+/** Enable */
+#define I2C_ADDR_CFG_SONA_EN 0x00100000
+/** Master Enable */
+#define I2C_ADDR_CFG_MnS 0x00080000
+/* Disable
+#define I2C_ADDR_CFG_MnS_DIS 0x00000000 */
+/** Enable */
+#define I2C_ADDR_CFG_MnS_EN 0x00080000
+/** Master Code Enable */
+#define I2C_ADDR_CFG_MCE 0x00040000
+/* Disable
+#define I2C_ADDR_CFG_MCE_DIS 0x00000000 */
+/** Enable */
+#define I2C_ADDR_CFG_MCE_EN 0x00040000
+/** General Call Enable */
+#define I2C_ADDR_CFG_GCE 0x00020000
+/* Disable
+#define I2C_ADDR_CFG_GCE_DIS 0x00000000 */
+/** Enable */
+#define I2C_ADDR_CFG_GCE_EN 0x00020000
+/** Ten Bit Address Mode */
+#define I2C_ADDR_CFG_TBAM 0x00010000
+/* 7-bit address mode enabled.
+#define I2C_ADDR_CFG_TBAM_7bit 0x00000000 */
+/** 10-bit address mode enabled. */
+#define I2C_ADDR_CFG_TBAM_10bit 0x00010000
+/** I2C Bus device address
+    This is the address of this device. (Watch out for reserved addresses by referring to Phillips Spec V2.1) This could either be a 7bit- address (bits [7:1]) or a 10bit- address (bits [9:0]). Note:The validity of the bits are in accordance with the TBAM bit. Bit-1 (Bit-0) is the LSB of the device address. */
+#define I2C_ADDR_CFG_ADR_MASK 0x000003FF
+/** field offset */
+#define I2C_ADDR_CFG_ADR_OFFSET 0
+
+/* Fields of "I2C Bus Status Register" */
+/** Read / not Write */
+#define I2C_BUS_STAT_RNW 0x00000004
+/* Write to I2C Bus.
+#define I2C_BUS_STAT_RNW_WRITE 0x00000000 */
+/** Read from I2C Bus. */
+#define I2C_BUS_STAT_RNW_READ 0x00000004
+/** Bus Status */
+#define I2C_BUS_STAT_BS_MASK 0x00000003
+/** field offset */
+#define I2C_BUS_STAT_BS_OFFSET 0
+/** I2C Bus is free. */
+#define I2C_BUS_STAT_BS_FREE 0x00000000
+/** A start condition has been detected on the bus (bus busy). */
+#define I2C_BUS_STAT_BS_SC 0x00000001
+/** The device is working as master and has claimed the control on the I2C-bus (busy master). */
+#define I2C_BUS_STAT_BS_BM 0x00000002
+/** A remote master has accessed this device as slave. */
+#define I2C_BUS_STAT_BS_RM 0x00000003
+
+/* Fields of "I2C FIFO Configuration Register" */
+/** TX FIFO Flow Control */
+#define I2C_FIFO_CFG_TXFC 0x00020000
+/* TX FIFO not as Flow Controller
+#define I2C_FIFO_CFG_TXFC_TXNFC 0x00000000 */
+/** RX FIFO Flow Control */
+#define I2C_FIFO_CFG_RXFC 0x00010000
+/* RX FIFO not as Flow Controller
+#define I2C_FIFO_CFG_RXFC_RXNFC 0x00000000 */
+/** The reset value depends on the used character sizes of the peripheral. The maximum selectable alignment depends on the maximum number of characters per stage. */
+#define I2C_FIFO_CFG_TXFA_MASK 0x00003000
+/** field offset */
+#define I2C_FIFO_CFG_TXFA_OFFSET 12
+/** Byte aligned (character alignment) */
+#define I2C_FIFO_CFG_TXFA_TXFA0 0x00000000
+/** Half word aligned (character alignment of two characters) */
+#define I2C_FIFO_CFG_TXFA_TXFA1 0x00001000
+/** Word aligned (character alignment of four characters) */
+#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000
+/** Double word aligned (character alignment of eight */
+#define I2C_FIFO_CFG_TXFA_TXFA3 0x00003000
+/** The reset value depends on the used character sizes of the peripheral. The maximum selectable alignment depends on the maximum number of characters per stage. */
+#define I2C_FIFO_CFG_RXFA_MASK 0x00000300
+/** field offset */
+#define I2C_FIFO_CFG_RXFA_OFFSET 8
+/** Byte aligned (character alignment) */
+#define I2C_FIFO_CFG_RXFA_RXFA0 0x00000000
+/** Half word aligned (character alignment of two characters) */
+#define I2C_FIFO_CFG_RXFA_RXFA1 0x00000100
+/** Word aligned (character alignment of four characters) */
+#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200
+/** Double word aligned (character alignment of eight */
+#define I2C_FIFO_CFG_RXFA_RXFA3 0x00000300
+/** DMA controller does not support a burst size of 2 words. The reset value is the half of the FIFO size. The maximum selectable burst size is smaller than the FIFO size. */
+#define I2C_FIFO_CFG_TXBS_MASK 0x00000030
+/** field offset */
+#define I2C_FIFO_CFG_TXBS_OFFSET 4
+/** 1 word */
+#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000
+/** 2 words */
+#define I2C_FIFO_CFG_TXBS_TXBS1 0x00000010
+/** 4 words */
+#define I2C_FIFO_CFG_TXBS_TXBS2 0x00000020
+/** 8 words */
+#define I2C_FIFO_CFG_TXBS_TXBS3 0x00000030
+/** DMA controller does not support a burst size of 2 words. The reset value is the half of the FIFO size. The maximum selectable burst size is smaller than the FIFO size. */
+#define I2C_FIFO_CFG_RXBS_MASK 0x00000003
+/** field offset */
+#define I2C_FIFO_CFG_RXBS_OFFSET 0
+/** 1 word */
+#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000
+/** 2 words */
+#define I2C_FIFO_CFG_RXBS_RXBS1 0x00000001
+/** 4 words */
+#define I2C_FIFO_CFG_RXBS_RXBS2 0x00000002
+/** 8 words */
+#define I2C_FIFO_CFG_RXBS_RXBS3 0x00000003
+
+/* Fields of "I2C Maximum Received Packet Size Register" */
+/** MRPS */
+#define I2C_MRPS_CTRL_MRPS_MASK 0x00003FFF
+/** field offset */
+#define I2C_MRPS_CTRL_MRPS_OFFSET 0
+
+/* Fields of "I2C Received Packet Size Status Register" */
+/** RPS */
+#define I2C_RPS_STAT_RPS_MASK 0x00003FFF
+/** field offset */
+#define I2C_RPS_STAT_RPS_OFFSET 0
+
+/* Fields of "I2C Transmit Packet Size Register" */
+/** TPS */
+#define I2C_TPS_CTRL_TPS_MASK 0x00003FFF
+/** field offset */
+#define I2C_TPS_CTRL_TPS_OFFSET 0
+
+/* Fields of "I2C Filled FIFO Stages Status Register" */
+/** FFS */
+#define I2C_FFS_STAT_FFS_MASK 0x0000000F
+/** field offset */
+#define I2C_FFS_STAT_FFS_OFFSET 0
+
+/* Fields of "I2C Timing Configuration Register" */
+/** SDA Delay Stages for Start/Stop bit in High Speed Mode
+    The actual delay is calculated as the value of this field + 3 */
+#define I2C_TIM_CFG_HS_SDA_DEL_MASK 0x00070000
+/** field offset */
+#define I2C_TIM_CFG_HS_SDA_DEL_OFFSET 16
+/** Enable Fast Mode SCL Low period timing */
+#define I2C_TIM_CFG_FS_SCL_LOW 0x00008000
+/* Disable
+#define I2C_TIM_CFG_FS_SCL_LOW_DIS 0x00000000 */
+/** Enable */
+#define I2C_TIM_CFG_FS_SCL_LOW_EN 0x00008000
+/** SCL Delay Stages for Hold Time Start (Restart) Bit.
+    The actual delay is calculated as the value of this field + 2 */
+#define I2C_TIM_CFG_SCL_DEL_HD_STA_MASK 0x00000E00
+/** field offset */
+#define I2C_TIM_CFG_SCL_DEL_HD_STA_OFFSET 9
+/** SDA Delay Stages for Start/Stop bit in High Speed Mode
+    The actual delay is calculated as the value of this field + 3 */
+#define I2C_TIM_CFG_HS_SDA_DEL_HD_DAT_MASK 0x000001C0
+/** field offset */
+#define I2C_TIM_CFG_HS_SDA_DEL_HD_DAT_OFFSET 6
+/** SDA Delay Stages for Start/Stop bit in High Speed Mode
+    The actual delay is calculated as the value of this field + 3 */
+#define I2C_TIM_CFG_SDA_DEL_HD_DAT_MASK 0x0000003F
+/** field offset */
+#define I2C_TIM_CFG_SDA_DEL_HD_DAT_OFFSET 0
+
+/* Fields of "I2C Error Interrupt Request Source Mask Register" */
+/** Enables the corresponding error interrupt. */
+#define I2C_ERR_IRQSM_TXF_OFL 0x00000008
+/* Disable
+#define I2C_ERR_IRQSM_TXF_OFL_DIS 0x00000000 */
+/** Enable */
+#define I2C_ERR_IRQSM_TXF_OFL_EN 0x00000008
+/** Enables the corresponding error interrupt. */
+#define I2C_ERR_IRQSM_TXF_UFL 0x00000004
+/* Disable
+#define I2C_ERR_IRQSM_TXF_UFL_DIS 0x00000000 */
+/** Enable */
+#define I2C_ERR_IRQSM_TXF_UFL_EN 0x00000004
+/** Enables the corresponding error interrupt. */
+#define I2C_ERR_IRQSM_RXF_OFL 0x00000002
+/* Disable
+#define I2C_ERR_IRQSM_RXF_OFL_DIS 0x00000000 */
+/** Enable */
+#define I2C_ERR_IRQSM_RXF_OFL_EN 0x00000002
+/** Enables the corresponding error interrupt. */
+#define I2C_ERR_IRQSM_RXF_UFL 0x00000001
+/* Disable
+#define I2C_ERR_IRQSM_RXF_UFL_DIS 0x00000000 */
+/** Enable */
+#define I2C_ERR_IRQSM_RXF_UFL_EN 0x00000001
+
+/* Fields of "I2C Error Interrupt Request Source Status Register" */
+/** TXF_OFL */
+#define I2C_ERR_IRQSS_TXF_OFL 0x00000008
+/* Nothing
+#define I2C_ERR_IRQSS_TXF_OFL_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define I2C_ERR_IRQSS_TXF_OFL_INTOCC 0x00000008
+/** TXF_UFL */
+#define I2C_ERR_IRQSS_TXF_UFL 0x00000004
+/* Nothing
+#define I2C_ERR_IRQSS_TXF_UFL_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define I2C_ERR_IRQSS_TXF_UFL_INTOCC 0x00000004
+/** RXF_OFL */
+#define I2C_ERR_IRQSS_RXF_OFL 0x00000002
+/* Nothing
+#define I2C_ERR_IRQSS_RXF_OFL_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define I2C_ERR_IRQSS_RXF_OFL_INTOCC 0x00000002
+/** RXF_UFL */
+#define I2C_ERR_IRQSS_RXF_UFL 0x00000001
+/* Nothing
+#define I2C_ERR_IRQSS_RXF_UFL_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define I2C_ERR_IRQSS_RXF_UFL_INTOCC 0x00000001
+
+/* Fields of "I2C Error Interrupt Request Source Clear Register" */
+/** TXF_OFL */
+#define I2C_ERR_IRQSC_TXF_OFL 0x00000008
+/* No-Operation
+#define I2C_ERR_IRQSC_TXF_OFL_NOP 0x00000000 */
+/** Clear */
+#define I2C_ERR_IRQSC_TXF_OFL_CLR 0x00000008
+/** TXF_UFL */
+#define I2C_ERR_IRQSC_TXF_UFL 0x00000004
+/* No-Operation
+#define I2C_ERR_IRQSC_TXF_UFL_NOP 0x00000000 */
+/** Clear */
+#define I2C_ERR_IRQSC_TXF_UFL_CLR 0x00000004
+/** RXF_OFL */
+#define I2C_ERR_IRQSC_RXF_OFL 0x00000002
+/* No-Operation
+#define I2C_ERR_IRQSC_RXF_OFL_NOP 0x00000000 */
+/** Clear */
+#define I2C_ERR_IRQSC_RXF_OFL_CLR 0x00000002
+/** RXF_UFL */
+#define I2C_ERR_IRQSC_RXF_UFL 0x00000001
+/* No-Operation
+#define I2C_ERR_IRQSC_RXF_UFL_NOP 0x00000000 */
+/** Clear */
+#define I2C_ERR_IRQSC_RXF_UFL_CLR 0x00000001
+
+/* Fields of "I2C Protocol Interrupt Request Source Mask Register" */
+/** Enables the corresponding interrupt. */
+#define I2C_P_IRQSM_RX 0x00000040
+/* Disable
+#define I2C_P_IRQSM_RX_DIS 0x00000000 */
+/** Enable */
+#define I2C_P_IRQSM_RX_EN 0x00000040
+/** Enables the corresponding interrupt. */
+#define I2C_P_IRQSM_TX_END 0x00000020
+/* Disable
+#define I2C_P_IRQSM_TX_END_DIS 0x00000000 */
+/** Enable */
+#define I2C_P_IRQSM_TX_END_EN 0x00000020
+/** Enables the corresponding interrupt. */
+#define I2C_P_IRQSM_NACK 0x00000010
+/* Disable
+#define I2C_P_IRQSM_NACK_DIS 0x00000000 */
+/** Enable */
+#define I2C_P_IRQSM_NACK_EN 0x00000010
+/** Enables the corresponding interrupt. */
+#define I2C_P_IRQSM_AL 0x00000008
+/* Disable
+#define I2C_P_IRQSM_AL_DIS 0x00000000 */
+/** Enable */
+#define I2C_P_IRQSM_AL_EN 0x00000008
+/** Enables the corresponding interrupt. */
+#define I2C_P_IRQSM_MC 0x00000004
+/* Disable
+#define I2C_P_IRQSM_MC_DIS 0x00000000 */
+/** Enable */
+#define I2C_P_IRQSM_MC_EN 0x00000004
+/** Enables the corresponding interrupt. */
+#define I2C_P_IRQSM_GC 0x00000002
+/* Disable
+#define I2C_P_IRQSM_GC_DIS 0x00000000 */
+/** Enable */
+#define I2C_P_IRQSM_GC_EN 0x00000002
+/** Enables the corresponding interrupt. */
+#define I2C_P_IRQSM_AM 0x00000001
+/* Disable
+#define I2C_P_IRQSM_AM_DIS 0x00000000 */
+/** Enable */
+#define I2C_P_IRQSM_AM_EN 0x00000001
+
+/* Fields of "I2C Protocol Interrupt Request Source Status Register" */
+/** RX */
+#define I2C_P_IRQSS_RX 0x00000040
+/* Nothing
+#define I2C_P_IRQSS_RX_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define I2C_P_IRQSS_RX_INTOCC 0x00000040
+/** TX_END */
+#define I2C_P_IRQSS_TX_END 0x00000020
+/* Nothing
+#define I2C_P_IRQSS_TX_END_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define I2C_P_IRQSS_TX_END_INTOCC 0x00000020
+/** NACK */
+#define I2C_P_IRQSS_NACK 0x00000010
+/* Nothing
+#define I2C_P_IRQSS_NACK_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define I2C_P_IRQSS_NACK_INTOCC 0x00000010
+/** AL */
+#define I2C_P_IRQSS_AL 0x00000008
+/* Nothing
+#define I2C_P_IRQSS_AL_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define I2C_P_IRQSS_AL_INTOCC 0x00000008
+/** MC */
+#define I2C_P_IRQSS_MC 0x00000004
+/* Nothing
+#define I2C_P_IRQSS_MC_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define I2C_P_IRQSS_MC_INTOCC 0x00000004
+/** GC */
+#define I2C_P_IRQSS_GC 0x00000002
+/* Nothing
+#define I2C_P_IRQSS_GC_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define I2C_P_IRQSS_GC_INTOCC 0x00000002
+/** AM */
+#define I2C_P_IRQSS_AM 0x00000001
+/* Nothing
+#define I2C_P_IRQSS_AM_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define I2C_P_IRQSS_AM_INTOCC 0x00000001
+
+/* Fields of "I2C Protocol Interrupt Request Source Clear Register" */
+/** RX */
+#define I2C_P_IRQSC_RX 0x00000040
+/* No-Operation
+#define I2C_P_IRQSC_RX_NOP 0x00000000 */
+/** Clear */
+#define I2C_P_IRQSC_RX_CLR 0x00000040
+/** TX_END */
+#define I2C_P_IRQSC_TX_END 0x00000020
+/* No-Operation
+#define I2C_P_IRQSC_TX_END_NOP 0x00000000 */
+/** Clear */
+#define I2C_P_IRQSC_TX_END_CLR 0x00000020
+/** NACK */
+#define I2C_P_IRQSC_NACK 0x00000010
+/* No-Operation
+#define I2C_P_IRQSC_NACK_NOP 0x00000000 */
+/** Clear */
+#define I2C_P_IRQSC_NACK_CLR 0x00000010
+/** AL */
+#define I2C_P_IRQSC_AL 0x00000008
+/* No-Operation
+#define I2C_P_IRQSC_AL_NOP 0x00000000 */
+/** Clear */
+#define I2C_P_IRQSC_AL_CLR 0x00000008
+/** MC */
+#define I2C_P_IRQSC_MC 0x00000004
+/* No-Operation
+#define I2C_P_IRQSC_MC_NOP 0x00000000 */
+/** Clear */
+#define I2C_P_IRQSC_MC_CLR 0x00000004
+/** GC */
+#define I2C_P_IRQSC_GC 0x00000002
+/* No-Operation
+#define I2C_P_IRQSC_GC_NOP 0x00000000 */
+/** Clear */
+#define I2C_P_IRQSC_GC_CLR 0x00000002
+/** AM */
+#define I2C_P_IRQSC_AM 0x00000001
+/* No-Operation
+#define I2C_P_IRQSC_AM_NOP 0x00000000 */
+/** Clear */
+#define I2C_P_IRQSC_AM_CLR 0x00000001
+
+/* Fields of "I2C Raw Interrupt Status Register" */
+/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */
+#define I2C_RIS_I2C_P_INT 0x00000020
+/* Nothing
+#define I2C_RIS_I2C_P_INT_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020
+/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */
+#define I2C_RIS_I2C_ERR_INT 0x00000010
+/* Nothing
+#define I2C_RIS_I2C_ERR_INT_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010
+/** BREQ_INT */
+#define I2C_RIS_BREQ_INT 0x00000008
+/* Nothing
+#define I2C_RIS_BREQ_INT_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define I2C_RIS_BREQ_INT_INTOCC 0x00000008
+/** LBREQ_INT */
+#define I2C_RIS_LBREQ_INT 0x00000004
+/* Nothing
+#define I2C_RIS_LBREQ_INT_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define I2C_RIS_LBREQ_INT_INTOCC 0x00000004
+/** SREQ_INT */
+#define I2C_RIS_SREQ_INT 0x00000002
+/* Nothing
+#define I2C_RIS_SREQ_INT_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define I2C_RIS_SREQ_INT_INTOCC 0x00000002
+/** LSREQ_INT */
+#define I2C_RIS_LSREQ_INT 0x00000001
+/* Nothing
+#define I2C_RIS_LSREQ_INT_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define I2C_RIS_LSREQ_INT_INTOCC 0x00000001
+
+/* Fields of "I2C Interrupt Mask Control Register" */
+/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */
+#define I2C_IMSC_I2C_P_INT 0x00000020
+/* Disable
+#define I2C_IMSC_I2C_P_INT_DIS 0x00000000 */
+/** Enable */
+#define I2C_IMSC_I2C_P_INT_EN 0x00000020
+/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */
+#define I2C_IMSC_I2C_ERR_INT 0x00000010
+/* Disable
+#define I2C_IMSC_I2C_ERR_INT_DIS 0x00000000 */
+/** Enable */
+#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010
+/** BREQ_INT */
+#define I2C_IMSC_BREQ_INT 0x00000008
+/* Disable
+#define I2C_IMSC_BREQ_INT_DIS 0x00000000 */
+/** Enable */
+#define I2C_IMSC_BREQ_INT_EN 0x00000008
+/** LBREQ_INT */
+#define I2C_IMSC_LBREQ_INT 0x00000004
+/* Disable
+#define I2C_IMSC_LBREQ_INT_DIS 0x00000000 */
+/** Enable */
+#define I2C_IMSC_LBREQ_INT_EN 0x00000004
+/** SREQ_INT */
+#define I2C_IMSC_SREQ_INT 0x00000002
+/* Disable
+#define I2C_IMSC_SREQ_INT_DIS 0x00000000 */
+/** Enable */
+#define I2C_IMSC_SREQ_INT_EN 0x00000002
+/** LSREQ_INT */
+#define I2C_IMSC_LSREQ_INT 0x00000001
+/* Disable
+#define I2C_IMSC_LSREQ_INT_DIS 0x00000000 */
+/** Enable */
+#define I2C_IMSC_LSREQ_INT_EN 0x00000001
+
+/* Fields of "I2C Masked Interrupt Status Register" */
+/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */
+#define I2C_MIS_I2C_P_INT 0x00000020
+/* Nothing
+#define I2C_MIS_I2C_P_INT_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define I2C_MIS_I2C_P_INT_INTOCC 0x00000020
+/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */
+#define I2C_MIS_I2C_ERR_INT 0x00000010
+/* Nothing
+#define I2C_MIS_I2C_ERR_INT_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define I2C_MIS_I2C_ERR_INT_INTOCC 0x00000010
+/** BREQ_INT */
+#define I2C_MIS_BREQ_INT 0x00000008
+/* Nothing
+#define I2C_MIS_BREQ_INT_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define I2C_MIS_BREQ_INT_INTOCC 0x00000008
+/** LBREQ_INT */
+#define I2C_MIS_LBREQ_INT 0x00000004
+/* Nothing
+#define I2C_MIS_LBREQ_INT_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define I2C_MIS_LBREQ_INT_INTOCC 0x00000004
+/** SREQ_INT */
+#define I2C_MIS_SREQ_INT 0x00000002
+/* Nothing
+#define I2C_MIS_SREQ_INT_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define I2C_MIS_SREQ_INT_INTOCC 0x00000002
+/** LSREQ_INT */
+#define I2C_MIS_LSREQ_INT 0x00000001
+/* Nothing
+#define I2C_MIS_LSREQ_INT_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define I2C_MIS_LSREQ_INT_INTOCC 0x00000001
+
+/* Fields of "I2C Interrupt Clear Register" */
+/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */
+#define I2C_ICR_I2C_P_INT 0x00000020
+/* No-Operation
+#define I2C_ICR_I2C_P_INT_NOP 0x00000000 */
+/** Clear */
+#define I2C_ICR_I2C_P_INT_CLR 0x00000020
+/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */
+#define I2C_ICR_I2C_ERR_INT 0x00000010
+/* No-Operation
+#define I2C_ICR_I2C_ERR_INT_NOP 0x00000000 */
+/** Clear */
+#define I2C_ICR_I2C_ERR_INT_CLR 0x00000010
+/** BREQ_INT */
+#define I2C_ICR_BREQ_INT 0x00000008
+/* No-Operation
+#define I2C_ICR_BREQ_INT_NOP 0x00000000 */
+/** Clear */
+#define I2C_ICR_BREQ_INT_CLR 0x00000008
+/** LBREQ_INT */
+#define I2C_ICR_LBREQ_INT 0x00000004
+/* No-Operation
+#define I2C_ICR_LBREQ_INT_NOP 0x00000000 */
+/** Clear */
+#define I2C_ICR_LBREQ_INT_CLR 0x00000004
+/** SREQ_INT */
+#define I2C_ICR_SREQ_INT 0x00000002
+/* No-Operation
+#define I2C_ICR_SREQ_INT_NOP 0x00000000 */
+/** Clear */
+#define I2C_ICR_SREQ_INT_CLR 0x00000002
+/** LSREQ_INT */
+#define I2C_ICR_LSREQ_INT 0x00000001
+/* No-Operation
+#define I2C_ICR_LSREQ_INT_NOP 0x00000000 */
+/** Clear */
+#define I2C_ICR_LSREQ_INT_CLR 0x00000001
+
+/* Fields of "I2C Interrupt Set Register" */
+/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */
+#define I2C_ISR_I2C_P_INT 0x00000020
+/* No-Operation
+#define I2C_ISR_I2C_P_INT_NOP 0x00000000 */
+/** Set */
+#define I2C_ISR_I2C_P_INT_SET 0x00000020
+/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */
+#define I2C_ISR_I2C_ERR_INT 0x00000010
+/* No-Operation
+#define I2C_ISR_I2C_ERR_INT_NOP 0x00000000 */
+/** Set */
+#define I2C_ISR_I2C_ERR_INT_SET 0x00000010
+/** BREQ_INT */
+#define I2C_ISR_BREQ_INT 0x00000008
+/* No-Operation
+#define I2C_ISR_BREQ_INT_NOP 0x00000000 */
+/** Set */
+#define I2C_ISR_BREQ_INT_SET 0x00000008
+/** LBREQ_INT */
+#define I2C_ISR_LBREQ_INT 0x00000004
+/* No-Operation
+#define I2C_ISR_LBREQ_INT_NOP 0x00000000 */
+/** Set */
+#define I2C_ISR_LBREQ_INT_SET 0x00000004
+/** SREQ_INT */
+#define I2C_ISR_SREQ_INT 0x00000002
+/* No-Operation
+#define I2C_ISR_SREQ_INT_NOP 0x00000000 */
+/** Set */
+#define I2C_ISR_SREQ_INT_SET 0x00000002
+/** LSREQ_INT */
+#define I2C_ISR_LSREQ_INT 0x00000001
+/* No-Operation
+#define I2C_ISR_LSREQ_INT_NOP 0x00000000 */
+/** Set */
+#define I2C_ISR_LSREQ_INT_SET 0x00000001
+
+/* Fields of "I2C DMA Enable Register" */
+/** BREQ_INT */
+#define I2C_DMAE_BREQ_INT 0x00000008
+/* Disable
+#define I2C_DMAE_BREQ_INT_DIS 0x00000000 */
+/** Enable */
+#define I2C_DMAE_BREQ_INT_EN 0x00000008
+/** LBREQ_INT */
+#define I2C_DMAE_LBREQ_INT 0x00000004
+/* Disable
+#define I2C_DMAE_LBREQ_INT_DIS 0x00000000 */
+/** Enable */
+#define I2C_DMAE_LBREQ_INT_EN 0x00000004
+/** SREQ_INT */
+#define I2C_DMAE_SREQ_INT 0x00000002
+/* Disable
+#define I2C_DMAE_SREQ_INT_DIS 0x00000000 */
+/** Enable */
+#define I2C_DMAE_SREQ_INT_EN 0x00000002
+/** LSREQ_INT */
+#define I2C_DMAE_LSREQ_INT 0x00000001
+/* Disable
+#define I2C_DMAE_LSREQ_INT_DIS 0x00000000 */
+/** Enable */
+#define I2C_DMAE_LSREQ_INT_EN 0x00000001
+
+/* Fields of "I2C Transmit Data Register" */
+/** Characters to be transmitted */
+#define I2C_TXD_TXD_MASK 0xFFFFFFFF
+/** field offset */
+#define I2C_TXD_TXD_OFFSET 0
+
+/* Fields of "I2C Receive Data Register" */
+/** Received characters */
+#define I2C_RXD_RXD_MASK 0xFFFFFFFF
+/** field offset */
+#define I2C_RXD_RXD_OFFSET 0
+
+/*! @} */ /* I2C_REGISTER */
+
+#endif /* _i2c_reg_h */
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/falcon/icu0_reg.h
@@ -0,0 +1,4324 @@
+/******************************************************************************
+
+                               Copyright (c) 2010
+                            Lantiq Deutschland GmbH
+
+  For licensing information, see the file 'LICENSE' in the root folder of
+  this software module.
+
+******************************************************************************/
+
+#ifndef _icu0_reg_h
+#define _icu0_reg_h
+
+/** \addtogroup ICU0_REGISTER
+   @{
+*/
+/* access macros */
+#define icu0_r32(reg) reg_r32(&icu0->reg)
+#define icu0_w32(val, reg) reg_w32(val, &icu0->reg)
+#define icu0_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &icu0->reg)
+#define icu0_r32_table(reg, idx) reg_r32_table(icu0->reg, idx)
+#define icu0_w32_table(val, reg, idx) reg_w32_table(val, icu0->reg, idx)
+#define icu0_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, icu0->reg, idx)
+#define icu0_adr_table(reg, idx) adr_table(icu0->reg, idx)
+
+
+/** ICU0 register structure */
+struct gpon_reg_icu0
+{
+   /** IM0 Interrupt Status Register
+       A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */
+   unsigned int im0_isr; /* 0x00000000 */
+   /** Reserved */
+   unsigned int res_0; /* 0x00000004 */
+   /** IM0 Interrupt Enable Register
+       This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM0_IOSR register and are not signalled via the interrupt line towards the controller. */
+   unsigned int im0_ier; /* 0x00000008 */
+   /** Reserved */
+   unsigned int res_1; /* 0x0000000C */
+   /** IM0 Interrupt Output Status Register
+       This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM0_IER register. */
+   unsigned int im0_iosr; /* 0x00000010 */
+   /** Reserved */
+   unsigned int res_2; /* 0x00000014 */
+   /** IM0 Interrupt Request Set Register
+       A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
+   unsigned int im0_irsr; /* 0x00000018 */
+   /** Reserved */
+   unsigned int res_3; /* 0x0000001C */
+   /** IM0 Interrupt Mode Register
+       This register shows the type of interrupt for each bit. */
+   unsigned int im0_imr; /* 0x00000020 */
+   /** Reserved */
+   unsigned int res_4; /* 0x00000024 */
+   /** IM1 Interrupt Status Register
+       A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */
+   unsigned int im1_isr; /* 0x00000028 */
+   /** Reserved */
+   unsigned int res_5; /* 0x0000002C */
+   /** IM1 Interrupt Enable Register
+       This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM1_IOSR register and are not signalled via the interrupt line towards the controller. */
+   unsigned int im1_ier; /* 0x00000030 */
+   /** Reserved */
+   unsigned int res_6; /* 0x00000034 */
+   /** IM1 Interrupt Output Status Register
+       This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM1_IER register. */
+   unsigned int im1_iosr; /* 0x00000038 */
+   /** Reserved */
+   unsigned int res_7; /* 0x0000003C */
+   /** IM1 Interrupt Request Set Register
+       A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
+   unsigned int im1_irsr; /* 0x00000040 */
+   /** Reserved */
+   unsigned int res_8; /* 0x00000044 */
+   /** IM1 Interrupt Mode Register
+       This register shows the type of interrupt for each bit. */
+   unsigned int im1_imr; /* 0x00000048 */
+   /** Reserved */
+   unsigned int res_9; /* 0x0000004C */
+   /** IM2 Interrupt Status Register
+       A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */
+   unsigned int im2_isr; /* 0x00000050 */
+   /** Reserved */
+   unsigned int res_10; /* 0x00000054 */
+   /** IM2 Interrupt Enable Register
+       This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM2_IOSR register and are not signalled via the interrupt line towards the controller. */
+   unsigned int im2_ier; /* 0x00000058 */
+   /** Reserved */
+   unsigned int res_11; /* 0x0000005C */
+   /** IM2 Interrupt Output Status Register
+       This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM2_IER register. */
+   unsigned int im2_iosr; /* 0x00000060 */
+   /** Reserved */
+   unsigned int res_12; /* 0x00000064 */
+   /** IM2 Interrupt Request Set Register
+       A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
+   unsigned int im2_irsr; /* 0x00000068 */
+   /** Reserved */
+   unsigned int res_13; /* 0x0000006C */
+   /** IM2 Interrupt Mode Register
+       This register shows the type of interrupt for each bit. */
+   unsigned int im2_imr; /* 0x00000070 */
+   /** Reserved */
+   unsigned int res_14; /* 0x00000074 */
+   /** IM3 Interrupt Status Register
+       A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */
+   unsigned int im3_isr; /* 0x00000078 */
+   /** Reserved */
+   unsigned int res_15; /* 0x0000007C */
+   /** IM3 Interrupt Enable Register
+       This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM3_IOSR register and are not signalled via the interrupt line towards the controller. */
+   unsigned int im3_ier; /* 0x00000080 */
+   /** Reserved */
+   unsigned int res_16; /* 0x00000084 */
+   /** IM3 Interrupt Output Status Register
+       This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM3_IER register. */
+   unsigned int im3_iosr; /* 0x00000088 */
+   /** Reserved */
+   unsigned int res_17; /* 0x0000008C */
+   /** IM3 Interrupt Request Set Register
+       A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
+   unsigned int im3_irsr; /* 0x00000090 */
+   /** Reserved */
+   unsigned int res_18; /* 0x00000094 */
+   /** IM3 Interrupt Mode Register
+       This register shows the type of interrupt for each bit. */
+   unsigned int im3_imr; /* 0x00000098 */
+   /** Reserved */
+   unsigned int res_19; /* 0x0000009C */
+   /** IM4 Interrupt Status Register
+       A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */
+   unsigned int im4_isr; /* 0x000000A0 */
+   /** Reserved */
+   unsigned int res_20; /* 0x000000A4 */
+   /** IM4 Interrupt Enable Register
+       This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM4_IOSR register and are not signalled via the interrupt line towards the controller. */
+   unsigned int im4_ier; /* 0x000000A8 */
+   /** Reserved */
+   unsigned int res_21; /* 0x000000AC */
+   /** IM4 Interrupt Output Status Register
+       This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM4_IER register. */
+   unsigned int im4_iosr; /* 0x000000B0 */
+   /** Reserved */
+   unsigned int res_22; /* 0x000000B4 */
+   /** IM4 Interrupt Request Set Register
+       A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
+   unsigned int im4_irsr; /* 0x000000B8 */
+   /** Reserved */
+   unsigned int res_23; /* 0x000000BC */
+   /** IM4 Interrupt Mode Register
+       This register shows the type of interrupt for each bit. */
+   unsigned int im4_imr; /* 0x000000C0 */
+   /** Reserved */
+   unsigned int res_24; /* 0x000000C4 */
+   /** ICU Interrupt Vector Register (5 bit variant)
+       Shows the leftmost pending interrupt request. If e.g. bit 14 of the IOSR register is set, 15 is reported, because the 15th interrupt request is active. */
+   unsigned int icu_ivec; /* 0x000000C8 */
+   /** Reserved */
+   unsigned int res_25; /* 0x000000CC */
+   /** ICU Interrupt Vector Register (6 bit variant)
+       Shows the leftmost pending interrupt request. If e.g. bit 14 of the IOSR register is set, 15 is reported, because the 15th interrupt request is active. */
+   unsigned int icu_ivec_6; /* 0x000000D0 */
+   /** Reserved */
+   unsigned int res_26[3]; /* 0x000000D4 */
+};
+
+
+/* Fields of "IM0 Interrupt Status Register" */
+/** PCM Transmit Crash Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM0_ISR_PCM_HW2_CRASH 0x80000000
+/* Nothing
+#define ICU0_IM0_ISR_PCM_HW2_CRASH_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM0_ISR_PCM_HW2_CRASH_INTACK 0x80000000
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_ISR_PCM_HW2_CRASH_INTOCC 0x80000000
+/** PCM Transmit Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM0_ISR_PCM_TX 0x40000000
+/* Nothing
+#define ICU0_IM0_ISR_PCM_TX_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM0_ISR_PCM_TX_INTACK 0x40000000
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_ISR_PCM_TX_INTOCC 0x40000000
+/** PCM Receive Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM0_ISR_PCM_RX 0x20000000
+/* Nothing
+#define ICU0_IM0_ISR_PCM_RX_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM0_ISR_PCM_RX_INTACK 0x20000000
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_ISR_PCM_RX_INTOCC 0x20000000
+/** Secure Hash Algorithm Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM0_ISR_SHA1_HASH 0x10000000
+/* Nothing
+#define ICU0_IM0_ISR_SHA1_HASH_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM0_ISR_SHA1_HASH_INTACK 0x10000000
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_ISR_SHA1_HASH_INTOCC 0x10000000
+/** Advanced Encryption Standard Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM0_ISR_AES_AES 0x08000000
+/* Nothing
+#define ICU0_IM0_ISR_AES_AES_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM0_ISR_AES_AES_INTACK 0x08000000
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_ISR_AES_AES_INTOCC 0x08000000
+/** SSC Frame Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM0_ISR_SSC0_F 0x00020000
+/* Nothing
+#define ICU0_IM0_ISR_SSC0_F_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM0_ISR_SSC0_F_INTACK 0x00020000
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_ISR_SSC0_F_INTOCC 0x00020000
+/** SSC Error Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM0_ISR_SSC0_E 0x00010000
+/* Nothing
+#define ICU0_IM0_ISR_SSC0_E_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM0_ISR_SSC0_E_INTACK 0x00010000
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_ISR_SSC0_E_INTOCC 0x00010000
+/** SSC Receive Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM0_ISR_SSC0_R 0x00008000
+/* Nothing
+#define ICU0_IM0_ISR_SSC0_R_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM0_ISR_SSC0_R_INTACK 0x00008000
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_ISR_SSC0_R_INTOCC 0x00008000
+/** SSC Transmit Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM0_ISR_SSC0_T 0x00004000
+/* Nothing
+#define ICU0_IM0_ISR_SSC0_T_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM0_ISR_SSC0_T_INTACK 0x00004000
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_ISR_SSC0_T_INTOCC 0x00004000
+/** I2C Peripheral Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM0_ISR_I2C_I2C_P_INT 0x00002000
+/* Nothing
+#define ICU0_IM0_ISR_I2C_I2C_P_INT_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM0_ISR_I2C_I2C_P_INT_INTACK 0x00002000
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_ISR_I2C_I2C_P_INT_INTOCC 0x00002000
+/** I2C Error Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM0_ISR_I2C_I2C_ERR_INT 0x00001000
+/* Nothing
+#define ICU0_IM0_ISR_I2C_I2C_ERR_INT_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM0_ISR_I2C_I2C_ERR_INT_INTACK 0x00001000
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_ISR_I2C_I2C_ERR_INT_INTOCC 0x00001000
+/** I2C Burst Data Transfer Request
+    This bit is an indirect interrupt. */
+#define ICU0_IM0_ISR_I2C_BREQ_INT 0x00000800
+/* Nothing
+#define ICU0_IM0_ISR_I2C_BREQ_INT_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM0_ISR_I2C_BREQ_INT_INTACK 0x00000800
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_ISR_I2C_BREQ_INT_INTOCC 0x00000800
+/** I2C Last Burst Data Transfer Request
+    This bit is an indirect interrupt. */
+#define ICU0_IM0_ISR_I2C_LBREQ_INT 0x00000400
+/* Nothing
+#define ICU0_IM0_ISR_I2C_LBREQ_INT_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM0_ISR_I2C_LBREQ_INT_INTACK 0x00000400
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_ISR_I2C_LBREQ_INT_INTOCC 0x00000400
+/** I2C Single Data Transfer Request
+    This bit is an indirect interrupt. */
+#define ICU0_IM0_ISR_I2C_SREQ_INT 0x00000200
+/* Nothing
+#define ICU0_IM0_ISR_I2C_SREQ_INT_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM0_ISR_I2C_SREQ_INT_INTACK 0x00000200
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_ISR_I2C_SREQ_INT_INTOCC 0x00000200
+/** I2C Last Single Data Transfer Request
+    This bit is an indirect interrupt. */
+#define ICU0_IM0_ISR_I2C_LSREQ_INT 0x00000100
+/* Nothing
+#define ICU0_IM0_ISR_I2C_LSREQ_INT_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM0_ISR_I2C_LSREQ_INT_INTACK 0x00000100
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_ISR_I2C_LSREQ_INT_INTOCC 0x00000100
+/** HOST IF Mailbox1 Transmit Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM0_ISR_HOST_MB1_TIR 0x00000010
+/* Nothing
+#define ICU0_IM0_ISR_HOST_MB1_TIR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM0_ISR_HOST_MB1_TIR_INTACK 0x00000010
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_ISR_HOST_MB1_TIR_INTOCC 0x00000010
+/** HOST IF Mailbox1 Receive Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM0_ISR_HOST_MB1_RIR 0x00000008
+/* Nothing
+#define ICU0_IM0_ISR_HOST_MB1_RIR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM0_ISR_HOST_MB1_RIR_INTACK 0x00000008
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_ISR_HOST_MB1_RIR_INTOCC 0x00000008
+/** HOST IF Mailbox0 Transmit Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM0_ISR_HOST_MB0_TIR 0x00000004
+/* Nothing
+#define ICU0_IM0_ISR_HOST_MB0_TIR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM0_ISR_HOST_MB0_TIR_INTACK 0x00000004
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_ISR_HOST_MB0_TIR_INTOCC 0x00000004
+/** HOST IF Mailbox0 Receive Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM0_ISR_HOST_MB0_RIR 0x00000002
+/* Nothing
+#define ICU0_IM0_ISR_HOST_MB0_RIR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM0_ISR_HOST_MB0_RIR_INTACK 0x00000002
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_ISR_HOST_MB0_RIR_INTOCC 0x00000002
+/** HOST IF Event Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM0_ISR_HOST_EIR 0x00000001
+/* Nothing
+#define ICU0_IM0_ISR_HOST_EIR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM0_ISR_HOST_EIR_INTACK 0x00000001
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_ISR_HOST_EIR_INTOCC 0x00000001
+
+/* Fields of "IM0 Interrupt Enable Register" */
+/** PCM Transmit Crash Interrupt
+    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IER_PCM_HW2_CRASH 0x80000000
+/* Disable
+#define ICU0_IM0_IER_PCM_HW2_CRASH_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM0_IER_PCM_HW2_CRASH_EN 0x80000000
+/** PCM Transmit Interrupt
+    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IER_PCM_TX 0x40000000
+/* Disable
+#define ICU0_IM0_IER_PCM_TX_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM0_IER_PCM_TX_EN 0x40000000
+/** PCM Receive Interrupt
+    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IER_PCM_RX 0x20000000
+/* Disable
+#define ICU0_IM0_IER_PCM_RX_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM0_IER_PCM_RX_EN 0x20000000
+/** Secure Hash Algorithm Interrupt
+    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IER_SHA1_HASH 0x10000000
+/* Disable
+#define ICU0_IM0_IER_SHA1_HASH_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM0_IER_SHA1_HASH_EN 0x10000000
+/** Advanced Encryption Standard Interrupt
+    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IER_AES_AES 0x08000000
+/* Disable
+#define ICU0_IM0_IER_AES_AES_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM0_IER_AES_AES_EN 0x08000000
+/** SSC Frame Interrupt
+    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IER_SSC0_F 0x00020000
+/* Disable
+#define ICU0_IM0_IER_SSC0_F_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM0_IER_SSC0_F_EN 0x00020000
+/** SSC Error Interrupt
+    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IER_SSC0_E 0x00010000
+/* Disable
+#define ICU0_IM0_IER_SSC0_E_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM0_IER_SSC0_E_EN 0x00010000
+/** SSC Receive Interrupt
+    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IER_SSC0_R 0x00008000
+/* Disable
+#define ICU0_IM0_IER_SSC0_R_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM0_IER_SSC0_R_EN 0x00008000
+/** SSC Transmit Interrupt
+    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IER_SSC0_T 0x00004000
+/* Disable
+#define ICU0_IM0_IER_SSC0_T_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM0_IER_SSC0_T_EN 0x00004000
+/** I2C Peripheral Interrupt
+    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IER_I2C_I2C_P_INT 0x00002000
+/* Disable
+#define ICU0_IM0_IER_I2C_I2C_P_INT_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM0_IER_I2C_I2C_P_INT_EN 0x00002000
+/** I2C Error Interrupt
+    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IER_I2C_I2C_ERR_INT 0x00001000
+/* Disable
+#define ICU0_IM0_IER_I2C_I2C_ERR_INT_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM0_IER_I2C_I2C_ERR_INT_EN 0x00001000
+/** I2C Burst Data Transfer Request
+    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IER_I2C_BREQ_INT 0x00000800
+/* Disable
+#define ICU0_IM0_IER_I2C_BREQ_INT_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM0_IER_I2C_BREQ_INT_EN 0x00000800
+/** I2C Last Burst Data Transfer Request
+    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IER_I2C_LBREQ_INT 0x00000400
+/* Disable
+#define ICU0_IM0_IER_I2C_LBREQ_INT_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM0_IER_I2C_LBREQ_INT_EN 0x00000400
+/** I2C Single Data Transfer Request
+    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IER_I2C_SREQ_INT 0x00000200
+/* Disable
+#define ICU0_IM0_IER_I2C_SREQ_INT_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM0_IER_I2C_SREQ_INT_EN 0x00000200
+/** I2C Last Single Data Transfer Request
+    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IER_I2C_LSREQ_INT 0x00000100
+/* Disable
+#define ICU0_IM0_IER_I2C_LSREQ_INT_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM0_IER_I2C_LSREQ_INT_EN 0x00000100
+/** HOST IF Mailbox1 Transmit Interrupt
+    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IER_HOST_MB1_TIR 0x00000010
+/* Disable
+#define ICU0_IM0_IER_HOST_MB1_TIR_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM0_IER_HOST_MB1_TIR_EN 0x00000010
+/** HOST IF Mailbox1 Receive Interrupt
+    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IER_HOST_MB1_RIR 0x00000008
+/* Disable
+#define ICU0_IM0_IER_HOST_MB1_RIR_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM0_IER_HOST_MB1_RIR_EN 0x00000008
+/** HOST IF Mailbox0 Transmit Interrupt
+    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IER_HOST_MB0_TIR 0x00000004
+/* Disable
+#define ICU0_IM0_IER_HOST_MB0_TIR_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM0_IER_HOST_MB0_TIR_EN 0x00000004
+/** HOST IF Mailbox0 Receive Interrupt
+    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IER_HOST_MB0_RIR 0x00000002
+/* Disable
+#define ICU0_IM0_IER_HOST_MB0_RIR_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM0_IER_HOST_MB0_RIR_EN 0x00000002
+/** HOST IF Event Interrupt
+    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IER_HOST_EIR 0x00000001
+/* Disable
+#define ICU0_IM0_IER_HOST_EIR_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM0_IER_HOST_EIR_EN 0x00000001
+
+/* Fields of "IM0 Interrupt Output Status Register" */
+/** PCM Transmit Crash Interrupt
+    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IOSR_PCM_HW2_CRASH 0x80000000
+/* Nothing
+#define ICU0_IM0_IOSR_PCM_HW2_CRASH_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_IOSR_PCM_HW2_CRASH_INTOCC 0x80000000
+/** PCM Transmit Interrupt
+    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IOSR_PCM_TX 0x40000000
+/* Nothing
+#define ICU0_IM0_IOSR_PCM_TX_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_IOSR_PCM_TX_INTOCC 0x40000000
+/** PCM Receive Interrupt
+    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IOSR_PCM_RX 0x20000000
+/* Nothing
+#define ICU0_IM0_IOSR_PCM_RX_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_IOSR_PCM_RX_INTOCC 0x20000000
+/** Secure Hash Algorithm Interrupt
+    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IOSR_SHA1_HASH 0x10000000
+/* Nothing
+#define ICU0_IM0_IOSR_SHA1_HASH_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_IOSR_SHA1_HASH_INTOCC 0x10000000
+/** Advanced Encryption Standard Interrupt
+    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IOSR_AES_AES 0x08000000
+/* Nothing
+#define ICU0_IM0_IOSR_AES_AES_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_IOSR_AES_AES_INTOCC 0x08000000
+/** SSC Frame Interrupt
+    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IOSR_SSC0_F 0x00020000
+/* Nothing
+#define ICU0_IM0_IOSR_SSC0_F_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_IOSR_SSC0_F_INTOCC 0x00020000
+/** SSC Error Interrupt
+    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IOSR_SSC0_E 0x00010000
+/* Nothing
+#define ICU0_IM0_IOSR_SSC0_E_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_IOSR_SSC0_E_INTOCC 0x00010000
+/** SSC Receive Interrupt
+    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IOSR_SSC0_R 0x00008000
+/* Nothing
+#define ICU0_IM0_IOSR_SSC0_R_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_IOSR_SSC0_R_INTOCC 0x00008000
+/** SSC Transmit Interrupt
+    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IOSR_SSC0_T 0x00004000
+/* Nothing
+#define ICU0_IM0_IOSR_SSC0_T_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_IOSR_SSC0_T_INTOCC 0x00004000
+/** I2C Peripheral Interrupt
+    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IOSR_I2C_I2C_P_INT 0x00002000
+/* Nothing
+#define ICU0_IM0_IOSR_I2C_I2C_P_INT_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_IOSR_I2C_I2C_P_INT_INTOCC 0x00002000
+/** I2C Error Interrupt
+    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IOSR_I2C_I2C_ERR_INT 0x00001000
+/* Nothing
+#define ICU0_IM0_IOSR_I2C_I2C_ERR_INT_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_IOSR_I2C_I2C_ERR_INT_INTOCC 0x00001000
+/** I2C Burst Data Transfer Request
+    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IOSR_I2C_BREQ_INT 0x00000800
+/* Nothing
+#define ICU0_IM0_IOSR_I2C_BREQ_INT_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_IOSR_I2C_BREQ_INT_INTOCC 0x00000800
+/** I2C Last Burst Data Transfer Request
+    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IOSR_I2C_LBREQ_INT 0x00000400
+/* Nothing
+#define ICU0_IM0_IOSR_I2C_LBREQ_INT_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_IOSR_I2C_LBREQ_INT_INTOCC 0x00000400
+/** I2C Single Data Transfer Request
+    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IOSR_I2C_SREQ_INT 0x00000200
+/* Nothing
+#define ICU0_IM0_IOSR_I2C_SREQ_INT_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_IOSR_I2C_SREQ_INT_INTOCC 0x00000200
+/** I2C Last Single Data Transfer Request
+    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IOSR_I2C_LSREQ_INT 0x00000100
+/* Nothing
+#define ICU0_IM0_IOSR_I2C_LSREQ_INT_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_IOSR_I2C_LSREQ_INT_INTOCC 0x00000100
+/** HOST IF Mailbox1 Transmit Interrupt
+    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IOSR_HOST_MB1_TIR 0x00000010
+/* Nothing
+#define ICU0_IM0_IOSR_HOST_MB1_TIR_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_IOSR_HOST_MB1_TIR_INTOCC 0x00000010
+/** HOST IF Mailbox1 Receive Interrupt
+    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IOSR_HOST_MB1_RIR 0x00000008
+/* Nothing
+#define ICU0_IM0_IOSR_HOST_MB1_RIR_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_IOSR_HOST_MB1_RIR_INTOCC 0x00000008
+/** HOST IF Mailbox0 Transmit Interrupt
+    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IOSR_HOST_MB0_TIR 0x00000004
+/* Nothing
+#define ICU0_IM0_IOSR_HOST_MB0_TIR_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_IOSR_HOST_MB0_TIR_INTOCC 0x00000004
+/** HOST IF Mailbox0 Receive Interrupt
+    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IOSR_HOST_MB0_RIR 0x00000002
+/* Nothing
+#define ICU0_IM0_IOSR_HOST_MB0_RIR_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_IOSR_HOST_MB0_RIR_INTOCC 0x00000002
+/** HOST IF Event Interrupt
+    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IOSR_HOST_EIR 0x00000001
+/* Nothing
+#define ICU0_IM0_IOSR_HOST_EIR_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM0_IOSR_HOST_EIR_INTOCC 0x00000001
+
+/* Fields of "IM0 Interrupt Request Set Register" */
+/** PCM Transmit Crash Interrupt
+    Software control for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IRSR_PCM_HW2_CRASH 0x80000000
+/** PCM Transmit Interrupt
+    Software control for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IRSR_PCM_TX 0x40000000
+/** PCM Receive Interrupt
+    Software control for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IRSR_PCM_RX 0x20000000
+/** Secure Hash Algorithm Interrupt
+    Software control for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IRSR_SHA1_HASH 0x10000000
+/** Advanced Encryption Standard Interrupt
+    Software control for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IRSR_AES_AES 0x08000000
+/** SSC Frame Interrupt
+    Software control for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IRSR_SSC0_F 0x00020000
+/** SSC Error Interrupt
+    Software control for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IRSR_SSC0_E 0x00010000
+/** SSC Receive Interrupt
+    Software control for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IRSR_SSC0_R 0x00008000
+/** SSC Transmit Interrupt
+    Software control for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IRSR_SSC0_T 0x00004000
+/** I2C Peripheral Interrupt
+    Software control for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IRSR_I2C_I2C_P_INT 0x00002000
+/** I2C Error Interrupt
+    Software control for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IRSR_I2C_I2C_ERR_INT 0x00001000
+/** I2C Burst Data Transfer Request
+    Software control for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IRSR_I2C_BREQ_INT 0x00000800
+/** I2C Last Burst Data Transfer Request
+    Software control for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IRSR_I2C_LBREQ_INT 0x00000400
+/** I2C Single Data Transfer Request
+    Software control for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IRSR_I2C_SREQ_INT 0x00000200
+/** I2C Last Single Data Transfer Request
+    Software control for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IRSR_I2C_LSREQ_INT 0x00000100
+/** HOST IF Mailbox1 Transmit Interrupt
+    Software control for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IRSR_HOST_MB1_TIR 0x00000010
+/** HOST IF Mailbox1 Receive Interrupt
+    Software control for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IRSR_HOST_MB1_RIR 0x00000008
+/** HOST IF Mailbox0 Transmit Interrupt
+    Software control for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IRSR_HOST_MB0_TIR 0x00000004
+/** HOST IF Mailbox0 Receive Interrupt
+    Software control for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IRSR_HOST_MB0_RIR 0x00000002
+/** HOST IF Event Interrupt
+    Software control for the corresponding bit in the IM0_ISR register. */
+#define ICU0_IM0_IRSR_HOST_EIR 0x00000001
+
+/* Fields of "IM0 Interrupt Mode Register" */
+/** PCM Transmit Crash Interrupt
+    Type of interrupt. */
+#define ICU0_IM0_IMR_PCM_HW2_CRASH 0x80000000
+/* Indirect Interrupt.
+#define ICU0_IM0_IMR_PCM_HW2_CRASH_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM0_IMR_PCM_HW2_CRASH_DIR 0x80000000
+/** PCM Transmit Interrupt
+    Type of interrupt. */
+#define ICU0_IM0_IMR_PCM_TX 0x40000000
+/* Indirect Interrupt.
+#define ICU0_IM0_IMR_PCM_TX_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM0_IMR_PCM_TX_DIR 0x40000000
+/** PCM Receive Interrupt
+    Type of interrupt. */
+#define ICU0_IM0_IMR_PCM_RX 0x20000000
+/* Indirect Interrupt.
+#define ICU0_IM0_IMR_PCM_RX_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM0_IMR_PCM_RX_DIR 0x20000000
+/** Secure Hash Algorithm Interrupt
+    Type of interrupt. */
+#define ICU0_IM0_IMR_SHA1_HASH 0x10000000
+/* Indirect Interrupt.
+#define ICU0_IM0_IMR_SHA1_HASH_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM0_IMR_SHA1_HASH_DIR 0x10000000
+/** Advanced Encryption Standard Interrupt
+    Type of interrupt. */
+#define ICU0_IM0_IMR_AES_AES 0x08000000
+/* Indirect Interrupt.
+#define ICU0_IM0_IMR_AES_AES_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM0_IMR_AES_AES_DIR 0x08000000
+/** SSC Frame Interrupt
+    Type of interrupt. */
+#define ICU0_IM0_IMR_SSC0_F 0x00020000
+/* Indirect Interrupt.
+#define ICU0_IM0_IMR_SSC0_F_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM0_IMR_SSC0_F_DIR 0x00020000
+/** SSC Error Interrupt
+    Type of interrupt. */
+#define ICU0_IM0_IMR_SSC0_E 0x00010000
+/* Indirect Interrupt.
+#define ICU0_IM0_IMR_SSC0_E_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM0_IMR_SSC0_E_DIR 0x00010000
+/** SSC Receive Interrupt
+    Type of interrupt. */
+#define ICU0_IM0_IMR_SSC0_R 0x00008000
+/* Indirect Interrupt.
+#define ICU0_IM0_IMR_SSC0_R_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM0_IMR_SSC0_R_DIR 0x00008000
+/** SSC Transmit Interrupt
+    Type of interrupt. */
+#define ICU0_IM0_IMR_SSC0_T 0x00004000
+/* Indirect Interrupt.
+#define ICU0_IM0_IMR_SSC0_T_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM0_IMR_SSC0_T_DIR 0x00004000
+/** I2C Peripheral Interrupt
+    Type of interrupt. */
+#define ICU0_IM0_IMR_I2C_I2C_P_INT 0x00002000
+/* Indirect Interrupt.
+#define ICU0_IM0_IMR_I2C_I2C_P_INT_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM0_IMR_I2C_I2C_P_INT_DIR 0x00002000
+/** I2C Error Interrupt
+    Type of interrupt. */
+#define ICU0_IM0_IMR_I2C_I2C_ERR_INT 0x00001000
+/* Indirect Interrupt.
+#define ICU0_IM0_IMR_I2C_I2C_ERR_INT_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM0_IMR_I2C_I2C_ERR_INT_DIR 0x00001000
+/** I2C Burst Data Transfer Request
+    Type of interrupt. */
+#define ICU0_IM0_IMR_I2C_BREQ_INT 0x00000800
+/* Indirect Interrupt.
+#define ICU0_IM0_IMR_I2C_BREQ_INT_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM0_IMR_I2C_BREQ_INT_DIR 0x00000800
+/** I2C Last Burst Data Transfer Request
+    Type of interrupt. */
+#define ICU0_IM0_IMR_I2C_LBREQ_INT 0x00000400
+/* Indirect Interrupt.
+#define ICU0_IM0_IMR_I2C_LBREQ_INT_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM0_IMR_I2C_LBREQ_INT_DIR 0x00000400
+/** I2C Single Data Transfer Request
+    Type of interrupt. */
+#define ICU0_IM0_IMR_I2C_SREQ_INT 0x00000200
+/* Indirect Interrupt.
+#define ICU0_IM0_IMR_I2C_SREQ_INT_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM0_IMR_I2C_SREQ_INT_DIR 0x00000200
+/** I2C Last Single Data Transfer Request
+    Type of interrupt. */
+#define ICU0_IM0_IMR_I2C_LSREQ_INT 0x00000100
+/* Indirect Interrupt.
+#define ICU0_IM0_IMR_I2C_LSREQ_INT_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM0_IMR_I2C_LSREQ_INT_DIR 0x00000100
+/** HOST IF Mailbox1 Transmit Interrupt
+    Type of interrupt. */
+#define ICU0_IM0_IMR_HOST_MB1_TIR 0x00000010
+/* Indirect Interrupt.
+#define ICU0_IM0_IMR_HOST_MB1_TIR_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM0_IMR_HOST_MB1_TIR_DIR 0x00000010
+/** HOST IF Mailbox1 Receive Interrupt
+    Type of interrupt. */
+#define ICU0_IM0_IMR_HOST_MB1_RIR 0x00000008
+/* Indirect Interrupt.
+#define ICU0_IM0_IMR_HOST_MB1_RIR_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM0_IMR_HOST_MB1_RIR_DIR 0x00000008
+/** HOST IF Mailbox0 Transmit Interrupt
+    Type of interrupt. */
+#define ICU0_IM0_IMR_HOST_MB0_TIR 0x00000004
+/* Indirect Interrupt.
+#define ICU0_IM0_IMR_HOST_MB0_TIR_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM0_IMR_HOST_MB0_TIR_DIR 0x00000004
+/** HOST IF Mailbox0 Receive Interrupt
+    Type of interrupt. */
+#define ICU0_IM0_IMR_HOST_MB0_RIR 0x00000002
+/* Indirect Interrupt.
+#define ICU0_IM0_IMR_HOST_MB0_RIR_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM0_IMR_HOST_MB0_RIR_DIR 0x00000002
+/** HOST IF Event Interrupt
+    Type of interrupt. */
+#define ICU0_IM0_IMR_HOST_EIR 0x00000001
+/* Indirect Interrupt.
+#define ICU0_IM0_IMR_HOST_EIR_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM0_IMR_HOST_EIR_DIR 0x00000001
+
+/* Fields of "IM1 Interrupt Status Register" */
+/** Crossbar Error Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM1_ISR_XBAR_ERROR 0x80000000
+/* Nothing
+#define ICU0_IM1_ISR_XBAR_ERROR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM1_ISR_XBAR_ERROR_INTACK 0x80000000
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_ISR_XBAR_ERROR_INTOCC 0x80000000
+/** DDR Controller Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM1_ISR_DDR 0x40000000
+/* Nothing
+#define ICU0_IM1_ISR_DDR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM1_ISR_DDR_INTACK 0x40000000
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_ISR_DDR_INTOCC 0x40000000
+/** FPI Bus Control Unit Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM1_ISR_BCU0 0x20000000
+/* Nothing
+#define ICU0_IM1_ISR_BCU0_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM1_ISR_BCU0_INTACK 0x20000000
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_ISR_BCU0_INTOCC 0x20000000
+/** SBIU interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM1_ISR_SBIU0 0x08000000
+/* Nothing
+#define ICU0_IM1_ISR_SBIU0_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM1_ISR_SBIU0_INTACK 0x08000000
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_ISR_SBIU0_INTOCC 0x08000000
+/** Watchdog Prewarning Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM1_ISR_WDT_PIR 0x02000000
+/* Nothing
+#define ICU0_IM1_ISR_WDT_PIR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM1_ISR_WDT_PIR_INTACK 0x02000000
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_ISR_WDT_PIR_INTOCC 0x02000000
+/** Watchdog Access Error Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM1_ISR_WDT_AEIR 0x01000000
+/* Nothing
+#define ICU0_IM1_ISR_WDT_AEIR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM1_ISR_WDT_AEIR_INTACK 0x01000000
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_ISR_WDT_AEIR_INTOCC 0x01000000
+/** SYS GPE Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM1_ISR_SYS_GPE 0x00200000
+/* Nothing
+#define ICU0_IM1_ISR_SYS_GPE_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM1_ISR_SYS_GPE_INTACK 0x00200000
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_ISR_SYS_GPE_INTOCC 0x00200000
+/** SYS1 Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM1_ISR_SYS1 0x00100000
+/* Nothing
+#define ICU0_IM1_ISR_SYS1_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM1_ISR_SYS1_INTACK 0x00100000
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_ISR_SYS1_INTOCC 0x00100000
+/** PMA Interrupt from IntNode of the RX Clk Domain
+    This bit is an indirect interrupt. */
+#define ICU0_IM1_ISR_PMA_RX 0x00020000
+/* Nothing
+#define ICU0_IM1_ISR_PMA_RX_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM1_ISR_PMA_RX_INTACK 0x00020000
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_ISR_PMA_RX_INTOCC 0x00020000
+/** PMA Interrupt from IntNode of the TX Clk Domain
+    This bit is an indirect interrupt. */
+#define ICU0_IM1_ISR_PMA_TX 0x00010000
+/* Nothing
+#define ICU0_IM1_ISR_PMA_TX_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM1_ISR_PMA_TX_INTACK 0x00010000
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_ISR_PMA_TX_INTOCC 0x00010000
+/** PMA Interrupt from IntNode of the 200MHz Domain
+    This bit is an indirect interrupt. */
+#define ICU0_IM1_ISR_PMA_200M 0x00008000
+/* Nothing
+#define ICU0_IM1_ISR_PMA_200M_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM1_ISR_PMA_200M_INTACK 0x00008000
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_ISR_PMA_200M_INTOCC 0x00008000
+/** Time of Day
+    This bit is an indirect interrupt. */
+#define ICU0_IM1_ISR_TOD 0x00004000
+/* Nothing
+#define ICU0_IM1_ISR_TOD_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM1_ISR_TOD_INTACK 0x00004000
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_ISR_TOD_INTOCC 0x00004000
+/** 8kHz root interrupt derived from GPON interface
+    This bit is a direct interrupt. */
+#define ICU0_IM1_ISR_FSC_ROOT 0x00002000
+/* Nothing
+#define ICU0_IM1_ISR_FSC_ROOT_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM1_ISR_FSC_ROOT_INTACK 0x00002000
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_ISR_FSC_ROOT_INTOCC 0x00002000
+/** FSC Timer Interrupt 1
+    Delayed version of FSCROOT. This bit is a direct interrupt. */
+#define ICU0_IM1_ISR_FSCT_CMP1 0x00001000
+/* Nothing
+#define ICU0_IM1_ISR_FSCT_CMP1_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM1_ISR_FSCT_CMP1_INTACK 0x00001000
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_ISR_FSCT_CMP1_INTOCC 0x00001000
+/** FSC Timer Interrupt 0
+    Delayed version of FSCROOT. This bit is a direct interrupt. */
+#define ICU0_IM1_ISR_FSCT_CMP0 0x00000800
+/* Nothing
+#define ICU0_IM1_ISR_FSCT_CMP0_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM1_ISR_FSCT_CMP0_INTACK 0x00000800
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_ISR_FSCT_CMP0_INTOCC 0x00000800
+/** 8kHz backup interrupt derived from core-PLL
+    This bit is an indirect interrupt. */
+#define ICU0_IM1_ISR_FSC_BKP 0x00000400
+/* Nothing
+#define ICU0_IM1_ISR_FSC_BKP_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM1_ISR_FSC_BKP_INTACK 0x00000400
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_ISR_FSC_BKP_INTOCC 0x00000400
+/** External Interrupt from GPIO P4
+    This bit is an indirect interrupt. */
+#define ICU0_IM1_ISR_P4 0x00000100
+/* Nothing
+#define ICU0_IM1_ISR_P4_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM1_ISR_P4_INTACK 0x00000100
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_ISR_P4_INTOCC 0x00000100
+/** External Interrupt from GPIO P3
+    This bit is an indirect interrupt. */
+#define ICU0_IM1_ISR_P3 0x00000080
+/* Nothing
+#define ICU0_IM1_ISR_P3_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM1_ISR_P3_INTACK 0x00000080
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_ISR_P3_INTOCC 0x00000080
+/** External Interrupt from GPIO P2
+    This bit is an indirect interrupt. */
+#define ICU0_IM1_ISR_P2 0x00000040
+/* Nothing
+#define ICU0_IM1_ISR_P2_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM1_ISR_P2_INTACK 0x00000040
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_ISR_P2_INTOCC 0x00000040
+/** External Interrupt from GPIO P1
+    This bit is an indirect interrupt. */
+#define ICU0_IM1_ISR_P1 0x00000020
+/* Nothing
+#define ICU0_IM1_ISR_P1_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM1_ISR_P1_INTACK 0x00000020
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_ISR_P1_INTOCC 0x00000020
+/** External Interrupt from GPIO P0
+    This bit is an indirect interrupt. */
+#define ICU0_IM1_ISR_P0 0x00000010
+/* Nothing
+#define ICU0_IM1_ISR_P0_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM1_ISR_P0_INTACK 0x00000010
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_ISR_P0_INTOCC 0x00000010
+/** EBU Serial Flash Busy
+    This bit is an indirect interrupt. */
+#define ICU0_IM1_ISR_EBU_SF_BUSY 0x00000004
+/* Nothing
+#define ICU0_IM1_ISR_EBU_SF_BUSY_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM1_ISR_EBU_SF_BUSY_INTACK 0x00000004
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_ISR_EBU_SF_BUSY_INTOCC 0x00000004
+/** EBU Serial Flash Command Overwrite Error
+    This bit is an indirect interrupt. */
+#define ICU0_IM1_ISR_EBU_SF_COVERR 0x00000002
+/* Nothing
+#define ICU0_IM1_ISR_EBU_SF_COVERR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM1_ISR_EBU_SF_COVERR_INTACK 0x00000002
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_ISR_EBU_SF_COVERR_INTOCC 0x00000002
+/** EBU Serial Flash Command Error
+    This bit is an indirect interrupt. */
+#define ICU0_IM1_ISR_EBU_SF_CMDERR 0x00000001
+/* Nothing
+#define ICU0_IM1_ISR_EBU_SF_CMDERR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM1_ISR_EBU_SF_CMDERR_INTACK 0x00000001
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_ISR_EBU_SF_CMDERR_INTOCC 0x00000001
+
+/* Fields of "IM1 Interrupt Enable Register" */
+/** Crossbar Error Interrupt
+    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IER_XBAR_ERROR 0x80000000
+/* Disable
+#define ICU0_IM1_IER_XBAR_ERROR_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM1_IER_XBAR_ERROR_EN 0x80000000
+/** DDR Controller Interrupt
+    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IER_DDR 0x40000000
+/* Disable
+#define ICU0_IM1_IER_DDR_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM1_IER_DDR_EN 0x40000000
+/** FPI Bus Control Unit Interrupt
+    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IER_BCU0 0x20000000
+/* Disable
+#define ICU0_IM1_IER_BCU0_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM1_IER_BCU0_EN 0x20000000
+/** SBIU interrupt
+    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IER_SBIU0 0x08000000
+/* Disable
+#define ICU0_IM1_IER_SBIU0_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM1_IER_SBIU0_EN 0x08000000
+/** Watchdog Prewarning Interrupt
+    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IER_WDT_PIR 0x02000000
+/* Disable
+#define ICU0_IM1_IER_WDT_PIR_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM1_IER_WDT_PIR_EN 0x02000000
+/** Watchdog Access Error Interrupt
+    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IER_WDT_AEIR 0x01000000
+/* Disable
+#define ICU0_IM1_IER_WDT_AEIR_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM1_IER_WDT_AEIR_EN 0x01000000
+/** SYS GPE Interrupt
+    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IER_SYS_GPE 0x00200000
+/* Disable
+#define ICU0_IM1_IER_SYS_GPE_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM1_IER_SYS_GPE_EN 0x00200000
+/** SYS1 Interrupt
+    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IER_SYS1 0x00100000
+/* Disable
+#define ICU0_IM1_IER_SYS1_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM1_IER_SYS1_EN 0x00100000
+/** PMA Interrupt from IntNode of the RX Clk Domain
+    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IER_PMA_RX 0x00020000
+/* Disable
+#define ICU0_IM1_IER_PMA_RX_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM1_IER_PMA_RX_EN 0x00020000
+/** PMA Interrupt from IntNode of the TX Clk Domain
+    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IER_PMA_TX 0x00010000
+/* Disable
+#define ICU0_IM1_IER_PMA_TX_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM1_IER_PMA_TX_EN 0x00010000
+/** PMA Interrupt from IntNode of the 200MHz Domain
+    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IER_PMA_200M 0x00008000
+/* Disable
+#define ICU0_IM1_IER_PMA_200M_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM1_IER_PMA_200M_EN 0x00008000
+/** Time of Day
+    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IER_TOD 0x00004000
+/* Disable
+#define ICU0_IM1_IER_TOD_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM1_IER_TOD_EN 0x00004000
+/** 8kHz root interrupt derived from GPON interface
+    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IER_FSC_ROOT 0x00002000
+/* Disable
+#define ICU0_IM1_IER_FSC_ROOT_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM1_IER_FSC_ROOT_EN 0x00002000
+/** FSC Timer Interrupt 1
+    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IER_FSCT_CMP1 0x00001000
+/* Disable
+#define ICU0_IM1_IER_FSCT_CMP1_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM1_IER_FSCT_CMP1_EN 0x00001000
+/** FSC Timer Interrupt 0
+    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IER_FSCT_CMP0 0x00000800
+/* Disable
+#define ICU0_IM1_IER_FSCT_CMP0_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM1_IER_FSCT_CMP0_EN 0x00000800
+/** 8kHz backup interrupt derived from core-PLL
+    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IER_FSC_BKP 0x00000400
+/* Disable
+#define ICU0_IM1_IER_FSC_BKP_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM1_IER_FSC_BKP_EN 0x00000400
+/** External Interrupt from GPIO P4
+    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IER_P4 0x00000100
+/* Disable
+#define ICU0_IM1_IER_P4_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM1_IER_P4_EN 0x00000100
+/** External Interrupt from GPIO P3
+    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IER_P3 0x00000080
+/* Disable
+#define ICU0_IM1_IER_P3_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM1_IER_P3_EN 0x00000080
+/** External Interrupt from GPIO P2
+    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IER_P2 0x00000040
+/* Disable
+#define ICU0_IM1_IER_P2_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM1_IER_P2_EN 0x00000040
+/** External Interrupt from GPIO P1
+    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IER_P1 0x00000020
+/* Disable
+#define ICU0_IM1_IER_P1_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM1_IER_P1_EN 0x00000020
+/** External Interrupt from GPIO P0
+    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IER_P0 0x00000010
+/* Disable
+#define ICU0_IM1_IER_P0_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM1_IER_P0_EN 0x00000010
+/** EBU Serial Flash Busy
+    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IER_EBU_SF_BUSY 0x00000004
+/* Disable
+#define ICU0_IM1_IER_EBU_SF_BUSY_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM1_IER_EBU_SF_BUSY_EN 0x00000004
+/** EBU Serial Flash Command Overwrite Error
+    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IER_EBU_SF_COVERR 0x00000002
+/* Disable
+#define ICU0_IM1_IER_EBU_SF_COVERR_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM1_IER_EBU_SF_COVERR_EN 0x00000002
+/** EBU Serial Flash Command Error
+    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IER_EBU_SF_CMDERR 0x00000001
+/* Disable
+#define ICU0_IM1_IER_EBU_SF_CMDERR_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM1_IER_EBU_SF_CMDERR_EN 0x00000001
+
+/* Fields of "IM1 Interrupt Output Status Register" */
+/** Crossbar Error Interrupt
+    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IOSR_XBAR_ERROR 0x80000000
+/* Nothing
+#define ICU0_IM1_IOSR_XBAR_ERROR_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_IOSR_XBAR_ERROR_INTOCC 0x80000000
+/** DDR Controller Interrupt
+    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IOSR_DDR 0x40000000
+/* Nothing
+#define ICU0_IM1_IOSR_DDR_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_IOSR_DDR_INTOCC 0x40000000
+/** FPI Bus Control Unit Interrupt
+    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IOSR_BCU0 0x20000000
+/* Nothing
+#define ICU0_IM1_IOSR_BCU0_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_IOSR_BCU0_INTOCC 0x20000000
+/** SBIU interrupt
+    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IOSR_SBIU0 0x08000000
+/* Nothing
+#define ICU0_IM1_IOSR_SBIU0_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_IOSR_SBIU0_INTOCC 0x08000000
+/** Watchdog Prewarning Interrupt
+    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IOSR_WDT_PIR 0x02000000
+/* Nothing
+#define ICU0_IM1_IOSR_WDT_PIR_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_IOSR_WDT_PIR_INTOCC 0x02000000
+/** Watchdog Access Error Interrupt
+    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IOSR_WDT_AEIR 0x01000000
+/* Nothing
+#define ICU0_IM1_IOSR_WDT_AEIR_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_IOSR_WDT_AEIR_INTOCC 0x01000000
+/** SYS GPE Interrupt
+    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IOSR_SYS_GPE 0x00200000
+/* Nothing
+#define ICU0_IM1_IOSR_SYS_GPE_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_IOSR_SYS_GPE_INTOCC 0x00200000
+/** SYS1 Interrupt
+    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IOSR_SYS1 0x00100000
+/* Nothing
+#define ICU0_IM1_IOSR_SYS1_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_IOSR_SYS1_INTOCC 0x00100000
+/** PMA Interrupt from IntNode of the RX Clk Domain
+    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IOSR_PMA_RX 0x00020000
+/* Nothing
+#define ICU0_IM1_IOSR_PMA_RX_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_IOSR_PMA_RX_INTOCC 0x00020000
+/** PMA Interrupt from IntNode of the TX Clk Domain
+    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IOSR_PMA_TX 0x00010000
+/* Nothing
+#define ICU0_IM1_IOSR_PMA_TX_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_IOSR_PMA_TX_INTOCC 0x00010000
+/** PMA Interrupt from IntNode of the 200MHz Domain
+    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IOSR_PMA_200M 0x00008000
+/* Nothing
+#define ICU0_IM1_IOSR_PMA_200M_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_IOSR_PMA_200M_INTOCC 0x00008000
+/** Time of Day
+    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IOSR_TOD 0x00004000
+/* Nothing
+#define ICU0_IM1_IOSR_TOD_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_IOSR_TOD_INTOCC 0x00004000
+/** 8kHz root interrupt derived from GPON interface
+    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IOSR_FSC_ROOT 0x00002000
+/* Nothing
+#define ICU0_IM1_IOSR_FSC_ROOT_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_IOSR_FSC_ROOT_INTOCC 0x00002000
+/** FSC Timer Interrupt 1
+    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IOSR_FSCT_CMP1 0x00001000
+/* Nothing
+#define ICU0_IM1_IOSR_FSCT_CMP1_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_IOSR_FSCT_CMP1_INTOCC 0x00001000
+/** FSC Timer Interrupt 0
+    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IOSR_FSCT_CMP0 0x00000800
+/* Nothing
+#define ICU0_IM1_IOSR_FSCT_CMP0_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_IOSR_FSCT_CMP0_INTOCC 0x00000800
+/** 8kHz backup interrupt derived from core-PLL
+    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IOSR_FSC_BKP 0x00000400
+/* Nothing
+#define ICU0_IM1_IOSR_FSC_BKP_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_IOSR_FSC_BKP_INTOCC 0x00000400
+/** External Interrupt from GPIO P4
+    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IOSR_P4 0x00000100
+/* Nothing
+#define ICU0_IM1_IOSR_P4_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_IOSR_P4_INTOCC 0x00000100
+/** External Interrupt from GPIO P3
+    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IOSR_P3 0x00000080
+/* Nothing
+#define ICU0_IM1_IOSR_P3_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_IOSR_P3_INTOCC 0x00000080
+/** External Interrupt from GPIO P2
+    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IOSR_P2 0x00000040
+/* Nothing
+#define ICU0_IM1_IOSR_P2_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_IOSR_P2_INTOCC 0x00000040
+/** External Interrupt from GPIO P1
+    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IOSR_P1 0x00000020
+/* Nothing
+#define ICU0_IM1_IOSR_P1_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_IOSR_P1_INTOCC 0x00000020
+/** External Interrupt from GPIO P0
+    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IOSR_P0 0x00000010
+/* Nothing
+#define ICU0_IM1_IOSR_P0_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_IOSR_P0_INTOCC 0x00000010
+/** EBU Serial Flash Busy
+    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IOSR_EBU_SF_BUSY 0x00000004
+/* Nothing
+#define ICU0_IM1_IOSR_EBU_SF_BUSY_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_IOSR_EBU_SF_BUSY_INTOCC 0x00000004
+/** EBU Serial Flash Command Overwrite Error
+    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IOSR_EBU_SF_COVERR 0x00000002
+/* Nothing
+#define ICU0_IM1_IOSR_EBU_SF_COVERR_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_IOSR_EBU_SF_COVERR_INTOCC 0x00000002
+/** EBU Serial Flash Command Error
+    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IOSR_EBU_SF_CMDERR 0x00000001
+/* Nothing
+#define ICU0_IM1_IOSR_EBU_SF_CMDERR_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM1_IOSR_EBU_SF_CMDERR_INTOCC 0x00000001
+
+/* Fields of "IM1 Interrupt Request Set Register" */
+/** Crossbar Error Interrupt
+    Software control for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IRSR_XBAR_ERROR 0x80000000
+/** DDR Controller Interrupt
+    Software control for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IRSR_DDR 0x40000000
+/** FPI Bus Control Unit Interrupt
+    Software control for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IRSR_BCU0 0x20000000
+/** SBIU interrupt
+    Software control for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IRSR_SBIU0 0x08000000
+/** Watchdog Prewarning Interrupt
+    Software control for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IRSR_WDT_PIR 0x02000000
+/** Watchdog Access Error Interrupt
+    Software control for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IRSR_WDT_AEIR 0x01000000
+/** SYS GPE Interrupt
+    Software control for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IRSR_SYS_GPE 0x00200000
+/** SYS1 Interrupt
+    Software control for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IRSR_SYS1 0x00100000
+/** PMA Interrupt from IntNode of the RX Clk Domain
+    Software control for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IRSR_PMA_RX 0x00020000
+/** PMA Interrupt from IntNode of the TX Clk Domain
+    Software control for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IRSR_PMA_TX 0x00010000
+/** PMA Interrupt from IntNode of the 200MHz Domain
+    Software control for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IRSR_PMA_200M 0x00008000
+/** Time of Day
+    Software control for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IRSR_TOD 0x00004000
+/** 8kHz root interrupt derived from GPON interface
+    Software control for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IRSR_FSC_ROOT 0x00002000
+/** FSC Timer Interrupt 1
+    Software control for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IRSR_FSCT_CMP1 0x00001000
+/** FSC Timer Interrupt 0
+    Software control for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IRSR_FSCT_CMP0 0x00000800
+/** 8kHz backup interrupt derived from core-PLL
+    Software control for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IRSR_FSC_BKP 0x00000400
+/** External Interrupt from GPIO P4
+    Software control for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IRSR_P4 0x00000100
+/** External Interrupt from GPIO P3
+    Software control for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IRSR_P3 0x00000080
+/** External Interrupt from GPIO P2
+    Software control for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IRSR_P2 0x00000040
+/** External Interrupt from GPIO P1
+    Software control for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IRSR_P1 0x00000020
+/** External Interrupt from GPIO P0
+    Software control for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IRSR_P0 0x00000010
+/** EBU Serial Flash Busy
+    Software control for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IRSR_EBU_SF_BUSY 0x00000004
+/** EBU Serial Flash Command Overwrite Error
+    Software control for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IRSR_EBU_SF_COVERR 0x00000002
+/** EBU Serial Flash Command Error
+    Software control for the corresponding bit in the IM1_ISR register. */
+#define ICU0_IM1_IRSR_EBU_SF_CMDERR 0x00000001
+
+/* Fields of "IM1 Interrupt Mode Register" */
+/** Crossbar Error Interrupt
+    Type of interrupt. */
+#define ICU0_IM1_IMR_XBAR_ERROR 0x80000000
+/* Indirect Interrupt.
+#define ICU0_IM1_IMR_XBAR_ERROR_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM1_IMR_XBAR_ERROR_DIR 0x80000000
+/** DDR Controller Interrupt
+    Type of interrupt. */
+#define ICU0_IM1_IMR_DDR 0x40000000
+/* Indirect Interrupt.
+#define ICU0_IM1_IMR_DDR_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM1_IMR_DDR_DIR 0x40000000
+/** FPI Bus Control Unit Interrupt
+    Type of interrupt. */
+#define ICU0_IM1_IMR_BCU0 0x20000000
+/* Indirect Interrupt.
+#define ICU0_IM1_IMR_BCU0_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM1_IMR_BCU0_DIR 0x20000000
+/** SBIU interrupt
+    Type of interrupt. */
+#define ICU0_IM1_IMR_SBIU0 0x08000000
+/* Indirect Interrupt.
+#define ICU0_IM1_IMR_SBIU0_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM1_IMR_SBIU0_DIR 0x08000000
+/** Watchdog Prewarning Interrupt
+    Type of interrupt. */
+#define ICU0_IM1_IMR_WDT_PIR 0x02000000
+/* Indirect Interrupt.
+#define ICU0_IM1_IMR_WDT_PIR_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM1_IMR_WDT_PIR_DIR 0x02000000
+/** Watchdog Access Error Interrupt
+    Type of interrupt. */
+#define ICU0_IM1_IMR_WDT_AEIR 0x01000000
+/* Indirect Interrupt.
+#define ICU0_IM1_IMR_WDT_AEIR_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM1_IMR_WDT_AEIR_DIR 0x01000000
+/** SYS GPE Interrupt
+    Type of interrupt. */
+#define ICU0_IM1_IMR_SYS_GPE 0x00200000
+/* Indirect Interrupt.
+#define ICU0_IM1_IMR_SYS_GPE_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM1_IMR_SYS_GPE_DIR 0x00200000
+/** SYS1 Interrupt
+    Type of interrupt. */
+#define ICU0_IM1_IMR_SYS1 0x00100000
+/* Indirect Interrupt.
+#define ICU0_IM1_IMR_SYS1_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM1_IMR_SYS1_DIR 0x00100000
+/** PMA Interrupt from IntNode of the RX Clk Domain
+    Type of interrupt. */
+#define ICU0_IM1_IMR_PMA_RX 0x00020000
+/* Indirect Interrupt.
+#define ICU0_IM1_IMR_PMA_RX_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM1_IMR_PMA_RX_DIR 0x00020000
+/** PMA Interrupt from IntNode of the TX Clk Domain
+    Type of interrupt. */
+#define ICU0_IM1_IMR_PMA_TX 0x00010000
+/* Indirect Interrupt.
+#define ICU0_IM1_IMR_PMA_TX_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM1_IMR_PMA_TX_DIR 0x00010000
+/** PMA Interrupt from IntNode of the 200MHz Domain
+    Type of interrupt. */
+#define ICU0_IM1_IMR_PMA_200M 0x00008000
+/* Indirect Interrupt.
+#define ICU0_IM1_IMR_PMA_200M_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM1_IMR_PMA_200M_DIR 0x00008000
+/** Time of Day
+    Type of interrupt. */
+#define ICU0_IM1_IMR_TOD 0x00004000
+/* Indirect Interrupt.
+#define ICU0_IM1_IMR_TOD_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM1_IMR_TOD_DIR 0x00004000
+/** 8kHz root interrupt derived from GPON interface
+    Type of interrupt. */
+#define ICU0_IM1_IMR_FSC_ROOT 0x00002000
+/* Indirect Interrupt.
+#define ICU0_IM1_IMR_FSC_ROOT_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM1_IMR_FSC_ROOT_DIR 0x00002000
+/** FSC Timer Interrupt 1
+    Type of interrupt. */
+#define ICU0_IM1_IMR_FSCT_CMP1 0x00001000
+/* Indirect Interrupt.
+#define ICU0_IM1_IMR_FSCT_CMP1_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM1_IMR_FSCT_CMP1_DIR 0x00001000
+/** FSC Timer Interrupt 0
+    Type of interrupt. */
+#define ICU0_IM1_IMR_FSCT_CMP0 0x00000800
+/* Indirect Interrupt.
+#define ICU0_IM1_IMR_FSCT_CMP0_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM1_IMR_FSCT_CMP0_DIR 0x00000800
+/** 8kHz backup interrupt derived from core-PLL
+    Type of interrupt. */
+#define ICU0_IM1_IMR_FSC_BKP 0x00000400
+/* Indirect Interrupt.
+#define ICU0_IM1_IMR_FSC_BKP_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM1_IMR_FSC_BKP_DIR 0x00000400
+/** External Interrupt from GPIO P4
+    Type of interrupt. */
+#define ICU0_IM1_IMR_P4 0x00000100
+/* Indirect Interrupt.
+#define ICU0_IM1_IMR_P4_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM1_IMR_P4_DIR 0x00000100
+/** External Interrupt from GPIO P3
+    Type of interrupt. */
+#define ICU0_IM1_IMR_P3 0x00000080
+/* Indirect Interrupt.
+#define ICU0_IM1_IMR_P3_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM1_IMR_P3_DIR 0x00000080
+/** External Interrupt from GPIO P2
+    Type of interrupt. */
+#define ICU0_IM1_IMR_P2 0x00000040
+/* Indirect Interrupt.
+#define ICU0_IM1_IMR_P2_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM1_IMR_P2_DIR 0x00000040
+/** External Interrupt from GPIO P1
+    Type of interrupt. */
+#define ICU0_IM1_IMR_P1 0x00000020
+/* Indirect Interrupt.
+#define ICU0_IM1_IMR_P1_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM1_IMR_P1_DIR 0x00000020
+/** External Interrupt from GPIO P0
+    Type of interrupt. */
+#define ICU0_IM1_IMR_P0 0x00000010
+/* Indirect Interrupt.
+#define ICU0_IM1_IMR_P0_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM1_IMR_P0_DIR 0x00000010
+/** EBU Serial Flash Busy
+    Type of interrupt. */
+#define ICU0_IM1_IMR_EBU_SF_BUSY 0x00000004
+/* Indirect Interrupt.
+#define ICU0_IM1_IMR_EBU_SF_BUSY_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM1_IMR_EBU_SF_BUSY_DIR 0x00000004
+/** EBU Serial Flash Command Overwrite Error
+    Type of interrupt. */
+#define ICU0_IM1_IMR_EBU_SF_COVERR 0x00000002
+/* Indirect Interrupt.
+#define ICU0_IM1_IMR_EBU_SF_COVERR_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM1_IMR_EBU_SF_COVERR_DIR 0x00000002
+/** EBU Serial Flash Command Error
+    Type of interrupt. */
+#define ICU0_IM1_IMR_EBU_SF_CMDERR 0x00000001
+/* Indirect Interrupt.
+#define ICU0_IM1_IMR_EBU_SF_CMDERR_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM1_IMR_EBU_SF_CMDERR_DIR 0x00000001
+
+/* Fields of "IM2 Interrupt Status Register" */
+/** EIM Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM2_ISR_EIM 0x80000000
+/* Nothing
+#define ICU0_IM2_ISR_EIM_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM2_ISR_EIM_INTACK 0x80000000
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_ISR_EIM_INTOCC 0x80000000
+/** GTC Upstream Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM2_ISR_GTC_US 0x40000000
+/* Nothing
+#define ICU0_IM2_ISR_GTC_US_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM2_ISR_GTC_US_INTACK 0x40000000
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_ISR_GTC_US_INTOCC 0x40000000
+/** GTC Downstream Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM2_ISR_GTC_DS 0x20000000
+/* Nothing
+#define ICU0_IM2_ISR_GTC_DS_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM2_ISR_GTC_DS_INTACK 0x20000000
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_ISR_GTC_DS_INTOCC 0x20000000
+/** TBM Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM2_ISR_TBM 0x00400000
+/* Nothing
+#define ICU0_IM2_ISR_TBM_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM2_ISR_TBM_INTACK 0x00400000
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_ISR_TBM_INTOCC 0x00400000
+/** Dispatcher Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM2_ISR_DISP 0x00200000
+/* Nothing
+#define ICU0_IM2_ISR_DISP_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM2_ISR_DISP_INTACK 0x00200000
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_ISR_DISP_INTOCC 0x00200000
+/** CONFIG Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM2_ISR_CONFIG 0x00100000
+/* Nothing
+#define ICU0_IM2_ISR_CONFIG_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM2_ISR_CONFIG_INTACK 0x00100000
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_ISR_CONFIG_INTOCC 0x00100000
+/** CONFIG Break Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM2_ISR_CONFIG_BREAK 0x00080000
+/* Nothing
+#define ICU0_IM2_ISR_CONFIG_BREAK_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM2_ISR_CONFIG_BREAK_INTACK 0x00080000
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_ISR_CONFIG_BREAK_INTOCC 0x00080000
+/** OCTRLC Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM2_ISR_OCTRLC 0x00040000
+/* Nothing
+#define ICU0_IM2_ISR_OCTRLC_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM2_ISR_OCTRLC_INTACK 0x00040000
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_ISR_OCTRLC_INTOCC 0x00040000
+/** ICTRLC 1 Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM2_ISR_ICTRLC1 0x00020000
+/* Nothing
+#define ICU0_IM2_ISR_ICTRLC1_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM2_ISR_ICTRLC1_INTACK 0x00020000
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_ISR_ICTRLC1_INTOCC 0x00020000
+/** ICTRLC 0 Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM2_ISR_ICTRLC0 0x00010000
+/* Nothing
+#define ICU0_IM2_ISR_ICTRLC0_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM2_ISR_ICTRLC0_INTACK 0x00010000
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_ISR_ICTRLC0_INTOCC 0x00010000
+/** LINK 1 Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM2_ISR_LINK1 0x00004000
+/* Nothing
+#define ICU0_IM2_ISR_LINK1_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM2_ISR_LINK1_INTACK 0x00004000
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_ISR_LINK1_INTOCC 0x00004000
+/** TMU Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM2_ISR_TMU 0x00001000
+/* Nothing
+#define ICU0_IM2_ISR_TMU_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM2_ISR_TMU_INTACK 0x00001000
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_ISR_TMU_INTOCC 0x00001000
+/** FSQM Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM2_ISR_FSQM 0x00000800
+/* Nothing
+#define ICU0_IM2_ISR_FSQM_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM2_ISR_FSQM_INTACK 0x00000800
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_ISR_FSQM_INTOCC 0x00000800
+/** IQM Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM2_ISR_IQM 0x00000400
+/* Nothing
+#define ICU0_IM2_ISR_IQM_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM2_ISR_IQM_INTACK 0x00000400
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_ISR_IQM_INTOCC 0x00000400
+/** OCTRLG Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM2_ISR_OCTRLG 0x00000200
+/* Nothing
+#define ICU0_IM2_ISR_OCTRLG_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM2_ISR_OCTRLG_INTACK 0x00000200
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_ISR_OCTRLG_INTOCC 0x00000200
+/** OCTRLL 3 Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM2_ISR_OCTRLL3 0x00000080
+/* Nothing
+#define ICU0_IM2_ISR_OCTRLL3_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM2_ISR_OCTRLL3_INTACK 0x00000080
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_ISR_OCTRLL3_INTOCC 0x00000080
+/** OCTRLL 2 Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM2_ISR_OCTRLL2 0x00000040
+/* Nothing
+#define ICU0_IM2_ISR_OCTRLL2_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM2_ISR_OCTRLL2_INTACK 0x00000040
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_ISR_OCTRLL2_INTOCC 0x00000040
+/** OCTRLL 1 Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM2_ISR_OCTRLL1 0x00000020
+/* Nothing
+#define ICU0_IM2_ISR_OCTRLL1_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM2_ISR_OCTRLL1_INTACK 0x00000020
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_ISR_OCTRLL1_INTOCC 0x00000020
+/** OCTRLL 0 Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM2_ISR_OCTRLL0 0x00000010
+/* Nothing
+#define ICU0_IM2_ISR_OCTRLL0_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM2_ISR_OCTRLL0_INTACK 0x00000010
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_ISR_OCTRLL0_INTOCC 0x00000010
+/** ICTRLL 3 Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM2_ISR_ICTRLL3 0x00000008
+/* Nothing
+#define ICU0_IM2_ISR_ICTRLL3_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM2_ISR_ICTRLL3_INTACK 0x00000008
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_ISR_ICTRLL3_INTOCC 0x00000008
+/** ICTRLL 2 Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM2_ISR_ICTRLL2 0x00000004
+/* Nothing
+#define ICU0_IM2_ISR_ICTRLL2_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM2_ISR_ICTRLL2_INTACK 0x00000004
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_ISR_ICTRLL2_INTOCC 0x00000004
+/** ICTRLL 1 Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM2_ISR_ICTRLL1 0x00000002
+/* Nothing
+#define ICU0_IM2_ISR_ICTRLL1_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM2_ISR_ICTRLL1_INTACK 0x00000002
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_ISR_ICTRLL1_INTOCC 0x00000002
+/** ICTRLL 0 Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM2_ISR_ICTRLL0 0x00000001
+/* Nothing
+#define ICU0_IM2_ISR_ICTRLL0_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM2_ISR_ICTRLL0_INTACK 0x00000001
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_ISR_ICTRLL0_INTOCC 0x00000001
+
+/* Fields of "IM2 Interrupt Enable Register" */
+/** EIM Interrupt
+    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IER_EIM 0x80000000
+/* Disable
+#define ICU0_IM2_IER_EIM_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM2_IER_EIM_EN 0x80000000
+/** GTC Upstream Interrupt
+    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IER_GTC_US 0x40000000
+/* Disable
+#define ICU0_IM2_IER_GTC_US_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM2_IER_GTC_US_EN 0x40000000
+/** GTC Downstream Interrupt
+    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IER_GTC_DS 0x20000000
+/* Disable
+#define ICU0_IM2_IER_GTC_DS_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM2_IER_GTC_DS_EN 0x20000000
+/** TBM Interrupt
+    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IER_TBM 0x00400000
+/* Disable
+#define ICU0_IM2_IER_TBM_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM2_IER_TBM_EN 0x00400000
+/** Dispatcher Interrupt
+    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IER_DISP 0x00200000
+/* Disable
+#define ICU0_IM2_IER_DISP_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM2_IER_DISP_EN 0x00200000
+/** CONFIG Interrupt
+    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IER_CONFIG 0x00100000
+/* Disable
+#define ICU0_IM2_IER_CONFIG_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM2_IER_CONFIG_EN 0x00100000
+/** CONFIG Break Interrupt
+    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IER_CONFIG_BREAK 0x00080000
+/* Disable
+#define ICU0_IM2_IER_CONFIG_BREAK_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM2_IER_CONFIG_BREAK_EN 0x00080000
+/** OCTRLC Interrupt
+    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IER_OCTRLC 0x00040000
+/* Disable
+#define ICU0_IM2_IER_OCTRLC_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM2_IER_OCTRLC_EN 0x00040000
+/** ICTRLC 1 Interrupt
+    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IER_ICTRLC1 0x00020000
+/* Disable
+#define ICU0_IM2_IER_ICTRLC1_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM2_IER_ICTRLC1_EN 0x00020000
+/** ICTRLC 0 Interrupt
+    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IER_ICTRLC0 0x00010000
+/* Disable
+#define ICU0_IM2_IER_ICTRLC0_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM2_IER_ICTRLC0_EN 0x00010000
+/** LINK 1 Interrupt
+    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IER_LINK1 0x00004000
+/* Disable
+#define ICU0_IM2_IER_LINK1_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM2_IER_LINK1_EN 0x00004000
+/** TMU Interrupt
+    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IER_TMU 0x00001000
+/* Disable
+#define ICU0_IM2_IER_TMU_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM2_IER_TMU_EN 0x00001000
+/** FSQM Interrupt
+    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IER_FSQM 0x00000800
+/* Disable
+#define ICU0_IM2_IER_FSQM_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM2_IER_FSQM_EN 0x00000800
+/** IQM Interrupt
+    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IER_IQM 0x00000400
+/* Disable
+#define ICU0_IM2_IER_IQM_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM2_IER_IQM_EN 0x00000400
+/** OCTRLG Interrupt
+    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IER_OCTRLG 0x00000200
+/* Disable
+#define ICU0_IM2_IER_OCTRLG_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM2_IER_OCTRLG_EN 0x00000200
+/** OCTRLL 3 Interrupt
+    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IER_OCTRLL3 0x00000080
+/* Disable
+#define ICU0_IM2_IER_OCTRLL3_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM2_IER_OCTRLL3_EN 0x00000080
+/** OCTRLL 2 Interrupt
+    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IER_OCTRLL2 0x00000040
+/* Disable
+#define ICU0_IM2_IER_OCTRLL2_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM2_IER_OCTRLL2_EN 0x00000040
+/** OCTRLL 1 Interrupt
+    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IER_OCTRLL1 0x00000020
+/* Disable
+#define ICU0_IM2_IER_OCTRLL1_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM2_IER_OCTRLL1_EN 0x00000020
+/** OCTRLL 0 Interrupt
+    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IER_OCTRLL0 0x00000010
+/* Disable
+#define ICU0_IM2_IER_OCTRLL0_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM2_IER_OCTRLL0_EN 0x00000010
+/** ICTRLL 3 Interrupt
+    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IER_ICTRLL3 0x00000008
+/* Disable
+#define ICU0_IM2_IER_ICTRLL3_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM2_IER_ICTRLL3_EN 0x00000008
+/** ICTRLL 2 Interrupt
+    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IER_ICTRLL2 0x00000004
+/* Disable
+#define ICU0_IM2_IER_ICTRLL2_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM2_IER_ICTRLL2_EN 0x00000004
+/** ICTRLL 1 Interrupt
+    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IER_ICTRLL1 0x00000002
+/* Disable
+#define ICU0_IM2_IER_ICTRLL1_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM2_IER_ICTRLL1_EN 0x00000002
+/** ICTRLL 0 Interrupt
+    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IER_ICTRLL0 0x00000001
+/* Disable
+#define ICU0_IM2_IER_ICTRLL0_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM2_IER_ICTRLL0_EN 0x00000001
+
+/* Fields of "IM2 Interrupt Output Status Register" */
+/** EIM Interrupt
+    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IOSR_EIM 0x80000000
+/* Nothing
+#define ICU0_IM2_IOSR_EIM_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_IOSR_EIM_INTOCC 0x80000000
+/** GTC Upstream Interrupt
+    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IOSR_GTC_US 0x40000000
+/* Nothing
+#define ICU0_IM2_IOSR_GTC_US_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_IOSR_GTC_US_INTOCC 0x40000000
+/** GTC Downstream Interrupt
+    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IOSR_GTC_DS 0x20000000
+/* Nothing
+#define ICU0_IM2_IOSR_GTC_DS_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_IOSR_GTC_DS_INTOCC 0x20000000
+/** TBM Interrupt
+    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IOSR_TBM 0x00400000
+/* Nothing
+#define ICU0_IM2_IOSR_TBM_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_IOSR_TBM_INTOCC 0x00400000
+/** Dispatcher Interrupt
+    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IOSR_DISP 0x00200000
+/* Nothing
+#define ICU0_IM2_IOSR_DISP_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_IOSR_DISP_INTOCC 0x00200000
+/** CONFIG Interrupt
+    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IOSR_CONFIG 0x00100000
+/* Nothing
+#define ICU0_IM2_IOSR_CONFIG_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_IOSR_CONFIG_INTOCC 0x00100000
+/** CONFIG Break Interrupt
+    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IOSR_CONFIG_BREAK 0x00080000
+/* Nothing
+#define ICU0_IM2_IOSR_CONFIG_BREAK_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_IOSR_CONFIG_BREAK_INTOCC 0x00080000
+/** OCTRLC Interrupt
+    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IOSR_OCTRLC 0x00040000
+/* Nothing
+#define ICU0_IM2_IOSR_OCTRLC_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_IOSR_OCTRLC_INTOCC 0x00040000
+/** ICTRLC 1 Interrupt
+    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IOSR_ICTRLC1 0x00020000
+/* Nothing
+#define ICU0_IM2_IOSR_ICTRLC1_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_IOSR_ICTRLC1_INTOCC 0x00020000
+/** ICTRLC 0 Interrupt
+    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IOSR_ICTRLC0 0x00010000
+/* Nothing
+#define ICU0_IM2_IOSR_ICTRLC0_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_IOSR_ICTRLC0_INTOCC 0x00010000
+/** LINK 1 Interrupt
+    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IOSR_LINK1 0x00004000
+/* Nothing
+#define ICU0_IM2_IOSR_LINK1_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_IOSR_LINK1_INTOCC 0x00004000
+/** TMU Interrupt
+    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IOSR_TMU 0x00001000
+/* Nothing
+#define ICU0_IM2_IOSR_TMU_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_IOSR_TMU_INTOCC 0x00001000
+/** FSQM Interrupt
+    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IOSR_FSQM 0x00000800
+/* Nothing
+#define ICU0_IM2_IOSR_FSQM_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_IOSR_FSQM_INTOCC 0x00000800
+/** IQM Interrupt
+    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IOSR_IQM 0x00000400
+/* Nothing
+#define ICU0_IM2_IOSR_IQM_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_IOSR_IQM_INTOCC 0x00000400
+/** OCTRLG Interrupt
+    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IOSR_OCTRLG 0x00000200
+/* Nothing
+#define ICU0_IM2_IOSR_OCTRLG_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_IOSR_OCTRLG_INTOCC 0x00000200
+/** OCTRLL 3 Interrupt
+    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IOSR_OCTRLL3 0x00000080
+/* Nothing
+#define ICU0_IM2_IOSR_OCTRLL3_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_IOSR_OCTRLL3_INTOCC 0x00000080
+/** OCTRLL 2 Interrupt
+    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IOSR_OCTRLL2 0x00000040
+/* Nothing
+#define ICU0_IM2_IOSR_OCTRLL2_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_IOSR_OCTRLL2_INTOCC 0x00000040
+/** OCTRLL 1 Interrupt
+    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IOSR_OCTRLL1 0x00000020
+/* Nothing
+#define ICU0_IM2_IOSR_OCTRLL1_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_IOSR_OCTRLL1_INTOCC 0x00000020
+/** OCTRLL 0 Interrupt
+    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IOSR_OCTRLL0 0x00000010
+/* Nothing
+#define ICU0_IM2_IOSR_OCTRLL0_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_IOSR_OCTRLL0_INTOCC 0x00000010
+/** ICTRLL 3 Interrupt
+    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IOSR_ICTRLL3 0x00000008
+/* Nothing
+#define ICU0_IM2_IOSR_ICTRLL3_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_IOSR_ICTRLL3_INTOCC 0x00000008
+/** ICTRLL 2 Interrupt
+    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IOSR_ICTRLL2 0x00000004
+/* Nothing
+#define ICU0_IM2_IOSR_ICTRLL2_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_IOSR_ICTRLL2_INTOCC 0x00000004
+/** ICTRLL 1 Interrupt
+    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IOSR_ICTRLL1 0x00000002
+/* Nothing
+#define ICU0_IM2_IOSR_ICTRLL1_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_IOSR_ICTRLL1_INTOCC 0x00000002
+/** ICTRLL 0 Interrupt
+    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IOSR_ICTRLL0 0x00000001
+/* Nothing
+#define ICU0_IM2_IOSR_ICTRLL0_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM2_IOSR_ICTRLL0_INTOCC 0x00000001
+
+/* Fields of "IM2 Interrupt Request Set Register" */
+/** EIM Interrupt
+    Software control for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IRSR_EIM 0x80000000
+/** GTC Upstream Interrupt
+    Software control for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IRSR_GTC_US 0x40000000
+/** GTC Downstream Interrupt
+    Software control for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IRSR_GTC_DS 0x20000000
+/** TBM Interrupt
+    Software control for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IRSR_TBM 0x00400000
+/** Dispatcher Interrupt
+    Software control for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IRSR_DISP 0x00200000
+/** CONFIG Interrupt
+    Software control for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IRSR_CONFIG 0x00100000
+/** CONFIG Break Interrupt
+    Software control for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IRSR_CONFIG_BREAK 0x00080000
+/** OCTRLC Interrupt
+    Software control for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IRSR_OCTRLC 0x00040000
+/** ICTRLC 1 Interrupt
+    Software control for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IRSR_ICTRLC1 0x00020000
+/** ICTRLC 0 Interrupt
+    Software control for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IRSR_ICTRLC0 0x00010000
+/** LINK 1 Interrupt
+    Software control for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IRSR_LINK1 0x00004000
+/** TMU Interrupt
+    Software control for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IRSR_TMU 0x00001000
+/** FSQM Interrupt
+    Software control for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IRSR_FSQM 0x00000800
+/** IQM Interrupt
+    Software control for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IRSR_IQM 0x00000400
+/** OCTRLG Interrupt
+    Software control for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IRSR_OCTRLG 0x00000200
+/** OCTRLL 3 Interrupt
+    Software control for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IRSR_OCTRLL3 0x00000080
+/** OCTRLL 2 Interrupt
+    Software control for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IRSR_OCTRLL2 0x00000040
+/** OCTRLL 1 Interrupt
+    Software control for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IRSR_OCTRLL1 0x00000020
+/** OCTRLL 0 Interrupt
+    Software control for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IRSR_OCTRLL0 0x00000010
+/** ICTRLL 3 Interrupt
+    Software control for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IRSR_ICTRLL3 0x00000008
+/** ICTRLL 2 Interrupt
+    Software control for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IRSR_ICTRLL2 0x00000004
+/** ICTRLL 1 Interrupt
+    Software control for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IRSR_ICTRLL1 0x00000002
+/** ICTRLL 0 Interrupt
+    Software control for the corresponding bit in the IM2_ISR register. */
+#define ICU0_IM2_IRSR_ICTRLL0 0x00000001
+
+/* Fields of "IM2 Interrupt Mode Register" */
+/** EIM Interrupt
+    Type of interrupt. */
+#define ICU0_IM2_IMR_EIM 0x80000000
+/* Indirect Interrupt.
+#define ICU0_IM2_IMR_EIM_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM2_IMR_EIM_DIR 0x80000000
+/** GTC Upstream Interrupt
+    Type of interrupt. */
+#define ICU0_IM2_IMR_GTC_US 0x40000000
+/* Indirect Interrupt.
+#define ICU0_IM2_IMR_GTC_US_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM2_IMR_GTC_US_DIR 0x40000000
+/** GTC Downstream Interrupt
+    Type of interrupt. */
+#define ICU0_IM2_IMR_GTC_DS 0x20000000
+/* Indirect Interrupt.
+#define ICU0_IM2_IMR_GTC_DS_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM2_IMR_GTC_DS_DIR 0x20000000
+/** TBM Interrupt
+    Type of interrupt. */
+#define ICU0_IM2_IMR_TBM 0x00400000
+/* Indirect Interrupt.
+#define ICU0_IM2_IMR_TBM_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM2_IMR_TBM_DIR 0x00400000
+/** Dispatcher Interrupt
+    Type of interrupt. */
+#define ICU0_IM2_IMR_DISP 0x00200000
+/* Indirect Interrupt.
+#define ICU0_IM2_IMR_DISP_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM2_IMR_DISP_DIR 0x00200000
+/** CONFIG Interrupt
+    Type of interrupt. */
+#define ICU0_IM2_IMR_CONFIG 0x00100000
+/* Indirect Interrupt.
+#define ICU0_IM2_IMR_CONFIG_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM2_IMR_CONFIG_DIR 0x00100000
+/** CONFIG Break Interrupt
+    Type of interrupt. */
+#define ICU0_IM2_IMR_CONFIG_BREAK 0x00080000
+/* Indirect Interrupt.
+#define ICU0_IM2_IMR_CONFIG_BREAK_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM2_IMR_CONFIG_BREAK_DIR 0x00080000
+/** OCTRLC Interrupt
+    Type of interrupt. */
+#define ICU0_IM2_IMR_OCTRLC 0x00040000
+/* Indirect Interrupt.
+#define ICU0_IM2_IMR_OCTRLC_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM2_IMR_OCTRLC_DIR 0x00040000
+/** ICTRLC 1 Interrupt
+    Type of interrupt. */
+#define ICU0_IM2_IMR_ICTRLC1 0x00020000
+/* Indirect Interrupt.
+#define ICU0_IM2_IMR_ICTRLC1_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM2_IMR_ICTRLC1_DIR 0x00020000
+/** ICTRLC 0 Interrupt
+    Type of interrupt. */
+#define ICU0_IM2_IMR_ICTRLC0 0x00010000
+/* Indirect Interrupt.
+#define ICU0_IM2_IMR_ICTRLC0_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM2_IMR_ICTRLC0_DIR 0x00010000
+/** LINK 1 Interrupt
+    Type of interrupt. */
+#define ICU0_IM2_IMR_LINK1 0x00004000
+/* Indirect Interrupt.
+#define ICU0_IM2_IMR_LINK1_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM2_IMR_LINK1_DIR 0x00004000
+/** TMU Interrupt
+    Type of interrupt. */
+#define ICU0_IM2_IMR_TMU 0x00001000
+/* Indirect Interrupt.
+#define ICU0_IM2_IMR_TMU_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM2_IMR_TMU_DIR 0x00001000
+/** FSQM Interrupt
+    Type of interrupt. */
+#define ICU0_IM2_IMR_FSQM 0x00000800
+/* Indirect Interrupt.
+#define ICU0_IM2_IMR_FSQM_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM2_IMR_FSQM_DIR 0x00000800
+/** IQM Interrupt
+    Type of interrupt. */
+#define ICU0_IM2_IMR_IQM 0x00000400
+/* Indirect Interrupt.
+#define ICU0_IM2_IMR_IQM_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM2_IMR_IQM_DIR 0x00000400
+/** OCTRLG Interrupt
+    Type of interrupt. */
+#define ICU0_IM2_IMR_OCTRLG 0x00000200
+/* Indirect Interrupt.
+#define ICU0_IM2_IMR_OCTRLG_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM2_IMR_OCTRLG_DIR 0x00000200
+/** OCTRLL 3 Interrupt
+    Type of interrupt. */
+#define ICU0_IM2_IMR_OCTRLL3 0x00000080
+/* Indirect Interrupt.
+#define ICU0_IM2_IMR_OCTRLL3_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM2_IMR_OCTRLL3_DIR 0x00000080
+/** OCTRLL 2 Interrupt
+    Type of interrupt. */
+#define ICU0_IM2_IMR_OCTRLL2 0x00000040
+/* Indirect Interrupt.
+#define ICU0_IM2_IMR_OCTRLL2_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM2_IMR_OCTRLL2_DIR 0x00000040
+/** OCTRLL 1 Interrupt
+    Type of interrupt. */
+#define ICU0_IM2_IMR_OCTRLL1 0x00000020
+/* Indirect Interrupt.
+#define ICU0_IM2_IMR_OCTRLL1_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM2_IMR_OCTRLL1_DIR 0x00000020
+/** OCTRLL 0 Interrupt
+    Type of interrupt. */
+#define ICU0_IM2_IMR_OCTRLL0 0x00000010
+/* Indirect Interrupt.
+#define ICU0_IM2_IMR_OCTRLL0_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM2_IMR_OCTRLL0_DIR 0x00000010
+/** ICTRLL 3 Interrupt
+    Type of interrupt. */
+#define ICU0_IM2_IMR_ICTRLL3 0x00000008
+/* Indirect Interrupt.
+#define ICU0_IM2_IMR_ICTRLL3_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM2_IMR_ICTRLL3_DIR 0x00000008
+/** ICTRLL 2 Interrupt
+    Type of interrupt. */
+#define ICU0_IM2_IMR_ICTRLL2 0x00000004
+/* Indirect Interrupt.
+#define ICU0_IM2_IMR_ICTRLL2_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM2_IMR_ICTRLL2_DIR 0x00000004
+/** ICTRLL 1 Interrupt
+    Type of interrupt. */
+#define ICU0_IM2_IMR_ICTRLL1 0x00000002
+/* Indirect Interrupt.
+#define ICU0_IM2_IMR_ICTRLL1_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM2_IMR_ICTRLL1_DIR 0x00000002
+/** ICTRLL 0 Interrupt
+    Type of interrupt. */
+#define ICU0_IM2_IMR_ICTRLL0 0x00000001
+/* Indirect Interrupt.
+#define ICU0_IM2_IMR_ICTRLL0_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM2_IMR_ICTRLL0_DIR 0x00000001
+
+/* Fields of "IM3 Interrupt Status Register" */
+/** DFEV0, Channel 0 General Purpose Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM3_ISR_DFEV0_1GP 0x80000000
+/* Nothing
+#define ICU0_IM3_ISR_DFEV0_1GP_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_DFEV0_1GP_INTACK 0x80000000
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_DFEV0_1GP_INTOCC 0x80000000
+/** DFEV0, Channel 0 Receive Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM3_ISR_DFEV0_1RX 0x40000000
+/* Nothing
+#define ICU0_IM3_ISR_DFEV0_1RX_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_DFEV0_1RX_INTACK 0x40000000
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_DFEV0_1RX_INTOCC 0x40000000
+/** DFEV0, Channel 0 Transmit Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM3_ISR_DFEV0_1TX 0x20000000
+/* Nothing
+#define ICU0_IM3_ISR_DFEV0_1TX_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_DFEV0_1TX_INTACK 0x20000000
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_DFEV0_1TX_INTOCC 0x20000000
+/** DFEV0, Channel 1 General Purpose Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM3_ISR_DFEV0_2GP 0x10000000
+/* Nothing
+#define ICU0_IM3_ISR_DFEV0_2GP_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_DFEV0_2GP_INTACK 0x10000000
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_DFEV0_2GP_INTOCC 0x10000000
+/** DFEV0, Channel 1 Receive Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM3_ISR_DFEV0_2RX 0x08000000
+/* Nothing
+#define ICU0_IM3_ISR_DFEV0_2RX_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_DFEV0_2RX_INTACK 0x08000000
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_DFEV0_2RX_INTOCC 0x08000000
+/** DFEV0, Channel 1 Transmit Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM3_ISR_DFEV0_2TX 0x04000000
+/* Nothing
+#define ICU0_IM3_ISR_DFEV0_2TX_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_DFEV0_2TX_INTACK 0x04000000
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_DFEV0_2TX_INTOCC 0x04000000
+/** GPTC Timer/Counter 3B Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM3_ISR_GPTC_TC3B 0x00200000
+/* Nothing
+#define ICU0_IM3_ISR_GPTC_TC3B_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_GPTC_TC3B_INTACK 0x00200000
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_GPTC_TC3B_INTOCC 0x00200000
+/** GPTC Timer/Counter 3A Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM3_ISR_GPTC_TC3A 0x00100000
+/* Nothing
+#define ICU0_IM3_ISR_GPTC_TC3A_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_GPTC_TC3A_INTACK 0x00100000
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_GPTC_TC3A_INTOCC 0x00100000
+/** GPTC Timer/Counter 2B Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM3_ISR_GPTC_TC2B 0x00080000
+/* Nothing
+#define ICU0_IM3_ISR_GPTC_TC2B_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_GPTC_TC2B_INTACK 0x00080000
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_GPTC_TC2B_INTOCC 0x00080000
+/** GPTC Timer/Counter 2A Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM3_ISR_GPTC_TC2A 0x00040000
+/* Nothing
+#define ICU0_IM3_ISR_GPTC_TC2A_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_GPTC_TC2A_INTACK 0x00040000
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_GPTC_TC2A_INTOCC 0x00040000
+/** GPTC Timer/Counter 1B Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM3_ISR_GPTC_TC1B 0x00020000
+/* Nothing
+#define ICU0_IM3_ISR_GPTC_TC1B_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_GPTC_TC1B_INTACK 0x00020000
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_GPTC_TC1B_INTOCC 0x00020000
+/** GPTC Timer/Counter 1A Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM3_ISR_GPTC_TC1A 0x00010000
+/* Nothing
+#define ICU0_IM3_ISR_GPTC_TC1A_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_GPTC_TC1A_INTACK 0x00010000
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_GPTC_TC1A_INTOCC 0x00010000
+/** ASC1 Soft Flow Control Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM3_ISR_ASC1_SFC 0x00008000
+/* Nothing
+#define ICU0_IM3_ISR_ASC1_SFC_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_ASC1_SFC_INTACK 0x00008000
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_ASC1_SFC_INTOCC 0x00008000
+/** ASC1 Modem Status Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM3_ISR_ASC1_MS 0x00004000
+/* Nothing
+#define ICU0_IM3_ISR_ASC1_MS_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_ASC1_MS_INTACK 0x00004000
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_ASC1_MS_INTOCC 0x00004000
+/** ASC1 Autobaud Detection Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM3_ISR_ASC1_ABDET 0x00002000
+/* Nothing
+#define ICU0_IM3_ISR_ASC1_ABDET_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_ASC1_ABDET_INTACK 0x00002000
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_ASC1_ABDET_INTOCC 0x00002000
+/** ASC1 Autobaud Start Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM3_ISR_ASC1_ABST 0x00001000
+/* Nothing
+#define ICU0_IM3_ISR_ASC1_ABST_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_ASC1_ABST_INTACK 0x00001000
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_ASC1_ABST_INTOCC 0x00001000
+/** ASC1 Transmit Buffer Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM3_ISR_ASC1_TB 0x00000800
+/* Nothing
+#define ICU0_IM3_ISR_ASC1_TB_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_ASC1_TB_INTACK 0x00000800
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_ASC1_TB_INTOCC 0x00000800
+/** ASC1 Error Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM3_ISR_ASC1_E 0x00000400
+/* Nothing
+#define ICU0_IM3_ISR_ASC1_E_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_ASC1_E_INTACK 0x00000400
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_ASC1_E_INTOCC 0x00000400
+/** ASC1 Receive Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM3_ISR_ASC1_R 0x00000200
+/* Nothing
+#define ICU0_IM3_ISR_ASC1_R_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_ASC1_R_INTACK 0x00000200
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_ASC1_R_INTOCC 0x00000200
+/** ASC1 Transmit Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM3_ISR_ASC1_T 0x00000100
+/* Nothing
+#define ICU0_IM3_ISR_ASC1_T_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_ASC1_T_INTACK 0x00000100
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_ASC1_T_INTOCC 0x00000100
+/** ASC0 Soft Flow Control Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM3_ISR_ASC0_SFC 0x00000080
+/* Nothing
+#define ICU0_IM3_ISR_ASC0_SFC_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_ASC0_SFC_INTACK 0x00000080
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_ASC0_SFC_INTOCC 0x00000080
+/** ASC1 Modem Status Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM3_ISR_ASC0_MS 0x00000040
+/* Nothing
+#define ICU0_IM3_ISR_ASC0_MS_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_ASC0_MS_INTACK 0x00000040
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_ASC0_MS_INTOCC 0x00000040
+/** ASC0 Autobaud Detection Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM3_ISR_ASC0_ABDET 0x00000020
+/* Nothing
+#define ICU0_IM3_ISR_ASC0_ABDET_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_ASC0_ABDET_INTACK 0x00000020
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_ASC0_ABDET_INTOCC 0x00000020
+/** ASC0 Autobaud Start Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM3_ISR_ASC0_ABST 0x00000010
+/* Nothing
+#define ICU0_IM3_ISR_ASC0_ABST_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_ASC0_ABST_INTACK 0x00000010
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_ASC0_ABST_INTOCC 0x00000010
+/** ASC0 Transmit Buffer Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM3_ISR_ASC0_TB 0x00000008
+/* Nothing
+#define ICU0_IM3_ISR_ASC0_TB_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_ASC0_TB_INTACK 0x00000008
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_ASC0_TB_INTOCC 0x00000008
+/** ASC0 Error Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM3_ISR_ASC0_E 0x00000004
+/* Nothing
+#define ICU0_IM3_ISR_ASC0_E_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_ASC0_E_INTACK 0x00000004
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_ASC0_E_INTOCC 0x00000004
+/** ASC0 Receive Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM3_ISR_ASC0_R 0x00000002
+/* Nothing
+#define ICU0_IM3_ISR_ASC0_R_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_ASC0_R_INTACK 0x00000002
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_ASC0_R_INTOCC 0x00000002
+/** ASC0 Transmit Interrupt
+    This bit is a direct interrupt. */
+#define ICU0_IM3_ISR_ASC0_T 0x00000001
+/* Nothing
+#define ICU0_IM3_ISR_ASC0_T_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM3_ISR_ASC0_T_INTACK 0x00000001
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_ISR_ASC0_T_INTOCC 0x00000001
+
+/* Fields of "IM3 Interrupt Enable Register" */
+/** DFEV0, Channel 0 General Purpose Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_DFEV0_1GP 0x80000000
+/* Disable
+#define ICU0_IM3_IER_DFEV0_1GP_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_DFEV0_1GP_EN 0x80000000
+/** DFEV0, Channel 0 Receive Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_DFEV0_1RX 0x40000000
+/* Disable
+#define ICU0_IM3_IER_DFEV0_1RX_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_DFEV0_1RX_EN 0x40000000
+/** DFEV0, Channel 0 Transmit Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_DFEV0_1TX 0x20000000
+/* Disable
+#define ICU0_IM3_IER_DFEV0_1TX_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_DFEV0_1TX_EN 0x20000000
+/** DFEV0, Channel 1 General Purpose Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_DFEV0_2GP 0x10000000
+/* Disable
+#define ICU0_IM3_IER_DFEV0_2GP_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_DFEV0_2GP_EN 0x10000000
+/** DFEV0, Channel 1 Receive Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_DFEV0_2RX 0x08000000
+/* Disable
+#define ICU0_IM3_IER_DFEV0_2RX_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_DFEV0_2RX_EN 0x08000000
+/** DFEV0, Channel 1 Transmit Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_DFEV0_2TX 0x04000000
+/* Disable
+#define ICU0_IM3_IER_DFEV0_2TX_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_DFEV0_2TX_EN 0x04000000
+/** GPTC Timer/Counter 3B Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_GPTC_TC3B 0x00200000
+/* Disable
+#define ICU0_IM3_IER_GPTC_TC3B_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_GPTC_TC3B_EN 0x00200000
+/** GPTC Timer/Counter 3A Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_GPTC_TC3A 0x00100000
+/* Disable
+#define ICU0_IM3_IER_GPTC_TC3A_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_GPTC_TC3A_EN 0x00100000
+/** GPTC Timer/Counter 2B Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_GPTC_TC2B 0x00080000
+/* Disable
+#define ICU0_IM3_IER_GPTC_TC2B_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_GPTC_TC2B_EN 0x00080000
+/** GPTC Timer/Counter 2A Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_GPTC_TC2A 0x00040000
+/* Disable
+#define ICU0_IM3_IER_GPTC_TC2A_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_GPTC_TC2A_EN 0x00040000
+/** GPTC Timer/Counter 1B Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_GPTC_TC1B 0x00020000
+/* Disable
+#define ICU0_IM3_IER_GPTC_TC1B_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_GPTC_TC1B_EN 0x00020000
+/** GPTC Timer/Counter 1A Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_GPTC_TC1A 0x00010000
+/* Disable
+#define ICU0_IM3_IER_GPTC_TC1A_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_GPTC_TC1A_EN 0x00010000
+/** ASC1 Soft Flow Control Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_ASC1_SFC 0x00008000
+/* Disable
+#define ICU0_IM3_IER_ASC1_SFC_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_ASC1_SFC_EN 0x00008000
+/** ASC1 Modem Status Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_ASC1_MS 0x00004000
+/* Disable
+#define ICU0_IM3_IER_ASC1_MS_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_ASC1_MS_EN 0x00004000
+/** ASC1 Autobaud Detection Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_ASC1_ABDET 0x00002000
+/* Disable
+#define ICU0_IM3_IER_ASC1_ABDET_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_ASC1_ABDET_EN 0x00002000
+/** ASC1 Autobaud Start Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_ASC1_ABST 0x00001000
+/* Disable
+#define ICU0_IM3_IER_ASC1_ABST_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_ASC1_ABST_EN 0x00001000
+/** ASC1 Transmit Buffer Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_ASC1_TB 0x00000800
+/* Disable
+#define ICU0_IM3_IER_ASC1_TB_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_ASC1_TB_EN 0x00000800
+/** ASC1 Error Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_ASC1_E 0x00000400
+/* Disable
+#define ICU0_IM3_IER_ASC1_E_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_ASC1_E_EN 0x00000400
+/** ASC1 Receive Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_ASC1_R 0x00000200
+/* Disable
+#define ICU0_IM3_IER_ASC1_R_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_ASC1_R_EN 0x00000200
+/** ASC1 Transmit Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_ASC1_T 0x00000100
+/* Disable
+#define ICU0_IM3_IER_ASC1_T_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_ASC1_T_EN 0x00000100
+/** ASC0 Soft Flow Control Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_ASC0_SFC 0x00000080
+/* Disable
+#define ICU0_IM3_IER_ASC0_SFC_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_ASC0_SFC_EN 0x00000080
+/** ASC1 Modem Status Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_ASC0_MS 0x00000040
+/* Disable
+#define ICU0_IM3_IER_ASC0_MS_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_ASC0_MS_EN 0x00000040
+/** ASC0 Autobaud Detection Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_ASC0_ABDET 0x00000020
+/* Disable
+#define ICU0_IM3_IER_ASC0_ABDET_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_ASC0_ABDET_EN 0x00000020
+/** ASC0 Autobaud Start Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_ASC0_ABST 0x00000010
+/* Disable
+#define ICU0_IM3_IER_ASC0_ABST_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_ASC0_ABST_EN 0x00000010
+/** ASC0 Transmit Buffer Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_ASC0_TB 0x00000008
+/* Disable
+#define ICU0_IM3_IER_ASC0_TB_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_ASC0_TB_EN 0x00000008
+/** ASC0 Error Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_ASC0_E 0x00000004
+/* Disable
+#define ICU0_IM3_IER_ASC0_E_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_ASC0_E_EN 0x00000004
+/** ASC0 Receive Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_ASC0_R 0x00000002
+/* Disable
+#define ICU0_IM3_IER_ASC0_R_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_ASC0_R_EN 0x00000002
+/** ASC0 Transmit Interrupt
+    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IER_ASC0_T 0x00000001
+/* Disable
+#define ICU0_IM3_IER_ASC0_T_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM3_IER_ASC0_T_EN 0x00000001
+
+/* Fields of "IM3 Interrupt Output Status Register" */
+/** DFEV0, Channel 0 General Purpose Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_DFEV0_1GP 0x80000000
+/* Nothing
+#define ICU0_IM3_IOSR_DFEV0_1GP_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_DFEV0_1GP_INTOCC 0x80000000
+/** DFEV0, Channel 0 Receive Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_DFEV0_1RX 0x40000000
+/* Nothing
+#define ICU0_IM3_IOSR_DFEV0_1RX_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_DFEV0_1RX_INTOCC 0x40000000
+/** DFEV0, Channel 0 Transmit Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_DFEV0_1TX 0x20000000
+/* Nothing
+#define ICU0_IM3_IOSR_DFEV0_1TX_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_DFEV0_1TX_INTOCC 0x20000000
+/** DFEV0, Channel 1 General Purpose Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_DFEV0_2GP 0x10000000
+/* Nothing
+#define ICU0_IM3_IOSR_DFEV0_2GP_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_DFEV0_2GP_INTOCC 0x10000000
+/** DFEV0, Channel 1 Receive Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_DFEV0_2RX 0x08000000
+/* Nothing
+#define ICU0_IM3_IOSR_DFEV0_2RX_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_DFEV0_2RX_INTOCC 0x08000000
+/** DFEV0, Channel 1 Transmit Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_DFEV0_2TX 0x04000000
+/* Nothing
+#define ICU0_IM3_IOSR_DFEV0_2TX_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_DFEV0_2TX_INTOCC 0x04000000
+/** GPTC Timer/Counter 3B Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_GPTC_TC3B 0x00200000
+/* Nothing
+#define ICU0_IM3_IOSR_GPTC_TC3B_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_GPTC_TC3B_INTOCC 0x00200000
+/** GPTC Timer/Counter 3A Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_GPTC_TC3A 0x00100000
+/* Nothing
+#define ICU0_IM3_IOSR_GPTC_TC3A_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_GPTC_TC3A_INTOCC 0x00100000
+/** GPTC Timer/Counter 2B Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_GPTC_TC2B 0x00080000
+/* Nothing
+#define ICU0_IM3_IOSR_GPTC_TC2B_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_GPTC_TC2B_INTOCC 0x00080000
+/** GPTC Timer/Counter 2A Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_GPTC_TC2A 0x00040000
+/* Nothing
+#define ICU0_IM3_IOSR_GPTC_TC2A_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_GPTC_TC2A_INTOCC 0x00040000
+/** GPTC Timer/Counter 1B Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_GPTC_TC1B 0x00020000
+/* Nothing
+#define ICU0_IM3_IOSR_GPTC_TC1B_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_GPTC_TC1B_INTOCC 0x00020000
+/** GPTC Timer/Counter 1A Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_GPTC_TC1A 0x00010000
+/* Nothing
+#define ICU0_IM3_IOSR_GPTC_TC1A_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_GPTC_TC1A_INTOCC 0x00010000
+/** ASC1 Soft Flow Control Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_ASC1_SFC 0x00008000
+/* Nothing
+#define ICU0_IM3_IOSR_ASC1_SFC_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_ASC1_SFC_INTOCC 0x00008000
+/** ASC1 Modem Status Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_ASC1_MS 0x00004000
+/* Nothing
+#define ICU0_IM3_IOSR_ASC1_MS_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_ASC1_MS_INTOCC 0x00004000
+/** ASC1 Autobaud Detection Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_ASC1_ABDET 0x00002000
+/* Nothing
+#define ICU0_IM3_IOSR_ASC1_ABDET_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_ASC1_ABDET_INTOCC 0x00002000
+/** ASC1 Autobaud Start Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_ASC1_ABST 0x00001000
+/* Nothing
+#define ICU0_IM3_IOSR_ASC1_ABST_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_ASC1_ABST_INTOCC 0x00001000
+/** ASC1 Transmit Buffer Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_ASC1_TB 0x00000800
+/* Nothing
+#define ICU0_IM3_IOSR_ASC1_TB_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_ASC1_TB_INTOCC 0x00000800
+/** ASC1 Error Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_ASC1_E 0x00000400
+/* Nothing
+#define ICU0_IM3_IOSR_ASC1_E_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_ASC1_E_INTOCC 0x00000400
+/** ASC1 Receive Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_ASC1_R 0x00000200
+/* Nothing
+#define ICU0_IM3_IOSR_ASC1_R_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_ASC1_R_INTOCC 0x00000200
+/** ASC1 Transmit Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_ASC1_T 0x00000100
+/* Nothing
+#define ICU0_IM3_IOSR_ASC1_T_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_ASC1_T_INTOCC 0x00000100
+/** ASC0 Soft Flow Control Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_ASC0_SFC 0x00000080
+/* Nothing
+#define ICU0_IM3_IOSR_ASC0_SFC_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_ASC0_SFC_INTOCC 0x00000080
+/** ASC1 Modem Status Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_ASC0_MS 0x00000040
+/* Nothing
+#define ICU0_IM3_IOSR_ASC0_MS_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_ASC0_MS_INTOCC 0x00000040
+/** ASC0 Autobaud Detection Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_ASC0_ABDET 0x00000020
+/* Nothing
+#define ICU0_IM3_IOSR_ASC0_ABDET_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_ASC0_ABDET_INTOCC 0x00000020
+/** ASC0 Autobaud Start Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_ASC0_ABST 0x00000010
+/* Nothing
+#define ICU0_IM3_IOSR_ASC0_ABST_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_ASC0_ABST_INTOCC 0x00000010
+/** ASC0 Transmit Buffer Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_ASC0_TB 0x00000008
+/* Nothing
+#define ICU0_IM3_IOSR_ASC0_TB_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_ASC0_TB_INTOCC 0x00000008
+/** ASC0 Error Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_ASC0_E 0x00000004
+/* Nothing
+#define ICU0_IM3_IOSR_ASC0_E_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_ASC0_E_INTOCC 0x00000004
+/** ASC0 Receive Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_ASC0_R 0x00000002
+/* Nothing
+#define ICU0_IM3_IOSR_ASC0_R_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_ASC0_R_INTOCC 0x00000002
+/** ASC0 Transmit Interrupt
+    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IOSR_ASC0_T 0x00000001
+/* Nothing
+#define ICU0_IM3_IOSR_ASC0_T_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM3_IOSR_ASC0_T_INTOCC 0x00000001
+
+/* Fields of "IM3 Interrupt Request Set Register" */
+/** DFEV0, Channel 0 General Purpose Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_DFEV0_1GP 0x80000000
+/** DFEV0, Channel 0 Receive Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_DFEV0_1RX 0x40000000
+/** DFEV0, Channel 0 Transmit Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_DFEV0_1TX 0x20000000
+/** DFEV0, Channel 1 General Purpose Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_DFEV0_2GP 0x10000000
+/** DFEV0, Channel 1 Receive Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_DFEV0_2RX 0x08000000
+/** DFEV0, Channel 1 Transmit Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_DFEV0_2TX 0x04000000
+/** GPTC Timer/Counter 3B Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_GPTC_TC3B 0x00200000
+/** GPTC Timer/Counter 3A Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_GPTC_TC3A 0x00100000
+/** GPTC Timer/Counter 2B Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_GPTC_TC2B 0x00080000
+/** GPTC Timer/Counter 2A Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_GPTC_TC2A 0x00040000
+/** GPTC Timer/Counter 1B Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_GPTC_TC1B 0x00020000
+/** GPTC Timer/Counter 1A Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_GPTC_TC1A 0x00010000
+/** ASC1 Soft Flow Control Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_ASC1_SFC 0x00008000
+/** ASC1 Modem Status Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_ASC1_MS 0x00004000
+/** ASC1 Autobaud Detection Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_ASC1_ABDET 0x00002000
+/** ASC1 Autobaud Start Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_ASC1_ABST 0x00001000
+/** ASC1 Transmit Buffer Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_ASC1_TB 0x00000800
+/** ASC1 Error Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_ASC1_E 0x00000400
+/** ASC1 Receive Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_ASC1_R 0x00000200
+/** ASC1 Transmit Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_ASC1_T 0x00000100
+/** ASC0 Soft Flow Control Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_ASC0_SFC 0x00000080
+/** ASC1 Modem Status Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_ASC0_MS 0x00000040
+/** ASC0 Autobaud Detection Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_ASC0_ABDET 0x00000020
+/** ASC0 Autobaud Start Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_ASC0_ABST 0x00000010
+/** ASC0 Transmit Buffer Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_ASC0_TB 0x00000008
+/** ASC0 Error Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_ASC0_E 0x00000004
+/** ASC0 Receive Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_ASC0_R 0x00000002
+/** ASC0 Transmit Interrupt
+    Software control for the corresponding bit in the IM3_ISR register. */
+#define ICU0_IM3_IRSR_ASC0_T 0x00000001
+
+/* Fields of "IM3 Interrupt Mode Register" */
+/** DFEV0, Channel 0 General Purpose Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_DFEV0_1GP 0x80000000
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_DFEV0_1GP_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_DFEV0_1GP_DIR 0x80000000
+/** DFEV0, Channel 0 Receive Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_DFEV0_1RX 0x40000000
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_DFEV0_1RX_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_DFEV0_1RX_DIR 0x40000000
+/** DFEV0, Channel 0 Transmit Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_DFEV0_1TX 0x20000000
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_DFEV0_1TX_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_DFEV0_1TX_DIR 0x20000000
+/** DFEV0, Channel 1 General Purpose Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_DFEV0_2GP 0x10000000
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_DFEV0_2GP_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_DFEV0_2GP_DIR 0x10000000
+/** DFEV0, Channel 1 Receive Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_DFEV0_2RX 0x08000000
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_DFEV0_2RX_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_DFEV0_2RX_DIR 0x08000000
+/** DFEV0, Channel 1 Transmit Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_DFEV0_2TX 0x04000000
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_DFEV0_2TX_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_DFEV0_2TX_DIR 0x04000000
+/** GPTC Timer/Counter 3B Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_GPTC_TC3B 0x00200000
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_GPTC_TC3B_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_GPTC_TC3B_DIR 0x00200000
+/** GPTC Timer/Counter 3A Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_GPTC_TC3A 0x00100000
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_GPTC_TC3A_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_GPTC_TC3A_DIR 0x00100000
+/** GPTC Timer/Counter 2B Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_GPTC_TC2B 0x00080000
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_GPTC_TC2B_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_GPTC_TC2B_DIR 0x00080000
+/** GPTC Timer/Counter 2A Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_GPTC_TC2A 0x00040000
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_GPTC_TC2A_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_GPTC_TC2A_DIR 0x00040000
+/** GPTC Timer/Counter 1B Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_GPTC_TC1B 0x00020000
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_GPTC_TC1B_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_GPTC_TC1B_DIR 0x00020000
+/** GPTC Timer/Counter 1A Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_GPTC_TC1A 0x00010000
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_GPTC_TC1A_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_GPTC_TC1A_DIR 0x00010000
+/** ASC1 Soft Flow Control Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_ASC1_SFC 0x00008000
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_ASC1_SFC_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_ASC1_SFC_DIR 0x00008000
+/** ASC1 Modem Status Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_ASC1_MS 0x00004000
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_ASC1_MS_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_ASC1_MS_DIR 0x00004000
+/** ASC1 Autobaud Detection Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_ASC1_ABDET 0x00002000
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_ASC1_ABDET_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_ASC1_ABDET_DIR 0x00002000
+/** ASC1 Autobaud Start Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_ASC1_ABST 0x00001000
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_ASC1_ABST_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_ASC1_ABST_DIR 0x00001000
+/** ASC1 Transmit Buffer Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_ASC1_TB 0x00000800
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_ASC1_TB_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_ASC1_TB_DIR 0x00000800
+/** ASC1 Error Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_ASC1_E 0x00000400
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_ASC1_E_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_ASC1_E_DIR 0x00000400
+/** ASC1 Receive Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_ASC1_R 0x00000200
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_ASC1_R_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_ASC1_R_DIR 0x00000200
+/** ASC1 Transmit Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_ASC1_T 0x00000100
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_ASC1_T_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_ASC1_T_DIR 0x00000100
+/** ASC0 Soft Flow Control Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_ASC0_SFC 0x00000080
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_ASC0_SFC_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_ASC0_SFC_DIR 0x00000080
+/** ASC1 Modem Status Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_ASC0_MS 0x00000040
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_ASC0_MS_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_ASC0_MS_DIR 0x00000040
+/** ASC0 Autobaud Detection Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_ASC0_ABDET 0x00000020
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_ASC0_ABDET_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_ASC0_ABDET_DIR 0x00000020
+/** ASC0 Autobaud Start Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_ASC0_ABST 0x00000010
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_ASC0_ABST_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_ASC0_ABST_DIR 0x00000010
+/** ASC0 Transmit Buffer Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_ASC0_TB 0x00000008
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_ASC0_TB_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_ASC0_TB_DIR 0x00000008
+/** ASC0 Error Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_ASC0_E 0x00000004
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_ASC0_E_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_ASC0_E_DIR 0x00000004
+/** ASC0 Receive Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_ASC0_R 0x00000002
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_ASC0_R_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_ASC0_R_DIR 0x00000002
+/** ASC0 Transmit Interrupt
+    Type of interrupt. */
+#define ICU0_IM3_IMR_ASC0_T 0x00000001
+/* Indirect Interrupt.
+#define ICU0_IM3_IMR_ASC0_T_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM3_IMR_ASC0_T_DIR 0x00000001
+
+/* Fields of "IM4 Interrupt Status Register" */
+/** VPE0 Performance Monitoring Counter Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM4_ISR_VPE0_PMCIR 0x80000000
+/* Nothing
+#define ICU0_IM4_ISR_VPE0_PMCIR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM4_ISR_VPE0_PMCIR_INTACK 0x80000000
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_ISR_VPE0_PMCIR_INTOCC 0x80000000
+/** VPE0 Error Level Flag Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM4_ISR_VPE0_ERL 0x40000000
+/* Nothing
+#define ICU0_IM4_ISR_VPE0_ERL_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM4_ISR_VPE0_ERL_INTACK 0x40000000
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_ISR_VPE0_ERL_INTOCC 0x40000000
+/** VPE0 Exception Level Flag Interrupt
+    This bit is an indirect interrupt. */
+#define ICU0_IM4_ISR_VPE0_EXL 0x20000000
+/* Nothing
+#define ICU0_IM4_ISR_VPE0_EXL_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM4_ISR_VPE0_EXL_INTACK 0x20000000
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_ISR_VPE0_EXL_INTOCC 0x20000000
+/** MPS Bin. Sem Interrupt to VPE0
+    This bit is an indirect interrupt. */
+#define ICU0_IM4_ISR_MPS_IR8 0x00400000
+/* Nothing
+#define ICU0_IM4_ISR_MPS_IR8_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM4_ISR_MPS_IR8_INTACK 0x00400000
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_ISR_MPS_IR8_INTOCC 0x00400000
+/** MPS Global Interrupt to VPE0
+    This bit is an indirect interrupt. */
+#define ICU0_IM4_ISR_MPS_IR7 0x00200000
+/* Nothing
+#define ICU0_IM4_ISR_MPS_IR7_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM4_ISR_MPS_IR7_INTACK 0x00200000
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_ISR_MPS_IR7_INTOCC 0x00200000
+/** MPS Status Interrupt #6 (VPE1 to VPE0)
+    This bit is an indirect interrupt. */
+#define ICU0_IM4_ISR_MPS_IR6 0x00100000
+/* Nothing
+#define ICU0_IM4_ISR_MPS_IR6_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM4_ISR_MPS_IR6_INTACK 0x00100000
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_ISR_MPS_IR6_INTOCC 0x00100000
+/** MPS Status Interrupt #5 (VPE1 to VPE0)
+    This bit is an indirect interrupt. */
+#define ICU0_IM4_ISR_MPS_IR5 0x00080000
+/* Nothing
+#define ICU0_IM4_ISR_MPS_IR5_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM4_ISR_MPS_IR5_INTACK 0x00080000
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_ISR_MPS_IR5_INTOCC 0x00080000
+/** MPS Status Interrupt #4 (VPE1 to VPE0)
+    This bit is an indirect interrupt. */
+#define ICU0_IM4_ISR_MPS_IR4 0x00040000
+/* Nothing
+#define ICU0_IM4_ISR_MPS_IR4_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM4_ISR_MPS_IR4_INTACK 0x00040000
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_ISR_MPS_IR4_INTOCC 0x00040000
+/** MPS Status Interrupt #3 (VPE1 to VPE0)
+    This bit is an indirect interrupt. */
+#define ICU0_IM4_ISR_MPS_IR3 0x00020000
+/* Nothing
+#define ICU0_IM4_ISR_MPS_IR3_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM4_ISR_MPS_IR3_INTACK 0x00020000
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_ISR_MPS_IR3_INTOCC 0x00020000
+/** MPS Status Interrupt #2 (VPE1 to VPE0)
+    This bit is an indirect interrupt. */
+#define ICU0_IM4_ISR_MPS_IR2 0x00010000
+/* Nothing
+#define ICU0_IM4_ISR_MPS_IR2_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM4_ISR_MPS_IR2_INTACK 0x00010000
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_ISR_MPS_IR2_INTOCC 0x00010000
+/** MPS Status Interrupt #1 (VPE1 to VPE0)
+    This bit is an indirect interrupt. */
+#define ICU0_IM4_ISR_MPS_IR1 0x00008000
+/* Nothing
+#define ICU0_IM4_ISR_MPS_IR1_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM4_ISR_MPS_IR1_INTACK 0x00008000
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_ISR_MPS_IR1_INTOCC 0x00008000
+/** MPS Status Interrupt #0 (VPE1 to VPE0)
+    This bit is an indirect interrupt. */
+#define ICU0_IM4_ISR_MPS_IR0 0x00004000
+/* Nothing
+#define ICU0_IM4_ISR_MPS_IR0_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM4_ISR_MPS_IR0_INTACK 0x00004000
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_ISR_MPS_IR0_INTOCC 0x00004000
+/** TMU Error
+    This bit is an indirect interrupt. */
+#define ICU0_IM4_ISR_TMU_ERR 0x00001000
+/* Nothing
+#define ICU0_IM4_ISR_TMU_ERR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM4_ISR_TMU_ERR_INTACK 0x00001000
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_ISR_TMU_ERR_INTOCC 0x00001000
+/** FSQM Error
+    This bit is an indirect interrupt. */
+#define ICU0_IM4_ISR_FSQM_ERR 0x00000800
+/* Nothing
+#define ICU0_IM4_ISR_FSQM_ERR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM4_ISR_FSQM_ERR_INTACK 0x00000800
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_ISR_FSQM_ERR_INTOCC 0x00000800
+/** IQM Error
+    This bit is an indirect interrupt. */
+#define ICU0_IM4_ISR_IQM_ERR 0x00000400
+/* Nothing
+#define ICU0_IM4_ISR_IQM_ERR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM4_ISR_IQM_ERR_INTACK 0x00000400
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_ISR_IQM_ERR_INTOCC 0x00000400
+/** OCTRLG Error
+    This bit is an indirect interrupt. */
+#define ICU0_IM4_ISR_OCTRLG_ERR 0x00000200
+/* Nothing
+#define ICU0_IM4_ISR_OCTRLG_ERR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM4_ISR_OCTRLG_ERR_INTACK 0x00000200
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_ISR_OCTRLG_ERR_INTOCC 0x00000200
+/** ICTRLG Error
+    This bit is an indirect interrupt. */
+#define ICU0_IM4_ISR_ICTRLG_ERR 0x00000100
+/* Nothing
+#define ICU0_IM4_ISR_ICTRLG_ERR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM4_ISR_ICTRLG_ERR_INTACK 0x00000100
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_ISR_ICTRLG_ERR_INTOCC 0x00000100
+/** OCTRLL 3 Error
+    This bit is an indirect interrupt. */
+#define ICU0_IM4_ISR_OCTRLL3_ERR 0x00000080
+/* Nothing
+#define ICU0_IM4_ISR_OCTRLL3_ERR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM4_ISR_OCTRLL3_ERR_INTACK 0x00000080
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_ISR_OCTRLL3_ERR_INTOCC 0x00000080
+/** OCTRLL 2 Error
+    This bit is an indirect interrupt. */
+#define ICU0_IM4_ISR_OCTRLL2_ERR 0x00000040
+/* Nothing
+#define ICU0_IM4_ISR_OCTRLL2_ERR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM4_ISR_OCTRLL2_ERR_INTACK 0x00000040
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_ISR_OCTRLL2_ERR_INTOCC 0x00000040
+/** OCTRLL 1 Error
+    This bit is an indirect interrupt. */
+#define ICU0_IM4_ISR_OCTRLL1_ERR 0x00000020
+/* Nothing
+#define ICU0_IM4_ISR_OCTRLL1_ERR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM4_ISR_OCTRLL1_ERR_INTACK 0x00000020
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_ISR_OCTRLL1_ERR_INTOCC 0x00000020
+/** OCTRLL 0 Error
+    This bit is an indirect interrupt. */
+#define ICU0_IM4_ISR_OCTRLL0_ERR 0x00000010
+/* Nothing
+#define ICU0_IM4_ISR_OCTRLL0_ERR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM4_ISR_OCTRLL0_ERR_INTACK 0x00000010
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_ISR_OCTRLL0_ERR_INTOCC 0x00000010
+/** ICTRLL 3 Error
+    This bit is an indirect interrupt. */
+#define ICU0_IM4_ISR_ICTRLL3_ERR 0x00000008
+/* Nothing
+#define ICU0_IM4_ISR_ICTRLL3_ERR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM4_ISR_ICTRLL3_ERR_INTACK 0x00000008
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_ISR_ICTRLL3_ERR_INTOCC 0x00000008
+/** ICTRLL 2 Error
+    This bit is an indirect interrupt. */
+#define ICU0_IM4_ISR_ICTRLL2_ERR 0x00000004
+/* Nothing
+#define ICU0_IM4_ISR_ICTRLL2_ERR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM4_ISR_ICTRLL2_ERR_INTACK 0x00000004
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_ISR_ICTRLL2_ERR_INTOCC 0x00000004
+/** ICTRLL 1 Error
+    This bit is an indirect interrupt. */
+#define ICU0_IM4_ISR_ICTRLL1_ERR 0x00000002
+/* Nothing
+#define ICU0_IM4_ISR_ICTRLL1_ERR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM4_ISR_ICTRLL1_ERR_INTACK 0x00000002
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_ISR_ICTRLL1_ERR_INTOCC 0x00000002
+/** ICTRLL 0 Error
+    This bit is an indirect interrupt. */
+#define ICU0_IM4_ISR_ICTRLL0_ERR 0x00000001
+/* Nothing
+#define ICU0_IM4_ISR_ICTRLL0_ERR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define ICU0_IM4_ISR_ICTRLL0_ERR_INTACK 0x00000001
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_ISR_ICTRLL0_ERR_INTOCC 0x00000001
+
+/* Fields of "IM4 Interrupt Enable Register" */
+/** VPE0 Performance Monitoring Counter Interrupt
+    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IER_VPE0_PMCIR 0x80000000
+/* Disable
+#define ICU0_IM4_IER_VPE0_PMCIR_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM4_IER_VPE0_PMCIR_EN 0x80000000
+/** VPE0 Error Level Flag Interrupt
+    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IER_VPE0_ERL 0x40000000
+/* Disable
+#define ICU0_IM4_IER_VPE0_ERL_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM4_IER_VPE0_ERL_EN 0x40000000
+/** VPE0 Exception Level Flag Interrupt
+    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IER_VPE0_EXL 0x20000000
+/* Disable
+#define ICU0_IM4_IER_VPE0_EXL_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM4_IER_VPE0_EXL_EN 0x20000000
+/** MPS Bin. Sem Interrupt to VPE0
+    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IER_MPS_IR8 0x00400000
+/* Disable
+#define ICU0_IM4_IER_MPS_IR8_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM4_IER_MPS_IR8_EN 0x00400000
+/** MPS Global Interrupt to VPE0
+    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IER_MPS_IR7 0x00200000
+/* Disable
+#define ICU0_IM4_IER_MPS_IR7_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM4_IER_MPS_IR7_EN 0x00200000
+/** MPS Status Interrupt #6 (VPE1 to VPE0)
+    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IER_MPS_IR6 0x00100000
+/* Disable
+#define ICU0_IM4_IER_MPS_IR6_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM4_IER_MPS_IR6_EN 0x00100000
+/** MPS Status Interrupt #5 (VPE1 to VPE0)
+    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IER_MPS_IR5 0x00080000
+/* Disable
+#define ICU0_IM4_IER_MPS_IR5_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM4_IER_MPS_IR5_EN 0x00080000
+/** MPS Status Interrupt #4 (VPE1 to VPE0)
+    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IER_MPS_IR4 0x00040000
+/* Disable
+#define ICU0_IM4_IER_MPS_IR4_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM4_IER_MPS_IR4_EN 0x00040000
+/** MPS Status Interrupt #3 (VPE1 to VPE0)
+    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IER_MPS_IR3 0x00020000
+/* Disable
+#define ICU0_IM4_IER_MPS_IR3_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM4_IER_MPS_IR3_EN 0x00020000
+/** MPS Status Interrupt #2 (VPE1 to VPE0)
+    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IER_MPS_IR2 0x00010000
+/* Disable
+#define ICU0_IM4_IER_MPS_IR2_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM4_IER_MPS_IR2_EN 0x00010000
+/** MPS Status Interrupt #1 (VPE1 to VPE0)
+    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IER_MPS_IR1 0x00008000
+/* Disable
+#define ICU0_IM4_IER_MPS_IR1_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM4_IER_MPS_IR1_EN 0x00008000
+/** MPS Status Interrupt #0 (VPE1 to VPE0)
+    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IER_MPS_IR0 0x00004000
+/* Disable
+#define ICU0_IM4_IER_MPS_IR0_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM4_IER_MPS_IR0_EN 0x00004000
+/** TMU Error
+    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IER_TMU_ERR 0x00001000
+/* Disable
+#define ICU0_IM4_IER_TMU_ERR_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM4_IER_TMU_ERR_EN 0x00001000
+/** FSQM Error
+    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IER_FSQM_ERR 0x00000800
+/* Disable
+#define ICU0_IM4_IER_FSQM_ERR_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM4_IER_FSQM_ERR_EN 0x00000800
+/** IQM Error
+    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IER_IQM_ERR 0x00000400
+/* Disable
+#define ICU0_IM4_IER_IQM_ERR_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM4_IER_IQM_ERR_EN 0x00000400
+/** OCTRLG Error
+    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IER_OCTRLG_ERR 0x00000200
+/* Disable
+#define ICU0_IM4_IER_OCTRLG_ERR_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM4_IER_OCTRLG_ERR_EN 0x00000200
+/** ICTRLG Error
+    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IER_ICTRLG_ERR 0x00000100
+/* Disable
+#define ICU0_IM4_IER_ICTRLG_ERR_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM4_IER_ICTRLG_ERR_EN 0x00000100
+/** OCTRLL 3 Error
+    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IER_OCTRLL3_ERR 0x00000080
+/* Disable
+#define ICU0_IM4_IER_OCTRLL3_ERR_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM4_IER_OCTRLL3_ERR_EN 0x00000080
+/** OCTRLL 2 Error
+    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IER_OCTRLL2_ERR 0x00000040
+/* Disable
+#define ICU0_IM4_IER_OCTRLL2_ERR_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM4_IER_OCTRLL2_ERR_EN 0x00000040
+/** OCTRLL 1 Error
+    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IER_OCTRLL1_ERR 0x00000020
+/* Disable
+#define ICU0_IM4_IER_OCTRLL1_ERR_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM4_IER_OCTRLL1_ERR_EN 0x00000020
+/** OCTRLL 0 Error
+    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IER_OCTRLL0_ERR 0x00000010
+/* Disable
+#define ICU0_IM4_IER_OCTRLL0_ERR_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM4_IER_OCTRLL0_ERR_EN 0x00000010
+/** ICTRLL 3 Error
+    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IER_ICTRLL3_ERR 0x00000008
+/* Disable
+#define ICU0_IM4_IER_ICTRLL3_ERR_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM4_IER_ICTRLL3_ERR_EN 0x00000008
+/** ICTRLL 2 Error
+    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IER_ICTRLL2_ERR 0x00000004
+/* Disable
+#define ICU0_IM4_IER_ICTRLL2_ERR_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM4_IER_ICTRLL2_ERR_EN 0x00000004
+/** ICTRLL 1 Error
+    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IER_ICTRLL1_ERR 0x00000002
+/* Disable
+#define ICU0_IM4_IER_ICTRLL1_ERR_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM4_IER_ICTRLL1_ERR_EN 0x00000002
+/** ICTRLL 0 Error
+    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IER_ICTRLL0_ERR 0x00000001
+/* Disable
+#define ICU0_IM4_IER_ICTRLL0_ERR_DIS 0x00000000 */
+/** Enable */
+#define ICU0_IM4_IER_ICTRLL0_ERR_EN 0x00000001
+
+/* Fields of "IM4 Interrupt Output Status Register" */
+/** VPE0 Performance Monitoring Counter Interrupt
+    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IOSR_VPE0_PMCIR 0x80000000
+/* Nothing
+#define ICU0_IM4_IOSR_VPE0_PMCIR_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_IOSR_VPE0_PMCIR_INTOCC 0x80000000
+/** VPE0 Error Level Flag Interrupt
+    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IOSR_VPE0_ERL 0x40000000
+/* Nothing
+#define ICU0_IM4_IOSR_VPE0_ERL_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_IOSR_VPE0_ERL_INTOCC 0x40000000
+/** VPE0 Exception Level Flag Interrupt
+    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IOSR_VPE0_EXL 0x20000000
+/* Nothing
+#define ICU0_IM4_IOSR_VPE0_EXL_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_IOSR_VPE0_EXL_INTOCC 0x20000000
+/** MPS Bin. Sem Interrupt to VPE0
+    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IOSR_MPS_IR8 0x00400000
+/* Nothing
+#define ICU0_IM4_IOSR_MPS_IR8_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_IOSR_MPS_IR8_INTOCC 0x00400000
+/** MPS Global Interrupt to VPE0
+    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IOSR_MPS_IR7 0x00200000
+/* Nothing
+#define ICU0_IM4_IOSR_MPS_IR7_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_IOSR_MPS_IR7_INTOCC 0x00200000
+/** MPS Status Interrupt #6 (VPE1 to VPE0)
+    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IOSR_MPS_IR6 0x00100000
+/* Nothing
+#define ICU0_IM4_IOSR_MPS_IR6_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_IOSR_MPS_IR6_INTOCC 0x00100000
+/** MPS Status Interrupt #5 (VPE1 to VPE0)
+    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IOSR_MPS_IR5 0x00080000
+/* Nothing
+#define ICU0_IM4_IOSR_MPS_IR5_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_IOSR_MPS_IR5_INTOCC 0x00080000
+/** MPS Status Interrupt #4 (VPE1 to VPE0)
+    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IOSR_MPS_IR4 0x00040000
+/* Nothing
+#define ICU0_IM4_IOSR_MPS_IR4_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_IOSR_MPS_IR4_INTOCC 0x00040000
+/** MPS Status Interrupt #3 (VPE1 to VPE0)
+    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IOSR_MPS_IR3 0x00020000
+/* Nothing
+#define ICU0_IM4_IOSR_MPS_IR3_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_IOSR_MPS_IR3_INTOCC 0x00020000
+/** MPS Status Interrupt #2 (VPE1 to VPE0)
+    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IOSR_MPS_IR2 0x00010000
+/* Nothing
+#define ICU0_IM4_IOSR_MPS_IR2_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_IOSR_MPS_IR2_INTOCC 0x00010000
+/** MPS Status Interrupt #1 (VPE1 to VPE0)
+    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IOSR_MPS_IR1 0x00008000
+/* Nothing
+#define ICU0_IM4_IOSR_MPS_IR1_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_IOSR_MPS_IR1_INTOCC 0x00008000
+/** MPS Status Interrupt #0 (VPE1 to VPE0)
+    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IOSR_MPS_IR0 0x00004000
+/* Nothing
+#define ICU0_IM4_IOSR_MPS_IR0_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_IOSR_MPS_IR0_INTOCC 0x00004000
+/** TMU Error
+    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IOSR_TMU_ERR 0x00001000
+/* Nothing
+#define ICU0_IM4_IOSR_TMU_ERR_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_IOSR_TMU_ERR_INTOCC 0x00001000
+/** FSQM Error
+    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IOSR_FSQM_ERR 0x00000800
+/* Nothing
+#define ICU0_IM4_IOSR_FSQM_ERR_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_IOSR_FSQM_ERR_INTOCC 0x00000800
+/** IQM Error
+    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IOSR_IQM_ERR 0x00000400
+/* Nothing
+#define ICU0_IM4_IOSR_IQM_ERR_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_IOSR_IQM_ERR_INTOCC 0x00000400
+/** OCTRLG Error
+    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IOSR_OCTRLG_ERR 0x00000200
+/* Nothing
+#define ICU0_IM4_IOSR_OCTRLG_ERR_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_IOSR_OCTRLG_ERR_INTOCC 0x00000200
+/** ICTRLG Error
+    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IOSR_ICTRLG_ERR 0x00000100
+/* Nothing
+#define ICU0_IM4_IOSR_ICTRLG_ERR_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_IOSR_ICTRLG_ERR_INTOCC 0x00000100
+/** OCTRLL 3 Error
+    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IOSR_OCTRLL3_ERR 0x00000080
+/* Nothing
+#define ICU0_IM4_IOSR_OCTRLL3_ERR_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_IOSR_OCTRLL3_ERR_INTOCC 0x00000080
+/** OCTRLL 2 Error
+    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IOSR_OCTRLL2_ERR 0x00000040
+/* Nothing
+#define ICU0_IM4_IOSR_OCTRLL2_ERR_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_IOSR_OCTRLL2_ERR_INTOCC 0x00000040
+/** OCTRLL 1 Error
+    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IOSR_OCTRLL1_ERR 0x00000020
+/* Nothing
+#define ICU0_IM4_IOSR_OCTRLL1_ERR_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_IOSR_OCTRLL1_ERR_INTOCC 0x00000020
+/** OCTRLL 0 Error
+    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IOSR_OCTRLL0_ERR 0x00000010
+/* Nothing
+#define ICU0_IM4_IOSR_OCTRLL0_ERR_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_IOSR_OCTRLL0_ERR_INTOCC 0x00000010
+/** ICTRLL 3 Error
+    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IOSR_ICTRLL3_ERR 0x00000008
+/* Nothing
+#define ICU0_IM4_IOSR_ICTRLL3_ERR_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_IOSR_ICTRLL3_ERR_INTOCC 0x00000008
+/** ICTRLL 2 Error
+    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IOSR_ICTRLL2_ERR 0x00000004
+/* Nothing
+#define ICU0_IM4_IOSR_ICTRLL2_ERR_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_IOSR_ICTRLL2_ERR_INTOCC 0x00000004
+/** ICTRLL 1 Error
+    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IOSR_ICTRLL1_ERR 0x00000002
+/* Nothing
+#define ICU0_IM4_IOSR_ICTRLL1_ERR_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_IOSR_ICTRLL1_ERR_INTOCC 0x00000002
+/** ICTRLL 0 Error
+    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IOSR_ICTRLL0_ERR 0x00000001
+/* Nothing
+#define ICU0_IM4_IOSR_ICTRLL0_ERR_NULL 0x00000000 */
+/** Read: Interrupt occurred. */
+#define ICU0_IM4_IOSR_ICTRLL0_ERR_INTOCC 0x00000001
+
+/* Fields of "IM4 Interrupt Request Set Register" */
+/** VPE0 Performance Monitoring Counter Interrupt
+    Software control for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IRSR_VPE0_PMCIR 0x80000000
+/** VPE0 Error Level Flag Interrupt
+    Software control for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IRSR_VPE0_ERL 0x40000000
+/** VPE0 Exception Level Flag Interrupt
+    Software control for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IRSR_VPE0_EXL 0x20000000
+/** MPS Bin. Sem Interrupt to VPE0
+    Software control for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IRSR_MPS_IR8 0x00400000
+/** MPS Global Interrupt to VPE0
+    Software control for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IRSR_MPS_IR7 0x00200000
+/** MPS Status Interrupt #6 (VPE1 to VPE0)
+    Software control for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IRSR_MPS_IR6 0x00100000
+/** MPS Status Interrupt #5 (VPE1 to VPE0)
+    Software control for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IRSR_MPS_IR5 0x00080000
+/** MPS Status Interrupt #4 (VPE1 to VPE0)
+    Software control for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IRSR_MPS_IR4 0x00040000
+/** MPS Status Interrupt #3 (VPE1 to VPE0)
+    Software control for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IRSR_MPS_IR3 0x00020000
+/** MPS Status Interrupt #2 (VPE1 to VPE0)
+    Software control for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IRSR_MPS_IR2 0x00010000
+/** MPS Status Interrupt #1 (VPE1 to VPE0)
+    Software control for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IRSR_MPS_IR1 0x00008000
+/** MPS Status Interrupt #0 (VPE1 to VPE0)
+    Software control for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IRSR_MPS_IR0 0x00004000
+/** TMU Error
+    Software control for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IRSR_TMU_ERR 0x00001000
+/** FSQM Error
+    Software control for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IRSR_FSQM_ERR 0x00000800
+/** IQM Error
+    Software control for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IRSR_IQM_ERR 0x00000400
+/** OCTRLG Error
+    Software control for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IRSR_OCTRLG_ERR 0x00000200
+/** ICTRLG Error
+    Software control for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IRSR_ICTRLG_ERR 0x00000100
+/** OCTRLL 3 Error
+    Software control for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IRSR_OCTRLL3_ERR 0x00000080
+/** OCTRLL 2 Error
+    Software control for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IRSR_OCTRLL2_ERR 0x00000040
+/** OCTRLL 1 Error
+    Software control for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IRSR_OCTRLL1_ERR 0x00000020
+/** OCTRLL 0 Error
+    Software control for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IRSR_OCTRLL0_ERR 0x00000010
+/** ICTRLL 3 Error
+    Software control for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IRSR_ICTRLL3_ERR 0x00000008
+/** ICTRLL 2 Error
+    Software control for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IRSR_ICTRLL2_ERR 0x00000004
+/** ICTRLL 1 Error
+    Software control for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IRSR_ICTRLL1_ERR 0x00000002
+/** ICTRLL 0 Error
+    Software control for the corresponding bit in the IM4_ISR register. */
+#define ICU0_IM4_IRSR_ICTRLL0_ERR 0x00000001
+
+/* Fields of "IM4 Interrupt Mode Register" */
+/** VPE0 Performance Monitoring Counter Interrupt
+    Type of interrupt. */
+#define ICU0_IM4_IMR_VPE0_PMCIR 0x80000000
+/* Indirect Interrupt.
+#define ICU0_IM4_IMR_VPE0_PMCIR_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM4_IMR_VPE0_PMCIR_DIR 0x80000000
+/** VPE0 Error Level Flag Interrupt
+    Type of interrupt. */
+#define ICU0_IM4_IMR_VPE0_ERL 0x40000000
+/* Indirect Interrupt.
+#define ICU0_IM4_IMR_VPE0_ERL_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM4_IMR_VPE0_ERL_DIR 0x40000000
+/** VPE0 Exception Level Flag Interrupt
+    Type of interrupt. */
+#define ICU0_IM4_IMR_VPE0_EXL 0x20000000
+/* Indirect Interrupt.
+#define ICU0_IM4_IMR_VPE0_EXL_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM4_IMR_VPE0_EXL_DIR 0x20000000
+/** MPS Bin. Sem Interrupt to VPE0
+    Type of interrupt. */
+#define ICU0_IM4_IMR_MPS_IR8 0x00400000
+/* Indirect Interrupt.
+#define ICU0_IM4_IMR_MPS_IR8_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM4_IMR_MPS_IR8_DIR 0x00400000
+/** MPS Global Interrupt to VPE0
+    Type of interrupt. */
+#define ICU0_IM4_IMR_MPS_IR7 0x00200000
+/* Indirect Interrupt.
+#define ICU0_IM4_IMR_MPS_IR7_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM4_IMR_MPS_IR7_DIR 0x00200000
+/** MPS Status Interrupt #6 (VPE1 to VPE0)
+    Type of interrupt. */
+#define ICU0_IM4_IMR_MPS_IR6 0x00100000
+/* Indirect Interrupt.
+#define ICU0_IM4_IMR_MPS_IR6_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM4_IMR_MPS_IR6_DIR 0x00100000
+/** MPS Status Interrupt #5 (VPE1 to VPE0)
+    Type of interrupt. */
+#define ICU0_IM4_IMR_MPS_IR5 0x00080000
+/* Indirect Interrupt.
+#define ICU0_IM4_IMR_MPS_IR5_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM4_IMR_MPS_IR5_DIR 0x00080000
+/** MPS Status Interrupt #4 (VPE1 to VPE0)
+    Type of interrupt. */
+#define ICU0_IM4_IMR_MPS_IR4 0x00040000
+/* Indirect Interrupt.
+#define ICU0_IM4_IMR_MPS_IR4_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM4_IMR_MPS_IR4_DIR 0x00040000
+/** MPS Status Interrupt #3 (VPE1 to VPE0)
+    Type of interrupt. */
+#define ICU0_IM4_IMR_MPS_IR3 0x00020000
+/* Indirect Interrupt.
+#define ICU0_IM4_IMR_MPS_IR3_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM4_IMR_MPS_IR3_DIR 0x00020000
+/** MPS Status Interrupt #2 (VPE1 to VPE0)
+    Type of interrupt. */
+#define ICU0_IM4_IMR_MPS_IR2 0x00010000
+/* Indirect Interrupt.
+#define ICU0_IM4_IMR_MPS_IR2_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM4_IMR_MPS_IR2_DIR 0x00010000
+/** MPS Status Interrupt #1 (VPE1 to VPE0)
+    Type of interrupt. */
+#define ICU0_IM4_IMR_MPS_IR1 0x00008000
+/* Indirect Interrupt.
+#define ICU0_IM4_IMR_MPS_IR1_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM4_IMR_MPS_IR1_DIR 0x00008000
+/** MPS Status Interrupt #0 (VPE1 to VPE0)
+    Type of interrupt. */
+#define ICU0_IM4_IMR_MPS_IR0 0x00004000
+/* Indirect Interrupt.
+#define ICU0_IM4_IMR_MPS_IR0_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM4_IMR_MPS_IR0_DIR 0x00004000
+/** TMU Error
+    Type of interrupt. */
+#define ICU0_IM4_IMR_TMU_ERR 0x00001000
+/* Indirect Interrupt.
+#define ICU0_IM4_IMR_TMU_ERR_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM4_IMR_TMU_ERR_DIR 0x00001000
+/** FSQM Error
+    Type of interrupt. */
+#define ICU0_IM4_IMR_FSQM_ERR 0x00000800
+/* Indirect Interrupt.
+#define ICU0_IM4_IMR_FSQM_ERR_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM4_IMR_FSQM_ERR_DIR 0x00000800
+/** IQM Error
+    Type of interrupt. */
+#define ICU0_IM4_IMR_IQM_ERR 0x00000400
+/* Indirect Interrupt.
+#define ICU0_IM4_IMR_IQM_ERR_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM4_IMR_IQM_ERR_DIR 0x00000400
+/** OCTRLG Error
+    Type of interrupt. */
+#define ICU0_IM4_IMR_OCTRLG_ERR 0x00000200
+/* Indirect Interrupt.
+#define ICU0_IM4_IMR_OCTRLG_ERR_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM4_IMR_OCTRLG_ERR_DIR 0x00000200
+/** ICTRLG Error
+    Type of interrupt. */
+#define ICU0_IM4_IMR_ICTRLG_ERR 0x00000100
+/* Indirect Interrupt.
+#define ICU0_IM4_IMR_ICTRLG_ERR_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM4_IMR_ICTRLG_ERR_DIR 0x00000100
+/** OCTRLL 3 Error
+    Type of interrupt. */
+#define ICU0_IM4_IMR_OCTRLL3_ERR 0x00000080
+/* Indirect Interrupt.
+#define ICU0_IM4_IMR_OCTRLL3_ERR_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM4_IMR_OCTRLL3_ERR_DIR 0x00000080
+/** OCTRLL 2 Error
+    Type of interrupt. */
+#define ICU0_IM4_IMR_OCTRLL2_ERR 0x00000040
+/* Indirect Interrupt.
+#define ICU0_IM4_IMR_OCTRLL2_ERR_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM4_IMR_OCTRLL2_ERR_DIR 0x00000040
+/** OCTRLL 1 Error
+    Type of interrupt. */
+#define ICU0_IM4_IMR_OCTRLL1_ERR 0x00000020
+/* Indirect Interrupt.
+#define ICU0_IM4_IMR_OCTRLL1_ERR_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM4_IMR_OCTRLL1_ERR_DIR 0x00000020
+/** OCTRLL 0 Error
+    Type of interrupt. */
+#define ICU0_IM4_IMR_OCTRLL0_ERR 0x00000010
+/* Indirect Interrupt.
+#define ICU0_IM4_IMR_OCTRLL0_ERR_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM4_IMR_OCTRLL0_ERR_DIR 0x00000010
+/** ICTRLL 3 Error
+    Type of interrupt. */
+#define ICU0_IM4_IMR_ICTRLL3_ERR 0x00000008
+/* Indirect Interrupt.
+#define ICU0_IM4_IMR_ICTRLL3_ERR_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM4_IMR_ICTRLL3_ERR_DIR 0x00000008
+/** ICTRLL 2 Error
+    Type of interrupt. */
+#define ICU0_IM4_IMR_ICTRLL2_ERR 0x00000004
+/* Indirect Interrupt.
+#define ICU0_IM4_IMR_ICTRLL2_ERR_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM4_IMR_ICTRLL2_ERR_DIR 0x00000004
+/** ICTRLL 1 Error
+    Type of interrupt. */
+#define ICU0_IM4_IMR_ICTRLL1_ERR 0x00000002
+/* Indirect Interrupt.
+#define ICU0_IM4_IMR_ICTRLL1_ERR_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM4_IMR_ICTRLL1_ERR_DIR 0x00000002
+/** ICTRLL 0 Error
+    Type of interrupt. */
+#define ICU0_IM4_IMR_ICTRLL0_ERR 0x00000001
+/* Indirect Interrupt.
+#define ICU0_IM4_IMR_ICTRLL0_ERR_IND 0x00000000 */
+/** Direct Interrupt. */
+#define ICU0_IM4_IMR_ICTRLL0_ERR_DIR 0x00000001
+
+/* Fields of "ICU Interrupt Vector Register (5 bit variant)" */
+/** IM4 Interrupt Vector Value
+    Returns the highest priority pending interrupt vector. */
+#define ICU0_ICU_IVEC_IM4_vec_MASK 0x01F00000
+/** field offset */
+#define ICU0_ICU_IVEC_IM4_vec_OFFSET 20
+/** Interrupt pending at bit 31 or no pending interrupt */
+#define ICU0_ICU_IVEC_IM4_vec_NOINTorBit31 0x00000000
+/** Interrupt pending at bit 0. */
+#define ICU0_ICU_IVEC_IM4_vec_BIT0 0x00100000
+/** Interrupt pending at bit 1. */
+#define ICU0_ICU_IVEC_IM4_vec_BIT1 0x00200000
+/** Interrupt pending at bit 30. */
+#define ICU0_ICU_IVEC_IM4_vec_BIT30 0x01F00000
+/** IM3 Interrupt Vector Value
+    Returns the highest priority pending interrupt vector. */
+#define ICU0_ICU_IVEC_IM3_vec_MASK 0x000F8000
+/** field offset */
+#define ICU0_ICU_IVEC_IM3_vec_OFFSET 15
+/** Interrupt pending at bit 31 or no pending interrupt */
+#define ICU0_ICU_IVEC_IM3_vec_NOINTorBit31 0x00000000
+/** Interrupt pending at bit 0. */
+#define ICU0_ICU_IVEC_IM3_vec_BIT0 0x00008000
+/** Interrupt pending at bit 1. */
+#define ICU0_ICU_IVEC_IM3_vec_BIT1 0x00010000
+/** Interrupt pending at bit 30. */
+#define ICU0_ICU_IVEC_IM3_vec_BIT30 0x000F8000
+/** IM2 Interrupt Vector Value
+    Returns the highest priority pending interrupt vector. */
+#define ICU0_ICU_IVEC_IM2_vec_MASK 0x00007C00
+/** field offset */
+#define ICU0_ICU_IVEC_IM2_vec_OFFSET 10
+/** Interrupt pending at bit 31 or no pending interrupt */
+#define ICU0_ICU_IVEC_IM2_vec_NOINTorBit31 0x00000000
+/** Interrupt pending at bit 0. */
+#define ICU0_ICU_IVEC_IM2_vec_BIT0 0x00000400
+/** Interrupt pending at bit 1. */
+#define ICU0_ICU_IVEC_IM2_vec_BIT1 0x00000800
+/** Interrupt pending at bit 30. */
+#define ICU0_ICU_IVEC_IM2_vec_BIT30 0x00007C00
+/** IM1 Interrupt Vector Value
+    Returns the highest priority pending interrupt vector. */
+#define ICU0_ICU_IVEC_IM1_vec_MASK 0x000003E0
+/** field offset */
+#define ICU0_ICU_IVEC_IM1_vec_OFFSET 5
+/** Interrupt pending at bit 31 or no pending interrupt */
+#define ICU0_ICU_IVEC_IM1_vec_NOINTorBit31 0x00000000
+/** Interrupt pending at bit 0. */
+#define ICU0_ICU_IVEC_IM1_vec_BIT0 0x00000020
+/** Interrupt pending at bit 1. */
+#define ICU0_ICU_IVEC_IM1_vec_BIT1 0x00000040
+/** Interrupt pending at bit 30. */
+#define ICU0_ICU_IVEC_IM1_vec_BIT30 0x000003E0
+/** IM0 Interrupt Vector Value
+    Returns the highest priority pending interrupt vector. */
+#define ICU0_ICU_IVEC_IM0_vec_MASK 0x0000001F
+/** field offset */
+#define ICU0_ICU_IVEC_IM0_vec_OFFSET 0
+/** Interrupt pending at bit 31 or no pending interrupt */
+#define ICU0_ICU_IVEC_IM0_vec_NOINTorBit31 0x00000000
+/** Interrupt pending at bit 0. */
+#define ICU0_ICU_IVEC_IM0_vec_BIT0 0x00000001
+/** Interrupt pending at bit 1. */
+#define ICU0_ICU_IVEC_IM0_vec_BIT1 0x00000002
+/** Interrupt pending at bit 30. */
+#define ICU0_ICU_IVEC_IM0_vec_BIT30 0x0000001F
+
+/* Fields of "ICU Interrupt Vector Register (6 bit variant)" */
+/** IM4 Interrupt Vector Value
+    Returns the highest priority pending interrupt vector. */
+#define ICU0_ICU_IVEC_6_IM4_vec_MASK 0x3F000000
+/** field offset */
+#define ICU0_ICU_IVEC_6_IM4_vec_OFFSET 24
+/** No pending interrupt */
+#define ICU0_ICU_IVEC_6_IM4_vec_NOINT 0x00000000
+/** Interrupt pending at bit 0. */
+#define ICU0_ICU_IVEC_6_IM4_vec_BIT0 0x01000000
+/** Interrupt pending at bit 1. */
+#define ICU0_ICU_IVEC_6_IM4_vec_BIT1 0x02000000
+/** Interrupt pending at bit 30. */
+#define ICU0_ICU_IVEC_6_IM4_vec_BIT30 0x1F000000
+/** Interrupt pending at bit 31. */
+#define ICU0_ICU_IVEC_6_IM4_vec_BIT31 0x20000000
+/** IM3 Interrupt Vector Value
+    Returns the highest priority pending interrupt vector. */
+#define ICU0_ICU_IVEC_6_IM3_vec_MASK 0x00FC0000
+/** field offset */
+#define ICU0_ICU_IVEC_6_IM3_vec_OFFSET 18
+/** No pending interrupt */
+#define ICU0_ICU_IVEC_6_IM3_vec_NOINT 0x00000000
+/** Interrupt pending at bit 0. */
+#define ICU0_ICU_IVEC_6_IM3_vec_BIT0 0x00040000
+/** Interrupt pending at bit 1. */
+#define ICU0_ICU_IVEC_6_IM3_vec_BIT1 0x00080000
+/** Interrupt pending at bit 30. */
+#define ICU0_ICU_IVEC_6_IM3_vec_BIT30 0x007C0000
+/** Interrupt pending at bit 31. */
+#define ICU0_ICU_IVEC_6_IM3_vec_BIT31 0x00800000
+/** IM2 Interrupt Vector Value
+    Returns the highest priority pending interrupt vector. */
+#define ICU0_ICU_IVEC_6_IM2_vec_MASK 0x0003F000
+/** field offset */
+#define ICU0_ICU_IVEC_6_IM2_vec_OFFSET 12
+/** No pending interrupt */
+#define ICU0_ICU_IVEC_6_IM2_vec_NOINT 0x00000000
+/** Interrupt pending at bit 0. */
+#define ICU0_ICU_IVEC_6_IM2_vec_BIT0 0x00001000
+/** Interrupt pending at bit 1. */
+#define ICU0_ICU_IVEC_6_IM2_vec_BIT1 0x00002000
+/** Interrupt pending at bit 30. */
+#define ICU0_ICU_IVEC_6_IM2_vec_BIT30 0x0001F000
+/** Interrupt pending at bit 31. */
+#define ICU0_ICU_IVEC_6_IM2_vec_BIT31 0x00020000
+/** IM1 Interrupt Vector Value
+    Returns the highest priority pending interrupt vector. */
+#define ICU0_ICU_IVEC_6_IM1_vec_MASK 0x00000FC0
+/** field offset */
+#define ICU0_ICU_IVEC_6_IM1_vec_OFFSET 6
+/** No pending interrupt */
+#define ICU0_ICU_IVEC_6_IM1_vec_NOINT 0x00000000
+/** Interrupt pending at bit 0. */
+#define ICU0_ICU_IVEC_6_IM1_vec_BIT0 0x00000040
+/** Interrupt pending at bit 1. */
+#define ICU0_ICU_IVEC_6_IM1_vec_BIT1 0x00000080
+/** Interrupt pending at bit 30. */
+#define ICU0_ICU_IVEC_6_IM1_vec_BIT30 0x000007C0
+/** Interrupt pending at bit 31. */
+#define ICU0_ICU_IVEC_6_IM1_vec_BIT31 0x00000800
+/** IM0 Interrupt Vector Value
+    Returns the highest priority pending interrupt vector. */
+#define ICU0_ICU_IVEC_6_IM0_vec_MASK 0x0000003F
+/** field offset */
+#define ICU0_ICU_IVEC_6_IM0_vec_OFFSET 0
+/** No pending interrupt */
+#define ICU0_ICU_IVEC_6_IM0_vec_NOINT 0x00000000
+/** Interrupt pending at bit 0. */
+#define ICU0_ICU_IVEC_6_IM0_vec_BIT0 0x00000001
+/** Interrupt pending at bit 1. */
+#define ICU0_ICU_IVEC_6_IM0_vec_BIT1 0x00000002
+/** Interrupt pending at bit 30. */
+#define ICU0_ICU_IVEC_6_IM0_vec_BIT30 0x0000001F
+/** Interrupt pending at bit 31. */
+#define ICU0_ICU_IVEC_6_IM0_vec_BIT31 0x00000020
+
+/*! @} */ /* ICU0_REGISTER */
+
+#endif /* _icu0_reg_h */
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/falcon/status_reg.h
@@ -0,0 +1,529 @@
+/******************************************************************************
+
+                               Copyright (c) 2010
+                            Lantiq Deutschland GmbH
+
+  For licensing information, see the file 'LICENSE' in the root folder of
+  this software module.
+
+******************************************************************************/
+
+#ifndef _status_reg_h
+#define _status_reg_h
+
+/** \addtogroup STATUS_REGISTER
+   @{
+*/
+/* access macros */
+#define status_r32(reg) reg_r32(&status->reg)
+#define status_w32(val, reg) reg_w32(val, &status->reg)
+#define status_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &status->reg)
+#define status_r32_table(reg, idx) reg_r32_table(status->reg, idx)
+#define status_w32_table(val, reg, idx) reg_w32_table(val, status->reg, idx)
+#define status_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, status->reg, idx)
+#define status_adr_table(reg, idx) adr_table(status->reg, idx)
+
+
+/** STATUS register structure */
+struct gpon_reg_status
+{
+   /** Reserved */
+   unsigned int res_0[3]; /* 0x00000000 */
+   /** Chip Identification Register */
+   unsigned int chipid; /* 0x0000000C */
+   /** Chip Location Register
+       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
+   unsigned int chiploc; /* 0x00000010 */
+   /** Redundancy register
+       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
+   unsigned int red0; /* 0x00000014 */
+   /** Redundancy register
+       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
+   unsigned int red1; /* 0x00000018 */
+   /** Redundancy register
+       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
+   unsigned int red2; /* 0x0000001C */
+   /** Redundancy register
+       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
+   unsigned int red3; /* 0x00000020 */
+   /** Redundancy register
+       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
+   unsigned int red4; /* 0x00000024 */
+   /** Redundancy register
+       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
+   unsigned int red5; /* 0x00000028 */
+   /** Redundancy register
+       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
+   unsigned int red6; /* 0x0000002C */
+   /** Redundancy register
+       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
+   unsigned int red7; /* 0x00000030 */
+   /** Redundancy register
+       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
+   unsigned int red8; /* 0x00000034 */
+   /** SPARE fuse register 0
+       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
+   unsigned int fuse0; /* 0x00000038 */
+   /** Fuses for Analog modules
+       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
+   unsigned int analog; /* 0x0000003C */
+   /** Configuration fuses for drivers and pll
+       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
+   unsigned int config; /* 0x00000040 */
+   /** SPARE fuse register 1
+       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
+   unsigned int fuse1; /* 0x00000044 */
+   /** Configuration for sbs0 rambist */
+   unsigned int mbcfg; /* 0x00000048 */
+   /** sbs0 bist result and debug data */
+   unsigned int mbdata; /* 0x0000004C */
+   /** Reserved */
+   unsigned int res_1[12]; /* 0x00000050 */
+};
+
+
+/* Fields of "Chip Identification Register" */
+/** Chip Version Number
+    Version number */
+#define STATUS_CHIPID_VERSION_MASK 0xF0000000
+/** field offset */
+#define STATUS_CHIPID_VERSION_OFFSET 28
+/** Part Number, Constant Part
+    The Part Number is fixed to 016Bhex. */
+#define STATUS_CHIPID_PARTNR_MASK 0x0FFFF000
+/** field offset */
+#define STATUS_CHIPID_PARTNR_OFFSET 12
+/** Manufacturer ID
+    The value of bit field MANID is fixed to 41hex as configured in the JTAG ID register. The JEDEC normalized manufacturer code for Infineon Technologies is C1hex */
+#define STATUS_CHIPID_MANID_MASK 0x00000FFE
+/** field offset */
+#define STATUS_CHIPID_MANID_OFFSET 1
+/** Constant bit
+    The value of bit field CONST1 is fixed to 1hex */
+#define STATUS_CHIPID_CONST1 0x00000001
+
+/* Fields of "Chip Location Register" */
+/** Chip Lot ID */
+#define STATUS_CHIPLOC_CHIPLOT_MASK 0xFFFF0000
+/** field offset */
+#define STATUS_CHIPLOC_CHIPLOT_OFFSET 16
+/** Chip X Coordinate */
+#define STATUS_CHIPLOC_CHIPX_MASK 0x0000FF00
+/** field offset */
+#define STATUS_CHIPLOC_CHIPX_OFFSET 8
+/** Chip Y Coordinate */
+#define STATUS_CHIPLOC_CHIPY_MASK 0x000000FF
+/** field offset */
+#define STATUS_CHIPLOC_CHIPY_OFFSET 0
+
+/* Fields of "Redundancy register" */
+/** Redundancy
+    redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
+#define STATUS_RED0_REDUNDANCY_MASK 0x0003FFFF
+/** field offset */
+#define STATUS_RED0_REDUNDANCY_OFFSET 0
+
+/* Fields of "Redundancy register" */
+/** Redundancy
+    redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
+#define STATUS_RED1_REDUNDANCY_MASK 0x0003FFFF
+/** field offset */
+#define STATUS_RED1_REDUNDANCY_OFFSET 0
+
+/* Fields of "Redundancy register" */
+/** Redundancy
+    redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
+#define STATUS_RED2_REDUNDANCY_MASK 0x0003FFFF
+/** field offset */
+#define STATUS_RED2_REDUNDANCY_OFFSET 0
+
+/* Fields of "Redundancy register" */
+/** Redundancy
+    redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
+#define STATUS_RED3_REDUNDANCY_MASK 0x0003FFFF
+/** field offset */
+#define STATUS_RED3_REDUNDANCY_OFFSET 0
+
+/* Fields of "Redundancy register" */
+/** Redundancy
+    redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
+#define STATUS_RED4_REDUNDANCY_MASK 0x0003FFFF
+/** field offset */
+#define STATUS_RED4_REDUNDANCY_OFFSET 0
+
+/* Fields of "Redundancy register" */
+/** Redundancy
+    redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
+#define STATUS_RED5_REDUNDANCY_MASK 0x0003FFFF
+/** field offset */
+#define STATUS_RED5_REDUNDANCY_OFFSET 0
+
+/* Fields of "Redundancy register" */
+/** Redundancy
+    redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
+#define STATUS_RED6_REDUNDANCY_MASK 0x0003FFFF
+/** field offset */
+#define STATUS_RED6_REDUNDANCY_OFFSET 0
+
+/* Fields of "Redundancy register" */
+/** Redundancy
+    redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
+#define STATUS_RED7_REDUNDANCY_MASK 0x0003FFFF
+/** field offset */
+#define STATUS_RED7_REDUNDANCY_OFFSET 0
+
+/* Fields of "Redundancy register" */
+/** Redundancy
+    redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
+#define STATUS_RED8_REDUNDANCY_MASK 0x0003FFFF
+/** field offset */
+#define STATUS_RED8_REDUNDANCY_OFFSET 0
+
+/* Fields of "SPARE fuse register 0" */
+/** Soft fuse control
+    Controls whether the status block is in its softfused state or not. In the softfused state the values written via software are active effective. */
+#define STATUS_FUSE0_SFC 0x80000000
+/* Not selected
+#define STATUS_FUSE0_SFC_NSEL 0x00000000 */
+/** Selected */
+#define STATUS_FUSE0_SFC_SEL 0x80000000
+/** Soft control MBCFG
+    Controls whether mbist configuration can be overwritten or not from subsystem. If not selected jtag mbcfg register is source for software mbist configuration */
+#define STATUS_FUSE0_SC_MBCFG 0x40000000
+/* Not selected
+#define STATUS_FUSE0_SC_MBCFG_NSEL 0x00000000 */
+/** Selected */
+#define STATUS_FUSE0_SC_MBCFG_SEL 0x40000000
+/** spare fuse0
+    eFuses not assigned to hw/sw, can be used for future applications */
+#define STATUS_FUSE0_F0_MASK 0x3C000000
+/** field offset */
+#define STATUS_FUSE0_F0_OFFSET 26
+/** VCALMM20 Voltage Reference
+    Voltage Reference for calibration via R and constant current (20 uA) */
+#define STATUS_FUSE0_VCALMM20_MASK 0x03F00000
+/** field offset */
+#define STATUS_FUSE0_VCALMM20_OFFSET 20
+/** VCALMM100 Voltage Reference
+    Voltage Reference for calibration via R and constant current (100 uA) */
+#define STATUS_FUSE0_VCALMM100_MASK 0x000FC000
+/** field offset */
+#define STATUS_FUSE0_VCALMM100_OFFSET 14
+/** VCALMM400 Voltage Reference
+    Voltage Reference for calibration via R and constant current (400 uA) */
+#define STATUS_FUSE0_VCALMM400_MASK 0x00003F00
+/** field offset */
+#define STATUS_FUSE0_VCALMM400_OFFSET 8
+/** RCALMM R error correction
+    The resistance deviation from ideal R (1000 Ohm) */
+#define STATUS_FUSE0_RCALMM_MASK 0x000000FF
+/** field offset */
+#define STATUS_FUSE0_RCALMM_OFFSET 0
+
+/* Fields of "Fuses for Analog modules" */
+/** reserved Analog eFuses
+    Reserved Register contains information stored in eFuses needed for the analog modules */
+#define STATUS_ANALOG_A0_MASK 0xFF000000
+/** field offset */
+#define STATUS_ANALOG_A0_OFFSET 24
+/** Absolut Temperature
+    Temperature ERROR */
+#define STATUS_ANALOG_TEMPMM_MASK 0x00FC0000
+/** field offset */
+#define STATUS_ANALOG_TEMPMM_OFFSET 18
+/** Bias Voltage Generation
+    temperature dependency */
+#define STATUS_ANALOG_TBGP_MASK 0x00038000
+/** field offset */
+#define STATUS_ANALOG_TBGP_OFFSET 15
+/** Bias Voltage Generation
+    voltage dependency */
+#define STATUS_ANALOG_VBGP_MASK 0x00007000
+/** field offset */
+#define STATUS_ANALOG_VBGP_OFFSET 12
+/** Bias Current Generation */
+#define STATUS_ANALOG_IREFBGP_MASK 0x00000F00
+/** field offset */
+#define STATUS_ANALOG_IREFBGP_OFFSET 8
+/** Drive DAC Gain */
+#define STATUS_ANALOG_GAINDRIVEDAC_MASK 0x000000F0
+/** field offset */
+#define STATUS_ANALOG_GAINDRIVEDAC_OFFSET 4
+/** BIAS DAC Gain */
+#define STATUS_ANALOG_GAINBIASDAC_MASK 0x0000000F
+/** field offset */
+#define STATUS_ANALOG_GAINBIASDAC_OFFSET 0
+
+/* Fields of "Configuration fuses for drivers and pll" */
+/** ddr PU driver
+    ddr pullup driver strength adjustment */
+#define STATUS_CONFIG_DDRPU_MASK 0xC0000000
+/** field offset */
+#define STATUS_CONFIG_DDRPU_OFFSET 30
+/** ddr PD driver
+    ddr pulldown driver strength adjustment */
+#define STATUS_CONFIG_DDRPD_MASK 0x30000000
+/** field offset */
+#define STATUS_CONFIG_DDRPD_OFFSET 28
+/** Authentification Unit enable
+    This bit can only be set via eFuse and enables the authentification unit. */
+#define STATUS_CONFIG_SHA1EN 0x08000000
+/* Not selected
+#define STATUS_CONFIG_SHA1EN_NSEL 0x00000000 */
+/** Selected */
+#define STATUS_CONFIG_SHA1EN_SEL 0x08000000
+/** Encryption Unit enable
+    This bit can only be set via eFuse and enables the encryption unit. */
+#define STATUS_CONFIG_AESEN 0x04000000
+/* Not selected
+#define STATUS_CONFIG_AESEN_NSEL 0x00000000 */
+/** Selected */
+#define STATUS_CONFIG_AESEN_SEL 0x04000000
+/** Subversion Number
+    The subversion number has no direct effect on hardware functions. It is used to provide another chip version number that is fixed in hardware and can be read out by software. In this way different product packages consisting of GPON_MODEM and software can be defined for example */
+#define STATUS_CONFIG_SUBVERS_MASK 0x03C00000
+/** field offset */
+#define STATUS_CONFIG_SUBVERS_OFFSET 22
+/** PLL settings
+    PLL settings for infrastructure block */
+#define STATUS_CONFIG_PLLINFRA_MASK 0x003FF000
+/** field offset */
+#define STATUS_CONFIG_PLLINFRA_OFFSET 12
+/** GPE frequency selection
+    Scaling down the GPE frequency for debugging purpose */
+#define STATUS_CONFIG_GPEFREQ_MASK 0x00000C00
+/** field offset */
+#define STATUS_CONFIG_GPEFREQ_OFFSET 10
+/** RM enable
+    Activates the Read Margin Settings defined in the RM Field, for all VIRAGE Memories except GPE */
+#define STATUS_CONFIG_RME 0x00000200
+/* Not selected
+#define STATUS_CONFIG_RME_NSEL 0x00000000 */
+/** Selected */
+#define STATUS_CONFIG_RME_SEL 0x00000200
+/** RM settings
+    Read Marging Settings for all VIRAGE Memories except GPE */
+#define STATUS_CONFIG_RM_MASK 0x000001E0
+/** field offset */
+#define STATUS_CONFIG_RM_OFFSET 5
+/** RM enable for GPE Memories
+    Activates the Read Margin Settings defined in the RM Field */
+#define STATUS_CONFIG_RMEGPE 0x00000010
+/* Not selected
+#define STATUS_CONFIG_RMEGPE_NSEL 0x00000000 */
+/** Selected */
+#define STATUS_CONFIG_RMEGPE_SEL 0x00000010
+/** RM settings for GPE Memories
+    Read Marging Settings for VIRAGE Memories in GPE module */
+#define STATUS_CONFIG_RMGPE_MASK 0x0000000F
+/** field offset */
+#define STATUS_CONFIG_RMGPE_OFFSET 0
+
+/* Fields of "SPARE fuse register 1" */
+/** spare fuse1
+    eFuses not assigned to hw/sw, can be used for future applications */
+#define STATUS_FUSE1_F1_MASK 0xFFF00000
+/** field offset */
+#define STATUS_FUSE1_F1_OFFSET 20
+/** DCDC DDR OFFSET
+    offset error sense path */
+#define STATUS_FUSE1_OFFSETDDRDCDC_MASK 0x000F0000
+/** field offset */
+#define STATUS_FUSE1_OFFSETDDRDCDC_OFFSET 16
+/** DCDC DDR GAIN
+    gain error sense path */
+#define STATUS_FUSE1_GAINDDRDCDC_MASK 0x0000FC00
+/** field offset */
+#define STATUS_FUSE1_GAINDDRDCDC_OFFSET 10
+/** DCDC APD OFFSET
+    offset error sense path */
+#define STATUS_FUSE1_OFFSETAPDDCDC_MASK 0x000003C0
+/** field offset */
+#define STATUS_FUSE1_OFFSETAPDDCDC_OFFSET 6
+/** DCDC APD GAIN
+    gain error sense path */
+#define STATUS_FUSE1_GAINAPDDCDC_MASK 0x0000003F
+/** field offset */
+#define STATUS_FUSE1_GAINAPDDCDC_OFFSET 0
+
+/* Fields of "Configuration for sbs0 rambist" */
+/** Disable asc monitoring during boot-up
+    Bit is used to avoid asc output for reducing pattern count on testsystem */
+#define STATUS_MBCFG_ASC_DBGDIS 0x01000000
+/* Disable
+#define STATUS_MBCFG_ASC_DBGDIS_DIS 0x00000000 */
+/** Enable */
+#define STATUS_MBCFG_ASC_DBGDIS_EN 0x01000000
+/** Descrambling Enable/Disable
+    Enables Address and Data Descrambling for internal Memory Test */
+#define STATUS_MBCFG_DSC 0x00800000
+/* Disable
+#define STATUS_MBCFG_DSC_DIS 0x00000000 */
+/** Enable */
+#define STATUS_MBCFG_DSC_EN 0x00800000
+/** Enable repair mode
+    When bit is set redundancy repair mode is activated */
+#define STATUS_MBCFG_REPAIR 0x00400000
+/* Disable
+#define STATUS_MBCFG_REPAIR_DIS 0x00000000 */
+/** Enable */
+#define STATUS_MBCFG_REPAIR_EN 0x00400000
+/** DEBUG Mode */
+#define STATUS_MBCFG_DBG 0x00200000
+/* Disable
+#define STATUS_MBCFG_DBG_DIS 0x00000000 */
+/** Enable */
+#define STATUS_MBCFG_DBG_EN 0x00200000
+/** Retention Time
+    Length oft the Retention Time */
+#define STATUS_MBCFG_RTIME_MASK 0x001C0000
+/** field offset */
+#define STATUS_MBCFG_RTIME_OFFSET 18
+/** retention mode is switched off */
+#define STATUS_MBCFG_RTIME_RET0 0x00000000
+/** Retention time 50 ms */
+#define STATUS_MBCFG_RTIME_RET50 0x00040000
+/** Retention time 60 ms */
+#define STATUS_MBCFG_RTIME_RET60 0x00080000
+/** Retention time 70 ms */
+#define STATUS_MBCFG_RTIME_RET70 0x000C0000
+/** Retention time 80 ms */
+#define STATUS_MBCFG_RTIME_RET80 0x00100000
+/** Retention time 90 ms */
+#define STATUS_MBCFG_RTIME_RET90 0x00140000
+/** Retention time 1000 ms */
+#define STATUS_MBCFG_RTIME_RET1000 0x00180000
+/** Test ID
+    Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
+#define STATUS_MBCFG_TID_5_MASK 0x00038000
+/** field offset */
+#define STATUS_MBCFG_TID_5_OFFSET 15
+/** No test is performed */
+#define STATUS_MBCFG_TID_5_NONE 0x00000000
+/** March test */
+#define STATUS_MBCFG_TID_5_MARCH 0x00008000
+/** Checkerboard test */
+#define STATUS_MBCFG_TID_5_CHCK 0x00010000
+/** Hammer test */
+#define STATUS_MBCFG_TID_5_HAM 0x00018000
+/** Address decoder test */
+#define STATUS_MBCFG_TID_5_ADEC 0x00020000
+/** Write mask byte test */
+#define STATUS_MBCFG_TID_5_WMBYTE 0x00028000
+/** Reserved */
+#define STATUS_MBCFG_TID_5_RES 0x00030000
+/** Test ID
+    Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
+#define STATUS_MBCFG_TID_4_MASK 0x00007000
+/** field offset */
+#define STATUS_MBCFG_TID_4_OFFSET 12
+/** No test is performed */
+#define STATUS_MBCFG_TID_4_NONE 0x00000000
+/** March test */
+#define STATUS_MBCFG_TID_4_MARCH 0x00001000
+/** Checkerboard test */
+#define STATUS_MBCFG_TID_4_CHCK 0x00002000
+/** Hammer test */
+#define STATUS_MBCFG_TID_4_HAM 0x00003000
+/** Address decoder test */
+#define STATUS_MBCFG_TID_4_ADEC 0x00004000
+/** Write mask byte test */
+#define STATUS_MBCFG_TID_4_WMBYTE 0x00005000
+/** Reserved */
+#define STATUS_MBCFG_TID_4_RES 0x00006000
+/** Test ID
+    Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
+#define STATUS_MBCFG_TID_3_MASK 0x00000E00
+/** field offset */
+#define STATUS_MBCFG_TID_3_OFFSET 9
+/** No test is performed */
+#define STATUS_MBCFG_TID_3_NONE 0x00000000
+/** March test */
+#define STATUS_MBCFG_TID_3_MARCH 0x00000200
+/** Checkerboard test */
+#define STATUS_MBCFG_TID_3_CHCK 0x00000400
+/** Hammer test */
+#define STATUS_MBCFG_TID_3_HAM 0x00000600
+/** Address decoder test */
+#define STATUS_MBCFG_TID_3_ADEC 0x00000800
+/** Write mask byte test */
+#define STATUS_MBCFG_TID_3_WMBYTE 0x00000A00
+/** Reserved */
+#define STATUS_MBCFG_TID_3_RES 0x00000C00
+/** Test ID
+    Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
+#define STATUS_MBCFG_TID_2_MASK 0x000001C0
+/** field offset */
+#define STATUS_MBCFG_TID_2_OFFSET 6
+/** No test is performed */
+#define STATUS_MBCFG_TID_2_NONE 0x00000000
+/** March test */
+#define STATUS_MBCFG_TID_2_MARCH 0x00000040
+/** Checkerboard test */
+#define STATUS_MBCFG_TID_2_CHCK 0x00000080
+/** Hammer test */
+#define STATUS_MBCFG_TID_2_HAM 0x000000C0
+/** Address decoder test */
+#define STATUS_MBCFG_TID_2_ADEC 0x00000100
+/** Write mask byte test */
+#define STATUS_MBCFG_TID_2_WMBYTE 0x00000140
+/** Reserved */
+#define STATUS_MBCFG_TID_2_RES 0x00000180
+/** Test ID
+    Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
+#define STATUS_MBCFG_TID_1_MASK 0x00000038
+/** field offset */
+#define STATUS_MBCFG_TID_1_OFFSET 3
+/** No test is performed */
+#define STATUS_MBCFG_TID_1_NONE 0x00000000
+/** March test */
+#define STATUS_MBCFG_TID_1_MARCH 0x00000008
+/** Checkerboard test */
+#define STATUS_MBCFG_TID_1_CHCK 0x00000010
+/** Hammer test */
+#define STATUS_MBCFG_TID_1_HAM 0x00000018
+/** Address decoder test */
+#define STATUS_MBCFG_TID_1_ADEC 0x00000020
+/** Write mask byte test */
+#define STATUS_MBCFG_TID_1_WMBYTE 0x00000028
+/** Reserved */
+#define STATUS_MBCFG_TID_1_RES 0x00000030
+/** Test ID
+    Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
+#define STATUS_MBCFG_TID_0_MASK 0x00000007
+/** field offset */
+#define STATUS_MBCFG_TID_0_OFFSET 0
+/** No test is performed */
+#define STATUS_MBCFG_TID_0_NONE 0x00000000
+/** March test */
+#define STATUS_MBCFG_TID_0_MARCH 0x00000001
+/** Checkerboard test */
+#define STATUS_MBCFG_TID_0_CHCK 0x00000002
+/** Hammer test */
+#define STATUS_MBCFG_TID_0_HAM 0x00000003
+/** Address decoder test */
+#define STATUS_MBCFG_TID_0_ADEC 0x00000004
+/** Write mask byte test */
+#define STATUS_MBCFG_TID_0_WMBYTE 0x00000005
+/** Reserved */
+#define STATUS_MBCFG_TID_0_RES 0x00000006
+
+/* Fields of "sbs0 bist result and debug data" */
+/** BIST result and debug data
+    Stores additional debug information */
+#define STATUS_MBDATA_DATA_MASK 0xFFFFFFF8
+/** field offset */
+#define STATUS_MBDATA_DATA_OFFSET 3
+/** MBIST NOGO
+    The BIST failed and cannot be repaired due to many failure locations */
+#define STATUS_MBDATA_MBNOGO 0x00000004
+/** MBIST FAILED
+    The BIST failed but can be repaired */
+#define STATUS_MBDATA_MBFAIL 0x00000002
+/** MBIST PASSED
+    The BIST passed without any Failures */
+#define STATUS_MBDATA_MBPASS 0x00000001
+
+/*! @} */ /* STATUS_REGISTER */
+
+#endif /* _status_reg_h */
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/falcon/sys1_reg.h
@@ -0,0 +1,2008 @@
+/******************************************************************************
+
+                               Copyright (c) 2010
+                            Lantiq Deutschland GmbH
+
+  For licensing information, see the file 'LICENSE' in the root folder of
+  this software module.
+
+******************************************************************************/
+
+#ifndef _sys1_reg_h
+#define _sys1_reg_h
+
+/** \addtogroup SYS1_REGISTER
+   @{
+*/
+/* access macros */
+#define sys1_r32(reg) reg_r32(&sys1->reg)
+#define sys1_w32(val, reg) reg_w32(val, &sys1->reg)
+#define sys1_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &sys1->reg)
+#define sys1_r32_table(reg, idx) reg_r32_table(sys1->reg, idx)
+#define sys1_w32_table(val, reg, idx) reg_w32_table(val, sys1->reg, idx)
+#define sys1_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, sys1->reg, idx)
+#define sys1_adr_table(reg, idx) adr_table(sys1->reg, idx)
+
+
+/** SYS1 register structure */
+struct gpon_reg_sys1
+{
+   /** Clock Status Register */
+   unsigned int clks; /* 0x00000000 */
+   /** Clock Enable Register
+       Via this register the clocks for the domains can be enabled. */
+   unsigned int clken; /* 0x00000004 */
+   /** Clock Clear Register
+       Via this register the clocks for the domains can be disabled. */
+   unsigned int clkclr; /* 0x00000008 */
+   /** Reserved */
+   unsigned int res_0[5]; /* 0x0000000C */
+   /** Activation Status Register */
+   unsigned int acts; /* 0x00000020 */
+   /** Activation Register
+       Via this register the domains can be activated. */
+   unsigned int act; /* 0x00000024 */
+   /** Deactivation Register
+       Via this register the domains can be deactivated. */
+   unsigned int deact; /* 0x00000028 */
+   /** Reboot Trigger Register
+       Via this register the domains can be rebooted (sent through reset). */
+   unsigned int rbt; /* 0x0000002C */
+   /** Reserved */
+   unsigned int res_1[4]; /* 0x00000030 */
+   /** CPU0 Clock Control Register
+       Clock control register for CPU0 */
+   unsigned int cpu0cc; /* 0x00000040 */
+   /** Reserved */
+   unsigned int res_2[7]; /* 0x00000044 */
+   /** CPU0 Reset Source Register
+       Via this register the CPU can find the the root cause for the boot it currently goes through, and take the appropriate measures. */
+   unsigned int cpu0rs; /* 0x00000060 */
+   /** Reserved */
+   unsigned int res_3[7]; /* 0x00000064 */
+   /** CPU0 Wakeup Configuration Register
+       Controls the wakeup condition for CPU0. Note: The upper 16 bit of this register have to be set to the same value as the mask bits within the yield-resume interface block. If the yield-resume interface is not used at all, set the upper 16 bit to 0. */
+   unsigned int cpu0wcfg; /* 0x00000080 */
+   /** Reserved */
+   unsigned int res_4[7]; /* 0x00000084 */
+   /** Bootmode Control Register
+       Reflects the bootmode for the CPU and provides means to manipulate it. */
+   unsigned int bmc; /* 0x000000A0 */
+   /** Reserved */
+   unsigned int res_5[3]; /* 0x000000A4 */
+   /** Sleep Configuration Register */
+   unsigned int scfg; /* 0x000000B0 */
+   /** Power Down Configuration Register
+       Via this register the configuration is done whether in case of deactivation the power supply of the domain shall be switched off. */
+   unsigned int pdcfg; /* 0x000000B4 */
+   /** CLKO Pad Control Register
+       Controls the behaviour of the CLKO pad/ball. */
+   unsigned int clkoc; /* 0x000000B8 */
+   /** Infrastructure Control Register
+       Controls the behaviour of the components of the infrastructure block. */
+   unsigned int infrac; /* 0x000000BC */
+   /** HRST_OUT_N Control Register
+       Controls the behaviour of the HRST_OUT_N pin. */
+   unsigned int hrstoutc; /* 0x000000C0 */
+   /** EBU Clock Control Register
+       Clock control register for the EBU. */
+   unsigned int ebucc; /* 0x000000C4 */
+   /** Reserved */
+   unsigned int res_6[2]; /* 0x000000C8 */
+   /** NMI Status Register
+       The Test NMI source is the GPTC counter 1A overflow bit. */
+   unsigned int nmis; /* 0x000000D0 */
+   /** NMI Set Register */
+   unsigned int nmiset; /* 0x000000D4 */
+   /** NMI Clear Register */
+   unsigned int nmiclr; /* 0x000000D8 */
+   /** NMI Test Configuration Register */
+   unsigned int nmitcfg; /* 0x000000DC */
+   /** NMI VPE1 Control Register */
+   unsigned int nmivpe1c; /* 0x000000E0 */
+   /** Reserved */
+   unsigned int res_7[3]; /* 0x000000E4 */
+   /** IRN Capture Register
+       This register shows the currently active interrupt events masked with the corresponding enable bits of the IRNEN register. The interrupts can be acknowledged by a write operation. */
+   unsigned int irncr; /* 0x000000F0 */
+   /** IRN Interrupt Control Register
+       A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
+   unsigned int irnicr; /* 0x000000F4 */
+   /** IRN Interrupt Enable Register
+       This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IRNCR register and are not signalled via the interrupt line towards the controller. */
+   unsigned int irnen; /* 0x000000F8 */
+   /** Reserved */
+   unsigned int res_8; /* 0x000000FC */
+};
+
+
+/* Fields of "Clock Status Register" */
+/** STATUS Clock Enable
+    Shows the clock enable bit for the STATUS domain. This domain contains the STATUS block. */
+#define CLKS_STATUS 0x80000000
+/* Disable
+#define CLKS_STATUS_DIS 0x00000000 */
+/** Enable */
+#define CLKS_STATUS_EN 0x80000000
+/** SHA1 Clock Enable
+    Shows the clock enable bit for the SHA1 domain. This domain contains the SHA1 block. */
+#define CLKS_SHA1 0x40000000
+/* Disable
+#define CLKS_SHA1_DIS 0x00000000 */
+/** Enable */
+#define CLKS_SHA1_EN 0x40000000
+/** AES Clock Enable
+    Shows the clock enable bit for the AES domain. This domain contains the AES block. */
+#define CLKS_AES 0x20000000
+/* Disable
+#define CLKS_AES_DIS 0x00000000 */
+/** Enable */
+#define CLKS_AES_EN 0x20000000
+/** PCM Clock Enable
+    Shows the clock enable bit for the PCM domain. This domain contains the PCM interface block. */
+#define CLKS_PCM 0x10000000
+/* Disable
+#define CLKS_PCM_DIS 0x00000000 */
+/** Enable */
+#define CLKS_PCM_EN 0x10000000
+/** FSCT Clock Enable
+    Shows the clock enable bit for the FSCT domain. This domain contains the FSCT block. */
+#define CLKS_FSCT 0x08000000
+/* Disable
+#define CLKS_FSCT_DIS 0x00000000 */
+/** Enable */
+#define CLKS_FSCT_EN 0x08000000
+/** GPTC Clock Enable
+    Shows the clock enable bit for the GPTC domain. This domain contains the GPTC block. */
+#define CLKS_GPTC 0x04000000
+/* Disable
+#define CLKS_GPTC_DIS 0x00000000 */
+/** Enable */
+#define CLKS_GPTC_EN 0x04000000
+/** MPS Clock Enable
+    Shows the clock enable bit for the MPS domain. This domain contains the MPS block. */
+#define CLKS_MPS 0x02000000
+/* Disable
+#define CLKS_MPS_DIS 0x00000000 */
+/** Enable */
+#define CLKS_MPS_EN 0x02000000
+/** DFEV0 Clock Enable
+    Shows the clock enable bit for the DFEV0 domain. This domain contains the DFEV0 block. */
+#define CLKS_DFEV0 0x01000000
+/* Disable
+#define CLKS_DFEV0_DIS 0x00000000 */
+/** Enable */
+#define CLKS_DFEV0_EN 0x01000000
+/** PADCTRL4 Clock Enable
+    Shows the clock enable bit for the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
+#define CLKS_PADCTRL4 0x00400000
+/* Disable
+#define CLKS_PADCTRL4_DIS 0x00000000 */
+/** Enable */
+#define CLKS_PADCTRL4_EN 0x00400000
+/** PADCTRL3 Clock Enable
+    Shows the clock enable bit for the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
+#define CLKS_PADCTRL3 0x00200000
+/* Disable
+#define CLKS_PADCTRL3_DIS 0x00000000 */
+/** Enable */
+#define CLKS_PADCTRL3_EN 0x00200000
+/** PADCTRL1 Clock Enable
+    Shows the clock enable bit for the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
+#define CLKS_PADCTRL1 0x00100000
+/* Disable
+#define CLKS_PADCTRL1_DIS 0x00000000 */
+/** Enable */
+#define CLKS_PADCTRL1_EN 0x00100000
+/** P4 Clock Enable
+    Shows the clock enable bit for the P4 domain. This domain contains the P4 instance of the GPIO block. */
+#define CLKS_P4 0x00040000
+/* Disable
+#define CLKS_P4_DIS 0x00000000 */
+/** Enable */
+#define CLKS_P4_EN 0x00040000
+/** P3 Clock Enable
+    Shows the clock enable bit for the P3 domain. This domain contains the P3 instance of the GPIO block. */
+#define CLKS_P3 0x00020000
+/* Disable
+#define CLKS_P3_DIS 0x00000000 */
+/** Enable */
+#define CLKS_P3_EN 0x00020000
+/** P1 Clock Enable
+    Shows the clock enable bit for the P1 domain. This domain contains the P1 instance of the GPIO block. */
+#define CLKS_P1 0x00010000
+/* Disable
+#define CLKS_P1_DIS 0x00000000 */
+/** Enable */
+#define CLKS_P1_EN 0x00010000
+/** HOST Clock Enable
+    Shows the clock enable bit for the HOST domain. This domain contains the HOST interface block. */
+#define CLKS_HOST 0x00008000
+/* Disable
+#define CLKS_HOST_DIS 0x00000000 */
+/** Enable */
+#define CLKS_HOST_EN 0x00008000
+/** I2C Clock Enable
+    Shows the clock enable bit for the I2C domain. This domain contains the I2C interface block. */
+#define CLKS_I2C 0x00004000
+/* Disable
+#define CLKS_I2C_DIS 0x00000000 */
+/** Enable */
+#define CLKS_I2C_EN 0x00004000
+/** SSC0 Clock Enable
+    Shows the clock enable bit for the SSC0 domain. This domain contains the SSC0 interface block. */
+#define CLKS_SSC0 0x00002000
+/* Disable
+#define CLKS_SSC0_DIS 0x00000000 */
+/** Enable */
+#define CLKS_SSC0_EN 0x00002000
+/** ASC0 Clock Enable
+    Shows the clock enable bit for the ASC0 domain. This domain contains the ASC0 interface block. */
+#define CLKS_ASC0 0x00001000
+/* Disable
+#define CLKS_ASC0_DIS 0x00000000 */
+/** Enable */
+#define CLKS_ASC0_EN 0x00001000
+/** ASC1 Clock Enable
+    Shows the clock enable bit for the ASC1 domain. This domain contains the ASC1 block. */
+#define CLKS_ASC1 0x00000800
+/* Disable
+#define CLKS_ASC1_DIS 0x00000000 */
+/** Enable */
+#define CLKS_ASC1_EN 0x00000800
+/** DCDCAPD Clock Enable
+    Shows the clock enable bit for the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
+#define CLKS_DCDCAPD 0x00000400
+/* Disable
+#define CLKS_DCDCAPD_DIS 0x00000000 */
+/** Enable */
+#define CLKS_DCDCAPD_EN 0x00000400
+/** DCDCDDR Clock Enable
+    Shows the clock enable bit for the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
+#define CLKS_DCDCDDR 0x00000200
+/* Disable
+#define CLKS_DCDCDDR_DIS 0x00000000 */
+/** Enable */
+#define CLKS_DCDCDDR_EN 0x00000200
+/** DCDC1V0 Clock Enable
+    Shows the clock enable bit for the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
+#define CLKS_DCDC1V0 0x00000100
+/* Disable
+#define CLKS_DCDC1V0_DIS 0x00000000 */
+/** Enable */
+#define CLKS_DCDC1V0_EN 0x00000100
+/** TRC2MEM Clock Enable
+    Shows the clock enable bit for the TRC2MEM domain. This domain contains the TRC2MEM block. */
+#define CLKS_TRC2MEM 0x00000040
+/* Disable
+#define CLKS_TRC2MEM_DIS 0x00000000 */
+/** Enable */
+#define CLKS_TRC2MEM_EN 0x00000040
+/** DDR Clock Enable
+    Shows the clock enable bit for the DDR domain. This domain contains the DDR interface block. */
+#define CLKS_DDR 0x00000020
+/* Disable
+#define CLKS_DDR_DIS 0x00000000 */
+/** Enable */
+#define CLKS_DDR_EN 0x00000020
+/** EBU Clock Enable
+    Shows the clock enable bit for the EBU domain. This domain contains the EBU interface block. */
+#define CLKS_EBU 0x00000010
+/* Disable
+#define CLKS_EBU_DIS 0x00000000 */
+/** Enable */
+#define CLKS_EBU_EN 0x00000010
+
+/* Fields of "Clock Enable Register" */
+/** Set Clock Enable STATUS
+    Sets the clock enable bit of the STATUS domain. This domain contains the STATUS block. */
+#define CLKEN_STATUS 0x80000000
+/* No-Operation
+#define CLKEN_STATUS_NOP 0x00000000 */
+/** Set */
+#define CLKEN_STATUS_SET 0x80000000
+/** Set Clock Enable SHA1
+    Sets the clock enable bit of the SHA1 domain. This domain contains the SHA1 block. */
+#define CLKEN_SHA1 0x40000000
+/* No-Operation
+#define CLKEN_SHA1_NOP 0x00000000 */
+/** Set */
+#define CLKEN_SHA1_SET 0x40000000
+/** Set Clock Enable AES
+    Sets the clock enable bit of the AES domain. This domain contains the AES block. */
+#define CLKEN_AES 0x20000000
+/* No-Operation
+#define CLKEN_AES_NOP 0x00000000 */
+/** Set */
+#define CLKEN_AES_SET 0x20000000
+/** Set Clock Enable PCM
+    Sets the clock enable bit of the PCM domain. This domain contains the PCM interface block. */
+#define CLKEN_PCM 0x10000000
+/* No-Operation
+#define CLKEN_PCM_NOP 0x00000000 */
+/** Set */
+#define CLKEN_PCM_SET 0x10000000
+/** Set Clock Enable FSCT
+    Sets the clock enable bit of the FSCT domain. This domain contains the FSCT block. */
+#define CLKEN_FSCT 0x08000000
+/* No-Operation
+#define CLKEN_FSCT_NOP 0x00000000 */
+/** Set */
+#define CLKEN_FSCT_SET 0x08000000
+/** Set Clock Enable GPTC
+    Sets the clock enable bit of the GPTC domain. This domain contains the GPTC block. */
+#define CLKEN_GPTC 0x04000000
+/* No-Operation
+#define CLKEN_GPTC_NOP 0x00000000 */
+/** Set */
+#define CLKEN_GPTC_SET 0x04000000
+/** Set Clock Enable MPS
+    Sets the clock enable bit of the MPS domain. This domain contains the MPS block. */
+#define CLKEN_MPS 0x02000000
+/* No-Operation
+#define CLKEN_MPS_NOP 0x00000000 */
+/** Set */
+#define CLKEN_MPS_SET 0x02000000
+/** Set Clock Enable DFEV0
+    Sets the clock enable bit of the DFEV0 domain. This domain contains the DFEV0 block. */
+#define CLKEN_DFEV0 0x01000000
+/* No-Operation
+#define CLKEN_DFEV0_NOP 0x00000000 */
+/** Set */
+#define CLKEN_DFEV0_SET 0x01000000
+/** Set Clock Enable PADCTRL4
+    Sets the clock enable bit of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
+#define CLKEN_PADCTRL4 0x00400000
+/* No-Operation
+#define CLKEN_PADCTRL4_NOP 0x00000000 */
+/** Set */
+#define CLKEN_PADCTRL4_SET 0x00400000
+/** Set Clock Enable PADCTRL3
+    Sets the clock enable bit of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
+#define CLKEN_PADCTRL3 0x00200000
+/* No-Operation
+#define CLKEN_PADCTRL3_NOP 0x00000000 */
+/** Set */
+#define CLKEN_PADCTRL3_SET 0x00200000
+/** Set Clock Enable PADCTRL1
+    Sets the clock enable bit of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
+#define CLKEN_PADCTRL1 0x00100000
+/* No-Operation
+#define CLKEN_PADCTRL1_NOP 0x00000000 */
+/** Set */
+#define CLKEN_PADCTRL1_SET 0x00100000
+/** Set Clock Enable P4
+    Sets the clock enable bit of the P4 domain. This domain contains the P4 instance of the GPIO block. */
+#define CLKEN_P4 0x00040000
+/* No-Operation
+#define CLKEN_P4_NOP 0x00000000 */
+/** Set */
+#define CLKEN_P4_SET 0x00040000
+/** Set Clock Enable P3
+    Sets the clock enable bit of the P3 domain. This domain contains the P3 instance of the GPIO block. */
+#define CLKEN_P3 0x00020000
+/* No-Operation
+#define CLKEN_P3_NOP 0x00000000 */
+/** Set */
+#define CLKEN_P3_SET 0x00020000
+/** Set Clock Enable P1
+    Sets the clock enable bit of the P1 domain. This domain contains the P1 instance of the GPIO block. */
+#define CLKEN_P1 0x00010000
+/* No-Operation
+#define CLKEN_P1_NOP 0x00000000 */
+/** Set */
+#define CLKEN_P1_SET 0x00010000
+/** Set Clock Enable HOST
+    Sets the clock enable bit of the HOST domain. This domain contains the HOST interface block. */
+#define CLKEN_HOST 0x00008000
+/* No-Operation
+#define CLKEN_HOST_NOP 0x00000000 */
+/** Set */
+#define CLKEN_HOST_SET 0x00008000
+/** Set Clock Enable I2C
+    Sets the clock enable bit of the I2C domain. This domain contains the I2C interface block. */
+#define CLKEN_I2C 0x00004000
+/* No-Operation
+#define CLKEN_I2C_NOP 0x00000000 */
+/** Set */
+#define CLKEN_I2C_SET 0x00004000
+/** Set Clock Enable SSC0
+    Sets the clock enable bit of the SSC0 domain. This domain contains the SSC0 interface block. */
+#define CLKEN_SSC0 0x00002000
+/* No-Operation
+#define CLKEN_SSC0_NOP 0x00000000 */
+/** Set */
+#define CLKEN_SSC0_SET 0x00002000
+/** Set Clock Enable ASC0
+    Sets the clock enable bit of the ASC0 domain. This domain contains the ASC0 interface block. */
+#define CLKEN_ASC0 0x00001000
+/* No-Operation
+#define CLKEN_ASC0_NOP 0x00000000 */
+/** Set */
+#define CLKEN_ASC0_SET 0x00001000
+/** Set Clock Enable ASC1
+    Sets the clock enable bit of the ASC1 domain. This domain contains the ASC1 block. */
+#define CLKEN_ASC1 0x00000800
+/* No-Operation
+#define CLKEN_ASC1_NOP 0x00000000 */
+/** Set */
+#define CLKEN_ASC1_SET 0x00000800
+/** Set Clock Enable DCDCAPD
+    Sets the clock enable bit of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
+#define CLKEN_DCDCAPD 0x00000400
+/* No-Operation
+#define CLKEN_DCDCAPD_NOP 0x00000000 */
+/** Set */
+#define CLKEN_DCDCAPD_SET 0x00000400
+/** Set Clock Enable DCDCDDR
+    Sets the clock enable bit of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
+#define CLKEN_DCDCDDR 0x00000200
+/* No-Operation
+#define CLKEN_DCDCDDR_NOP 0x00000000 */
+/** Set */
+#define CLKEN_DCDCDDR_SET 0x00000200
+/** Set Clock Enable DCDC1V0
+    Sets the clock enable bit of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
+#define CLKEN_DCDC1V0 0x00000100
+/* No-Operation
+#define CLKEN_DCDC1V0_NOP 0x00000000 */
+/** Set */
+#define CLKEN_DCDC1V0_SET 0x00000100
+/** Set Clock Enable TRC2MEM
+    Sets the clock enable bit of the TRC2MEM domain. This domain contains the TRC2MEM block. */
+#define CLKEN_TRC2MEM 0x00000040
+/* No-Operation
+#define CLKEN_TRC2MEM_NOP 0x00000000 */
+/** Set */
+#define CLKEN_TRC2MEM_SET 0x00000040
+/** Set Clock Enable DDR
+    Sets the clock enable bit of the DDR domain. This domain contains the DDR interface block. */
+#define CLKEN_DDR 0x00000020
+/* No-Operation
+#define CLKEN_DDR_NOP 0x00000000 */
+/** Set */
+#define CLKEN_DDR_SET 0x00000020
+/** Set Clock Enable EBU
+    Sets the clock enable bit of the EBU domain. This domain contains the EBU interface block. */
+#define CLKEN_EBU 0x00000010
+/* No-Operation
+#define CLKEN_EBU_NOP 0x00000000 */
+/** Set */
+#define CLKEN_EBU_SET 0x00000010
+
+/* Fields of "Clock Clear Register" */
+/** Clear Clock Enable STATUS
+    Clears the clock enable bit of the STATUS domain. This domain contains the STATUS block. */
+#define CLKCLR_STATUS 0x80000000
+/* No-Operation
+#define CLKCLR_STATUS_NOP 0x00000000 */
+/** Clear */
+#define CLKCLR_STATUS_CLR 0x80000000
+/** Clear Clock Enable SHA1
+    Clears the clock enable bit of the SHA1 domain. This domain contains the SHA1 block. */
+#define CLKCLR_SHA1 0x40000000
+/* No-Operation
+#define CLKCLR_SHA1_NOP 0x00000000 */
+/** Clear */
+#define CLKCLR_SHA1_CLR 0x40000000
+/** Clear Clock Enable AES
+    Clears the clock enable bit of the AES domain. This domain contains the AES block. */
+#define CLKCLR_AES 0x20000000
+/* No-Operation
+#define CLKCLR_AES_NOP 0x00000000 */
+/** Clear */
+#define CLKCLR_AES_CLR 0x20000000
+/** Clear Clock Enable PCM
+    Clears the clock enable bit of the PCM domain. This domain contains the PCM interface block. */
+#define CLKCLR_PCM 0x10000000
+/* No-Operation
+#define CLKCLR_PCM_NOP 0x00000000 */
+/** Clear */
+#define CLKCLR_PCM_CLR 0x10000000
+/** Clear Clock Enable FSCT
+    Clears the clock enable bit of the FSCT domain. This domain contains the FSCT block. */
+#define CLKCLR_FSCT 0x08000000
+/* No-Operation
+#define CLKCLR_FSCT_NOP 0x00000000 */
+/** Clear */
+#define CLKCLR_FSCT_CLR 0x08000000
+/** Clear Clock Enable GPTC
+    Clears the clock enable bit of the GPTC domain. This domain contains the GPTC block. */
+#define CLKCLR_GPTC 0x04000000
+/* No-Operation
+#define CLKCLR_GPTC_NOP 0x00000000 */
+/** Clear */
+#define CLKCLR_GPTC_CLR 0x04000000
+/** Clear Clock Enable MPS
+    Clears the clock enable bit of the MPS domain. This domain contains the MPS block. */
+#define CLKCLR_MPS 0x02000000
+/* No-Operation
+#define CLKCLR_MPS_NOP 0x00000000 */
+/** Clear */
+#define CLKCLR_MPS_CLR 0x02000000
+/** Clear Clock Enable DFEV0
+    Clears the clock enable bit of the DFEV0 domain. This domain contains the DFEV0 block. */
+#define CLKCLR_DFEV0 0x01000000
+/* No-Operation
+#define CLKCLR_DFEV0_NOP 0x00000000 */
+/** Clear */
+#define CLKCLR_DFEV0_CLR 0x01000000
+/** Clear Clock Enable PADCTRL4
+    Clears the clock enable bit of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
+#define CLKCLR_PADCTRL4 0x00400000
+/* No-Operation
+#define CLKCLR_PADCTRL4_NOP 0x00000000 */
+/** Clear */
+#define CLKCLR_PADCTRL4_CLR 0x00400000
+/** Clear Clock Enable PADCTRL3
+    Clears the clock enable bit of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
+#define CLKCLR_PADCTRL3 0x00200000
+/* No-Operation
+#define CLKCLR_PADCTRL3_NOP 0x00000000 */
+/** Clear */
+#define CLKCLR_PADCTRL3_CLR 0x00200000
+/** Clear Clock Enable PADCTRL1
+    Clears the clock enable bit of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
+#define CLKCLR_PADCTRL1 0x00100000
+/* No-Operation
+#define CLKCLR_PADCTRL1_NOP 0x00000000 */
+/** Clear */
+#define CLKCLR_PADCTRL1_CLR 0x00100000
+/** Clear Clock Enable P4
+    Clears the clock enable bit of the P4 domain. This domain contains the P4 instance of the GPIO block. */
+#define CLKCLR_P4 0x00040000
+/* No-Operation
+#define CLKCLR_P4_NOP 0x00000000 */
+/** Clear */
+#define CLKCLR_P4_CLR 0x00040000
+/** Clear Clock Enable P3
+    Clears the clock enable bit of the P3 domain. This domain contains the P3 instance of the GPIO block. */
+#define CLKCLR_P3 0x00020000
+/* No-Operation
+#define CLKCLR_P3_NOP 0x00000000 */
+/** Clear */
+#define CLKCLR_P3_CLR 0x00020000
+/** Clear Clock Enable P1
+    Clears the clock enable bit of the P1 domain. This domain contains the P1 instance of the GPIO block. */
+#define CLKCLR_P1 0x00010000
+/* No-Operation
+#define CLKCLR_P1_NOP 0x00000000 */
+/** Clear */
+#define CLKCLR_P1_CLR 0x00010000
+/** Clear Clock Enable HOST
+    Clears the clock enable bit of the HOST domain. This domain contains the HOST interface block. */
+#define CLKCLR_HOST 0x00008000
+/* No-Operation
+#define CLKCLR_HOST_NOP 0x00000000 */
+/** Clear */
+#define CLKCLR_HOST_CLR 0x00008000
+/** Clear Clock Enable I2C
+    Clears the clock enable bit of the I2C domain. This domain contains the I2C interface block. */
+#define CLKCLR_I2C 0x00004000
+/* No-Operation
+#define CLKCLR_I2C_NOP 0x00000000 */
+/** Clear */
+#define CLKCLR_I2C_CLR 0x00004000
+/** Clear Clock Enable SSC0
+    Clears the clock enable bit of the SSC0 domain. This domain contains the SSC0 interface block. */
+#define CLKCLR_SSC0 0x00002000
+/* No-Operation
+#define CLKCLR_SSC0_NOP 0x00000000 */
+/** Clear */
+#define CLKCLR_SSC0_CLR 0x00002000
+/** Clear Clock Enable ASC0
+    Clears the clock enable bit of the ASC0 domain. This domain contains the ASC0 interface block. */
+#define CLKCLR_ASC0 0x00001000
+/* No-Operation
+#define CLKCLR_ASC0_NOP 0x00000000 */
+/** Clear */
+#define CLKCLR_ASC0_CLR 0x00001000
+/** Clear Clock Enable ASC1
+    Clears the clock enable bit of the ASC1 domain. This domain contains the ASC1 block. */
+#define CLKCLR_ASC1 0x00000800
+/* No-Operation
+#define CLKCLR_ASC1_NOP 0x00000000 */
+/** Clear */
+#define CLKCLR_ASC1_CLR 0x00000800
+/** Clear Clock Enable DCDCAPD
+    Clears the clock enable bit of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
+#define CLKCLR_DCDCAPD 0x00000400
+/* No-Operation
+#define CLKCLR_DCDCAPD_NOP 0x00000000 */
+/** Clear */
+#define CLKCLR_DCDCAPD_CLR 0x00000400
+/** Clear Clock Enable DCDCDDR
+    Clears the clock enable bit of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
+#define CLKCLR_DCDCDDR 0x00000200
+/* No-Operation
+#define CLKCLR_DCDCDDR_NOP 0x00000000 */
+/** Clear */
+#define CLKCLR_DCDCDDR_CLR 0x00000200
+/** Clear Clock Enable DCDC1V0
+    Clears the clock enable bit of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
+#define CLKCLR_DCDC1V0 0x00000100
+/* No-Operation
+#define CLKCLR_DCDC1V0_NOP 0x00000000 */
+/** Clear */
+#define CLKCLR_DCDC1V0_CLR 0x00000100
+/** Clear Clock Enable TRC2MEM
+    Clears the clock enable bit of the TRC2MEM domain. This domain contains the TRC2MEM block. */
+#define CLKCLR_TRC2MEM 0x00000040
+/* No-Operation
+#define CLKCLR_TRC2MEM_NOP 0x00000000 */
+/** Clear */
+#define CLKCLR_TRC2MEM_CLR 0x00000040
+/** Clear Clock Enable DDR
+    Clears the clock enable bit of the DDR domain. This domain contains the DDR interface block. */
+#define CLKCLR_DDR 0x00000020
+/* No-Operation
+#define CLKCLR_DDR_NOP 0x00000000 */
+/** Clear */
+#define CLKCLR_DDR_CLR 0x00000020
+/** Clear Clock Enable EBU
+    Clears the clock enable bit of the EBU domain. This domain contains the EBU interface block. */
+#define CLKCLR_EBU 0x00000010
+/* No-Operation
+#define CLKCLR_EBU_NOP 0x00000000 */
+/** Clear */
+#define CLKCLR_EBU_CLR 0x00000010
+
+/* Fields of "Activation Status Register" */
+/** STATUS Status
+    Shows the activation status of the STATUS domain. This domain contains the STATUS block. */
+#define ACTS_STATUS 0x80000000
+/* The block is inactive.
+#define ACTS_STATUS_INACT 0x00000000 */
+/** The block is active. */
+#define ACTS_STATUS_ACT 0x80000000
+/** SHA1 Status
+    Shows the activation status of the SHA1 domain. This domain contains the SHA1 block. */
+#define ACTS_SHA1 0x40000000
+/* The block is inactive.
+#define ACTS_SHA1_INACT 0x00000000 */
+/** The block is active. */
+#define ACTS_SHA1_ACT 0x40000000
+/** AES Status
+    Shows the activation status of the AES domain. This domain contains the AES block. */
+#define ACTS_AES 0x20000000
+/* The block is inactive.
+#define ACTS_AES_INACT 0x00000000 */
+/** The block is active. */
+#define ACTS_AES_ACT 0x20000000
+/** PCM Status
+    Shows the activation status of the PCM domain. This domain contains the PCM interface block. */
+#define ACTS_PCM 0x10000000
+/* The block is inactive.
+#define ACTS_PCM_INACT 0x00000000 */
+/** The block is active. */
+#define ACTS_PCM_ACT 0x10000000
+/** FSCT Status
+    Shows the activation status of the FSCT domain. This domain contains the FSCT block. */
+#define ACTS_FSCT 0x08000000
+/* The block is inactive.
+#define ACTS_FSCT_INACT 0x00000000 */
+/** The block is active. */
+#define ACTS_FSCT_ACT 0x08000000
+/** GPTC Status
+    Shows the activation status of the GPTC domain. This domain contains the GPTC block. */
+#define ACTS_GPTC 0x04000000
+/* The block is inactive.
+#define ACTS_GPTC_INACT 0x00000000 */
+/** The block is active. */
+#define ACTS_GPTC_ACT 0x04000000
+/** MPS Status
+    Shows the activation status of the MPS domain. This domain contains the MPS block. */
+#define ACTS_MPS 0x02000000
+/* The block is inactive.
+#define ACTS_MPS_INACT 0x00000000 */
+/** The block is active. */
+#define ACTS_MPS_ACT 0x02000000
+/** DFEV0 Status
+    Shows the activation status of the DFEV0 domain. This domain contains the DFEV0 block. */
+#define ACTS_DFEV0 0x01000000
+/* The block is inactive.
+#define ACTS_DFEV0_INACT 0x00000000 */
+/** The block is active. */
+#define ACTS_DFEV0_ACT 0x01000000
+/** PADCTRL4 Status
+    Shows the activation status of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
+#define ACTS_PADCTRL4 0x00400000
+/* The block is inactive.
+#define ACTS_PADCTRL4_INACT 0x00000000 */
+/** The block is active. */
+#define ACTS_PADCTRL4_ACT 0x00400000
+/** PADCTRL3 Status
+    Shows the activation status of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
+#define ACTS_PADCTRL3 0x00200000
+/* The block is inactive.
+#define ACTS_PADCTRL3_INACT 0x00000000 */
+/** The block is active. */
+#define ACTS_PADCTRL3_ACT 0x00200000
+/** PADCTRL1 Status
+    Shows the activation status of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
+#define ACTS_PADCTRL1 0x00100000
+/* The block is inactive.
+#define ACTS_PADCTRL1_INACT 0x00000000 */
+/** The block is active. */
+#define ACTS_PADCTRL1_ACT 0x00100000
+/** P4 Status
+    Shows the activation status of the P4 domain. This domain contains the P4 instance of the GPIO block. */
+#define ACTS_P4 0x00040000
+/* The block is inactive.
+#define ACTS_P4_INACT 0x00000000 */
+/** The block is active. */
+#define ACTS_P4_ACT 0x00040000
+/** P3 Status
+    Shows the activation status of the P3 domain. This domain contains the P3 instance of the GPIO block. */
+#define ACTS_P3 0x00020000
+/* The block is inactive.
+#define ACTS_P3_INACT 0x00000000 */
+/** The block is active. */
+#define ACTS_P3_ACT 0x00020000
+/** P1 Status
+    Shows the activation status of the P1 domain. This domain contains the P1 instance of the GPIO block. */
+#define ACTS_P1 0x00010000
+/* The block is inactive.
+#define ACTS_P1_INACT 0x00000000 */
+/** The block is active. */
+#define ACTS_P1_ACT 0x00010000
+/** HOST Status
+    Shows the activation status of the HOST domain. This domain contains the HOST interface block. */
+#define ACTS_HOST 0x00008000
+/* The block is inactive.
+#define ACTS_HOST_INACT 0x00000000 */
+/** The block is active. */
+#define ACTS_HOST_ACT 0x00008000
+/** I2C Status
+    Shows the activation status of the I2C domain. This domain contains the I2C interface block. */
+#define ACTS_I2C 0x00004000
+/* The block is inactive.
+#define ACTS_I2C_INACT 0x00000000 */
+/** The block is active. */
+#define ACTS_I2C_ACT 0x00004000
+/** SSC0 Status
+    Shows the activation status of the SSC0 domain. This domain contains the SSC0 interface block. */
+#define ACTS_SSC0 0x00002000
+/* The block is inactive.
+#define ACTS_SSC0_INACT 0x00000000 */
+/** The block is active. */
+#define ACTS_SSC0_ACT 0x00002000
+/** ASC0 Status
+    Shows the activation status of the ASC0 domain. This domain contains the ASC0 interface block. */
+#define ACTS_ASC0 0x00001000
+/* The block is inactive.
+#define ACTS_ASC0_INACT 0x00000000 */
+/** The block is active. */
+#define ACTS_ASC0_ACT 0x00001000
+/** ASC1 Status
+    Shows the activation status of the ASC1 domain. This domain contains the ASC1 block. */
+#define ACTS_ASC1 0x00000800
+/* The block is inactive.
+#define ACTS_ASC1_INACT 0x00000000 */
+/** The block is active. */
+#define ACTS_ASC1_ACT 0x00000800
+/** DCDCAPD Status
+    Shows the activation status of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
+#define ACTS_DCDCAPD 0x00000400
+/* The block is inactive.
+#define ACTS_DCDCAPD_INACT 0x00000000 */
+/** The block is active. */
+#define ACTS_DCDCAPD_ACT 0x00000400
+/** DCDCDDR Status
+    Shows the activation status of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
+#define ACTS_DCDCDDR 0x00000200
+/* The block is inactive.
+#define ACTS_DCDCDDR_INACT 0x00000000 */
+/** The block is active. */
+#define ACTS_DCDCDDR_ACT 0x00000200
+/** DCDC1V0 Status
+    Shows the activation status of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
+#define ACTS_DCDC1V0 0x00000100
+/* The block is inactive.
+#define ACTS_DCDC1V0_INACT 0x00000000 */
+/** The block is active. */
+#define ACTS_DCDC1V0_ACT 0x00000100
+/** TRC2MEM Status
+    Shows the activation status of the TRC2MEM domain. This domain contains the TRC2MEM block. */
+#define ACTS_TRC2MEM 0x00000040
+/* The block is inactive.
+#define ACTS_TRC2MEM_INACT 0x00000000 */
+/** The block is active. */
+#define ACTS_TRC2MEM_ACT 0x00000040
+/** DDR Status
+    Shows the activation status of the DDR domain. This domain contains the DDR interface block. */
+#define ACTS_DDR 0x00000020
+/* The block is inactive.
+#define ACTS_DDR_INACT 0x00000000 */
+/** The block is active. */
+#define ACTS_DDR_ACT 0x00000020
+/** EBU Status
+    Shows the activation status of the EBU domain. This domain contains the EBU interface block. */
+#define ACTS_EBU 0x00000010
+/* The block is inactive.
+#define ACTS_EBU_INACT 0x00000000 */
+/** The block is active. */
+#define ACTS_EBU_ACT 0x00000010
+
+/* Fields of "Activation Register" */
+/** Activate STATUS
+    Sets the activation flag of the STATUS domain. This domain contains the STATUS block. */
+#define ACT_STATUS 0x80000000
+/* No-Operation
+#define ACT_STATUS_NOP 0x00000000 */
+/** Set */
+#define ACT_STATUS_SET 0x80000000
+/** Activate SHA1
+    Sets the activation flag of the SHA1 domain. This domain contains the SHA1 block. */
+#define ACT_SHA1 0x40000000
+/* No-Operation
+#define ACT_SHA1_NOP 0x00000000 */
+/** Set */
+#define ACT_SHA1_SET 0x40000000
+/** Activate AES
+    Sets the activation flag of the AES domain. This domain contains the AES block. */
+#define ACT_AES 0x20000000
+/* No-Operation
+#define ACT_AES_NOP 0x00000000 */
+/** Set */
+#define ACT_AES_SET 0x20000000
+/** Activate PCM
+    Sets the activation flag of the PCM domain. This domain contains the PCM interface block. */
+#define ACT_PCM 0x10000000
+/* No-Operation
+#define ACT_PCM_NOP 0x00000000 */
+/** Set */
+#define ACT_PCM_SET 0x10000000
+/** Activate FSCT
+    Sets the activation flag of the FSCT domain. This domain contains the FSCT block. */
+#define ACT_FSCT 0x08000000
+/* No-Operation
+#define ACT_FSCT_NOP 0x00000000 */
+/** Set */
+#define ACT_FSCT_SET 0x08000000
+/** Activate GPTC
+    Sets the activation flag of the GPTC domain. This domain contains the GPTC block. */
+#define ACT_GPTC 0x04000000
+/* No-Operation
+#define ACT_GPTC_NOP 0x00000000 */
+/** Set */
+#define ACT_GPTC_SET 0x04000000
+/** Activate MPS
+    Sets the activation flag of the MPS domain. This domain contains the MPS block. */
+#define ACT_MPS 0x02000000
+/* No-Operation
+#define ACT_MPS_NOP 0x00000000 */
+/** Set */
+#define ACT_MPS_SET 0x02000000
+/** Activate DFEV0
+    Sets the activation flag of the DFEV0 domain. This domain contains the DFEV0 block. */
+#define ACT_DFEV0 0x01000000
+/* No-Operation
+#define ACT_DFEV0_NOP 0x00000000 */
+/** Set */
+#define ACT_DFEV0_SET 0x01000000
+/** Activate PADCTRL4
+    Sets the activation flag of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
+#define ACT_PADCTRL4 0x00400000
+/* No-Operation
+#define ACT_PADCTRL4_NOP 0x00000000 */
+/** Set */
+#define ACT_PADCTRL4_SET 0x00400000
+/** Activate PADCTRL3
+    Sets the activation flag of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
+#define ACT_PADCTRL3 0x00200000
+/* No-Operation
+#define ACT_PADCTRL3_NOP 0x00000000 */
+/** Set */
+#define ACT_PADCTRL3_SET 0x00200000
+/** Activate PADCTRL1
+    Sets the activation flag of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
+#define ACT_PADCTRL1 0x00100000
+/* No-Operation
+#define ACT_PADCTRL1_NOP 0x00000000 */
+/** Set */
+#define ACT_PADCTRL1_SET 0x00100000
+/** Activate P4
+    Sets the activation flag of the P4 domain. This domain contains the P4 instance of the GPIO block. */
+#define ACT_P4 0x00040000
+/* No-Operation
+#define ACT_P4_NOP 0x00000000 */
+/** Set */
+#define ACT_P4_SET 0x00040000
+/** Activate P3
+    Sets the activation flag of the P3 domain. This domain contains the P3 instance of the GPIO block. */
+#define ACT_P3 0x00020000
+/* No-Operation
+#define ACT_P3_NOP 0x00000000 */
+/** Set */
+#define ACT_P3_SET 0x00020000
+/** Activate P1
+    Sets the activation flag of the P1 domain. This domain contains the P1 instance of the GPIO block. */
+#define ACT_P1 0x00010000
+/* No-Operation
+#define ACT_P1_NOP 0x00000000 */
+/** Set */
+#define ACT_P1_SET 0x00010000
+/** Activate HOST
+    Sets the activation flag of the HOST domain. This domain contains the HOST interface block. */
+#define ACT_HOST 0x00008000
+/* No-Operation
+#define ACT_HOST_NOP 0x00000000 */
+/** Set */
+#define ACT_HOST_SET 0x00008000
+/** Activate I2C
+    Sets the activation flag of the I2C domain. This domain contains the I2C interface block. */
+#define ACT_I2C 0x00004000
+/* No-Operation
+#define ACT_I2C_NOP 0x00000000 */
+/** Set */
+#define ACT_I2C_SET 0x00004000
+/** Activate SSC0
+    Sets the activation flag of the SSC0 domain. This domain contains the SSC0 interface block. */
+#define ACT_SSC0 0x00002000
+/* No-Operation
+#define ACT_SSC0_NOP 0x00000000 */
+/** Set */
+#define ACT_SSC0_SET 0x00002000
+/** Activate ASC0
+    Sets the activation flag of the ASC0 domain. This domain contains the ASC0 interface block. */
+#define ACT_ASC0 0x00001000
+/* No-Operation
+#define ACT_ASC0_NOP 0x00000000 */
+/** Set */
+#define ACT_ASC0_SET 0x00001000
+/** Activate ASC1
+    Sets the activation flag of the ASC1 domain. This domain contains the ASC1 block. */
+#define ACT_ASC1 0x00000800
+/* No-Operation
+#define ACT_ASC1_NOP 0x00000000 */
+/** Set */
+#define ACT_ASC1_SET 0x00000800
+/** Activate DCDCAPD
+    Sets the activation flag of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
+#define ACT_DCDCAPD 0x00000400
+/* No-Operation
+#define ACT_DCDCAPD_NOP 0x00000000 */
+/** Set */
+#define ACT_DCDCAPD_SET 0x00000400
+/** Activate DCDCDDR
+    Sets the activation flag of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
+#define ACT_DCDCDDR 0x00000200
+/* No-Operation
+#define ACT_DCDCDDR_NOP 0x00000000 */
+/** Set */
+#define ACT_DCDCDDR_SET 0x00000200
+/** Activate DCDC1V0
+    Sets the activation flag of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
+#define ACT_DCDC1V0 0x00000100
+/* No-Operation
+#define ACT_DCDC1V0_NOP 0x00000000 */
+/** Set */
+#define ACT_DCDC1V0_SET 0x00000100
+/** Activate TRC2MEM
+    Sets the activation flag of the TRC2MEM domain. This domain contains the TRC2MEM block. */
+#define ACT_TRC2MEM 0x00000040
+/* No-Operation
+#define ACT_TRC2MEM_NOP 0x00000000 */
+/** Set */
+#define ACT_TRC2MEM_SET 0x00000040
+/** Activate DDR
+    Sets the activation flag of the DDR domain. This domain contains the DDR interface block. */
+#define ACT_DDR 0x00000020
+/* No-Operation
+#define ACT_DDR_NOP 0x00000000 */
+/** Set */
+#define ACT_DDR_SET 0x00000020
+/** Activate EBU
+    Sets the activation flag of the EBU domain. This domain contains the EBU interface block. */
+#define ACT_EBU 0x00000010
+/* No-Operation
+#define ACT_EBU_NOP 0x00000000 */
+/** Set */
+#define ACT_EBU_SET 0x00000010
+
+/* Fields of "Deactivation Register" */
+/** Deactivate STATUS
+    Clears the activation flag of the STATUS domain. This domain contains the STATUS block. */
+#define DEACT_STATUS 0x80000000
+/* No-Operation
+#define DEACT_STATUS_NOP 0x00000000 */
+/** Clear */
+#define DEACT_STATUS_CLR 0x80000000
+/** Deactivate SHA1
+    Clears the activation flag of the SHA1 domain. This domain contains the SHA1 block. */
+#define DEACT_SHA1 0x40000000
+/* No-Operation
+#define DEACT_SHA1_NOP 0x00000000 */
+/** Clear */
+#define DEACT_SHA1_CLR 0x40000000
+/** Deactivate AES
+    Clears the activation flag of the AES domain. This domain contains the AES block. */
+#define DEACT_AES 0x20000000
+/* No-Operation
+#define DEACT_AES_NOP 0x00000000 */
+/** Clear */
+#define DEACT_AES_CLR 0x20000000
+/** Deactivate PCM
+    Clears the activation flag of the PCM domain. This domain contains the PCM interface block. */
+#define DEACT_PCM 0x10000000
+/* No-Operation
+#define DEACT_PCM_NOP 0x00000000 */
+/** Clear */
+#define DEACT_PCM_CLR 0x10000000
+/** Deactivate FSCT
+    Clears the activation flag of the FSCT domain. This domain contains the FSCT block. */
+#define DEACT_FSCT 0x08000000
+/* No-Operation
+#define DEACT_FSCT_NOP 0x00000000 */
+/** Clear */
+#define DEACT_FSCT_CLR 0x08000000
+/** Deactivate GPTC
+    Clears the activation flag of the GPTC domain. This domain contains the GPTC block. */
+#define DEACT_GPTC 0x04000000
+/* No-Operation
+#define DEACT_GPTC_NOP 0x00000000 */
+/** Clear */
+#define DEACT_GPTC_CLR 0x04000000
+/** Deactivate MPS
+    Clears the activation flag of the MPS domain. This domain contains the MPS block. */
+#define DEACT_MPS 0x02000000
+/* No-Operation
+#define DEACT_MPS_NOP 0x00000000 */
+/** Clear */
+#define DEACT_MPS_CLR 0x02000000
+/** Deactivate DFEV0
+    Clears the activation flag of the DFEV0 domain. This domain contains the DFEV0 block. */
+#define DEACT_DFEV0 0x01000000
+/* No-Operation
+#define DEACT_DFEV0_NOP 0x00000000 */
+/** Clear */
+#define DEACT_DFEV0_CLR 0x01000000
+/** Deactivate PADCTRL4
+    Clears the activation flag of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
+#define DEACT_PADCTRL4 0x00400000
+/* No-Operation
+#define DEACT_PADCTRL4_NOP 0x00000000 */
+/** Clear */
+#define DEACT_PADCTRL4_CLR 0x00400000
+/** Deactivate PADCTRL3
+    Clears the activation flag of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
+#define DEACT_PADCTRL3 0x00200000
+/* No-Operation
+#define DEACT_PADCTRL3_NOP 0x00000000 */
+/** Clear */
+#define DEACT_PADCTRL3_CLR 0x00200000
+/** Deactivate PADCTRL1
+    Clears the activation flag of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
+#define DEACT_PADCTRL1 0x00100000
+/* No-Operation
+#define DEACT_PADCTRL1_NOP 0x00000000 */
+/** Clear */
+#define DEACT_PADCTRL1_CLR 0x00100000
+/** Deactivate P4
+    Clears the activation flag of the P4 domain. This domain contains the P4 instance of the GPIO block. */
+#define DEACT_P4 0x00040000
+/* No-Operation
+#define DEACT_P4_NOP 0x00000000 */
+/** Clear */
+#define DEACT_P4_CLR 0x00040000
+/** Deactivate P3
+    Clears the activation flag of the P3 domain. This domain contains the P3 instance of the GPIO block. */
+#define DEACT_P3 0x00020000
+/* No-Operation
+#define DEACT_P3_NOP 0x00000000 */
+/** Clear */
+#define DEACT_P3_CLR 0x00020000
+/** Deactivate P1
+    Clears the activation flag of the P1 domain. This domain contains the P1 instance of the GPIO block. */
+#define DEACT_P1 0x00010000
+/* No-Operation
+#define DEACT_P1_NOP 0x00000000 */
+/** Clear */
+#define DEACT_P1_CLR 0x00010000
+/** Deactivate HOST
+    Clears the activation flag of the HOST domain. This domain contains the HOST interface block. */
+#define DEACT_HOST 0x00008000
+/* No-Operation
+#define DEACT_HOST_NOP 0x00000000 */
+/** Clear */
+#define DEACT_HOST_CLR 0x00008000
+/** Deactivate I2C
+    Clears the activation flag of the I2C domain. This domain contains the I2C interface block. */
+#define DEACT_I2C 0x00004000
+/* No-Operation
+#define DEACT_I2C_NOP 0x00000000 */
+/** Clear */
+#define DEACT_I2C_CLR 0x00004000
+/** Deactivate SSC0
+    Clears the activation flag of the SSC0 domain. This domain contains the SSC0 interface block. */
+#define DEACT_SSC0 0x00002000
+/* No-Operation
+#define DEACT_SSC0_NOP 0x00000000 */
+/** Clear */
+#define DEACT_SSC0_CLR 0x00002000
+/** Deactivate ASC0
+    Clears the activation flag of the ASC0 domain. This domain contains the ASC0 interface block. */
+#define DEACT_ASC0 0x00001000
+/* No-Operation
+#define DEACT_ASC0_NOP 0x00000000 */
+/** Clear */
+#define DEACT_ASC0_CLR 0x00001000
+/** Deactivate ASC1
+    Clears the activation flag of the ASC1 domain. This domain contains the ASC1 block. */
+#define DEACT_ASC1 0x00000800
+/* No-Operation
+#define DEACT_ASC1_NOP 0x00000000 */
+/** Clear */
+#define DEACT_ASC1_CLR 0x00000800
+/** Deactivate DCDCAPD
+    Clears the activation flag of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
+#define DEACT_DCDCAPD 0x00000400
+/* No-Operation
+#define DEACT_DCDCAPD_NOP 0x00000000 */
+/** Clear */
+#define DEACT_DCDCAPD_CLR 0x00000400
+/** Deactivate DCDCDDR
+    Clears the activation flag of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
+#define DEACT_DCDCDDR 0x00000200
+/* No-Operation
+#define DEACT_DCDCDDR_NOP 0x00000000 */
+/** Clear */
+#define DEACT_DCDCDDR_CLR 0x00000200
+/** Deactivate DCDC1V0
+    Clears the activation flag of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
+#define DEACT_DCDC1V0 0x00000100
+/* No-Operation
+#define DEACT_DCDC1V0_NOP 0x00000000 */
+/** Clear */
+#define DEACT_DCDC1V0_CLR 0x00000100
+/** Deactivate TRC2MEM
+    Clears the activation flag of the TRC2MEM domain. This domain contains the TRC2MEM block. */
+#define DEACT_TRC2MEM 0x00000040
+/* No-Operation
+#define DEACT_TRC2MEM_NOP 0x00000000 */
+/** Clear */
+#define DEACT_TRC2MEM_CLR 0x00000040
+/** Deactivate DDR
+    Clears the activation flag of the DDR domain. This domain contains the DDR interface block. */
+#define DEACT_DDR 0x00000020
+/* No-Operation
+#define DEACT_DDR_NOP 0x00000000 */
+/** Clear */
+#define DEACT_DDR_CLR 0x00000020
+/** Deactivate EBU
+    Clears the activation flag of the EBU domain. This domain contains the EBU interface block. */
+#define DEACT_EBU 0x00000010
+/* No-Operation
+#define DEACT_EBU_NOP 0x00000000 */
+/** Clear */
+#define DEACT_EBU_CLR 0x00000010
+
+/* Fields of "Reboot Trigger Register" */
+/** Reboot STATUS
+    Triggers a reboot of the STATUS domain. This domain contains the STATUS block. */
+#define RBT_STATUS 0x80000000
+/* No-Operation
+#define RBT_STATUS_NOP 0x00000000 */
+/** Trigger */
+#define RBT_STATUS_TRIG 0x80000000
+/** Reboot SHA1
+    Triggers a reboot of the SHA1 domain. This domain contains the SHA1 block. */
+#define RBT_SHA1 0x40000000
+/* No-Operation
+#define RBT_SHA1_NOP 0x00000000 */
+/** Trigger */
+#define RBT_SHA1_TRIG 0x40000000
+/** Reboot AES
+    Triggers a reboot of the AES domain. This domain contains the AES block. */
+#define RBT_AES 0x20000000
+/* No-Operation
+#define RBT_AES_NOP 0x00000000 */
+/** Trigger */
+#define RBT_AES_TRIG 0x20000000
+/** Reboot PCM
+    Triggers a reboot of the PCM domain. This domain contains the PCM interface block. */
+#define RBT_PCM 0x10000000
+/* No-Operation
+#define RBT_PCM_NOP 0x00000000 */
+/** Trigger */
+#define RBT_PCM_TRIG 0x10000000
+/** Reboot FSCT
+    Triggers a reboot of the FSCT domain. This domain contains the FSCT block. */
+#define RBT_FSCT 0x08000000
+/* No-Operation
+#define RBT_FSCT_NOP 0x00000000 */
+/** Trigger */
+#define RBT_FSCT_TRIG 0x08000000
+/** Reboot GPTC
+    Triggers a reboot of the GPTC domain. This domain contains the GPTC block. */
+#define RBT_GPTC 0x04000000
+/* No-Operation
+#define RBT_GPTC_NOP 0x00000000 */
+/** Trigger */
+#define RBT_GPTC_TRIG 0x04000000
+/** Reboot MPS
+    Triggers a reboot of the MPS domain. This domain contains the MPS block. */
+#define RBT_MPS 0x02000000
+/* No-Operation
+#define RBT_MPS_NOP 0x00000000 */
+/** Trigger */
+#define RBT_MPS_TRIG 0x02000000
+/** Reboot DFEV0
+    Triggers a reboot of the DFEV0 domain. This domain contains the DFEV0 block. */
+#define RBT_DFEV0 0x01000000
+/* No-Operation
+#define RBT_DFEV0_NOP 0x00000000 */
+/** Trigger */
+#define RBT_DFEV0_TRIG 0x01000000
+/** Reboot PADCTRL4
+    Triggers a reboot of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
+#define RBT_PADCTRL4 0x00400000
+/* No-Operation
+#define RBT_PADCTRL4_NOP 0x00000000 */
+/** Trigger */
+#define RBT_PADCTRL4_TRIG 0x00400000
+/** Reboot PADCTRL3
+    Triggers a reboot of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
+#define RBT_PADCTRL3 0x00200000
+/* No-Operation
+#define RBT_PADCTRL3_NOP 0x00000000 */
+/** Trigger */
+#define RBT_PADCTRL3_TRIG 0x00200000
+/** Reboot PADCTRL1
+    Triggers a reboot of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
+#define RBT_PADCTRL1 0x00100000
+/* No-Operation
+#define RBT_PADCTRL1_NOP 0x00000000 */
+/** Trigger */
+#define RBT_PADCTRL1_TRIG 0x00100000
+/** Reboot P4
+    Triggers a reboot of the P4 domain. This domain contains the P4 instance of the GPIO block. */
+#define RBT_P4 0x00040000
+/* No-Operation
+#define RBT_P4_NOP 0x00000000 */
+/** Trigger */
+#define RBT_P4_TRIG 0x00040000
+/** Reboot P3
+    Triggers a reboot of the P3 domain. This domain contains the P3 instance of the GPIO block. */
+#define RBT_P3 0x00020000
+/* No-Operation
+#define RBT_P3_NOP 0x00000000 */
+/** Trigger */
+#define RBT_P3_TRIG 0x00020000
+/** Reboot P1
+    Triggers a reboot of the P1 domain. This domain contains the P1 instance of the GPIO block. */
+#define RBT_P1 0x00010000
+/* No-Operation
+#define RBT_P1_NOP 0x00000000 */
+/** Trigger */
+#define RBT_P1_TRIG 0x00010000
+/** Reboot HOST
+    Triggers a reboot of the HOST domain. This domain contains the HOST interface block. */
+#define RBT_HOST 0x00008000
+/* No-Operation
+#define RBT_HOST_NOP 0x00000000 */
+/** Trigger */
+#define RBT_HOST_TRIG 0x00008000
+/** Reboot I2C
+    Triggers a reboot of the I2C domain. This domain contains the I2C interface block. */
+#define RBT_I2C 0x00004000
+/* No-Operation
+#define RBT_I2C_NOP 0x00000000 */
+/** Trigger */
+#define RBT_I2C_TRIG 0x00004000
+/** Reboot SSC0
+    Triggers a reboot of the SSC0 domain. This domain contains the SSC0 interface block. */
+#define RBT_SSC0 0x00002000
+/* No-Operation
+#define RBT_SSC0_NOP 0x00000000 */
+/** Trigger */
+#define RBT_SSC0_TRIG 0x00002000
+/** Reboot ASC0
+    Triggers a reboot of the ASC0 domain. This domain contains the ASC0 interface block. */
+#define RBT_ASC0 0x00001000
+/* No-Operation
+#define RBT_ASC0_NOP 0x00000000 */
+/** Trigger */
+#define RBT_ASC0_TRIG 0x00001000
+/** Reboot ASC1
+    Triggers a reboot of the ASC1 domain. This domain contains the ASC1 block. */
+#define RBT_ASC1 0x00000800
+/* No-Operation
+#define RBT_ASC1_NOP 0x00000000 */
+/** Trigger */
+#define RBT_ASC1_TRIG 0x00000800
+/** Reboot DCDCAPD
+    Triggers a reboot of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
+#define RBT_DCDCAPD 0x00000400
+/* No-Operation
+#define RBT_DCDCAPD_NOP 0x00000000 */
+/** Trigger */
+#define RBT_DCDCAPD_TRIG 0x00000400
+/** Reboot DCDCDDR
+    Triggers a reboot of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
+#define RBT_DCDCDDR 0x00000200
+/* No-Operation
+#define RBT_DCDCDDR_NOP 0x00000000 */
+/** Trigger */
+#define RBT_DCDCDDR_TRIG 0x00000200
+/** Reboot DCDC1V0
+    Triggers a reboot of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
+#define RBT_DCDC1V0 0x00000100
+/* No-Operation
+#define RBT_DCDC1V0_NOP 0x00000000 */
+/** Trigger */
+#define RBT_DCDC1V0_TRIG 0x00000100
+/** Reboot TRC2MEM
+    Triggers a reboot of the TRC2MEM domain. This domain contains the TRC2MEM block. */
+#define RBT_TRC2MEM 0x00000040
+/* No-Operation
+#define RBT_TRC2MEM_NOP 0x00000000 */
+/** Trigger */
+#define RBT_TRC2MEM_TRIG 0x00000040
+/** Reboot DDR
+    Triggers a reboot of the DDR domain. This domain contains the DDR interface block. */
+#define RBT_DDR 0x00000020
+/* No-Operation
+#define RBT_DDR_NOP 0x00000000 */
+/** Trigger */
+#define RBT_DDR_TRIG 0x00000020
+/** Reboot EBU
+    Triggers a reboot of the EBU domain. This domain contains the EBU interface block. */
+#define RBT_EBU 0x00000010
+/* No-Operation
+#define RBT_EBU_NOP 0x00000000 */
+/** Trigger */
+#define RBT_EBU_TRIG 0x00000010
+/** Reboot XBAR
+    Triggers a reboot of the XBAR. */
+#define RBT_XBAR 0x00000002
+/* No-Operation
+#define RBT_XBAR_NOP 0x00000000 */
+/** Trigger */
+#define RBT_XBAR_TRIG 0x00000002
+/** Reboot CPU
+    Triggers a reboot of the CPU. */
+#define RBT_CPU 0x00000001
+/* No-Operation
+#define RBT_CPU_NOP 0x00000000 */
+/** Trigger */
+#define RBT_CPU_TRIG 0x00000001
+
+/* Fields of "CPU0 Clock Control Register" */
+/** CPU Clock Divider
+    Via this bit the divider and therefore the frequency of the clock of CPU0 can be selected. */
+#define CPU0CC_CPUDIV 0x00000001
+/* Frequency set to the nominal value.
+#define CPU0CC_CPUDIV_SELFNOM 0x00000000 */
+/** Frequency set to half of its nominal value. */
+#define CPU0CC_CPUDIV_SELFHALF 0x00000001
+
+/* Fields of "CPU0 Reset Source Register" */
+/** Software Reboot Request Occurred
+    This bit can be acknowledged by a write operation. */
+#define CPU0RS_SWRRO 0x00000004
+/* Nothing
+#define CPU0RS_SWRRO_NULL 0x00000000 */
+/** Write: Acknowledge the event. */
+#define CPU0RS_SWRRO_EVACK 0x00000004
+/** Read: Event occurred. */
+#define CPU0RS_SWRRO_EVOCC 0x00000004
+/** Hardware Reset Source
+    Reflects the root cause for the last hardware reset. The infrastructure-block is only reset in case of POR. For all other blocks there is no difference between the three HW-reset sources. */
+#define CPU0RS_HWRS_MASK 0x00000003
+/** field offset */
+#define CPU0RS_HWRS_OFFSET 0
+/** Power-on reset. */
+#define CPU0RS_HWRS_POR 0x00000000
+/** RST pin. */
+#define CPU0RS_HWRS_RST 0x00000001
+/** Watchdog reset request. */
+#define CPU0RS_HWRS_WDT 0x00000002
+
+/* Fields of "CPU0 Wakeup Configuration Register" */
+/** Wakeup Request Source Yield Resume 15
+    Select the signal connected to the yield/resume interface pin 15 as source for wakeup from sleep state. */
+#define CPU0WCFG_WRSYR15 0x80000000
+/* Not selected
+#define CPU0WCFG_WRSYR15_NSEL 0x00000000 */
+/** Selected */
+#define CPU0WCFG_WRSYR15_SEL 0x80000000
+/** Wakeup Request Source Yield Resume 14
+    Select the signal connected to the yield/resume interface pin 14 as source for wakeup from sleep state. */
+#define CPU0WCFG_WRSYR14 0x40000000
+/* Not selected
+#define CPU0WCFG_WRSYR14_NSEL 0x00000000 */
+/** Selected */
+#define CPU0WCFG_WRSYR14_SEL 0x40000000
+/** Wakeup Request Source Yield Resume 13
+    Select the signal connected to the yield/resume interface pin 13 as source for wakeup from sleep state. */
+#define CPU0WCFG_WRSYR13 0x20000000
+/* Not selected
+#define CPU0WCFG_WRSYR13_NSEL 0x00000000 */
+/** Selected */
+#define CPU0WCFG_WRSYR13_SEL 0x20000000
+/** Wakeup Request Source Yield Resume 12
+    Select the signal connected to the yield/resume interface pin 12 as source for wakeup from sleep state. */
+#define CPU0WCFG_WRSYR12 0x10000000
+/* Not selected
+#define CPU0WCFG_WRSYR12_NSEL 0x00000000 */
+/** Selected */
+#define CPU0WCFG_WRSYR12_SEL 0x10000000
+/** Wakeup Request Source Yield Resume 11
+    Select the signal connected to the yield/resume interface pin 11 as source for wakeup from sleep state. */
+#define CPU0WCFG_WRSYR11 0x08000000
+/* Not selected
+#define CPU0WCFG_WRSYR11_NSEL 0x00000000 */
+/** Selected */
+#define CPU0WCFG_WRSYR11_SEL 0x08000000
+/** Wakeup Request Source Yield Resume 10
+    Select the signal connected to the yield/resume interface pin 10 as source for wakeup from sleep state. */
+#define CPU0WCFG_WRSYR10 0x04000000
+/* Not selected
+#define CPU0WCFG_WRSYR10_NSEL 0x00000000 */
+/** Selected */
+#define CPU0WCFG_WRSYR10_SEL 0x04000000
+/** Wakeup Request Source Yield Resume 9
+    Select the signal connected to the yield/resume interface pin 9 as source for wakeup from sleep state. */
+#define CPU0WCFG_WRSYR9 0x02000000
+/* Not selected
+#define CPU0WCFG_WRSYR9_NSEL 0x00000000 */
+/** Selected */
+#define CPU0WCFG_WRSYR9_SEL 0x02000000
+/** Wakeup Request Source Yield Resume 8
+    Select the signal connected to the yield/resume interface pin 8 as source for wakeup from sleep state. */
+#define CPU0WCFG_WRSYR8 0x01000000
+/* Not selected
+#define CPU0WCFG_WRSYR8_NSEL 0x00000000 */
+/** Selected */
+#define CPU0WCFG_WRSYR8_SEL 0x01000000
+/** Wakeup Request Source Yield Resume 7
+    Select the signal connected to the yield/resume interface pin 7 as source for wakeup from sleep state. */
+#define CPU0WCFG_WRSYR7 0x00800000
+/* Not selected
+#define CPU0WCFG_WRSYR7_NSEL 0x00000000 */
+/** Selected */
+#define CPU0WCFG_WRSYR7_SEL 0x00800000
+/** Wakeup Request Source Yield Resume 6
+    Select the signal connected to the yield/resume interface pin 6 as source for wakeup from sleep state. */
+#define CPU0WCFG_WRSYR6 0x00400000
+/* Not selected
+#define CPU0WCFG_WRSYR6_NSEL 0x00000000 */
+/** Selected */
+#define CPU0WCFG_WRSYR6_SEL 0x00400000
+/** Wakeup Request Source Yield Resume 5
+    Select the signal connected to the yield/resume interface pin 5 as source for wakeup from sleep state. */
+#define CPU0WCFG_WRSYR5 0x00200000
+/* Not selected
+#define CPU0WCFG_WRSYR5_NSEL 0x00000000 */
+/** Selected */
+#define CPU0WCFG_WRSYR5_SEL 0x00200000
+/** Wakeup Request Source Yield Resume 4
+    Select the signal connected to the yield/resume interface pin 4 as source for wakeup from sleep state. */
+#define CPU0WCFG_WRSYR4 0x00100000
+/* Not selected
+#define CPU0WCFG_WRSYR4_NSEL 0x00000000 */
+/** Selected */
+#define CPU0WCFG_WRSYR4_SEL 0x00100000
+/** Wakeup Request Source Yield Resume 3
+    Select the signal connected to the yield/resume interface pin 3 as source for wakeup from sleep state. */
+#define CPU0WCFG_WRSYR3 0x00080000
+/* Not selected
+#define CPU0WCFG_WRSYR3_NSEL 0x00000000 */
+/** Selected */
+#define CPU0WCFG_WRSYR3_SEL 0x00080000
+/** Wakeup Request Source Yield Resume 2
+    Select the signal connected to the yield/resume interface pin 2 as source for wakeup from sleep state. */
+#define CPU0WCFG_WRSYR2 0x00040000
+/* Not selected
+#define CPU0WCFG_WRSYR2_NSEL 0x00000000 */
+/** Selected */
+#define CPU0WCFG_WRSYR2_SEL 0x00040000
+/** Wakeup Request Source Yield Resume 1
+    Select the signal connected to the yield/resume interface pin 1 as source for wakeup from sleep state. */
+#define CPU0WCFG_WRSYR1 0x00020000
+/* Not selected
+#define CPU0WCFG_WRSYR1_NSEL 0x00000000 */
+/** Selected */
+#define CPU0WCFG_WRSYR1_SEL 0x00020000
+/** Wakeup Request Source Yield Resume 0
+    Select the signal connected to the yield/resume interface pin 0 as source for wakeup from sleep state. */
+#define CPU0WCFG_WRSYR0 0x00010000
+/* Not selected
+#define CPU0WCFG_WRSYR0_NSEL 0x00000000 */
+/** Selected */
+#define CPU0WCFG_WRSYR0_SEL 0x00010000
+/** Wakeup Request Source Debug
+    Select signal EJ_DINT as source for wakeup from sleep state. */
+#define CPU0WCFG_WRSDBG 0x00000100
+/* Not selected
+#define CPU0WCFG_WRSDBG_NSEL 0x00000000 */
+/** Selected */
+#define CPU0WCFG_WRSDBG_SEL 0x00000100
+/** Wakeup Request Source ICU of VPE1
+    Select signal ICU_IRQ of VPE1 as source for wakeup from sleep state. */
+#define CPU0WCFG_WRSICUVPE1 0x00000002
+/* Not selected
+#define CPU0WCFG_WRSICUVPE1_NSEL 0x00000000 */
+/** Selected */
+#define CPU0WCFG_WRSICUVPE1_SEL 0x00000002
+/** Wakeup Request Source ICU of VPE0
+    Select signal ICU_IRQ of VPE0 as source for wakeup from sleep state. */
+#define CPU0WCFG_WRSICUVPE0 0x00000001
+/* Not selected
+#define CPU0WCFG_WRSICUVPE0_NSEL 0x00000000 */
+/** Selected */
+#define CPU0WCFG_WRSICUVPE0_SEL 0x00000001
+
+/* Fields of "Bootmode Control Register" */
+/** Software Bootmode Select
+    Enables SW writing of Bootmode and shows whether or not the SW-programmed bootmode is reflected in field Bootmode instead of the hardware given value. */
+#define BMC_BMSW 0x80000000
+/* Disable
+#define BMC_BMSW_DIS 0x00000000 */
+/** Enable */
+#define BMC_BMSW_EN 0x80000000
+/** Bootmode
+    Initially this field holds the value of the pinstraps LED_BMODEx on positions 5:0, and the value of the corresponding JTAG register bit on position 6. Writing is enabled by setting Software Bootmode Select to 1 during the write cycle. */
+#define BMC_BM_MASK 0x0000007F
+/** field offset */
+#define BMC_BM_OFFSET 0
+
+/* Fields of "Sleep Configuration Register" */
+/** Enable XBAR Clockoff When All XBAR masters Clockoff
+    Enable XBAR clock shutdown in case all XBAR masters are in clockoff mode. This bit has no effect if bit CPU0 is not enabled. */
+#define SCFG_XBAR 0x00010000
+/* Disable
+#define SCFG_XBAR_DIS 0x00000000 */
+/** Enable */
+#define SCFG_XBAR_EN 0x00010000
+/** CPU0 Clockoff On Sleep
+    Enable CPU0 clock shutdown in case its SI_SLEEP signal becomes active. */
+#define SCFG_CPU0 0x00000001
+/* Disable
+#define SCFG_CPU0_DIS 0x00000000 */
+/** Enable */
+#define SCFG_CPU0_EN 0x00000001
+
+/* Fields of "Power Down Configuration Register" */
+/** Enable Power Down STATUS
+    Ignore this bit as power-gating is not supported for this chip. */
+#define PDCFG_STATUS 0x80000000
+/* Disable
+#define PDCFG_STATUS_DIS 0x00000000 */
+/** Enable */
+#define PDCFG_STATUS_EN 0x80000000
+/** Enable Power Down SHA1
+    Ignore this bit as power-gating is not supported for this chip. */
+#define PDCFG_SHA1 0x40000000
+/* Disable
+#define PDCFG_SHA1_DIS 0x00000000 */
+/** Enable */
+#define PDCFG_SHA1_EN 0x40000000
+/** Enable Power Down AES
+    Ignore this bit as power-gating is not supported for this chip. */
+#define PDCFG_AES 0x20000000
+/* Disable
+#define PDCFG_AES_DIS 0x00000000 */
+/** Enable */
+#define PDCFG_AES_EN 0x20000000
+/** Enable Power Down PCM
+    Ignore this bit as power-gating is not supported for this chip. */
+#define PDCFG_PCM 0x10000000
+/* Disable
+#define PDCFG_PCM_DIS 0x00000000 */
+/** Enable */
+#define PDCFG_PCM_EN 0x10000000
+/** Enable Power Down FSCT
+    Ignore this bit as power-gating is not supported for this chip. */
+#define PDCFG_FSCT 0x08000000
+/* Disable
+#define PDCFG_FSCT_DIS 0x00000000 */
+/** Enable */
+#define PDCFG_FSCT_EN 0x08000000
+/** Enable Power Down GPTC
+    Ignore this bit as power-gating is not supported for this chip. */
+#define PDCFG_GPTC 0x04000000
+/* Disable
+#define PDCFG_GPTC_DIS 0x00000000 */
+/** Enable */
+#define PDCFG_GPTC_EN 0x04000000
+/** Enable Power Down MPS
+    Ignore this bit as power-gating is not supported for this chip. */
+#define PDCFG_MPS 0x02000000
+/* Disable
+#define PDCFG_MPS_DIS 0x00000000 */
+/** Enable */
+#define PDCFG_MPS_EN 0x02000000
+/** Enable Power Down DFEV0
+    Ignore this bit as power-gating is not supported for this chip. */
+#define PDCFG_DFEV0 0x01000000
+/* Disable
+#define PDCFG_DFEV0_DIS 0x00000000 */
+/** Enable */
+#define PDCFG_DFEV0_EN 0x01000000
+/** Enable Power Down PADCTRL4
+    Ignore this bit as power-gating is not supported for this chip. */
+#define PDCFG_PADCTRL4 0x00400000
+/* Disable
+#define PDCFG_PADCTRL4_DIS 0x00000000 */
+/** Enable */
+#define PDCFG_PADCTRL4_EN 0x00400000
+/** Enable Power Down PADCTRL3
+    Ignore this bit as power-gating is not supported for this chip. */
+#define PDCFG_PADCTRL3 0x00200000
+/* Disable
+#define PDCFG_PADCTRL3_DIS 0x00000000 */
+/** Enable */
+#define PDCFG_PADCTRL3_EN 0x00200000
+/** Enable Power Down PADCTRL1
+    Ignore this bit as power-gating is not supported for this chip. */
+#define PDCFG_PADCTRL1 0x00100000
+/* Disable
+#define PDCFG_PADCTRL1_DIS 0x00000000 */
+/** Enable */
+#define PDCFG_PADCTRL1_EN 0x00100000
+/** Enable Power Down P4
+    Ignore this bit as power-gating is not supported for this chip. */
+#define PDCFG_P4 0x00040000
+/* Disable
+#define PDCFG_P4_DIS 0x00000000 */
+/** Enable */
+#define PDCFG_P4_EN 0x00040000
+/** Enable Power Down P3
+    Ignore this bit as power-gating is not supported for this chip. */
+#define PDCFG_P3 0x00020000
+/* Disable
+#define PDCFG_P3_DIS 0x00000000 */
+/** Enable */
+#define PDCFG_P3_EN 0x00020000
+/** Enable Power Down P1
+    Ignore this bit as power-gating is not supported for this chip. */
+#define PDCFG_P1 0x00010000
+/* Disable
+#define PDCFG_P1_DIS 0x00000000 */
+/** Enable */
+#define PDCFG_P1_EN 0x00010000
+/** Enable Power Down HOST
+    Ignore this bit as power-gating is not supported for this chip. */
+#define PDCFG_HOST 0x00008000
+/* Disable
+#define PDCFG_HOST_DIS 0x00000000 */
+/** Enable */
+#define PDCFG_HOST_EN 0x00008000
+/** Enable Power Down I2C
+    Ignore this bit as power-gating is not supported for this chip. */
+#define PDCFG_I2C 0x00004000
+/* Disable
+#define PDCFG_I2C_DIS 0x00000000 */
+/** Enable */
+#define PDCFG_I2C_EN 0x00004000
+/** Enable Power Down SSC0
+    Ignore this bit as power-gating is not supported for this chip. */
+#define PDCFG_SSC0 0x00002000
+/* Disable
+#define PDCFG_SSC0_DIS 0x00000000 */
+/** Enable */
+#define PDCFG_SSC0_EN 0x00002000
+/** Enable Power Down ASC0
+    Ignore this bit as power-gating is not supported for this chip. */
+#define PDCFG_ASC0 0x00001000
+/* Disable
+#define PDCFG_ASC0_DIS 0x00000000 */
+/** Enable */
+#define PDCFG_ASC0_EN 0x00001000
+/** Enable Power Down ASC1
+    Ignore this bit as power-gating is not supported for this chip. */
+#define PDCFG_ASC1 0x00000800
+/* Disable
+#define PDCFG_ASC1_DIS 0x00000000 */
+/** Enable */
+#define PDCFG_ASC1_EN 0x00000800
+/** Enable Power Down DCDCAPD
+    Ignore this bit as power-gating is not supported for this chip. */
+#define PDCFG_DCDCAPD 0x00000400
+/* Disable
+#define PDCFG_DCDCAPD_DIS 0x00000000 */
+/** Enable */
+#define PDCFG_DCDCAPD_EN 0x00000400
+/** Enable Power Down DCDCDDR
+    Ignore this bit as power-gating is not supported for this chip. */
+#define PDCFG_DCDCDDR 0x00000200
+/* Disable
+#define PDCFG_DCDCDDR_DIS 0x00000000 */
+/** Enable */
+#define PDCFG_DCDCDDR_EN 0x00000200
+/** Enable Power Down DCDC1V0
+    Ignore this bit as power-gating is not supported for this chip. */
+#define PDCFG_DCDC1V0 0x00000100
+/* Disable
+#define PDCFG_DCDC1V0_DIS 0x00000000 */
+/** Enable */
+#define PDCFG_DCDC1V0_EN 0x00000100
+/** Enable Power Down TRC2MEM
+    Ignore this bit as power-gating is not supported for this chip. */
+#define PDCFG_TRC2MEM 0x00000040
+/* Disable
+#define PDCFG_TRC2MEM_DIS 0x00000000 */
+/** Enable */
+#define PDCFG_TRC2MEM_EN 0x00000040
+/** Enable Power Down DDR
+    Ignore this bit as power-gating is not supported for this chip. */
+#define PDCFG_DDR 0x00000020
+/* Disable
+#define PDCFG_DDR_DIS 0x00000000 */
+/** Enable */
+#define PDCFG_DDR_EN 0x00000020
+/** Enable Power Down EBU
+    Ignore this bit as power-gating is not supported for this chip. */
+#define PDCFG_EBU 0x00000010
+/* Disable
+#define PDCFG_EBU_DIS 0x00000000 */
+/** Enable */
+#define PDCFG_EBU_EN 0x00000010
+
+/* Fields of "CLKO Pad Control Register" */
+/** Ethernet Reference Clock CLKO Select
+    Selects the CLKO pad's input as source for the GPHY, SGMII PLLs. */
+#define CLKOC_ETHREF 0x00000002
+/* Not selected
+#define CLKOC_ETHREF_NSEL 0x00000000 */
+/** Selected */
+#define CLKOC_ETHREF_SEL 0x00000002
+/** Output Enable
+    Enables the output driver of the CLKO pad. */
+#define CLKOC_OEN 0x00000001
+/* Disable
+#define CLKOC_OEN_DIS 0x00000000 */
+/** Enable */
+#define CLKOC_OEN_EN 0x00000001
+
+/* Fields of "Infrastructure Control Register" */
+/** General Purpose Control
+    Backup bits. Currently they are connected as: bit 0 : connected to the configmode_on pin of the pinstrapping block. bit 1 : clock enable of the GPE primary clock. bits 3:2 : frequency select of the GPE primary clock. 00 = 769.2MHz, 01 = 625MHz, 10 = 555.6MHz, 11 = 500MHz All other bits are unconnected. */
+#define INFRAC_GP_MASK 0x1F000000
+/** field offset */
+#define INFRAC_GP_OFFSET 24
+/** CMOS2CML Ethernet Control
+    CMOS2CML Ethernet Control. */
+#define INFRAC_CMOS2CML_GPON_MASK 0x0000F000
+/** field offset */
+#define INFRAC_CMOS2CML_GPON_OFFSET 12
+/** CMOS2CML Ethernet Control
+    CMOS2CML Ethernet Control. */
+#define INFRAC_CMOS2CML_ETH_MASK 0x00000F00
+/** field offset */
+#define INFRAC_CMOS2CML_ETH_OFFSET 8
+/** Dying Gasp Enable
+    Enables the dying gasp detector. */
+#define INFRAC_DGASPEN 0x00000040
+/* Disable
+#define INFRAC_DGASPEN_DIS 0x00000000 */
+/** Enable */
+#define INFRAC_DGASPEN_EN 0x00000040
+/** Dying Gasp Hysteresis Control
+    Dying Gasp Hysteresis Control. */
+#define INFRAC_DGASPHYS_MASK 0x00000030
+/** field offset */
+#define INFRAC_DGASPHYS_OFFSET 4
+/** Linear Regulator 1.5V Enable
+    Enables 1.5V linear regulator. */
+#define INFRAC_LIN1V5EN 0x00000008
+/* Disable
+#define INFRAC_LIN1V5EN_DIS 0x00000000 */
+/** Enable */
+#define INFRAC_LIN1V5EN_EN 0x00000008
+/** Linear Regulator 1.5V Control
+    Linear regulator 1.5V control. */
+#define INFRAC_LIN1V5C_MASK 0x00000007
+/** field offset */
+#define INFRAC_LIN1V5C_OFFSET 0
+
+/* Fields of "HRST_OUT_N Control Register" */
+/** HRST_OUT_N Pin Value
+    Controls the value of the HRST_OUT_N pin. */
+#define HRSTOUTC_VALUE 0x00000001
+
+/* Fields of "EBU Clock Control Register" */
+/** EBU Clock Divider
+    Via this bit the frequency of the clock of the EBU can be selected. */
+#define EBUCC_EBUDIV 0x00000001
+/* Frequency set to 50MHz.
+#define EBUCC_EBUDIV_SELF50 0x00000000 */
+/** Frequency set to 100MHz. */
+#define EBUCC_EBUDIV_SELF100 0x00000001
+
+/* Fields of "NMI Status Register" */
+/** NMI Status Flag TEST
+    Shows whether the event NMI TEST occurred. */
+#define NMIS_TEST 0x00000100
+/* Nothing
+#define NMIS_TEST_NULL 0x00000000 */
+/** Read: Event occurred. */
+#define NMIS_TEST_EVOCC 0x00000100
+/** NMI Status Flag DGASP
+    Shows whether the event NMI DGASP occurred. */
+#define NMIS_DGASP 0x00000004
+/* Nothing
+#define NMIS_DGASP_NULL 0x00000000 */
+/** Read: Event occurred. */
+#define NMIS_DGASP_EVOCC 0x00000004
+/** NMI Status Flag HOST
+    Shows whether the event NMI HOST occurred. */
+#define NMIS_HOST 0x00000002
+/* Nothing
+#define NMIS_HOST_NULL 0x00000000 */
+/** Read: Event occurred. */
+#define NMIS_HOST_EVOCC 0x00000002
+/** NMI Status Flag PIN
+    Shows whether the event NMI PIN occurred. */
+#define NMIS_PIN 0x00000001
+/* Nothing
+#define NMIS_PIN_NULL 0x00000000 */
+/** Read: Event occurred. */
+#define NMIS_PIN_EVOCC 0x00000001
+
+/* Fields of "NMI Set Register" */
+/** Set NMI Status Flag TEST
+    Sets the corresponding NMI status flag. */
+#define NMISET_TEST 0x00000100
+/* Nothing
+#define NMISET_TEST_NULL 0x00000000 */
+/** Set */
+#define NMISET_TEST_SET 0x00000100
+/** Set NMI Status Flag DGASP
+    Sets the corresponding NMI status flag. */
+#define NMISET_DGASP 0x00000004
+/* Nothing
+#define NMISET_DGASP_NULL 0x00000000 */
+/** Set */
+#define NMISET_DGASP_SET 0x00000004
+/** Set NMI Status Flag HOST
+    Sets the corresponding NMI status flag. */
+#define NMISET_HOST 0x00000002
+/* Nothing
+#define NMISET_HOST_NULL 0x00000000 */
+/** Set */
+#define NMISET_HOST_SET 0x00000002
+/** Set NMI Status Flag PIN
+    Sets the corresponding NMI status flag. */
+#define NMISET_PIN 0x00000001
+/* Nothing
+#define NMISET_PIN_NULL 0x00000000 */
+/** Set */
+#define NMISET_PIN_SET 0x00000001
+
+/* Fields of "NMI Clear Register" */
+/** Clear NMI Status Flag TEST
+    Clears the corresponding NMI status flag. */
+#define NMICLR_TEST 0x00000100
+/* Nothing
+#define NMICLR_TEST_NULL 0x00000000 */
+/** Clear */
+#define NMICLR_TEST_CLR 0x00000100
+/** Clear NMI Status Flag DGASP
+    Clears the corresponding NMI status flag. */
+#define NMICLR_DGASP 0x00000004
+/* Nothing
+#define NMICLR_DGASP_NULL 0x00000000 */
+/** Clear */
+#define NMICLR_DGASP_CLR 0x00000004
+/** Clear NMI Status Flag HOST
+    Clears the corresponding NMI status flag. */
+#define NMICLR_HOST 0x00000002
+/* Nothing
+#define NMICLR_HOST_NULL 0x00000000 */
+/** Clear */
+#define NMICLR_HOST_CLR 0x00000002
+/** Clear NMI Status Flag PIN
+    Clears the corresponding NMI status flag. */
+#define NMICLR_PIN 0x00000001
+/* Nothing
+#define NMICLR_PIN_NULL 0x00000000 */
+/** Clear */
+#define NMICLR_PIN_CLR 0x00000001
+
+/* Fields of "NMI Test Configuration Register" */
+/** Enable NMI Test Feature
+    Enables the operation of the NMI TEST flag. This is the mask for the Non-Maskable-Interrupt dedicated to SW tests. All others cannot be masked. */
+#define NMITCFG_TEN 0x00000100
+/* Disable
+#define NMITCFG_TEN_DIS 0x00000000 */
+/** Enable */
+#define NMITCFG_TEN_EN 0x00000100
+
+/* Fields of "NMI VPE1 Control Register" */
+/** NMI VPE1 State
+    Reflects the state of the NMI signal towards VPE1. This bit is controlled by software only, there is no hardware NMI source dedicated to VPE1. So VPE0 could trigger an NMI at VPE1 using this bit in its own NMI-routine. */
+#define NMIVPE1C_NMI 0x00000001
+/* False
+#define NMIVPE1C_NMI_FALSE 0x00000000 */
+/** True */
+#define NMIVPE1C_NMI_TRUE 0x00000001
+
+/* Fields of "IRN Capture Register" */
+/** DCDCAPD Alarm
+    The DCDC Converter for the APD Supply submitted an alarm. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define IRNCR_DCDCAPD 0x00400000
+/* Nothing
+#define IRNCR_DCDCAPD_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define IRNCR_DCDCAPD_INTACK 0x00400000
+/** Read: Interrupt occurred. */
+#define IRNCR_DCDCAPD_INTOCC 0x00400000
+/** DCDCDDR Alarm
+    The DCDC Converter for the DDR Supply submitted an alarm. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define IRNCR_DCDCDDR 0x00200000
+/* Nothing
+#define IRNCR_DCDCDDR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define IRNCR_DCDCDDR_INTACK 0x00200000
+/** Read: Interrupt occurred. */
+#define IRNCR_DCDCDDR_INTOCC 0x00200000
+/** DCDC1V0 Alarm
+    The DCDC Converter for the 1.0 Volts submitted an alarm. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define IRNCR_DCDC1V0 0x00100000
+/* Nothing
+#define IRNCR_DCDC1V0_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define IRNCR_DCDC1V0_INTACK 0x00100000
+/** Read: Interrupt occurred. */
+#define IRNCR_DCDC1V0_INTOCC 0x00100000
+/** SIF0 wakeup request
+    SmartSlic Interface 0 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define IRNCR_SIF0 0x00010000
+/* Nothing
+#define IRNCR_SIF0_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define IRNCR_SIF0_INTACK 0x00010000
+/** Read: Interrupt occurred. */
+#define IRNCR_SIF0_INTOCC 0x00010000
+
+/* Fields of "IRN Interrupt Control Register" */
+/** DCDCAPD Alarm
+    Interrupt control bit for the corresponding bit in the IRNCR register. */
+#define IRNICR_DCDCAPD 0x00400000
+/** DCDCDDR Alarm
+    Interrupt control bit for the corresponding bit in the IRNCR register. */
+#define IRNICR_DCDCDDR 0x00200000
+/** DCDC1V0 Alarm
+    Interrupt control bit for the corresponding bit in the IRNCR register. */
+#define IRNICR_DCDC1V0 0x00100000
+/** SIF0 wakeup request
+    Interrupt control bit for the corresponding bit in the IRNCR register. */
+#define IRNICR_SIF0 0x00010000
+
+/* Fields of "IRN Interrupt Enable Register" */
+/** DCDCAPD Alarm
+    Interrupt enable bit for the corresponding bit in the IRNCR register. */
+#define IRNEN_DCDCAPD 0x00400000
+/* Disable
+#define IRNEN_DCDCAPD_DIS 0x00000000 */
+/** Enable */
+#define IRNEN_DCDCAPD_EN 0x00400000
+/** DCDCDDR Alarm
+    Interrupt enable bit for the corresponding bit in the IRNCR register. */
+#define IRNEN_DCDCDDR 0x00200000
+/* Disable
+#define IRNEN_DCDCDDR_DIS 0x00000000 */
+/** Enable */
+#define IRNEN_DCDCDDR_EN 0x00200000
+/** DCDC1V0 Alarm
+    Interrupt enable bit for the corresponding bit in the IRNCR register. */
+#define IRNEN_DCDC1V0 0x00100000
+/* Disable
+#define IRNEN_DCDC1V0_DIS 0x00000000 */
+/** Enable */
+#define IRNEN_DCDC1V0_EN 0x00100000
+/** SIF0 wakeup request
+    Interrupt enable bit for the corresponding bit in the IRNCR register. */
+#define IRNEN_SIF0 0x00010000
+/* Disable
+#define IRNEN_SIF0_DIS 0x00000000 */
+/** Enable */
+#define IRNEN_SIF0_EN 0x00010000
+
+/*! @} */ /* SYS1_REGISTER */
+
+#endif /* _sys1_reg_h */
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/falcon/sys_eth_reg.h
@@ -0,0 +1,1132 @@
+/******************************************************************************
+
+                               Copyright (c) 2010
+                            Lantiq Deutschland GmbH
+
+  For licensing information, see the file 'LICENSE' in the root folder of
+  this software module.
+
+******************************************************************************/
+
+#ifndef _sys_eth_reg_h
+#define _sys_eth_reg_h
+
+/** \addtogroup SYS_ETH_REGISTER
+   @{
+*/
+/* access macros */
+#define sys_eth_r32(reg) reg_r32(&sys_eth->reg)
+#define sys_eth_w32(val, reg) reg_w32(val, &sys_eth->reg)
+#define sys_eth_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &sys_eth->reg)
+#define sys_eth_r32_table(reg, idx) reg_r32_table(sys_eth->reg, idx)
+#define sys_eth_w32_table(val, reg, idx) reg_w32_table(val, sys_eth->reg, idx)
+#define sys_eth_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, sys_eth->reg, idx)
+#define sys_eth_adr_table(reg, idx) adr_table(sys_eth->reg, idx)
+
+
+/** SYS_ETH register structure */
+struct gpon_reg_sys_eth
+{
+   /** Clock Status Register */
+   unsigned int clks; /* 0x00000000 */
+   /** Clock Enable Register
+       Via this register the clocks for the domains can be enabled. */
+   unsigned int clken; /* 0x00000004 */
+   /** Clock Clear Register
+       Via this register the clocks for the domains can be disabled. */
+   unsigned int clkclr; /* 0x00000008 */
+   /** Reserved */
+   unsigned int res_0[5]; /* 0x0000000C */
+   /** Activation Status Register */
+   unsigned int acts; /* 0x00000020 */
+   /** Activation Register
+       Via this register the domains can be activated. */
+   unsigned int act; /* 0x00000024 */
+   /** Deactivation Register
+       Via this register the domains can be deactivated. */
+   unsigned int deact; /* 0x00000028 */
+   /** Reboot Trigger Register
+       Via this register the domains can be rebooted (sent through reset). */
+   unsigned int rbt; /* 0x0000002C */
+   /** Reserved */
+   unsigned int res_1[32]; /* 0x00000030 */
+   /** External PHY Control Register */
+   unsigned int extphyc; /* 0x000000B0 */
+   /** Power Down Configuration Register
+       Via this register the configuration is done whether in case of deactivation the power supply of the domain shall be removed. */
+   unsigned int pdcfg; /* 0x000000B4 */
+   /** Datarate Control Register
+       Controls the datarate of the various physical layers. The contents of the writeable fields of this register shall not be changed during operation. */
+   unsigned int drc; /* 0x000000B8 */
+   /** GMAC Multiplexer Control Register
+       Controls the interconnect between GMACs and the various physical layers. All fields need to have a different content. If two GMACs are muxed to the same PHY unpredictable results may occur. The contents of this register shall not be changed during operation. */
+   unsigned int gmuxc; /* 0x000000BC */
+   /** Datarate Status Register
+       Shows the datarate of the GMACs. The datarate of a GMAC is derived from the datarate of the physical layer it is multiplexed to. This register is for debugging only. */
+   unsigned int drs; /* 0x000000C0 */
+   /** SGMII Control Register */
+   unsigned int sgmiic; /* 0x000000C4 */
+   /** Reserved */
+   unsigned int res_2[14]; /* 0x000000C8 */
+};
+
+
+/* Fields of "Clock Status Register" */
+/** GPHY1MII2 Clock Enable
+    Shows the clock enable bit for GPHY1MII2. */
+#define SYS_ETH_CLKS_GPHY1MII2 0x02000000
+/* Disable
+#define SYS_ETH_CLKS_GPHY1MII2_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_CLKS_GPHY1MII2_EN 0x02000000
+/** GPHY0MII2 Clock Enable
+    Shows the clock enable bit for GPHY0MII2. */
+#define SYS_ETH_CLKS_GPHY0MII2 0x01000000
+/* Disable
+#define SYS_ETH_CLKS_GPHY0MII2_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_CLKS_GPHY0MII2_EN 0x01000000
+/** PADCTRL2 Clock Enable
+    Shows the clock enable bit for the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
+#define SYS_ETH_CLKS_PADCTRL2 0x00200000
+/* Disable
+#define SYS_ETH_CLKS_PADCTRL2_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_CLKS_PADCTRL2_EN 0x00200000
+/** PADCTRL0 Clock Enable
+    Shows the clock enable bit for the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
+#define SYS_ETH_CLKS_PADCTRL0 0x00100000
+/* Disable
+#define SYS_ETH_CLKS_PADCTRL0_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_CLKS_PADCTRL0_EN 0x00100000
+/** P2 Clock Enable
+    Shows the clock enable bit for the P2 domain. This domain contains the P2 instance of the GPIO block. */
+#define SYS_ETH_CLKS_P2 0x00020000
+/* Disable
+#define SYS_ETH_CLKS_P2_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_CLKS_P2_EN 0x00020000
+/** P0 Clock Enable
+    Shows the clock enable bit for the P0 domain. This domain contains the P0 instance of the GPIO block. */
+#define SYS_ETH_CLKS_P0 0x00010000
+/* Disable
+#define SYS_ETH_CLKS_P0_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_CLKS_P0_EN 0x00010000
+/** xMII Clock Enable
+    Shows the clock enable bit for the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
+#define SYS_ETH_CLKS_xMII 0x00000800
+/* Disable
+#define SYS_ETH_CLKS_xMII_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_CLKS_xMII_EN 0x00000800
+/** SGMII Clock Enable
+    Shows the clock enable bit for the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
+#define SYS_ETH_CLKS_SGMII 0x00000400
+/* Disable
+#define SYS_ETH_CLKS_SGMII_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_CLKS_SGMII_EN 0x00000400
+/** GPHY1 Clock Enable
+    Shows the clock enable bit for the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
+#define SYS_ETH_CLKS_GPHY1 0x00000200
+/* Disable
+#define SYS_ETH_CLKS_GPHY1_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_CLKS_GPHY1_EN 0x00000200
+/** GPHY0 Clock Enable
+    Shows the clock enable bit for the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
+#define SYS_ETH_CLKS_GPHY0 0x00000100
+/* Disable
+#define SYS_ETH_CLKS_GPHY0_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_CLKS_GPHY0_EN 0x00000100
+/** MDIO Clock Enable
+    Shows the clock enable bit for the MDIO domain. This domain contains the MDIO block. */
+#define SYS_ETH_CLKS_MDIO 0x00000080
+/* Disable
+#define SYS_ETH_CLKS_MDIO_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_CLKS_MDIO_EN 0x00000080
+/** GMAC3 Clock Enable
+    Shows the clock enable bit for the GMAC3 domain. This domain contains the GMAC3 block. */
+#define SYS_ETH_CLKS_GMAC3 0x00000008
+/* Disable
+#define SYS_ETH_CLKS_GMAC3_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_CLKS_GMAC3_EN 0x00000008
+/** GMAC2 Clock Enable
+    Shows the clock enable bit for the GMAC2 domain. This domain contains the GMAC2 block. */
+#define SYS_ETH_CLKS_GMAC2 0x00000004
+/* Disable
+#define SYS_ETH_CLKS_GMAC2_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_CLKS_GMAC2_EN 0x00000004
+/** GMAC1 Clock Enable
+    Shows the clock enable bit for the GMAC1 domain. This domain contains the GMAC1 block. */
+#define SYS_ETH_CLKS_GMAC1 0x00000002
+/* Disable
+#define SYS_ETH_CLKS_GMAC1_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_CLKS_GMAC1_EN 0x00000002
+/** GMAC0 Clock Enable
+    Shows the clock enable bit for the GMAC0 domain. This domain contains the GMAC0 block. */
+#define SYS_ETH_CLKS_GMAC0 0x00000001
+/* Disable
+#define SYS_ETH_CLKS_GMAC0_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_CLKS_GMAC0_EN 0x00000001
+
+/* Fields of "Clock Enable Register" */
+/** Set Clock Enable GPHY1MII2
+    Sets the clock enable bit of the GPHY1MII2. */
+#define SYS_ETH_CLKEN_GPHY1MII2 0x02000000
+/* No-Operation
+#define SYS_ETH_CLKEN_GPHY1MII2_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_CLKEN_GPHY1MII2_SET 0x02000000
+/** Set Clock Enable GPHY0MII2
+    Sets the clock enable bit of the GPHY0MII2. */
+#define SYS_ETH_CLKEN_GPHY0MII2 0x01000000
+/* No-Operation
+#define SYS_ETH_CLKEN_GPHY0MII2_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_CLKEN_GPHY0MII2_SET 0x01000000
+/** Set Clock Enable PADCTRL2
+    Sets the clock enable bit of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
+#define SYS_ETH_CLKEN_PADCTRL2 0x00200000
+/* No-Operation
+#define SYS_ETH_CLKEN_PADCTRL2_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_CLKEN_PADCTRL2_SET 0x00200000
+/** Set Clock Enable PADCTRL0
+    Sets the clock enable bit of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
+#define SYS_ETH_CLKEN_PADCTRL0 0x00100000
+/* No-Operation
+#define SYS_ETH_CLKEN_PADCTRL0_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_CLKEN_PADCTRL0_SET 0x00100000
+/** Set Clock Enable P2
+    Sets the clock enable bit of the P2 domain. This domain contains the P2 instance of the GPIO block. */
+#define SYS_ETH_CLKEN_P2 0x00020000
+/* No-Operation
+#define SYS_ETH_CLKEN_P2_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_CLKEN_P2_SET 0x00020000
+/** Set Clock Enable P0
+    Sets the clock enable bit of the P0 domain. This domain contains the P0 instance of the GPIO block. */
+#define SYS_ETH_CLKEN_P0 0x00010000
+/* No-Operation
+#define SYS_ETH_CLKEN_P0_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_CLKEN_P0_SET 0x00010000
+/** Set Clock Enable xMII
+    Sets the clock enable bit of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
+#define SYS_ETH_CLKEN_xMII 0x00000800
+/* No-Operation
+#define SYS_ETH_CLKEN_xMII_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_CLKEN_xMII_SET 0x00000800
+/** Set Clock Enable SGMII
+    Sets the clock enable bit of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
+#define SYS_ETH_CLKEN_SGMII 0x00000400
+/* No-Operation
+#define SYS_ETH_CLKEN_SGMII_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_CLKEN_SGMII_SET 0x00000400
+/** Set Clock Enable GPHY1
+    Sets the clock enable bit of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
+#define SYS_ETH_CLKEN_GPHY1 0x00000200
+/* No-Operation
+#define SYS_ETH_CLKEN_GPHY1_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_CLKEN_GPHY1_SET 0x00000200
+/** Set Clock Enable GPHY0
+    Sets the clock enable bit of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
+#define SYS_ETH_CLKEN_GPHY0 0x00000100
+/* No-Operation
+#define SYS_ETH_CLKEN_GPHY0_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_CLKEN_GPHY0_SET 0x00000100
+/** Set Clock Enable MDIO
+    Sets the clock enable bit of the MDIO domain. This domain contains the MDIO block. */
+#define SYS_ETH_CLKEN_MDIO 0x00000080
+/* No-Operation
+#define SYS_ETH_CLKEN_MDIO_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_CLKEN_MDIO_SET 0x00000080
+/** Set Clock Enable GMAC3
+    Sets the clock enable bit of the GMAC3 domain. This domain contains the GMAC3 block. */
+#define SYS_ETH_CLKEN_GMAC3 0x00000008
+/* No-Operation
+#define SYS_ETH_CLKEN_GMAC3_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_CLKEN_GMAC3_SET 0x00000008
+/** Set Clock Enable GMAC2
+    Sets the clock enable bit of the GMAC2 domain. This domain contains the GMAC2 block. */
+#define SYS_ETH_CLKEN_GMAC2 0x00000004
+/* No-Operation
+#define SYS_ETH_CLKEN_GMAC2_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_CLKEN_GMAC2_SET 0x00000004
+/** Set Clock Enable GMAC1
+    Sets the clock enable bit of the GMAC1 domain. This domain contains the GMAC1 block. */
+#define SYS_ETH_CLKEN_GMAC1 0x00000002
+/* No-Operation
+#define SYS_ETH_CLKEN_GMAC1_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_CLKEN_GMAC1_SET 0x00000002
+/** Set Clock Enable GMAC0
+    Sets the clock enable bit of the GMAC0 domain. This domain contains the GMAC0 block. */
+#define SYS_ETH_CLKEN_GMAC0 0x00000001
+/* No-Operation
+#define SYS_ETH_CLKEN_GMAC0_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_CLKEN_GMAC0_SET 0x00000001
+
+/* Fields of "Clock Clear Register" */
+/** Clear Clock Enable GPHY1MII2
+    Clears the clock enable bit of the GPHY1MII2. */
+#define SYS_ETH_CLKCLR_GPHY1MII2 0x02000000
+/* No-Operation
+#define SYS_ETH_CLKCLR_GPHY1MII2_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_CLKCLR_GPHY1MII2_CLR 0x02000000
+/** Clear Clock Enable GPHY0MII2
+    Clears the clock enable bit of the GPHY0MII2. */
+#define SYS_ETH_CLKCLR_GPHY0MII2 0x01000000
+/* No-Operation
+#define SYS_ETH_CLKCLR_GPHY0MII2_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_CLKCLR_GPHY0MII2_CLR 0x01000000
+/** Clear Clock Enable PADCTRL2
+    Clears the clock enable bit of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
+#define SYS_ETH_CLKCLR_PADCTRL2 0x00200000
+/* No-Operation
+#define SYS_ETH_CLKCLR_PADCTRL2_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_CLKCLR_PADCTRL2_CLR 0x00200000
+/** Clear Clock Enable PADCTRL0
+    Clears the clock enable bit of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
+#define SYS_ETH_CLKCLR_PADCTRL0 0x00100000
+/* No-Operation
+#define SYS_ETH_CLKCLR_PADCTRL0_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_CLKCLR_PADCTRL0_CLR 0x00100000
+/** Clear Clock Enable P2
+    Clears the clock enable bit of the P2 domain. This domain contains the P2 instance of the GPIO block. */
+#define SYS_ETH_CLKCLR_P2 0x00020000
+/* No-Operation
+#define SYS_ETH_CLKCLR_P2_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_CLKCLR_P2_CLR 0x00020000
+/** Clear Clock Enable P0
+    Clears the clock enable bit of the P0 domain. This domain contains the P0 instance of the GPIO block. */
+#define SYS_ETH_CLKCLR_P0 0x00010000
+/* No-Operation
+#define SYS_ETH_CLKCLR_P0_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_CLKCLR_P0_CLR 0x00010000
+/** Clear Clock Enable xMII
+    Clears the clock enable bit of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
+#define SYS_ETH_CLKCLR_xMII 0x00000800
+/* No-Operation
+#define SYS_ETH_CLKCLR_xMII_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_CLKCLR_xMII_CLR 0x00000800
+/** Clear Clock Enable SGMII
+    Clears the clock enable bit of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
+#define SYS_ETH_CLKCLR_SGMII 0x00000400
+/* No-Operation
+#define SYS_ETH_CLKCLR_SGMII_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_CLKCLR_SGMII_CLR 0x00000400
+/** Clear Clock Enable GPHY1
+    Clears the clock enable bit of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
+#define SYS_ETH_CLKCLR_GPHY1 0x00000200
+/* No-Operation
+#define SYS_ETH_CLKCLR_GPHY1_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_CLKCLR_GPHY1_CLR 0x00000200
+/** Clear Clock Enable GPHY0
+    Clears the clock enable bit of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
+#define SYS_ETH_CLKCLR_GPHY0 0x00000100
+/* No-Operation
+#define SYS_ETH_CLKCLR_GPHY0_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_CLKCLR_GPHY0_CLR 0x00000100
+/** Clear Clock Enable MDIO
+    Clears the clock enable bit of the MDIO domain. This domain contains the MDIO block. */
+#define SYS_ETH_CLKCLR_MDIO 0x00000080
+/* No-Operation
+#define SYS_ETH_CLKCLR_MDIO_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_CLKCLR_MDIO_CLR 0x00000080
+/** Clear Clock Enable GMAC3
+    Clears the clock enable bit of the GMAC3 domain. This domain contains the GMAC3 block. */
+#define SYS_ETH_CLKCLR_GMAC3 0x00000008
+/* No-Operation
+#define SYS_ETH_CLKCLR_GMAC3_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_CLKCLR_GMAC3_CLR 0x00000008
+/** Clear Clock Enable GMAC2
+    Clears the clock enable bit of the GMAC2 domain. This domain contains the GMAC2 block. */
+#define SYS_ETH_CLKCLR_GMAC2 0x00000004
+/* No-Operation
+#define SYS_ETH_CLKCLR_GMAC2_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_CLKCLR_GMAC2_CLR 0x00000004
+/** Clear Clock Enable GMAC1
+    Clears the clock enable bit of the GMAC1 domain. This domain contains the GMAC1 block. */
+#define SYS_ETH_CLKCLR_GMAC1 0x00000002
+/* No-Operation
+#define SYS_ETH_CLKCLR_GMAC1_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_CLKCLR_GMAC1_CLR 0x00000002
+/** Clear Clock Enable GMAC0
+    Clears the clock enable bit of the GMAC0 domain. This domain contains the GMAC0 block. */
+#define SYS_ETH_CLKCLR_GMAC0 0x00000001
+/* No-Operation
+#define SYS_ETH_CLKCLR_GMAC0_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_CLKCLR_GMAC0_CLR 0x00000001
+
+/* Fields of "Activation Status Register" */
+/** PADCTRL2 Status
+    Shows the activation status of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
+#define SYS_ETH_ACTS_PADCTRL2 0x00200000
+/* The block is inactive.
+#define SYS_ETH_ACTS_PADCTRL2_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_ETH_ACTS_PADCTRL2_ACT 0x00200000
+/** PADCTRL0 Status
+    Shows the activation status of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
+#define SYS_ETH_ACTS_PADCTRL0 0x00100000
+/* The block is inactive.
+#define SYS_ETH_ACTS_PADCTRL0_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_ETH_ACTS_PADCTRL0_ACT 0x00100000
+/** P2 Status
+    Shows the activation status of the P2 domain. This domain contains the P2 instance of the GPIO block. */
+#define SYS_ETH_ACTS_P2 0x00020000
+/* The block is inactive.
+#define SYS_ETH_ACTS_P2_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_ETH_ACTS_P2_ACT 0x00020000
+/** P0 Status
+    Shows the activation status of the P0 domain. This domain contains the P0 instance of the GPIO block. */
+#define SYS_ETH_ACTS_P0 0x00010000
+/* The block is inactive.
+#define SYS_ETH_ACTS_P0_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_ETH_ACTS_P0_ACT 0x00010000
+/** xMII Status
+    Shows the activation status of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
+#define SYS_ETH_ACTS_xMII 0x00000800
+/* The block is inactive.
+#define SYS_ETH_ACTS_xMII_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_ETH_ACTS_xMII_ACT 0x00000800
+/** SGMII Status
+    Shows the activation status of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
+#define SYS_ETH_ACTS_SGMII 0x00000400
+/* The block is inactive.
+#define SYS_ETH_ACTS_SGMII_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_ETH_ACTS_SGMII_ACT 0x00000400
+/** GPHY1 Status
+    Shows the activation status of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
+#define SYS_ETH_ACTS_GPHY1 0x00000200
+/* The block is inactive.
+#define SYS_ETH_ACTS_GPHY1_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_ETH_ACTS_GPHY1_ACT 0x00000200
+/** GPHY0 Status
+    Shows the activation status of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
+#define SYS_ETH_ACTS_GPHY0 0x00000100
+/* The block is inactive.
+#define SYS_ETH_ACTS_GPHY0_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_ETH_ACTS_GPHY0_ACT 0x00000100
+/** MDIO Status
+    Shows the activation status of the MDIO domain. This domain contains the MDIO block. */
+#define SYS_ETH_ACTS_MDIO 0x00000080
+/* The block is inactive.
+#define SYS_ETH_ACTS_MDIO_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_ETH_ACTS_MDIO_ACT 0x00000080
+/** GMAC3 Status
+    Shows the activation status of the GMAC3 domain. This domain contains the GMAC3 block. */
+#define SYS_ETH_ACTS_GMAC3 0x00000008
+/* The block is inactive.
+#define SYS_ETH_ACTS_GMAC3_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_ETH_ACTS_GMAC3_ACT 0x00000008
+/** GMAC2 Status
+    Shows the activation status of the GMAC2 domain. This domain contains the GMAC2 block. */
+#define SYS_ETH_ACTS_GMAC2 0x00000004
+/* The block is inactive.
+#define SYS_ETH_ACTS_GMAC2_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_ETH_ACTS_GMAC2_ACT 0x00000004
+/** GMAC1 Status
+    Shows the activation status of the GMAC1 domain. This domain contains the GMAC1 block. */
+#define SYS_ETH_ACTS_GMAC1 0x00000002
+/* The block is inactive.
+#define SYS_ETH_ACTS_GMAC1_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_ETH_ACTS_GMAC1_ACT 0x00000002
+/** GMAC0 Status
+    Shows the activation status of the GMAC0 domain. This domain contains the GMAC0 block. */
+#define SYS_ETH_ACTS_GMAC0 0x00000001
+/* The block is inactive.
+#define SYS_ETH_ACTS_GMAC0_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_ETH_ACTS_GMAC0_ACT 0x00000001
+
+/* Fields of "Activation Register" */
+/** Activate PADCTRL2
+    Sets the activation flag of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
+#define SYS_ETH_ACT_PADCTRL2 0x00200000
+/* No-Operation
+#define SYS_ETH_ACT_PADCTRL2_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_ACT_PADCTRL2_SET 0x00200000
+/** Activate PADCTRL0
+    Sets the activation flag of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
+#define SYS_ETH_ACT_PADCTRL0 0x00100000
+/* No-Operation
+#define SYS_ETH_ACT_PADCTRL0_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_ACT_PADCTRL0_SET 0x00100000
+/** Activate P2
+    Sets the activation flag of the P2 domain. This domain contains the P2 instance of the GPIO block. */
+#define SYS_ETH_ACT_P2 0x00020000
+/* No-Operation
+#define SYS_ETH_ACT_P2_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_ACT_P2_SET 0x00020000
+/** Activate P0
+    Sets the activation flag of the P0 domain. This domain contains the P0 instance of the GPIO block. */
+#define SYS_ETH_ACT_P0 0x00010000
+/* No-Operation
+#define SYS_ETH_ACT_P0_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_ACT_P0_SET 0x00010000
+/** Activate xMII
+    Sets the activation flag of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
+#define SYS_ETH_ACT_xMII 0x00000800
+/* No-Operation
+#define SYS_ETH_ACT_xMII_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_ACT_xMII_SET 0x00000800
+/** Activate SGMII
+    Sets the activation flag of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
+#define SYS_ETH_ACT_SGMII 0x00000400
+/* No-Operation
+#define SYS_ETH_ACT_SGMII_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_ACT_SGMII_SET 0x00000400
+/** Activate GPHY1
+    Sets the activation flag of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
+#define SYS_ETH_ACT_GPHY1 0x00000200
+/* No-Operation
+#define SYS_ETH_ACT_GPHY1_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_ACT_GPHY1_SET 0x00000200
+/** Activate GPHY0
+    Sets the activation flag of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
+#define SYS_ETH_ACT_GPHY0 0x00000100
+/* No-Operation
+#define SYS_ETH_ACT_GPHY0_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_ACT_GPHY0_SET 0x00000100
+/** Activate MDIO
+    Sets the activation flag of the MDIO domain. This domain contains the MDIO block. */
+#define SYS_ETH_ACT_MDIO 0x00000080
+/* No-Operation
+#define SYS_ETH_ACT_MDIO_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_ACT_MDIO_SET 0x00000080
+/** Activate GMAC3
+    Sets the activation flag of the GMAC3 domain. This domain contains the GMAC3 block. */
+#define SYS_ETH_ACT_GMAC3 0x00000008
+/* No-Operation
+#define SYS_ETH_ACT_GMAC3_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_ACT_GMAC3_SET 0x00000008
+/** Activate GMAC2
+    Sets the activation flag of the GMAC2 domain. This domain contains the GMAC2 block. */
+#define SYS_ETH_ACT_GMAC2 0x00000004
+/* No-Operation
+#define SYS_ETH_ACT_GMAC2_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_ACT_GMAC2_SET 0x00000004
+/** Activate GMAC1
+    Sets the activation flag of the GMAC1 domain. This domain contains the GMAC1 block. */
+#define SYS_ETH_ACT_GMAC1 0x00000002
+/* No-Operation
+#define SYS_ETH_ACT_GMAC1_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_ACT_GMAC1_SET 0x00000002
+/** Activate GMAC0
+    Sets the activation flag of the GMAC0 domain. This domain contains the GMAC0 block. */
+#define SYS_ETH_ACT_GMAC0 0x00000001
+/* No-Operation
+#define SYS_ETH_ACT_GMAC0_NOP 0x00000000 */
+/** Set */
+#define SYS_ETH_ACT_GMAC0_SET 0x00000001
+
+/* Fields of "Deactivation Register" */
+/** Deactivate PADCTRL2
+    Clears the activation flag of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
+#define SYS_ETH_DEACT_PADCTRL2 0x00200000
+/* No-Operation
+#define SYS_ETH_DEACT_PADCTRL2_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_DEACT_PADCTRL2_CLR 0x00200000
+/** Deactivate PADCTRL0
+    Clears the activation flag of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
+#define SYS_ETH_DEACT_PADCTRL0 0x00100000
+/* No-Operation
+#define SYS_ETH_DEACT_PADCTRL0_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_DEACT_PADCTRL0_CLR 0x00100000
+/** Deactivate P2
+    Clears the activation flag of the P2 domain. This domain contains the P2 instance of the GPIO block. */
+#define SYS_ETH_DEACT_P2 0x00020000
+/* No-Operation
+#define SYS_ETH_DEACT_P2_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_DEACT_P2_CLR 0x00020000
+/** Deactivate P0
+    Clears the activation flag of the P0 domain. This domain contains the P0 instance of the GPIO block. */
+#define SYS_ETH_DEACT_P0 0x00010000
+/* No-Operation
+#define SYS_ETH_DEACT_P0_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_DEACT_P0_CLR 0x00010000
+/** Deactivate xMII
+    Clears the activation flag of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
+#define SYS_ETH_DEACT_xMII 0x00000800
+/* No-Operation
+#define SYS_ETH_DEACT_xMII_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_DEACT_xMII_CLR 0x00000800
+/** Deactivate SGMII
+    Clears the activation flag of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
+#define SYS_ETH_DEACT_SGMII 0x00000400
+/* No-Operation
+#define SYS_ETH_DEACT_SGMII_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_DEACT_SGMII_CLR 0x00000400
+/** Deactivate GPHY1
+    Clears the activation flag of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
+#define SYS_ETH_DEACT_GPHY1 0x00000200
+/* No-Operation
+#define SYS_ETH_DEACT_GPHY1_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_DEACT_GPHY1_CLR 0x00000200
+/** Deactivate GPHY0
+    Clears the activation flag of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
+#define SYS_ETH_DEACT_GPHY0 0x00000100
+/* No-Operation
+#define SYS_ETH_DEACT_GPHY0_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_DEACT_GPHY0_CLR 0x00000100
+/** Deactivate MDIO
+    Clears the activation flag of the MDIO domain. This domain contains the MDIO block. */
+#define SYS_ETH_DEACT_MDIO 0x00000080
+/* No-Operation
+#define SYS_ETH_DEACT_MDIO_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_DEACT_MDIO_CLR 0x00000080
+/** Deactivate GMAC3
+    Clears the activation flag of the GMAC3 domain. This domain contains the GMAC3 block. */
+#define SYS_ETH_DEACT_GMAC3 0x00000008
+/* No-Operation
+#define SYS_ETH_DEACT_GMAC3_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_DEACT_GMAC3_CLR 0x00000008
+/** Deactivate GMAC2
+    Clears the activation flag of the GMAC2 domain. This domain contains the GMAC2 block. */
+#define SYS_ETH_DEACT_GMAC2 0x00000004
+/* No-Operation
+#define SYS_ETH_DEACT_GMAC2_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_DEACT_GMAC2_CLR 0x00000004
+/** Deactivate GMAC1
+    Clears the activation flag of the GMAC1 domain. This domain contains the GMAC1 block. */
+#define SYS_ETH_DEACT_GMAC1 0x00000002
+/* No-Operation
+#define SYS_ETH_DEACT_GMAC1_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_DEACT_GMAC1_CLR 0x00000002
+/** Deactivate GMAC0
+    Clears the activation flag of the GMAC0 domain. This domain contains the GMAC0 block. */
+#define SYS_ETH_DEACT_GMAC0 0x00000001
+/* No-Operation
+#define SYS_ETH_DEACT_GMAC0_NOP 0x00000000 */
+/** Clear */
+#define SYS_ETH_DEACT_GMAC0_CLR 0x00000001
+
+/* Fields of "Reboot Trigger Register" */
+/** Reboot PADCTRL2
+    Triggers a reboot of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
+#define SYS_ETH_RBT_PADCTRL2 0x00200000
+/* No-Operation
+#define SYS_ETH_RBT_PADCTRL2_NOP 0x00000000 */
+/** Trigger */
+#define SYS_ETH_RBT_PADCTRL2_TRIG 0x00200000
+/** Reboot PADCTRL0
+    Triggers a reboot of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
+#define SYS_ETH_RBT_PADCTRL0 0x00100000
+/* No-Operation
+#define SYS_ETH_RBT_PADCTRL0_NOP 0x00000000 */
+/** Trigger */
+#define SYS_ETH_RBT_PADCTRL0_TRIG 0x00100000
+/** Reboot P2
+    Triggers a reboot of the P2 domain. This domain contains the P2 instance of the GPIO block. */
+#define SYS_ETH_RBT_P2 0x00020000
+/* No-Operation
+#define SYS_ETH_RBT_P2_NOP 0x00000000 */
+/** Trigger */
+#define SYS_ETH_RBT_P2_TRIG 0x00020000
+/** Reboot P0
+    Triggers a reboot of the P0 domain. This domain contains the P0 instance of the GPIO block. */
+#define SYS_ETH_RBT_P0 0x00010000
+/* No-Operation
+#define SYS_ETH_RBT_P0_NOP 0x00000000 */
+/** Trigger */
+#define SYS_ETH_RBT_P0_TRIG 0x00010000
+/** Reboot xMII
+    Triggers a reboot of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
+#define SYS_ETH_RBT_xMII 0x00000800
+/* No-Operation
+#define SYS_ETH_RBT_xMII_NOP 0x00000000 */
+/** Trigger */
+#define SYS_ETH_RBT_xMII_TRIG 0x00000800
+/** Reboot SGMII
+    Triggers a reboot of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
+#define SYS_ETH_RBT_SGMII 0x00000400
+/* No-Operation
+#define SYS_ETH_RBT_SGMII_NOP 0x00000000 */
+/** Trigger */
+#define SYS_ETH_RBT_SGMII_TRIG 0x00000400
+/** Reboot GPHY1
+    Triggers a reboot of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
+#define SYS_ETH_RBT_GPHY1 0x00000200
+/* No-Operation
+#define SYS_ETH_RBT_GPHY1_NOP 0x00000000 */
+/** Trigger */
+#define SYS_ETH_RBT_GPHY1_TRIG 0x00000200
+/** Reboot GPHY0
+    Triggers a reboot of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
+#define SYS_ETH_RBT_GPHY0 0x00000100
+/* No-Operation
+#define SYS_ETH_RBT_GPHY0_NOP 0x00000000 */
+/** Trigger */
+#define SYS_ETH_RBT_GPHY0_TRIG 0x00000100
+/** Reboot MDIO
+    Triggers a reboot of the MDIO domain. This domain contains the MDIO block. */
+#define SYS_ETH_RBT_MDIO 0x00000080
+/* No-Operation
+#define SYS_ETH_RBT_MDIO_NOP 0x00000000 */
+/** Trigger */
+#define SYS_ETH_RBT_MDIO_TRIG 0x00000080
+/** Reboot GMAC3
+    Triggers a reboot of the GMAC3 domain. This domain contains the GMAC3 block. */
+#define SYS_ETH_RBT_GMAC3 0x00000008
+/* No-Operation
+#define SYS_ETH_RBT_GMAC3_NOP 0x00000000 */
+/** Trigger */
+#define SYS_ETH_RBT_GMAC3_TRIG 0x00000008
+/** Reboot GMAC2
+    Triggers a reboot of the GMAC2 domain. This domain contains the GMAC2 block. */
+#define SYS_ETH_RBT_GMAC2 0x00000004
+/* No-Operation
+#define SYS_ETH_RBT_GMAC2_NOP 0x00000000 */
+/** Trigger */
+#define SYS_ETH_RBT_GMAC2_TRIG 0x00000004
+/** Reboot GMAC1
+    Triggers a reboot of the GMAC1 domain. This domain contains the GMAC1 block. */
+#define SYS_ETH_RBT_GMAC1 0x00000002
+/* No-Operation
+#define SYS_ETH_RBT_GMAC1_NOP 0x00000000 */
+/** Trigger */
+#define SYS_ETH_RBT_GMAC1_TRIG 0x00000002
+/** Reboot GMAC0
+    Triggers a reboot of the GMAC0 domain. This domain contains the GMAC0 block. */
+#define SYS_ETH_RBT_GMAC0 0x00000001
+/* No-Operation
+#define SYS_ETH_RBT_GMAC0_NOP 0x00000000 */
+/** Trigger */
+#define SYS_ETH_RBT_GMAC0_TRIG 0x00000001
+
+/* Fields of "External PHY Control Register" */
+/** PHY_CLKO Output Enable
+    Enables the output driver of the PHY_CLKO pin. */
+#define SYS_ETH_EXTPHYC_CLKEN 0x80000000
+/* Disable
+#define SYS_ETH_EXTPHYC_CLKEN_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_EXTPHYC_CLKEN_EN 0x80000000
+/** PHY_CLKO Frequency Select
+    Selects the frequency of the PHY_CLKO pin. */
+#define SYS_ETH_EXTPHYC_CLKSEL_MASK 0x00000007
+/** field offset */
+#define SYS_ETH_EXTPHYC_CLKSEL_OFFSET 0
+/** 25 MHz. */
+#define SYS_ETH_EXTPHYC_CLKSEL_F25 0x00000001
+/** 125 MHz. */
+#define SYS_ETH_EXTPHYC_CLKSEL_F125 0x00000002
+/** 50 MHz. */
+#define SYS_ETH_EXTPHYC_CLKSEL_F50 0x00000005
+
+/* Fields of "Power Down Configuration Register" */
+/** Enable Power Down PADCTRL2
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_ETH_PDCFG_PADCTRL2 0x00200000
+/* Disable
+#define SYS_ETH_PDCFG_PADCTRL2_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_PDCFG_PADCTRL2_EN 0x00200000
+/** Enable Power Down PADCTRL0
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_ETH_PDCFG_PADCTRL0 0x00100000
+/* Disable
+#define SYS_ETH_PDCFG_PADCTRL0_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_PDCFG_PADCTRL0_EN 0x00100000
+/** Enable Power Down P2
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_ETH_PDCFG_P2 0x00020000
+/* Disable
+#define SYS_ETH_PDCFG_P2_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_PDCFG_P2_EN 0x00020000
+/** Enable Power Down P0
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_ETH_PDCFG_P0 0x00010000
+/* Disable
+#define SYS_ETH_PDCFG_P0_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_PDCFG_P0_EN 0x00010000
+/** Enable Power Down xMII
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_ETH_PDCFG_xMII 0x00000800
+/* Disable
+#define SYS_ETH_PDCFG_xMII_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_PDCFG_xMII_EN 0x00000800
+/** Enable Power Down SGMII
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_ETH_PDCFG_SGMII 0x00000400
+/* Disable
+#define SYS_ETH_PDCFG_SGMII_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_PDCFG_SGMII_EN 0x00000400
+/** Enable Power Down GPHY1
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_ETH_PDCFG_GPHY1 0x00000200
+/* Disable
+#define SYS_ETH_PDCFG_GPHY1_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_PDCFG_GPHY1_EN 0x00000200
+/** Enable Power Down GPHY0
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_ETH_PDCFG_GPHY0 0x00000100
+/* Disable
+#define SYS_ETH_PDCFG_GPHY0_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_PDCFG_GPHY0_EN 0x00000100
+/** Enable Power Down MDIO
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_ETH_PDCFG_MDIO 0x00000080
+/* Disable
+#define SYS_ETH_PDCFG_MDIO_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_PDCFG_MDIO_EN 0x00000080
+/** Enable Power Down GMAC3
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_ETH_PDCFG_GMAC3 0x00000008
+/* Disable
+#define SYS_ETH_PDCFG_GMAC3_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_PDCFG_GMAC3_EN 0x00000008
+/** Enable Power Down GMAC2
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_ETH_PDCFG_GMAC2 0x00000004
+/* Disable
+#define SYS_ETH_PDCFG_GMAC2_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_PDCFG_GMAC2_EN 0x00000004
+/** Enable Power Down GMAC1
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_ETH_PDCFG_GMAC1 0x00000002
+/* Disable
+#define SYS_ETH_PDCFG_GMAC1_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_PDCFG_GMAC1_EN 0x00000002
+/** Enable Power Down GMAC0
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_ETH_PDCFG_GMAC0 0x00000001
+/* Disable
+#define SYS_ETH_PDCFG_GMAC0_DIS 0x00000000 */
+/** Enable */
+#define SYS_ETH_PDCFG_GMAC0_EN 0x00000001
+
+/* Fields of "Datarate Control Register" */
+/** MDC Clockrate
+    Selects the clockrate of the MDIO interface. */
+#define SYS_ETH_DRC_MDC_MASK 0x30000000
+/** field offset */
+#define SYS_ETH_DRC_MDC_OFFSET 28
+/** 312.5/128 = appr. 2.44 MHz. */
+#define SYS_ETH_DRC_MDC_F2M44 0x00000000
+/** 312.5/64 = appr. 4.88 MHz. */
+#define SYS_ETH_DRC_MDC_F4M88 0x10000000
+/** 312.5/32 = appr. 9.77 MHz. */
+#define SYS_ETH_DRC_MDC_F9M77 0x20000000
+/** 312.5/16 = appr. 19.5 MHz. */
+#define SYS_ETH_DRC_MDC_F19M5 0x30000000
+/** xMII1 Datarate
+    Selects the datarate of the xMII1 interface. */
+#define SYS_ETH_DRC_xMII1_MASK 0x07000000
+/** field offset */
+#define SYS_ETH_DRC_xMII1_OFFSET 24
+/** 10 MBit/s. */
+#define SYS_ETH_DRC_xMII1_DR10 0x00000000
+/** 100 MBit/s. */
+#define SYS_ETH_DRC_xMII1_DR100 0x01000000
+/** 1000 MBit/s. */
+#define SYS_ETH_DRC_xMII1_DR1000 0x02000000
+/** 200 MBit/s. */
+#define SYS_ETH_DRC_xMII1_DR200 0x05000000
+/** xMII0 Datarate
+    Selects the datarate of the xMII0 interface. */
+#define SYS_ETH_DRC_xMII0_MASK 0x00700000
+/** field offset */
+#define SYS_ETH_DRC_xMII0_OFFSET 20
+/** 10 MBit/s. */
+#define SYS_ETH_DRC_xMII0_DR10 0x00000000
+/** 100 MBit/s. */
+#define SYS_ETH_DRC_xMII0_DR100 0x00100000
+/** 1000 MBit/s. */
+#define SYS_ETH_DRC_xMII0_DR1000 0x00200000
+/** 200 MBit/s. */
+#define SYS_ETH_DRC_xMII0_DR200 0x00500000
+/** SGMII Datarate
+    Selects the datarate of the SGMII interface. */
+#define SYS_ETH_DRC_SGMII_MASK 0x00070000
+/** field offset */
+#define SYS_ETH_DRC_SGMII_OFFSET 16
+/** 10 MBit/s. */
+#define SYS_ETH_DRC_SGMII_DR10 0x00000000
+/** 100 MBit/s. */
+#define SYS_ETH_DRC_SGMII_DR100 0x00010000
+/** 1000 MBit/s. */
+#define SYS_ETH_DRC_SGMII_DR1000 0x00020000
+/** 2500 MBit/s. */
+#define SYS_ETH_DRC_SGMII_DR2500 0x00040000
+/** GPHY1_MII2 Datarate
+    Shows the datarate of the GPHY1_MII2 interface. */
+#define SYS_ETH_DRC_GPHY1_MII2_MASK 0x00007000
+/** field offset */
+#define SYS_ETH_DRC_GPHY1_MII2_OFFSET 12
+/** 10 MBit/s. */
+#define SYS_ETH_DRC_GPHY1_MII2_DR10 0x00000000
+/** 100 MBit/s. */
+#define SYS_ETH_DRC_GPHY1_MII2_DR100 0x00001000
+/** GPHY1_GMII Datarate
+    Shows the datarate of the GPHY1_GMII interface. */
+#define SYS_ETH_DRC_GPHY1_GMII_MASK 0x00000700
+/** field offset */
+#define SYS_ETH_DRC_GPHY1_GMII_OFFSET 8
+/** 10 MBit/s. */
+#define SYS_ETH_DRC_GPHY1_GMII_DR10 0x00000000
+/** 100 MBit/s. */
+#define SYS_ETH_DRC_GPHY1_GMII_DR100 0x00000100
+/** 1000 MBit/s. */
+#define SYS_ETH_DRC_GPHY1_GMII_DR1000 0x00000200
+/** GPHY0_MII2 Datarate
+    Shows the datarate of the GPHY0_MII2 interface. */
+#define SYS_ETH_DRC_GPHY0_MII2_MASK 0x00000070
+/** field offset */
+#define SYS_ETH_DRC_GPHY0_MII2_OFFSET 4
+/** 10 MBit/s. */
+#define SYS_ETH_DRC_GPHY0_MII2_DR10 0x00000000
+/** 100 MBit/s. */
+#define SYS_ETH_DRC_GPHY0_MII2_DR100 0x00000010
+/** GPHY0_GMII Datarate
+    Shows the datarate of the GPHY0_GMII interface. */
+#define SYS_ETH_DRC_GPHY0_GMII_MASK 0x00000007
+/** field offset */
+#define SYS_ETH_DRC_GPHY0_GMII_OFFSET 0
+/** 10 MBit/s. */
+#define SYS_ETH_DRC_GPHY0_GMII_DR10 0x00000000
+/** 100 MBit/s. */
+#define SYS_ETH_DRC_GPHY0_GMII_DR100 0x00000001
+/** 1000 MBit/s. */
+#define SYS_ETH_DRC_GPHY0_GMII_DR1000 0x00000002
+
+/* Fields of "GMAC Multiplexer Control Register" */
+/** GMAC 3 MUX setting
+    Selects the physical layer to be connected to GMAC3 */
+#define SYS_ETH_GMUXC_GMAC3_MASK 0x00007000
+/** field offset */
+#define SYS_ETH_GMUXC_GMAC3_OFFSET 12
+/** GMAC connects to GPHY0_GMII interface */
+#define SYS_ETH_GMUXC_GMAC3_GPHY0_GMII 0x00000000
+/** GMAC connects to GPHY0_MII2 interface */
+#define SYS_ETH_GMUXC_GMAC3_GPHY0_MII2 0x00001000
+/** GMAC connects to GPHY1_GMII interface */
+#define SYS_ETH_GMUXC_GMAC3_GPHY1_GMII 0x00002000
+/** GMAC connects to GPHY1_MII2 interface */
+#define SYS_ETH_GMUXC_GMAC3_GPHY1_MII2 0x00003000
+/** GMAC connects to SGMII interface */
+#define SYS_ETH_GMUXC_GMAC3_SGMII 0x00004000
+/** GMAC connects to xMII0 interface */
+#define SYS_ETH_GMUXC_GMAC3_xMII0 0x00005000
+/** GMAC connects to xMII1 interface */
+#define SYS_ETH_GMUXC_GMAC3_xMII1 0x00006000
+/** GMAC 2 MUX setting
+    Selects the physical layer to be connected to GMAC2 */
+#define SYS_ETH_GMUXC_GMAC2_MASK 0x00000700
+/** field offset */
+#define SYS_ETH_GMUXC_GMAC2_OFFSET 8
+/** GMAC connects to GPHY0_GMII interface */
+#define SYS_ETH_GMUXC_GMAC2_GPHY0_GMII 0x00000000
+/** GMAC connects to GPHY0_MII2 interface */
+#define SYS_ETH_GMUXC_GMAC2_GPHY0_MII2 0x00000100
+/** GMAC connects to GPHY1_GMII interface */
+#define SYS_ETH_GMUXC_GMAC2_GPHY1_GMII 0x00000200
+/** GMAC connects to GPHY1_MII2 interface */
+#define SYS_ETH_GMUXC_GMAC2_GPHY1_MII2 0x00000300
+/** GMAC connects to SGMII interface */
+#define SYS_ETH_GMUXC_GMAC2_SGMII 0x00000400
+/** GMAC connects to xMII0 interface */
+#define SYS_ETH_GMUXC_GMAC2_xMII0 0x00000500
+/** GMAC connects to xMII1 interface */
+#define SYS_ETH_GMUXC_GMAC2_xMII1 0x00000600
+/** GMAC 1 MUX setting
+    Selects the physical layer to be connected to GMAC1 */
+#define SYS_ETH_GMUXC_GMAC1_MASK 0x00000070
+/** field offset */
+#define SYS_ETH_GMUXC_GMAC1_OFFSET 4
+/** GMAC connects to GPHY0_GMII interface */
+#define SYS_ETH_GMUXC_GMAC1_GPHY0_GMII 0x00000000
+/** GMAC connects to GPHY0_MII2 interface */
+#define SYS_ETH_GMUXC_GMAC1_GPHY0_MII2 0x00000010
+/** GMAC connects to GPHY1_GMII interface */
+#define SYS_ETH_GMUXC_GMAC1_GPHY1_GMII 0x00000020
+/** GMAC connects to GPHY1_MII2 interface */
+#define SYS_ETH_GMUXC_GMAC1_GPHY1_MII2 0x00000030
+/** GMAC connects to SGMII interface */
+#define SYS_ETH_GMUXC_GMAC1_SGMII 0x00000040
+/** GMAC connects to xMII0 interface */
+#define SYS_ETH_GMUXC_GMAC1_xMII0 0x00000050
+/** GMAC connects to xMII1 interface */
+#define SYS_ETH_GMUXC_GMAC1_xMII1 0x00000060
+/** GMAC 0 MUX setting
+    Selects the physical layer to be connected to GMAC0 */
+#define SYS_ETH_GMUXC_GMAC0_MASK 0x00000007
+/** field offset */
+#define SYS_ETH_GMUXC_GMAC0_OFFSET 0
+/** GMAC connects to GPHY0_GMII interface */
+#define SYS_ETH_GMUXC_GMAC0_GPHY0_GMII 0x00000000
+/** GMAC connects to GPHY0_MII2 interface */
+#define SYS_ETH_GMUXC_GMAC0_GPHY0_MII2 0x00000001
+/** GMAC connects to GPHY1_GMII interface */
+#define SYS_ETH_GMUXC_GMAC0_GPHY1_GMII 0x00000002
+/** GMAC connects to GPHY1_MII2 interface */
+#define SYS_ETH_GMUXC_GMAC0_GPHY1_MII2 0x00000003
+/** GMAC connects to SGMII interface */
+#define SYS_ETH_GMUXC_GMAC0_SGMII 0x00000004
+/** GMAC connects to xMII0 interface */
+#define SYS_ETH_GMUXC_GMAC0_xMII0 0x00000005
+/** GMAC connects to xMII1 interface */
+#define SYS_ETH_GMUXC_GMAC0_xMII1 0x00000006
+
+/* Fields of "Datarate Status Register" */
+/** GMAC 3 datarate
+    Shows the datarate of GMAC3 */
+#define SYS_ETH_DRS_GMAC3_MASK 0x00007000
+/** field offset */
+#define SYS_ETH_DRS_GMAC3_OFFSET 12
+/** 10 MBit/s. */
+#define SYS_ETH_DRS_GMAC3_DR10 0x00000000
+/** 100 MBit/s. */
+#define SYS_ETH_DRS_GMAC3_DR100 0x00001000
+/** 1000 MBit/s. */
+#define SYS_ETH_DRS_GMAC3_DR1000 0x00002000
+/** 2500 MBit/s. */
+#define SYS_ETH_DRS_GMAC3_DR2500 0x00004000
+/** 200 MBit/s. */
+#define SYS_ETH_DRS_GMAC3_DR200 0x00005000
+/** GMAC 2 datarate
+    Shows the datarate of GMAC2 */
+#define SYS_ETH_DRS_GMAC2_MASK 0x00000700
+/** field offset */
+#define SYS_ETH_DRS_GMAC2_OFFSET 8
+/** 10 MBit/s. */
+#define SYS_ETH_DRS_GMAC2_DR10 0x00000000
+/** 100 MBit/s. */
+#define SYS_ETH_DRS_GMAC2_DR100 0x00000100
+/** 1000 MBit/s. */
+#define SYS_ETH_DRS_GMAC2_DR1000 0x00000200
+/** 2500 MBit/s. */
+#define SYS_ETH_DRS_GMAC2_DR2500 0x00000400
+/** 200 MBit/s. */
+#define SYS_ETH_DRS_GMAC2_DR200 0x00000500
+/** GMAC 1 datarate
+    Shows the datarate of GMAC1 */
+#define SYS_ETH_DRS_GMAC1_MASK 0x00000070
+/** field offset */
+#define SYS_ETH_DRS_GMAC1_OFFSET 4
+/** 10 MBit/s. */
+#define SYS_ETH_DRS_GMAC1_DR10 0x00000000
+/** 100 MBit/s. */
+#define SYS_ETH_DRS_GMAC1_DR100 0x00000010
+/** 1000 MBit/s. */
+#define SYS_ETH_DRS_GMAC1_DR1000 0x00000020
+/** 2500 MBit/s. */
+#define SYS_ETH_DRS_GMAC1_DR2500 0x00000040
+/** 200 MBit/s. */
+#define SYS_ETH_DRS_GMAC1_DR200 0x00000050
+/** GMAC 0 datarate
+    Shows the datarate of GMAC0 */
+#define SYS_ETH_DRS_GMAC0_MASK 0x00000007
+/** field offset */
+#define SYS_ETH_DRS_GMAC0_OFFSET 0
+/** 10 MBit/s. */
+#define SYS_ETH_DRS_GMAC0_DR10 0x00000000
+/** 100 MBit/s. */
+#define SYS_ETH_DRS_GMAC0_DR100 0x00000001
+/** 1000 MBit/s. */
+#define SYS_ETH_DRS_GMAC0_DR1000 0x00000002
+/** 2500 MBit/s. */
+#define SYS_ETH_DRS_GMAC0_DR2500 0x00000004
+/** 200 MBit/s. */
+#define SYS_ETH_DRS_GMAC0_DR200 0x00000005
+
+/* Fields of "SGMII Control Register" */
+/** Auto Negotiation Protocol
+    Selects the TBX/SGMII mode for the autonegotiation of the SGMII interface. */
+#define SYS_ETH_SGMIIC_ANP 0x00000002
+/* TBX Mode (IEEE 802.3 Clause 37 ANEG)
+#define SYS_ETH_SGMIIC_ANP_TBXM 0x00000000 */
+/** SGMII Mode (Cisco Aneg) */
+#define SYS_ETH_SGMIIC_ANP_SGMIIM 0x00000002
+/** Auto Negotiation MAC/PHY
+    Selects the MAC/PHY mode for the autonegotiation of the SGMII interface. */
+#define SYS_ETH_SGMIIC_ANMP 0x00000001
+/* MAC Mode
+#define SYS_ETH_SGMIIC_ANMP_MAC 0x00000000 */
+/** PHY Mode */
+#define SYS_ETH_SGMIIC_ANMP_PHY 0x00000001
+
+/*! @} */ /* SYS_ETH_REGISTER */
+
+#endif /* _sys_eth_reg_h */
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/falcon/sys_gpe_reg.h
@@ -0,0 +1,2829 @@
+/******************************************************************************
+
+                               Copyright (c) 2010
+                            Lantiq Deutschland GmbH
+
+  For licensing information, see the file 'LICENSE' in the root folder of
+  this software module.
+
+******************************************************************************/
+
+#ifndef _sys_gpe_reg_h
+#define _sys_gpe_reg_h
+
+/** \addtogroup SYS_GPE_REGISTER
+   @{
+*/
+/* access macros */
+#define sys_gpe_r32(reg) reg_r32(&sys_gpe->reg)
+#define sys_gpe_w32(val, reg) reg_w32(val, &sys_gpe->reg)
+#define sys_gpe_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &sys_gpe->reg)
+#define sys_gpe_r32_table(reg, idx) reg_r32_table(sys_gpe->reg, idx)
+#define sys_gpe_w32_table(val, reg, idx) reg_w32_table(val, sys_gpe->reg, idx)
+#define sys_gpe_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, sys_gpe->reg, idx)
+#define sys_gpe_adr_table(reg, idx) adr_table(sys_gpe->reg, idx)
+
+
+/** SYS_GPE register structure */
+struct gpon_reg_sys_gpe
+{
+   /** Clock Status Register
+       The clock status reflects the actual clocking mode as a function of the SW settings and the hardware sleep mode. */
+   unsigned int clks; /* 0x00000000 */
+   /** Clock Enable Register
+       Via this register the clocks for the domains can be enabled. */
+   unsigned int clken; /* 0x00000004 */
+   /** Clock Clear Register
+       Via this register the clocks for the domains can be disabled. */
+   unsigned int clkclr; /* 0x00000008 */
+   /** Reserved */
+   unsigned int res_0[5]; /* 0x0000000C */
+   /** Activation Status Register */
+   unsigned int acts; /* 0x00000020 */
+   /** Activation Register
+       Via this register the domains can be activated. */
+   unsigned int act; /* 0x00000024 */
+   /** Deactivation Register
+       Via this register the domains can be deactivated. */
+   unsigned int deact; /* 0x00000028 */
+   /** Reboot Trigger Register
+       Via this register the domains can be rebooted (sent through reset). */
+   unsigned int rbt; /* 0x0000002C */
+   /** Reserved */
+   unsigned int res_1[33]; /* 0x00000030 */
+   /** Power Down Configuration Register
+       Via this register the configuration is done whether in case of deactivation the power supply of the domain shall be removed. */
+   unsigned int pdcfg; /* 0x000000B4 */
+   /** Sleep Source Configuration Register
+       All sleep/wakeup conditions selected in this register contribute to the generation of the hardware sleep/wakeup request. Unselected conditions are ignored for sleep and wakeup. If no bit is selected, HW sleep is disabled. */
+   unsigned int sscfg; /* 0x000000B8 */
+   /** Sleep Source Timer Register */
+   unsigned int sst; /* 0x000000BC */
+   /** Sleep Destination Status Register
+       Shows the status of the sleep destination vector. All clock domains selected in this register will be shutoff in case of a hardware sleep request. These clocks will be automatically reenabled in case of a hardware wakeup request. */
+   unsigned int sds; /* 0x000000C0 */
+   /** Sleep Destination Set Register
+       Via this register the the domains to be shutoff in case of a hardware sleep request can be selected. */
+   unsigned int sdset; /* 0x000000C4 */
+   /** Sleep Destination Clear Register
+       Via this register the the domains to be shutoff in case of a hardware sleep request can be deselected. */
+   unsigned int sdclr; /* 0x000000C8 */
+   /** Reserved */
+   unsigned int res_2[9]; /* 0x000000CC */
+   /** IRNCS Capture Register
+       This register shows the currently active interrupt events masked with the corresponding enable bits of the IRNCSEN register. The interrupts can be acknowledged by a write operation. */
+   unsigned int irncscr; /* 0x000000F0 */
+   /** IRNCS Interrupt Control Register
+       A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
+   unsigned int irncsicr; /* 0x000000F4 */
+   /** IRNCS Interrupt Enable Register
+       This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IRNCSCR register and are not signalled via the interrupt line towards the controller. */
+   unsigned int irncsen; /* 0x000000F8 */
+   /** Reserved */
+   unsigned int res_3; /* 0x000000FC */
+};
+
+
+/* Fields of "Clock Status Register" */
+/** COP7 Clock Enable
+    Shows the clock enable bit for the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
+#define SYS_GPE_CLKS_COP7 0x80000000
+/* Disable
+#define SYS_GPE_CLKS_COP7_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_COP7_EN 0x80000000
+/** COP6 Clock Enable
+    Shows the clock enable bit for the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
+#define SYS_GPE_CLKS_COP6 0x40000000
+/* Disable
+#define SYS_GPE_CLKS_COP6_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_COP6_EN 0x40000000
+/** COP5 Clock Enable
+    Shows the clock enable bit for the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
+#define SYS_GPE_CLKS_COP5 0x20000000
+/* Disable
+#define SYS_GPE_CLKS_COP5_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_COP5_EN 0x20000000
+/** COP4 Clock Enable
+    Shows the clock enable bit for the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
+#define SYS_GPE_CLKS_COP4 0x10000000
+/* Disable
+#define SYS_GPE_CLKS_COP4_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_COP4_EN 0x10000000
+/** COP3 Clock Enable
+    Shows the clock enable bit for the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
+#define SYS_GPE_CLKS_COP3 0x08000000
+/* Disable
+#define SYS_GPE_CLKS_COP3_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_COP3_EN 0x08000000
+/** COP2 Clock Enable
+    Shows the clock enable bit for the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
+#define SYS_GPE_CLKS_COP2 0x04000000
+/* Disable
+#define SYS_GPE_CLKS_COP2_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_COP2_EN 0x04000000
+/** COP1 Clock Enable
+    Shows the clock enable bit for the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
+#define SYS_GPE_CLKS_COP1 0x02000000
+/* Disable
+#define SYS_GPE_CLKS_COP1_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_COP1_EN 0x02000000
+/** COP0 Clock Enable
+    Shows the clock enable bit for the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
+#define SYS_GPE_CLKS_COP0 0x01000000
+/* Disable
+#define SYS_GPE_CLKS_COP0_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_COP0_EN 0x01000000
+/** PE5 Clock Enable
+    Shows the clock enable bit for the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
+#define SYS_GPE_CLKS_PE5 0x00200000
+/* Disable
+#define SYS_GPE_CLKS_PE5_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_PE5_EN 0x00200000
+/** PE4 Clock Enable
+    Shows the clock enable bit for the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
+#define SYS_GPE_CLKS_PE4 0x00100000
+/* Disable
+#define SYS_GPE_CLKS_PE4_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_PE4_EN 0x00100000
+/** PE3 Clock Enable
+    Shows the clock enable bit for the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
+#define SYS_GPE_CLKS_PE3 0x00080000
+/* Disable
+#define SYS_GPE_CLKS_PE3_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_PE3_EN 0x00080000
+/** PE2 Clock Enable
+    Shows the clock enable bit for the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
+#define SYS_GPE_CLKS_PE2 0x00040000
+/* Disable
+#define SYS_GPE_CLKS_PE2_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_PE2_EN 0x00040000
+/** PE1 Clock Enable
+    Shows the clock enable bit for the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
+#define SYS_GPE_CLKS_PE1 0x00020000
+/* Disable
+#define SYS_GPE_CLKS_PE1_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_PE1_EN 0x00020000
+/** PE0 Clock Enable
+    Shows the clock enable bit for the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
+#define SYS_GPE_CLKS_PE0 0x00010000
+/* Disable
+#define SYS_GPE_CLKS_PE0_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_PE0_EN 0x00010000
+/** ARB Clock Enable
+    Shows the clock enable bit for the ARB domain. This domain contains the Arbiter. */
+#define SYS_GPE_CLKS_ARB 0x00002000
+/* Disable
+#define SYS_GPE_CLKS_ARB_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_ARB_EN 0x00002000
+/** FSQM Clock Enable
+    Shows the clock enable bit for the FSQM domain. This domain contains the FSQM. */
+#define SYS_GPE_CLKS_FSQM 0x00001000
+/* Disable
+#define SYS_GPE_CLKS_FSQM_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_FSQM_EN 0x00001000
+/** TMU Clock Enable
+    Shows the clock enable bit for the TMU domain. This domain contains the TMU. */
+#define SYS_GPE_CLKS_TMU 0x00000800
+/* Disable
+#define SYS_GPE_CLKS_TMU_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_TMU_EN 0x00000800
+/** MRG Clock Enable
+    Shows the clock enable bit for the MRG domain. This domain contains the Merger. */
+#define SYS_GPE_CLKS_MRG 0x00000400
+/* Disable
+#define SYS_GPE_CLKS_MRG_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_MRG_EN 0x00000400
+/** DISP Clock Enable
+    Shows the clock enable bit for the DISP domain. This domain contains the Dispatcher. */
+#define SYS_GPE_CLKS_DISP 0x00000200
+/* Disable
+#define SYS_GPE_CLKS_DISP_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_DISP_EN 0x00000200
+/** IQM Clock Enable
+    Shows the clock enable bit for the IQM domain. This domain contains the IQM. */
+#define SYS_GPE_CLKS_IQM 0x00000100
+/* Disable
+#define SYS_GPE_CLKS_IQM_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_IQM_EN 0x00000100
+/** CPUE Clock Enable
+    Shows the clock enable bit for the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
+#define SYS_GPE_CLKS_CPUE 0x00000080
+/* Disable
+#define SYS_GPE_CLKS_CPUE_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_CPUE_EN 0x00000080
+/** CPUI Clock Enable
+    Shows the clock enable bit for the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
+#define SYS_GPE_CLKS_CPUI 0x00000040
+/* Disable
+#define SYS_GPE_CLKS_CPUI_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_CPUI_EN 0x00000040
+/** GPONE Clock Enable
+    Shows the clock enable bit for the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
+#define SYS_GPE_CLKS_GPONE 0x00000020
+/* Disable
+#define SYS_GPE_CLKS_GPONE_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_GPONE_EN 0x00000020
+/** GPONI Clock Enable
+    Shows the clock enable bit for the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
+#define SYS_GPE_CLKS_GPONI 0x00000010
+/* Disable
+#define SYS_GPE_CLKS_GPONI_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_GPONI_EN 0x00000010
+/** LAN3 Clock Enable
+    Shows the clock enable bit for the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
+#define SYS_GPE_CLKS_LAN3 0x00000008
+/* Disable
+#define SYS_GPE_CLKS_LAN3_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_LAN3_EN 0x00000008
+/** LAN2 Clock Enable
+    Shows the clock enable bit for the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
+#define SYS_GPE_CLKS_LAN2 0x00000004
+/* Disable
+#define SYS_GPE_CLKS_LAN2_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_LAN2_EN 0x00000004
+/** LAN1 Clock Enable
+    Shows the clock enable bit for the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
+#define SYS_GPE_CLKS_LAN1 0x00000002
+/* Disable
+#define SYS_GPE_CLKS_LAN1_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_LAN1_EN 0x00000002
+/** LAN0 Clock Enable
+    Shows the clock enable bit for the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
+#define SYS_GPE_CLKS_LAN0 0x00000001
+/* Disable
+#define SYS_GPE_CLKS_LAN0_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_CLKS_LAN0_EN 0x00000001
+
+/* Fields of "Clock Enable Register" */
+/** Set Clock Enable COP7
+    Sets the clock enable bit of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
+#define SYS_GPE_CLKEN_COP7 0x80000000
+/* No-Operation
+#define SYS_GPE_CLKEN_COP7_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_COP7_SET 0x80000000
+/** Set Clock Enable COP6
+    Sets the clock enable bit of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
+#define SYS_GPE_CLKEN_COP6 0x40000000
+/* No-Operation
+#define SYS_GPE_CLKEN_COP6_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_COP6_SET 0x40000000
+/** Set Clock Enable COP5
+    Sets the clock enable bit of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
+#define SYS_GPE_CLKEN_COP5 0x20000000
+/* No-Operation
+#define SYS_GPE_CLKEN_COP5_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_COP5_SET 0x20000000
+/** Set Clock Enable COP4
+    Sets the clock enable bit of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
+#define SYS_GPE_CLKEN_COP4 0x10000000
+/* No-Operation
+#define SYS_GPE_CLKEN_COP4_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_COP4_SET 0x10000000
+/** Set Clock Enable COP3
+    Sets the clock enable bit of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
+#define SYS_GPE_CLKEN_COP3 0x08000000
+/* No-Operation
+#define SYS_GPE_CLKEN_COP3_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_COP3_SET 0x08000000
+/** Set Clock Enable COP2
+    Sets the clock enable bit of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
+#define SYS_GPE_CLKEN_COP2 0x04000000
+/* No-Operation
+#define SYS_GPE_CLKEN_COP2_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_COP2_SET 0x04000000
+/** Set Clock Enable COP1
+    Sets the clock enable bit of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
+#define SYS_GPE_CLKEN_COP1 0x02000000
+/* No-Operation
+#define SYS_GPE_CLKEN_COP1_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_COP1_SET 0x02000000
+/** Set Clock Enable COP0
+    Sets the clock enable bit of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
+#define SYS_GPE_CLKEN_COP0 0x01000000
+/* No-Operation
+#define SYS_GPE_CLKEN_COP0_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_COP0_SET 0x01000000
+/** Set Clock Enable PE5
+    Sets the clock enable bit of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
+#define SYS_GPE_CLKEN_PE5 0x00200000
+/* No-Operation
+#define SYS_GPE_CLKEN_PE5_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_PE5_SET 0x00200000
+/** Set Clock Enable PE4
+    Sets the clock enable bit of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
+#define SYS_GPE_CLKEN_PE4 0x00100000
+/* No-Operation
+#define SYS_GPE_CLKEN_PE4_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_PE4_SET 0x00100000
+/** Set Clock Enable PE3
+    Sets the clock enable bit of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
+#define SYS_GPE_CLKEN_PE3 0x00080000
+/* No-Operation
+#define SYS_GPE_CLKEN_PE3_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_PE3_SET 0x00080000
+/** Set Clock Enable PE2
+    Sets the clock enable bit of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
+#define SYS_GPE_CLKEN_PE2 0x00040000
+/* No-Operation
+#define SYS_GPE_CLKEN_PE2_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_PE2_SET 0x00040000
+/** Set Clock Enable PE1
+    Sets the clock enable bit of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
+#define SYS_GPE_CLKEN_PE1 0x00020000
+/* No-Operation
+#define SYS_GPE_CLKEN_PE1_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_PE1_SET 0x00020000
+/** Set Clock Enable PE0
+    Sets the clock enable bit of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
+#define SYS_GPE_CLKEN_PE0 0x00010000
+/* No-Operation
+#define SYS_GPE_CLKEN_PE0_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_PE0_SET 0x00010000
+/** Set Clock Enable ARB
+    Sets the clock enable bit of the ARB domain. This domain contains the Arbiter. */
+#define SYS_GPE_CLKEN_ARB 0x00002000
+/* No-Operation
+#define SYS_GPE_CLKEN_ARB_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_ARB_SET 0x00002000
+/** Set Clock Enable FSQM
+    Sets the clock enable bit of the FSQM domain. This domain contains the FSQM. */
+#define SYS_GPE_CLKEN_FSQM 0x00001000
+/* No-Operation
+#define SYS_GPE_CLKEN_FSQM_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_FSQM_SET 0x00001000
+/** Set Clock Enable TMU
+    Sets the clock enable bit of the TMU domain. This domain contains the TMU. */
+#define SYS_GPE_CLKEN_TMU 0x00000800
+/* No-Operation
+#define SYS_GPE_CLKEN_TMU_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_TMU_SET 0x00000800
+/** Set Clock Enable MRG
+    Sets the clock enable bit of the MRG domain. This domain contains the Merger. */
+#define SYS_GPE_CLKEN_MRG 0x00000400
+/* No-Operation
+#define SYS_GPE_CLKEN_MRG_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_MRG_SET 0x00000400
+/** Set Clock Enable DISP
+    Sets the clock enable bit of the DISP domain. This domain contains the Dispatcher. */
+#define SYS_GPE_CLKEN_DISP 0x00000200
+/* No-Operation
+#define SYS_GPE_CLKEN_DISP_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_DISP_SET 0x00000200
+/** Set Clock Enable IQM
+    Sets the clock enable bit of the IQM domain. This domain contains the IQM. */
+#define SYS_GPE_CLKEN_IQM 0x00000100
+/* No-Operation
+#define SYS_GPE_CLKEN_IQM_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_IQM_SET 0x00000100
+/** Set Clock Enable CPUE
+    Sets the clock enable bit of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
+#define SYS_GPE_CLKEN_CPUE 0x00000080
+/* No-Operation
+#define SYS_GPE_CLKEN_CPUE_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_CPUE_SET 0x00000080
+/** Set Clock Enable CPUI
+    Sets the clock enable bit of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
+#define SYS_GPE_CLKEN_CPUI 0x00000040
+/* No-Operation
+#define SYS_GPE_CLKEN_CPUI_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_CPUI_SET 0x00000040
+/** Set Clock Enable GPONE
+    Sets the clock enable bit of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
+#define SYS_GPE_CLKEN_GPONE 0x00000020
+/* No-Operation
+#define SYS_GPE_CLKEN_GPONE_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_GPONE_SET 0x00000020
+/** Set Clock Enable GPONI
+    Sets the clock enable bit of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
+#define SYS_GPE_CLKEN_GPONI 0x00000010
+/* No-Operation
+#define SYS_GPE_CLKEN_GPONI_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_GPONI_SET 0x00000010
+/** Set Clock Enable LAN3
+    Sets the clock enable bit of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
+#define SYS_GPE_CLKEN_LAN3 0x00000008
+/* No-Operation
+#define SYS_GPE_CLKEN_LAN3_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_LAN3_SET 0x00000008
+/** Set Clock Enable LAN2
+    Sets the clock enable bit of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
+#define SYS_GPE_CLKEN_LAN2 0x00000004
+/* No-Operation
+#define SYS_GPE_CLKEN_LAN2_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_LAN2_SET 0x00000004
+/** Set Clock Enable LAN1
+    Sets the clock enable bit of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
+#define SYS_GPE_CLKEN_LAN1 0x00000002
+/* No-Operation
+#define SYS_GPE_CLKEN_LAN1_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_LAN1_SET 0x00000002
+/** Set Clock Enable LAN0
+    Sets the clock enable bit of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
+#define SYS_GPE_CLKEN_LAN0 0x00000001
+/* No-Operation
+#define SYS_GPE_CLKEN_LAN0_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_CLKEN_LAN0_SET 0x00000001
+
+/* Fields of "Clock Clear Register" */
+/** Clear Clock Enable COP7
+    Clears the clock enable bit of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
+#define SYS_GPE_CLKCLR_COP7 0x80000000
+/* No-Operation
+#define SYS_GPE_CLKCLR_COP7_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_COP7_CLR 0x80000000
+/** Clear Clock Enable COP6
+    Clears the clock enable bit of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
+#define SYS_GPE_CLKCLR_COP6 0x40000000
+/* No-Operation
+#define SYS_GPE_CLKCLR_COP6_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_COP6_CLR 0x40000000
+/** Clear Clock Enable COP5
+    Clears the clock enable bit of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
+#define SYS_GPE_CLKCLR_COP5 0x20000000
+/* No-Operation
+#define SYS_GPE_CLKCLR_COP5_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_COP5_CLR 0x20000000
+/** Clear Clock Enable COP4
+    Clears the clock enable bit of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
+#define SYS_GPE_CLKCLR_COP4 0x10000000
+/* No-Operation
+#define SYS_GPE_CLKCLR_COP4_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_COP4_CLR 0x10000000
+/** Clear Clock Enable COP3
+    Clears the clock enable bit of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
+#define SYS_GPE_CLKCLR_COP3 0x08000000
+/* No-Operation
+#define SYS_GPE_CLKCLR_COP3_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_COP3_CLR 0x08000000
+/** Clear Clock Enable COP2
+    Clears the clock enable bit of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
+#define SYS_GPE_CLKCLR_COP2 0x04000000
+/* No-Operation
+#define SYS_GPE_CLKCLR_COP2_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_COP2_CLR 0x04000000
+/** Clear Clock Enable COP1
+    Clears the clock enable bit of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
+#define SYS_GPE_CLKCLR_COP1 0x02000000
+/* No-Operation
+#define SYS_GPE_CLKCLR_COP1_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_COP1_CLR 0x02000000
+/** Clear Clock Enable COP0
+    Clears the clock enable bit of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
+#define SYS_GPE_CLKCLR_COP0 0x01000000
+/* No-Operation
+#define SYS_GPE_CLKCLR_COP0_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_COP0_CLR 0x01000000
+/** Clear Clock Enable PE5
+    Clears the clock enable bit of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
+#define SYS_GPE_CLKCLR_PE5 0x00200000
+/* No-Operation
+#define SYS_GPE_CLKCLR_PE5_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_PE5_CLR 0x00200000
+/** Clear Clock Enable PE4
+    Clears the clock enable bit of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
+#define SYS_GPE_CLKCLR_PE4 0x00100000
+/* No-Operation
+#define SYS_GPE_CLKCLR_PE4_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_PE4_CLR 0x00100000
+/** Clear Clock Enable PE3
+    Clears the clock enable bit of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
+#define SYS_GPE_CLKCLR_PE3 0x00080000
+/* No-Operation
+#define SYS_GPE_CLKCLR_PE3_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_PE3_CLR 0x00080000
+/** Clear Clock Enable PE2
+    Clears the clock enable bit of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
+#define SYS_GPE_CLKCLR_PE2 0x00040000
+/* No-Operation
+#define SYS_GPE_CLKCLR_PE2_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_PE2_CLR 0x00040000
+/** Clear Clock Enable PE1
+    Clears the clock enable bit of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
+#define SYS_GPE_CLKCLR_PE1 0x00020000
+/* No-Operation
+#define SYS_GPE_CLKCLR_PE1_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_PE1_CLR 0x00020000
+/** Clear Clock Enable PE0
+    Clears the clock enable bit of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
+#define SYS_GPE_CLKCLR_PE0 0x00010000
+/* No-Operation
+#define SYS_GPE_CLKCLR_PE0_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_PE0_CLR 0x00010000
+/** Clear Clock Enable ARB
+    Clears the clock enable bit of the ARB domain. This domain contains the Arbiter. */
+#define SYS_GPE_CLKCLR_ARB 0x00002000
+/* No-Operation
+#define SYS_GPE_CLKCLR_ARB_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_ARB_CLR 0x00002000
+/** Clear Clock Enable FSQM
+    Clears the clock enable bit of the FSQM domain. This domain contains the FSQM. */
+#define SYS_GPE_CLKCLR_FSQM 0x00001000
+/* No-Operation
+#define SYS_GPE_CLKCLR_FSQM_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_FSQM_CLR 0x00001000
+/** Clear Clock Enable TMU
+    Clears the clock enable bit of the TMU domain. This domain contains the TMU. */
+#define SYS_GPE_CLKCLR_TMU 0x00000800
+/* No-Operation
+#define SYS_GPE_CLKCLR_TMU_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_TMU_CLR 0x00000800
+/** Clear Clock Enable MRG
+    Clears the clock enable bit of the MRG domain. This domain contains the Merger. */
+#define SYS_GPE_CLKCLR_MRG 0x00000400
+/* No-Operation
+#define SYS_GPE_CLKCLR_MRG_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_MRG_CLR 0x00000400
+/** Clear Clock Enable DISP
+    Clears the clock enable bit of the DISP domain. This domain contains the Dispatcher. */
+#define SYS_GPE_CLKCLR_DISP 0x00000200
+/* No-Operation
+#define SYS_GPE_CLKCLR_DISP_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_DISP_CLR 0x00000200
+/** Clear Clock Enable IQM
+    Clears the clock enable bit of the IQM domain. This domain contains the IQM. */
+#define SYS_GPE_CLKCLR_IQM 0x00000100
+/* No-Operation
+#define SYS_GPE_CLKCLR_IQM_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_IQM_CLR 0x00000100
+/** Clear Clock Enable CPUE
+    Clears the clock enable bit of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
+#define SYS_GPE_CLKCLR_CPUE 0x00000080
+/* No-Operation
+#define SYS_GPE_CLKCLR_CPUE_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_CPUE_CLR 0x00000080
+/** Clear Clock Enable CPUI
+    Clears the clock enable bit of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
+#define SYS_GPE_CLKCLR_CPUI 0x00000040
+/* No-Operation
+#define SYS_GPE_CLKCLR_CPUI_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_CPUI_CLR 0x00000040
+/** Clear Clock Enable GPONE
+    Clears the clock enable bit of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
+#define SYS_GPE_CLKCLR_GPONE 0x00000020
+/* No-Operation
+#define SYS_GPE_CLKCLR_GPONE_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_GPONE_CLR 0x00000020
+/** Clear Clock Enable GPONI
+    Clears the clock enable bit of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
+#define SYS_GPE_CLKCLR_GPONI 0x00000010
+/* No-Operation
+#define SYS_GPE_CLKCLR_GPONI_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_GPONI_CLR 0x00000010
+/** Clear Clock Enable LAN3
+    Clears the clock enable bit of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
+#define SYS_GPE_CLKCLR_LAN3 0x00000008
+/* No-Operation
+#define SYS_GPE_CLKCLR_LAN3_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_LAN3_CLR 0x00000008
+/** Clear Clock Enable LAN2
+    Clears the clock enable bit of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
+#define SYS_GPE_CLKCLR_LAN2 0x00000004
+/* No-Operation
+#define SYS_GPE_CLKCLR_LAN2_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_LAN2_CLR 0x00000004
+/** Clear Clock Enable LAN1
+    Clears the clock enable bit of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
+#define SYS_GPE_CLKCLR_LAN1 0x00000002
+/* No-Operation
+#define SYS_GPE_CLKCLR_LAN1_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_LAN1_CLR 0x00000002
+/** Clear Clock Enable LAN0
+    Clears the clock enable bit of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
+#define SYS_GPE_CLKCLR_LAN0 0x00000001
+/* No-Operation
+#define SYS_GPE_CLKCLR_LAN0_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_CLKCLR_LAN0_CLR 0x00000001
+
+/* Fields of "Activation Status Register" */
+/** COP7 Status
+    Shows the activation status of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
+#define SYS_GPE_ACTS_COP7 0x80000000
+/* The block is inactive.
+#define SYS_GPE_ACTS_COP7_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_COP7_ACT 0x80000000
+/** COP6 Status
+    Shows the activation status of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
+#define SYS_GPE_ACTS_COP6 0x40000000
+/* The block is inactive.
+#define SYS_GPE_ACTS_COP6_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_COP6_ACT 0x40000000
+/** COP5 Status
+    Shows the activation status of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
+#define SYS_GPE_ACTS_COP5 0x20000000
+/* The block is inactive.
+#define SYS_GPE_ACTS_COP5_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_COP5_ACT 0x20000000
+/** COP4 Status
+    Shows the activation status of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
+#define SYS_GPE_ACTS_COP4 0x10000000
+/* The block is inactive.
+#define SYS_GPE_ACTS_COP4_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_COP4_ACT 0x10000000
+/** COP3 Status
+    Shows the activation status of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
+#define SYS_GPE_ACTS_COP3 0x08000000
+/* The block is inactive.
+#define SYS_GPE_ACTS_COP3_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_COP3_ACT 0x08000000
+/** COP2 Status
+    Shows the activation status of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
+#define SYS_GPE_ACTS_COP2 0x04000000
+/* The block is inactive.
+#define SYS_GPE_ACTS_COP2_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_COP2_ACT 0x04000000
+/** COP1 Status
+    Shows the activation status of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
+#define SYS_GPE_ACTS_COP1 0x02000000
+/* The block is inactive.
+#define SYS_GPE_ACTS_COP1_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_COP1_ACT 0x02000000
+/** COP0 Status
+    Shows the activation status of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
+#define SYS_GPE_ACTS_COP0 0x01000000
+/* The block is inactive.
+#define SYS_GPE_ACTS_COP0_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_COP0_ACT 0x01000000
+/** PE5 Status
+    Shows the activation status of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
+#define SYS_GPE_ACTS_PE5 0x00200000
+/* The block is inactive.
+#define SYS_GPE_ACTS_PE5_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_PE5_ACT 0x00200000
+/** PE4 Status
+    Shows the activation status of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
+#define SYS_GPE_ACTS_PE4 0x00100000
+/* The block is inactive.
+#define SYS_GPE_ACTS_PE4_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_PE4_ACT 0x00100000
+/** PE3 Status
+    Shows the activation status of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
+#define SYS_GPE_ACTS_PE3 0x00080000
+/* The block is inactive.
+#define SYS_GPE_ACTS_PE3_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_PE3_ACT 0x00080000
+/** PE2 Status
+    Shows the activation status of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
+#define SYS_GPE_ACTS_PE2 0x00040000
+/* The block is inactive.
+#define SYS_GPE_ACTS_PE2_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_PE2_ACT 0x00040000
+/** PE1 Status
+    Shows the activation status of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
+#define SYS_GPE_ACTS_PE1 0x00020000
+/* The block is inactive.
+#define SYS_GPE_ACTS_PE1_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_PE1_ACT 0x00020000
+/** PE0 Status
+    Shows the activation status of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
+#define SYS_GPE_ACTS_PE0 0x00010000
+/* The block is inactive.
+#define SYS_GPE_ACTS_PE0_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_PE0_ACT 0x00010000
+/** ARB Status
+    Shows the activation status of the ARB domain. This domain contains the Arbiter. */
+#define SYS_GPE_ACTS_ARB 0x00002000
+/* The block is inactive.
+#define SYS_GPE_ACTS_ARB_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_ARB_ACT 0x00002000
+/** FSQM Status
+    Shows the activation status of the FSQM domain. This domain contains the FSQM. */
+#define SYS_GPE_ACTS_FSQM 0x00001000
+/* The block is inactive.
+#define SYS_GPE_ACTS_FSQM_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_FSQM_ACT 0x00001000
+/** TMU Status
+    Shows the activation status of the TMU domain. This domain contains the TMU. */
+#define SYS_GPE_ACTS_TMU 0x00000800
+/* The block is inactive.
+#define SYS_GPE_ACTS_TMU_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_TMU_ACT 0x00000800
+/** MRG Status
+    Shows the activation status of the MRG domain. This domain contains the Merger. */
+#define SYS_GPE_ACTS_MRG 0x00000400
+/* The block is inactive.
+#define SYS_GPE_ACTS_MRG_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_MRG_ACT 0x00000400
+/** DISP Status
+    Shows the activation status of the DISP domain. This domain contains the Dispatcher. */
+#define SYS_GPE_ACTS_DISP 0x00000200
+/* The block is inactive.
+#define SYS_GPE_ACTS_DISP_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_DISP_ACT 0x00000200
+/** IQM Status
+    Shows the activation status of the IQM domain. This domain contains the IQM. */
+#define SYS_GPE_ACTS_IQM 0x00000100
+/* The block is inactive.
+#define SYS_GPE_ACTS_IQM_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_IQM_ACT 0x00000100
+/** CPUE Status
+    Shows the activation status of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
+#define SYS_GPE_ACTS_CPUE 0x00000080
+/* The block is inactive.
+#define SYS_GPE_ACTS_CPUE_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_CPUE_ACT 0x00000080
+/** CPUI Status
+    Shows the activation status of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
+#define SYS_GPE_ACTS_CPUI 0x00000040
+/* The block is inactive.
+#define SYS_GPE_ACTS_CPUI_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_CPUI_ACT 0x00000040
+/** GPONE Status
+    Shows the activation status of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
+#define SYS_GPE_ACTS_GPONE 0x00000020
+/* The block is inactive.
+#define SYS_GPE_ACTS_GPONE_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_GPONE_ACT 0x00000020
+/** GPONI Status
+    Shows the activation status of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
+#define SYS_GPE_ACTS_GPONI 0x00000010
+/* The block is inactive.
+#define SYS_GPE_ACTS_GPONI_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_GPONI_ACT 0x00000010
+/** LAN3 Status
+    Shows the activation status of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
+#define SYS_GPE_ACTS_LAN3 0x00000008
+/* The block is inactive.
+#define SYS_GPE_ACTS_LAN3_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_LAN3_ACT 0x00000008
+/** LAN2 Status
+    Shows the activation status of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
+#define SYS_GPE_ACTS_LAN2 0x00000004
+/* The block is inactive.
+#define SYS_GPE_ACTS_LAN2_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_LAN2_ACT 0x00000004
+/** LAN1 Status
+    Shows the activation status of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
+#define SYS_GPE_ACTS_LAN1 0x00000002
+/* The block is inactive.
+#define SYS_GPE_ACTS_LAN1_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_LAN1_ACT 0x00000002
+/** LAN0 Status
+    Shows the activation status of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
+#define SYS_GPE_ACTS_LAN0 0x00000001
+/* The block is inactive.
+#define SYS_GPE_ACTS_LAN0_INACT 0x00000000 */
+/** The block is active. */
+#define SYS_GPE_ACTS_LAN0_ACT 0x00000001
+
+/* Fields of "Activation Register" */
+/** Activate COP7
+    Sets the activation flag of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
+#define SYS_GPE_ACT_COP7 0x80000000
+/* No-Operation
+#define SYS_GPE_ACT_COP7_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_COP7_SET 0x80000000
+/** Activate COP6
+    Sets the activation flag of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
+#define SYS_GPE_ACT_COP6 0x40000000
+/* No-Operation
+#define SYS_GPE_ACT_COP6_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_COP6_SET 0x40000000
+/** Activate COP5
+    Sets the activation flag of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
+#define SYS_GPE_ACT_COP5 0x20000000
+/* No-Operation
+#define SYS_GPE_ACT_COP5_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_COP5_SET 0x20000000
+/** Activate COP4
+    Sets the activation flag of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
+#define SYS_GPE_ACT_COP4 0x10000000
+/* No-Operation
+#define SYS_GPE_ACT_COP4_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_COP4_SET 0x10000000
+/** Activate COP3
+    Sets the activation flag of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
+#define SYS_GPE_ACT_COP3 0x08000000
+/* No-Operation
+#define SYS_GPE_ACT_COP3_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_COP3_SET 0x08000000
+/** Activate COP2
+    Sets the activation flag of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
+#define SYS_GPE_ACT_COP2 0x04000000
+/* No-Operation
+#define SYS_GPE_ACT_COP2_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_COP2_SET 0x04000000
+/** Activate COP1
+    Sets the activation flag of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
+#define SYS_GPE_ACT_COP1 0x02000000
+/* No-Operation
+#define SYS_GPE_ACT_COP1_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_COP1_SET 0x02000000
+/** Activate COP0
+    Sets the activation flag of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
+#define SYS_GPE_ACT_COP0 0x01000000
+/* No-Operation
+#define SYS_GPE_ACT_COP0_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_COP0_SET 0x01000000
+/** Activate PE5
+    Sets the activation flag of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
+#define SYS_GPE_ACT_PE5 0x00200000
+/* No-Operation
+#define SYS_GPE_ACT_PE5_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_PE5_SET 0x00200000
+/** Activate PE4
+    Sets the activation flag of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
+#define SYS_GPE_ACT_PE4 0x00100000
+/* No-Operation
+#define SYS_GPE_ACT_PE4_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_PE4_SET 0x00100000
+/** Activate PE3
+    Sets the activation flag of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
+#define SYS_GPE_ACT_PE3 0x00080000
+/* No-Operation
+#define SYS_GPE_ACT_PE3_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_PE3_SET 0x00080000
+/** Activate PE2
+    Sets the activation flag of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
+#define SYS_GPE_ACT_PE2 0x00040000
+/* No-Operation
+#define SYS_GPE_ACT_PE2_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_PE2_SET 0x00040000
+/** Activate PE1
+    Sets the activation flag of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
+#define SYS_GPE_ACT_PE1 0x00020000
+/* No-Operation
+#define SYS_GPE_ACT_PE1_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_PE1_SET 0x00020000
+/** Activate PE0
+    Sets the activation flag of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
+#define SYS_GPE_ACT_PE0 0x00010000
+/* No-Operation
+#define SYS_GPE_ACT_PE0_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_PE0_SET 0x00010000
+/** Activate ARB
+    Sets the activation flag of the ARB domain. This domain contains the Arbiter. */
+#define SYS_GPE_ACT_ARB 0x00002000
+/* No-Operation
+#define SYS_GPE_ACT_ARB_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_ARB_SET 0x00002000
+/** Activate FSQM
+    Sets the activation flag of the FSQM domain. This domain contains the FSQM. */
+#define SYS_GPE_ACT_FSQM 0x00001000
+/* No-Operation
+#define SYS_GPE_ACT_FSQM_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_FSQM_SET 0x00001000
+/** Activate TMU
+    Sets the activation flag of the TMU domain. This domain contains the TMU. */
+#define SYS_GPE_ACT_TMU 0x00000800
+/* No-Operation
+#define SYS_GPE_ACT_TMU_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_TMU_SET 0x00000800
+/** Activate MRG
+    Sets the activation flag of the MRG domain. This domain contains the Merger. */
+#define SYS_GPE_ACT_MRG 0x00000400
+/* No-Operation
+#define SYS_GPE_ACT_MRG_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_MRG_SET 0x00000400
+/** Activate DISP
+    Sets the activation flag of the DISP domain. This domain contains the Dispatcher. */
+#define SYS_GPE_ACT_DISP 0x00000200
+/* No-Operation
+#define SYS_GPE_ACT_DISP_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_DISP_SET 0x00000200
+/** Activate IQM
+    Sets the activation flag of the IQM domain. This domain contains the IQM. */
+#define SYS_GPE_ACT_IQM 0x00000100
+/* No-Operation
+#define SYS_GPE_ACT_IQM_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_IQM_SET 0x00000100
+/** Activate CPUE
+    Sets the activation flag of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
+#define SYS_GPE_ACT_CPUE 0x00000080
+/* No-Operation
+#define SYS_GPE_ACT_CPUE_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_CPUE_SET 0x00000080
+/** Activate CPUI
+    Sets the activation flag of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
+#define SYS_GPE_ACT_CPUI 0x00000040
+/* No-Operation
+#define SYS_GPE_ACT_CPUI_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_CPUI_SET 0x00000040
+/** Activate GPONE
+    Sets the activation flag of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
+#define SYS_GPE_ACT_GPONE 0x00000020
+/* No-Operation
+#define SYS_GPE_ACT_GPONE_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_GPONE_SET 0x00000020
+/** Activate GPONI
+    Sets the activation flag of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
+#define SYS_GPE_ACT_GPONI 0x00000010
+/* No-Operation
+#define SYS_GPE_ACT_GPONI_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_GPONI_SET 0x00000010
+/** Activate LAN3
+    Sets the activation flag of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
+#define SYS_GPE_ACT_LAN3 0x00000008
+/* No-Operation
+#define SYS_GPE_ACT_LAN3_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_LAN3_SET 0x00000008
+/** Activate LAN2
+    Sets the activation flag of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
+#define SYS_GPE_ACT_LAN2 0x00000004
+/* No-Operation
+#define SYS_GPE_ACT_LAN2_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_LAN2_SET 0x00000004
+/** Activate LAN1
+    Sets the activation flag of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
+#define SYS_GPE_ACT_LAN1 0x00000002
+/* No-Operation
+#define SYS_GPE_ACT_LAN1_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_LAN1_SET 0x00000002
+/** Activate LAN0
+    Sets the activation flag of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
+#define SYS_GPE_ACT_LAN0 0x00000001
+/* No-Operation
+#define SYS_GPE_ACT_LAN0_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_ACT_LAN0_SET 0x00000001
+
+/* Fields of "Deactivation Register" */
+/** Deactivate COP7
+    Clears the activation flag of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
+#define SYS_GPE_DEACT_COP7 0x80000000
+/* No-Operation
+#define SYS_GPE_DEACT_COP7_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_COP7_CLR 0x80000000
+/** Deactivate COP6
+    Clears the activation flag of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
+#define SYS_GPE_DEACT_COP6 0x40000000
+/* No-Operation
+#define SYS_GPE_DEACT_COP6_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_COP6_CLR 0x40000000
+/** Deactivate COP5
+    Clears the activation flag of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
+#define SYS_GPE_DEACT_COP5 0x20000000
+/* No-Operation
+#define SYS_GPE_DEACT_COP5_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_COP5_CLR 0x20000000
+/** Deactivate COP4
+    Clears the activation flag of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
+#define SYS_GPE_DEACT_COP4 0x10000000
+/* No-Operation
+#define SYS_GPE_DEACT_COP4_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_COP4_CLR 0x10000000
+/** Deactivate COP3
+    Clears the activation flag of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
+#define SYS_GPE_DEACT_COP3 0x08000000
+/* No-Operation
+#define SYS_GPE_DEACT_COP3_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_COP3_CLR 0x08000000
+/** Deactivate COP2
+    Clears the activation flag of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
+#define SYS_GPE_DEACT_COP2 0x04000000
+/* No-Operation
+#define SYS_GPE_DEACT_COP2_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_COP2_CLR 0x04000000
+/** Deactivate COP1
+    Clears the activation flag of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
+#define SYS_GPE_DEACT_COP1 0x02000000
+/* No-Operation
+#define SYS_GPE_DEACT_COP1_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_COP1_CLR 0x02000000
+/** Deactivate COP0
+    Clears the activation flag of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
+#define SYS_GPE_DEACT_COP0 0x01000000
+/* No-Operation
+#define SYS_GPE_DEACT_COP0_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_COP0_CLR 0x01000000
+/** Deactivate PE5
+    Clears the activation flag of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
+#define SYS_GPE_DEACT_PE5 0x00200000
+/* No-Operation
+#define SYS_GPE_DEACT_PE5_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_PE5_CLR 0x00200000
+/** Deactivate PE4
+    Clears the activation flag of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
+#define SYS_GPE_DEACT_PE4 0x00100000
+/* No-Operation
+#define SYS_GPE_DEACT_PE4_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_PE4_CLR 0x00100000
+/** Deactivate PE3
+    Clears the activation flag of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
+#define SYS_GPE_DEACT_PE3 0x00080000
+/* No-Operation
+#define SYS_GPE_DEACT_PE3_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_PE3_CLR 0x00080000
+/** Deactivate PE2
+    Clears the activation flag of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
+#define SYS_GPE_DEACT_PE2 0x00040000
+/* No-Operation
+#define SYS_GPE_DEACT_PE2_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_PE2_CLR 0x00040000
+/** Deactivate PE1
+    Clears the activation flag of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
+#define SYS_GPE_DEACT_PE1 0x00020000
+/* No-Operation
+#define SYS_GPE_DEACT_PE1_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_PE1_CLR 0x00020000
+/** Deactivate PE0
+    Clears the activation flag of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
+#define SYS_GPE_DEACT_PE0 0x00010000
+/* No-Operation
+#define SYS_GPE_DEACT_PE0_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_PE0_CLR 0x00010000
+/** Deactivate ARB
+    Clears the activation flag of the ARB domain. This domain contains the Arbiter. */
+#define SYS_GPE_DEACT_ARB 0x00002000
+/* No-Operation
+#define SYS_GPE_DEACT_ARB_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_ARB_CLR 0x00002000
+/** Deactivate FSQM
+    Clears the activation flag of the FSQM domain. This domain contains the FSQM. */
+#define SYS_GPE_DEACT_FSQM 0x00001000
+/* No-Operation
+#define SYS_GPE_DEACT_FSQM_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_FSQM_CLR 0x00001000
+/** Deactivate TMU
+    Clears the activation flag of the TMU domain. This domain contains the TMU. */
+#define SYS_GPE_DEACT_TMU 0x00000800
+/* No-Operation
+#define SYS_GPE_DEACT_TMU_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_TMU_CLR 0x00000800
+/** Deactivate MRG
+    Clears the activation flag of the MRG domain. This domain contains the Merger. */
+#define SYS_GPE_DEACT_MRG 0x00000400
+/* No-Operation
+#define SYS_GPE_DEACT_MRG_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_MRG_CLR 0x00000400
+/** Deactivate DISP
+    Clears the activation flag of the DISP domain. This domain contains the Dispatcher. */
+#define SYS_GPE_DEACT_DISP 0x00000200
+/* No-Operation
+#define SYS_GPE_DEACT_DISP_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_DISP_CLR 0x00000200
+/** Deactivate IQM
+    Clears the activation flag of the IQM domain. This domain contains the IQM. */
+#define SYS_GPE_DEACT_IQM 0x00000100
+/* No-Operation
+#define SYS_GPE_DEACT_IQM_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_IQM_CLR 0x00000100
+/** Deactivate CPUE
+    Clears the activation flag of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
+#define SYS_GPE_DEACT_CPUE 0x00000080
+/* No-Operation
+#define SYS_GPE_DEACT_CPUE_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_CPUE_CLR 0x00000080
+/** Deactivate CPUI
+    Clears the activation flag of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
+#define SYS_GPE_DEACT_CPUI 0x00000040
+/* No-Operation
+#define SYS_GPE_DEACT_CPUI_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_CPUI_CLR 0x00000040
+/** Deactivate GPONE
+    Clears the activation flag of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
+#define SYS_GPE_DEACT_GPONE 0x00000020
+/* No-Operation
+#define SYS_GPE_DEACT_GPONE_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_GPONE_CLR 0x00000020
+/** Deactivate GPONI
+    Clears the activation flag of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
+#define SYS_GPE_DEACT_GPONI 0x00000010
+/* No-Operation
+#define SYS_GPE_DEACT_GPONI_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_GPONI_CLR 0x00000010
+/** Deactivate LAN3
+    Clears the activation flag of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
+#define SYS_GPE_DEACT_LAN3 0x00000008
+/* No-Operation
+#define SYS_GPE_DEACT_LAN3_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_LAN3_CLR 0x00000008
+/** Deactivate LAN2
+    Clears the activation flag of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
+#define SYS_GPE_DEACT_LAN2 0x00000004
+/* No-Operation
+#define SYS_GPE_DEACT_LAN2_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_LAN2_CLR 0x00000004
+/** Deactivate LAN1
+    Clears the activation flag of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
+#define SYS_GPE_DEACT_LAN1 0x00000002
+/* No-Operation
+#define SYS_GPE_DEACT_LAN1_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_LAN1_CLR 0x00000002
+/** Deactivate LAN0
+    Clears the activation flag of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
+#define SYS_GPE_DEACT_LAN0 0x00000001
+/* No-Operation
+#define SYS_GPE_DEACT_LAN0_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_DEACT_LAN0_CLR 0x00000001
+
+/* Fields of "Reboot Trigger Register" */
+/** Reboot COP7
+    Triggers a reboot of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
+#define SYS_GPE_RBT_COP7 0x80000000
+/* No-Operation
+#define SYS_GPE_RBT_COP7_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_COP7_TRIG 0x80000000
+/** Reboot COP6
+    Triggers a reboot of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
+#define SYS_GPE_RBT_COP6 0x40000000
+/* No-Operation
+#define SYS_GPE_RBT_COP6_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_COP6_TRIG 0x40000000
+/** Reboot COP5
+    Triggers a reboot of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
+#define SYS_GPE_RBT_COP5 0x20000000
+/* No-Operation
+#define SYS_GPE_RBT_COP5_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_COP5_TRIG 0x20000000
+/** Reboot COP4
+    Triggers a reboot of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
+#define SYS_GPE_RBT_COP4 0x10000000
+/* No-Operation
+#define SYS_GPE_RBT_COP4_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_COP4_TRIG 0x10000000
+/** Reboot COP3
+    Triggers a reboot of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
+#define SYS_GPE_RBT_COP3 0x08000000
+/* No-Operation
+#define SYS_GPE_RBT_COP3_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_COP3_TRIG 0x08000000
+/** Reboot COP2
+    Triggers a reboot of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
+#define SYS_GPE_RBT_COP2 0x04000000
+/* No-Operation
+#define SYS_GPE_RBT_COP2_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_COP2_TRIG 0x04000000
+/** Reboot COP1
+    Triggers a reboot of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
+#define SYS_GPE_RBT_COP1 0x02000000
+/* No-Operation
+#define SYS_GPE_RBT_COP1_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_COP1_TRIG 0x02000000
+/** Reboot COP0
+    Triggers a reboot of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
+#define SYS_GPE_RBT_COP0 0x01000000
+/* No-Operation
+#define SYS_GPE_RBT_COP0_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_COP0_TRIG 0x01000000
+/** Reboot PE5
+    Triggers a reboot of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
+#define SYS_GPE_RBT_PE5 0x00200000
+/* No-Operation
+#define SYS_GPE_RBT_PE5_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_PE5_TRIG 0x00200000
+/** Reboot PE4
+    Triggers a reboot of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
+#define SYS_GPE_RBT_PE4 0x00100000
+/* No-Operation
+#define SYS_GPE_RBT_PE4_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_PE4_TRIG 0x00100000
+/** Reboot PE3
+    Triggers a reboot of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
+#define SYS_GPE_RBT_PE3 0x00080000
+/* No-Operation
+#define SYS_GPE_RBT_PE3_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_PE3_TRIG 0x00080000
+/** Reboot PE2
+    Triggers a reboot of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
+#define SYS_GPE_RBT_PE2 0x00040000
+/* No-Operation
+#define SYS_GPE_RBT_PE2_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_PE2_TRIG 0x00040000
+/** Reboot PE1
+    Triggers a reboot of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
+#define SYS_GPE_RBT_PE1 0x00020000
+/* No-Operation
+#define SYS_GPE_RBT_PE1_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_PE1_TRIG 0x00020000
+/** Reboot PE0
+    Triggers a reboot of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
+#define SYS_GPE_RBT_PE0 0x00010000
+/* No-Operation
+#define SYS_GPE_RBT_PE0_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_PE0_TRIG 0x00010000
+/** Reboot ARB
+    Triggers a reboot of the ARB domain. This domain contains the Arbiter. */
+#define SYS_GPE_RBT_ARB 0x00002000
+/* No-Operation
+#define SYS_GPE_RBT_ARB_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_ARB_TRIG 0x00002000
+/** Reboot FSQM
+    Triggers a reboot of the FSQM domain. This domain contains the FSQM. */
+#define SYS_GPE_RBT_FSQM 0x00001000
+/* No-Operation
+#define SYS_GPE_RBT_FSQM_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_FSQM_TRIG 0x00001000
+/** Reboot TMU
+    Triggers a reboot of the TMU domain. This domain contains the TMU. */
+#define SYS_GPE_RBT_TMU 0x00000800
+/* No-Operation
+#define SYS_GPE_RBT_TMU_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_TMU_TRIG 0x00000800
+/** Reboot MRG
+    Triggers a reboot of the MRG domain. This domain contains the Merger. */
+#define SYS_GPE_RBT_MRG 0x00000400
+/* No-Operation
+#define SYS_GPE_RBT_MRG_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_MRG_TRIG 0x00000400
+/** Reboot DISP
+    Triggers a reboot of the DISP domain. This domain contains the Dispatcher. */
+#define SYS_GPE_RBT_DISP 0x00000200
+/* No-Operation
+#define SYS_GPE_RBT_DISP_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_DISP_TRIG 0x00000200
+/** Reboot IQM
+    Triggers a reboot of the IQM domain. This domain contains the IQM. */
+#define SYS_GPE_RBT_IQM 0x00000100
+/* No-Operation
+#define SYS_GPE_RBT_IQM_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_IQM_TRIG 0x00000100
+/** Reboot CPUE
+    Triggers a reboot of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
+#define SYS_GPE_RBT_CPUE 0x00000080
+/* No-Operation
+#define SYS_GPE_RBT_CPUE_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_CPUE_TRIG 0x00000080
+/** Reboot CPUI
+    Triggers a reboot of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
+#define SYS_GPE_RBT_CPUI 0x00000040
+/* No-Operation
+#define SYS_GPE_RBT_CPUI_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_CPUI_TRIG 0x00000040
+/** Reboot GPONE
+    Triggers a reboot of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
+#define SYS_GPE_RBT_GPONE 0x00000020
+/* No-Operation
+#define SYS_GPE_RBT_GPONE_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_GPONE_TRIG 0x00000020
+/** Reboot GPONI
+    Triggers a reboot of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
+#define SYS_GPE_RBT_GPONI 0x00000010
+/* No-Operation
+#define SYS_GPE_RBT_GPONI_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_GPONI_TRIG 0x00000010
+/** Reboot LAN3
+    Triggers a reboot of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
+#define SYS_GPE_RBT_LAN3 0x00000008
+/* No-Operation
+#define SYS_GPE_RBT_LAN3_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_LAN3_TRIG 0x00000008
+/** Reboot LAN2
+    Triggers a reboot of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
+#define SYS_GPE_RBT_LAN2 0x00000004
+/* No-Operation
+#define SYS_GPE_RBT_LAN2_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_LAN2_TRIG 0x00000004
+/** Reboot LAN1
+    Triggers a reboot of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
+#define SYS_GPE_RBT_LAN1 0x00000002
+/* No-Operation
+#define SYS_GPE_RBT_LAN1_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_LAN1_TRIG 0x00000002
+/** Reboot LAN0
+    Triggers a reboot of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
+#define SYS_GPE_RBT_LAN0 0x00000001
+/* No-Operation
+#define SYS_GPE_RBT_LAN0_NOP 0x00000000 */
+/** Trigger */
+#define SYS_GPE_RBT_LAN0_TRIG 0x00000001
+
+/* Fields of "Power Down Configuration Register" */
+/** Enable Power Down COP7
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_COP7 0x80000000
+/* Disable
+#define SYS_GPE_PDCFG_COP7_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_COP7_EN 0x80000000
+/** Enable Power Down COP6
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_COP6 0x40000000
+/* Disable
+#define SYS_GPE_PDCFG_COP6_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_COP6_EN 0x40000000
+/** Enable Power Down COP5
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_COP5 0x20000000
+/* Disable
+#define SYS_GPE_PDCFG_COP5_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_COP5_EN 0x20000000
+/** Enable Power Down COP4
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_COP4 0x10000000
+/* Disable
+#define SYS_GPE_PDCFG_COP4_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_COP4_EN 0x10000000
+/** Enable Power Down COP3
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_COP3 0x08000000
+/* Disable
+#define SYS_GPE_PDCFG_COP3_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_COP3_EN 0x08000000
+/** Enable Power Down COP2
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_COP2 0x04000000
+/* Disable
+#define SYS_GPE_PDCFG_COP2_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_COP2_EN 0x04000000
+/** Enable Power Down COP1
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_COP1 0x02000000
+/* Disable
+#define SYS_GPE_PDCFG_COP1_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_COP1_EN 0x02000000
+/** Enable Power Down COP0
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_COP0 0x01000000
+/* Disable
+#define SYS_GPE_PDCFG_COP0_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_COP0_EN 0x01000000
+/** Enable Power Down PE5
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_PE5 0x00200000
+/* Disable
+#define SYS_GPE_PDCFG_PE5_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_PE5_EN 0x00200000
+/** Enable Power Down PE4
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_PE4 0x00100000
+/* Disable
+#define SYS_GPE_PDCFG_PE4_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_PE4_EN 0x00100000
+/** Enable Power Down PE3
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_PE3 0x00080000
+/* Disable
+#define SYS_GPE_PDCFG_PE3_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_PE3_EN 0x00080000
+/** Enable Power Down PE2
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_PE2 0x00040000
+/* Disable
+#define SYS_GPE_PDCFG_PE2_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_PE2_EN 0x00040000
+/** Enable Power Down PE1
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_PE1 0x00020000
+/* Disable
+#define SYS_GPE_PDCFG_PE1_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_PE1_EN 0x00020000
+/** Enable Power Down PE0
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_PE0 0x00010000
+/* Disable
+#define SYS_GPE_PDCFG_PE0_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_PE0_EN 0x00010000
+/** Enable Power Down ARB
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_ARB 0x00002000
+/* Disable
+#define SYS_GPE_PDCFG_ARB_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_ARB_EN 0x00002000
+/** Enable Power Down FSQM
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_FSQM 0x00001000
+/* Disable
+#define SYS_GPE_PDCFG_FSQM_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_FSQM_EN 0x00001000
+/** Enable Power Down TMU
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_TMU 0x00000800
+/* Disable
+#define SYS_GPE_PDCFG_TMU_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_TMU_EN 0x00000800
+/** Enable Power Down MRG
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_MRG 0x00000400
+/* Disable
+#define SYS_GPE_PDCFG_MRG_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_MRG_EN 0x00000400
+/** Enable Power Down DISP
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_DISP 0x00000200
+/* Disable
+#define SYS_GPE_PDCFG_DISP_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_DISP_EN 0x00000200
+/** Enable Power Down IQM
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_IQM 0x00000100
+/* Disable
+#define SYS_GPE_PDCFG_IQM_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_IQM_EN 0x00000100
+/** Enable Power Down CPUE
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_CPUE 0x00000080
+/* Disable
+#define SYS_GPE_PDCFG_CPUE_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_CPUE_EN 0x00000080
+/** Enable Power Down CPUI
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_CPUI 0x00000040
+/* Disable
+#define SYS_GPE_PDCFG_CPUI_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_CPUI_EN 0x00000040
+/** Enable Power Down GPONE
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_GPONE 0x00000020
+/* Disable
+#define SYS_GPE_PDCFG_GPONE_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_GPONE_EN 0x00000020
+/** Enable Power Down GPONI
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_GPONI 0x00000010
+/* Disable
+#define SYS_GPE_PDCFG_GPONI_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_GPONI_EN 0x00000010
+/** Enable Power Down LAN3
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_LAN3 0x00000008
+/* Disable
+#define SYS_GPE_PDCFG_LAN3_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_LAN3_EN 0x00000008
+/** Enable Power Down LAN2
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_LAN2 0x00000004
+/* Disable
+#define SYS_GPE_PDCFG_LAN2_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_LAN2_EN 0x00000004
+/** Enable Power Down LAN1
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_LAN1 0x00000002
+/* Disable
+#define SYS_GPE_PDCFG_LAN1_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_LAN1_EN 0x00000002
+/** Enable Power Down LAN0
+    Ignore this bit as power-gating is not supported for this chip. */
+#define SYS_GPE_PDCFG_LAN0 0x00000001
+/* Disable
+#define SYS_GPE_PDCFG_LAN0_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_PDCFG_LAN0_EN 0x00000001
+
+/* Fields of "Sleep Source Configuration Register" */
+/** Sleep/Wakeup Source CPU
+    Selects the CPU access signal as sleep/wakeup source. */
+#define SYS_GPE_SSCFG_CPU 0x00020000
+/* Not selected
+#define SYS_GPE_SSCFG_CPU_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SSCFG_CPU_SEL 0x00020000
+/** Sleep/Wakeup Source FSQM
+    Selects the FSQM signal as sleep/wakeup source. */
+#define SYS_GPE_SSCFG_FSQM 0x00008000
+/* Not selected
+#define SYS_GPE_SSCFG_FSQM_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SSCFG_FSQM_SEL 0x00008000
+/** Sleep/Wakeup Source GPONT
+    Selects the FIFO empty signal of the TCONT Request FIFO of port GPON as sleep/wakeup source. */
+#define SYS_GPE_SSCFG_GPONT 0x00002000
+/* Not selected
+#define SYS_GPE_SSCFG_GPONT_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SSCFG_GPONT_SEL 0x00002000
+/** Sleep/Wakeup Source GPONE
+    Selects the FIFO empty signal of the EGRESS FIFO of port GPON as sleep/wakeup source. */
+#define SYS_GPE_SSCFG_GPONE 0x00001000
+/* Not selected
+#define SYS_GPE_SSCFG_GPONE_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SSCFG_GPONE_SEL 0x00001000
+/** Sleep/Wakeup Source LAN3E
+    Selects the FIFO empty signal of the EGRESS FIFO of port LAN3 as sleep/wakeup source. */
+#define SYS_GPE_SSCFG_LAN3E 0x00000800
+/* Not selected
+#define SYS_GPE_SSCFG_LAN3E_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SSCFG_LAN3E_SEL 0x00000800
+/** Sleep/Wakeup Source LAN2E
+    Selects the FIFO empty signal of the EGRESS FIFO of port LAN2 as sleep/wakeup source. */
+#define SYS_GPE_SSCFG_LAN2E 0x00000400
+/* Not selected
+#define SYS_GPE_SSCFG_LAN2E_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SSCFG_LAN2E_SEL 0x00000400
+/** Sleep/Wakeup Source LAN1E
+    Selects the FIFO empty signal of the EGRESS FIFO of port LAN1 as sleep/wakeup source. */
+#define SYS_GPE_SSCFG_LAN1E 0x00000200
+/* Not selected
+#define SYS_GPE_SSCFG_LAN1E_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SSCFG_LAN1E_SEL 0x00000200
+/** Sleep/Wakeup Source LAN0E
+    Selects the FIFO empty signal of the EGRESS FIFO of port LAN0 as sleep/wakeup source. */
+#define SYS_GPE_SSCFG_LAN0E 0x00000100
+/* Not selected
+#define SYS_GPE_SSCFG_LAN0E_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SSCFG_LAN0E_SEL 0x00000100
+/** Sleep/Wakeup Source GPONI
+    Selects the FIFO empty signal of the INGRESS FIFO of port GPON as sleep/wakeup source. */
+#define SYS_GPE_SSCFG_GPONI 0x00000010
+/* Not selected
+#define SYS_GPE_SSCFG_GPONI_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SSCFG_GPONI_SEL 0x00000010
+/** Sleep/Wakeup Source LAN3I
+    Selects the FIFO empty signal of the INGRESS FIFO of port LAN3 as sleep/wakeup source. */
+#define SYS_GPE_SSCFG_LAN3I 0x00000008
+/* Not selected
+#define SYS_GPE_SSCFG_LAN3I_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SSCFG_LAN3I_SEL 0x00000008
+/** Sleep/Wakeup Source LAN2I
+    Selects the FIFO empty signal of the INGRESS FIFO of port LAN2 as sleep/wakeup source. */
+#define SYS_GPE_SSCFG_LAN2I 0x00000004
+/* Not selected
+#define SYS_GPE_SSCFG_LAN2I_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SSCFG_LAN2I_SEL 0x00000004
+/** Sleep/Wakeup Source LAN1I
+    Selects the FIFO empty signal of the INGRESS FIFO of port LAN1 as sleep/wakeup source. */
+#define SYS_GPE_SSCFG_LAN1I 0x00000002
+/* Not selected
+#define SYS_GPE_SSCFG_LAN1I_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SSCFG_LAN1I_SEL 0x00000002
+/** Sleep/Wakeup Source LAN0I
+    Selects the FIFO empty signal of the INGRESS FIFO of port LAN0 as sleep/wakeup source. */
+#define SYS_GPE_SSCFG_LAN0I 0x00000001
+/* Not selected
+#define SYS_GPE_SSCFG_LAN0I_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SSCFG_LAN0I_SEL 0x00000001
+
+/* Fields of "Sleep Source Timer Register" */
+/** Sleep Delay Value
+    A HW sleep request is delayed by this value multiplied by 3.2ns before it takes effect. A wakeup request is not delayed but takes effect immediately. Values lower than 256 are limited to 256. */
+#define SYS_GPE_SST_SDV_MASK 0x7FFFFFFF
+/** field offset */
+#define SYS_GPE_SST_SDV_OFFSET 0
+
+/* Fields of "Sleep Destination Status Register" */
+/** Shutoff COP7 on HW Sleep
+    If selected the domain COP7 is shutoff on a hardware sleep request. This domain contains the Coprocessor 7 of the SCE. */
+#define SYS_GPE_SDS_COP7 0x80000000
+/* Not selected
+#define SYS_GPE_SDS_COP7_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_COP7_SEL 0x80000000
+/** Shutoff COP6 on HW Sleep
+    If selected the domain COP6 is shutoff on a hardware sleep request. This domain contains the Coprocessor 6 of the SCE. */
+#define SYS_GPE_SDS_COP6 0x40000000
+/* Not selected
+#define SYS_GPE_SDS_COP6_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_COP6_SEL 0x40000000
+/** Shutoff COP5 on HW Sleep
+    If selected the domain COP5 is shutoff on a hardware sleep request. This domain contains the Coprocessor 5 of the SCE. */
+#define SYS_GPE_SDS_COP5 0x20000000
+/* Not selected
+#define SYS_GPE_SDS_COP5_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_COP5_SEL 0x20000000
+/** Shutoff COP4 on HW Sleep
+    If selected the domain COP4 is shutoff on a hardware sleep request. This domain contains the Coprocessor 4 of the SCE. */
+#define SYS_GPE_SDS_COP4 0x10000000
+/* Not selected
+#define SYS_GPE_SDS_COP4_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_COP4_SEL 0x10000000
+/** Shutoff COP3 on HW Sleep
+    If selected the domain COP3 is shutoff on a hardware sleep request. This domain contains the Coprocessor 3 of the SCE. */
+#define SYS_GPE_SDS_COP3 0x08000000
+/* Not selected
+#define SYS_GPE_SDS_COP3_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_COP3_SEL 0x08000000
+/** Shutoff COP2 on HW Sleep
+    If selected the domain COP2 is shutoff on a hardware sleep request. This domain contains the Coprocessor 2 of the SCE. */
+#define SYS_GPE_SDS_COP2 0x04000000
+/* Not selected
+#define SYS_GPE_SDS_COP2_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_COP2_SEL 0x04000000
+/** Shutoff COP1 on HW Sleep
+    If selected the domain COP1 is shutoff on a hardware sleep request. This domain contains the Coprocessor 1 of the SCE. */
+#define SYS_GPE_SDS_COP1 0x02000000
+/* Not selected
+#define SYS_GPE_SDS_COP1_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_COP1_SEL 0x02000000
+/** Shutoff COP0 on HW Sleep
+    If selected the domain COP0 is shutoff on a hardware sleep request. This domain contains the Coprocessor 0 of the SCE. */
+#define SYS_GPE_SDS_COP0 0x01000000
+/* Not selected
+#define SYS_GPE_SDS_COP0_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_COP0_SEL 0x01000000
+/** Shutoff PE5 on HW Sleep
+    If selected the domain PE5 is shutoff on a hardware sleep request. This domain contains the Processing Element 5 of the SCE. */
+#define SYS_GPE_SDS_PE5 0x00200000
+/* Not selected
+#define SYS_GPE_SDS_PE5_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_PE5_SEL 0x00200000
+/** Shutoff PE4 on HW Sleep
+    If selected the domain PE4 is shutoff on a hardware sleep request. This domain contains the Processing Element 4 of the SCE. */
+#define SYS_GPE_SDS_PE4 0x00100000
+/* Not selected
+#define SYS_GPE_SDS_PE4_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_PE4_SEL 0x00100000
+/** Shutoff PE3 on HW Sleep
+    If selected the domain PE3 is shutoff on a hardware sleep request. This domain contains the Processing Element 3 of the SCE. */
+#define SYS_GPE_SDS_PE3 0x00080000
+/* Not selected
+#define SYS_GPE_SDS_PE3_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_PE3_SEL 0x00080000
+/** Shutoff PE2 on HW Sleep
+    If selected the domain PE2 is shutoff on a hardware sleep request. This domain contains the Processing Element 2 of the SCE. */
+#define SYS_GPE_SDS_PE2 0x00040000
+/* Not selected
+#define SYS_GPE_SDS_PE2_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_PE2_SEL 0x00040000
+/** Shutoff PE1 on HW Sleep
+    If selected the domain PE1 is shutoff on a hardware sleep request. This domain contains the Processing Element 1 of the SCE. */
+#define SYS_GPE_SDS_PE1 0x00020000
+/* Not selected
+#define SYS_GPE_SDS_PE1_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_PE1_SEL 0x00020000
+/** Shutoff PE0 on HW Sleep
+    If selected the domain PE0 is shutoff on a hardware sleep request. This domain contains the Processing Element 0 of the SCE. */
+#define SYS_GPE_SDS_PE0 0x00010000
+/* Not selected
+#define SYS_GPE_SDS_PE0_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_PE0_SEL 0x00010000
+/** Shutoff ARB on HW Sleep
+    If selected the domain ARB is shutoff on a hardware sleep request. This domain contains the Arbiter. */
+#define SYS_GPE_SDS_ARB 0x00002000
+/* Not selected
+#define SYS_GPE_SDS_ARB_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_ARB_SEL 0x00002000
+/** Shutoff FSQM on HW Sleep
+    If selected the domain FSQM is shutoff on a hardware sleep request. This domain contains the FSQM. */
+#define SYS_GPE_SDS_FSQM 0x00001000
+/* Not selected
+#define SYS_GPE_SDS_FSQM_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_FSQM_SEL 0x00001000
+/** Shutoff TMU on HW Sleep
+    If selected the domain TMU is shutoff on a hardware sleep request. This domain contains the TMU. */
+#define SYS_GPE_SDS_TMU 0x00000800
+/* Not selected
+#define SYS_GPE_SDS_TMU_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_TMU_SEL 0x00000800
+/** Shutoff MRG on HW Sleep
+    If selected the domain MRG is shutoff on a hardware sleep request. This domain contains the Merger. */
+#define SYS_GPE_SDS_MRG 0x00000400
+/* Not selected
+#define SYS_GPE_SDS_MRG_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_MRG_SEL 0x00000400
+/** Shutoff DISP on HW Sleep
+    If selected the domain DISP is shutoff on a hardware sleep request. This domain contains the Dispatcher. */
+#define SYS_GPE_SDS_DISP 0x00000200
+/* Not selected
+#define SYS_GPE_SDS_DISP_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_DISP_SEL 0x00000200
+/** Shutoff IQM on HW Sleep
+    If selected the domain IQM is shutoff on a hardware sleep request. This domain contains the IQM. */
+#define SYS_GPE_SDS_IQM 0x00000100
+/* Not selected
+#define SYS_GPE_SDS_IQM_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_IQM_SEL 0x00000100
+/** Shutoff CPUE on HW Sleep
+    If selected the domain CPUE is shutoff on a hardware sleep request. This domain contains all parts related to the CPU EGRESS interface. */
+#define SYS_GPE_SDS_CPUE 0x00000080
+/* Not selected
+#define SYS_GPE_SDS_CPUE_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_CPUE_SEL 0x00000080
+/** Shutoff CPUI on HW Sleep
+    If selected the domain CPUI is shutoff on a hardware sleep request. This domain contains all parts related to the CPU INGRESS interface. */
+#define SYS_GPE_SDS_CPUI 0x00000040
+/* Not selected
+#define SYS_GPE_SDS_CPUI_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_CPUI_SEL 0x00000040
+/** Shutoff GPONE on HW Sleep
+    If selected the domain GPONE is shutoff on a hardware sleep request. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
+#define SYS_GPE_SDS_GPONE 0x00000020
+/* Not selected
+#define SYS_GPE_SDS_GPONE_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_GPONE_SEL 0x00000020
+/** Shutoff GPONI on HW Sleep
+    If selected the domain GPONI is shutoff on a hardware sleep request. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
+#define SYS_GPE_SDS_GPONI 0x00000010
+/* Not selected
+#define SYS_GPE_SDS_GPONI_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_GPONI_SEL 0x00000010
+/** Shutoff LAN3 on HW Sleep
+    If selected the domain LAN3 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN3 interface. */
+#define SYS_GPE_SDS_LAN3 0x00000008
+/* Not selected
+#define SYS_GPE_SDS_LAN3_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_LAN3_SEL 0x00000008
+/** Shutoff LAN2 on HW Sleep
+    If selected the domain LAN2 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN2 interface. */
+#define SYS_GPE_SDS_LAN2 0x00000004
+/* Not selected
+#define SYS_GPE_SDS_LAN2_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_LAN2_SEL 0x00000004
+/** Shutoff LAN1 on HW Sleep
+    If selected the domain LAN1 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN1 interface. */
+#define SYS_GPE_SDS_LAN1 0x00000002
+/* Not selected
+#define SYS_GPE_SDS_LAN1_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_LAN1_SEL 0x00000002
+/** Shutoff LAN0 on HW Sleep
+    If selected the domain LAN0 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN0 interface. */
+#define SYS_GPE_SDS_LAN0 0x00000001
+/* Not selected
+#define SYS_GPE_SDS_LAN0_NSEL 0x00000000 */
+/** Selected */
+#define SYS_GPE_SDS_LAN0_SEL 0x00000001
+
+/* Fields of "Sleep Destination Set Register" */
+/** Set Sleep Selection COP7
+    Sets the selection bit for domain COP7This domain contains the Coprocessor 7 of the SCE. */
+#define SYS_GPE_SDSET_COP7 0x80000000
+/* No-Operation
+#define SYS_GPE_SDSET_COP7_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_COP7_SET 0x80000000
+/** Set Sleep Selection COP6
+    Sets the selection bit for domain COP6This domain contains the Coprocessor 6 of the SCE. */
+#define SYS_GPE_SDSET_COP6 0x40000000
+/* No-Operation
+#define SYS_GPE_SDSET_COP6_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_COP6_SET 0x40000000
+/** Set Sleep Selection COP5
+    Sets the selection bit for domain COP5This domain contains the Coprocessor 5 of the SCE. */
+#define SYS_GPE_SDSET_COP5 0x20000000
+/* No-Operation
+#define SYS_GPE_SDSET_COP5_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_COP5_SET 0x20000000
+/** Set Sleep Selection COP4
+    Sets the selection bit for domain COP4This domain contains the Coprocessor 4 of the SCE. */
+#define SYS_GPE_SDSET_COP4 0x10000000
+/* No-Operation
+#define SYS_GPE_SDSET_COP4_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_COP4_SET 0x10000000
+/** Set Sleep Selection COP3
+    Sets the selection bit for domain COP3This domain contains the Coprocessor 3 of the SCE. */
+#define SYS_GPE_SDSET_COP3 0x08000000
+/* No-Operation
+#define SYS_GPE_SDSET_COP3_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_COP3_SET 0x08000000
+/** Set Sleep Selection COP2
+    Sets the selection bit for domain COP2This domain contains the Coprocessor 2 of the SCE. */
+#define SYS_GPE_SDSET_COP2 0x04000000
+/* No-Operation
+#define SYS_GPE_SDSET_COP2_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_COP2_SET 0x04000000
+/** Set Sleep Selection COP1
+    Sets the selection bit for domain COP1This domain contains the Coprocessor 1 of the SCE. */
+#define SYS_GPE_SDSET_COP1 0x02000000
+/* No-Operation
+#define SYS_GPE_SDSET_COP1_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_COP1_SET 0x02000000
+/** Set Sleep Selection COP0
+    Sets the selection bit for domain COP0This domain contains the Coprocessor 0 of the SCE. */
+#define SYS_GPE_SDSET_COP0 0x01000000
+/* No-Operation
+#define SYS_GPE_SDSET_COP0_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_COP0_SET 0x01000000
+/** Set Sleep Selection PE5
+    Sets the selection bit for domain PE5This domain contains the Processing Element 5 of the SCE. */
+#define SYS_GPE_SDSET_PE5 0x00200000
+/* No-Operation
+#define SYS_GPE_SDSET_PE5_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_PE5_SET 0x00200000
+/** Set Sleep Selection PE4
+    Sets the selection bit for domain PE4This domain contains the Processing Element 4 of the SCE. */
+#define SYS_GPE_SDSET_PE4 0x00100000
+/* No-Operation
+#define SYS_GPE_SDSET_PE4_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_PE4_SET 0x00100000
+/** Set Sleep Selection PE3
+    Sets the selection bit for domain PE3This domain contains the Processing Element 3 of the SCE. */
+#define SYS_GPE_SDSET_PE3 0x00080000
+/* No-Operation
+#define SYS_GPE_SDSET_PE3_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_PE3_SET 0x00080000
+/** Set Sleep Selection PE2
+    Sets the selection bit for domain PE2This domain contains the Processing Element 2 of the SCE. */
+#define SYS_GPE_SDSET_PE2 0x00040000
+/* No-Operation
+#define SYS_GPE_SDSET_PE2_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_PE2_SET 0x00040000
+/** Set Sleep Selection PE1
+    Sets the selection bit for domain PE1This domain contains the Processing Element 1 of the SCE. */
+#define SYS_GPE_SDSET_PE1 0x00020000
+/* No-Operation
+#define SYS_GPE_SDSET_PE1_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_PE1_SET 0x00020000
+/** Set Sleep Selection PE0
+    Sets the selection bit for domain PE0This domain contains the Processing Element 0 of the SCE. */
+#define SYS_GPE_SDSET_PE0 0x00010000
+/* No-Operation
+#define SYS_GPE_SDSET_PE0_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_PE0_SET 0x00010000
+/** Set Sleep Selection ARB
+    Sets the selection bit for domain ARBThis domain contains the Arbiter. */
+#define SYS_GPE_SDSET_ARB 0x00002000
+/* No-Operation
+#define SYS_GPE_SDSET_ARB_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_ARB_SET 0x00002000
+/** Set Sleep Selection FSQM
+    Sets the selection bit for domain FSQMThis domain contains the FSQM. */
+#define SYS_GPE_SDSET_FSQM 0x00001000
+/* No-Operation
+#define SYS_GPE_SDSET_FSQM_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_FSQM_SET 0x00001000
+/** Set Sleep Selection TMU
+    Sets the selection bit for domain TMUThis domain contains the TMU. */
+#define SYS_GPE_SDSET_TMU 0x00000800
+/* No-Operation
+#define SYS_GPE_SDSET_TMU_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_TMU_SET 0x00000800
+/** Set Sleep Selection MRG
+    Sets the selection bit for domain MRGThis domain contains the Merger. */
+#define SYS_GPE_SDSET_MRG 0x00000400
+/* No-Operation
+#define SYS_GPE_SDSET_MRG_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_MRG_SET 0x00000400
+/** Set Sleep Selection DISP
+    Sets the selection bit for domain DISPThis domain contains the Dispatcher. */
+#define SYS_GPE_SDSET_DISP 0x00000200
+/* No-Operation
+#define SYS_GPE_SDSET_DISP_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_DISP_SET 0x00000200
+/** Set Sleep Selection IQM
+    Sets the selection bit for domain IQMThis domain contains the IQM. */
+#define SYS_GPE_SDSET_IQM 0x00000100
+/* No-Operation
+#define SYS_GPE_SDSET_IQM_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_IQM_SET 0x00000100
+/** Set Sleep Selection CPUE
+    Sets the selection bit for domain CPUEThis domain contains all parts related to the CPU EGRESS interface. */
+#define SYS_GPE_SDSET_CPUE 0x00000080
+/* No-Operation
+#define SYS_GPE_SDSET_CPUE_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_CPUE_SET 0x00000080
+/** Set Sleep Selection CPUI
+    Sets the selection bit for domain CPUIThis domain contains all parts related to the CPU INGRESS interface. */
+#define SYS_GPE_SDSET_CPUI 0x00000040
+/* No-Operation
+#define SYS_GPE_SDSET_CPUI_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_CPUI_SET 0x00000040
+/** Set Sleep Selection GPONE
+    Sets the selection bit for domain GPONEThis domain contains all parts related to the GPON (GTC) EGRESS interface. */
+#define SYS_GPE_SDSET_GPONE 0x00000020
+/* No-Operation
+#define SYS_GPE_SDSET_GPONE_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_GPONE_SET 0x00000020
+/** Set Sleep Selection GPONI
+    Sets the selection bit for domain GPONIThis domain contains all parts related to the GPON (GTC) INGRESS interface. */
+#define SYS_GPE_SDSET_GPONI 0x00000010
+/* No-Operation
+#define SYS_GPE_SDSET_GPONI_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_GPONI_SET 0x00000010
+/** Set Sleep Selection LAN3
+    Sets the selection bit for domain LAN3This domain contains all parts related to the LAN3 interface. */
+#define SYS_GPE_SDSET_LAN3 0x00000008
+/* No-Operation
+#define SYS_GPE_SDSET_LAN3_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_LAN3_SET 0x00000008
+/** Set Sleep Selection LAN2
+    Sets the selection bit for domain LAN2This domain contains all parts related to the LAN2 interface. */
+#define SYS_GPE_SDSET_LAN2 0x00000004
+/* No-Operation
+#define SYS_GPE_SDSET_LAN2_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_LAN2_SET 0x00000004
+/** Set Sleep Selection LAN1
+    Sets the selection bit for domain LAN1This domain contains all parts related to the LAN1 interface. */
+#define SYS_GPE_SDSET_LAN1 0x00000002
+/* No-Operation
+#define SYS_GPE_SDSET_LAN1_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_LAN1_SET 0x00000002
+/** Set Sleep Selection LAN0
+    Sets the selection bit for domain LAN0This domain contains all parts related to the LAN0 interface. */
+#define SYS_GPE_SDSET_LAN0 0x00000001
+/* No-Operation
+#define SYS_GPE_SDSET_LAN0_NOP 0x00000000 */
+/** Set */
+#define SYS_GPE_SDSET_LAN0_SET 0x00000001
+
+/* Fields of "Sleep Destination Clear Register" */
+/** Clear Sleep Selection COP7
+    Clears the selection bit for domain COP7This domain contains the Coprocessor 7 of the SCE. */
+#define SYS_GPE_SDCLR_COP7 0x80000000
+/* No-Operation
+#define SYS_GPE_SDCLR_COP7_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_COP7_CLR 0x80000000
+/** Clear Sleep Selection COP6
+    Clears the selection bit for domain COP6This domain contains the Coprocessor 6 of the SCE. */
+#define SYS_GPE_SDCLR_COP6 0x40000000
+/* No-Operation
+#define SYS_GPE_SDCLR_COP6_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_COP6_CLR 0x40000000
+/** Clear Sleep Selection COP5
+    Clears the selection bit for domain COP5This domain contains the Coprocessor 5 of the SCE. */
+#define SYS_GPE_SDCLR_COP5 0x20000000
+/* No-Operation
+#define SYS_GPE_SDCLR_COP5_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_COP5_CLR 0x20000000
+/** Clear Sleep Selection COP4
+    Clears the selection bit for domain COP4This domain contains the Coprocessor 4 of the SCE. */
+#define SYS_GPE_SDCLR_COP4 0x10000000
+/* No-Operation
+#define SYS_GPE_SDCLR_COP4_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_COP4_CLR 0x10000000
+/** Clear Sleep Selection COP3
+    Clears the selection bit for domain COP3This domain contains the Coprocessor 3 of the SCE. */
+#define SYS_GPE_SDCLR_COP3 0x08000000
+/* No-Operation
+#define SYS_GPE_SDCLR_COP3_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_COP3_CLR 0x08000000
+/** Clear Sleep Selection COP2
+    Clears the selection bit for domain COP2This domain contains the Coprocessor 2 of the SCE. */
+#define SYS_GPE_SDCLR_COP2 0x04000000
+/* No-Operation
+#define SYS_GPE_SDCLR_COP2_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_COP2_CLR 0x04000000
+/** Clear Sleep Selection COP1
+    Clears the selection bit for domain COP1This domain contains the Coprocessor 1 of the SCE. */
+#define SYS_GPE_SDCLR_COP1 0x02000000
+/* No-Operation
+#define SYS_GPE_SDCLR_COP1_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_COP1_CLR 0x02000000
+/** Clear Sleep Selection COP0
+    Clears the selection bit for domain COP0This domain contains the Coprocessor 0 of the SCE. */
+#define SYS_GPE_SDCLR_COP0 0x01000000
+/* No-Operation
+#define SYS_GPE_SDCLR_COP0_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_COP0_CLR 0x01000000
+/** Clear Sleep Selection PE5
+    Clears the selection bit for domain PE5This domain contains the Processing Element 5 of the SCE. */
+#define SYS_GPE_SDCLR_PE5 0x00200000
+/* No-Operation
+#define SYS_GPE_SDCLR_PE5_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_PE5_CLR 0x00200000
+/** Clear Sleep Selection PE4
+    Clears the selection bit for domain PE4This domain contains the Processing Element 4 of the SCE. */
+#define SYS_GPE_SDCLR_PE4 0x00100000
+/* No-Operation
+#define SYS_GPE_SDCLR_PE4_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_PE4_CLR 0x00100000
+/** Clear Sleep Selection PE3
+    Clears the selection bit for domain PE3This domain contains the Processing Element 3 of the SCE. */
+#define SYS_GPE_SDCLR_PE3 0x00080000
+/* No-Operation
+#define SYS_GPE_SDCLR_PE3_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_PE3_CLR 0x00080000
+/** Clear Sleep Selection PE2
+    Clears the selection bit for domain PE2This domain contains the Processing Element 2 of the SCE. */
+#define SYS_GPE_SDCLR_PE2 0x00040000
+/* No-Operation
+#define SYS_GPE_SDCLR_PE2_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_PE2_CLR 0x00040000
+/** Clear Sleep Selection PE1
+    Clears the selection bit for domain PE1This domain contains the Processing Element 1 of the SCE. */
+#define SYS_GPE_SDCLR_PE1 0x00020000
+/* No-Operation
+#define SYS_GPE_SDCLR_PE1_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_PE1_CLR 0x00020000
+/** Clear Sleep Selection PE0
+    Clears the selection bit for domain PE0This domain contains the Processing Element 0 of the SCE. */
+#define SYS_GPE_SDCLR_PE0 0x00010000
+/* No-Operation
+#define SYS_GPE_SDCLR_PE0_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_PE0_CLR 0x00010000
+/** Clear Sleep Selection ARB
+    Clears the selection bit for domain ARBThis domain contains the Arbiter. */
+#define SYS_GPE_SDCLR_ARB 0x00002000
+/* No-Operation
+#define SYS_GPE_SDCLR_ARB_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_ARB_CLR 0x00002000
+/** Clear Sleep Selection FSQM
+    Clears the selection bit for domain FSQMThis domain contains the FSQM. */
+#define SYS_GPE_SDCLR_FSQM 0x00001000
+/* No-Operation
+#define SYS_GPE_SDCLR_FSQM_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_FSQM_CLR 0x00001000
+/** Clear Sleep Selection TMU
+    Clears the selection bit for domain TMUThis domain contains the TMU. */
+#define SYS_GPE_SDCLR_TMU 0x00000800
+/* No-Operation
+#define SYS_GPE_SDCLR_TMU_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_TMU_CLR 0x00000800
+/** Clear Sleep Selection MRG
+    Clears the selection bit for domain MRGThis domain contains the Merger. */
+#define SYS_GPE_SDCLR_MRG 0x00000400
+/* No-Operation
+#define SYS_GPE_SDCLR_MRG_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_MRG_CLR 0x00000400
+/** Clear Sleep Selection DISP
+    Clears the selection bit for domain DISPThis domain contains the Dispatcher. */
+#define SYS_GPE_SDCLR_DISP 0x00000200
+/* No-Operation
+#define SYS_GPE_SDCLR_DISP_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_DISP_CLR 0x00000200
+/** Clear Sleep Selection IQM
+    Clears the selection bit for domain IQMThis domain contains the IQM. */
+#define SYS_GPE_SDCLR_IQM 0x00000100
+/* No-Operation
+#define SYS_GPE_SDCLR_IQM_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_IQM_CLR 0x00000100
+/** Clear Sleep Selection CPUE
+    Clears the selection bit for domain CPUEThis domain contains all parts related to the CPU EGRESS interface. */
+#define SYS_GPE_SDCLR_CPUE 0x00000080
+/* No-Operation
+#define SYS_GPE_SDCLR_CPUE_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_CPUE_CLR 0x00000080
+/** Clear Sleep Selection CPUI
+    Clears the selection bit for domain CPUIThis domain contains all parts related to the CPU INGRESS interface. */
+#define SYS_GPE_SDCLR_CPUI 0x00000040
+/* No-Operation
+#define SYS_GPE_SDCLR_CPUI_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_CPUI_CLR 0x00000040
+/** Clear Sleep Selection GPONE
+    Clears the selection bit for domain GPONEThis domain contains all parts related to the GPON (GTC) EGRESS interface. */
+#define SYS_GPE_SDCLR_GPONE 0x00000020
+/* No-Operation
+#define SYS_GPE_SDCLR_GPONE_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_GPONE_CLR 0x00000020
+/** Clear Sleep Selection GPONI
+    Clears the selection bit for domain GPONIThis domain contains all parts related to the GPON (GTC) INGRESS interface. */
+#define SYS_GPE_SDCLR_GPONI 0x00000010
+/* No-Operation
+#define SYS_GPE_SDCLR_GPONI_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_GPONI_CLR 0x00000010
+/** Clear Sleep Selection LAN3
+    Clears the selection bit for domain LAN3This domain contains all parts related to the LAN3 interface. */
+#define SYS_GPE_SDCLR_LAN3 0x00000008
+/* No-Operation
+#define SYS_GPE_SDCLR_LAN3_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_LAN3_CLR 0x00000008
+/** Clear Sleep Selection LAN2
+    Clears the selection bit for domain LAN2This domain contains all parts related to the LAN2 interface. */
+#define SYS_GPE_SDCLR_LAN2 0x00000004
+/* No-Operation
+#define SYS_GPE_SDCLR_LAN2_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_LAN2_CLR 0x00000004
+/** Clear Sleep Selection LAN1
+    Clears the selection bit for domain LAN1This domain contains all parts related to the LAN1 interface. */
+#define SYS_GPE_SDCLR_LAN1 0x00000002
+/* No-Operation
+#define SYS_GPE_SDCLR_LAN1_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_LAN1_CLR 0x00000002
+/** Clear Sleep Selection LAN0
+    Clears the selection bit for domain LAN0This domain contains all parts related to the LAN0 interface. */
+#define SYS_GPE_SDCLR_LAN0 0x00000001
+/* No-Operation
+#define SYS_GPE_SDCLR_LAN0_NOP 0x00000000 */
+/** Clear */
+#define SYS_GPE_SDCLR_LAN0_CLR 0x00000001
+
+/* Fields of "IRNCS Capture Register" */
+/** FSQM wakeup request
+    The FSQM submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define SYS_GPE_IRNCSCR_FSQMWR 0x80000000
+/* Nothing
+#define SYS_GPE_IRNCSCR_FSQMWR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define SYS_GPE_IRNCSCR_FSQMWR_INTACK 0x80000000
+/** Read: Interrupt occurred. */
+#define SYS_GPE_IRNCSCR_FSQMWR_INTOCC 0x80000000
+/** GPONT wakeup request
+    The TCONT Request FIFO of port GPON submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define SYS_GPE_IRNCSCR_GPONTWR 0x20000000
+/* Nothing
+#define SYS_GPE_IRNCSCR_GPONTWR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define SYS_GPE_IRNCSCR_GPONTWR_INTACK 0x20000000
+/** Read: Interrupt occurred. */
+#define SYS_GPE_IRNCSCR_GPONTWR_INTOCC 0x20000000
+/** GPONE wakeup request
+    The EGRESS FIFO of port GPON submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define SYS_GPE_IRNCSCR_GPONEWR 0x10000000
+/* Nothing
+#define SYS_GPE_IRNCSCR_GPONEWR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define SYS_GPE_IRNCSCR_GPONEWR_INTACK 0x10000000
+/** Read: Interrupt occurred. */
+#define SYS_GPE_IRNCSCR_GPONEWR_INTOCC 0x10000000
+/** LAN3E wakeup request
+    The EGRESS FIFO of port LAN3 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define SYS_GPE_IRNCSCR_LAN3EWR 0x08000000
+/* Nothing
+#define SYS_GPE_IRNCSCR_LAN3EWR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define SYS_GPE_IRNCSCR_LAN3EWR_INTACK 0x08000000
+/** Read: Interrupt occurred. */
+#define SYS_GPE_IRNCSCR_LAN3EWR_INTOCC 0x08000000
+/** LAN2E wakeup requestThe ENGRESS FIFO of port LAN2 submitted a wakeup request.
+    This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define SYS_GPE_IRNCSCR_LAN2EWR 0x04000000
+/* Nothing
+#define SYS_GPE_IRNCSCR_LAN2EWR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define SYS_GPE_IRNCSCR_LAN2EWR_INTACK 0x04000000
+/** Read: Interrupt occurred. */
+#define SYS_GPE_IRNCSCR_LAN2EWR_INTOCC 0x04000000
+/** LAN1E wakeup request
+    The EGRESS FIFO of port LAN1 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define SYS_GPE_IRNCSCR_LAN1EWR 0x02000000
+/* Nothing
+#define SYS_GPE_IRNCSCR_LAN1EWR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define SYS_GPE_IRNCSCR_LAN1EWR_INTACK 0x02000000
+/** Read: Interrupt occurred. */
+#define SYS_GPE_IRNCSCR_LAN1EWR_INTOCC 0x02000000
+/** LAN0E wakeup request
+    The EGRESS FIFO of port LAN0 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define SYS_GPE_IRNCSCR_LAN0EWR 0x01000000
+/* Nothing
+#define SYS_GPE_IRNCSCR_LAN0EWR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define SYS_GPE_IRNCSCR_LAN0EWR_INTACK 0x01000000
+/** Read: Interrupt occurred. */
+#define SYS_GPE_IRNCSCR_LAN0EWR_INTOCC 0x01000000
+/** GPONI wakeup request
+    The INGRESS FIFO of port GPON submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define SYS_GPE_IRNCSCR_GPONIWR 0x00100000
+/* Nothing
+#define SYS_GPE_IRNCSCR_GPONIWR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define SYS_GPE_IRNCSCR_GPONIWR_INTACK 0x00100000
+/** Read: Interrupt occurred. */
+#define SYS_GPE_IRNCSCR_GPONIWR_INTOCC 0x00100000
+/** LAN3I wakeup request
+    The INGRESS FIFO of port LAN3 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define SYS_GPE_IRNCSCR_LAN3IWR 0x00080000
+/* Nothing
+#define SYS_GPE_IRNCSCR_LAN3IWR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define SYS_GPE_IRNCSCR_LAN3IWR_INTACK 0x00080000
+/** Read: Interrupt occurred. */
+#define SYS_GPE_IRNCSCR_LAN3IWR_INTOCC 0x00080000
+/** LAN2I wakeup request
+    The INGRESS FIFO of port LAN2 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define SYS_GPE_IRNCSCR_LAN2IWR 0x00040000
+/* Nothing
+#define SYS_GPE_IRNCSCR_LAN2IWR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define SYS_GPE_IRNCSCR_LAN2IWR_INTACK 0x00040000
+/** Read: Interrupt occurred. */
+#define SYS_GPE_IRNCSCR_LAN2IWR_INTOCC 0x00040000
+/** LAN1I wakeup request
+    The INGRESS FIFO of port LAN1 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define SYS_GPE_IRNCSCR_LAN1IWR 0x00020000
+/* Nothing
+#define SYS_GPE_IRNCSCR_LAN1IWR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define SYS_GPE_IRNCSCR_LAN1IWR_INTACK 0x00020000
+/** Read: Interrupt occurred. */
+#define SYS_GPE_IRNCSCR_LAN1IWR_INTOCC 0x00020000
+/** LAN0I wakeup request
+    The INGRESS FIFO of port LAN0 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define SYS_GPE_IRNCSCR_LAN0IWR 0x00010000
+/* Nothing
+#define SYS_GPE_IRNCSCR_LAN0IWR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define SYS_GPE_IRNCSCR_LAN0IWR_INTACK 0x00010000
+/** Read: Interrupt occurred. */
+#define SYS_GPE_IRNCSCR_LAN0IWR_INTOCC 0x00010000
+/** FSQM sleep request
+    The FSQM submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define SYS_GPE_IRNCSCR_FSQMSR 0x00008000
+/* Nothing
+#define SYS_GPE_IRNCSCR_FSQMSR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define SYS_GPE_IRNCSCR_FSQMSR_INTACK 0x00008000
+/** Read: Interrupt occurred. */
+#define SYS_GPE_IRNCSCR_FSQMSR_INTOCC 0x00008000
+/** GPONT sleep request
+    The TCONT Request FIFO of port GPON submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define SYS_GPE_IRNCSCR_GPONTSR 0x00002000
+/* Nothing
+#define SYS_GPE_IRNCSCR_GPONTSR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define SYS_GPE_IRNCSCR_GPONTSR_INTACK 0x00002000
+/** Read: Interrupt occurred. */
+#define SYS_GPE_IRNCSCR_GPONTSR_INTOCC 0x00002000
+/** GPONE sleep request
+    The EGRESS FIFO of port GPON submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define SYS_GPE_IRNCSCR_GPONESR 0x00001000
+/* Nothing
+#define SYS_GPE_IRNCSCR_GPONESR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define SYS_GPE_IRNCSCR_GPONESR_INTACK 0x00001000
+/** Read: Interrupt occurred. */
+#define SYS_GPE_IRNCSCR_GPONESR_INTOCC 0x00001000
+/** LAN3E sleep request
+    The EGRESS FIFO of port LAN3 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define SYS_GPE_IRNCSCR_LAN3ESR 0x00000800
+/* Nothing
+#define SYS_GPE_IRNCSCR_LAN3ESR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define SYS_GPE_IRNCSCR_LAN3ESR_INTACK 0x00000800
+/** Read: Interrupt occurred. */
+#define SYS_GPE_IRNCSCR_LAN3ESR_INTOCC 0x00000800
+/** LAN2E sleep requestThe ENGRESS FIFO of port LAN2 submitted a sleep request.
+    This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define SYS_GPE_IRNCSCR_LAN2ESR 0x00000400
+/* Nothing
+#define SYS_GPE_IRNCSCR_LAN2ESR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define SYS_GPE_IRNCSCR_LAN2ESR_INTACK 0x00000400
+/** Read: Interrupt occurred. */
+#define SYS_GPE_IRNCSCR_LAN2ESR_INTOCC 0x00000400
+/** LAN1E sleep request
+    The EGRESS FIFO of port LAN1 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define SYS_GPE_IRNCSCR_LAN1ESR 0x00000200
+/* Nothing
+#define SYS_GPE_IRNCSCR_LAN1ESR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define SYS_GPE_IRNCSCR_LAN1ESR_INTACK 0x00000200
+/** Read: Interrupt occurred. */
+#define SYS_GPE_IRNCSCR_LAN1ESR_INTOCC 0x00000200
+/** LAN0E sleep request
+    The EGRESS FIFO of port LAN0 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define SYS_GPE_IRNCSCR_LAN0ESR 0x00000100
+/* Nothing
+#define SYS_GPE_IRNCSCR_LAN0ESR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define SYS_GPE_IRNCSCR_LAN0ESR_INTACK 0x00000100
+/** Read: Interrupt occurred. */
+#define SYS_GPE_IRNCSCR_LAN0ESR_INTOCC 0x00000100
+/** GPONI sleep request
+    The INGRESS FIFO of port GPON submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define SYS_GPE_IRNCSCR_GPONISR 0x00000010
+/* Nothing
+#define SYS_GPE_IRNCSCR_GPONISR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define SYS_GPE_IRNCSCR_GPONISR_INTACK 0x00000010
+/** Read: Interrupt occurred. */
+#define SYS_GPE_IRNCSCR_GPONISR_INTOCC 0x00000010
+/** LAN3I sleep request
+    The INGRESS FIFO of port LAN3 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define SYS_GPE_IRNCSCR_LAN3ISR 0x00000008
+/* Nothing
+#define SYS_GPE_IRNCSCR_LAN3ISR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define SYS_GPE_IRNCSCR_LAN3ISR_INTACK 0x00000008
+/** Read: Interrupt occurred. */
+#define SYS_GPE_IRNCSCR_LAN3ISR_INTOCC 0x00000008
+/** LAN2I sleep request
+    The INGRESS FIFO of port LAN2 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define SYS_GPE_IRNCSCR_LAN2ISR 0x00000004
+/* Nothing
+#define SYS_GPE_IRNCSCR_LAN2ISR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define SYS_GPE_IRNCSCR_LAN2ISR_INTACK 0x00000004
+/** Read: Interrupt occurred. */
+#define SYS_GPE_IRNCSCR_LAN2ISR_INTOCC 0x00000004
+/** LAN1I sleep request
+    The INGRESS FIFO of port LAN1 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define SYS_GPE_IRNCSCR_LAN1ISR 0x00000002
+/* Nothing
+#define SYS_GPE_IRNCSCR_LAN1ISR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define SYS_GPE_IRNCSCR_LAN1ISR_INTACK 0x00000002
+/** Read: Interrupt occurred. */
+#define SYS_GPE_IRNCSCR_LAN1ISR_INTOCC 0x00000002
+/** LAN0I sleep request
+    The INGRESS FIFO of port LAN0 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
+#define SYS_GPE_IRNCSCR_LAN0ISR 0x00000001
+/* Nothing
+#define SYS_GPE_IRNCSCR_LAN0ISR_NULL 0x00000000 */
+/** Write: Acknowledge the interrupt. */
+#define SYS_GPE_IRNCSCR_LAN0ISR_INTACK 0x00000001
+/** Read: Interrupt occurred. */
+#define SYS_GPE_IRNCSCR_LAN0ISR_INTOCC 0x00000001
+
+/* Fields of "IRNCS Interrupt Control Register" */
+/** FSQM wakeup request
+    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSICR_FSQMWR 0x80000000
+/** GPONT wakeup request
+    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSICR_GPONTWR 0x20000000
+/** GPONE wakeup request
+    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSICR_GPONEWR 0x10000000
+/** LAN3E wakeup request
+    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSICR_LAN3EWR 0x08000000
+/** LAN2E wakeup requestThe ENGRESS FIFO of port LAN2 submitted a wakeup request.
+    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSICR_LAN2EWR 0x04000000
+/** LAN1E wakeup request
+    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSICR_LAN1EWR 0x02000000
+/** LAN0E wakeup request
+    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSICR_LAN0EWR 0x01000000
+/** GPONI wakeup request
+    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSICR_GPONIWR 0x00100000
+/** LAN3I wakeup request
+    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSICR_LAN3IWR 0x00080000
+/** LAN2I wakeup request
+    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSICR_LAN2IWR 0x00040000
+/** LAN1I wakeup request
+    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSICR_LAN1IWR 0x00020000
+/** LAN0I wakeup request
+    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSICR_LAN0IWR 0x00010000
+/** FSQM sleep request
+    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSICR_FSQMSR 0x00008000
+/** GPONT sleep request
+    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSICR_GPONTSR 0x00002000
+/** GPONE sleep request
+    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSICR_GPONESR 0x00001000
+/** LAN3E sleep request
+    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSICR_LAN3ESR 0x00000800
+/** LAN2E sleep requestThe ENGRESS FIFO of port LAN2 submitted a sleep request.
+    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSICR_LAN2ESR 0x00000400
+/** LAN1E sleep request
+    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSICR_LAN1ESR 0x00000200
+/** LAN0E sleep request
+    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSICR_LAN0ESR 0x00000100
+/** GPONI sleep request
+    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSICR_GPONISR 0x00000010
+/** LAN3I sleep request
+    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSICR_LAN3ISR 0x00000008
+/** LAN2I sleep request
+    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSICR_LAN2ISR 0x00000004
+/** LAN1I sleep request
+    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSICR_LAN1ISR 0x00000002
+/** LAN0I sleep request
+    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSICR_LAN0ISR 0x00000001
+
+/* Fields of "IRNCS Interrupt Enable Register" */
+/** FSQM wakeup request
+    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSEN_FSQMWR 0x80000000
+/* Disable
+#define SYS_GPE_IRNCSEN_FSQMWR_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_IRNCSEN_FSQMWR_EN 0x80000000
+/** GPONT wakeup request
+    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSEN_GPONTWR 0x20000000
+/* Disable
+#define SYS_GPE_IRNCSEN_GPONTWR_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_IRNCSEN_GPONTWR_EN 0x20000000
+/** GPONE wakeup request
+    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSEN_GPONEWR 0x10000000
+/* Disable
+#define SYS_GPE_IRNCSEN_GPONEWR_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_IRNCSEN_GPONEWR_EN 0x10000000
+/** LAN3E wakeup request
+    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSEN_LAN3EWR 0x08000000
+/* Disable
+#define SYS_GPE_IRNCSEN_LAN3EWR_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_IRNCSEN_LAN3EWR_EN 0x08000000
+/** LAN2E wakeup requestThe ENGRESS FIFO of port LAN2 submitted a wakeup request.
+    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSEN_LAN2EWR 0x04000000
+/* Disable
+#define SYS_GPE_IRNCSEN_LAN2EWR_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_IRNCSEN_LAN2EWR_EN 0x04000000
+/** LAN1E wakeup request
+    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSEN_LAN1EWR 0x02000000
+/* Disable
+#define SYS_GPE_IRNCSEN_LAN1EWR_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_IRNCSEN_LAN1EWR_EN 0x02000000
+/** LAN0E wakeup request
+    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSEN_LAN0EWR 0x01000000
+/* Disable
+#define SYS_GPE_IRNCSEN_LAN0EWR_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_IRNCSEN_LAN0EWR_EN 0x01000000
+/** GPONI wakeup request
+    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSEN_GPONIWR 0x00100000
+/* Disable
+#define SYS_GPE_IRNCSEN_GPONIWR_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_IRNCSEN_GPONIWR_EN 0x00100000
+/** LAN3I wakeup request
+    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSEN_LAN3IWR 0x00080000
+/* Disable
+#define SYS_GPE_IRNCSEN_LAN3IWR_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_IRNCSEN_LAN3IWR_EN 0x00080000
+/** LAN2I wakeup request
+    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSEN_LAN2IWR 0x00040000
+/* Disable
+#define SYS_GPE_IRNCSEN_LAN2IWR_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_IRNCSEN_LAN2IWR_EN 0x00040000
+/** LAN1I wakeup request
+    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSEN_LAN1IWR 0x00020000
+/* Disable
+#define SYS_GPE_IRNCSEN_LAN1IWR_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_IRNCSEN_LAN1IWR_EN 0x00020000
+/** LAN0I wakeup request
+    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSEN_LAN0IWR 0x00010000
+/* Disable
+#define SYS_GPE_IRNCSEN_LAN0IWR_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_IRNCSEN_LAN0IWR_EN 0x00010000
+/** FSQM sleep request
+    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSEN_FSQMSR 0x00008000
+/* Disable
+#define SYS_GPE_IRNCSEN_FSQMSR_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_IRNCSEN_FSQMSR_EN 0x00008000
+/** GPONT sleep request
+    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSEN_GPONTSR 0x00002000
+/* Disable
+#define SYS_GPE_IRNCSEN_GPONTSR_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_IRNCSEN_GPONTSR_EN 0x00002000
+/** GPONE sleep request
+    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSEN_GPONESR 0x00001000
+/* Disable
+#define SYS_GPE_IRNCSEN_GPONESR_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_IRNCSEN_GPONESR_EN 0x00001000
+/** LAN3E sleep request
+    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSEN_LAN3ESR 0x00000800
+/* Disable
+#define SYS_GPE_IRNCSEN_LAN3ESR_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_IRNCSEN_LAN3ESR_EN 0x00000800
+/** LAN2E sleep requestThe ENGRESS FIFO of port LAN2 submitted a sleep request.
+    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSEN_LAN2ESR 0x00000400
+/* Disable
+#define SYS_GPE_IRNCSEN_LAN2ESR_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_IRNCSEN_LAN2ESR_EN 0x00000400
+/** LAN1E sleep request
+    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSEN_LAN1ESR 0x00000200
+/* Disable
+#define SYS_GPE_IRNCSEN_LAN1ESR_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_IRNCSEN_LAN1ESR_EN 0x00000200
+/** LAN0E sleep request
+    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSEN_LAN0ESR 0x00000100
+/* Disable
+#define SYS_GPE_IRNCSEN_LAN0ESR_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_IRNCSEN_LAN0ESR_EN 0x00000100
+/** GPONI sleep request
+    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSEN_GPONISR 0x00000010
+/* Disable
+#define SYS_GPE_IRNCSEN_GPONISR_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_IRNCSEN_GPONISR_EN 0x00000010
+/** LAN3I sleep request
+    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSEN_LAN3ISR 0x00000008
+/* Disable
+#define SYS_GPE_IRNCSEN_LAN3ISR_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_IRNCSEN_LAN3ISR_EN 0x00000008
+/** LAN2I sleep request
+    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSEN_LAN2ISR 0x00000004
+/* Disable
+#define SYS_GPE_IRNCSEN_LAN2ISR_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_IRNCSEN_LAN2ISR_EN 0x00000004
+/** LAN1I sleep request
+    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSEN_LAN1ISR 0x00000002
+/* Disable
+#define SYS_GPE_IRNCSEN_LAN1ISR_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_IRNCSEN_LAN1ISR_EN 0x00000002
+/** LAN0I sleep request
+    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
+#define SYS_GPE_IRNCSEN_LAN0ISR 0x00000001
+/* Disable
+#define SYS_GPE_IRNCSEN_LAN0ISR_DIS 0x00000000 */
+/** Enable */
+#define SYS_GPE_IRNCSEN_LAN0ISR_EN 0x00000001
+
+/*! @} */ /* SYS_GPE_REGISTER */
+
+#endif /* _sys_gpe_reg_h */
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h
@@ -0,0 +1,58 @@
+/*
+ *  Lantiq FALCON specific CPU feature overrides
+ *
+ *  Copyright (C) 2010 Thomas Langer, Lantiq Deutschland
+ *
+ *  This file was derived from: include/asm-mips/cpu-features.h
+ *	Copyright (C) 2003, 2004 Ralf Baechle
+ *	Copyright (C) 2004 Maciej W. Rozycki
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ */
+#ifndef __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb		1
+#define cpu_has_4kex		1
+#define cpu_has_3k_cache	0
+#define cpu_has_4k_cache	1
+#define cpu_has_tx39_cache	0
+#define cpu_has_sb1_cache	0
+#define cpu_has_fpu		0
+#define cpu_has_32fpr		0
+#define cpu_has_counter		1
+#define cpu_has_watch		1
+#define cpu_has_divec		1
+
+#define cpu_has_prefetch	1
+#define cpu_has_ejtag		1
+#define cpu_has_llsc		1
+
+#define cpu_has_mips16		1
+#define cpu_has_mdmx		0
+#define cpu_has_mips3d		0
+#define cpu_has_smartmips	0
+
+#define cpu_has_mips32r1	1
+#define cpu_has_mips32r2	1
+#define cpu_has_mips64r1	0
+#define cpu_has_mips64r2	0
+
+#define cpu_has_dsp		1
+#define cpu_has_mipsmt		1
+
+#define cpu_has_vint		1
+#define cpu_has_veic		1
+
+#define cpu_has_64bits		0
+#define cpu_has_64bit_zero_reg	0
+#define cpu_has_64bit_gp_regs	0
+#define cpu_has_64bit_addresses	0
+
+#define cpu_dcache_line_size()	32
+#define cpu_icache_line_size()	32
+
+#endif /* __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H */
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/falcon/ebu_reg.h
@@ -0,0 +1,1520 @@
+/******************************************************************************
+
+                               Copyright (c) 2010
+                            Lantiq Deutschland GmbH
+
+  For licensing information, see the file 'LICENSE' in the root folder of
+  this software module.
+
+******************************************************************************/
+
+#ifndef _ebu_reg_h
+#define _ebu_reg_h
+
+/** \addtogroup EBU_REGISTER
+   @{
+*/
+/* access macros */
+#define ebu_r32(reg) reg_r32(&ebu->reg)
+#define ebu_w32(val, reg) reg_w32(val, &ebu->reg)
+#define ebu_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &ebu->reg)
+#define ebu_r32_table(reg, idx) reg_r32_table(ebu->reg, idx)
+#define ebu_w32_table(val, reg, idx) reg_w32_table(val, ebu->reg, idx)
+#define ebu_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, ebu->reg, idx)
+#define ebu_adr_table(reg, idx) adr_table(ebu->reg, idx)
+
+
+/** EBU register structure */
+struct gpon_reg_ebu
+{
+   /** Reserved */
+   unsigned int res_0[2]; /* 0x00000000 */
+   /** Module ID Register
+       Module type and version identifier */
+   unsigned int modid; /* 0x00000008 */
+   /** Module Control Register
+       This register contains general configuration information observed for all CS regions or dealing with EBU functionality that is not directly related to external memory access. */
+   unsigned int modcon; /* 0x0000000C */
+   /** Bus Read Configuration Register0
+       Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */
+   unsigned int busrcon0; /* 0x00000010 */
+   /** Bus Read Parameters Register0 */
+   unsigned int busrp0; /* 0x00000014 */
+   /** Bus Write Configuration Register0
+       Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */
+   unsigned int buswcon0; /* 0x00000018 */
+   /** Bus Write Parameters Register0 */
+   unsigned int buswp0; /* 0x0000001C */
+   /** Bus Read Configuration Register1
+       Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */
+   unsigned int busrcon1; /* 0x00000020 */
+   /** Bus Read Parameters Register1 */
+   unsigned int busrp1; /* 0x00000024 */
+   /** Bus Write Configuration Register1
+       Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */
+   unsigned int buswcon1; /* 0x00000028 */
+   /** Bus Write Parameters Register1 */
+   unsigned int buswp1; /* 0x0000002C */
+   /** Reserved */
+   unsigned int res_1[8]; /* 0x00000030 */
+   /** Bus Protocol Configuration Extension Register 0 */
+   unsigned int busconext0; /* 0x00000050 */
+   /** Bus Protocol Configuration Extension Register 1 */
+   unsigned int busconext1; /* 0x00000054 */
+   /** Reserved */
+   unsigned int res_2[10]; /* 0x00000058 */
+   /** Serial Flash Configuration Register
+       The content of this register configures the EBU's Serial Flash protocol engine. */
+   unsigned int sfcon; /* 0x00000080 */
+   /** Serial Flash Timing Register
+       This register defines the signal timing for the Serial Flash Access. See Section 3.18.3 on page 112 for details. */
+   unsigned int sftime; /* 0x00000084 */
+   /** Serial Flash Status Register
+       This register holds status information on the Serial Flash device(s) attached and the EBU's Serial Flash protocol engine. */
+   unsigned int sfstat; /* 0x00000088 */
+   /** Serial Flash Command Register
+       When writing to this register's opcode field, a command is started in the EBU's Serial Flash controller. */
+   unsigned int sfcmd; /* 0x0000008C */
+   /** Serial Flash Address Register
+       This register holds the address to be sent (if any) with accesses to/from a Serial Flash started by writing to EBU_SFCMD (Indirect Access Mode, see Section 3.18.2.4.1 on page 103). */
+   unsigned int sfaddr; /* 0x00000090 */
+   /** Serial Flash Data Register
+       This register holds the data being transferred (if any) with accesses to/from a Serial Flash started by writing to EBU_SFCMD (Indirect Access Mode, see Section 4.18.2.4.1 on page 116). */
+   unsigned int sfdata; /* 0x00000094 */
+   /** Serial Flash I/O Control Register
+       This register provides additional configuration for controlling the IO pads of the Serial Flash interface. */
+   unsigned int sfio; /* 0x00000098 */
+   /** Reserved */
+   unsigned int res_3[25]; /* 0x0000009C */
+};
+
+
+/* Fields of "Module ID Register" */
+/** Feature Select
+    This field indicates the types of external devices/protocols supported by the GPON version of the EBU. */
+#define MODID_FSEL_MASK 0xE0000000
+/** field offset */
+#define MODID_FSEL_OFFSET 29
+/** Support for SRAM, NAND/NOR/OneNand Flash and Cellular RAM is implemented. */
+#define MODID_FSEL_SRAM_FLASH_CRAM 0x00000000
+/** Support for SRAM, NAND/NOR/OneNand Flash, Cellular RAM and SDR SDRAM is implemented. */
+#define MODID_FSEL_SRAM_FLASH_CRAM_SDR 0x20000000
+/** Support for SRAM, NAND/NOR/OneNand Flash, Cellular RAM and SDR/DDR SDRAM is implemented. */
+#define MODID_FSEL_SRAM_FLASH_CRAM_DDR 0x40000000
+/** Support for SRAM, NAND/NOR/OneNand Flash, Cellular RAM, SDR/DDR SDRAM 0nd LPDDR-Flash is implemented. */
+#define MODID_FSEL_SRAM_FLASH_CRAM_DDR_LPNVM 0x60000000
+/** Serial Flash Support
+    Indicates whether or not the support of Serial Flash devices is available. */
+#define MODID_SF 0x10000000
+/* Not Available
+#define MODID_SF_NAV 0x00000000 */
+/** Available */
+#define MODID_SF_AV 0x10000000
+/** AAD-mux Support
+    Indicates whether or not the GPON EBU supports AAD-mux protocol for Burst Flash and Cellular RAM. */
+#define MODID_AAD 0x08000000
+/* Not Available
+#define MODID_AAD_NAV 0x00000000 */
+/** Available */
+#define MODID_AAD_AV 0x08000000
+/** Indicates whether or not the GPON EBU implements a DLL which is e.g. used for 50% duty cycle external clock generation. Note that a DLL is always implemented if DDR-SDRAM support is selected. */
+#define MODID_DLL 0x04000000
+/* Not Available
+#define MODID_DLL_NAV 0x00000000 */
+/** Available */
+#define MODID_DLL_AV 0x04000000
+/** Pad Multiplexing Scheme */
+#define MODID_PMS_MASK 0x03000000
+/** field offset */
+#define MODID_PMS_OFFSET 24
+/** The EBU comprises of dedicated address pins A[EXTAW-1=:16]. */
+#define MODID_PMS_PMS_CLASSIC 0x00000000
+/** Revision
+    Revision Number */
+#define MODID_REV_MASK 0x000F0000
+/** field offset */
+#define MODID_REV_OFFSET 16
+/** Module ID
+    This field contains the EBU's unique peripheral ID. */
+#define MODID_ID_MASK 0x0000FF00
+/** field offset */
+#define MODID_ID_OFFSET 8
+/** Version
+    This field gives the EBU version number. */
+#define MODID_VERSION_MASK 0x000000FF
+/** field offset */
+#define MODID_VERSION_OFFSET 0
+
+/* Fields of "Module Control Register" */
+/** Reserved */
+#define MODCON_DLLUPDINT_MASK 0xC0000000
+/** field offset */
+#define MODCON_DLLUPDINT_OFFSET 30
+/** Access Inhibit Acknowledge
+    After suspension of all accesses to the External Bus has been requested by setting bit acc_inh, acc_inh_ack acknowledges the request and inidcates that access suspension is now in effect. The bit is cleared when acc_inh gets deasserted. */
+#define MODCON_AIA 0x02000000
+/* no access restriction are active in the EBU subsystem
+#define MODCON_AIA_NO_INHIBIT 0x00000000 */
+/** accesses are restricted to selected (configuration) system bus port(s) */
+#define MODCON_AIA_INHIBIT 0x02000000
+/** Access Inhibit request
+    Setting this bit will suspend all non-CPU system bus ports and the EBU itself from accessing the External Bus. This feature is usually used when the CPU needs to reconfigure protocol parameters in the EBU in order to avoid external accesses with invalid settings. The EBU acknowledges that the access suspension is in effect by asserting acc_inh_ack. */
+#define MODCON_AI 0x01000000
+/* no access restriction are active in the EBU subsystem
+#define MODCON_AI_NO_INHIBIT 0x00000000 */
+/** accesses are restricted to selected (configuration) system bus port(s) */
+#define MODCON_AI_INHIBIT 0x01000000
+/** Lock Timeout */
+#define MODCON_LTO_MASK 0x00FF0000
+/** field offset */
+#define MODCON_LTO_OFFSET 16
+/** Reserved */
+#define MODCON_DDREN 0x00008000
+/** Pad Drive Control
+    Intended to be used to control the EBU pad''s drive strength. Refer to the GPON chip specification to see which drive strnegth options are available and whether they are actually controlled by the EBU's register bit. The value stored in this register bit is directly connected to the corresponding output of the EBU module and takes no functional effect within the EBU itself. */
+#define MODCON_PEXT 0x00004000
+/* Normal drive
+#define MODCON_PEXT_NORMAL 0x00000000 */
+/** Strong drive */
+#define MODCON_PEXT_STRONG 0x00004000
+/** Pad Slew Falling Edge Control
+    Intended to be used to trim the External Bus pad's falling edge slew rate. Refer to the GPON chip specification to see which slew rate options are available and whether they are actually controlled by the EBU's register bit. The value stored in this register bit is directly connected to the corresponding output of the EBU module and takes no functional effect within the EBU itself. */
+#define MODCON_SLF 0x00002000
+/* Slow slew rate
+#define MODCON_SLF_SLOW 0x00000000 */
+/** Fast slew rate */
+#define MODCON_SLF_FAST 0x00002000
+/** Pad Slew Rising Edge Control
+    Intended to be used to trim the External Bus pad's rising edge slew rate. Refer to the GPON chip specification to see which slew rate options are available and whether they are actually controlled by the EBU's register bit. The value stored in this register bit is directly connected to the corresponding output of the EBU module and takes no functional effect within the EBU itself. */
+#define MODCON_SLR 0x00001000
+/* Slow slew rate
+#define MODCON_SLR_SLOW 0x00000000 */
+/** Fast slew rate */
+#define MODCON_SLR_FAST 0x00001000
+/** Write Buffering Mode
+    This bit controls when the EBU starts a new write burst transaction from the Memport interface. */
+#define MODCON_WBM 0x00000040
+/* The EBU starts a write transaction on the External Bus as early as possible, expecting that the n beats of the write burst will be transferred within n or n+1 clock cycles over the EBU's Memport interface. Use this mode if the EBU is clocked at the same or a slower frequency than the system bus interconnect.
+#define MODCON_WBM_START_WRITE_EARLY 0x00000000 */
+/** The EBU start a write transaction only after all data of a write burst have been received over the EBU's Memport interface. Use this mode if the EBU is clocked at a higher frequency than the system bus interrconnect. */
+#define MODCON_WBM_START_WRITE_LATE 0x00000040
+/** Reserved */
+#define MODCON_SDCLKEN 0x00000020
+/** Standby Mode Enable
+    When set allows the EBU subsystem to enter standby mode in response to a rising edge on input signal standby_req_i. See Section 3.9.3 for details. */
+#define MODCON_STBYEN 0x00000010
+/* Disable
+#define MODCON_STBYEN_DIS 0x00000000 */
+/** Enable */
+#define MODCON_STBYEN_EN 0x00000010
+/** Enable BFCLK1
+    This field will enables or disables mirroring the clock that is output on BFCLKO_0 also on pad BFCLKO_1 to double the drive strength. See also Section 3.17.3) */
+#define MODCON_BFCLK1EN 0x00000008
+/* Disable
+#define MODCON_BFCLK1EN_DIS 0x00000000 */
+/** Enable */
+#define MODCON_BFCLK1EN_EN 0x00000008
+/** Ready/Busy Status Edge
+    This is a read-only bit which shows a change of the logic level shown in the sts field since last read. It is reset by a read access. */
+#define MODCON_STSEDGE 0x00000004
+/** Ready/Busy Status
+    This is a read-only bit which reflects the current logic level present on the RDY/BSY or STS input pin which is (optionally) fed-in from a General Purpose I/O pad which is not part of the EBU via the EBU's input pin signal gpio_nand_rdy_ */
+#define MODCON_STS 0x00000002
+/** External Bus Arbitration Mode
+    This bit allows to disconnect the EBU from the External Bus. While EBU_MODCON.acc_inh_ack is 0, the value of arb_mode is forced to OWN_BUS. */
+#define MODCON_AM 0x00000001
+/* The EBU does not own the bus (multi-master)
+#define MODCON_AM_SHAREDBUS 0x00000000 */
+/** The EBU owns the external bus. */
+#define MODCON_AM_OWNBUS 0x00000001
+
+/* Fields of "Bus Read Configuration Register0" */
+/** Device Type For Region
+    After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */
+#define BUSRCON0_AGEN_MASK 0xF0000000
+/** field offset */
+#define BUSRCON0_AGEN_OFFSET 28
+/** Muxed Asynchronous Type External Memory */
+#define BUSRCON0_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000
+/** Muxed Burst Type External Memory */
+#define BUSRCON0_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000
+/** NAND Flash (page optimised) */
+#define BUSRCON0_AGEN_NAND_FLASH 0x20000000
+/** Muxed Cellular RAM External Memory */
+#define BUSRCON0_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000
+/** Demuxed Asynchronous Type External Memory */
+#define BUSRCON0_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000
+/** Demuxed Burst Type External Memory */
+#define BUSRCON0_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000
+/** Demuxed Page Mode External Memory */
+#define BUSRCON0_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000
+/** Demuxed Cellular RAM External Memory */
+#define BUSRCON0_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000
+/** Serial Flash */
+#define BUSRCON0_AGEN_SERIAL_FLASH 0xF0000000
+/** Device Addressing Mode
+    t.b.d. */
+#define BUSRCON0_PORTW_MASK 0x0C000000
+/** field offset */
+#define BUSRCON0_PORTW_OFFSET 26
+/** 8-bit multiplexed */
+#define BUSRCON0_PORTW_8_BIT_MUX 0x00000000
+/** 16-bit multiplexed */
+#define BUSRCON0_PORTW_16_BIT_MUX 0x04000000
+/** Twin, 16-bit multiplexed */
+#define BUSRCON0_PORTW_TWIN_16_BIT_MUX 0x08000000
+/** 32-bit multiplexed */
+#define BUSRCON0_PORTW_32_BIT_MUX 0x0C000000
+/** External Wait Control
+    Function of the WAIT input. This is specific to the device type (i.e. the agen field). */
+#define BUSRCON0_WAIT_MASK 0x03000000
+/** field offset */
+#define BUSRCON0_WAIT_OFFSET 24
+/** WAIT is ignored (default after reset). */
+#define BUSRCON0_WAIT_OFF 0x00000000
+/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */
+#define BUSRCON0_WAIT_EARLY_WAIT 0x01000000
+/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */
+#define BUSRCON0_WAIT_TWO_STAGE_SYNC 0x01000000
+/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */
+#define BUSRCON0_WAIT_WAIT_WITH_DATA 0x02000000
+/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */
+#define BUSRCON0_WAIT_SINGLE_STAGE_SYNC 0x02000000
+/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */
+#define BUSRCON0_WAIT_ABORT_AND_RETRY 0x03000000
+/** Disable Burst Address Wrapping */
+#define BUSRCON0_DBA 0x00800000
+/** Reversed polarity at wait */
+#define BUSRCON0_WAITINV 0x00400000
+/* Low active.
+#define BUSRCON0_WAITINV_ACTLOW 0x00000000 */
+/** High active */
+#define BUSRCON0_WAITINV_ACTHI 0x00400000
+/** Early ADV Enable for Synchronous Bursts */
+#define BUSRCON0_EBSE 0x00200000
+/* Low active.
+#define BUSRCON0_EBSE_DELAYED 0x00000000 */
+/** High active */
+#define BUSRCON0_EBSE_NOT_DELAYED 0x00200000
+/** Early Control Signals for Synchronous Bursts */
+#define BUSRCON0_ECSE 0x00100000
+/* Low active.
+#define BUSRCON0_ECSE_DELAYED 0x00000000 */
+/** High active */
+#define BUSRCON0_ECSE_NOT_DELAYED 0x00100000
+/** Synchronous Burst Buffer Mode Select */
+#define BUSRCON0_FBBMSEL 0x00080000
+/* FIXED_LENGTH
+#define BUSRCON0_FBBMSEL_FIXED_LENGTH 0x00000000 */
+/** CONTINUOUS */
+#define BUSRCON0_FBBMSEL_CONTINUOUS 0x00080000
+/** Burst Length for Synchronous Burst */
+#define BUSRCON0_FETBLEN_MASK 0x00070000
+/** field offset */
+#define BUSRCON0_FETBLEN_OFFSET 16
+/** Up to 1 data cycle (default after reset). */
+#define BUSRCON0_FETBLEN_SINGLE 0x00000000
+/** Up to 2 data cycles. */
+#define BUSRCON0_FETBLEN_BURST2 0x00010000
+/** Up to 4 data cycles. */
+#define BUSRCON0_FETBLEN_BURST4 0x00020000
+/** Up to 8 data cycles. */
+#define BUSRCON0_FETBLEN_BURST8 0x00030000
+/** Up to 16 data cycles. */
+#define BUSRCON0_FETBLEN_BURST16 0x00040000
+/** Reserved
+    This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */
+#define BUSRCON0_NANDAMAP_MASK 0x0000C000
+/** field offset */
+#define BUSRCON0_NANDAMAP_OFFSET 14
+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
+#define BUSRCON0_NANDAMAP_NAND_A17_16 0x00000000
+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
+#define BUSRCON0_NANDAMAP_NAND_WAIT_ADV 0x00004000
+/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */
+#define BUSRCON0_NANDAMAP_NAND_AD9_8 0x00008000
+/** Reserved for future use. Do not use or unpredictable results may occur. */
+#define BUSRCON0_NANDAMAP_NAND_RFU 0x0000C000
+/** AAD-mux Protocol
+    If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */
+#define BUSRCON0_AADMUX 0x00002000
+/* Muxed device is write accessed in AD-mux mode.
+#define BUSRCON0_AADMUX_AD_MUX 0x00000000 */
+/** Muxed device is write accessed in AAD-mux mode. */
+#define BUSRCON0_AADMUX_AAD_MUX 0x00002000
+/** Asynchronous Address Phase */
+#define BUSRCON0_AAP 0x00001000
+/* Clock is enabled at beginning of access.
+#define BUSRCON0_AAP_EARLY 0x00000000 */
+/** Clock is enabled after address phase. */
+#define BUSRCON0_AAP_LATE 0x00001000
+/** Burst Flash Read Single Stage Synchronisation */
+#define BUSRCON0_BFSSS 0x00000800
+/* Two stages of synchronisation used.
+#define BUSRCON0_BFSSS_TWO_STAGE 0x00000000 */
+/** Single stage of synchronisation used. */
+#define BUSRCON0_BFSSS_SINGLE_STAGE 0x00000800
+/** Burst Flash Clock Feedback Enable */
+#define BUSRCON0_FDBKEN 0x00000400
+/* Disable
+#define BUSRCON0_FDBKEN_DIS 0x00000000 */
+/** Enable */
+#define BUSRCON0_FDBKEN_EN 0x00000400
+/** Auxiliary Chip Select Enable
+    Not supported in GPON-EBU, field must be set to 0. */
+#define BUSRCON0_CSA 0x00000200
+/* Disable
+#define BUSRCON0_CSA_DIS 0x00000000 */
+/** Enable */
+#define BUSRCON0_CSA_EN 0x00000200
+/** Flash Non-Array Access Enable
+    Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */
+#define BUSRCON0_NAA 0x00000100
+/* Disable
+#define BUSRCON0_NAA_DIS 0x00000000 */
+/** Enable */
+#define BUSRCON0_NAA_EN 0x00000100
+/** Module Enable */
+#define BUSRCON0_ENABLE 0x00000001
+/* Disable
+#define BUSRCON0_ENABLE_DIS 0x00000000 */
+/** Enable */
+#define BUSRCON0_ENABLE_EN 0x00000001
+
+/* Fields of "Bus Read Parameters Register0" */
+/** Address Cycles
+    Number of cycles for address phase. */
+#define BUSRP0_ADDRC_MASK 0xF0000000
+/** field offset */
+#define BUSRP0_ADDRC_OFFSET 28
+/** Address Hold Cycles For Multiplexed Address
+    Number of address hold cycles during multiplexed accesses. */
+#define BUSRP0_ADHOLC_MASK 0x0F000000
+/** field offset */
+#define BUSRP0_ADHOLC_OFFSET 24
+/** Programmed Command Delay Cycles
+    Number of delay cycles during command delay phase. */
+#define BUSRP0_CMDDELAY_MASK 0x00F00000
+/** field offset */
+#define BUSRP0_CMDDELAY_OFFSET 20
+/** Extended Data */
+#define BUSRP0_EXTDATA_MASK 0x000C0000
+/** field offset */
+#define BUSRP0_EXTDATA_OFFSET 18
+/** External device outputs data every BFCLK cycle */
+#define BUSRP0_EXTDATA_ONE 0x00000000
+/** External device outputs data every 2nd BFCLK cycles */
+#define BUSRP0_EXTDATA_TWO 0x00040000
+/** External device outputs data every 4th BFCLK cycles */
+#define BUSRP0_EXTDATA_FOUR 0x00080000
+/** External device outputs data every 8th BFCLK cycles */
+#define BUSRP0_EXTDATA_EIGHT 0x000C0000
+/** Frequency of external clock at pin BFCLKO */
+#define BUSRP0_EXTCLOCK_MASK 0x00030000
+/** field offset */
+#define BUSRP0_EXTCLOCK_OFFSET 16
+/** Equal to ebu_clk frequency. */
+#define BUSRP0_EXTCLOCK_ONE_TO_ONE 0x00000000
+/** 1/2 of ebu_clk frequency. */
+#define BUSRP0_EXTCLOCK_ONE_TO_TWO 0x00010000
+/** 1/3 of ebu_clk frequency. */
+#define BUSRP0_EXTCLOCK_ONE_TO_THREE 0x00020000
+/** 1/4 of ebu_clk frequency (default after reset). */
+#define BUSRP0_EXTCLOCK_ONE_TO_FOUR 0x00030000
+/** Data Hold Cycles For read Accesses
+    Number of data hold cycles during read accesses. Applies to spinner support only where the address is guaranteed stable for datac clocks after RD high */
+#define BUSRP0_DATAC_MASK 0x0000F000
+/** field offset */
+#define BUSRP0_DATAC_OFFSET 12
+/** Programmed Wait States for read accesses
+    Number of programmed wait states for read accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */
+#define BUSRP0_WAITRDC_MASK 0x00000F80
+/** field offset */
+#define BUSRP0_WAITRDC_OFFSET 7
+/** Recovery Cycles After read Accesses, same CS
+    Number of idle cycles after read accesses when the next access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */
+#define BUSRP0_RECOVC_MASK 0x00000070
+/** field offset */
+#define BUSRP0_RECOVC_OFFSET 4
+/** Recovery Cycles After read Accesses, other CS
+    Number of idle cycles after read accesses when the next access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */
+#define BUSRP0_DTACS_MASK 0x0000000F
+/** field offset */
+#define BUSRP0_DTACS_OFFSET 0
+
+/* Fields of "Bus Write Configuration Register0" */
+/** Device Type For Region
+    After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */
+#define BUSWCON0_AGEN_MASK 0xF0000000
+/** field offset */
+#define BUSWCON0_AGEN_OFFSET 28
+/** Muxed Asynchronous Type External Memory */
+#define BUSWCON0_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000
+/** Muxed Burst Type External Memory */
+#define BUSWCON0_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000
+/** NAND Flash (page optimised) */
+#define BUSWCON0_AGEN_NAND_FLASH 0x20000000
+/** Muxed Cellular RAM External Memory */
+#define BUSWCON0_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000
+/** Demuxed Asynchronous Type External Memory */
+#define BUSWCON0_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000
+/** Demuxed Burst Type External Memory */
+#define BUSWCON0_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000
+/** Demuxed Page Mode External Memory */
+#define BUSWCON0_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000
+/** Demuxed Cellular RAM External Memory */
+#define BUSWCON0_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000
+/** Serial Flash */
+#define BUSWCON0_AGEN_SERIAL_FLASH 0xF0000000
+/** Device Addressing Mode
+    t.b.d. */
+#define BUSWCON0_PORTW_MASK 0x0C000000
+/** field offset */
+#define BUSWCON0_PORTW_OFFSET 26
+/** External Wait Control
+    Function of the WAIT input. This is specific to the device type (i.e. the agen field). */
+#define BUSWCON0_WAIT_MASK 0x03000000
+/** field offset */
+#define BUSWCON0_WAIT_OFFSET 24
+/** WAIT is ignored (default after reset). */
+#define BUSWCON0_WAIT_OFF 0x00000000
+/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */
+#define BUSWCON0_WAIT_EARLY_WAIT 0x01000000
+/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */
+#define BUSWCON0_WAIT_TWO_STAGE_SYNC 0x01000000
+/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */
+#define BUSWCON0_WAIT_WAIT_WITH_DATA 0x02000000
+/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */
+#define BUSWCON0_WAIT_SINGLE_STAGE_SYNC 0x02000000
+/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */
+#define BUSWCON0_WAIT_ABORT_AND_RETRY 0x03000000
+/** Reserved */
+#define BUSWCON0_LOCKCS 0x00800000
+/** Reversed polarity at wait */
+#define BUSWCON0_WAITINV 0x00400000
+/* Low active.
+#define BUSWCON0_WAITINV_ACTLOW 0x00000000 */
+/** High active */
+#define BUSWCON0_WAITINV_ACTHI 0x00400000
+/** Early ADV Enable for Synchronous Bursts */
+#define BUSWCON0_EBSE 0x00200000
+/* Low active.
+#define BUSWCON0_EBSE_DELAYED 0x00000000 */
+/** High active */
+#define BUSWCON0_EBSE_NOT_DELAYED 0x00200000
+/** Early Control Signals for Synchronous Bursts */
+#define BUSWCON0_ECSE 0x00100000
+/* Low active.
+#define BUSWCON0_ECSE_DELAYED 0x00000000 */
+/** High active */
+#define BUSWCON0_ECSE_NOT_DELAYED 0x00100000
+/** Synchronous Burst Buffer Mode Select */
+#define BUSWCON0_FBBMSEL 0x00080000
+/* FIXED_LENGTH
+#define BUSWCON0_FBBMSEL_FIXED_LENGTH 0x00000000 */
+/** CONTINUOUS */
+#define BUSWCON0_FBBMSEL_CONTINUOUS 0x00080000
+/** Burst Length for Synchronous Burst */
+#define BUSWCON0_FETBLEN_MASK 0x00070000
+/** field offset */
+#define BUSWCON0_FETBLEN_OFFSET 16
+/** Up to 1 data cycle (default after reset). */
+#define BUSWCON0_FETBLEN_SINGLE 0x00000000
+/** Up to 2 data cycles. */
+#define BUSWCON0_FETBLEN_BURST2 0x00010000
+/** Up to 4 data cycles. */
+#define BUSWCON0_FETBLEN_BURST4 0x00020000
+/** Up to 8 data cycles. */
+#define BUSWCON0_FETBLEN_BURST8 0x00030000
+/** Up to 16 data cycles. */
+#define BUSWCON0_FETBLEN_BURST16 0x00040000
+/** Reserved
+    This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */
+#define BUSWCON0_NANDAMAP_MASK 0x0000C000
+/** field offset */
+#define BUSWCON0_NANDAMAP_OFFSET 14
+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
+#define BUSWCON0_NANDAMAP_NAND_A17_16 0x00000000
+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
+#define BUSWCON0_NANDAMAP_NAND_WAIT_ADV 0x00004000
+/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */
+#define BUSWCON0_NANDAMAP_NAND_AD9_8 0x00008000
+/** Reserved for future use. Do not use or unpredictable results may occur. */
+#define BUSWCON0_NANDAMAP_NAND_RFU 0x0000C000
+/** AAD-mux Protocol
+    If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */
+#define BUSWCON0_AADMUX 0x00002000
+/* Muxed device is write accessed in AD-mux mode.
+#define BUSWCON0_AADMUX_AD_MUX 0x00000000 */
+/** Muxed device is write accessed in AAD-mux mode. */
+#define BUSWCON0_AADMUX_AAD_MUX 0x00002000
+/** Asynchronous Address Phase */
+#define BUSWCON0_AAP 0x00001000
+/* Clock is enabled at beginning of access.
+#define BUSWCON0_AAP_EARLY 0x00000000 */
+/** Clock is enabled after address phase. */
+#define BUSWCON0_AAP_LATE 0x00001000
+/** Auxiliary Chip Select Enable
+    Not supported in GPON-EBU, field must be set to 0. */
+#define BUSWCON0_CSA 0x00000200
+/* Disable
+#define BUSWCON0_CSA_DIS 0x00000000 */
+/** Enable */
+#define BUSWCON0_CSA_EN 0x00000200
+/** Flash Non-Array Access Enable
+    Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */
+#define BUSWCON0_NAA 0x00000100
+/* Disable
+#define BUSWCON0_NAA_DIS 0x00000000 */
+/** Enable */
+#define BUSWCON0_NAA_EN 0x00000100
+/** Module Enable */
+#define BUSWCON0_ENABLE 0x00000001
+/* Disable
+#define BUSWCON0_ENABLE_DIS 0x00000000 */
+/** Enable */
+#define BUSWCON0_ENABLE_EN 0x00000001
+
+/* Fields of "Bus Write Parameters Register0" */
+/** Address Cycles
+    Number of cycles for address phase. */
+#define BUSWP0_ADDRC_MASK 0xF0000000
+/** field offset */
+#define BUSWP0_ADDRC_OFFSET 28
+/** Address Hold Cycles For Multiplexed Address
+    Number of address hold cycles during multiplexed accesses. */
+#define BUSWP0_ADHOLC_MASK 0x0F000000
+/** field offset */
+#define BUSWP0_ADHOLC_OFFSET 24
+/** Programmed Command Delay Cycles
+    Number of delay cycles during command delay phase. */
+#define BUSWP0_CMDDELAY_MASK 0x00F00000
+/** field offset */
+#define BUSWP0_CMDDELAY_OFFSET 20
+/** Extended Data */
+#define BUSWP0_EXTDATA_MASK 0x000C0000
+/** field offset */
+#define BUSWP0_EXTDATA_OFFSET 18
+/** External device outputs data every BFCLK cycle */
+#define BUSWP0_EXTDATA_ONE 0x00000000
+/** External device outputs data every 2nd BFCLK cycles */
+#define BUSWP0_EXTDATA_TWO 0x00040000
+/** External device outputs data every 4th BFCLK cycles */
+#define BUSWP0_EXTDATA_FOUR 0x00080000
+/** External device outputs data every 8th BFCLK cycles */
+#define BUSWP0_EXTDATA_EIGHT 0x000C0000
+/** Frequency of external clock at pin BFCLKO */
+#define BUSWP0_EXTCLOCK_MASK 0x00030000
+/** field offset */
+#define BUSWP0_EXTCLOCK_OFFSET 16
+/** Equal to ebu_clk frequency. */
+#define BUSWP0_EXTCLOCK_ONE_TO_ONE 0x00000000
+/** 1/2 of ebu_clk frequency. */
+#define BUSWP0_EXTCLOCK_ONE_TO_TWO 0x00010000
+/** 1/3 of ebu_clk frequency. */
+#define BUSWP0_EXTCLOCK_ONE_TO_THREE 0x00020000
+/** 1/4 of ebu_clk frequency (default after reset). */
+#define BUSWP0_EXTCLOCK_ONE_TO_FOUR 0x00030000
+/** Data Hold Cycles For write Accesses
+    Number of data hold cycles during write accesses. */
+#define BUSWP0_DATAC_MASK 0x0000F000
+/** field offset */
+#define BUSWP0_DATAC_OFFSET 12
+/** Programmed Wait States For write Accesses
+    Number of programmed wait states for write accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */
+#define BUSWP0_WAITWDC_MASK 0x00000F80
+/** field offset */
+#define BUSWP0_WAITWDC_OFFSET 7
+/** Recovery Cycles After write Accesses, same CS
+    Number of idle cycles after write accesses when following access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */
+#define BUSWP0_RECOVC_MASK 0x00000070
+/** field offset */
+#define BUSWP0_RECOVC_OFFSET 4
+/** Recovery Cycles After write Accesses, other CS
+    Number of idle cycles after write accesses when the following access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */
+#define BUSWP0_DTACS_MASK 0x0000000F
+/** field offset */
+#define BUSWP0_DTACS_OFFSET 0
+
+/* Fields of "Bus Read Configuration Register1" */
+/** Device Type For Region
+    After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */
+#define BUSRCON1_AGEN_MASK 0xF0000000
+/** field offset */
+#define BUSRCON1_AGEN_OFFSET 28
+/** Muxed Asynchronous Type External Memory */
+#define BUSRCON1_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000
+/** Muxed Burst Type External Memory */
+#define BUSRCON1_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000
+/** NAND Flash (page optimised) */
+#define BUSRCON1_AGEN_NAND_FLASH 0x20000000
+/** Muxed Cellular RAM External Memory */
+#define BUSRCON1_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000
+/** Demuxed Asynchronous Type External Memory */
+#define BUSRCON1_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000
+/** Demuxed Burst Type External Memory */
+#define BUSRCON1_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000
+/** Demuxed Page Mode External Memory */
+#define BUSRCON1_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000
+/** Demuxed Cellular RAM External Memory */
+#define BUSRCON1_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000
+/** Serial Flash */
+#define BUSRCON1_AGEN_SERIAL_FLASH 0xF0000000
+/** Device Addressing Mode
+    t.b.d. */
+#define BUSRCON1_PORTW_MASK 0x0C000000
+/** field offset */
+#define BUSRCON1_PORTW_OFFSET 26
+/** 8-bit multiplexed */
+#define BUSRCON1_PORTW_8_BIT_MUX 0x00000000
+/** 16-bit multiplexed */
+#define BUSRCON1_PORTW_16_BIT_MUX 0x04000000
+/** Twin, 16-bit multiplexed */
+#define BUSRCON1_PORTW_TWIN_16_BIT_MUX 0x08000000
+/** 32-bit multiplexed */
+#define BUSRCON1_PORTW_32_BIT_MUX 0x0C000000
+/** External Wait Control
+    Function of the WAIT input. This is specific to the device type (i.e. the agen field). */
+#define BUSRCON1_WAIT_MASK 0x03000000
+/** field offset */
+#define BUSRCON1_WAIT_OFFSET 24
+/** WAIT is ignored (default after reset). */
+#define BUSRCON1_WAIT_OFF 0x00000000
+/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */
+#define BUSRCON1_WAIT_EARLY_WAIT 0x01000000
+/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */
+#define BUSRCON1_WAIT_TWO_STAGE_SYNC 0x01000000
+/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */
+#define BUSRCON1_WAIT_WAIT_WITH_DATA 0x02000000
+/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */
+#define BUSRCON1_WAIT_SINGLE_STAGE_SYNC 0x02000000
+/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */
+#define BUSRCON1_WAIT_ABORT_AND_RETRY 0x03000000
+/** Disable Burst Address Wrapping */
+#define BUSRCON1_DBA 0x00800000
+/** Reversed polarity at wait */
+#define BUSRCON1_WAITINV 0x00400000
+/* Low active.
+#define BUSRCON1_WAITINV_ACTLOW 0x00000000 */
+/** High active */
+#define BUSRCON1_WAITINV_ACTHI 0x00400000
+/** Early ADV Enable for Synchronous Bursts */
+#define BUSRCON1_EBSE 0x00200000
+/* Low active.
+#define BUSRCON1_EBSE_DELAYED 0x00000000 */
+/** High active */
+#define BUSRCON1_EBSE_NOT_DELAYED 0x00200000
+/** Early Control Signals for Synchronous Bursts */
+#define BUSRCON1_ECSE 0x00100000
+/* Low active.
+#define BUSRCON1_ECSE_DELAYED 0x00000000 */
+/** High active */
+#define BUSRCON1_ECSE_NOT_DELAYED 0x00100000
+/** Synchronous Burst Buffer Mode Select */
+#define BUSRCON1_FBBMSEL 0x00080000
+/* FIXED_LENGTH
+#define BUSRCON1_FBBMSEL_FIXED_LENGTH 0x00000000 */
+/** CONTINUOUS */
+#define BUSRCON1_FBBMSEL_CONTINUOUS 0x00080000
+/** Burst Length for Synchronous Burst */
+#define BUSRCON1_FETBLEN_MASK 0x00070000
+/** field offset */
+#define BUSRCON1_FETBLEN_OFFSET 16
+/** Up to 1 data cycle (default after reset). */
+#define BUSRCON1_FETBLEN_SINGLE 0x00000000
+/** Up to 2 data cycles. */
+#define BUSRCON1_FETBLEN_BURST2 0x00010000
+/** Up to 4 data cycles. */
+#define BUSRCON1_FETBLEN_BURST4 0x00020000
+/** Up to 8 data cycles. */
+#define BUSRCON1_FETBLEN_BURST8 0x00030000
+/** Up to 16 data cycles. */
+#define BUSRCON1_FETBLEN_BURST16 0x00040000
+/** Reserved
+    This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */
+#define BUSRCON1_NANDAMAP_MASK 0x0000C000
+/** field offset */
+#define BUSRCON1_NANDAMAP_OFFSET 14
+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
+#define BUSRCON1_NANDAMAP_NAND_A17_16 0x00000000
+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
+#define BUSRCON1_NANDAMAP_NAND_WAIT_ADV 0x00004000
+/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */
+#define BUSRCON1_NANDAMAP_NAND_AD9_8 0x00008000
+/** Reserved for future use. Do not use or unpredictable results may occur. */
+#define BUSRCON1_NANDAMAP_NAND_RFU 0x0000C000
+/** AAD-mux Protocol
+    If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */
+#define BUSRCON1_AADMUX 0x00002000
+/* Muxed device is write accessed in AD-mux mode.
+#define BUSRCON1_AADMUX_AD_MUX 0x00000000 */
+/** Muxed device is write accessed in AAD-mux mode. */
+#define BUSRCON1_AADMUX_AAD_MUX 0x00002000
+/** Asynchronous Address Phase */
+#define BUSRCON1_AAP 0x00001000
+/* Clock is enabled at beginning of access.
+#define BUSRCON1_AAP_EARLY 0x00000000 */
+/** Clock is enabled after address phase. */
+#define BUSRCON1_AAP_LATE 0x00001000
+/** Burst Flash Read Single Stage Synchronisation */
+#define BUSRCON1_BFSSS 0x00000800
+/* Two stages of synchronisation used.
+#define BUSRCON1_BFSSS_TWO_STAGE 0x00000000 */
+/** Single stage of synchronisation used. */
+#define BUSRCON1_BFSSS_SINGLE_STAGE 0x00000800
+/** Burst Flash Clock Feedback Enable */
+#define BUSRCON1_FDBKEN 0x00000400
+/* Disable
+#define BUSRCON1_FDBKEN_DIS 0x00000000 */
+/** Enable */
+#define BUSRCON1_FDBKEN_EN 0x00000400
+/** Auxiliary Chip Select Enable
+    Not supported in GPON-EBU, field must be set to 0. */
+#define BUSRCON1_CSA 0x00000200
+/* Disable
+#define BUSRCON1_CSA_DIS 0x00000000 */
+/** Enable */
+#define BUSRCON1_CSA_EN 0x00000200
+/** Flash Non-Array Access Enable
+    Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */
+#define BUSRCON1_NAA 0x00000100
+/* Disable
+#define BUSRCON1_NAA_DIS 0x00000000 */
+/** Enable */
+#define BUSRCON1_NAA_EN 0x00000100
+/** Module Enable */
+#define BUSRCON1_ENABLE 0x00000001
+/* Disable
+#define BUSRCON1_ENABLE_DIS 0x00000000 */
+/** Enable */
+#define BUSRCON1_ENABLE_EN 0x00000001
+
+/* Fields of "Bus Read Parameters Register1" */
+/** Address Cycles
+    Number of cycles for address phase. */
+#define BUSRP1_ADDRC_MASK 0xF0000000
+/** field offset */
+#define BUSRP1_ADDRC_OFFSET 28
+/** Address Hold Cycles For Multiplexed Address
+    Number of address hold cycles during multiplexed accesses. */
+#define BUSRP1_ADHOLC_MASK 0x0F000000
+/** field offset */
+#define BUSRP1_ADHOLC_OFFSET 24
+/** Programmed Command Delay Cycles
+    Number of delay cycles during command delay phase. */
+#define BUSRP1_CMDDELAY_MASK 0x00F00000
+/** field offset */
+#define BUSRP1_CMDDELAY_OFFSET 20
+/** Extended Data */
+#define BUSRP1_EXTDATA_MASK 0x000C0000
+/** field offset */
+#define BUSRP1_EXTDATA_OFFSET 18
+/** External device outputs data every BFCLK cycle */
+#define BUSRP1_EXTDATA_ONE 0x00000000
+/** External device outputs data every 2nd BFCLK cycles */
+#define BUSRP1_EXTDATA_TWO 0x00040000
+/** External device outputs data every 4th BFCLK cycles */
+#define BUSRP1_EXTDATA_FOUR 0x00080000
+/** External device outputs data every 8th BFCLK cycles */
+#define BUSRP1_EXTDATA_EIGHT 0x000C0000
+/** Frequency of external clock at pin BFCLKO */
+#define BUSRP1_EXTCLOCK_MASK 0x00030000
+/** field offset */
+#define BUSRP1_EXTCLOCK_OFFSET 16
+/** Equal to ebu_clk frequency. */
+#define BUSRP1_EXTCLOCK_ONE_TO_ONE 0x00000000
+/** 1/2 of ebu_clk frequency. */
+#define BUSRP1_EXTCLOCK_ONE_TO_TWO 0x00010000
+/** 1/3 of ebu_clk frequency. */
+#define BUSRP1_EXTCLOCK_ONE_TO_THREE 0x00020000
+/** 1/4 of ebu_clk frequency (default after reset). */
+#define BUSRP1_EXTCLOCK_ONE_TO_FOUR 0x00030000
+/** Data Hold Cycles For read Accesses
+    Number of data hold cycles during read accesses. Applies to spinner support only where the address is guaranteed stable for datac clocks after RD high */
+#define BUSRP1_DATAC_MASK 0x0000F000
+/** field offset */
+#define BUSRP1_DATAC_OFFSET 12
+/** Programmed Wait States for read accesses
+    Number of programmed wait states for read accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */
+#define BUSRP1_WAITRDC_MASK 0x00000F80
+/** field offset */
+#define BUSRP1_WAITRDC_OFFSET 7
+/** Recovery Cycles After read Accesses, same CS
+    Number of idle cycles after read accesses when the next access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */
+#define BUSRP1_RECOVC_MASK 0x00000070
+/** field offset */
+#define BUSRP1_RECOVC_OFFSET 4
+/** Recovery Cycles After read Accesses, other CS
+    Number of idle cycles after read accesses when the next access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */
+#define BUSRP1_DTACS_MASK 0x0000000F
+/** field offset */
+#define BUSRP1_DTACS_OFFSET 0
+
+/* Fields of "Bus Write Configuration Register1" */
+/** Device Type For Region
+    After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */
+#define BUSWCON1_AGEN_MASK 0xF0000000
+/** field offset */
+#define BUSWCON1_AGEN_OFFSET 28
+/** Muxed Asynchronous Type External Memory */
+#define BUSWCON1_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000
+/** Muxed Burst Type External Memory */
+#define BUSWCON1_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000
+/** NAND Flash (page optimised) */
+#define BUSWCON1_AGEN_NAND_FLASH 0x20000000
+/** Muxed Cellular RAM External Memory */
+#define BUSWCON1_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000
+/** Demuxed Asynchronous Type External Memory */
+#define BUSWCON1_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000
+/** Demuxed Burst Type External Memory */
+#define BUSWCON1_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000
+/** Demuxed Page Mode External Memory */
+#define BUSWCON1_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000
+/** Demuxed Cellular RAM External Memory */
+#define BUSWCON1_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000
+/** Serial Flash */
+#define BUSWCON1_AGEN_SERIAL_FLASH 0xF0000000
+/** Device Addressing Mode
+    t.b.d. */
+#define BUSWCON1_PORTW_MASK 0x0C000000
+/** field offset */
+#define BUSWCON1_PORTW_OFFSET 26
+/** External Wait Control
+    Function of the WAIT input. This is specific to the device type (i.e. the agen field). */
+#define BUSWCON1_WAIT_MASK 0x03000000
+/** field offset */
+#define BUSWCON1_WAIT_OFFSET 24
+/** WAIT is ignored (default after reset). */
+#define BUSWCON1_WAIT_OFF 0x00000000
+/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */
+#define BUSWCON1_WAIT_EARLY_WAIT 0x01000000
+/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */
+#define BUSWCON1_WAIT_TWO_STAGE_SYNC 0x01000000
+/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */
+#define BUSWCON1_WAIT_WAIT_WITH_DATA 0x02000000
+/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */
+#define BUSWCON1_WAIT_SINGLE_STAGE_SYNC 0x02000000
+/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */
+#define BUSWCON1_WAIT_ABORT_AND_RETRY 0x03000000
+/** Reserved */
+#define BUSWCON1_LOCKCS 0x00800000
+/** Reversed polarity at wait */
+#define BUSWCON1_WAITINV 0x00400000
+/* Low active.
+#define BUSWCON1_WAITINV_ACTLOW 0x00000000 */
+/** High active */
+#define BUSWCON1_WAITINV_ACTHI 0x00400000
+/** Early ADV Enable for Synchronous Bursts */
+#define BUSWCON1_EBSE 0x00200000
+/* Low active.
+#define BUSWCON1_EBSE_DELAYED 0x00000000 */
+/** High active */
+#define BUSWCON1_EBSE_NOT_DELAYED 0x00200000
+/** Early Control Signals for Synchronous Bursts */
+#define BUSWCON1_ECSE 0x00100000
+/* Low active.
+#define BUSWCON1_ECSE_DELAYED 0x00000000 */
+/** High active */
+#define BUSWCON1_ECSE_NOT_DELAYED 0x00100000
+/** Synchronous Burst Buffer Mode Select */
+#define BUSWCON1_FBBMSEL 0x00080000
+/* FIXED_LENGTH
+#define BUSWCON1_FBBMSEL_FIXED_LENGTH 0x00000000 */
+/** CONTINUOUS */
+#define BUSWCON1_FBBMSEL_CONTINUOUS 0x00080000
+/** Burst Length for Synchronous Burst */
+#define BUSWCON1_FETBLEN_MASK 0x00070000
+/** field offset */
+#define BUSWCON1_FETBLEN_OFFSET 16
+/** Up to 1 data cycle (default after reset). */
+#define BUSWCON1_FETBLEN_SINGLE 0x00000000
+/** Up to 2 data cycles. */
+#define BUSWCON1_FETBLEN_BURST2 0x00010000
+/** Up to 4 data cycles. */
+#define BUSWCON1_FETBLEN_BURST4 0x00020000
+/** Up to 8 data cycles. */
+#define BUSWCON1_FETBLEN_BURST8 0x00030000
+/** Up to 16 data cycles. */
+#define BUSWCON1_FETBLEN_BURST16 0x00040000
+/** Reserved
+    This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */
+#define BUSWCON1_NANDAMAP_MASK 0x0000C000
+/** field offset */
+#define BUSWCON1_NANDAMAP_OFFSET 14
+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
+#define BUSWCON1_NANDAMAP_NAND_A17_16 0x00000000
+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
+#define BUSWCON1_NANDAMAP_NAND_WAIT_ADV 0x00004000
+/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */
+#define BUSWCON1_NANDAMAP_NAND_AD9_8 0x00008000
+/** Reserved for future use. Do not use or unpredictable results may occur. */
+#define BUSWCON1_NANDAMAP_NAND_RFU 0x0000C000
+/** AAD-mux Protocol
+    If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */
+#define BUSWCON1_AADMUX 0x00002000
+/* Muxed device is write accessed in AD-mux mode.
+#define BUSWCON1_AADMUX_AD_MUX 0x00000000 */
+/** Muxed device is write accessed in AAD-mux mode. */
+#define BUSWCON1_AADMUX_AAD_MUX 0x00002000
+/** Asynchronous Address Phase */
+#define BUSWCON1_AAP 0x00001000
+/* Clock is enabled at beginning of access.
+#define BUSWCON1_AAP_EARLY 0x00000000 */
+/** Clock is enabled after address phase. */
+#define BUSWCON1_AAP_LATE 0x00001000
+/** Auxiliary Chip Select Enable
+    Not supported in GPON-EBU, field must be set to 0. */
+#define BUSWCON1_CSA 0x00000200
+/* Disable
+#define BUSWCON1_CSA_DIS 0x00000000 */
+/** Enable */
+#define BUSWCON1_CSA_EN 0x00000200
+/** Flash Non-Array Access Enable
+    Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */
+#define BUSWCON1_NAA 0x00000100
+/* Disable
+#define BUSWCON1_NAA_DIS 0x00000000 */
+/** Enable */
+#define BUSWCON1_NAA_EN 0x00000100
+/** Module Enable */
+#define BUSWCON1_ENABLE 0x00000001
+/* Disable
+#define BUSWCON1_ENABLE_DIS 0x00000000 */
+/** Enable */
+#define BUSWCON1_ENABLE_EN 0x00000001
+
+/* Fields of "Bus Write Parameters Register1" */
+/** Address Cycles
+    Number of cycles for address phase. */
+#define BUSWP1_ADDRC_MASK 0xF0000000
+/** field offset */
+#define BUSWP1_ADDRC_OFFSET 28
+/** Address Hold Cycles For Multiplexed Address
+    Number of address hold cycles during multiplexed accesses. */
+#define BUSWP1_ADHOLC_MASK 0x0F000000
+/** field offset */
+#define BUSWP1_ADHOLC_OFFSET 24
+/** Programmed Command Delay Cycles
+    Number of delay cycles during command delay phase. */
+#define BUSWP1_CMDDELAY_MASK 0x00F00000
+/** field offset */
+#define BUSWP1_CMDDELAY_OFFSET 20
+/** Extended Data */
+#define BUSWP1_EXTDATA_MASK 0x000C0000
+/** field offset */
+#define BUSWP1_EXTDATA_OFFSET 18
+/** External device outputs data every BFCLK cycle */
+#define BUSWP1_EXTDATA_ONE 0x00000000
+/** External device outputs data every 2nd BFCLK cycles */
+#define BUSWP1_EXTDATA_TWO 0x00040000
+/** External device outputs data every 4th BFCLK cycles */
+#define BUSWP1_EXTDATA_FOUR 0x00080000
+/** External device outputs data every 8th BFCLK cycles */
+#define BUSWP1_EXTDATA_EIGHT 0x000C0000
+/** Frequency of external clock at pin BFCLKO */
+#define BUSWP1_EXTCLOCK_MASK 0x00030000
+/** field offset */
+#define BUSWP1_EXTCLOCK_OFFSET 16
+/** Equal to ebu_clk frequency. */
+#define BUSWP1_EXTCLOCK_ONE_TO_ONE 0x00000000
+/** 1/2 of ebu_clk frequency. */
+#define BUSWP1_EXTCLOCK_ONE_TO_TWO 0x00010000
+/** 1/3 of ebu_clk frequency. */
+#define BUSWP1_EXTCLOCK_ONE_TO_THREE 0x00020000
+/** 1/4 of ebu_clk frequency (default after reset). */
+#define BUSWP1_EXTCLOCK_ONE_TO_FOUR 0x00030000
+/** Data Hold Cycles For write Accesses
+    Number of data hold cycles during write accesses. */
+#define BUSWP1_DATAC_MASK 0x0000F000
+/** field offset */
+#define BUSWP1_DATAC_OFFSET 12
+/** Programmed Wait States For write Accesses
+    Number of programmed wait states for write accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */
+#define BUSWP1_WAITWDC_MASK 0x00000F80
+/** field offset */
+#define BUSWP1_WAITWDC_OFFSET 7
+/** Recovery Cycles After write Accesses, same CS
+    Number of idle cycles after write accesses when following access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */
+#define BUSWP1_RECOVC_MASK 0x00000070
+/** field offset */
+#define BUSWP1_RECOVC_OFFSET 4
+/** Recovery Cycles After write Accesses, other CS
+    Number of idle cycles after write accesses when the following access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */
+#define BUSWP1_DTACS_MASK 0x0000000F
+/** field offset */
+#define BUSWP1_DTACS_OFFSET 0
+
+/* Fields of "Bus Protocol Configuration Extension Register 0" */
+/** Byte Control Mapping
+    Remapping of byte enable signals on address lines is not supported in the GPON-EBU. */
+#define BUSCONEXT0_BCMAP_MASK 0x00030000
+/** field offset */
+#define BUSCONEXT0_BCMAP_OFFSET 16
+/** No mirroring of byte enables. */
+#define BUSCONEXT0_BCMAP_NOBCMAP 0x00000000
+/** Asynchronous Early Write
+    This bit is obsolete and must be set to 0 or unpredictable results may result. */
+#define BUSCONEXT0_AEW 0x00008000
+/** AAD-mux Consecutive Address Cycles
+    This bit selects whether ADV gets deasserted between the high and the low address phase of a synchronous AAD-mux access or the two address cycles are consecutive. See Figure 32 for a waveform example that results when acac is set. acac only takes effect if the CS region is configured for synchronous AADmux access (agen = 1 or 3, aadmux = 1) and is ignored otherwise. */
+#define BUSCONEXT0_ACAC 0x00004000
+/* ADV is deasserted between high and low address phase.
+#define BUSCONEXT0_ACAC_SEPERATED 0x00000000 */
+/** ADV is not deasserted between high and low address phase. */
+#define BUSCONEXT0_ACAC_CONSECUTIVE 0x00004000
+/** AAD-mux Write Address-to-Address Delay
+    Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when writing to the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSWCON, fields agen and aadmux. */
+#define BUSCONEXT0_WAAC_MASK 0x00003800
+/** field offset */
+#define BUSCONEXT0_WAAC_OFFSET 11
+/** AAD-mux Read Address-to-Address Delay
+    Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when reading from the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSRCON, fields agen and aadmux. */
+#define BUSCONEXT0_RAAC_MASK 0x00000700
+/** field offset */
+#define BUSCONEXT0_RAAC_OFFSET 8
+/** AAD-mux Paging Enable for CS0
+    If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field selects whether or not to use paging. If paging is enabled, the EBU skips the high address cycle in case the upper address that would be sent are the same as in the most recent access to the device.configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */
+#define BUSCONEXT0_PAGE_EN 0x00000080
+/* Disable
+#define BUSCONEXT0_PAGE_EN_DIS 0x00000000 */
+/** Enable */
+#define BUSCONEXT0_PAGE_EN_EN 0x00000080
+/** AAD-mux Address Extension Bit Generation Mode
+    If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */
+#define BUSCONEXT0_AEBM_MASK 0x00000070
+/** field offset */
+#define BUSCONEXT0_AEBM_OFFSET 4
+/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 0 */
+#define BUSCONEXT0_AEBM_AMAP_CRE_RFU0 0x00000000
+/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 1 */
+#define BUSCONEXT0_AEBM_AMAP_CRE_RFU1 0x00000010
+/** A[15] in the high address cycle is set to AMemport[amsb+18], A[14] is set to AMemport[amsb+17] */
+#define BUSCONEXT0_AEBM_AMAP_CRE_AND_RFU 0x00000020
+/** Do not use */
+#define BUSCONEXT0_AEBM_reserved 0x00000030
+/** A[15:14] in the high address cycle is set to 00B. */
+#define BUSCONEXT0_AEBM_DIRECT_00 0x00000040
+/** A[15:14] in the high address cycle is set to 01B */
+#define BUSCONEXT0_AEBM_DIRECT_01 0x00000050
+/** A[15:14] in the high address cycle is set to 10B */
+#define BUSCONEXT0_AEBM_DIRECT_10 0x00000060
+/** A[15:14] in the high address cycle is set to 11B. */
+#define BUSCONEXT0_AEBM_DIRECT_11 0x00000070
+/** Most Significant Address Bit of External Device
+    If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then for amsb < 14 the EBU always sets A[13:amsb] = 0 in the high address cycle of an access. The value of A[15:14] is defined in field aebm. A value of amsb > 13 therefore has no effect. It is recommended to set amsb that it matches the addressable range of the external device according to the following formula: amsb = n - 16 for a device with 2n addressable words. */
+#define BUSCONEXT0_AMSB_MASK 0x0000000F
+/** field offset */
+#define BUSCONEXT0_AMSB_OFFSET 0
+
+/* Fields of "Bus Protocol Configuration Extension Register 1" */
+/** Byte Control Mapping
+    Remapping of byte enable signals on address lines is not supported in the GPON-EBU. */
+#define BUSCONEXT1_BCMAP_MASK 0x00030000
+/** field offset */
+#define BUSCONEXT1_BCMAP_OFFSET 16
+/** No mirroring of byte enables. */
+#define BUSCONEXT1_BCMAP_NOBCMAP 0x00000000
+/** Asynchronous Early Write
+    This bit is obsolete and must be set to 0 or unpredictable results may result. */
+#define BUSCONEXT1_AEW 0x00008000
+/** AAD-mux Consecutive Address Cycles
+    This bit selects whether ADV gets deasserted between the high and the low address phase of a synchronous AAD-mux access or the two address cycles are consecutive. See Figure 32 for a waveform example that results when acac is set. acac only takes effect if the CS region is configured for synchronous AADmux access (agen = 1 or 3, aadmux = 1) and is ignored otherwise. */
+#define BUSCONEXT1_ACAC 0x00004000
+/* ADV is deasserted between high and low address phase.
+#define BUSCONEXT1_ACAC_SEPERATED 0x00000000 */
+/** ADV is not deasserted between high and low address phase. */
+#define BUSCONEXT1_ACAC_CONSECUTIVE 0x00004000
+/** AAD-mux Write Address-to-Address Delay
+    Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when writing to the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSWCON, fields agen and aadmux. */
+#define BUSCONEXT1_WAAC_MASK 0x00003800
+/** field offset */
+#define BUSCONEXT1_WAAC_OFFSET 11
+/** AAD-mux Read Address-to-Address Delay
+    Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when reading from the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSRCON, fields agen and aadmux. */
+#define BUSCONEXT1_RAAC_MASK 0x00000700
+/** field offset */
+#define BUSCONEXT1_RAAC_OFFSET 8
+/** AAD-mux Paging Enable for CS0
+    If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field selects whether or not to use paging. If paging is enabled, the EBU skips the high address cycle in case the upper address that would be sent are the same as in the most recent access to the device.configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */
+#define BUSCONEXT1_PAGE_EN 0x00000080
+/* Disable
+#define BUSCONEXT1_PAGE_EN_DIS 0x00000000 */
+/** Enable */
+#define BUSCONEXT1_PAGE_EN_EN 0x00000080
+/** AAD-mux Address Extension Bit Generation Mode
+    If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */
+#define BUSCONEXT1_AEBM_MASK 0x00000070
+/** field offset */
+#define BUSCONEXT1_AEBM_OFFSET 4
+/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 0 */
+#define BUSCONEXT1_AEBM_AMAP_CRE_RFU0 0x00000000
+/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 1 */
+#define BUSCONEXT1_AEBM_AMAP_CRE_RFU1 0x00000010
+/** A[15] in the high address cycle is set to AMemport[amsb+18], A[14] is set to AMemport[amsb+17] */
+#define BUSCONEXT1_AEBM_AMAP_CRE_AND_RFU 0x00000020
+/** Do not use */
+#define BUSCONEXT1_AEBM_reserved 0x00000030
+/** A[15:14] in the high address cycle is set to 00B. */
+#define BUSCONEXT1_AEBM_DIRECT_00 0x00000040
+/** A[15:14] in the high address cycle is set to 01B */
+#define BUSCONEXT1_AEBM_DIRECT_01 0x00000050
+/** A[15:14] in the high address cycle is set to 10B */
+#define BUSCONEXT1_AEBM_DIRECT_10 0x00000060
+/** A[15:14] in the high address cycle is set to 11B. */
+#define BUSCONEXT1_AEBM_DIRECT_11 0x00000070
+/** Most Significant Address Bit of External Device
+    If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then for amsb < 14 the EBU always sets A[13:amsb] = 0 in the high address cycle of an access. The value of A[15:14] is defined in field aebm. A value of amsb > 13 therefore has no effect. It is recommended to set amsb that it matches the addressable range of the external device according to the following formula: amsb = n - 16 for a device with 2n addressable words. */
+#define BUSCONEXT1_AMSB_MASK 0x0000000F
+/** field offset */
+#define BUSCONEXT1_AMSB_OFFSET 0
+
+/* Fields of "Serial Flash Configuration Register" */
+/** Direct Access Device Port Width
+    DA_PORTW Defines the number of signal lines to be used with direct read access from a Serial Flash as defined for the command with opcode rd_opc. Depending on thedevice type and/or command, the number of used signal lines might differbetween command, address, and data phase of the transaction. */
+#define SFCON_DA_PORTW_MASK 0xE0000000
+/** field offset */
+#define SFCON_DA_PORTW_OFFSET 29
+/** One signal line used in all phases of the transaction. */
+#define SFCON_DA_PORTW_WIDTH_1_1_1 0x00000000
+/** One signal line used in the COMMAND and ADDRESS phase of the transaction and two signal lines used in the DATA phase. */
+#define SFCON_DA_PORTW_WIDTH_1_1_2 0x20000000
+/** One signal used in the COMMAND phase of the transaction and two signal lines used in the ADDRESS/DUMMY phase and the DATA phase. */
+#define SFCON_DA_PORTW_WIDTH_1_2_2 0x40000000
+/** Two signal lines used in all phases of the transaction. */
+#define SFCON_DA_PORTW_WIDTH_2_2_2 0x60000000
+/** One signal line used in the COMMAND and ADDRESS phase of the transaction and four signal lines used in the DATA phase. */
+#define SFCON_DA_PORTW_WIDTH_1_1_4 0x80000000
+/** One signal used in the COMMAND phase of the transaction and four signal lines used in the ADDRESS/DUMMY phase and the DATA phase. */
+#define SFCON_DA_PORTW_WIDTH_1_4_4 0xA0000000
+/** Four signal lines used in all phases of the transaction. */
+#define SFCON_DA_PORTW_WIDTH_4_4_4 0xC0000000
+/** for future use. */
+#define SFCON_DA_PORTW_WIDTH_reserved 0xE0000000
+/** Read Abort Enable
+    If set, a read access from the external device can be aborted via signal sf_rd_abort_i. See Section 3.18.2.9 for details. */
+#define SFCON_RD_ABORT_EN 0x10000000
+/** Device Size
+    Defines the number of significant address bits for the Serial Flash device(s). All address bits above the MSB are forced to 0. The configuration in this field also defines for the address auto-increment feature when to wrap around from the upper most address to 0. */
+#define SFCON_DEV_SIZE_MASK 0x0F000000
+/** field offset */
+#define SFCON_DEV_SIZE_OFFSET 24
+/** 16 MBit device */
+#define SFCON_DEV_SIZE_A20_0 0x00000000
+/** 32 MBit device */
+#define SFCON_DEV_SIZE_A21_0 0x01000000
+/** 64 MBit device */
+#define SFCON_DEV_SIZE_A22_0 0x02000000
+/** 128 MBit device */
+#define SFCON_DEV_SIZE_A23_0 0x03000000
+/** 256 MBit device */
+#define SFCON_DEV_SIZE_A24_0 0x04000000
+/** 512 MBit device */
+#define SFCON_DEV_SIZE_A25_0 0x05000000
+/** 1 GBit device */
+#define SFCON_DEV_SIZE_A26_0 0x06000000
+/** 2 GBit device */
+#define SFCON_DEV_SIZE_A27_0 0x07000000
+/** 4 GBit device */
+#define SFCON_DEV_SIZE_A28_0 0x08000000
+/** 8 GBit device */
+#define SFCON_DEV_SIZE_A29_0 0x09000000
+/** 16 GBit device */
+#define SFCON_DEV_SIZE_A30_0 0x0A000000
+/** 32 GBit device */
+#define SFCON_DEV_SIZE_A31_0 0x0B000000
+/** Device Page Size
+    Defines the page size employed by all connected Serial Flash devices. The device page size is used to determine the address wrap-around for the write address auto-increment feature. */
+#define SFCON_DPS_MASK 0x00C00000
+/** field offset */
+#define SFCON_DPS_OFFSET 22
+/** Device page size is 256 Bytes */
+#define SFCON_DPS_DPS_256 0x00000000
+/** Device page size is 512 Bytes */
+#define SFCON_DPS_DPS_512 0x00400000
+/** Page Buffer Size
+    Defines the size of the EBU's page buffer used in Buffered Access. Page buffer size configured here must be less than or equal to the maximum page buffer size which is a built option of the EBU (256 Bytes for GPON). */
+#define SFCON_PB_SIZE_MASK 0x00300000
+/** field offset */
+#define SFCON_PB_SIZE_OFFSET 20
+/** No read buffer is available/used. */
+#define SFCON_PB_SIZE_NONE 0x00000000
+/** 128 Bytes */
+#define SFCON_PB_SIZE_SIZE_128 0x00100000
+/** 256 Bytes */
+#define SFCON_PB_SIZE_SIZE_256 0x00200000
+/** Bidirectional Data Bus
+    Defines whether the Serial Flash uses a unidirectional or a bidirectional data bus. */
+#define SFCON_BIDIR 0x00080000
+/* The Serial Flash interface uses a pair of two unidirectional busses (one for write, one for read)
+#define SFCON_BIDIR_UNIDIRECTIONAL 0x00000000 */
+/** The Serial Flash interface uses a bidirectional data bus. */
+#define SFCON_BIDIR_BIDIRECTIONAL 0x00080000
+/** No Busy Error termination
+    By default, the EBU error-terminates all direct access to a Serial Flash while EBU_SFSTAT.busy is set. By setting NO_BUSY_ERR, the EBU can be configured to permit direct accesses to proceed to the Serial Flash, e.g. for devices that support a read-while-write functionality. */
+#define SFCON_NO_BUSY_ERR 0x00040000
+/** End-of-Busy Detection Mode
+    Defines how the EBU detects the end of a busy phase in the Serial Flash device. The current version of the EBU requires the software to explicitly poll the device's status register and then inform the EBU on the end of the busy status by clearing the corresponding bit in register EBU_SF_STAT. */
+#define SFCON_EOBDM_MASK 0x00030000
+/** field offset */
+#define SFCON_EOBDM_OFFSET 16
+/** No read buffer is available/used. */
+#define SFCON_EOBDM_SOFTWARE 0x00000000
+/** Poll device status register (not supported yet) */
+#define SFCON_EOBDM_POLL_SR 0x00010000
+/** Poll devices busy/ready pin fed into EBU via WAIT pin (not supported yet). */
+#define SFCON_EOBDM_POLL_RDY 0x00020000
+/** Same as POLL_RDY, but CS must be asserted to have the device output its busy/ready status (not supported yet). */
+#define SFCON_EOBDM_POLL_RDY_WITH_CS 0x00030000
+/** Direct Access Keep Chip Select
+    Defines whether the Serial Flash remains selected after a direct access transaction has been finished. */
+#define SFCON_DA_KEEP_CS 0x00008000
+/* After a direct read access, the Serial Flash device is always deselected (CS deasserted). Follow-up read accesses always require sending command opcode and address.
+#define SFCON_DA_KEEP_CS_DESELECT 0x00000000 */
+/** Chip Select of device is kept active after direct read access so that device is ready for follow-up read of next sequential byte without the need to send command and address. If the next command is to another Chip Select, is a different command or accesses a different address, the EBU first deactivates the kept Chip Select before it starts the new transaction with sending the command opcode and address. */
+#define SFCON_DA_KEEP_CS_KEEP_SELECTED 0x00008000
+/** Early Read Abort Enable
+    When aborting a Serial Flash Read is enabled in bit EBU_SFCON.rd_abort_en, bit early_abort selects at what point in the protocol an external access might be aborted. Datasheets of many Serial Flash devices are not explicit on what happens (and whether it is allowed) when a read access is cut-short by deselecting the device during the CMD, ADDR or DUMMY phase of the protocol. */
+#define SFCON_EARLY_ABORT 0x00004000
+/* DISABLE Early abortion is disabled (default after reset). Once the EBU has started the access on the External Bus (first bit time slot), the EBU continues the external transfer until the first data byte has been received. After a direct read access, the Serial Flash device is always deselected (CS deasserted). Follow-up read accesses always require sending command opcode and address.
+#define SFCON_EARLY_ABORT_DISABLE 0x00000000 */
+/** Early abortion is not yet supported in the current version of the EBU. Do not use. The feature is a late improvement to the EBU and could not be verified completely before the final release. After proven to work, it should be made officially available to reduce access latency after aborted Serial Flash reads. Setting early_abort to ENABLE alters the read abort handling in the following way: Once the EBU has started the access on the External Bus, the transfer is cut-short after transferring the CMD byte, the three address bytes, any DUMMY bits or at the end of the next data byte - whatever comes first. */
+#define SFCON_EARLY_ABORT_ENABLE 0x00004000
+/** Direct Access Address Length
+    Defines the number of address bytes to be sent (MSB first) to the device with a direct read access transaction. Other values than listed below are not supported and have unpredictable results. */
+#define SFCON_DA_ALEN_MASK 0x00003000
+/** field offset */
+#define SFCON_DA_ALEN_OFFSET 12
+/** 3 address bytes (bits 23:0 of the internal address) */
+#define SFCON_DA_ALEN_THREE 0x00000000
+/** Read Access Dummy Bytes
+    This field defines the number of dummy bytes to send between the last address byte before the EBU starts capturing read data from the bus for a direct read access. The number of dummy bytes depends on the data access command being used (see field), the clock frequency and the type of device being used. */
+#define SFCON_RD_DUMLEN_MASK 0x00000F00
+/** field offset */
+#define SFCON_RD_DUMLEN_OFFSET 8
+/** Direct Read Access Command Opcode
+    This byte defines the command opcode to send when performing a data read from the Serial Flash in Direct Access Mode. Any value can be set (the EBU does not interpret the value, but directly uses the contents of this register field in the command phase of the transaction). Common opcodes to be used and understood by most devices are READ (03H) and FAST_READ (0BH), but some devices might provide additional opcodes, e.g. to support higher clock frequencies requiring additional dummy bytes or to define a wider interface bus. */
+#define SFCON_RD_OPC_MASK 0x000000FF
+/** field offset */
+#define SFCON_RD_OPC_OFFSET 0
+/** READ */
+#define SFCON_RD_OPC_READ 0x00000003
+/** FAST_READ */
+#define SFCON_RD_OPC_FAST_READ 0x0000000B
+
+/* Fields of "Serial Flash Timing Register" */
+/** CS Idle time
+    This field defines the minimum time the device's Chip Select has to be deasserted in between accesses. Most devices require a minimum deselect time between 50 and 100 ns. See Table 43 for the encoding used in this field. */
+#define SFTIME_CS_IDLE_MASK 0xF0000000
+/** field offset */
+#define SFTIME_CS_IDLE_OFFSET 28
+/** 1 EBU clock cycles */
+#define SFTIME_CS_IDLE_CLKC_0 0x00000000
+/** 2 EBU clock cycles */
+#define SFTIME_CS_IDLE_CLKC_1 0x10000000
+/** 3 EBU clock cycles */
+#define SFTIME_CS_IDLE_CLKC_2 0x20000000
+/** 4 EBU clock cycles */
+#define SFTIME_CS_IDLE_CLKC_3 0x30000000
+/** 6 EBU clock cycles */
+#define SFTIME_CS_IDLE_CLKC_4 0x40000000
+/** 8 EBU clock cycles */
+#define SFTIME_CS_IDLE_CLKC_5 0x50000000
+/** 10 EBU clock cycles */
+#define SFTIME_CS_IDLE_CLKC_6 0x60000000
+/** 12 EBU clock cycles */
+#define SFTIME_CS_IDLE_CLKC_7 0x70000000
+/** 14 EBU clock cycles */
+#define SFTIME_CS_IDLE_CLKC_8 0x80000000
+/** 16 EBU clock cycles */
+#define SFTIME_CS_IDLE_CLKC_9 0x90000000
+/** 20 EBU clock cycles */
+#define SFTIME_CS_IDLE_CLKC_10 0xA0000000
+/** 24 EBU clock cycles */
+#define SFTIME_CS_IDLE_CLKC_11 0xB0000000
+/** 32 EBU clock cycles */
+#define SFTIME_CS_IDLE_CLKC_12 0xC0000000
+/** 40 EBU clock cycles */
+#define SFTIME_CS_IDLE_CLKC_13 0xD0000000
+/** 48 EBU clock cycles */
+#define SFTIME_CS_IDLE_CLKC_14 0xE0000000
+/** 64 EBU clock cycles */
+#define SFTIME_CS_IDLE_CLKC_15 0xF0000000
+/** CS Hold time
+    This field defines (in multiples of the EBU internal clock's period) the minimum time the device's Chip Select must remain asserted after transfer of the last bit of a write transaction. This CS hold time does not apply to read accesses */
+#define SFTIME_CS_HOLD_MASK 0x0C000000
+/** field offset */
+#define SFTIME_CS_HOLD_OFFSET 26
+/** CS Setup time
+    This field defines (in multiples of the EBU internal clock's period) when to assert the device's Chip Select before the first SCK clock period for transferring the command is started on the External Bus */
+#define SFTIME_CS_SETUP_MASK 0x03000000
+/** field offset */
+#define SFTIME_CS_SETUP_OFFSET 24
+/** Write-to-Read Pause
+    This field defines the length of the optional pause when switching from write to read direction in the transaction. During this pause, SCK is held stable. */
+#define SFTIME_WR2RD_PAUSE_MASK 0x00300000
+/** field offset */
+#define SFTIME_WR2RD_PAUSE_OFFSET 20
+/** Read Data Position
+    This field defines when to capture valid read data bit(s) (in multiples of half of the EBU internal clock's period) relative to the beginning of the SCK clock's period defined in EBU_SFTIME.sck_per. RD_POS must be less than or equal to EBU_SFTIME.sck_per (not checked in hardware) or unpredictable results may occur. */
+#define SFTIME_RD_POS_MASK 0x000F0000
+/** field offset */
+#define SFTIME_RD_POS_OFFSET 16
+/** SCK Fall-edge Position
+    This field defines the positioning of the SCK fall edge (in multiples of half of the EBU internal clock's period) with respect to the beginning of the SCK clock's period defined in EBU_SFTIME.sck_per. SCKF_POS must be less than or equal to SCK_PER (not checked in hardware) or unpredictable results may occur. If EBU_SFTIME.sck_inv is set, SCKF_POS defines the positioning of the falling instead of the rising edge of SCK. In the current version of the EBU, SCKF_POS must be set 0 or unpredictable results may occur. */
+#define SFTIME_SCKF_POS_MASK 0x0000F000
+/** field offset */
+#define SFTIME_SCKF_POS_OFFSET 12
+/** SCK Rise-edge Position
+    This field defines the positioning of the SCK rise edge (in multiples of half of the EBU internal clock's period) with respect to the beginning of the SCK clock's period defined in EBU_SFTIME.sck_per. SCKR_POS must be less than EBU_SFTIME.sck_per (not checked in hardware) or unpredictable results may occur. If EBU_SFTIME.sck_inv is set, SCKR_POS defines the positioning of the falling instead of the rising edge of SCK. */
+#define SFTIME_SCKR_POS_MASK 0x00000F00
+/** field offset */
+#define SFTIME_SCKR_POS_OFFSET 8
+/** SCK Feedback Clock Inversion
+    If set, read data gets captured with the falling instead of the rising edge of SCK if clock feedback is enabled in EBU_SFTIME.sck_fdbk_en. */
+#define SFTIME_SCK_FDBK_INV 0x00000040
+/** SCK Clock Feedback
+    If set, read data is captured using the external SCK clock feedback into the chip instead of the EBU's internal clock. Using the feedback clock compensate for the high delay over the pads and its use is required at higher frequencies. A penalty for synchronizing the read data from the SCK into the ebu_clk domain applies to the read access latency. */
+#define SFTIME_SCK_FDBK_EN 0x00000020
+/** Inverted SCK
+    If set, the clock to the Serial Flash devices is inverted. This also results in SCK high while a Serial Flash remains selected between transactions (keep_cs feature). In the current version of the EBU, clock inversion is not supported. SCK_INV must be set to 0 or unpredictable results may occur. */
+#define SFTIME_SCK_INV 0x00000010
+/** SCK Period
+    This field defines the period of the SCK clock in multiples of half of the EBU clock period. The EBU supports values between 2 and 14, corresponding to a frequency ratio range from 1:1. to 1:7 between SCK and the internal clock. Other values are prohibited and result in unpredictable behaviour. In the current version of the EBU, odd values for SCK_PER are not supported. */
+#define SFTIME_SCK_PER_MASK 0x0000000F
+/** field offset */
+#define SFTIME_SCK_PER_OFFSET 0
+
+/* Fields of "Serial Flash Status Register" */
+/** Command Overwrite Error
+    This bit is set on an attempt to start an indirect access while a previous indirect access has not finished. The bit remains unaltered when the software writes a '0' and is toggled when a '1' is written. This toggle-by-write-1 behavior allows to also set the bit for testing purposes. In normal operation, the software is supposed to only write a '1' to this bit to clear after it has been set by the Serial Flash protocol engine. */
+#define SFSTAT_CMD_OVWRT_ERR 0x40000000
+/** Command Error
+    This bit is set when the EBU discards an indirect or direct access to/from a Serial Flash. The bit remains unaltered when the software writes a '0' and is toggled when a '1' is written. This toggle-by-write-1 behavior allows to also set the bit for testing purposes. In normal operation, the software is supposed to only write a '1' to this bit to clear after it has been set by the Serial Flash protocol engine. */
+#define SFSTAT_CMD_ERR 0x20000000
+/** Access Command Pending
+    If set, indicates that access from/to a Serial Flash device has not finished yet. */
+#define SFSTAT_CMD_PEND 0x00400000
+/** External Device Selected
+    If set, indicates that the Chip Select of a Serial Flash device is currently active on the External Bus. */
+#define SFSTAT_SELECTED 0x00200000
+/** Protocol Engine Active
+    If set, indicates that the EBU's Serial Flash protocol engine is active. */
+#define SFSTAT_ACTIVE 0x00100000
+/** Page Buffer Invalidate
+    When writing a one to this bit, bits PB_VALID and PB_UPDATE are both cleared, thereby invalidating the page buffer for access to/from the Serial Flash device. After invalidating the buffer, PB_INVALID is automatically cleared so that it always reads as 0. */
+#define SFSTAT_PB_INVALID 0x00010000
+/** Page Buffer Update
+    This bit is set when data in the page buffer gets modified. It is cleared when new data gets loaded to the page buffer, when it is written back to the device (WRITE_PAGE command) or when PB_VALID gets cleared. */
+#define SFSTAT_PB_UPDATE 0x00002000
+/** Page Buffer Valid
+    This bit is set after the last data byte of a LOAD_PAGE command has been stored in the page buffer or when the page buffer is explicitely validated via a VALIDATE_PAGE special command. It remains set until the page buffer gets invalidated by writing a 1 to PB_INVALID or any of the LOAD_PAGE special commands. While PB_VALID is set, all accesses to the buffered address range are diverted to the page buffer with no access being performed on the External Bus. */
+#define SFSTAT_PB_VALID 0x00001000
+/** Page Buffer Busy
+    The bit is set when the EBU starts executing a LOAD_PAGE or a WRITE_PAGE command and cleared when the last byte of the requested page has been transferred from/to the external device. The inverted value of PB_BUSY is output on the EBU interface and may trigger a system interrupt. */
+#define SFSTAT_PB_BUSY 0x00000100
+/** Device Busy
+    This bit is set by the Serial Flash protocol engine when an indirect access is performed via register EBU_SFCMD with SET_BUSY being set. While busy is set, access to the Serial Flash is very limited and all transactions are error-terminated except when explicitly marked to ignore the busy status. If the EBU is configured in EBU_SFCON.EOBDM to automatically poll the busy status of the device, busy is cleared as soon as the device is found to be idle again. On a software write, busy remains unaltered when written with a '0' and is toggled when written with a '1', respectively.This toggle-by-write-1 behaviour allows to also set the bit for testing purposes. In normal operation, the software is supposed to only write a '1' to this bit after it got set by the Serial Flash protocol engine and no automatic busy detection is configured in EBU_SFCON.EOBDM Then the software has to clear busy when it finds the device to be no longer busy by either polling the device's status register via the EBU or by waiting for the maximum busy time of the operation started in the device. */
+#define SFSTAT_BUSY 0x00000001
+
+/* Fields of "Serial Flash Command Register" */
+/** Command Type
+    This field is a qualifier of the command opcode in EBU_SFCMD.opc. Two types */
+#define SFCMD_CMDTYPE 0x80000000
+/* The opcode in EBU_SFCMD.opc is directly used in the command phase of a single transaction to the Serial Flash device.
+#define SFCMD_CMDTYPE_ACCESS_CMD 0x00000000 */
+/** The opcode in EBU_SFCMD.opc is used to start a special command in the Serial Flash Controller which might include any number of external transactions to/from the Serial Flash device. */
+#define SFCMD_CMDTYPE_SPECIAL_CMD 0x80000000
+/** Device Port Width
+    Defines the number of signal lines to be used with direct read access from a Serial Flash as defined for the command with opcode opc. The encoding of this field is the same as forDA_PORTW. */
+#define SFCMD_PORTW_MASK 0x70000000
+/** field offset */
+#define SFCMD_PORTW_OFFSET 28
+/** Bidirectional Signal Lines
+    If set selects bidirectional signal lines to be used for the data transfer. */
+#define SFCMD_BIDIR 0x08000000
+/** Chip Select
+    This field selects which of the EBU's Chip Selects to activated for the command that is written to EBU_SFCMD.opc. A value between 0 and 3 selects one of the EBU's main CSs while 4 to 7 chooses one of the Auxiliary Chip Selects CSA[3:0], respectively. */
+#define SFCMD_CS_MASK 0x07000000
+/** field offset */
+#define SFCMD_CS_OFFSET 24
+/** Disable Auto Address Increment
+    By default, the address in register EBU_SFADDR is automatically incremented with each data byte being transferred. By setting this bit, the auto-increment can be disabled. */
+#define SFCMD_DIS_AAI 0x00800000
+/** Address Length
+    Defines the number of address bytes from register EBU_SFADDR to sent in the address phase of the transaction to/from the Serial Flash. Note: Address bytes are also sent when the command has no data. */
+#define SFCMD_ALEN_MASK 0x00700000
+/** field offset */
+#define SFCMD_ALEN_OFFSET 20
+/** Dummy Phase Length
+    Defines the number of dummy bytes to send to the device between the command/address phase and the data phase of a transaction. Note:Dummy bytes are also sent when the command has no address and/or no data. */
+#define SFCMD_DUMLEN_MASK 0x000F0000
+/** field offset */
+#define SFCMD_DUMLEN_OFFSET 16
+/** Keep Chip Select
+    Defines whether the Serial Flash remains selected after the indirect access transaction has been finished. */
+#define SFCMD_KEEP_CS 0x00008000
+/* After a direct read access, the Serial Flash device is always deselected (CS deasserted). Follow-up read accesses always require sending command opcode and address.
+#define SFCMD_KEEP_CS_DESELECT 0x00000000 */
+/** Chip Select of device is kept active after direct read access so that device is ready for follow-up read of next sequential byte without the need to send command and address. If the next command is to another Chip Select, is a different command or accesses a different address, the EBU first deactivates the kept Chip Select before it starts the new transaction with sending the command opcode and address. */
+#define SFCMD_KEEP_CS_KEEP_SELECTED 0x00008000
+/** Set Busy Flag
+    If set, starting the command sets EBU_SFSTAT.busy. */
+#define SFCMD_SET_BUSY 0x00004000
+/** Ignore Busy
+    By default, the EBU error terminates all attempts to access a Serial Flash while EBU_SFSTAT.busy is set. Setting this bit overrules this error termination and permits the command written to EBU_SFCMD.opc to proceed to the External Bus. Normally, this bit is only set to execute a Read Status Register command to the Serial Flash, but may also be used for any other type of access the device is able to handle while it is busy. */
+#define SFCMD_IGNORE_BUSY 0x00002000
+/** Skip Opcode
+    If this bit is set, the opcode in field OPC is not sent to the External Bus, but the external transaction starts with sending the first address byte (if ALEN 0), the first dummy byte (if alen = 0 and DUMLEN 0), or directly with transferring the data bytes (if ALEN = DUMLEN = 0 and DLEN 0). Limiting the external transfer to just the data phase - together with the keep_cs feature - allow to transfer any number of data bytes for a device command sent via EBU_SFCMD by keeping the device selected between accesses and chaining multiple indirect access commands each transferring up to 4 data bytes from/to register EBU_SFDATA. */
+#define SFCMD_SKIP_OPC 0x00001000
+/** Data Length
+    This field defines the number of data bytes to transfer in the data phase of the command. For a read command, the data bytes are stored in register EBU_SFDATA, for a write transfer they are taken from that register. As the data register can hold at most 4 bytes, DLEN is restricted to the range [0..4]. */
+#define SFCMD_DLEN_MASK 0x00000E00
+/** field offset */
+#define SFCMD_DLEN_OFFSET 9
+/** Direction
+    Defines the direction of the data transfer (if any) in the data phase of the transaction to/from the serial bus. */
+#define SFCMD_DIR 0x00000100
+/* dlen bytes of data are read from the Serial Flash during the data phase of the transaction and stored in register EBU_SFDATA.
+#define SFCMD_DIR_READ 0x00000000 */
+/** dlen bytes of data are read from register EBU_SFDATA and written to the Serial Flash during the data phase of the transactione */
+#define SFCMD_DIR_WRITE 0x00000100
+/** Command Opcode
+    A write access to this field starts an Indirect Access command in the EBU's Serial Flash controller. Two types of commands are supported (selected in EBU_SFCMD.cmdtype) and determine how the EBU interprets the opcode:- - For a ACCESS_CMD, a single transaction is executed to/from the Serial Flash device and the OPC is sent to the device in the command phase of the protocol. The number of address, dummy and data bytes to transfer with the command are given in fields ALEN, DUMLEN, and DLEN of register EBU_SFCMD, respectively. - For a SPECIAL_CMD, the EBU starts a complex operation that usually involves multiple transactions to/from the Serial Flash device. See Section 3.18.2.5 for an overview of the complex commands currently supported. */
+#define SFCMD_OPC_MASK 0x000000FF
+/** field offset */
+#define SFCMD_OPC_OFFSET 0
+
+/* Fields of "Serial Flash Address Register" */
+/** Address
+    Before writing to register EBU_SFCMD to start a command that requires the transfer of an address, the address to use must be stored in this register. If not disabled in EBU_SFCMD.dis_aai, ADDR is incremented automatically with each data byte transferred between the EBU and the Serial Flash for an indirect access. Note:Register EBU_SFADDR is only used for access in Indirect Access Mode and is ignored/remains unaltered for all accesses in Direct Access Mode. */
+#define SFADDR_ADDR_MASK 0xFFFFFFFF
+/** field offset */
+#define SFADDR_ADDR_OFFSET 0
+
+/* Fields of "Serial Flash Data Register" */
+/** Data Bytes
+    Before writing to register EBU_SFCMD to start a command that requires the transfer of data from the EBU to the Serial Flash device (write access), the data to send must be stored in this register. The data bytes have to be right-aligned in this register, that is, the last byte to send must be placed in bits DATA[7:0], the second-to-last byte in bits DATA[15:8], etc.. Similarly, for a read access with data being transferred from the Serial Flash to the EBU, this register collects the read data received from the device. The read data is right-aligned, that is, the last byte received gets placed in bits DATA[7:0], the second-to-last byte in bits DATA[15:8], etc... The number of data bytes to be transferred between EBU and the Serial Flash is defined in EBU_SFCMD.DLEN. Note:Register EBU_SFDATA is only used for accesses in Indirect Access Mode and is ignored/remains unaltered for all accesses in Direct Access Mode. */
+#define SFDATA_DATA_MASK 0xFFFFFFFF
+/** field offset */
+#define SFDATA_DATA_OFFSET 0
+
+/* Fields of "Serial Flash I/O Control Register" */
+/** Start of Write Delay
+    By default, the EBU starts driving to AD[3:0] two EBU clock cycles before asserting the CS for an external Serial Flash access. For write accesses, this delay can be increased via field SOWD. */
+#define SFIO_SOWD_MASK 0x0000F000
+/** field offset */
+#define SFIO_SOWD_OFFSET 12
+/** End of Write Delay
+    This field defines the time (in number of EBU clock cycles) for which the EBU keeps driving the External Bus AD[3:0] after deassertion of the device's CS. */
+#define SFIO_EOWD_MASK 0x00000F00
+/** field offset */
+#define SFIO_EOWD_OFFSET 8
+/** Data Output
+    The EBU always controls the AD[3:0] pins while a CS for a Serial Flash device is asserted. Field UNUSED_WD defines the values being driven to these pins while the Serial Flash controller is not writing data to or is reading data from the device via the respective line. See Section 3.18.6 for details. */
+#define SFIO_UNUSED_WD_MASK 0x0000000F
+/** field offset */
+#define SFIO_UNUSED_WD_OFFSET 0
+
+/*! @} */ /* EBU_REGISTER */
+
+#endif /* _ebu_reg_h */