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From cb3ef99c1553565e1dc0301ccd5c1c0fa2d15c15 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 31 Dec 2021 17:56:14 +0100
Subject: [PATCH] arm64: dts: ipq8074: add CPU clock
Now that CPU clock is exposed and can be controlled, add the necessary
properties to the CPU nodes.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
+#include <dt-bindings/clock/qcom,apss-ipq.h>
/ {
#address-cells = <2>;
@@ -38,6 +39,8 @@
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu";
};
CPU1: cpu@1 {
@@ -46,6 +49,8 @@
enable-method = "psci";
reg = <0x1>;
next-level-cache = <&L2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu";
};
CPU2: cpu@2 {
@@ -54,6 +59,8 @@
enable-method = "psci";
reg = <0x2>;
next-level-cache = <&L2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu";
};
CPU3: cpu@3 {
@@ -62,6 +69,8 @@
enable-method = "psci";
reg = <0x3>;
next-level-cache = <&L2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu";
};
L2_0: l2-cache {
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