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path: root/target/linux/ipq806x/patches/0180-ARM-dts-Add-ADM-DMA-nodes-and-SPI-linkage.patch
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From c78ae23b6c174c9f2e0973a247942b6b4adb7e82 Mon Sep 17 00:00:00 2001
From: Andy Gross <agross@codeaurora.org>
Date: Thu, 26 Jun 2014 13:02:59 -0500
Subject: [PATCH 180/182] ARM: dts: Add ADM DMA nodes and SPI linkage

This patch adds the ADM DMA controller DT nodes and also enables the use of dma
in SPI.

Signed-off-by: Andy Gross <agross@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq8064-ap148.dts |   11 +++++++++++
 arch/arm/boot/dts/qcom-ipq8064.dtsi      |    8 +++++---
 2 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
index 2b2d63c..c54a3ee 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -44,6 +44,10 @@
 					drive-strength = <10>;
 					bias-none;
 				};
+				cs {
+					pins = "gpio20";
+					drive-strength = <12>;
+				};
 			};
 			nand_pins: nand_pins {
 				mux {
@@ -100,12 +104,17 @@
 
 				cs-gpios = <&qcom_pinmux 20 0>;
 
+				dmas = <&adm_dma 6 9>,
+					<&adm_dma 5 10>;
+				dma-names = "rx", "tx";
+
 				flash: m25p80@0 {
 					compatible = "s25fl256s1";
 					#address-cells = <1>;
 					#size-cells = <1>;
 					spi-max-frequency = <50000000>;
 					reg = <0>;
+					m25p,fast-read;
 
 					partition@0 {
 						label = "rootfs";
@@ -140,8 +149,10 @@
 			ranges = <0x00000000 0 0x00000000 0x31f00000 0 0x00100000   /* configuration space */
 				  0x81000000 0 0	  0x31e00000 0 0x00100000   /* downstream I/O */
 				  0x82000000 0 0x00000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
+
 		};
 
+
 		sata-phy@1b400000 {
 			status = "ok";
 		};
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 97e4c3d..f74e923 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -421,19 +421,21 @@
 			compatible = "qcom,adm";
 			reg = <0x18300000 0x100000>;
 			interrupts = <0 170 0>;
+			#dma-cells = <2>;
 
 			clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
-			clock-names = "core_clk", "iface_clk";
+			clock-names = "core", "iface";
 
 			resets = <&gcc ADM0_RESET>,
 				<&gcc ADM0_PBUS_RESET>,
 				<&gcc ADM0_C0_RESET>,
 				<&gcc ADM0_C1_RESET>,
 				<&gcc ADM0_C2_RESET>;
-
-			reset-names = "adm", "pbus", "c0", "c1", "c2";
+			reset-names = "clk", "pbus", "c0", "c1", "c2";
+			qcom,ee = <0>;
 
 			status = "disabled";
+
 		};
 
 		nand@0x1ac00000 {
-- 
1.7.10.4