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From 1fb18acab2d71e7e4efd9c10492edb1baf84dcc0 Mon Sep 17 00:00:00 2001
From: Andy Gross <agross@codeaurora.org>
Date: Wed, 20 May 2015 15:41:07 +0530
Subject: [PATCH] ARM: DT: ipq8064: Add ADM device node
This patch adds support for the ADM DMA on the IPQ8064 SOC
Signed-off-by: Andy Gross <agross@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 4 ++++
arch/arm/boot/dts/qcom-ipq8064.dtsi | 21 +++++++++++++++++++++
2 files changed, 25 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -90,6 +90,10 @@
cs-gpios = <&qcom_pinmux 20 0>;
+ dmas = <&adm_dma 6>,
+ <&adm_dma 5>;
+ dma-names = "rx", "tx";
+
flash: m25p80@0 {
compatible = "s25fl256s1";
#address-cells = <1>;
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -657,5 +657,25 @@
};
};
+ adm_dma: dma@18300000 {
+ compatible = "qcom,adm";
+ reg = <0x18300000 0x100000>;
+ interrupts = <0 170 0>;
+ #dma-cells = <1>;
+
+ clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
+ clock-names = "core", "iface";
+
+ resets = <&gcc ADM0_RESET>,
+ <&gcc ADM0_PBUS_RESET>,
+ <&gcc ADM0_C0_RESET>,
+ <&gcc ADM0_C1_RESET>,
+ <&gcc ADM0_C2_RESET>;
+ reset-names = "clk", "pbus", "c0", "c1", "c2";
+ qcom,ee = <0>;
+
+ status = "disabled";
+ };
+
};
};
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