path: root/target/linux/coldfire/patches/004-m5445x_headers.patch

From fa0f89c9cf9ceecc3feac1d96914c8e91f98d90f Mon Sep 17 00:00:00 2001
From: Kurt Mahan <kmahan@freescale.com>
Date: Wed, 31 Oct 2007 16:43:01 -0600
Subject: [PATCH] Add MCF5445x Specific Header Files.

LTIBName: m5445x-headers
Signed-off-by: Kurt Mahan <kmahan@freescale.com>
---
 include/asm-m68k/mcf5445x_ccm.h    |  161 ++++
 include/asm-m68k/mcf5445x_dspi.h   |  402 ++++++++++
 include/asm-m68k/mcf5445x_dtim.h   |   87 +++
 include/asm-m68k/mcf5445x_edma.h   | 1458 ++++++++++++++++++++++++++++++++++++
 include/asm-m68k/mcf5445x_eport.h  |  117 +++
 include/asm-m68k/mcf5445x_fbcs.h   |  182 +++++
 include/asm-m68k/mcf5445x_gpio.h   | 1257 +++++++++++++++++++++++++++++++
 include/asm-m68k/mcf5445x_i2c.h    |   39 +
 include/asm-m68k/mcf5445x_intc.h   |  724 ++++++++++++++++++
 include/asm-m68k/mcf5445x_pci.h    |  238 ++++++
 include/asm-m68k/mcf5445x_pciarb.h |   40 +
 include/asm-m68k/mcf5445x_sdramc.h |  115 +++
 include/asm-m68k/mcf5445x_ssi.h    |  187 +++++
 include/asm-m68k/mcf5445x_usb.h    |   49 ++
 14 files changed, 5056 insertions(+), 0 deletions(-)
 create mode 100644 include/asm-m68k/mcf5445x_ccm.h
 create mode 100644 include/asm-m68k/mcf5445x_dspi.h
 create mode 100644 include/asm-m68k/mcf5445x_dtim.h
 create mode 100644 include/asm-m68k/mcf5445x_edma.h
 create mode 100644 include/asm-m68k/mcf5445x_eport.h
 create mode 100644 include/asm-m68k/mcf5445x_fbcs.h
 create mode 100644 include/asm-m68k/mcf5445x_gpio.h
 create mode 100644 include/asm-m68k/mcf5445x_i2c.h
 create mode 100644 include/asm-m68k/mcf5445x_intc.h
 create mode 100644 include/asm-m68k/mcf5445x_pci.h
 create mode 100644 include/asm-m68k/mcf5445x_pciarb.h
 create mode 100644 include/asm-m68k/mcf5445x_sdramc.h
 create mode 100644 include/asm-m68k/mcf5445x_ssi.h
 create mode 100644 include/asm-m68k/mcf5445x_usb.h

--- /dev/null
+++ b/include/asm-m68k/mcf5445x_ccm.h
@@ -0,0 +1,161 @@
+/*
+ * Matt Waddel Matt.Waddel@freescale.com
+ *
+ * Copyright Freescale Semiconductor, Inc. 2007
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MCF5445X_CCM_H__
+#define __MCF5445X_CCM_H__
+
+/*********************************************************************
+*
+* Chip Configuration Module (CCM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_CCM_CCR	MCF_REG16(0xFC0A0004)	/* Chip Configuration Register (Read-only) (256 or 360 TEPBGA) */
+#define MCF_CCM_RCON	MCF_REG16(0xFC0A0008)	/* Reset Configuration (Read-only) (256 or 360 TEPBGA) */
+#define MCF_CCM_CIR	MCF_REG16(0xFC0A000A)	/* Chip Identification Register (Read-only) */
+#define MCF_CCM_MISCCR	MCF_REG16(0xFC0A0010)	/* Miscellaneous Control Register */
+#define MCF_CCM_CDR	MCF_REG16(0xFC0A0012)	/* Clock Divider Register */
+#define MCF_CCM_UOCSR	MCF_REG16(0xFC0A0014)	/* USB On-the-Go Controller Status Register */
+#define MCF_CCM_SBFSR	MCF_REG16(0xFC0A0018)	/* Serial Boot Facility Status Register (Read Only) */
+#define MCF_CCM_SBFCR	MCF_REG16(0xFC0A0020)	/* Serial Boot Facility Control Register */
+
+/* Bit definitions and macros for CCR_360 */
+#define MCF_CCM_CCR_360_PLLMULT2(x)         (((x) & 0x0003))	/* 2-Bit PLL clock mode */
+#define MCF_CCM_CCR_360_PCISLEW             (0x0004)		/* PCI pad slew rate mode */
+#define MCF_CCM_CCR_360_PCIMODE             (0x0008)		/* PCI host/agent mode */
+#define MCF_CCM_CCR_360_PLLMODE             (0x0010)		/* PLL Mode */
+#define MCF_CCM_CCR_360_FBCONFIG(x)         (((x) & 0x0007) << 5)  /* Flexbus/PCI port size configuration */
+#define MCF_CCM_CCR_360_PLLMULT3(x)         (((x) & 0x0007))	/* 3-Bit PLL Clock Mode */
+#define MCF_CCM_CCR_360_OSCMODE             (0x0008)		/* Oscillator Clock Mode */
+#define MCF_CCM_CCR_360_FBCONFIG_MASK       (0x00E0)
+#define MCF_CCM_CCR_360_PLLMULT2_MASK       (0x0003)
+#define MCF_CCM_CCR_360_PLLMULT3_MASK       (0x0007)
+#define MCF_CCM_CCR_360_FBCONFIG_NM_NP_32   (0x0000)
+#define MCF_CCM_CCR_360_FBCONFIG_NM_NP_8    (0x0020)
+#define MCF_CCM_CCR_360_FBCONFIG_NM_NP_16   (0x0040)
+#define MCF_CCM_CCR_360_FBCONFIG_M_P_16     (0x0060)
+#define MCF_CCM_CCR_360_FBCONFIG_M_NP_32    (0x0080)
+#define MCF_CCM_CCR_360_FBCONFIG_M_NP_8     (0x00A0)
+#define MCF_CCM_CCR_360_FBCONFIG_M_NP_16    (0x00C0)
+#define MCF_CCM_CCR_360_FBCONFIG_M_P_8      (0x00E0)
+#define MCF_CCM_CCR_360_PLLMULT2_12X        (0x0000)
+#define MCF_CCM_CCR_360_PLLMULT2_6X         (0x0001)
+#define MCF_CCM_CCR_360_PLLMULT2_16X        (0x0002)
+#define MCF_CCM_CCR_360_PLLMULT2_8X         (0x0003)
+#define MCF_CCM_CCR_360_PLLMULT3_20X        (0x0000)
+#define MCF_CCM_CCR_360_PLLMULT3_10X        (0x0001)
+#define MCF_CCM_CCR_360_PLLMULT3_24X        (0x0002)
+#define MCF_CCM_CCR_360_PLLMULT3_18X        (0x0003)
+#define MCF_CCM_CCR_360_PLLMULT3_12X        (0x0004)
+#define MCF_CCM_CCR_360_PLLMULT3_6X         (0x0005)
+#define MCF_CCM_CCR_360_PLLMULT3_16X        (0x0006)
+#define MCF_CCM_CCR_360_PLLMULT3_8X         (0x0007)
+
+/* Bit definitions and macros for CCR_256 */
+#define MCF_CCM_CCR_256_PLLMULT3(x)         (((x) & 0x0007))  /* 3-Bit PLL clock mode */
+#define MCF_CCM_CCR_256_OSCMODE             (0x0008)	      /* Oscillator clock mode */
+#define MCF_CCM_CCR_256_PLLMODE             (0x0010)	      /* PLL Mode */
+#define MCF_CCM_CCR_256_FBCONFIG(x)         (((x) & 0x0007) << 5)  /* Flexbus/PCI port size configuration */
+#define MCF_CCM_CCR_256_FBCONFIG_MASK       (0x00E0)
+#define MCF_CCM_CCR_256_FBCONFIG_NM_32      (0x0000)
+#define MCF_CCM_CCR_256_FBCONFIG_NM_8       (0x0020)
+#define MCF_CCM_CCR_256_FBCONFIG_NM_16      (0x0040)
+#define MCF_CCM_CCR_256_FBCONFIG_M_32       (0x0080)
+#define MCF_CCM_CCR_256_FBCONFIG_M_8        (0x00A0)
+#define MCF_CCM_CCR_256_FBCONFIG_M_16       (0x00C0)
+#define MCF_CCM_CCR_256_PLLMULT3_MASK       (0x0007)
+#define MCF_CCM_CCR_256_PLLMULT3_20X        (0x0000)
+#define MCF_CCM_CCR_256_PLLMULT3_10X        (0x0001)
+#define MCF_CCM_CCR_256_PLLMULT3_24X        (0x0002)
+#define MCF_CCM_CCR_256_PLLMULT3_18X        (0x0003)
+#define MCF_CCM_CCR_256_PLLMULT3_12X        (0x0004)
+#define MCF_CCM_CCR_256_PLLMULT3_6X         (0x0005)
+#define MCF_CCM_CCR_256_PLLMULT3_16X        (0x0006)
+#define MCF_CCM_CCR_256_PLLMULT3_8X         (0x0007)
+
+/* Bit definitions and macros for RCON_360 */
+#define MCF_CCM_RCON_360_PLLMULT(x)     (((x)&0x0003))	/* PLL clock mode */
+#define MCF_CCM_RCON_360_PCISLEW        (0x0004)	/* PCI pad slew rate mode */
+#define MCF_CCM_RCON_360_PCIMODE        (0x0008)	/* PCI host/agent mode */
+#define MCF_CCM_RCON_360_PLLMODE        (0x0010)	/* PLL Mode */
+#define MCF_CCM_RCON_360_FBCONFIG(x)    (((x) & 0x0007) << 5)	/* Flexbus/PCI port size configuration */
+
+/* Bit definitions and macros for RCON_256 */
+#define MCF_CCM_RCON_256_PLLMULT(x)     (((x) & 0x0007)) /* PLL clock mode */
+#define MCF_CCM_RCON_256_OSCMODE        (0x0008)	/* Oscillator clock mode */
+#define MCF_CCM_RCON_256_PLLMODE        (0x0010)	/* PLL Mode */
+#define MCF_CCM_RCON_256_FBCONFIG(x)    (((x) & 0x0007) << 5)	/* Flexbus/PCI port size configuration */
+
+/* Bit definitions and macros for CIR */
+#define MCF_CCM_CIR_PRN(x)          (((x) & 0x003F))	/* Part revision number */
+#define MCF_CCM_CIR_PIN(x)          (((x) & 0x03FF) << 6)	/* Part identification number */
+#define MCF_CCM_CIR_PIN_MASK        (0xFFC0)
+#define MCF_CCM_CIR_PRN_MASK        (0x003F)
+#define MCF_CCM_CIR_PIN_MCF54450    (0x4F << 6)
+#define MCF_CCM_CIR_PIN_MCF54451    (0x4D << 6)
+#define MCF_CCM_CIR_PIN_MCF54452    (0x4B << 6)
+#define MCF_CCM_CIR_PIN_MCF54453    (0x49 << 6)
+#define MCF_CCM_CIR_PIN_MCF54454    (0x4A << 6)
+#define MCF_CCM_CIR_PIN_MCF54455    (0x48 << 6)
+
+/* Bit definitions and macros for MISCCR */
+#define MCF_CCM_MISCCR_USBSRC           (0x0001)	/* USB clock source */
+#define MCF_CCM_MISCCR_USBOC            (0x0002)	/* USB VBUS over-current sense polarity */
+#define MCF_CCM_MISCCR_USBPUE           (0x0004)	/* USB transceiver pull-up enable */
+#define MCF_CCM_MISCCR_SSISRC           (0x0010)	/* SSI clock source */
+#define MCF_CCM_MISCCR_TIMDMA           (0x0020)	/* Timer DMA mux selection */
+#define MCF_CCM_MISCCR_SSIPUS           (0x0040)	/* SSI RXD/TXD pull select */
+#define MCF_CCM_MISCCR_SSIPUE           (0x0080)	/* SSI RXD/TXD pull enable */
+#define MCF_CCM_MISCCR_BMT(x)           (((x) & 0x0007) << 8)	/* Bus monitor timing field */
+#define MCF_CCM_MISCCR_BME              (0x0800)	/* Bus monitor external enable bit */
+#define MCF_CCM_MISCCR_LIMP             (0x1000)	/* Limp mode enable */
+#define MCF_CCM_MISCCR_BMT_65536        (0)
+#define MCF_CCM_MISCCR_BMT_32768        (1)
+#define MCF_CCM_MISCCR_BMT_16384        (2)
+#define MCF_CCM_MISCCR_BMT_8192         (3)
+#define MCF_CCM_MISCCR_BMT_4096         (4)
+#define MCF_CCM_MISCCR_BMT_2048         (5)
+#define MCF_CCM_MISCCR_BMT_1024         (6)
+#define MCF_CCM_MISCCR_BMT_512          (7)
+#define MCF_CCM_MISCCR_SSIPUS_UP        (1)
+#define MCF_CCM_MISCCR_SSIPUS_DOWN      (0)
+#define MCF_CCM_MISCCR_TIMDMA_TIM       (1)
+#define MCF_CCM_MISCCR_TIMDMA_SSI       (0)
+#define MCF_CCM_MISCCR_SSISRC_CLKIN     (0)
+#define MCF_CCM_MISCCR_SSISRC_PLL       (1)
+#define MCF_CCM_MISCCR_USBOC_ACTHI      (0)
+#define MCF_CCM_MISCCR_USBOV_ACTLO      (1)
+#define MCF_CCM_MISCCR_USBSRC_CLKIN     (0)
+#define MCF_CCM_MISCCR_USBSRC_PLL       (1)
+
+/* Bit definitions and macros for CDR */
+#define MCF_CCM_CDR_SSIDIV(x)   (((x) & 0x00FF))	/* SSI oversampling clock divider */
+#define MCF_CCM_CDR_LPDIV(x)    (((x) & 0x000F) << 8)	/* Low power clock divider */
+
+/* Bit definitions and macros for UOCSR */
+#define MCF_CCM_UOCSR_XPDE          (0x0001)	/* On-chip transceiver pull-down enable */
+#define MCF_CCM_UOCSR_UOMIE         (0x0002)	/* USB OTG misc interrupt enable */
+#define MCF_CCM_UOCSR_WKUP          (0x0004)	/* USB OTG controller wake-up event */
+#define MCF_CCM_UOCSR_PWRFLT        (0x0008)	/* VBUS power fault */
+#define MCF_CCM_UOCSR_SEND          (0x0010)	/* Session end */
+#define MCF_CCM_UOCSR_VVLD          (0x0020)	/* VBUS valid indicator */
+#define MCF_CCM_UOCSR_BVLD          (0x0040)	/* B-peripheral valid indicator */
+#define MCF_CCM_UOCSR_AVLD          (0x0080)	/* A-peripheral valid indicator */
+#define MCF_CCM_UOCSR_DPPU          (0x0100)	/* D+ pull-up for FS enabled (read-only) */
+#define MCF_CCM_UOCSR_DCR_VBUS      (0x0200)	/* VBUS discharge resistor enabled (read-only) */
+#define MCF_CCM_UOCSR_CRG_VBUS      (0x0400)	/* VBUS charge resistor enabled (read-only) */
+#define MCF_CCM_UOCSR_DMPD          (0x1000)	/* D- 15Kohm pull-down (read-only) */
+#define MCF_CCM_UOCSR_DPPD          (0x2000)	/* D+ 15Kohm pull-down (read-only) */
+
+/********************************************************************/
+
+#endif /* __MCF5445X_CCM_H__ */
--- /dev/null
+++ b/include/asm-m68k/mcf5445x_dspi.h
@@ -0,0 +1,402 @@
+/*
+ * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
+ *
+ * Copyright Freescale Semiconductor, Inc. 2007
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MCF5445X_DSPI_H__
+#define __MCF5445X_DSPI_H__
+
+/*********************************************************************
+*
+* DMA Serial Peripheral Interface (DSPI)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_DSPI_DMCR           MCF_REG32(0xFC05C000)   /* DSPI Module Configuration Register */
+#define MCF_DSPI_DTCR           MCF_REG32(0xFC05C008)   /* DSPI Transfer Count Register */
+#define MCF_DSPI_DCTAR0         MCF_REG32(0xFC05C00C)   /* DSPI Clock and Transfer Attributes Register */
+#define MCF_DSPI_DCTAR1         MCF_REG32(0xFC05C010)   /* DSPI Clock and Transfer Attributes Register */
+#define MCF_DSPI_DCTAR2         MCF_REG32(0xFC05C014)   /* DSPI Clock and Transfer Attributes Register */
+#define MCF_DSPI_DCTAR3         MCF_REG32(0xFC05C018)   /* DSPI Clock and Transfer Attributes Register */
+#define MCF_DSPI_DCTAR4         MCF_REG32(0xFC05C01C)   /* DSPI Clock and Transfer Attributes Register */
+#define MCF_DSPI_DCTAR5         MCF_REG32(0xFC05C020)   /* DSPI Clock and Transfer Attributes Register */
+#define MCF_DSPI_DCTAR6         MCF_REG32(0xFC05C024)   /* DSPI Clock and Transfer Attributes Register */
+#define MCF_DSPI_DCTAR7         MCF_REG32(0xFC05C028)   /* DSPI Clock and Transfer Attributes Register */
+#define MCF_DSPI_DSR            MCF_REG32(0xFC05C02C)   /* DSPI Status Register */
+#define MCF_DSPI_DRSER          MCF_REG32(0xFC05C030)   /* DSPI DMA/Interrupt Request Select and Enable Register */
+#define MCF_DSPI_DTFR           MCF_REG32(0xFC05C034)   /* DSPI Transmit FIFO Register */
+#define MCF_DSPI_DRFR           MCF_REG32(0xFC05C038)   /* DSPI Receive FIFO Register */
+#define MCF_DSPI_DTFDR0         MCF_REG32(0xFC05C03C)   /* DSPI Transmit FIFO Debugging Registers */
+#define MCF_DSPI_DTFDR1         MCF_REG32(0xFC05C040)   /* DSPI Transmit FIFO Debugging Registers */
+#define MCF_DSPI_DTFDR2         MCF_REG32(0xFC05C044)   /* DSPI Transmit FIFO Debugging Registers */
+#define MCF_DSPI_DTFDR3         MCF_REG32(0xFC05C048)   /* DSPI Transmit FIFO Debugging Registers */
+#define MCF_DSPI_DRFDR0         MCF_REG32(0xFC05C07C)   /* DSPI Receive FIFO Debugging Registers */
+#define MCF_DSPI_DRFDR1         MCF_REG32(0xFC05C080)   /* DSPI Receive FIFO Debugging Registers */
+#define MCF_DSPI_DRFDR2         MCF_REG32(0xFC05C084)   /* DSPI Receive FIFO Debugging Registers */
+#define MCF_DSPI_DRFDR3         MCF_REG32(0xFC05C088)   /* DSPI Receive FIFO Debugging Registers */
+
+/* Parameterized register read/write macros for multiple registers */
+#define MCF_DSPI_DCTAR(x)       MCF_REG32(0xFC05C00C+((x)*0x004))	/* DSPI Clock and Transfer Attributes Register */
+#define MCF_DSPI_DTFDR(x)       MCF_REG32(0xFC05C03C+((x)*0x004))	/* DSPI Transmit FIFO Debugging Registers */
+#define MCF_DSPI_DRFDR(x)       MCF_REG32(0xFC05C07C+((x)*0x004))	/* DSPI Receive FIFO Debugging Registers */
+
+/* Bit definitions and macros for DMCR */
+#define MCF_DSPI_DMCR_HALT          (0x00000001)            /* Halt -- stops and starts DSPI transfers */
+#define MCF_DSPI_DMCR_SMPLPT(x)     (((x)&0x00000003)<<8)   /* Sample point selection */
+#define MCF_DSPI_DMCR_CLRRXF        (0x00000400)            /* Clear receive FIFO */
+#define MCF_DSPI_DMCR_CLRTXF        (0x00000800)            /* Clear transmit FIFO */
+#define MCF_DSPI_DMCR_DISRXF        (0x00001000)            /* Disable receive FIFO */
+#define MCF_DSPI_DMCR_DISTXF        (0x00002000)            /* Disable transmit FIFO */
+#define MCF_DSPI_DMCR_MDIS          (0x00004000)            /* Module Disable */
+#define MCF_DSPI_DMCR_PCSIS0        (0x00010000)            /* Peripheral chip-select 0 inactive state */
+#define MCF_DSPI_DMCR_PCSIS1        (0x00020000)            /* Peripheral chip-select 1 inactive state */
+#define MCF_DSPI_DMCR_PCSIS2        (0x00040000)            /* Peripheral chip-select 2 inactive state */
+#define MCF_DSPI_DMCR_PCSIS3        (0x00080000)            /* Peripheral chip-select 3 inactive state */
+#define MCF_DSPI_DMCR_PCSIS4        (0x00100000)            /* Peripheral chip-select 4 inactive state */
+#define MCF_DSPI_DMCR_PCSIS5        (0x00200000)            /* Peripheral chip-select 5 inactive state */
+#define MCF_DSPI_DMCR_PCSIS6        (0x00400000)            /* Peripheral chip-select 6 inactive state */
+#define MCF_DSPI_DMCR_PCSIS7        (0x00800000)            /* Peripheral chip-select 7 inactive state */
+#define MCF_DSPI_DMCR_ROOE          (0x01000000)            /* Receive FIFO overflow overwrite enable */
+#define MCF_DSPI_DMCR_PCSSE         (0x02000000)            /* Peripheral chip select strobe enable */
+#define MCF_DSPI_DMCR_MTFE          (0x04000000)            /* Modified timing format enable */
+#define MCF_DSPI_DMCR_FRZ           (0x08000000)            /* Freeze */
+#define MCF_DSPI_DMCR_DCONF(x)      (((x)&0x00000003)<<28)  /* DSPI configuration */
+#define MCF_DSPI_DMCR_CONT_SCKE     (0x40000000)            /* Continuous SCK enable */
+#define MCF_DSPI_DMCR_MSTR          (0x80000000)            /* Master/Slave mode select */
+#define MCF_DSPI_DMCR_DCONF_SPI     (0x00000000)
+#define MCF_DSPI_DMCR_PCSIS7_LOW    (0x00000000)
+#define MCF_DSPI_DMCR_PCSIS7_HIGH   (0x00800000)
+#define MCF_DSPI_DMCR_PCSIS6_LOW    (0x00000000)
+#define MCF_DSPI_DMCR_PCSIS6_HIGH   (0x00400000)
+#define MCF_DSPI_DMCR_PCSIS5_LOW    (0x00000000)
+#define MCF_DSPI_DMCR_PCSIS5_HIGH   (0x00200000)
+#define MCF_DSPI_DMCR_PCSIS4_LOW    (0x00000000)
+#define MCF_DSPI_DMCR_PCSIS4_HIGH   (0x00100000)
+#define MCF_DSPI_DMCR_PCSIS3_LOW    (0x00000000)
+#define MCF_DSPI_DMCR_PCSIS3_HIGH   (0x00080000)
+#define MCF_DSPI_DMCR_PCSIS2_LOW    (0x00000000)
+#define MCF_DSPI_DMCR_PCSIS2_HIGH   (0x00040000)
+#define MCF_DSPI_DMCR_PCSIS1_LOW    (0x00000000)
+#define MCF_DSPI_DMCR_PCSIS1_HIGH   (0x00020000)
+#define MCF_DSPI_DMCR_PCSIS0_LOW    (0x00000000)
+#define MCF_DSPI_DMCR_PCSIS0_HIGH   (0x00010000)
+
+/* Bit definitions and macros for DTCR */
+#define MCF_DSPI_DTCR_SPI_TCNT(x)   (((x)&0x0000FFFF)<<16)  /* SPI transfer count */
+
+/* Bit definitions and macros for DCTAR group */
+#define MCF_DSPI_DCTAR_BR(x)                (((x)&0x0000000F))      /* Baud rate scaler */
+#define MCF_DSPI_DCTAR_DT(x)                (((x)&0x0000000F)<<4)   /* Delay after transfer scaler */
+#define MCF_DSPI_DCTAR_ASC(x)               (((x)&0x0000000F)<<8)   /* After SCK delay scaler */
+#define MCF_DSPI_DCTAR_CSSCK(x)             (((x)&0x0000000F)<<12)  /* PCS to SCK delay scaler */
+#define MCF_DSPI_DCTAR_PBR(x)               (((x)&0x00000003)<<16)  /* Baud rate prescaler */
+#define MCF_DSPI_DCTAR_PDT(x)               (((x)&0x00000003)<<18)  /* Delay after transfer prescaler */
+#define MCF_DSPI_DCTAR_PASC(x)              (((x)&0x00000003)<<20)  /* After SCK delay prescaler */
+#define MCF_DSPI_DCTAR_PCSSCK(x)            (((x)&0x00000003)<<22)  /* PCS to SCK delay prescaler */
+#define MCF_DSPI_DCTAR_LSBFE                (0x01000000)            /* LSB first enable */
+#define MCF_DSPI_DCTAR_CPHA                 (0x02000000)            /* Clock phase */
+#define MCF_DSPI_DCTAR_CPOL                 (0x04000000)            /* Clock polarity */
+#define MCF_DSPI_DCTAR_FMSZ(x)              (((x)&0x0000000F)<<27)  /* Frame size */
+#define MCF_DSPI_DCTAR_DBR                  (0x80000000)            /* Double baud rate */
+#define MCF_DSPI_DCTAR_CPOL_LOW             (0x00000000)
+#define MCF_DSPI_DCTAR_CPOL_HIGH            (0x04000000)
+#define MCF_DSPI_DCTAR_CPHA_LATCH_RISING    (0x00000000)
+#define MCF_DSPI_DCTAR_CPHA_LATCH_FALLING   (0x02000000)
+#define MCF_DSPI_DCTAR_PCSSCK_1CLK          (0x00000000)
+#define MCF_DSPI_DCTAR_PCSSCK_3CLK          (0x00400000)
+#define MCF_DSPI_DCTAR_PCSSCK_5CLK          (0x00800000)
+#define MCF_DSPI_DCTAR_PCSSCK_7CLK          (0x00C00000)
+#define MCF_DSPI_DCTAR_PASC_1CLK            (0x00000000)
+#define MCF_DSPI_DCTAR_PASC_3CLK            (0x00100000)
+#define MCF_DSPI_DCTAR_PASC_5CLK            (0x00200000)
+#define MCF_DSPI_DCTAR_PASC_7CLK            (0x00300000)
+#define MCF_DSPI_DCTAR_PDT_1CLK             (0x00000000)
+#define MCF_DSPI_DCTAR_PDT_3CLK             (0x00040000)
+#define MCF_DSPI_DCTAR_PDT_5CLK             (0x00080000)
+#define MCF_DSPI_DCTAR_PDT_7CLK             (0x000C0000)
+#define MCF_DSPI_DCTAR_PBR_2CLK             (0x00000000)
+#define MCF_DSPI_DCTAR_PBR_3CLK             (0x00010000)
+#define MCF_DSPI_DCTAR_PBR_5CLK             (0x00020000)
+#define MCF_DSPI_DCTAR_PBR_7CLK             (0x00030000)
+
+/* Bit definitions and macros for DCTAR0 */
+#define MCF_DSPI_DCTAR0_BR(x)                   (((x)&0x0000000F))      /* Baud rate scaler */
+#define MCF_DSPI_DCTAR0_DT(x)                   (((x)&0x0000000F)<<4)   /* Delay after transfer scaler */
+#define MCF_DSPI_DCTAR0_ASC(x)                  (((x)&0x0000000F)<<8)   /* After SCK delay scaler */
+#define MCF_DSPI_DCTAR0_CSSCK(x)                (((x)&0x0000000F)<<12)  /* PCS to SCK delay scaler */
+#define MCF_DSPI_DCTAR0_PBR(x)                  (((x)&0x00000003)<<16)  /* Baud rate prescaler */
+#define MCF_DSPI_DCTAR0_PDT(x)                  (((x)&0x00000003)<<18)  /* Delay after transfer prescaler */
+#define MCF_DSPI_DCTAR0_PASC(x)                 (((x)&0x00000003)<<20)  /* After SCK delay prescaler */
+#define MCF_DSPI_DCTAR0_PCSSCK(x)               (((x)&0x00000003)<<22)  /* PCS to SCK delay prescaler */
+#define MCF_DSPI_DCTAR0_LSBFE                   (0x01000000)            /* LSB first enable */
+#define MCF_DSPI_DCTAR0_CPHA                    (0x02000000)            /* Clock phase */
+#define MCF_DSPI_DCTAR0_CPOL                    (0x04000000)            /* Clock polarity */
+#define MCF_DSPI_DCTAR0_FMSZ(x)                 (((x)&0x0000000F)<<27)  /* Frame size */
+#define MCF_DSPI_DCTAR0_DBR                     (0x80000000)            /* Double baud rate */
+#define MCF_DSPI_DCTAR0_CPOL_LOW                (0x00000000)
+#define MCF_DSPI_DCTAR0_CPOL_HIGH               (0x04000000)
+#define MCF_DSPI_DCTAR0_CPHA_LATCH_RISING       (0x00000000)
+#define MCF_DSPI_DCTAR0_CPHA_LATCH_FALLING      (0x02000000)
+#define MCF_DSPI_DCTAR0_PCSSCK_1CLK             (0x00000000)
+#define MCF_DSPI_DCTAR0_PCSSCK_3CLK             (0x00400000)
+#define MCF_DSPI_DCTAR0_PCSSCK_5CLK             (0x00800000)
+#define MCF_DSPI_DCTAR0_PCSSCK_7CLK             (0x00C00000)
+#define MCF_DSPI_DCTAR0_PASC_1CLK               (0x00000000)
+#define MCF_DSPI_DCTAR0_PASC_3CLK               (0x00100000)
+#define MCF_DSPI_DCTAR0_PASC_5CLK               (0x00200000)
+#define MCF_DSPI_DCTAR0_PASC_7CLK               (0x00300000)
+#define MCF_DSPI_DCTAR0_PDT_1CLK                (0x00000000)
+#define MCF_DSPI_DCTAR0_PDT_3CLK                (0x00040000)
+#define MCF_DSPI_DCTAR0_PDT_5CLK                (0x00080000)
+#define MCF_DSPI_DCTAR0_PDT_7CLK                (0x000C0000)
+#define MCF_DSPI_DCTAR0_PBR_2CLK                (0x00000000)
+#define MCF_DSPI_DCTAR0_PBR_3CLK                (0x00010000)
+#define MCF_DSPI_DCTAR0_PBR_5CLK                (0x00020000)
+#define MCF_DSPI_DCTAR0_PBR_7CLK                (0x00030000)
+
+/* Bit definitions and macros for DCTAR1 */
+#define MCF_DSPI_DCTAR1_BR(x)       (((x)&0x0000000F))      /* Baud rate scaler */
+#define MCF_DSPI_DCTAR1_DT(x)       (((x)&0x0000000F)<<4)   /* Delay after transfer scaler */
+#define MCF_DSPI_DCTAR1_ASC(x)      (((x)&0x0000000F)<<8)   /* After SCK delay scaler */
+#define MCF_DSPI_DCTAR1_CSSCK(x)    (((x)&0x0000000F)<<12)  /* PCS to SCK delay scaler */
+#define MCF_DSPI_DCTAR1_PBR(x)      (((x)&0x00000003)<<16)  /* Baud rate prescaler */
+#define MCF_DSPI_DCTAR1_PDT(x)      (((x)&0x00000003)<<18)  /* Delay after transfer prescaler */
+#define MCF_DSPI_DCTAR1_PASC(x)     (((x)&0x00000003)<<20)  /* After SCK delay prescaler */
+#define MCF_DSPI_DCTAR1_PCSSCK(x)   (((x)&0x00000003)<<22)  /* PCS to SCK delay prescaler */
+#define MCF_DSPI_DCTAR1_LSBFE       (0x01000000)            /* LSB first enable */
+#define MCF_DSPI_DCTAR1_CPHA        (0x02000000)            /* Clock phase */
+#define MCF_DSPI_DCTAR1_CPOL        (0x04000000)            /* Clock polarity */
+#define MCF_DSPI_DCTAR1_FMSZ(x)     (((x)&0x0000000F)<<27)  /* Frame size */
+#define MCF_DSPI_DCTAR1_DBR         (0x80000000)            /* Double baud rate */
+
+/* Bit definitions and macros for DCTAR2 */
+#define MCF_DSPI_DCTAR2_BR(x)       (((x)&0x0000000F))      /* Baud rate scaler */
+#define MCF_DSPI_DCTAR2_DT(x)       (((x)&0x0000000F)<<4)   /* Delay after transfer scaler */
+#define MCF_DSPI_DCTAR2_ASC(x)      (((x)&0x0000000F)<<8)   /* After SCK delay scaler */
+#define MCF_DSPI_DCTAR2_CSSCK(x)    (((x)&0x0000000F)<<12)  /* PCS to SCK delay scaler */
+#define MCF_DSPI_DCTAR2_PBR(x)      (((x)&0x00000003)<<16)  /* Baud rate prescaler */
+#define MCF_DSPI_DCTAR2_PDT(x)      (((x)&0x00000003)<<18)  /* Delay after transfer prescaler */
+#define MCF_DSPI_DCTAR2_PASC(x)     (((x)&0x00000003)<<20)  /* After SCK delay prescaler */
+#define MCF_DSPI_DCTAR2_PCSSCK(x)   (((x)&0x00000003)<<22)  /* PCS to SCK delay prescaler */
+#define MCF_DSPI_DCTAR2_LSBFE       (0x01000000)            /* LSB first enable */
+#define MCF_DSPI_DCTAR2_CPHA        (0x02000000)            /* Clock phase */
+#define MCF_DSPI_DCTAR2_CPOL        (0x04000000)            /* Clock polarity */
+#define MCF_DSPI_DCTAR2_FMSZ(x)     (((x)&0x0000000F)<<27)  /* Frame size */
+#define MCF_DSPI_DCTAR2_DBR         (0x80000000)            /* Double baud rate */
+
+/* Bit definitions and macros for DCTAR3 */
+#define MCF_DSPI_DCTAR3_BR(x)       (((x)&0x0000000F))      /* Baud rate scaler */
+#define MCF_DSPI_DCTAR3_DT(x)       (((x)&0x0000000F)<<4)   /* Delay after transfer scaler */
+#define MCF_DSPI_DCTAR3_ASC(x)      (((x)&0x0000000F)<<8)   /* After SCK delay scaler */
+#define MCF_DSPI_DCTAR3_CSSCK(x)    (((x)&0x0000000F)<<12)  /* PCS to SCK delay scaler */
+#define MCF_DSPI_DCTAR3_PBR(x)      (((x)&0x00000003)<<16)  /* Baud rate prescaler */
+#define MCF_DSPI_DCTAR3_PDT(x)      (((x)&0x00000003)<<18)  /* Delay after transfer prescaler */
+#define MCF_DSPI_DCTAR3_PASC(x)     (((x)&0x00000003)<<20)  /* After SCK delay prescaler */
+#define MCF_DSPI_DCTAR3_PCSSCK(x)   (((x)&0x00000003)<<22)  /* PCS to SCK delay prescaler */
+#define MCF_DSPI_DCTAR3_LSBFE       (0x01000000)            /* LSB first enable */
+#define MCF_DSPI_DCTAR3_CPHA        (0x02000000)            /* Clock phase */
+#define MCF_DSPI_DCTAR3_CPOL        (0x04000000)            /* Clock polarity */
+#define MCF_DSPI_DCTAR3_FMSZ(x)     (((x)&0x0000000F)<<27)  /* Frame size */
+#define MCF_DSPI_DCTAR3_DBR         (0x80000000)            /* Double baud rate */
+
+/* Bit definitions and macros for DCTAR4 */
+#define MCF_DSPI_DCTAR4_BR(x)       (((x)&0x0000000F))      /* Baud rate scaler */
+#define MCF_DSPI_DCTAR4_DT(x)       (((x)&0x0000000F)<<4)   /* Delay after transfer scaler */
+#define MCF_DSPI_DCTAR4_ASC(x)      (((x)&0x0000000F)<<8)   /* After SCK delay scaler */
+#define MCF_DSPI_DCTAR4_CSSCK(x)    (((x)&0x0000000F)<<12)  /* PCS to SCK delay scaler */
+#define MCF_DSPI_DCTAR4_PBR(x)      (((x)&0x00000003)<<16)  /* Baud rate prescaler */
+#define MCF_DSPI_DCTAR4_PDT(x)      (((x)&0x00000003)<<18)  /* Delay after transfer prescaler */
+#define MCF_DSPI_DCTAR4_PASC(x)     (((x)&0x00000003)<<20)  /* After SCK delay prescaler */
+#define MCF_DSPI_DCTAR4_PCSSCK(x)   (((x)&0x00000003)<<22)  /* PCS to SCK delay prescaler */
+#define MCF_DSPI_DCTAR4_LSBFE       (0x01000000)            /* LSB first enable */
+#define MCF_DSPI_DCTAR4_CPHA        (0x02000000)            /* Clock phase */
+#define MCF_DSPI_DCTAR4_CPOL        (0x04000000)            /* Clock polarity */
+#define MCF_DSPI_DCTAR4_FMSZ(x)     (((x)&0x0000000F)<<27)  /* Frame size */
+#define MCF_DSPI_DCTAR4_DBR         (0x80000000)            /* Double baud rate */
+
+/* Bit definitions and macros for DCTAR5 */
+#define MCF_DSPI_DCTAR5_BR(x)       (((x)&0x0000000F))      /* Baud rate scaler */
+#define MCF_DSPI_DCTAR5_DT(x)       (((x)&0x0000000F)<<4)   /* Delay after transfer scaler */
+#define MCF_DSPI_DCTAR5_ASC(x)      (((x)&0x0000000F)<<8)   /* After SCK delay scaler */
+#define MCF_DSPI_DCTAR5_CSSCK(x)    (((x)&0x0000000F)<<12)  /* PCS to SCK delay scaler */
+#define MCF_DSPI_DCTAR5_PBR(x)      (((x)&0x00000003)<<16)  /* Baud rate prescaler */
+#define MCF_DSPI_DCTAR5_PDT(x)      (((x)&0x00000003)<<18)  /* Delay after transfer prescaler */
+#define MCF_DSPI_DCTAR5_PASC(x)     (((x)&0x00000003)<<20)  /* After SCK delay prescaler */
+#define MCF_DSPI_DCTAR5_PCSSCK(x)   (((x)&0x00000003)<<22)  /* PCS to SCK delay prescaler */
+#define MCF_DSPI_DCTAR5_LSBFE       (0x01000000)            /* LSB first enable */
+#define MCF_DSPI_DCTAR5_CPHA        (0x02000000)            /* Clock phase */
+#define MCF_DSPI_DCTAR5_CPOL        (0x04000000)            /* Clock polarity */
+#define MCF_DSPI_DCTAR5_FMSZ(x)     (((x)&0x0000000F)<<27)  /* Frame size */
+#define MCF_DSPI_DCTAR5_DBR         (0x80000000)            /* Double baud rate */
+
+/* Bit definitions and macros for DCTAR6 */
+#define MCF_DSPI_DCTAR6_BR(x)       (((x)&0x0000000F))      /* Baud rate scaler */
+#define MCF_DSPI_DCTAR6_DT(x)       (((x)&0x0000000F)<<4)   /* Delay after transfer scaler */
+#define MCF_DSPI_DCTAR6_ASC(x)      (((x)&0x0000000F)<<8)   /* After SCK delay scaler */
+#define MCF_DSPI_DCTAR6_CSSCK(x)    (((x)&0x0000000F)<<12)  /* PCS to SCK delay scaler */
+#define MCF_DSPI_DCTAR6_PBR(x)      (((x)&0x00000003)<<16)  /* Baud rate prescaler */
+#define MCF_DSPI_DCTAR6_PDT(x)      (((x)&0x00000003)<<18)  /* Delay after transfer prescaler */
+#define MCF_DSPI_DCTAR6_PASC(x)     (((x)&0x00000003)<<20)  /* After SCK delay prescaler */
+#define MCF_DSPI_DCTAR6_PCSSCK(x)   (((x)&0x00000003)<<22)  /* PCS to SCK delay prescaler */
+#define MCF_DSPI_DCTAR6_LSBFE       (0x01000000)            /* LSB first enable */
+#define MCF_DSPI_DCTAR6_CPHA        (0x02000000)            /* Clock phase */
+#define MCF_DSPI_DCTAR6_CPOL        (0x04000000)            /* Clock polarity */
+#define MCF_DSPI_DCTAR6_FMSZ(x)     (((x)&0x0000000F)<<27)  /* Frame size */
+#define MCF_DSPI_DCTAR6_DBR         (0x80000000)            /* Double baud rate */
+
+/* Bit definitions and macros for DCTAR7 */
+#define MCF_DSPI_DCTAR7_BR(x)       (((x)&0x0000000F))      /* Baud rate scaler */
+#define MCF_DSPI_DCTAR7_DT(x)       (((x)&0x0000000F)<<4)   /* Delay after transfer scaler */
+#define MCF_DSPI_DCTAR7_ASC(x)      (((x)&0x0000000F)<<8)   /* After SCK delay scaler */
+#define MCF_DSPI_DCTAR7_CSSCK(x)    (((x)&0x0000000F)<<12)  /* PCS to SCK delay scaler */
+#define MCF_DSPI_DCTAR7_PBR(x)      (((x)&0x00000003)<<16)  /* Baud rate prescaler */
+#define MCF_DSPI_DCTAR7_PDT(x)      (((x)&0x00000003)<<18)  /* Delay after transfer prescaler */
+#define MCF_DSPI_DCTAR7_PASC(x)     (((x)&0x00000003)<<20)  /* After SCK delay prescaler */
+#define MCF_DSPI_DCTAR7_PCSSCK(x)   (((x)&0x00000003)<<22)  /* PCS to SCK delay prescaler */
+#define MCF_DSPI_DCTAR7_LSBFE       (0x01000000)            /* LSB first enable */
+#define MCF_DSPI_DCTAR7_CPHA        (0x02000000)            /* Clock phase */
+#define MCF_DSPI_DCTAR7_CPOL        (0x04000000)            /* Clock polarity */
+#define MCF_DSPI_DCTAR7_FMSZ(x)     (((x)&0x0000000F)<<27)  /* Frame size */
+#define MCF_DSPI_DCTAR7_DBR         (0x80000000)            /* Double baud rate */
+
+/* Bit definitions and macros for DSR */
+#define MCF_DSPI_DSR_RXPTR(x)   (((x)&0x0000000F))      /* Receive next pointer */
+#define MCF_DSPI_DSR_RXCTR(x)   (((x)&0x0000000F)<<4)   /* Receive FIFO counter */
+#define MCF_DSPI_DSR_TXPTR(x)   (((x)&0x0000000F)<<8)   /* Transmit next pointer */
+#define MCF_DSPI_DSR_TXCTR(x)   (((x)&0x0000000F)<<12)  /* Transmit FIFO counter */
+#define MCF_DSPI_DSR_RFDF       (0x00020000)            /* Receive FIFO drain flag */
+#define MCF_DSPI_DSR_RFOF       (0x00080000)            /* Receive FIFO overflow flag */
+#define MCF_DSPI_DSR_TFFF       (0x02000000)            /* Transmit FIFO fill flag */
+#define MCF_DSPI_DSR_TFUF       (0x08000000)            /* Transmit FIFO underflow flag */
+#define MCF_DSPI_DSR_EOQF       (0x10000000)            /* End of queue flag */
+#define MCF_DSPI_DSR_TXRXS      (0x40000000)            /* Tx and Rx status (enabled | disabled) */
+#define MCF_DSPI_DSR_TCF        (0x80000000)            /* Transfer complete flag */
+
+/* Bit definitions and macros for DRSER */
+#define MCF_DSPI_DRSER_RFDFS    (0x00010000)    /* Receive FIFO drain DMA or interrupt select */
+#define MCF_DSPI_DRSER_RFDFE    (0x00020000)    /* Receive FIFO drain request enable */
+#define MCF_DSPI_DRSER_RFOFE    (0x00080000)    /* Receive FIFO overflow request enable */
+#define MCF_DSPI_DRSER_TFFFS    (0x01000000)    /* Transmit FIFO fill DMA or interrupt select */
+#define MCF_DSPI_DRSER_TFFFE    (0x02000000)    /* Transmit FIFO fill request enable */
+#define MCF_DSPI_DRSER_TFUFE    (0x08000000)    /* Transmit FIFO underflow request enable */
+#define MCF_DSPI_DRSER_EOQFE    (0x10000000)    /* DSPI finished request enable */
+#define MCF_DSPI_DRSER_TCFE     (0x80000000)    /* Transmission complete request enable */
+
+/* Bit definitions and macros for DTFR */
+#define MCF_DSPI_DTFR_TXDATA(x)     (((x)&0x0000FFFF))      /* Transmit data */
+#define MCF_DSPI_DTFR_PCS0          (0x00010000)            /* Peripheral chip select 0 */
+#define MCF_DSPI_DTFR_PCS1          (0x00020000)            /* Peripheral chip select 1 */
+#define MCF_DSPI_DTFR_PCS2          (0x00040000)            /* Peripheral chip select 2 */
+#define MCF_DSPI_DTFR_PCS3          (0x00080000)            /* Peripheral chip select 3 */
+#define MCF_DSPI_DTFR_PCS4          (0x00100000)            /* Peripheral chip select 4 */
+#define MCF_DSPI_DTFR_PCS5          (0x00200000)            /* Peripheral chip select 5 */
+#define MCF_DSPI_DTFR_PCS6          (0x00400000)            /* Peripheral chip select 6 */
+#define MCF_DSPI_DTFR_PCS7          (0x00800000)            /* Peripheral chip select 7 */
+#define MCF_DSPI_DTFR_CTCNT         (0x04000000)            /* Clear SPI transfer counter */
+#define MCF_DSPI_DTFR_EOQ           (0x08000000)            /* End of queue */
+#define MCF_DSPI_DTFR_CTAS(x)       (((x)&0x00000007)<<28)  /* Clock and transfer attributes select */
+#define MCF_DSPI_DTFR_CONT          (0x80000000)            /* Continuous peripheral chip-select enable */
+
+/* Bit definitions and macros for DRFR */
+#define MCF_DSPI_DRFR_RXDATA(x)     (((x)&0x0000FFFF))  /* Receive data */
+
+/* Bit definitions and macros for DTFDR group */
+#define MCF_DSPI_DTFDR_TXDATA(x)    (((x)&0x0000FFFF))      /* Transmit data */
+#define MCF_DSPI_DTFDR_PCS0         (0x00010000)            /* Peripheral chip select 0 */
+#define MCF_DSPI_DTFDR_PCS1         (0x00020000)            /* Peripheral chip select 1 */
+#define MCF_DSPI_DTFDR_PCS2         (0x00040000)            /* Peripheral chip select 2 */
+#define MCF_DSPI_DTFDR_PCS3         (0x00080000)            /* Peripheral chip select 3 */
+#define MCF_DSPI_DTFDR_PCS4         (0x00100000)            /* Peripheral chip select 4 */
+#define MCF_DSPI_DTFDR_PCS5         (0x00200000)            /* Peripheral chip select 5 */
+#define MCF_DSPI_DTFDR_PCS6         (0x00400000)            /* Peripheral chip select 6 */
+#define MCF_DSPI_DTFDR_PCS7         (0x00800000)            /* Peripheral chip select 7 */
+#define MCF_DSPI_DTFDR_CTCNT        (0x04000000)            /* Clear SPI transfer counter */
+#define MCF_DSPI_DTFDR_EOQ          (0x08000000)            /* End of queue */
+#define MCF_DSPI_DTFDR_CTAS(x)      (((x)&0x00000007)<<28)  /* Clock and transfer attributes select */
+#define MCF_DSPI_DTFDR_CONT         (0x80000000)            /* Continuous peripheral chip-select enable */
+
+/* Bit definitions and macros for DTFDR0 */
+#define MCF_DSPI_DTFDR0_TXDATA(x)   (((x)&0x0000FFFF))      /* Transmit data */
+#define MCF_DSPI_DTFDR0_PCS0        (0x00010000)            /* Peripheral chip select 0 */
+#define MCF_DSPI_DTFDR0_PCS1        (0x00020000)            /* Peripheral chip select 1 */
+#define MCF_DSPI_DTFDR0_PCS2        (0x00040000)            /* Peripheral chip select 2 */
+#define MCF_DSPI_DTFDR0_PCS3        (0x00080000)            /* Peripheral chip select 3 */
+#define MCF_DSPI_DTFDR0_PCS4        (0x00100000)            /* Peripheral chip select 4 */
+#define MCF_DSPI_DTFDR0_PCS5        (0x00200000)            /* Peripheral chip select 5 */
+#define MCF_DSPI_DTFDR0_PCS6        (0x00400000)            /* Peripheral chip select 6 */
+#define MCF_DSPI_DTFDR0_PCS7        (0x00800000)            /* Peripheral chip select 7 */
+#define MCF_DSPI_DTFDR0_CTCNT       (0x04000000)            /* Clear SPI transfer counter */
+#define MCF_DSPI_DTFDR0_EOQ         (0x08000000)            /* End of queue */
+#define MCF_DSPI_DTFDR0_CTAS(x)     (((x)&0x00000007)<<28)  /* Clock and transfer attributes select */
+#define MCF_DSPI_DTFDR0_CONT        (0x80000000)            /* Continuous peripheral chip-select enable */
+
+/* Bit definitions and macros for DTFDR1 */
+#define MCF_DSPI_DTFDR1_TXDATA(x)   (((x)&0x0000FFFF))      /* Transmit data */
+#define MCF_DSPI_DTFDR1_PCS0        (0x00010000)            /* Peripheral chip select 0 */
+#define MCF_DSPI_DTFDR1_PCS1        (0x00020000)            /* Peripheral chip select 1 */
+#define MCF_DSPI_DTFDR1_PCS2        (0x00040000)            /* Peripheral chip select 2 */
+#define MCF_DSPI_DTFDR1_PCS3        (0x00080000)            /* Peripheral chip select 3 */
+#define MCF_DSPI_DTFDR1_PCS4        (0x00100000)            /* Peripheral chip select 4 */
+#define MCF_DSPI_DTFDR1_PCS5        (0x00200000)            /* Peripheral chip select 5 */
+#define MCF_DSPI_DTFDR1_PCS6        (0x00400000)            /* Peripheral chip select 6 */
+#define MCF_DSPI_DTFDR1_PCS7        (0x00800000)            /* Peripheral chip select 7 */
+#define MCF_DSPI_DTFDR1_CTCNT       (0x04000000)            /* Clear SPI transfer counter */
+#define MCF_DSPI_DTFDR1_EOQ         (0x08000000)            /* End of queue */
+#define MCF_DSPI_DTFDR1_CTAS(x)     (((x)&0x00000007)<<28)  /* Clock and transfer attributes select */
+#define MCF_DSPI_DTFDR1_CONT        (0x80000000)            /* Continuous peripheral chip-select enable */
+
+/* Bit definitions and macros for DTFDR2 */
+#define MCF_DSPI_DTFDR2_TXDATA(x)   (((x)&0x0000FFFF))      /* Transmit data */
+#define MCF_DSPI_DTFDR2_PCS0        (0x00010000)            /* Peripheral chip select 0 */
+#define MCF_DSPI_DTFDR2_PCS1        (0x00020000)            /* Peripheral chip select 1 */
+#define MCF_DSPI_DTFDR2_PCS2        (0x00040000)            /* Peripheral chip select 2 */
+#define MCF_DSPI_DTFDR2_PCS3        (0x00080000)            /* Peripheral chip select 3 */
+#define MCF_DSPI_DTFDR2_PCS4        (0x00100000)            /* Peripheral chip select 4 */
+#define MCF_DSPI_DTFDR2_PCS5        (0x00200000)            /* Peripheral chip select 5 */
+#define MCF_DSPI_DTFDR2_PCS6        (0x00400000)            /* Peripheral chip select 6 */
+#define MCF_DSPI_DTFDR2_PCS7        (0x00800000)            /* Peripheral chip select 7 */
+#define MCF_DSPI_DTFDR2_CTCNT       (0x04000000)            /* Clear SPI transfer counter */
+#define MCF_DSPI_DTFDR2_EOQ         (0x08000000)            /* End of queue */
+#define MCF_DSPI_DTFDR2_CTAS(x)     (((x)&0x00000007)<<28)  /* Clock and transfer attributes select */
+#define MCF_DSPI_DTFDR2_CONT        (0x80000000)            /* Continuous peripheral chip-select enable */
+
+/* Bit definitions and macros for DTFDR3 */
+#define MCF_DSPI_DTFDR3_TXDATA(x)   (((x)&0x0000FFFF))      /* Transmit data */
+#define MCF_DSPI_DTFDR3_PCS0        (0x00010000)            /* Peripheral chip select 0 */
+#define MCF_DSPI_DTFDR3_PCS1        (0x00020000)            /* Peripheral chip select 1 */
+#define MCF_DSPI_DTFDR3_PCS2        (0x00040000)            /* Peripheral chip select 2 */
+#define MCF_DSPI_DTFDR3_PCS3        (0x00080000)            /* Peripheral chip select 3 */
+#define MCF_DSPI_DTFDR3_PCS4        (0x00100000)            /* Peripheral chip select 4 */
+#define MCF_DSPI_DTFDR3_PCS5        (0x00200000)            /* Peripheral chip select 5 */
+#define MCF_DSPI_DTFDR3_PCS6        (0x00400000)            /* Peripheral chip select 6 */
+#define MCF_DSPI_DTFDR3_PCS7        (0x00800000)            /* Peripheral chip select 7 */
+#define MCF_DSPI_DTFDR3_CTCNT       (0x04000000)            /* Clear SPI transfer counter */
+#define MCF_DSPI_DTFDR3_EOQ         (0x08000000)            /* End of queue */
+#define MCF_DSPI_DTFDR3_CTAS(x)     (((x)&0x00000007)<<28)  /* Clock and transfer attributes select */
+#define MCF_DSPI_DTFDR3_CONT        (0x80000000)            /* Continuous peripheral chip-select enable */
+
+/* Bit definitions and macros for DRFDR group */
+#define MCF_DSPI_DRFDR_RXDATA(x)    (((x)&0x0000FFFF))  /* Receive data */
+
+/* Bit definitions and macros for DRFDR0 */
+#define MCF_DSPI_DRFDR0_RXDATA(x)   (((x)&0x0000FFFF))  /* Receive data */
+
+/* Bit definitions and macros for DRFDR1 */
+#define MCF_DSPI_DRFDR1_RXDATA(x)   (((x)&0x0000FFFF))  /* Receive data */
+
+/* Bit definitions and macros for DRFDR2 */
+#define MCF_DSPI_DRFDR2_RXDATA(x)   (((x)&0x0000FFFF))  /* Receive data */
+
+/* Bit definitions and macros for DRFDR3 */
+#define MCF_DSPI_DRFDR3_RXDATA(x)   (((x)&0x0000FFFF))  /* Receive data */
+
+/********************************************************************/
+
+#endif /* __MCF5445X_DSPI_H__ */
--- /dev/null
+++ b/include/asm-m68k/mcf5445x_dtim.h
@@ -0,0 +1,87 @@
+/*
+ * Matt Waddel Matt.Waddel@freescale.com
+ *
+ * Copyright Freescale Semiconductor, Inc. 2007
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MCF5445X_DTIM_H__
+#define __MCF5445X_DTIM_H__
+
+/*********************************************************************
+*
+* DMA Timers (DTIM)
+*
+*********************************************************************/
+/* Register read/write macros */
+#define MCF_DTIM0_DTMR	0xFC070000	/* DMA Timer Mode Register */
+#define MCF_DTIM0_DTXMR	0xFC070002	/* DMA Timer Extended Mode Register */
+#define MCF_DTIM0_DTER	0xFC070003	/* DMA Timer Event Register */
+#define MCF_DTIM0_DTRR	0xFC070004	/* DMA Timer Reference Register */
+#define MCF_DTIM0_DTCR	0xFC070008	/* DMA Timer Capture Register */
+#define MCF_DTIM0_DTCN	0xFC07000C	/* DMA Timer Counter Register */
+#define MCF_DTIM1_DTMR	0xFC074000	/* DMA Timer Mode Register */
+#define MCF_DTIM1_DTXMR	0xFC074002	/* DMA Timer Extended Mode Register */
+#define MCF_DTIM1_DTER	0xFC074003	/* DMA Timer Event Register */
+#define MCF_DTIM1_DTRR	0xFC074004	/* DMA Timer Reference Register */
+#define MCF_DTIM1_DTCR	0xFC074008	/* DMA Timer Capture Register */
+#define MCF_DTIM1_DTCN	0xFC07400C	/* DMA Timer Counter Register */
+#define MCF_DTIM2_DTMR	0xFC078000	/* DMA Timer Mode Register */
+#define MCF_DTIM2_DTXMR	0xFC078002	/* DMA Timer Extended Mode Register */
+#define MCF_DTIM2_DTER	0xFC078003	/* DMA Timer Event Register */
+#define MCF_DTIM2_DTRR	0xFC078004	/* DMA Timer Reference Register */
+#define MCF_DTIM2_DTCR	0xFC078008	/* DMA Timer Capture Register */
+#define MCF_DTIM2_DTCN	0xFC07800C	/* DMA Timer Counter Register */
+#define MCF_DTIM3_DTMR	0xFC07C000	/* DMA Timer Mode Register */
+#define MCF_DTIM3_DTXMR	0xFC07C002	/* DMA Timer Extended Mode Register */
+#define MCF_DTIM3_DTER	0xFC07C003	/* DMA Timer Event Register */
+#define MCF_DTIM3_DTRR	0xFC07C004	/* DMA Timer Reference Register */
+#define MCF_DTIM3_DTCR	0xFC07C008	/* DMA Timer Capture Register */
+#define MCF_DTIM3_DTCN	0xFC07C00C	/* DMA Timer Counter Register */
+
+/* Parameterized register read/write macros for multiple modules */
+#define MCF_DTIM_DTMR(x)	0xFC070000+((x)*0x4000)  /* DMA Timer Mode Register */
+#define MCF_DTIM_DTXMR(x)	0xFC070002+((x)*0x4000)  /* DMA Timer Extended Mode Register */
+#define MCF_DTIM_DTER(x)	0xFC070003+((x)*0x4000)  /* DMA Timer Event Register */
+#define MCF_DTIM_DTRR(x)	0xFC070004+((x)*0x4000)  /* DMA Timer Reference Register */
+#define MCF_DTIM_DTCR(x)	0xFC070008+((x)*0x4000)  /* DMA Timer Capture Register */
+#define MCF_DTIM_DTCN(x)	0xFC07000C+((x)*0x4000)  /* DMA Timer Counter Register */
+
+/* Bit definitions and macros for DTMR */
+#define MCF_DTIM_DTMR_RST	(0x0001)		/* Reset */
+#define MCF_DTIM_DTMR_CLK(x)	(((x)&0x0003)<<1)	/* Input clock source */
+#define MCF_DTIM_DTMR_FRR	(0x0008)		/* Free run/restart */
+#define MCF_DTIM_DTMR_ORRI	(0x0010)		/* Output reference request/interrupt enable */
+#define MCF_DTIM_DTMR_OM	(0x0020)		/* Output Mode */
+#define MCF_DTIM_DTMR_CE(x)	(((x)&0x0003)<<6)	/* Capture Edge */
+#define MCF_DTIM_DTMR_PS(x)	(((x)&0x00FF)<<8)	/* Prescaler value */
+#define MCF_DTIM_DTMR_RST_EN	(0x0001)
+#define MCF_DTIM_DTMR_RST_RST	(0x0000)
+#define MCF_DTIM_DTMR_CE_ANY	(0x00C0)
+#define MCF_DTIM_DTMR_CE_FALL	(0x0080)
+#define MCF_DTIM_DTMR_CE_RISE	(0x0040)
+#define MCF_DTIM_DTMR_CE_NONE	(0x0000)
+#define MCF_DTIM_DTMR_CLK_DTIN	(0x0006)
+#define MCF_DTIM_DTMR_CLK_DIV16	(0x0004)
+#define MCF_DTIM_DTMR_CLK_DIV1	(0x0002)
+#define MCF_DTIM_DTMR_CLK_STOP	(0x0000)
+
+/* Bit definitions and macros for DTXMR */
+#define MCF_DTIM_DTXMR_MODE16	(0x01)	/* Increment Mode */
+#define MCF_DTIM_DTXMR_DMAEN	(0x80)	/* DMA request */
+
+/* Bit definitions and macros for DTER */
+#define MCF_DTIM_DTER_CAP	(0x01)	/* Capture event */
+#define MCF_DTIM_DTER_REF	(0x02)	/* Output reference event */
+
+/* Interrupts used for system timers */
+#define MCFSIM_ICR_TIMER1       (0xFC048040+32)
+#define MCFSIM_ICR_TIMER2       (0xFC048040+33)
+
+/********************************************************************/
+
+#endif /* __MCF5445X_DTIM_H__ */
--- /dev/null
+++ b/include/asm-m68k/mcf5445x_edma.h
@@ -0,0 +1,1458 @@
+/*
+ * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
+ *
+ * Copyright Freescale Semiconductor, Inc. 2007
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef __MCF5445X_EDMA_H__
+#define __MCF5445X_EDMA_H__
+
+/*********************************************************************
+*
+* Enhanced DMA (EDMA)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_EDMA_CR                     MCF_REG32(0xFC044000)
+#define MCF_EDMA_ES                     MCF_REG32(0xFC044004)
+#define MCF_EDMA_ERQ                    MCF_REG16(0xFC04400E)
+#define MCF_EDMA_EEI                    MCF_REG16(0xFC044016)
+#define MCF_EDMA_SERQ                   MCF_REG08(0xFC044018)
+#define MCF_EDMA_CERQ                   MCF_REG08(0xFC044019)
+#define MCF_EDMA_SEEI                   MCF_REG08(0xFC04401A)
+#define MCF_EDMA_CEEI                   MCF_REG08(0xFC04401B)
+#define MCF_EDMA_CINT                   MCF_REG08(0xFC04401C)
+#define MCF_EDMA_CERR                   MCF_REG08(0xFC04401D)
+#define MCF_EDMA_SSRT                   MCF_REG08(0xFC04401E)
+#define MCF_EDMA_CDNE                   MCF_REG08(0xFC04401F)
+#define MCF_EDMA_INTR                   MCF_REG16(0xFC044026)
+#define MCF_EDMA_ERR                    MCF_REG16(0xFC04402E)
+#define MCF_EDMA_DCHPRI0                MCF_REG08(0xFC044100)
+#define MCF_EDMA_DCHPRI1                MCF_REG08(0xFC044101)
+#define MCF_EDMA_DCHPRI2                MCF_REG08(0xFC044102)
+#define MCF_EDMA_DCHPRI3                MCF_REG08(0xFC044103)
+#define MCF_EDMA_DCHPRI4                MCF_REG08(0xFC044104)
+#define MCF_EDMA_DCHPRI5                MCF_REG08(0xFC044105)
+#define MCF_EDMA_DCHPRI6                MCF_REG08(0xFC044106)
+#define MCF_EDMA_DCHPRI7                MCF_REG08(0xFC044107)
+#define MCF_EDMA_DCHPRI8                MCF_REG08(0xFC044108)
+#define MCF_EDMA_DCHPRI9                MCF_REG08(0xFC044109)
+#define MCF_EDMA_DCHPRI10               MCF_REG08(0xFC04410A)
+#define MCF_EDMA_DCHPRI11               MCF_REG08(0xFC04410B)
+#define MCF_EDMA_DCHPRI12               MCF_REG08(0xFC04410C)
+#define MCF_EDMA_DCHPRI13               MCF_REG08(0xFC04410D)
+#define MCF_EDMA_DCHPRI14               MCF_REG08(0xFC04410E)
+#define MCF_EDMA_DCHPRI15               MCF_REG08(0xFC04410F)
+#define MCF_EDMA_TCD0_SADDR             MCF_REG32(0xFC045000)
+#define MCF_EDMA_TCD0_ATTR              MCF_REG16(0xFC045004)
+#define MCF_EDMA_TCD0_SOFF              MCF_REG16(0xFC045006)
+#define MCF_EDMA_TCD0_NBYTES            MCF_REG32(0xFC045008)
+#define MCF_EDMA_TCD0_SLAST             MCF_REG32(0xFC04500C)
+#define MCF_EDMA_TCD0_DADDR             MCF_REG32(0xFC045010)
+#define MCF_EDMA_TCD0_CITER_ELINK       MCF_REG16(0xFC045014)
+#define MCF_EDMA_TCD0_CITER             MCF_REG16(0xFC045014)
+#define MCF_EDMA_TCD0_DOFF              MCF_REG16(0xFC045016)
+#define MCF_EDMA_TCD0_DLAST_SGA         MCF_REG32(0xFC045018)
+#define MCF_EDMA_TCD0_BITER_ELINK       MCF_REG16(0xFC04501C)
+#define MCF_EDMA_TCD0_BITER             MCF_REG16(0xFC04501C)
+#define MCF_EDMA_TCD0_CSR               MCF_REG16(0xFC04501E)
+#define MCF_EDMA_TCD1_SADDR             MCF_REG32(0xFC045020)
+#define MCF_EDMA_TCD1_ATTR              MCF_REG16(0xFC045024)
+#define MCF_EDMA_TCD1_SOFF              MCF_REG16(0xFC045026)
+#define MCF_EDMA_TCD1_NBYTES            MCF_REG32(0xFC045028)
+#define MCF_EDMA_TCD1_SLAST             MCF_REG32(0xFC04502C)
+#define MCF_EDMA_TCD1_DADDR             MCF_REG32(0xFC045030)
+#define MCF_EDMA_TCD1_CITER_ELINK       MCF_REG16(0xFC045034)
+#define MCF_EDMA_TCD1_CITER             MCF_REG16(0xFC045034)
+#define MCF_EDMA_TCD1_DOFF              MCF_REG16(0xFC045036)
+#define MCF_EDMA_TCD1_DLAST_SGA         MCF_REG32(0xFC045038)
+#define MCF_EDMA_TCD1_BITER             MCF_REG16(0xFC04503C)
+#define MCF_EDMA_TCD1_BITER_ELINK       MCF_REG16(0xFC04503C)
+#define MCF_EDMA_TCD1_CSR               MCF_REG16(0xFC04503E)
+#define MCF_EDMA_TCD2_SADDR             MCF_REG32(0xFC045040)
+#define MCF_EDMA_TCD2_ATTR              MCF_REG16(0xFC045044)
+#define MCF_EDMA_TCD2_SOFF              MCF_REG16(0xFC045046)
+#define MCF_EDMA_TCD2_NBYTES            MCF_REG32(0xFC045048)
+#define MCF_EDMA_TCD2_SLAST             MCF_REG32(0xFC04504C)
+#define MCF_EDMA_TCD2_DADDR             MCF_REG32(0xFC045050)
+#define MCF_EDMA_TCD2_CITER             MCF_REG16(0xFC045054)
+#define MCF_EDMA_TCD2_CITER_ELINK       MCF_REG16(0xFC045054)
+#define MCF_EDMA_TCD2_DOFF              MCF_REG16(0xFC045056)
+#define MCF_EDMA_TCD2_DLAST_SGA         MCF_REG32(0xFC045058)
+#define MCF_EDMA_TCD2_BITER_ELINK       MCF_REG16(0xFC04505C)
+#define MCF_EDMA_TCD2_BITER             MCF_REG16(0xFC04505C)
+#define MCF_EDMA_TCD2_CSR               MCF_REG16(0xFC04505E)
+#define MCF_EDMA_TCD3_SADDR             MCF_REG32(0xFC045060)
+#define MCF_EDMA_TCD3_ATTR              MCF_REG16(0xFC045064)
+#define MCF_EDMA_TCD3_SOFF              MCF_REG16(0xFC045066)
+#define MCF_EDMA_TCD3_NBYTES            MCF_REG32(0xFC045068)
+#define MCF_EDMA_TCD3_SLAST             MCF_REG32(0xFC04506C)
+#define MCF_EDMA_TCD3_DADDR             MCF_REG32(0xFC045070)
+#define MCF_EDMA_TCD3_CITER             MCF_REG16(0xFC045074)
+#define MCF_EDMA_TCD3_CITER_ELINK       MCF_REG16(0xFC045074)
+#define MCF_EDMA_TCD3_DOFF              MCF_REG16(0xFC045076)
+#define MCF_EDMA_TCD3_DLAST_SGA         MCF_REG32(0xFC045078)
+#define MCF_EDMA_TCD3_BITER_ELINK       MCF_REG16(0xFC04507C)
+#define MCF_EDMA_TCD3_BITER             MCF_REG16(0xFC04507C)
+#define MCF_EDMA_TCD3_CSR               MCF_REG16(0xFC04507E)
+#define MCF_EDMA_TCD4_SADDR             MCF_REG32(0xFC045080)
+#define MCF_EDMA_TCD4_ATTR              MCF_REG16(0xFC045084)
+#define MCF_EDMA_TCD4_SOFF              MCF_REG16(0xFC045086)
+#define MCF_EDMA_TCD4_NBYTES            MCF_REG32(0xFC045088)
+#define MCF_EDMA_TCD4_SLAST             MCF_REG32(0xFC04508C)
+#define MCF_EDMA_TCD4_DADDR             MCF_REG32(0xFC045090)
+#define MCF_EDMA_TCD4_CITER             MCF_REG16(0xFC045094)
+#define MCF_EDMA_TCD4_CITER_ELINK       MCF_REG16(0xFC045094)
+#define MCF_EDMA_TCD4_DOFF              MCF_REG16(0xFC045096)
+#define MCF_EDMA_TCD4_DLAST_SGA         MCF_REG32(0xFC045098)
+#define MCF_EDMA_TCD4_BITER             MCF_REG16(0xFC04509C)
+#define MCF_EDMA_TCD4_BITER_ELINK       MCF_REG16(0xFC04509C)
+#define MCF_EDMA_TCD4_CSR               MCF_REG16(0xFC04509E)
+#define MCF_EDMA_TCD5_SADDR             MCF_REG32(0xFC0450A0)
+#define MCF_EDMA_TCD5_ATTR              MCF_REG16(0xFC0450A4)
+#define MCF_EDMA_TCD5_SOFF              MCF_REG16(0xFC0450A6)
+#define MCF_EDMA_TCD5_NBYTES            MCF_REG32(0xFC0450A8)
+#define MCF_EDMA_TCD5_SLAST             MCF_REG32(0xFC0450AC)
+#define MCF_EDMA_TCD5_DADDR             MCF_REG32(0xFC0450B0)
+#define MCF_EDMA_TCD5_CITER             MCF_REG16(0xFC0450B4)
+#define MCF_EDMA_TCD5_CITER_ELINK       MCF_REG16(0xFC0450B4)
+#define MCF_EDMA_TCD5_DOFF              MCF_REG16(0xFC0450B6)
+#define MCF_EDMA_TCD5_DLAST_SGA         MCF_REG32(0xFC0450B8)
+#define MCF_EDMA_TCD5_BITER_ELINK       MCF_REG16(0xFC0450BC)
+#define MCF_EDMA_TCD5_BITER             MCF_REG16(0xFC0450BC)
+#define MCF_EDMA_TCD5_CSR               MCF_REG16(0xFC0450BE)
+#define MCF_EDMA_TCD6_SADDR             MCF_REG32(0xFC0450C0)
+#define MCF_EDMA_TCD6_ATTR              MCF_REG16(0xFC0450C4)
+#define MCF_EDMA_TCD6_SOFF              MCF_REG16(0xFC0450C6)
+#define MCF_EDMA_TCD6_NBYTES            MCF_REG32(0xFC0450C8)
+#define MCF_EDMA_TCD6_SLAST             MCF_REG32(0xFC0450CC)
+#define MCF_EDMA_TCD6_DADDR             MCF_REG32(0xFC0450D0)
+#define MCF_EDMA_TCD6_CITER             MCF_REG16(0xFC0450D4)
+#define MCF_EDMA_TCD6_CITER_ELINK       MCF_REG16(0xFC0450D4)
+#define MCF_EDMA_TCD6_DOFF              MCF_REG16(0xFC0450D6)
+#define MCF_EDMA_TCD6_DLAST_SGA         MCF_REG32(0xFC0450D8)
+#define MCF_EDMA_TCD6_BITER_ELINK       MCF_REG16(0xFC0450DC)
+#define MCF_EDMA_TCD6_BITER             MCF_REG16(0xFC0450DC)
+#define MCF_EDMA_TCD6_CSR               MCF_REG16(0xFC0450DE)
+#define MCF_EDMA_TCD7_SADDR             MCF_REG32(0xFC0450E0)
+#define MCF_EDMA_TCD7_ATTR              MCF_REG16(0xFC0450E4)
+#define MCF_EDMA_TCD7_SOFF              MCF_REG16(0xFC0450E6)
+#define MCF_EDMA_TCD7_NBYTES            MCF_REG32(0xFC0450E8)
+#define MCF_EDMA_TCD7_SLAST             MCF_REG32(0xFC0450EC)
+#define MCF_EDMA_TCD7_DADDR             MCF_REG32(0xFC0450F0)
+#define MCF_EDMA_TCD7_CITER             MCF_REG16(0xFC0450F4)
+#define MCF_EDMA_TCD7_CITER_ELINK       MCF_REG16(0xFC0450F4)
+#define MCF_EDMA_TCD7_DOFF              MCF_REG16(0xFC0450F6)
+#define MCF_EDMA_TCD7_DLAST_SGA         MCF_REG32(0xFC0450F8)
+#define MCF_EDMA_TCD7_BITER_ELINK       MCF_REG16(0xFC0450FC)
+#define MCF_EDMA_TCD7_BITER             MCF_REG16(0xFC0450FC)
+#define MCF_EDMA_TCD7_CSR               MCF_REG16(0xFC0450FE)
+#define MCF_EDMA_TCD8_SADDR             MCF_REG32(0xFC045100)
+#define MCF_EDMA_TCD8_ATTR              MCF_REG16(0xFC045104)
+#define MCF_EDMA_TCD8_SOFF              MCF_REG16(0xFC045106)
+#define MCF_EDMA_TCD8_NBYTES            MCF_REG32(0xFC045108)
+#define MCF_EDMA_TCD8_SLAST             MCF_REG32(0xFC04510C)
+#define MCF_EDMA_TCD8_DADDR             MCF_REG32(0xFC045110)
+#define MCF_EDMA_TCD8_CITER             MCF_REG16(0xFC045114)
+#define MCF_EDMA_TCD8_CITER_ELINK       MCF_REG16(0xFC045114)
+#define MCF_EDMA_TCD8_DOFF              MCF_REG16(0xFC045116)
+#define MCF_EDMA_TCD8_DLAST_SGA         MCF_REG32(0xFC045118)
+#define MCF_EDMA_TCD8_BITER_ELINK       MCF_REG16(0xFC04511C)
+#define MCF_EDMA_TCD8_BITER             MCF_REG16(0xFC04511C)
+#define MCF_EDMA_TCD8_CSR               MCF_REG16(0xFC04511E)
+#define MCF_EDMA_TCD9_SADDR             MCF_REG32(0xFC045120)
+#define MCF_EDMA_TCD9_ATTR              MCF_REG16(0xFC045124)
+#define MCF_EDMA_TCD9_SOFF              MCF_REG16(0xFC045126)
+#define MCF_EDMA_TCD9_NBYTES            MCF_REG32(0xFC045128)
+#define MCF_EDMA_TCD9_SLAST             MCF_REG32(0xFC04512C)
+#define MCF_EDMA_TCD9_DADDR             MCF_REG32(0xFC045130)
+#define MCF_EDMA_TCD9_CITER_ELINK       MCF_REG16(0xFC045134)
+#define MCF_EDMA_TCD9_CITER             MCF_REG16(0xFC045134)
+#define MCF_EDMA_TCD9_DOFF              MCF_REG16(0xFC045136)
+#define MCF_EDMA_TCD9_DLAST_SGA         MCF_REG32(0xFC045138)
+#define MCF_EDMA_TCD9_BITER_ELINK       MCF_REG16(0xFC04513C)
+#define MCF_EDMA_TCD9_BITER             MCF_REG16(0xFC04513C)
+#define MCF_EDMA_TCD9_CSR               MCF_REG16(0xFC04513E)
+#define MCF_EDMA_TCD10_SADDR            MCF_REG32(0xFC045140)
+#define MCF_EDMA_TCD10_ATTR             MCF_REG16(0xFC045144)
+#define MCF_EDMA_TCD10_SOFF             MCF_REG16(0xFC045146)
+#define MCF_EDMA_TCD10_NBYTES           MCF_REG32(0xFC045148)
+#define MCF_EDMA_TCD10_SLAST            MCF_REG32(0xFC04514C)
+#define MCF_EDMA_TCD10_DADDR            MCF_REG32(0xFC045150)
+#define MCF_EDMA_TCD10_CITER_ELINK      MCF_REG16(0xFC045154)
+#define MCF_EDMA_TCD10_CITER            MCF_REG16(0xFC045154)
+#define MCF_EDMA_TCD10_DOFF             MCF_REG16(0xFC045156)
+#define MCF_EDMA_TCD10_DLAST_SGA        MCF_REG32(0xFC045158)
+#define MCF_EDMA_TCD10_BITER            MCF_REG16(0xFC04515C)
+#define MCF_EDMA_TCD10_BITER_ELINK      MCF_REG16(0xFC04515C)
+#define MCF_EDMA_TCD10_CSR              MCF_REG16(0xFC04515E)
+#define MCF_EDMA_TCD11_SADDR            MCF_REG32(0xFC045160)
+#define MCF_EDMA_TCD11_ATTR             MCF_REG16(0xFC045164)
+#define MCF_EDMA_TCD11_SOFF             MCF_REG16(0xFC045166)
+#define MCF_EDMA_TCD11_NBYTES           MCF_REG32(0xFC045168)
+#define MCF_EDMA_TCD11_SLAST            MCF_REG32(0xFC04516C)
+#define MCF_EDMA_TCD11_DADDR            MCF_REG32(0xFC045170)
+#define MCF_EDMA_TCD11_CITER            MCF_REG16(0xFC045174)
+#define MCF_EDMA_TCD11_CITER_ELINK      MCF_REG16(0xFC045174)
+#define MCF_EDMA_TCD11_DOFF             MCF_REG16(0xFC045176)
+#define MCF_EDMA_TCD11_DLAST_SGA        MCF_REG32(0xFC045178)
+#define MCF_EDMA_TCD11_BITER            MCF_REG16(0xFC04517C)
+#define MCF_EDMA_TCD11_BITER_ELINK      MCF_REG16(0xFC04517C)
+#define MCF_EDMA_TCD11_CSR              MCF_REG16(0xFC04517E)
+#define MCF_EDMA_TCD12_SADDR            MCF_REG32(0xFC045180)
+#define MCF_EDMA_TCD12_ATTR             MCF_REG16(0xFC045184)
+#define MCF_EDMA_TCD12_SOFF             MCF_REG16(0xFC045186)
+#define MCF_EDMA_TCD12_NBYTES           MCF_REG32(0xFC045188)
+#define MCF_EDMA_TCD12_SLAST            MCF_REG32(0xFC04518C)
+#define MCF_EDMA_TCD12_DADDR            MCF_REG32(0xFC045190)
+#define MCF_EDMA_TCD12_CITER            MCF_REG16(0xFC045194)
+#define MCF_EDMA_TCD12_CITER_ELINK      MCF_REG16(0xFC045194)
+#define MCF_EDMA_TCD12_DOFF             MCF_REG16(0xFC045196)
+#define MCF_EDMA_TCD12_DLAST_SGA        MCF_REG32(0xFC045198)
+#define MCF_EDMA_TCD12_BITER            MCF_REG16(0xFC04519C)
+#define MCF_EDMA_TCD12_BITER_ELINK      MCF_REG16(0xFC04519C)
+#define MCF_EDMA_TCD12_CSR              MCF_REG16(0xFC04519E)
+#define MCF_EDMA_TCD13_SADDR            MCF_REG32(0xFC0451A0)
+#define MCF_EDMA_TCD13_ATTR             MCF_REG16(0xFC0451A4)
+#define MCF_EDMA_TCD13_SOFF             MCF_REG16(0xFC0451A6)
+#define MCF_EDMA_TCD13_NBYTES           MCF_REG32(0xFC0451A8)
+#define MCF_EDMA_TCD13_SLAST            MCF_REG32(0xFC0451AC)
+#define MCF_EDMA_TCD13_DADDR            MCF_REG32(0xFC0451B0)
+#define MCF_EDMA_TCD13_CITER_ELINK      MCF_REG16(0xFC0451B4)
+#define MCF_EDMA_TCD13_CITER            MCF_REG16(0xFC0451B4)
+#define MCF_EDMA_TCD13_DOFF             MCF_REG16(0xFC0451B6)
+#define MCF_EDMA_TCD13_DLAST_SGA        MCF_REG32(0xFC0451B8)
+#define MCF_EDMA_TCD13_BITER_ELINK      MCF_REG16(0xFC0451BC)
+#define MCF_EDMA_TCD13_BITER            MCF_REG16(0xFC0451BC)
+#define MCF_EDMA_TCD13_CSR              MCF_REG16(0xFC0451BE)
+#define MCF_EDMA_TCD14_SADDR            MCF_REG32(0xFC0451C0)
+#define MCF_EDMA_TCD14_ATTR             MCF_REG16(0xFC0451C4)
+#define MCF_EDMA_TCD14_SOFF             MCF_REG16(0xFC0451C6)
+#define MCF_EDMA_TCD14_NBYTES           MCF_REG32(0xFC0451C8)
+#define MCF_EDMA_TCD14_SLAST            MCF_REG32(0xFC0451CC)
+#define MCF_EDMA_TCD14_DADDR            MCF_REG32(0xFC0451D0)
+#define MCF_EDMA_TCD14_CITER            MCF_REG16(0xFC0451D4)
+#define MCF_EDMA_TCD14_CITER_ELINK      MCF_REG16(0xFC0451D4)
+#define MCF_EDMA_TCD14_DOFF             MCF_REG16(0xFC0451D6)
+#define MCF_EDMA_TCD14_DLAST_SGA        MCF_REG32(0xFC0451D8)
+#define MCF_EDMA_TCD14_BITER_ELINK      MCF_REG16(0xFC0451DC)
+#define MCF_EDMA_TCD14_BITER            MCF_REG16(0xFC0451DC)
+#define MCF_EDMA_TCD14_CSR              MCF_REG16(0xFC0451DE)
+#define MCF_EDMA_TCD15_SADDR            MCF_REG32(0xFC0451E0)
+#define MCF_EDMA_TCD15_ATTR             MCF_REG16(0xFC0451E4)
+#define MCF_EDMA_TCD15_SOFF             MCF_REG16(0xFC0451E6)
+#define MCF_EDMA_TCD15_NBYTES           MCF_REG32(0xFC0451E8)
+#define MCF_EDMA_TCD15_SLAST            MCF_REG32(0xFC0451EC)
+#define MCF_EDMA_TCD15_DADDR            MCF_REG32(0xFC0451F0)
+#define MCF_EDMA_TCD15_CITER_ELINK      MCF_REG16(0xFC0451F4)
+#define MCF_EDMA_TCD15_CITER            MCF_REG16(0xFC0451F4)
+#define MCF_EDMA_TCD15_DOFF             MCF_REG16(0xFC0451F6)
+#define MCF_EDMA_TCD15_DLAST_SGA        MCF_REG32(0xFC0451F8)
+#define MCF_EDMA_TCD15_BITER            MCF_REG16(0xFC0451FC)
+#define MCF_EDMA_TCD15_BITER_ELINK      MCF_REG16(0xFC0451FC)
+#define MCF_EDMA_TCD15_CSR              MCF_REG16(0xFC0451FE)
+
+/* Parameterized register read/write macros for multiple registers */
+#define MCF_EDMA_DCHPRI(x)              MCF_REG08(0xFC044100+((x)*0x001))
+#define MCF_EDMA_TCD_SADDR(x)           MCF_REG32(0xFC045000+((x)*0x020))
+#define MCF_EDMA_TCD_ATTR(x)            MCF_REG16(0xFC045004+((x)*0x020))
+#define MCF_EDMA_TCD_SOFF(x)            MCF_REG16(0xFC045006+((x)*0x020))
+#define MCF_EDMA_TCD_NBYTES(x)          MCF_REG32(0xFC045008+((x)*0x020))
+#define MCF_EDMA_TCD_SLAST(x)           MCF_REG32(0xFC04500C+((x)*0x020))
+#define MCF_EDMA_TCD_DADDR(x)           MCF_REG32(0xFC045010+((x)*0x020))
+#define MCF_EDMA_TCD_CITER_ELINK(x)     MCF_REG16(0xFC045014+((x)*0x020))
+#define MCF_EDMA_TCD_CITER(x)           MCF_REG16(0xFC045014+((x)*0x020))
+#define MCF_EDMA_TCD_DOFF(x)            MCF_REG16(0xFC045016+((x)*0x020))
+#define MCF_EDMA_TCD_DLAST_SGA(x)       MCF_REG32(0xFC045018+((x)*0x020))
+#define MCF_EDMA_TCD_BITER_ELINK(x)     MCF_REG16(0xFC04501C+((x)*0x020))
+#define MCF_EDMA_TCD_BITER(x)           MCF_REG16(0xFC04501C+((x)*0x020))
+#define MCF_EDMA_TCD_CSR(x)             MCF_REG16(0xFC04501e +((x)*0x020))
+
+/* Bit definitions and macros for CR */
+#define MCF_EDMA_CR_EDBG        (0x00000002)
+#define MCF_EDMA_CR_ERCA        (0x00000004)
+
+/* Bit definitions and macros for ES */
+#define MCF_EDMA_ES_DBE         (0x00000001)
+#define MCF_EDMA_ES_SBE         (0x00000002)
+#define MCF_EDMA_ES_SGE         (0x00000004)
+#define MCF_EDMA_ES_NCE         (0x00000008)
+#define MCF_EDMA_ES_DOE         (0x00000010)
+#define MCF_EDMA_ES_DAE         (0x00000020)
+#define MCF_EDMA_ES_SOE         (0x00000040)
+#define MCF_EDMA_ES_SAE         (0x00000080)
+#define MCF_EDMA_ES_ERRCHN(x)   (((x)&0x0000000F)<<8)
+#define MCF_EDMA_ES_CPE         (0x00004000)
+#define MCF_EDMA_ES_VLD         (0x80000000)
+
+/* Bit definitions and macros for ERQ */
+#define MCF_EDMA_ERQ_ERQ0       (0x0001)
+#define MCF_EDMA_ERQ_ERQ1       (0x0002)
+#define MCF_EDMA_ERQ_ERQ2       (0x0004)
+#define MCF_EDMA_ERQ_ERQ3       (0x0008)
+#define MCF_EDMA_ERQ_ERQ4       (0x0010)
+#define MCF_EDMA_ERQ_ERQ5       (0x0020)
+#define MCF_EDMA_ERQ_ERQ6       (0x0040)
+#define MCF_EDMA_ERQ_ERQ7       (0x0080)
+#define MCF_EDMA_ERQ_ERQ8       (0x0100)
+#define MCF_EDMA_ERQ_ERQ9       (0x0200)
+#define MCF_EDMA_ERQ_ERQ10      (0x0400)
+#define MCF_EDMA_ERQ_ERQ11      (0x0800)
+#define MCF_EDMA_ERQ_ERQ12      (0x1000)
+#define MCF_EDMA_ERQ_ERQ13      (0x2000)
+#define MCF_EDMA_ERQ_ERQ14      (0x4000)
+#define MCF_EDMA_ERQ_ERQ15      (0x8000)
+
+/* Bit definitions and macros for EEI */
+#define MCF_EDMA_EEI_EEI0       (0x0001)
+#define MCF_EDMA_EEI_EEI1       (0x0002)
+#define MCF_EDMA_EEI_EEI2       (0x0004)
+#define MCF_EDMA_EEI_EEI3       (0x0008)
+#define MCF_EDMA_EEI_EEI4       (0x0010)
+#define MCF_EDMA_EEI_EEI5       (0x0020)
+#define MCF_EDMA_EEI_EEI6       (0x0040)
+#define MCF_EDMA_EEI_EEI7       (0x0080)
+#define MCF_EDMA_EEI_EEI8       (0x0100)
+#define MCF_EDMA_EEI_EEI9       (0x0200)
+#define MCF_EDMA_EEI_EEI10      (0x0400)
+#define MCF_EDMA_EEI_EEI11      (0x0800)
+#define MCF_EDMA_EEI_EEI12      (0x1000)
+#define MCF_EDMA_EEI_EEI13      (0x2000)
+#define MCF_EDMA_EEI_EEI14      (0x4000)
+#define MCF_EDMA_EEI_EEI15      (0x8000)
+
+/* Bit definitions and macros for SERQ */
+#define MCF_EDMA_SERQ_SERQ(x)   (((x)&0x0F))
+#define MCF_EDMA_SERQ_SAER      (0x40)
+
+/* Bit definitions and macros for CERQ */
+#define MCF_EDMA_CERQ_CERQ(x)   (((x)&0x0F))
+#define MCF_EDMA_CERQ_CAER      (0x40)
+
+/* Bit definitions and macros for SEEI */
+#define MCF_EDMA_SEEI_SEEI(x)   (((x)&0x0F))
+#define MCF_EDMA_SEEI_SAEE      (0x40)
+
+/* Bit definitions and macros for CEEI */
+#define MCF_EDMA_CEEI_CEEI(x)   (((x)&0x0F))
+#define MCF_EDMA_CEEI_CAEE      (0x40)
+
+/* Bit definitions and macros for CINT */
+#define MCF_EDMA_CINT_CINT(x)   (((x)&0x0F))
+#define MCF_EDMA_CINT_CAIR      (0x40)
+
+/* Bit definitions and macros for CERR */
+#define MCF_EDMA_CERR_CERR(x)   (((x)&0x0F))
+#define MCF_EDMA_CERR_CAER      (0x40)
+
+/* Bit definitions and macros for SSRT */
+#define MCF_EDMA_SSRT_SSRT(x)   (((x)&0x0F))
+#define MCF_EDMA_SSRT_SAST      (0x40)
+
+/* Bit definitions and macros for CDNE */
+#define MCF_EDMA_CDNE_CDNE(x)   (((x)&0x0F))
+#define MCF_EDMA_CDNE_CADN      (0x40)
+
+/* Bit definitions and macros for INTR */
+#define MCF_EDMA_INTR_INT0      (0x0001)
+#define MCF_EDMA_INTR_INT1      (0x0002)
+#define MCF_EDMA_INTR_INT2      (0x0004)
+#define MCF_EDMA_INTR_INT3      (0x0008)
+#define MCF_EDMA_INTR_INT4      (0x0010)
+#define MCF_EDMA_INTR_INT5      (0x0020)
+#define MCF_EDMA_INTR_INT6      (0x0040)
+#define MCF_EDMA_INTR_INT7      (0x0080)
+#define MCF_EDMA_INTR_INT8      (0x0100)
+#define MCF_EDMA_INTR_INT9      (0x0200)
+#define MCF_EDMA_INTR_INT10     (0x0400)
+#define MCF_EDMA_INTR_INT11     (0x0800)
+#define MCF_EDMA_INTR_INT12     (0x1000)
+#define MCF_EDMA_INTR_INT13     (0x2000)
+#define MCF_EDMA_INTR_INT14     (0x4000)
+#define MCF_EDMA_INTR_INT15     (0x8000)
+
+/* Bit definitions and macros for ERR */
+#define MCF_EDMA_ERR_ERR0       (0x0001)
+#define MCF_EDMA_ERR_ERR1       (0x0002)
+#define MCF_EDMA_ERR_ERR2       (0x0004)
+#define MCF_EDMA_ERR_ERR3       (0x0008)
+#define MCF_EDMA_ERR_ERR4       (0x0010)
+#define MCF_EDMA_ERR_ERR5       (0x0020)
+#define MCF_EDMA_ERR_ERR6       (0x0040)
+#define MCF_EDMA_ERR_ERR7       (0x0080)
+#define MCF_EDMA_ERR_ERR8       (0x0100)
+#define MCF_EDMA_ERR_ERR9       (0x0200)
+#define MCF_EDMA_ERR_ERR10      (0x0400)
+#define MCF_EDMA_ERR_ERR11      (0x0800)
+#define MCF_EDMA_ERR_ERR12      (0x1000)
+#define MCF_EDMA_ERR_ERR13      (0x2000)
+#define MCF_EDMA_ERR_ERR14      (0x4000)
+#define MCF_EDMA_ERR_ERR15      (0x8000)
+
+/* Bit definitions and macros for DCHPRI group */
+#define MCF_EDMA_DCHPRI_CHPRI(x)    (((x)&0x0F))
+#define MCF_EDMA_DCHPRI_ECP         (0x80)
+
+/* Bit definitions and macros for DCHPRI0 */
+#define MCF_EDMA_DCHPRI0_CHPRI(x)   (((x)&0x0F))
+#define MCF_EDMA_DCHPRI0_ECP        (0x80)
+
+/* Bit definitions and macros for DCHPRI1 */
+#define MCF_EDMA_DCHPRI1_CHPRI(x)   (((x)&0x0F))
+#define MCF_EDMA_DCHPRI1_ECP        (0x80)
+
+/* Bit definitions and macros for DCHPRI2 */
+#define MCF_EDMA_DCHPRI2_CHPRI(x)   (((x)&0x0F))
+#define MCF_EDMA_DCHPRI2_ECP        (0x80)
+
+/* Bit definitions and macros for DCHPRI3 */
+#define MCF_EDMA_DCHPRI3_CHPRI(x)   (((x)&0x0F))
+#define MCF_EDMA_DCHPRI3_ECP        (0x80)
+
+/* Bit definitions and macros for DCHPRI4 */
+#define MCF_EDMA_DCHPRI4_CHPRI(x)   (((x)&0x0F))
+#define MCF_EDMA_DCHPRI4_ECP        (0x80)
+
+/* Bit definitions and macros for DCHPRI5 */
+#define MCF_EDMA_DCHPRI5_CHPRI(x)   (((x)&0x0F))
+#define MCF_EDMA_DCHPRI5_ECP        (0x80)
+
+/* Bit definitions and macros for DCHPRI6 */
+#define MCF_EDMA_DCHPRI6_CHPRI(x)   (((x)&0x0F))
+#define MCF_EDMA_DCHPRI6_ECP        (0x80)
+
+/* Bit definitions and macros for DCHPRI7 */
+#define MCF_EDMA_DCHPRI7_CHPRI(x)   (((x)&0x0F))
+#define MCF_EDMA_DCHPRI7_ECP        (0x80)
+
+/* Bit definitions and macros for DCHPRI8 */
+#define MCF_EDMA_DCHPRI8_CHPRI(x)   (((x)&0x0F))
+#define MCF_EDMA_DCHPRI8_ECP        (0x80)
+
+/* Bit definitions and macros for DCHPRI9 */
+#define MCF_EDMA_DCHPRI9_CHPRI(x)   (((x)&0x0F))
+#define MCF_EDMA_DCHPRI9_ECP        (0x80)
+
+/* Bit definitions and macros for DCHPRI10 */
+#define MCF_EDMA_DCHPRI10_CHPRI(x)      (((x)&0x0F))
+#define MCF_EDMA_DCHPRI10_ECP           (0x80)
+
+/* Bit definitions and macros for DCHPRI11 */
+#define MCF_EDMA_DCHPRI11_CHPRI(x)      (((x)&0x0F))
+#define MCF_EDMA_DCHPRI11_ECP           (0x80)
+
+/* Bit definitions and macros for DCHPRI12 */
+#define MCF_EDMA_DCHPRI12_CHPRI(x)      (((x)&0x0F))
+#define MCF_EDMA_DCHPRI12_ECP           (0x80)
+
+/* Bit definitions and macros for DCHPRI13 */
+#define MCF_EDMA_DCHPRI13_CHPRI(x)      (((x)&0x0F))
+#define MCF_EDMA_DCHPRI13_ECP           (0x80)
+
+/* Bit definitions and macros for DCHPRI14 */
+#define MCF_EDMA_DCHPRI14_CHPRI(x)      (((x)&0x0F))
+#define MCF_EDMA_DCHPRI14_ECP           (0x80)
+
+/* Bit definitions and macros for DCHPRI15 */
+#define MCF_EDMA_DCHPRI15_CHPRI(x)      (((x)&0x0F))
+#define MCF_EDMA_DCHPRI15_ECP           (0x80)
+
+/* Bit definitions and macros for TCD_SADDR group */
+#define MCF_EDMA_TCD_SADDR_SADDR(x)     (x)
+
+/* Bit definitions and macros for TCD0_SADDR */
+#define MCF_EDMA_TCD0_SADDR_SADDR(x)    (x)
+
+/* Bit definitions and macros for TCD_ATTR group */
+#define MCF_EDMA_TCD_ATTR_DSIZE(x)          (((x)&0x0007))
+#define MCF_EDMA_TCD_ATTR_DMOD(x)           (((x)&0x001F)<<3)
+#define MCF_EDMA_TCD_ATTR_SSIZE(x)          (((x)&0x0007)<<8)
+#define MCF_EDMA_TCD_ATTR_SMOD(x)           (((x)&0x001F)<<11)
+#define MCF_EDMA_TCD_ATTR_SSIZE_8BIT        (0x0000)
+#define MCF_EDMA_TCD_ATTR_SSIZE_16BIT       (0x0100)
+#define MCF_EDMA_TCD_ATTR_SSIZE_32BIT       (0x0200)
+#define MCF_EDMA_TCD_ATTR_SSIZE_16BYTE      (0x0400)
+#define MCF_EDMA_TCD_ATTR_DSIZE_8BIT        (0x0000)
+#define MCF_EDMA_TCD_ATTR_DSIZE_16BIT       (0x0001)
+#define MCF_EDMA_TCD_ATTR_DSIZE_32BIT       (0x0002)
+#define MCF_EDMA_TCD_ATTR_DSIZE_16BYTE      (0x0004)
+
+/* Bit definitions and macros for TCD0_ATTR */
+#define MCF_EDMA_TCD0_ATTR_DSIZE(x)         (((x)&0x0007))
+#define MCF_EDMA_TCD0_ATTR_DMOD(x)          (((x)&0x001F)<<3)
+#define MCF_EDMA_TCD0_ATTR_SSIZE(x)         (((x)&0x0007)<<8)
+#define MCF_EDMA_TCD0_ATTR_SMOD(x)          (((x)&0x001F)<<11)
+#define MCF_EDMA_TCD0_ATTR_SSIZE_8BIT       (0x0000)
+#define MCF_EDMA_TCD0_ATTR_SSIZE_16BIT      (0x0100)
+#define MCF_EDMA_TCD0_ATTR_SSIZE_32BIT      (0x0200)
+#define MCF_EDMA_TCD0_ATTR_SSIZE_16BYTE     (0x0400)
+#define MCF_EDMA_TCD0_ATTR_DSIZE_8BIT       (0x0000)
+#define MCF_EDMA_TCD0_ATTR_DSIZE_16BIT      (0x0001)
+#define MCF_EDMA_TCD0_ATTR_DSIZE_32BIT      (0x0002)
+#define MCF_EDMA_TCD0_ATTR_DSIZE_16BYTE     (0x0004)
+
+/* Bit definitions and macros for TCD_SOFF group */
+#define MCF_EDMA_TCD_SOFF_SOFF(x)   (x)
+
+/* Bit definitions and macros for TCD0_SOFF */
+#define MCF_EDMA_TCD0_SOFF_SOFF(x)      (x)
+
+/* Bit definitions and macros for TCD_NBYTES group */
+#define MCF_EDMA_TCD_NBYTES_NBYTES(x)   (x)
+
+/* Bit definitions and macros for TCD0_NBYTES */
+#define MCF_EDMA_TCD0_NBYTES_NBYTES(x)      (x)
+
+/* Bit definitions and macros for TCD_SLAST group */
+#define MCF_EDMA_TCD_SLAST_SLAST(x)     (x)
+
+/* Bit definitions and macros for TCD0_SLAST */
+#define MCF_EDMA_TCD0_SLAST_SLAST(x)    (x)
+
+/* Bit definitions and macros for TCD_DADDR group */
+#define MCF_EDMA_TCD_DADDR_DADDR(x)     (x)
+
+/* Bit definitions and macros for TCD0_DADDR */
+#define MCF_EDMA_TCD0_DADDR_DADDR(x)    (x)
+
+/* Bit definitions and macros for TCD_CITER_ELINK group */
+#define MCF_EDMA_TCD_CITER_ELINK_CITER(x)       (((x)&0x01FF))
+#define MCF_EDMA_TCD_CITER_ELINK_LINKCH(x)      (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD_CITER_ELINK_E_LINK         (0x8000)
+
+/* Bit definitions and macros for TCD0_CITER_ELINK */
+#define MCF_EDMA_TCD0_CITER_ELINK_CITER(x)      (((x)&0x01FF))
+#define MCF_EDMA_TCD0_CITER_ELINK_LINKCH(x)     (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD0_CITER_ELINK_E_LINK        (0x8000)
+
+/* Bit definitions and macros for TCD_CITER group */
+#define MCF_EDMA_TCD_CITER_CITER(x)     (((x)&0x7FFF))
+#define MCF_EDMA_TCD_CITER_E_LINK       (0x8000)
+
+/* Bit definitions and macros for TCD0_CITER */
+#define MCF_EDMA_TCD0_CITER_CITER(x)    (((x)&0x7FFF))
+#define MCF_EDMA_TCD0_CITER_E_LINK      (0x8000)
+
+/* Bit definitions and macros for TCD_DOFF group */
+#define MCF_EDMA_TCD_DOFF_DOFF(x)   (x)
+
+/* Bit definitions and macros for TCD0_DOFF */
+#define MCF_EDMA_TCD0_DOFF_DOFF(x)      (x)
+
+/* Bit definitions and macros for TCD_DLAST_SGA group */
+#define MCF_EDMA_TCD_DLAST_SGA_DLAST_SGA(x)     (x)
+
+/* Bit definitions and macros for TCD0_DLAST_SGA */
+#define MCF_EDMA_TCD0_DLAST_SGA_DLAST_SGA(x)    (x)
+
+/* Bit definitions and macros for TCD_BITER_ELINK group */
+#define MCF_EDMA_TCD_BITER_ELINK_BITER(x)       (((x)&0x01FF))
+#define MCF_EDMA_TCD_BITER_ELINK_LINKCH(x)      (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD_BITER_ELINK_E_LINK         (0x8000)
+
+/* Bit definitions and macros for TCD0_BITER_ELINK */
+#define MCF_EDMA_TCD0_BITER_ELINK_BITER(x)      (((x)&0x01FF))
+#define MCF_EDMA_TCD0_BITER_ELINK_LINKCH(x)     (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD0_BITER_ELINK_E_LINK        (0x8000)
+
+/* Bit definitions and macros for TCD_BITER group */
+#define MCF_EDMA_TCD_BITER_BITER(x)     (((x)&0x7FFF))
+#define MCF_EDMA_TCD_BITER_E_LINK       (0x8000)
+
+/* Bit definitions and macros for TCD0_BITER */
+#define MCF_EDMA_TCD0_BITER_BITER(x)    (((x)&0x7FFF))
+#define MCF_EDMA_TCD0_BITER_E_LINK      (0x8000)
+
+/* Bit definitions and macros for TCD_CSR group */
+#define MCF_EDMA_TCD_CSR_START              (0x0001)
+#define MCF_EDMA_TCD_CSR_INT_MAJOR          (0x0002)
+#define MCF_EDMA_TCD_CSR_INT_HALF           (0x0004)
+#define MCF_EDMA_TCD_CSR_D_REQ              (0x0008)
+#define MCF_EDMA_TCD_CSR_E_SG               (0x0010)
+#define MCF_EDMA_TCD_CSR_E_LINK             (0x0020)
+#define MCF_EDMA_TCD_CSR_ACTIVE             (0x0040)
+#define MCF_EDMA_TCD_CSR_DONE               (0x0080)
+#define MCF_EDMA_TCD_CSR_LINKCH(x)          (((x)&0x003F)<<8)
+#define MCF_EDMA_TCD_CSR_BWC(x)             (((x)&0x0003)<<14)
+#define MCF_EDMA_TCD_CSR_BWC_NO_STALL       (0x0000)
+#define MCF_EDMA_TCD_CSR_BWC_4CYC_STALL     (0x8000)
+#define MCF_EDMA_TCD_CSR_BWC_8CYC_STALL     (0xC000)
+
+/* Bit definitions and macros for TCD0_CSR */
+#define MCF_EDMA_TCD0_CSR_START             (0x0001)
+#define MCF_EDMA_TCD0_CSR_INT_MAJOR         (0x0002)
+#define MCF_EDMA_TCD0_CSR_INT_HALF          (0x0004)
+#define MCF_EDMA_TCD0_CSR_D_REQ             (0x0008)
+#define MCF_EDMA_TCD0_CSR_E_SG              (0x0010)
+#define MCF_EDMA_TCD0_CSR_E_LINK            (0x0020)
+#define MCF_EDMA_TCD0_CSR_ACTIVE            (0x0040)
+#define MCF_EDMA_TCD0_CSR_DONE              (0x0080)
+#define MCF_EDMA_TCD0_CSR_LINKCH(x)         (((x)&0x003F)<<8)
+#define MCF_EDMA_TCD0_CSR_BWC(x)            (((x)&0x0003)<<14)
+#define MCF_EDMA_TCD0_CSR_BWC_NO_STALL      (0x0000)
+#define MCF_EDMA_TCD0_CSR_BWC_4CYC_STALL    (0x8000)
+#define MCF_EDMA_TCD0_CSR_BWC_8CYC_STALL    (0xC000)
+
+/* Bit definitions and macros for TCD1_SADDR */
+#define MCF_EDMA_TCD1_SADDR_SADDR(x)    (x)
+
+/* Bit definitions and macros for TCD1_ATTR */
+#define MCF_EDMA_TCD1_ATTR_DSIZE(x)     (((x)&0x0007))
+#define MCF_EDMA_TCD1_ATTR_DMOD(x)      (((x)&0x001F)<<3)
+#define MCF_EDMA_TCD1_ATTR_SSIZE(x)     (((x)&0x0007)<<8)
+#define MCF_EDMA_TCD1_ATTR_SMOD(x)      (((x)&0x001F)<<11)
+
+/* Bit definitions and macros for TCD1_SOFF */
+#define MCF_EDMA_TCD1_SOFF_SOFF(x)      (x)
+
+/* Bit definitions and macros for TCD1_NBYTES */
+#define MCF_EDMA_TCD1_NBYTES_NBYTES(x)      (x)
+
+/* Bit definitions and macros for TCD1_SLAST */
+#define MCF_EDMA_TCD1_SLAST_SLAST(x)    (x)
+
+/* Bit definitions and macros for TCD1_DADDR */
+#define MCF_EDMA_TCD1_DADDR_DADDR(x)    (x)
+
+/* Bit definitions and macros for TCD1_CITER_ELINK */
+#define MCF_EDMA_TCD1_CITER_ELINK_CITER(x)      (((x)&0x01FF))
+#define MCF_EDMA_TCD1_CITER_ELINK_LINKCH(x)     (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD1_CITER_ELINK_E_LINK        (0x8000)
+
+/* Bit definitions and macros for TCD1_CITER */
+#define MCF_EDMA_TCD1_CITER_CITER(x)    (((x)&0x7FFF))
+#define MCF_EDMA_TCD1_CITER_E_LINK      (0x8000)
+
+/* Bit definitions and macros for TCD1_DOFF */
+#define MCF_EDMA_TCD1_DOFF_DOFF(x)      (x)
+
+/* Bit definitions and macros for TCD1_DLAST_SGA */
+#define MCF_EDMA_TCD1_DLAST_SGA_DLAST_SGA(x)    (x)
+
+/* Bit definitions and macros for TCD1_BITER */
+#define MCF_EDMA_TCD1_BITER_BITER(x)    (((x)&0x7FFF))
+#define MCF_EDMA_TCD1_BITER_E_LINK      (0x8000)
+
+/* Bit definitions and macros for TCD1_BITER_ELINK */
+#define MCF_EDMA_TCD1_BITER_ELINK_BITER(x)      (((x)&0x01FF))
+#define MCF_EDMA_TCD1_BITER_ELINK_LINKCH(x)     (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD1_BITER_ELINK_E_LINK        (0x8000)
+
+/* Bit definitions and macros for TCD1_CSR */
+#define MCF_EDMA_TCD1_CSR_START         (0x0001)
+#define MCF_EDMA_TCD1_CSR_INT_MAJOR     (0x0002)
+#define MCF_EDMA_TCD1_CSR_INT_HALF      (0x0004)
+#define MCF_EDMA_TCD1_CSR_D_REQ         (0x0008)
+#define MCF_EDMA_TCD1_CSR_E_SG          (0x0010)
+#define MCF_EDMA_TCD1_CSR_E_LINK        (0x0020)
+#define MCF_EDMA_TCD1_CSR_ACTIVE        (0x0040)
+#define MCF_EDMA_TCD1_CSR_DONE          (0x0080)
+#define MCF_EDMA_TCD1_CSR_LINKCH(x)     (((x)&0x003F)<<8)
+#define MCF_EDMA_TCD1_CSR_BWC(x)        (((x)&0x0003)<<14)
+
+/* Bit definitions and macros for TCD2_SADDR */
+#define MCF_EDMA_TCD2_SADDR_SADDR(x)    (x)
+
+/* Bit definitions and macros for TCD2_ATTR */
+#define MCF_EDMA_TCD2_ATTR_DSIZE(x)     (((x)&0x0007))
+#define MCF_EDMA_TCD2_ATTR_DMOD(x)      (((x)&0x001F)<<3)
+#define MCF_EDMA_TCD2_ATTR_SSIZE(x)     (((x)&0x0007)<<8)
+#define MCF_EDMA_TCD2_ATTR_SMOD(x)      (((x)&0x001F)<<11)
+
+/* Bit definitions and macros for TCD2_SOFF */
+#define MCF_EDMA_TCD2_SOFF_SOFF(x)      (x)
+
+/* Bit definitions and macros for TCD2_NBYTES */
+#define MCF_EDMA_TCD2_NBYTES_NBYTES(x)      (x)
+
+/* Bit definitions and macros for TCD2_SLAST */
+#define MCF_EDMA_TCD2_SLAST_SLAST(x)    (x)
+
+/* Bit definitions and macros for TCD2_DADDR */
+#define MCF_EDMA_TCD2_DADDR_DADDR(x)    (x)
+
+/* Bit definitions and macros for TCD2_CITER */
+#define MCF_EDMA_TCD2_CITER_CITER(x)    (((x)&0x7FFF))
+#define MCF_EDMA_TCD2_CITER_E_LINK      (0x8000)
+
+/* Bit definitions and macros for TCD2_CITER_ELINK */
+#define MCF_EDMA_TCD2_CITER_ELINK_CITER(x)      (((x)&0x01FF))
+#define MCF_EDMA_TCD2_CITER_ELINK_LINKCH(x)     (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD2_CITER_ELINK_E_LINK        (0x8000)
+
+/* Bit definitions and macros for TCD2_DOFF */
+#define MCF_EDMA_TCD2_DOFF_DOFF(x)      (x)
+
+/* Bit definitions and macros for TCD2_DLAST_SGA */
+#define MCF_EDMA_TCD2_DLAST_SGA_DLAST_SGA(x)    (x)
+
+/* Bit definitions and macros for TCD2_BITER_ELINK */
+#define MCF_EDMA_TCD2_BITER_ELINK_BITER(x)      (((x)&0x01FF))
+#define MCF_EDMA_TCD2_BITER_ELINK_LINKCH(x)     (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD2_BITER_ELINK_E_LINK        (0x8000)
+
+/* Bit definitions and macros for TCD2_BITER */
+#define MCF_EDMA_TCD2_BITER_BITER(x)    (((x)&0x7FFF))
+#define MCF_EDMA_TCD2_BITER_E_LINK      (0x8000)
+
+/* Bit definitions and macros for TCD2_CSR */
+#define MCF_EDMA_TCD2_CSR_START         (0x0001)
+#define MCF_EDMA_TCD2_CSR_INT_MAJOR     (0x0002)
+#define MCF_EDMA_TCD2_CSR_INT_HALF      (0x0004)
+#define MCF_EDMA_TCD2_CSR_D_REQ         (0x0008)
+#define MCF_EDMA_TCD2_CSR_E_SG          (0x0010)
+#define MCF_EDMA_TCD2_CSR_E_LINK        (0x0020)
+#define MCF_EDMA_TCD2_CSR_ACTIVE        (0x0040)
+#define MCF_EDMA_TCD2_CSR_DONE          (0x0080)
+#define MCF_EDMA_TCD2_CSR_LINKCH(x)     (((x)&0x003F)<<8)
+#define MCF_EDMA_TCD2_CSR_BWC(x)        (((x)&0x0003)<<14)
+
+/* Bit definitions and macros for TCD3_SADDR */
+#define MCF_EDMA_TCD3_SADDR_SADDR(x)    (x)
+
+/* Bit definitions and macros for TCD3_ATTR */
+#define MCF_EDMA_TCD3_ATTR_DSIZE(x)     (((x)&0x0007))
+#define MCF_EDMA_TCD3_ATTR_DMOD(x)      (((x)&0x001F)<<3)
+#define MCF_EDMA_TCD3_ATTR_SSIZE(x)     (((x)&0x0007)<<8)
+#define MCF_EDMA_TCD3_ATTR_SMOD(x)      (((x)&0x001F)<<11)
+
+/* Bit definitions and macros for TCD3_SOFF */
+#define MCF_EDMA_TCD3_SOFF_SOFF(x)      (x)
+
+/* Bit definitions and macros for TCD3_NBYTES */
+#define MCF_EDMA_TCD3_NBYTES_NBYTES(x)      (x)
+
+/* Bit definitions and macros for TCD3_SLAST */
+#define MCF_EDMA_TCD3_SLAST_SLAST(x)    (x)
+
+/* Bit definitions and macros for TCD3_DADDR */
+#define MCF_EDMA_TCD3_DADDR_DADDR(x)    (x)
+
+/* Bit definitions and macros for TCD3_CITER */
+#define MCF_EDMA_TCD3_CITER_CITER(x)    (((x)&0x7FFF))
+#define MCF_EDMA_TCD3_CITER_E_LINK      (0x8000)
+
+/* Bit definitions and macros for TCD3_CITER_ELINK */
+#define MCF_EDMA_TCD3_CITER_ELINK_CITER(x)      (((x)&0x01FF))
+#define MCF_EDMA_TCD3_CITER_ELINK_LINKCH(x)     (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD3_CITER_ELINK_E_LINK        (0x8000)
+
+/* Bit definitions and macros for TCD3_DOFF */
+#define MCF_EDMA_TCD3_DOFF_DOFF(x)      (x)
+
+/* Bit definitions and macros for TCD3_DLAST_SGA */
+#define MCF_EDMA_TCD3_DLAST_SGA_DLAST_SGA(x)    (x)
+
+/* Bit definitions and macros for TCD3_BITER_ELINK */
+#define MCF_EDMA_TCD3_BITER_ELINK_BITER(x)      (((x)&0x01FF))
+#define MCF_EDMA_TCD3_BITER_ELINK_LINKCH(x)     (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD3_BITER_ELINK_E_LINK        (0x8000)
+
+/* Bit definitions and macros for TCD3_BITER */
+#define MCF_EDMA_TCD3_BITER_BITER(x)    (((x)&0x7FFF))
+#define MCF_EDMA_TCD3_BITER_E_LINK      (0x8000)
+
+/* Bit definitions and macros for TCD3_CSR */
+#define MCF_EDMA_TCD3_CSR_START         (0x0001)
+#define MCF_EDMA_TCD3_CSR_INT_MAJOR     (0x0002)
+#define MCF_EDMA_TCD3_CSR_INT_HALF      (0x0004)
+#define MCF_EDMA_TCD3_CSR_D_REQ         (0x0008)
+#define MCF_EDMA_TCD3_CSR_E_SG          (0x0010)
+#define MCF_EDMA_TCD3_CSR_E_LINK        (0x0020)
+#define MCF_EDMA_TCD3_CSR_ACTIVE        (0x0040)
+#define MCF_EDMA_TCD3_CSR_DONE          (0x0080)
+#define MCF_EDMA_TCD3_CSR_LINKCH(x)     (((x)&0x003F)<<8)
+#define MCF_EDMA_TCD3_CSR_BWC(x)        (((x)&0x0003)<<14)
+
+/* Bit definitions and macros for TCD4_SADDR */
+#define MCF_EDMA_TCD4_SADDR_SADDR(x)    (x)
+
+/* Bit definitions and macros for TCD4_ATTR */
+#define MCF_EDMA_TCD4_ATTR_DSIZE(x)     (((x)&0x0007))
+#define MCF_EDMA_TCD4_ATTR_DMOD(x)      (((x)&0x001F)<<3)
+#define MCF_EDMA_TCD4_ATTR_SSIZE(x)     (((x)&0x0007)<<8)
+#define MCF_EDMA_TCD4_ATTR_SMOD(x)      (((x)&0x001F)<<11)
+
+/* Bit definitions and macros for TCD4_SOFF */
+#define MCF_EDMA_TCD4_SOFF_SOFF(x)      (x)
+
+/* Bit definitions and macros for TCD4_NBYTES */
+#define MCF_EDMA_TCD4_NBYTES_NBYTES(x)      (x)
+
+/* Bit definitions and macros for TCD4_SLAST */
+#define MCF_EDMA_TCD4_SLAST_SLAST(x)    (x)
+
+/* Bit definitions and macros for TCD4_DADDR */
+#define MCF_EDMA_TCD4_DADDR_DADDR(x)    (x)
+
+/* Bit definitions and macros for TCD4_CITER */
+#define MCF_EDMA_TCD4_CITER_CITER(x)    (((x)&0x7FFF))
+#define MCF_EDMA_TCD4_CITER_E_LINK      (0x8000)
+
+/* Bit definitions and macros for TCD4_CITER_ELINK */
+#define MCF_EDMA_TCD4_CITER_ELINK_CITER(x)      (((x)&0x01FF))
+#define MCF_EDMA_TCD4_CITER_ELINK_LINKCH(x)     (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD4_CITER_ELINK_E_LINK        (0x8000)
+
+/* Bit definitions and macros for TCD4_DOFF */
+#define MCF_EDMA_TCD4_DOFF_DOFF(x)      (x)
+
+/* Bit definitions and macros for TCD4_DLAST_SGA */
+#define MCF_EDMA_TCD4_DLAST_SGA_DLAST_SGA(x)    (x)
+
+/* Bit definitions and macros for TCD4_BITER */
+#define MCF_EDMA_TCD4_BITER_BITER(x)    (((x)&0x7FFF))
+#define MCF_EDMA_TCD4_BITER_E_LINK      (0x8000)
+
+/* Bit definitions and macros for TCD4_BITER_ELINK */
+#define MCF_EDMA_TCD4_BITER_ELINK_BITER(x)      (((x)&0x01FF))
+#define MCF_EDMA_TCD4_BITER_ELINK_LINKCH(x)     (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD4_BITER_ELINK_E_LINK        (0x8000)
+
+/* Bit definitions and macros for TCD4_CSR */
+#define MCF_EDMA_TCD4_CSR_START         (0x0001)
+#define MCF_EDMA_TCD4_CSR_INT_MAJOR     (0x0002)
+#define MCF_EDMA_TCD4_CSR_INT_HALF      (0x0004)
+#define MCF_EDMA_TCD4_CSR_D_REQ         (0x0008)
+#define MCF_EDMA_TCD4_CSR_E_SG          (0x0010)
+#define MCF_EDMA_TCD4_CSR_E_LINK        (0x0020)
+#define MCF_EDMA_TCD4_CSR_ACTIVE        (0x0040)
+#define MCF_EDMA_TCD4_CSR_DONE          (0x0080)
+#define MCF_EDMA_TCD4_CSR_LINKCH(x)     (((x)&0x003F)<<8)
+#define MCF_EDMA_TCD4_CSR_BWC(x)        (((x)&0x0003)<<14)
+
+/* Bit definitions and macros for TCD5_SADDR */
+#define MCF_EDMA_TCD5_SADDR_SADDR(x)    (x)
+
+/* Bit definitions and macros for TCD5_ATTR */
+#define MCF_EDMA_TCD5_ATTR_DSIZE(x)     (((x)&0x0007))
+#define MCF_EDMA_TCD5_ATTR_DMOD(x)      (((x)&0x001F)<<3)
+#define MCF_EDMA_TCD5_ATTR_SSIZE(x)     (((x)&0x0007)<<8)
+#define MCF_EDMA_TCD5_ATTR_SMOD(x)      (((x)&0x001F)<<11)
+
+/* Bit definitions and macros for TCD5_SOFF */
+#define MCF_EDMA_TCD5_SOFF_SOFF(x)      (x)
+
+/* Bit definitions and macros for TCD5_NBYTES */
+#define MCF_EDMA_TCD5_NBYTES_NBYTES(x)      (x)
+
+/* Bit definitions and macros for TCD5_SLAST */
+#define MCF_EDMA_TCD5_SLAST_SLAST(x)    (x)
+
+/* Bit definitions and macros for TCD5_DADDR */
+#define MCF_EDMA_TCD5_DADDR_DADDR(x)    (x)
+
+/* Bit definitions and macros for TCD5_CITER */
+#define MCF_EDMA_TCD5_CITER_CITER(x)    (((x)&0x7FFF))
+#define MCF_EDMA_TCD5_CITER_E_LINK      (0x8000)
+
+/* Bit definitions and macros for TCD5_CITER_ELINK */
+#define MCF_EDMA_TCD5_CITER_ELINK_CITER(x)      (((x)&0x01FF))
+#define MCF_EDMA_TCD5_CITER_ELINK_LINKCH(x)     (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD5_CITER_ELINK_E_LINK        (0x8000)
+
+/* Bit definitions and macros for TCD5_DOFF */
+#define MCF_EDMA_TCD5_DOFF_DOFF(x)      (x)
+
+/* Bit definitions and macros for TCD5_DLAST_SGA */
+#define MCF_EDMA_TCD5_DLAST_SGA_DLAST_SGA(x)    (x)
+
+/* Bit definitions and macros for TCD5_BITER_ELINK */
+#define MCF_EDMA_TCD5_BITER_ELINK_BITER(x)      (((x)&0x01FF))
+#define MCF_EDMA_TCD5_BITER_ELINK_LINKCH(x)     (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD5_BITER_ELINK_E_LINK        (0x8000)
+
+/* Bit definitions and macros for TCD5_BITER */
+#define MCF_EDMA_TCD5_BITER_BITER(x)    (((x)&0x7FFF))
+#define MCF_EDMA_TCD5_BITER_E_LINK      (0x8000)
+
+/* Bit definitions and macros for TCD5_CSR */
+#define MCF_EDMA_TCD5_CSR_START         (0x0001)
+#define MCF_EDMA_TCD5_CSR_INT_MAJOR     (0x0002)
+#define MCF_EDMA_TCD5_CSR_INT_HALF      (0x0004)
+#define MCF_EDMA_TCD5_CSR_D_REQ         (0x0008)
+#define MCF_EDMA_TCD5_CSR_E_SG          (0x0010)
+#define MCF_EDMA_TCD5_CSR_E_LINK        (0x0020)
+#define MCF_EDMA_TCD5_CSR_ACTIVE        (0x0040)
+#define MCF_EDMA_TCD5_CSR_DONE          (0x0080)
+#define MCF_EDMA_TCD5_CSR_LINKCH(x)     (((x)&0x003F)<<8)
+#define MCF_EDMA_TCD5_CSR_BWC(x)        (((x)&0x0003)<<14)
+
+/* Bit definitions and macros for TCD6_SADDR */
+#define MCF_EDMA_TCD6_SADDR_SADDR(x)    (x)
+
+/* Bit definitions and macros for TCD6_ATTR */
+#define MCF_EDMA_TCD6_ATTR_DSIZE(x)     (((x)&0x0007))
+#define MCF_EDMA_TCD6_ATTR_DMOD(x)      (((x)&0x001F)<<3)
+#define MCF_EDMA_TCD6_ATTR_SSIZE(x)     (((x)&0x0007)<<8)
+#define MCF_EDMA_TCD6_ATTR_SMOD(x)      (((x)&0x001F)<<11)
+
+/* Bit definitions and macros for TCD6_SOFF */
+#define MCF_EDMA_TCD6_SOFF_SOFF(x)      (x)
+
+/* Bit definitions and macros for TCD6_NBYTES */
+#define MCF_EDMA_TCD6_NBYTES_NBYTES(x)      (x)
+
+/* Bit definitions and macros for TCD6_SLAST */
+#define MCF_EDMA_TCD6_SLAST_SLAST(x)    (x)
+
+/* Bit definitions and macros for TCD6_DADDR */
+#define MCF_EDMA_TCD6_DADDR_DADDR(x)    (x)
+
+/* Bit definitions and macros for TCD6_CITER */
+#define MCF_EDMA_TCD6_CITER_CITER(x)    (((x)&0x7FFF))
+#define MCF_EDMA_TCD6_CITER_E_LINK      (0x8000)
+
+/* Bit definitions and macros for TCD6_CITER_ELINK */
+#define MCF_EDMA_TCD6_CITER_ELINK_CITER(x)      (((x)&0x01FF))
+#define MCF_EDMA_TCD6_CITER_ELINK_LINKCH(x)     (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD6_CITER_ELINK_E_LINK        (0x8000)
+
+/* Bit definitions and macros for TCD6_DOFF */
+#define MCF_EDMA_TCD6_DOFF_DOFF(x)      (x)
+
+/* Bit definitions and macros for TCD6_DLAST_SGA */
+#define MCF_EDMA_TCD6_DLAST_SGA_DLAST_SGA(x)    (x)
+
+/* Bit definitions and macros for TCD6_BITER_ELINK */
+#define MCF_EDMA_TCD6_BITER_ELINK_BITER(x)      (((x)&0x01FF))
+#define MCF_EDMA_TCD6_BITER_ELINK_LINKCH(x)     (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD6_BITER_ELINK_E_LINK        (0x8000)
+
+/* Bit definitions and macros for TCD6_BITER */
+#define MCF_EDMA_TCD6_BITER_BITER(x)    (((x)&0x7FFF))
+#define MCF_EDMA_TCD6_BITER_E_LINK      (0x8000)
+
+/* Bit definitions and macros for TCD6_CSR */
+#define MCF_EDMA_TCD6_CSR_START         (0x0001)
+#define MCF_EDMA_TCD6_CSR_INT_MAJOR     (0x0002)
+#define MCF_EDMA_TCD6_CSR_INT_HALF      (0x0004)
+#define MCF_EDMA_TCD6_CSR_D_REQ         (0x0008)
+#define MCF_EDMA_TCD6_CSR_E_SG          (0x0010)
+#define MCF_EDMA_TCD6_CSR_E_LINK        (0x0020)
+#define MCF_EDMA_TCD6_CSR_ACTIVE        (0x0040)
+#define MCF_EDMA_TCD6_CSR_DONE          (0x0080)
+#define MCF_EDMA_TCD6_CSR_LINKCH(x)     (((x)&0x003F)<<8)
+#define MCF_EDMA_TCD6_CSR_BWC(x)        (((x)&0x0003)<<14)
+
+/* Bit definitions and macros for TCD7_SADDR */
+#define MCF_EDMA_TCD7_SADDR_SADDR(x)    (x)
+
+/* Bit definitions and macros for TCD7_ATTR */
+#define MCF_EDMA_TCD7_ATTR_DSIZE(x)     (((x)&0x0007))
+#define MCF_EDMA_TCD7_ATTR_DMOD(x)      (((x)&0x001F)<<3)
+#define MCF_EDMA_TCD7_ATTR_SSIZE(x)     (((x)&0x0007)<<8)
+#define MCF_EDMA_TCD7_ATTR_SMOD(x)      (((x)&0x001F)<<11)
+
+/* Bit definitions and macros for TCD7_SOFF */
+#define MCF_EDMA_TCD7_SOFF_SOFF(x)      (x)
+
+/* Bit definitions and macros for TCD7_NBYTES */
+#define MCF_EDMA_TCD7_NBYTES_NBYTES(x)      (x)
+
+/* Bit definitions and macros for TCD7_SLAST */
+#define MCF_EDMA_TCD7_SLAST_SLAST(x)    (x)
+
+/* Bit definitions and macros for TCD7_DADDR */
+#define MCF_EDMA_TCD7_DADDR_DADDR(x)    (x)
+
+/* Bit definitions and macros for TCD7_CITER */
+#define MCF_EDMA_TCD7_CITER_CITER(x)    (((x)&0x7FFF))
+#define MCF_EDMA_TCD7_CITER_E_LINK      (0x8000)
+
+/* Bit definitions and macros for TCD7_CITER_ELINK */
+#define MCF_EDMA_TCD7_CITER_ELINK_CITER(x)      (((x)&0x01FF))
+#define MCF_EDMA_TCD7_CITER_ELINK_LINKCH(x)     (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD7_CITER_ELINK_E_LINK        (0x8000)
+
+/* Bit definitions and macros for TCD7_DOFF */
+#define MCF_EDMA_TCD7_DOFF_DOFF(x)      (x)
+
+/* Bit definitions and macros for TCD7_DLAST_SGA */
+#define MCF_EDMA_TCD7_DLAST_SGA_DLAST_SGA(x)    (x)
+
+/* Bit definitions and macros for TCD7_BITER_ELINK */
+#define MCF_EDMA_TCD7_BITER_ELINK_BITER(x)      (((x)&0x01FF))
+#define MCF_EDMA_TCD7_BITER_ELINK_LINKCH(x)     (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD7_BITER_ELINK_E_LINK        (0x8000)
+
+/* Bit definitions and macros for TCD7_BITER */
+#define MCF_EDMA_TCD7_BITER_BITER(x)    (((x)&0x7FFF))
+#define MCF_EDMA_TCD7_BITER_E_LINK      (0x8000)
+
+/* Bit definitions and macros for TCD7_CSR */
+#define MCF_EDMA_TCD7_CSR_START         (0x0001)
+#define MCF_EDMA_TCD7_CSR_INT_MAJOR     (0x0002)
+#define MCF_EDMA_TCD7_CSR_INT_HALF      (0x0004)
+#define MCF_EDMA_TCD7_CSR_D_REQ         (0x0008)
+#define MCF_EDMA_TCD7_CSR_E_SG          (0x0010)
+#define MCF_EDMA_TCD7_CSR_E_LINK        (0x0020)
+#define MCF_EDMA_TCD7_CSR_ACTIVE        (0x0040)
+#define MCF_EDMA_TCD7_CSR_DONE          (0x0080)
+#define MCF_EDMA_TCD7_CSR_LINKCH(x)     (((x)&0x003F)<<8)
+#define MCF_EDMA_TCD7_CSR_BWC(x)        (((x)&0x0003)<<14)
+
+/* Bit definitions and macros for TCD8_SADDR */
+#define MCF_EDMA_TCD8_SADDR_SADDR(x)    (x)
+
+/* Bit definitions and macros for TCD8_ATTR */
+#define MCF_EDMA_TCD8_ATTR_DSIZE(x)     (((x)&0x0007))
+#define MCF_EDMA_TCD8_ATTR_DMOD(x)      (((x)&0x001F)<<3)
+#define MCF_EDMA_TCD8_ATTR_SSIZE(x)     (((x)&0x0007)<<8)
+#define MCF_EDMA_TCD8_ATTR_SMOD(x)      (((x)&0x001F)<<11)
+
+/* Bit definitions and macros for TCD8_SOFF */
+#define MCF_EDMA_TCD8_SOFF_SOFF(x)      (x)
+
+/* Bit definitions and macros for TCD8_NBYTES */
+#define MCF_EDMA_TCD8_NBYTES_NBYTES(x)      (x)
+
+/* Bit definitions and macros for TCD8_SLAST */
+#define MCF_EDMA_TCD8_SLAST_SLAST(x)    (x)
+
+/* Bit definitions and macros for TCD8_DADDR */
+#define MCF_EDMA_TCD8_DADDR_DADDR(x)    (x)
+
+/* Bit definitions and macros for TCD8_CITER */
+#define MCF_EDMA_TCD8_CITER_CITER(x)    (((x)&0x7FFF))
+#define MCF_EDMA_TCD8_CITER_E_LINK      (0x8000)
+
+/* Bit definitions and macros for TCD8_CITER_ELINK */
+#define MCF_EDMA_TCD8_CITER_ELINK_CITER(x)      (((x)&0x01FF))
+#define MCF_EDMA_TCD8_CITER_ELINK_LINKCH(x)     (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD8_CITER_ELINK_E_LINK        (0x8000)
+
+/* Bit definitions and macros for TCD8_DOFF */
+#define MCF_EDMA_TCD8_DOFF_DOFF(x)      (x)
+
+/* Bit definitions and macros for TCD8_DLAST_SGA */
+#define MCF_EDMA_TCD8_DLAST_SGA_DLAST_SGA(x)    (x)
+
+/* Bit definitions and macros for TCD8_BITER_ELINK */
+#define MCF_EDMA_TCD8_BITER_ELINK_BITER(x)      (((x)&0x01FF))
+#define MCF_EDMA_TCD8_BITER_ELINK_LINKCH(x)     (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD8_BITER_ELINK_E_LINK        (0x8000)
+
+/* Bit definitions and macros for TCD8_BITER */
+#define MCF_EDMA_TCD8_BITER_BITER(x)    (((x)&0x7FFF))
+#define MCF_EDMA_TCD8_BITER_E_LINK      (0x8000)
+
+/* Bit definitions and macros for TCD8_CSR */
+#define MCF_EDMA_TCD8_CSR_START         (0x0001)
+#define MCF_EDMA_TCD8_CSR_INT_MAJOR     (0x0002)
+#define MCF_EDMA_TCD8_CSR_INT_HALF      (0x0004)
+#define MCF_EDMA_TCD8_CSR_D_REQ         (0x0008)
+#define MCF_EDMA_TCD8_CSR_E_SG          (0x0010)
+#define MCF_EDMA_TCD8_CSR_E_LINK        (0x0020)
+#define MCF_EDMA_TCD8_CSR_ACTIVE        (0x0040)
+#define MCF_EDMA_TCD8_CSR_DONE          (0x0080)
+#define MCF_EDMA_TCD8_CSR_LINKCH(x)     (((x)&0x003F)<<8)
+#define MCF_EDMA_TCD8_CSR_BWC(x)        (((x)&0x0003)<<14)
+
+/* Bit definitions and macros for TCD9_SADDR */
+#define MCF_EDMA_TCD9_SADDR_SADDR(x)    (x)
+
+/* Bit definitions and macros for TCD9_ATTR */
+#define MCF_EDMA_TCD9_ATTR_DSIZE(x)     (((x)&0x0007))
+#define MCF_EDMA_TCD9_ATTR_DMOD(x)      (((x)&0x001F)<<3)
+#define MCF_EDMA_TCD9_ATTR_SSIZE(x)     (((x)&0x0007)<<8)
+#define MCF_EDMA_TCD9_ATTR_SMOD(x)      (((x)&0x001F)<<11)
+
+/* Bit definitions and macros for TCD9_SOFF */
+#define MCF_EDMA_TCD9_SOFF_SOFF(x)      (x)
+
+/* Bit definitions and macros for TCD9_NBYTES */
+#define MCF_EDMA_TCD9_NBYTES_NBYTES(x)      (x)
+
+/* Bit definitions and macros for TCD9_SLAST */
+#define MCF_EDMA_TCD9_SLAST_SLAST(x)    (x)
+
+/* Bit definitions and macros for TCD9_DADDR */
+#define MCF_EDMA_TCD9_DADDR_DADDR(x)    (x)
+
+/* Bit definitions and macros for TCD9_CITER_ELINK */
+#define MCF_EDMA_TCD9_CITER_ELINK_CITER(x)      (((x)&0x01FF))
+#define MCF_EDMA_TCD9_CITER_ELINK_LINKCH(x)     (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD9_CITER_ELINK_E_LINK        (0x8000)
+
+/* Bit definitions and macros for TCD9_CITER */
+#define MCF_EDMA_TCD9_CITER_CITER(x)    (((x)&0x7FFF))
+#define MCF_EDMA_TCD9_CITER_E_LINK      (0x8000)
+
+/* Bit definitions and macros for TCD9_DOFF */
+#define MCF_EDMA_TCD9_DOFF_DOFF(x)      (x)
+
+/* Bit definitions and macros for TCD9_DLAST_SGA */
+#define MCF_EDMA_TCD9_DLAST_SGA_DLAST_SGA(x)    (x)
+
+/* Bit definitions and macros for TCD9_BITER_ELINK */
+#define MCF_EDMA_TCD9_BITER_ELINK_BITER(x)      (((x)&0x01FF))
+#define MCF_EDMA_TCD9_BITER_ELINK_LINKCH(x)     (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD9_BITER_ELINK_E_LINK        (0x8000)
+
+/* Bit definitions and macros for TCD9_BITER */
+#define MCF_EDMA_TCD9_BITER_BITER(x)    (((x)&0x7FFF))
+#define MCF_EDMA_TCD9_BITER_E_LINK      (0x8000)
+
+/* Bit definitions and macros for TCD9_CSR */
+#define MCF_EDMA_TCD9_CSR_START         (0x0001)
+#define MCF_EDMA_TCD9_CSR_INT_MAJOR     (0x0002)
+#define MCF_EDMA_TCD9_CSR_INT_HALF      (0x0004)
+#define MCF_EDMA_TCD9_CSR_D_REQ         (0x0008)
+#define MCF_EDMA_TCD9_CSR_E_SG          (0x0010)
+#define MCF_EDMA_TCD9_CSR_E_LINK        (0x0020)
+#define MCF_EDMA_TCD9_CSR_ACTIVE        (0x0040)
+#define MCF_EDMA_TCD9_CSR_DONE          (0x0080)
+#define MCF_EDMA_TCD9_CSR_LINKCH(x)     (((x)&0x003F)<<8)
+#define MCF_EDMA_TCD9_CSR_BWC(x)        (((x)&0x0003)<<14)
+
+/* Bit definitions and macros for TCD10_SADDR */
+#define MCF_EDMA_TCD10_SADDR_SADDR(x)   (x)
+
+/* Bit definitions and macros for TCD10_ATTR */
+#define MCF_EDMA_TCD10_ATTR_DSIZE(x)    (((x)&0x0007))
+#define MCF_EDMA_TCD10_ATTR_DMOD(x)     (((x)&0x001F)<<3)
+#define MCF_EDMA_TCD10_ATTR_SSIZE(x)    (((x)&0x0007)<<8)
+#define MCF_EDMA_TCD10_ATTR_SMOD(x)     (((x)&0x001F)<<11)
+
+/* Bit definitions and macros for TCD10_SOFF */
+#define MCF_EDMA_TCD10_SOFF_SOFF(x)     (x)
+
+/* Bit definitions and macros for TCD10_NBYTES */
+#define MCF_EDMA_TCD10_NBYTES_NBYTES(x)     (x)
+
+/* Bit definitions and macros for TCD10_SLAST */
+#define MCF_EDMA_TCD10_SLAST_SLAST(x)   (x)
+
+/* Bit definitions and macros for TCD10_DADDR */
+#define MCF_EDMA_TCD10_DADDR_DADDR(x)   (x)
+
+/* Bit definitions and macros for TCD10_CITER_ELINK */
+#define MCF_EDMA_TCD10_CITER_ELINK_CITER(x)     (((x)&0x01FF))
+#define MCF_EDMA_TCD10_CITER_ELINK_LINKCH(x)    (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD10_CITER_ELINK_E_LINK       (0x8000)
+
+/* Bit definitions and macros for TCD10_CITER */
+#define MCF_EDMA_TCD10_CITER_CITER(x)   (((x)&0x7FFF))
+#define MCF_EDMA_TCD10_CITER_E_LINK     (0x8000)
+
+/* Bit definitions and macros for TCD10_DOFF */
+#define MCF_EDMA_TCD10_DOFF_DOFF(x)     (x)
+
+/* Bit definitions and macros for TCD10_DLAST_SGA */
+#define MCF_EDMA_TCD10_DLAST_SGA_DLAST_SGA(x)   (x)
+
+/* Bit definitions and macros for TCD10_BITER */
+#define MCF_EDMA_TCD10_BITER_BITER(x)   (((x)&0x7FFF))
+#define MCF_EDMA_TCD10_BITER_E_LINK     (0x8000)
+
+/* Bit definitions and macros for TCD10_BITER_ELINK */
+#define MCF_EDMA_TCD10_BITER_ELINK_BITER(x)     (((x)&0x01FF))
+#define MCF_EDMA_TCD10_BITER_ELINK_LINKCH(x)    (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD10_BITER_ELINK_E_LINK       (0x8000)
+
+/* Bit definitions and macros for TCD10_CSR */
+#define MCF_EDMA_TCD10_CSR_START        (0x0001)
+#define MCF_EDMA_TCD10_CSR_INT_MAJOR    (0x0002)
+#define MCF_EDMA_TCD10_CSR_INT_HALF     (0x0004)
+#define MCF_EDMA_TCD10_CSR_D_REQ        (0x0008)
+#define MCF_EDMA_TCD10_CSR_E_SG         (0x0010)
+#define MCF_EDMA_TCD10_CSR_E_LINK       (0x0020)
+#define MCF_EDMA_TCD10_CSR_ACTIVE       (0x0040)
+#define MCF_EDMA_TCD10_CSR_DONE         (0x0080)
+#define MCF_EDMA_TCD10_CSR_LINKCH(x)    (((x)&0x003F)<<8)
+#define MCF_EDMA_TCD10_CSR_BWC(x)       (((x)&0x0003)<<14)
+
+/* Bit definitions and macros for TCD11_SADDR */
+#define MCF_EDMA_TCD11_SADDR_SADDR(x)   (x)
+
+/* Bit definitions and macros for TCD11_ATTR */
+#define MCF_EDMA_TCD11_ATTR_DSIZE(x)    (((x)&0x0007))
+#define MCF_EDMA_TCD11_ATTR_DMOD(x)     (((x)&0x001F)<<3)
+#define MCF_EDMA_TCD11_ATTR_SSIZE(x)    (((x)&0x0007)<<8)
+#define MCF_EDMA_TCD11_ATTR_SMOD(x)     (((x)&0x001F)<<11)
+
+/* Bit definitions and macros for TCD11_SOFF */
+#define MCF_EDMA_TCD11_SOFF_SOFF(x)     (x)
+
+/* Bit definitions and macros for TCD11_NBYTES */
+#define MCF_EDMA_TCD11_NBYTES_NBYTES(x)     (x)
+
+/* Bit definitions and macros for TCD11_SLAST */
+#define MCF_EDMA_TCD11_SLAST_SLAST(x)   (x)
+
+/* Bit definitions and macros for TCD11_DADDR */
+#define MCF_EDMA_TCD11_DADDR_DADDR(x)   (x)
+
+/* Bit definitions and macros for TCD11_CITER */
+#define MCF_EDMA_TCD11_CITER_CITER(x)   (((x)&0x7FFF))
+#define MCF_EDMA_TCD11_CITER_E_LINK     (0x8000)
+
+/* Bit definitions and macros for TCD11_CITER_ELINK */
+#define MCF_EDMA_TCD11_CITER_ELINK_CITER(x)     (((x)&0x01FF))
+#define MCF_EDMA_TCD11_CITER_ELINK_LINKCH(x)    (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD11_CITER_ELINK_E_LINK       (0x8000)
+
+/* Bit definitions and macros for TCD11_DOFF */
+#define MCF_EDMA_TCD11_DOFF_DOFF(x)     (x)
+
+/* Bit definitions and macros for TCD11_DLAST_SGA */
+#define MCF_EDMA_TCD11_DLAST_SGA_DLAST_SGA(x)   (x)
+
+/* Bit definitions and macros for TCD11_BITER */
+#define MCF_EDMA_TCD11_BITER_BITER(x)   (((x)&0x7FFF))
+#define MCF_EDMA_TCD11_BITER_E_LINK     (0x8000)
+
+/* Bit definitions and macros for TCD11_BITER_ELINK */
+#define MCF_EDMA_TCD11_BITER_ELINK_BITER(x)     (((x)&0x01FF))
+#define MCF_EDMA_TCD11_BITER_ELINK_LINKCH(x)    (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD11_BITER_ELINK_E_LINK       (0x8000)
+
+/* Bit definitions and macros for TCD11_CSR */
+#define MCF_EDMA_TCD11_CSR_START        (0x0001)
+#define MCF_EDMA_TCD11_CSR_INT_MAJOR    (0x0002)
+#define MCF_EDMA_TCD11_CSR_INT_HALF     (0x0004)
+#define MCF_EDMA_TCD11_CSR_D_REQ        (0x0008)
+#define MCF_EDMA_TCD11_CSR_E_SG         (0x0010)
+#define MCF_EDMA_TCD11_CSR_E_LINK       (0x0020)
+#define MCF_EDMA_TCD11_CSR_ACTIVE       (0x0040)
+#define MCF_EDMA_TCD11_CSR_DONE         (0x0080)
+#define MCF_EDMA_TCD11_CSR_LINKCH(x)    (((x)&0x003F)<<8)
+#define MCF_EDMA_TCD11_CSR_BWC(x)       (((x)&0x0003)<<14)
+
+/* Bit definitions and macros for TCD12_SADDR */
+#define MCF_EDMA_TCD12_SADDR_SADDR(x)   (x)
+
+/* Bit definitions and macros for TCD12_ATTR */
+#define MCF_EDMA_TCD12_ATTR_DSIZE(x)    (((x)&0x0007))
+#define MCF_EDMA_TCD12_ATTR_DMOD(x)     (((x)&0x001F)<<3)
+#define MCF_EDMA_TCD12_ATTR_SSIZE(x)    (((x)&0x0007)<<8)
+#define MCF_EDMA_TCD12_ATTR_SMOD(x)     (((x)&0x001F)<<11)
+
+/* Bit definitions and macros for TCD12_SOFF */
+#define MCF_EDMA_TCD12_SOFF_SOFF(x)     (x)
+
+/* Bit definitions and macros for TCD12_NBYTES */
+#define MCF_EDMA_TCD12_NBYTES_NBYTES(x)     (x)
+
+/* Bit definitions and macros for TCD12_SLAST */
+#define MCF_EDMA_TCD12_SLAST_SLAST(x)   (x)
+
+/* Bit definitions and macros for TCD12_DADDR */
+#define MCF_EDMA_TCD12_DADDR_DADDR(x)   (x)
+
+/* Bit definitions and macros for TCD12_CITER */
+#define MCF_EDMA_TCD12_CITER_CITER(x)   (((x)&0x7FFF))
+#define MCF_EDMA_TCD12_CITER_E_LINK     (0x8000)
+
+/* Bit definitions and macros for TCD12_CITER_ELINK */
+#define MCF_EDMA_TCD12_CITER_ELINK_CITER(x)     (((x)&0x01FF))
+#define MCF_EDMA_TCD12_CITER_ELINK_LINKCH(x)    (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD12_CITER_ELINK_E_LINK       (0x8000)
+
+/* Bit definitions and macros for TCD12_DOFF */
+#define MCF_EDMA_TCD12_DOFF_DOFF(x)     (x)
+
+/* Bit definitions and macros for TCD12_DLAST_SGA */
+#define MCF_EDMA_TCD12_DLAST_SGA_DLAST_SGA(x)   (x)
+
+/* Bit definitions and macros for TCD12_BITER */
+#define MCF_EDMA_TCD12_BITER_BITER(x)   (((x)&0x7FFF))
+#define MCF_EDMA_TCD12_BITER_E_LINK     (0x8000)
+
+/* Bit definitions and macros for TCD12_BITER_ELINK */
+#define MCF_EDMA_TCD12_BITER_ELINK_BITER(x)     (((x)&0x01FF))
+#define MCF_EDMA_TCD12_BITER_ELINK_LINKCH(x)    (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD12_BITER_ELINK_E_LINK       (0x8000)
+
+/* Bit definitions and macros for TCD12_CSR */
+#define MCF_EDMA_TCD12_CSR_START        (0x0001)
+#define MCF_EDMA_TCD12_CSR_INT_MAJOR    (0x0002)
+#define MCF_EDMA_TCD12_CSR_INT_HALF     (0x0004)
+#define MCF_EDMA_TCD12_CSR_D_REQ        (0x0008)
+#define MCF_EDMA_TCD12_CSR_E_SG         (0x0010)
+#define MCF_EDMA_TCD12_CSR_E_LINK       (0x0020)
+#define MCF_EDMA_TCD12_CSR_ACTIVE       (0x0040)
+#define MCF_EDMA_TCD12_CSR_DONE         (0x0080)
+#define MCF_EDMA_TCD12_CSR_LINKCH(x)    (((x)&0x003F)<<8)
+#define MCF_EDMA_TCD12_CSR_BWC(x)       (((x)&0x0003)<<14)
+
+/* Bit definitions and macros for TCD13_SADDR */
+#define MCF_EDMA_TCD13_SADDR_SADDR(x)   (x)
+
+/* Bit definitions and macros for TCD13_ATTR */
+#define MCF_EDMA_TCD13_ATTR_DSIZE(x)    (((x)&0x0007))
+#define MCF_EDMA_TCD13_ATTR_DMOD(x)     (((x)&0x001F)<<3)
+#define MCF_EDMA_TCD13_ATTR_SSIZE(x)    (((x)&0x0007)<<8)
+#define MCF_EDMA_TCD13_ATTR_SMOD(x)     (((x)&0x001F)<<11)
+
+/* Bit definitions and macros for TCD13_SOFF */
+#define MCF_EDMA_TCD13_SOFF_SOFF(x)     (x)
+
+/* Bit definitions and macros for TCD13_NBYTES */
+#define MCF_EDMA_TCD13_NBYTES_NBYTES(x)     (x)
+
+/* Bit definitions and macros for TCD13_SLAST */
+#define MCF_EDMA_TCD13_SLAST_SLAST(x)   (x)
+
+/* Bit definitions and macros for TCD13_DADDR */
+#define MCF_EDMA_TCD13_DADDR_DADDR(x)   (x)
+
+/* Bit definitions and macros for TCD13_CITER_ELINK */
+#define MCF_EDMA_TCD13_CITER_ELINK_CITER(x)     (((x)&0x01FF))
+#define MCF_EDMA_TCD13_CITER_ELINK_LINKCH(x)    (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD13_CITER_ELINK_E_LINK       (0x8000)
+
+/* Bit definitions and macros for TCD13_CITER */
+#define MCF_EDMA_TCD13_CITER_CITER(x)   (((x)&0x7FFF))
+#define MCF_EDMA_TCD13_CITER_E_LINK     (0x8000)
+
+/* Bit definitions and macros for TCD13_DOFF */
+#define MCF_EDMA_TCD13_DOFF_DOFF(x)     (x)
+
+/* Bit definitions and macros for TCD13_DLAST_SGA */
+#define MCF_EDMA_TCD13_DLAST_SGA_DLAST_SGA(x)   (x)
+
+/* Bit definitions and macros for TCD13_BITER_ELINK */
+#define MCF_EDMA_TCD13_BITER_ELINK_BITER(x)     (((x)&0x01FF))
+#define MCF_EDMA_TCD13_BITER_ELINK_LINKCH(x)    (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD13_BITER_ELINK_E_LINK       (0x8000)
+
+/* Bit definitions and macros for TCD13_BITER */
+#define MCF_EDMA_TCD13_BITER_BITER(x)   (((x)&0x7FFF))
+#define MCF_EDMA_TCD13_BITER_E_LINK     (0x8000)
+
+/* Bit definitions and macros for TCD13_CSR */
+#define MCF_EDMA_TCD13_CSR_START        (0x0001)
+#define MCF_EDMA_TCD13_CSR_INT_MAJOR    (0x0002)
+#define MCF_EDMA_TCD13_CSR_INT_HALF     (0x0004)
+#define MCF_EDMA_TCD13_CSR_D_REQ        (0x0008)
+#define MCF_EDMA_TCD13_CSR_E_SG         (0x0010)
+#define MCF_EDMA_TCD13_CSR_E_LINK       (0x0020)
+#define MCF_EDMA_TCD13_CSR_ACTIVE       (0x0040)
+#define MCF_EDMA_TCD13_CSR_DONE         (0x0080)
+#define MCF_EDMA_TCD13_CSR_LINKCH(x)    (((x)&0x003F)<<8)
+#define MCF_EDMA_TCD13_CSR_BWC(x)       (((x)&0x0003)<<14)
+
+/* Bit definitions and macros for TCD14_SADDR */
+#define MCF_EDMA_TCD14_SADDR_SADDR(x)   (x)
+
+/* Bit definitions and macros for TCD14_ATTR */
+#define MCF_EDMA_TCD14_ATTR_DSIZE(x)    (((x)&0x0007))
+#define MCF_EDMA_TCD14_ATTR_DMOD(x)     (((x)&0x001F)<<3)
+#define MCF_EDMA_TCD14_ATTR_SSIZE(x)    (((x)&0x0007)<<8)
+#define MCF_EDMA_TCD14_ATTR_SMOD(x)     (((x)&0x001F)<<11)
+
+/* Bit definitions and macros for TCD14_SOFF */
+#define MCF_EDMA_TCD14_SOFF_SOFF(x)     (x)
+
+/* Bit definitions and macros for TCD14_NBYTES */
+#define MCF_EDMA_TCD14_NBYTES_NBYTES(x)     (x)
+
+/* Bit definitions and macros for TCD14_SLAST */
+#define MCF_EDMA_TCD14_SLAST_SLAST(x)   (x)
+
+/* Bit definitions and macros for TCD14_DADDR */
+#define MCF_EDMA_TCD14_DADDR_DADDR(x)   (x)
+
+/* Bit definitions and macros for TCD14_CITER */
+#define MCF_EDMA_TCD14_CITER_CITER(x)   (((x)&0x7FFF))
+#define MCF_EDMA_TCD14_CITER_E_LINK     (0x8000)
+
+/* Bit definitions and macros for TCD14_CITER_ELINK */
+#define MCF_EDMA_TCD14_CITER_ELINK_CITER(x)     (((x)&0x01FF))
+#define MCF_EDMA_TCD14_CITER_ELINK_LINKCH(x)    (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD14_CITER_ELINK_E_LINK       (0x8000)
+
+/* Bit definitions and macros for TCD14_DOFF */
+#define MCF_EDMA_TCD14_DOFF_DOFF(x)     (x)
+
+/* Bit definitions and macros for TCD14_DLAST_SGA */
+#define MCF_EDMA_TCD14_DLAST_SGA_DLAST_SGA(x)   (x)
+
+/* Bit definitions and macros for TCD14_BITER_ELINK */
+#define MCF_EDMA_TCD14_BITER_ELINK_BITER(x)     (((x)&0x01FF))
+#define MCF_EDMA_TCD14_BITER_ELINK_LINKCH(x)    (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD14_BITER_ELINK_E_LINK       (0x8000)
+
+/* Bit definitions and macros for TCD14_BITER */
+#define MCF_EDMA_TCD14_BITER_BITER(x)   (((x)&0x7FFF))
+#define MCF_EDMA_TCD14_BITER_E_LINK     (0x8000)
+
+/* Bit definitions and macros for TCD14_CSR */
+#define MCF_EDMA_TCD14_CSR_START        (0x0001)
+#define MCF_EDMA_TCD14_CSR_INT_MAJOR    (0x0002)
+#define MCF_EDMA_TCD14_CSR_INT_HALF     (0x0004)
+#define MCF_EDMA_TCD14_CSR_D_REQ        (0x0008)
+#define MCF_EDMA_TCD14_CSR_E_SG         (0x0010)
+#define MCF_EDMA_TCD14_CSR_E_LINK       (0x0020)
+#define MCF_EDMA_TCD14_CSR_ACTIVE       (0x0040)
+#define MCF_EDMA_TCD14_CSR_DONE         (0x0080)
+#define MCF_EDMA_TCD14_CSR_LINKCH(x)    (((x)&0x003F)<<8)
+#define MCF_EDMA_TCD14_CSR_BWC(x)       (((x)&0x0003)<<14)
+
+/* Bit definitions and macros for TCD15_SADDR */
+#define MCF_EDMA_TCD15_SADDR_SADDR(x)   (x)
+
+/* Bit definitions and macros for TCD15_ATTR */
+#define MCF_EDMA_TCD15_ATTR_DSIZE(x)    (((x)&0x0007))
+#define MCF_EDMA_TCD15_ATTR_DMOD(x)     (((x)&0x001F)<<3)
+#define MCF_EDMA_TCD15_ATTR_SSIZE(x)    (((x)&0x0007)<<8)
+#define MCF_EDMA_TCD15_ATTR_SMOD(x)     (((x)&0x001F)<<11)
+
+/* Bit definitions and macros for TCD15_SOFF */
+#define MCF_EDMA_TCD15_SOFF_SOFF(x)     (x)
+
+/* Bit definitions and macros for TCD15_NBYTES */
+#define MCF_EDMA_TCD15_NBYTES_NBYTES(x)     (x)
+
+/* Bit definitions and macros for TCD15_SLAST */
+#define MCF_EDMA_TCD15_SLAST_SLAST(x)   (x)
+
+/* Bit definitions and macros for TCD15_DADDR */
+#define MCF_EDMA_TCD15_DADDR_DADDR(x)   (x)
+
+/* Bit definitions and macros for TCD15_CITER_ELINK */
+#define MCF_EDMA_TCD15_CITER_ELINK_CITER(x)     (((x)&0x01FF))
+#define MCF_EDMA_TCD15_CITER_ELINK_LINKCH(x)    (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD15_CITER_ELINK_E_LINK       (0x8000)
+
+/* Bit definitions and macros for TCD15_CITER */
+#define MCF_EDMA_TCD15_CITER_CITER(x)   (((x)&0x7FFF))
+#define MCF_EDMA_TCD15_CITER_E_LINK     (0x8000)
+
+/* Bit definitions and macros for TCD15_DOFF */
+#define MCF_EDMA_TCD15_DOFF_DOFF(x)     (x)
+
+/* Bit definitions and macros for TCD15_DLAST_SGA */
+#define MCF_EDMA_TCD15_DLAST_SGA_DLAST_SGA(x)   (x)
+
+/* Bit definitions and macros for TCD15_BITER */
+#define MCF_EDMA_TCD15_BITER_BITER(x)   (((x)&0x7FFF))
+#define MCF_EDMA_TCD15_BITER_E_LINK     (0x8000)
+
+/* Bit definitions and macros for TCD15_BITER_ELINK */
+#define MCF_EDMA_TCD15_BITER_ELINK_BITER(x)     (((x)&0x01FF))
+#define MCF_EDMA_TCD15_BITER_ELINK_LINKCH(x)    (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD15_BITER_ELINK_E_LINK       (0x8000)
+
+/* Bit definitions and macros for TCD15_CSR */
+#define MCF_EDMA_TCD15_CSR_START        (0x0001)
+#define MCF_EDMA_TCD15_CSR_INT_MAJOR    (0x0002)
+#define MCF_EDMA_TCD15_CSR_INT_HALF     (0x0004)
+#define MCF_EDMA_TCD15_CSR_D_REQ        (0x0008)
+#define MCF_EDMA_TCD15_CSR_E_SG         (0x0010)
+#define MCF_EDMA_TCD15_CSR_E_LINK       (0x0020)
+#define MCF_EDMA_TCD15_CSR_ACTIVE       (0x0040)
+#define MCF_EDMA_TCD15_CSR_DONE         (0x0080)
+#define MCF_EDMA_TCD15_CSR_LINKCH(x)    (((x)&0x003F)<<8)
+#define MCF_EDMA_TCD15_CSR_BWC(x)       (((x)&0x0003)<<14)
+
+/********************************************************************/
+
+#endif /* __MCF5445X_EDMA_H__ */
--- /dev/null
+++ b/include/asm-m68k/mcf5445x_eport.h
@@ -0,0 +1,117 @@
+/*
+ * Kurt Mahan kmahan@freescale.com
+ *
+ * Copyright Freescale Semiconductor, Inc. 2007
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MCF5445X_EPORT_H__
+#define __MCF5445X_EPORT_H__
+
+/*********************************************************************
+*
+* Edge Port Module (EPORT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_EPORT_EPPAR         MCF_REG16(0xFC094000)
+#define MCF_EPORT_EPDDR         MCF_REG08(0xFC094002)
+#define MCF_EPORT_EPIER         MCF_REG08(0xFC094003)
+#define MCF_EPORT_EPDR          MCF_REG08(0xFC094004)
+#define MCF_EPORT_EPPDR         MCF_REG08(0xFC094005)
+#define MCF_EPORT_EPFR          MCF_REG08(0xFC094006)
+
+/* Bit definitions and macros for EPPAR */
+#define MCF_EPORT_EPPAR_EPPA1(x)        (((x)&0x0003)<<2)
+#define MCF_EPORT_EPPAR_EPPA2(x)        (((x)&0x0003)<<4)
+#define MCF_EPORT_EPPAR_EPPA3(x)        (((x)&0x0003)<<6)
+#define MCF_EPORT_EPPAR_EPPA4(x)        (((x)&0x0003)<<8)
+#define MCF_EPORT_EPPAR_EPPA5(x)        (((x)&0x0003)<<10)
+#define MCF_EPORT_EPPAR_EPPA6(x)        (((x)&0x0003)<<12)
+#define MCF_EPORT_EPPAR_EPPA7(x)        (((x)&0x0003)<<14)
+#define MCF_EPORT_EPPAR_LEVEL           (0)
+#define MCF_EPORT_EPPAR_RISING          (1)
+#define MCF_EPORT_EPPAR_FALLING         (2)
+#define MCF_EPORT_EPPAR_BOTH            (3)
+#define MCF_EPORT_EPPAR_EPPA7_LEVEL     (0x0000)
+#define MCF_EPORT_EPPAR_EPPA7_RISING    (0x4000)
+#define MCF_EPORT_EPPAR_EPPA7_FALLING   (0x8000)
+#define MCF_EPORT_EPPAR_EPPA7_BOTH      (0xC000)
+#define MCF_EPORT_EPPAR_EPPA6_LEVEL     (0x0000)
+#define MCF_EPORT_EPPAR_EPPA6_RISING    (0x1000)
+#define MCF_EPORT_EPPAR_EPPA6_FALLING   (0x2000)
+#define MCF_EPORT_EPPAR_EPPA6_BOTH      (0x3000)
+#define MCF_EPORT_EPPAR_EPPA5_LEVEL     (0x0000)
+#define MCF_EPORT_EPPAR_EPPA5_RISING    (0x0400)
+#define MCF_EPORT_EPPAR_EPPA5_FALLING   (0x0800)
+#define MCF_EPORT_EPPAR_EPPA5_BOTH      (0x0C00)
+#define MCF_EPORT_EPPAR_EPPA4_LEVEL     (0x0000)
+#define MCF_EPORT_EPPAR_EPPA4_RISING    (0x0100)
+#define MCF_EPORT_EPPAR_EPPA4_FALLING   (0x0200)
+#define MCF_EPORT_EPPAR_EPPA4_BOTH      (0x0300)
+#define MCF_EPORT_EPPAR_EPPA3_LEVEL     (0x0000)
+#define MCF_EPORT_EPPAR_EPPA3_RISING    (0x0040)
+#define MCF_EPORT_EPPAR_EPPA3_FALLING   (0x0080)
+#define MCF_EPORT_EPPAR_EPPA3_BOTH      (0x00C0)
+#define MCF_EPORT_EPPAR_EPPA2_LEVEL     (0x0000)
+#define MCF_EPORT_EPPAR_EPPA2_RISING    (0x0010)
+#define MCF_EPORT_EPPAR_EPPA2_FALLING   (0x0020)
+#define MCF_EPORT_EPPAR_EPPA2_BOTH      (0x0030)
+#define MCF_EPORT_EPPAR_EPPA1_LEVEL     (0x0000)
+#define MCF_EPORT_EPPAR_EPPA1_RISING    (0x0004)
+#define MCF_EPORT_EPPAR_EPPA1_FALLING   (0x0008)
+#define MCF_EPORT_EPPAR_EPPA1_BOTH      (0x000C)
+
+/* Bit definitions and macros for EPDDR */
+#define MCF_EPORT_EPDDR_EPDD1   (0x02)
+#define MCF_EPORT_EPDDR_EPDD2   (0x04)
+#define MCF_EPORT_EPDDR_EPDD3   (0x08)
+#define MCF_EPORT_EPDDR_EPDD4   (0x10)
+#define MCF_EPORT_EPDDR_EPDD5   (0x20)
+#define MCF_EPORT_EPDDR_EPDD6   (0x40)
+#define MCF_EPORT_EPDDR_EPDD7   (0x80)
+
+/* Bit definitions and macros for EPIER */
+#define MCF_EPORT_EPIER_EPIE1   (0x02)
+#define MCF_EPORT_EPIER_EPIE2   (0x04)
+#define MCF_EPORT_EPIER_EPIE3   (0x08)
+#define MCF_EPORT_EPIER_EPIE4   (0x10)
+#define MCF_EPORT_EPIER_EPIE5   (0x20)
+#define MCF_EPORT_EPIER_EPIE6   (0x40)
+#define MCF_EPORT_EPIER_EPIE7   (0x80)
+
+/* Bit definitions and macros for EPDR */
+#define MCF_EPORT_EPDR_EPD1     (0x02)
+#define MCF_EPORT_EPDR_EPD2     (0x04)
+#define MCF_EPORT_EPDR_EPD3     (0x08)
+#define MCF_EPORT_EPDR_EPD4     (0x10)
+#define MCF_EPORT_EPDR_EPD5     (0x20)
+#define MCF_EPORT_EPDR_EPD6     (0x40)
+#define MCF_EPORT_EPDR_EPD7     (0x80)
+
+/* Bit definitions and macros for EPPDR */
+#define MCF_EPORT_EPPDR_EPPD1   (0x02)
+#define MCF_EPORT_EPPDR_EPPD2   (0x04)
+#define MCF_EPORT_EPPDR_EPPD3   (0x08)
+#define MCF_EPORT_EPPDR_EPPD4   (0x10)
+#define MCF_EPORT_EPPDR_EPPD5   (0x20)
+#define MCF_EPORT_EPPDR_EPPD6   (0x40)
+#define MCF_EPORT_EPPDR_EPPD7   (0x80)
+
+/* Bit definitions and macros for EPFR */
+#define MCF_EPORT_EPFR_EPF1     (0x02)
+#define MCF_EPORT_EPFR_EPF2     (0x04)
+#define MCF_EPORT_EPFR_EPF3     (0x08)
+#define MCF_EPORT_EPFR_EPF4     (0x10)
+#define MCF_EPORT_EPFR_EPF5     (0x20)
+#define MCF_EPORT_EPFR_EPF6     (0x40)
+#define MCF_EPORT_EPFR_EPF7     (0x80)
+
+/********************************************************************/
+
+#endif /* __MCF5445X_EPORT_H__ */
--- /dev/null
+++ b/include/asm-m68k/mcf5445x_fbcs.h
@@ -0,0 +1,182 @@
+/*
+ * Matt Waddel Matt.Waddel@freescale.com
+ *
+ * Copyright Freescale Semiconductor, Inc. 2007
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MCF5445X_FBCS_H__
+#define __MCF5445X_FBCS_H__
+
+/*********************************************************************
+*
+* FlexBus Chip Selects (FBCS)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_FBCS_CSAR0	MCF_REG32(0xFC008000)   /* Chip-select Addr Register */
+#define MCF_FBCS_CSMR0	MCF_REG32(0xFC008004)   /* Chip-select Mask Register */
+#define MCF_FBCS_CSCR0	MCF_REG32(0xFC008008)   /* Chip-select Cntl Register */
+#define MCF_FBCS_CSAR1	MCF_REG32(0xFC00800C)   /* Chip-select Addr Register */
+#define MCF_FBCS_CSMR1	MCF_REG32(0xFC008010)   /* Chip-select Mask Register */
+#define MCF_FBCS_CSCR1	MCF_REG32(0xFC008014)   /* Chip-select Cntl Register */
+#define MCF_FBCS_CSAR2	MCF_REG32(0xFC008018)   /* Chip-select Addr Register */
+#define MCF_FBCS_CSMR2	MCF_REG32(0xFC00801C)   /* Chip-select Mask Register */
+#define MCF_FBCS_CSCR2	MCF_REG32(0xFC008020)   /* Chip-select Cntl Register */
+#define MCF_FBCS_CSAR3	MCF_REG32(0xFC008024)   /* Chip-select Addr Register */
+#define MCF_FBCS_CSMR3	MCF_REG32(0xFC008028)   /* Chip-select Mask Register */
+#define MCF_FBCS_CSCR3	MCF_REG32(0xFC00802C)   /* Chip-select Cntl Register */
+
+/* Parameterized register read/write macros for multiple registers */
+#define MCF_FBCS_CSAR(x)	MCF_REG32(0xFC008000+((x)*0x00C))   /* Chip-select Addr Register */
+#define MCF_FBCS_CSMR(x)	MCF_REG32(0xFC008004+((x)*0x00C))   /* Chip-select Mask Register */
+#define MCF_FBCS_CSCR(x)	MCF_REG32(0xFC008008+((x)*0x00C))   /* Chip-select Cntl Register */
+
+/* Bit definitions and macros for CSAR group */
+#define MCF_FBCS_CSAR_BA(x)     ((x)&0xFFFF0000)
+
+/* Bit definitions and macros for CSAR0 */
+#define MCF_FBCS_CSAR0_BA(x)    ((x)&0xFFFF0000)
+
+/* Bit definitions and macros for CSMR group */
+#define MCF_FBCS_CSMR_V             (0x00000001)            /* Valid bit */
+#define MCF_FBCS_CSMR_WP            (0x00000100)            /* Write protect */
+#define MCF_FBCS_CSMR_BAM(x)        (((x)&0x0000FFFF)<<16)  /* Base addr mask */
+#define MCF_FBCS_CSMR_BAM_4G        (0xFFFF0000)
+#define MCF_FBCS_CSMR_BAM_2G        (0x7FFF0000)
+#define MCF_FBCS_CSMR_BAM_1G        (0x3FFF0000)
+#define MCF_FBCS_CSMR_BAM_1024M     (0x3FFF0000)
+#define MCF_FBCS_CSMR_BAM_512M      (0x1FFF0000)
+#define MCF_FBCS_CSMR_BAM_256M      (0x0FFF0000)
+#define MCF_FBCS_CSMR_BAM_128M      (0x07FF0000)
+#define MCF_FBCS_CSMR_BAM_64M       (0x03FF0000)
+#define MCF_FBCS_CSMR_BAM_32M       (0x01FF0000)
+#define MCF_FBCS_CSMR_BAM_16M       (0x00FF0000)
+#define MCF_FBCS_CSMR_BAM_8M        (0x007F0000)
+#define MCF_FBCS_CSMR_BAM_4M        (0x003F0000)
+#define MCF_FBCS_CSMR_BAM_2M        (0x001F0000)
+#define MCF_FBCS_CSMR_BAM_1M        (0x000F0000)
+#define MCF_FBCS_CSMR_BAM_1024K     (0x000F0000)
+#define MCF_FBCS_CSMR_BAM_512K      (0x00070000)
+#define MCF_FBCS_CSMR_BAM_256K      (0x00030000)
+#define MCF_FBCS_CSMR_BAM_128K      (0x00010000)
+#define MCF_FBCS_CSMR_BAM_64K       (0x00000000)
+
+/* Bit definitions and macros for CSMR0 */
+#define MCF_FBCS_CSMR0_V            (0x00000001)            /* Valid bit */
+#define MCF_FBCS_CSMR0_WP           (0x00000100)            /* Write protect */
+#define MCF_FBCS_CSMR0_BAM(x)       (((x)&0x0000FFFF)<<16)  /* Base addr mask */
+#define MCF_FBCS_CSMR0_BAM_4G       (0xFFFF0000)
+#define MCF_FBCS_CSMR0_BAM_2G       (0x7FFF0000)
+#define MCF_FBCS_CSMR0_BAM_1G       (0x3FFF0000)
+#define MCF_FBCS_CSMR0_BAM_1024M    (0x3FFF0000)
+#define MCF_FBCS_CSMR0_BAM_512M     (0x1FFF0000)
+#define MCF_FBCS_CSMR0_BAM_256M     (0x0FFF0000)
+#define MCF_FBCS_CSMR0_BAM_128M     (0x07FF0000)
+#define MCF_FBCS_CSMR0_BAM_64M      (0x03FF0000)
+#define MCF_FBCS_CSMR0_BAM_32M      (0x01FF0000)
+#define MCF_FBCS_CSMR0_BAM_16M      (0x00FF0000)
+#define MCF_FBCS_CSMR0_BAM_8M       (0x007F0000)
+#define MCF_FBCS_CSMR0_BAM_4M       (0x003F0000)
+#define MCF_FBCS_CSMR0_BAM_2M       (0x001F0000)
+#define MCF_FBCS_CSMR0_BAM_1M       (0x000F0000)
+#define MCF_FBCS_CSMR0_BAM_1024K    (0x000F0000)
+#define MCF_FBCS_CSMR0_BAM_512K     (0x00070000)
+#define MCF_FBCS_CSMR0_BAM_256K     (0x00030000)
+#define MCF_FBCS_CSMR0_BAM_128K     (0x00010000)
+#define MCF_FBCS_CSMR0_BAM_64K      (0x00000000)
+
+/* Bit definitions and macros for CSCR group */
+#define MCF_FBCS_CSCR_BSTW      (0x00000008)            /* Burst-write enable */
+#define MCF_FBCS_CSCR_BSTR      (0x00000010)            /* Burst-read enable */
+#define MCF_FBCS_CSCR_BEM       (0x00000020)            /* Byte-enable mode */
+#define MCF_FBCS_CSCR_PS(x)     (((x)&0x00000003)<<6)   /* Port size */
+#define MCF_FBCS_CSCR_AA        (0x00000100)            /* Auto-acknowledge */
+#define MCF_FBCS_CSCR_WS(x)     (((x)&0x0000003F)<<10)  /* Wait states */
+#define MCF_FBCS_CSCR_WRAH(x)   (((x)&0x00000003)<<16)  /* Write address hold or deselect */
+#define MCF_FBCS_CSCR_RDAH(x)   (((x)&0x00000003)<<18)  /* Read address hold or deselect */
+#define MCF_FBCS_CSCR_ASET(x)   (((x)&0x00000003)<<20)  /* Address setup */
+#define MCF_FBCS_CSCR_SWSEN     (0x00800000)            /* Secondary wait state enable */
+#define MCF_FBCS_CSCR_SWS(x)    (((x)&0x0000003F)<<26)  /* Secondary wait states */
+#define MCF_FBCS_CSCR_PS_8      (0x00000040)
+#define MCF_FBCS_CSCR_PS_16     (0x00000080)
+#define MCF_FBCS_CSCR_PS_32     (0x00000000)
+
+/* Bit definitions and macros for CSCR0 */
+#define MCF_FBCS_CSCR0_BSTW	(0x00000008)            /* Burst-write enable */
+#define MCF_FBCS_CSCR0_BSTR	(0x00000010)            /* Burst-read enable */
+#define MCF_FBCS_CSCR0_BEM	(0x00000020)            /* Byte-enable mode */
+#define MCF_FBCS_CSCR0_PS(x)	(((x)&0x00000003)<<6)   /* Port size */
+#define MCF_FBCS_CSCR0_AA	(0x00000100)            /* Auto-acknowledge */
+#define MCF_FBCS_CSCR0_WS(x)	(((x)&0x0000003F)<<10)  /* Wait states */
+#define MCF_FBCS_CSCR0_WRAH(x)	(((x)&0x00000003)<<16)  /* Write address hold or deselect */
+#define MCF_FBCS_CSCR0_RDAH(x)	(((x)&0x00000003)<<18)  /* Read address hold or deselect */
+#define MCF_FBCS_CSCR0_ASET(x)	(((x)&0x00000003)<<20)  /* Address setup */
+#define MCF_FBCS_CSCR0_SWSEN	(0x00800000)            /* Secondary wait state enable */
+#define MCF_FBCS_CSCR0_SWS(x)	(((x)&0x0000003F)<<26)  /* Secondary wait states */
+#define MCF_FBCS_CSCR0_PS_8	(0x00000040)
+#define MCF_FBCS_CSCR0_PS_16	(0x00000080)
+#define MCF_FBCS_CSCR0_PS_32	(0x00000000)
+
+/* Bit definitions and macros for CSMR1 */
+#define MCF_FBCS_CSMR1_V	(0x00000001)            /* Valid bit */
+#define MCF_FBCS_CSMR1_WP	(0x00000100)            /* Write protect */
+#define MCF_FBCS_CSMR1_BAM(x)	(((x)&0x0000FFFF)<<16)  /* Base address mask */
+
+/* Bit definitions and macros for CSCR1 */
+#define MCF_FBCS_CSCR1_BSTW	(0x00000008)            /* Burst-write enable */
+#define MCF_FBCS_CSCR1_BSTR	(0x00000010)            /* Burst-read enable */
+#define MCF_FBCS_CSCR1_BEM	(0x00000020)            /* Byte-enable mode */
+#define MCF_FBCS_CSCR1_PS(x)	(((x)&0x00000003)<<6)   /* Port size */
+#define MCF_FBCS_CSCR1_AA	(0x00000100)            /* Auto-acknowledge */
+#define MCF_FBCS_CSCR1_WS(x)	(((x)&0x0000003F)<<10)  /* Wait states */
+#define MCF_FBCS_CSCR1_WRAH(x)	(((x)&0x00000003)<<16)  /* Write address hold or deselect */
+#define MCF_FBCS_CSCR1_RDAH(x)	(((x)&0x00000003)<<18)  /* Read address hold or deselect */
+#define MCF_FBCS_CSCR1_ASET(x)	(((x)&0x00000003)<<20)  /* Address setup */
+#define MCF_FBCS_CSCR1_SWSEN	(0x00800000)            /* Secondary wait state enable */
+#define MCF_FBCS_CSCR1_SWS(x)	(((x)&0x0000003F)<<26)  /* Secondary wait states */
+
+/* Bit definitions and macros for CSMR2 */
+#define MCF_FBCS_CSMR2_V	(0x00000001)            /* Valid bit */
+#define MCF_FBCS_CSMR2_WP	(0x00000100)            /* Write protect */
+#define MCF_FBCS_CSMR2_BAM(x)	(((x)&0x0000FFFF)<<16)  /* Base address mask */
+
+/* Bit definitions and macros for CSCR2 */
+#define MCF_FBCS_CSCR2_BSTW	(0x00000008)            /* Burst-write enable */
+#define MCF_FBCS_CSCR2_BSTR	(0x00000010)            /* Burst-read enable */
+#define MCF_FBCS_CSCR2_BEM	(0x00000020)            /* Byte-enable mode */
+#define MCF_FBCS_CSCR2_PS(x)	(((x)&0x00000003)<<6)   /* Port size */
+#define MCF_FBCS_CSCR2_AA	(0x00000100)            /* Auto-acknowledge */
+#define MCF_FBCS_CSCR2_WS(x)	(((x)&0x0000003F)<<10)  /* Wait states */
+#define MCF_FBCS_CSCR2_WRAH(x)	(((x)&0x00000003)<<16)  /* Write address hold or deselect */
+#define MCF_FBCS_CSCR2_RDAH(x)	(((x)&0x00000003)<<18)  /* Read address hold or deselect */
+#define MCF_FBCS_CSCR2_ASET(x)	(((x)&0x00000003)<<20)  /* Address setup */
+#define MCF_FBCS_CSCR2_SWSEN	(0x00800000)            /* Secondary wait state enable */
+#define MCF_FBCS_CSCR2_SWS(x)	(((x)&0x0000003F)<<26)  /* Secondary wait states */
+
+/* Bit definitions and macros for CSMR3 */
+#define MCF_FBCS_CSMR3_V	(0x00000001)            /* Valid bit */
+#define MCF_FBCS_CSMR3_WP	(0x00000100)            /* Write protect */
+#define MCF_FBCS_CSMR3_BAM(x)	(((x)&0x0000FFFF)<<16)  /* Base address mask */
+
+/* Bit definitions and macros for CSCR3 */
+#define MCF_FBCS_CSCR3_BSTW	(0x00000008)            /* Burst-write enable */
+#define MCF_FBCS_CSCR3_BSTR	(0x00000010)            /* Burst-read enable */
+#define MCF_FBCS_CSCR3_BEM	(0x00000020)            /* Byte-enable mode */
+#define MCF_FBCS_CSCR3_PS(x)	(((x)&0x00000003)<<6)   /* Port size */
+#define MCF_FBCS_CSCR3_AA	(0x00000100)            /* Auto-acknowledge */
+#define MCF_FBCS_CSCR3_WS(x)	(((x)&0x0000003F)<<10)  /* Wait states */
+#define MCF_FBCS_CSCR3_WRAH(x)	(((x)&0x00000003)<<16)  /* Write address hold or deselect */
+#define MCF_FBCS_CSCR3_RDAH(x)	(((x)&0x00000003)<<18)  /* Read address hold or deselect */
+#define MCF_FBCS_CSCR3_ASET(x)	(((x)&0x00000003)<<20)  /* Address setup */
+#define MCF_FBCS_CSCR3_SWSEN	(0x00800000)            /* Secondary wait state enable */
+#define MCF_FBCS_CSCR3_SWS(x)	(((x)&0x0000003F)<<26)  /* Secondary wait states */
+
+/********************************************************************/
+
+#endif /* __MCF5445X_FBCS_H__ */
--- /dev/null
+++ b/include/asm-m68k/mcf5445x_gpio.h
@@ -0,0 +1,1257 @@
+/*
+ * Matt Waddel Matt.Waddel@freescale.com
+ *
+ * Copyright Freescale Semiconductor, Inc. 2007
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MCF5445X_GPIO_H__
+#define __MCF5445X_GPIO_H__
+
+/*********************************************************************
+*
+* General Purpose I/O Module (GPIO)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_GPIO_PODR_FEC0H	MCF_REG08(0xFC0A4000)	/* FEC0 High Port Output Data Register */
+#define MCF_GPIO_PODR_FEC0L	MCF_REG08(0xFC0A4001)	/* FEC0 Low Port Output Data Register */
+#define MCF_GPIO_PODR_SSI	MCF_REG08(0xFC0A4002)	/* SSI Port Output Data Register */
+#define MCF_GPIO_PODR_FBCTL	MCF_REG08(0xFC0A4003)	/* Flexbus Control Port Output Data Register */
+#define MCF_GPIO_PODR_BE	MCF_REG08(0xFC0A4004)	/* Flexbus Byte Enable Port Output Data Register */
+#define MCF_GPIO_PODR_CS	MCF_REG08(0xFC0A4005)	/* Flexbus Chip-Select Port Output Data Register */
+#define MCF_GPIO_PODR_DMA	MCF_REG08(0xFC0A4006)	/* DMA Port Output Data Register */
+#define MCF_GPIO_PODR_FECI2C	MCF_REG08(0xFC0A4007)	/* FEC1 / I2C Port Output Data Register */
+#define MCF_GPIO_PODR_UART	MCF_REG08(0xFC0A4009)	/* UART Port Output Data Register */
+#define MCF_GPIO_PODR_DSPI	MCF_REG08(0xFC0A400A)	/* DSPI Port Output Data Register */
+#define MCF_GPIO_PODR_TIMER	MCF_REG08(0xFC0A400B)	/* Timer Port Output Data Register */
+#define MCF_GPIO_PODR_PCI	MCF_REG08(0xFC0A400C)	/* PCI Port Output Data Register */
+#define MCF_GPIO_PODR_USB	MCF_REG08(0xFC0A400D)	/* USB Port Output Data Register */
+#define MCF_GPIO_PODR_ATAH	MCF_REG08(0xFC0A400E)	/* ATA High Port Output Data Register */
+#define MCF_GPIO_PODR_ATAL	MCF_REG08(0xFC0A400F)	/* ATA Low Port Output Data Register */
+#define MCF_GPIO_PODR_FEC1H	MCF_REG08(0xFC0A4010)	/* FEC1 High Port Output Data Register */
+#define MCF_GPIO_PODR_FEC1L	MCF_REG08(0xFC0A4011)	/* FEC1 Low Port Output Data Register */
+#define MCF_GPIO_PODR_FBADH	MCF_REG08(0xFC0A4014)	/* Flexbus AD High Port Output Data Register */
+#define MCF_GPIO_PODR_FBADMH	MCF_REG08(0xFC0A4015)	/* Flexbus AD Med-High Port Output Data Register */
+#define MCF_GPIO_PODR_FBADML	MCF_REG08(0xFC0A4016)	/* Flexbus AD Med-Low Port Output Data Register */
+#define MCF_GPIO_PODR_FBADL	MCF_REG08(0xFC0A4017)	/* Flexbus AD Low Port Output Data Register */
+#define MCF_GPIO_PDDR_FEC0H	MCF_REG08(0xFC0A4018)	/* FEC0 High Port Data Direction Register */
+#define MCF_GPIO_PDDR_FEC0L	MCF_REG08(0xFC0A4019)	/* FEC0 Low Port Data Direction Register */
+#define MCF_GPIO_PDDR_SSI	MCF_REG08(0xFC0A401A)	/* SSI Port Data Direction Register */
+#define MCF_GPIO_PDDR_FBCTL	MCF_REG08(0xFC0A401B)	/* Flexbus Control Port Data Direction Register */
+#define MCF_GPIO_PDDR_BE	MCF_REG08(0xFC0A401C)	/* Flexbus Byte Enable Port Data Direction Register */
+#define MCF_GPIO_PDDR_CS	MCF_REG08(0xFC0A401D)	/* Flexbus Chip-Select Port Data Direction Register */
+#define MCF_GPIO_PDDR_DMA	MCF_REG08(0xFC0A401E)	/* DMA Port Data Direction Register */
+#define MCF_GPIO_PDDR_FECI2C	MCF_REG08(0xFC0A401F)	/* FEC1 / I2C Port Data Direction Register */
+#define MCF_GPIO_PDDR_UART	MCF_REG08(0xFC0A4021)	/* UART Port Data Direction Register */
+#define MCF_GPIO_PDDR_DSPI	MCF_REG08(0xFC0A4022)	/* DSPI Port Data Direction Register */
+#define MCF_GPIO_PDDR_TIMER	MCF_REG08(0xFC0A4023)	/* Timer Port Data Direction Register */
+#define MCF_GPIO_PDDR_PCI	MCF_REG08(0xFC0A4024)	/* PCI Port Data Direction Register */
+#define MCF_GPIO_PDDR_USB	MCF_REG08(0xFC0A4025)	/* USB Port Data Direction Register */
+#define MCF_GPIO_PDDR_ATAH	MCF_REG08(0xFC0A4026)	/* ATA High Port Data Direction Register */
+#define MCF_GPIO_PDDR_ATAL	MCF_REG08(0xFC0A4027)	/* ATA Low Port Data Direction Register */
+#define MCF_GPIO_PDDR_FEC1H	MCF_REG08(0xFC0A4028)	/* FEC1 High Port Data Direction Register */
+#define MCF_GPIO_PDDR_FEC1L	MCF_REG08(0xFC0A4029)	/* FEC1 Low Port Data Direction Register */
+#define MCF_GPIO_PDDR_FBADH	MCF_REG08(0xFC0A402C)	/* Flexbus AD High Port Data Direction Register */
+#define MCF_GPIO_PDDR_FBADMH	MCF_REG08(0xFC0A402D)	/* Flexbus AD Med-High Port Data Direction Register */
+#define MCF_GPIO_PDDR_FBADML	MCF_REG08(0xFC0A402E)	/* Flexbus AD Med-Low Port Data Direction Register */
+#define MCF_GPIO_PDDR_FBADL	MCF_REG08(0xFC0A402F)	/* Flexbus AD Low Port Data Direction Register */
+#define MCF_GPIO_PPDSDR_FEC0H	MCF_REG08(0xFC0A4030)	/* FEC0 High Port Pin Data/Set Data Register */
+#define MCF_GPIO_PPDSDR_FEC0L	MCF_REG08(0xFC0A4031)	/* FEC0 Low Port Clear Output Data Register */
+#define MCF_GPIO_PPDSDR_SSI	MCF_REG08(0xFC0A4032)	/* SSI Port Pin Data/Set Data Register */
+#define MCF_GPIO_PPDSDR_FBCTL	MCF_REG08(0xFC0A4033)	/* Flexbus Control Port Pin Data/Set Data Register */
+#define MCF_GPIO_PPDSDR_BE	MCF_REG08(0xFC0A4034)	/* Flexbus Byte Enable Port Pin Data/Set Data Register */
+#define MCF_GPIO_PPDSDR_CS	MCF_REG08(0xFC0A4035)	/* Flexbus Chip-Select Port Pin Data/Set Data Register */
+#define MCF_GPIO_PPDSDR_DMA	MCF_REG08(0xFC0A4036)	/* DMA Port Pin Data/Set Data Register */
+#define MCF_GPIO_PPDSDR_FECI2C	MCF_REG08(0xFC0A4037)	/* FEC1 / I2C Port Pin Data/Set Data Register */
+#define MCF_GPIO_PPDSDR_UART	MCF_REG08(0xFC0A4039)	/* UART Port Pin Data/Set Data Register */
+#define MCF_GPIO_PPDSDR_DSPI	MCF_REG08(0xFC0A403A)	/* DSPI Port Pin Data/Set Data Register */
+#define MCF_GPIO_PPDSDR_TIMER	MCF_REG08(0xFC0A403B)	/* FTimer Port Pin Data/Set Data Register */
+#define MCF_GPIO_PPDSDR_PCI	MCF_REG08(0xFC0A403C)	/* PCI Port Pin Data/Set Data Register */
+#define MCF_GPIO_PPDSDR_USB	MCF_REG08(0xFC0A403D)	/* USB Port Pin Data/Set Data Register */
+#define MCF_GPIO_PPDSDR_ATAH	MCF_REG08(0xFC0A403E)	/* ATA High Port Pin Data/Set Data Register */
+#define MCF_GPIO_PPDSDR_ATAL	MCF_REG08(0xFC0A403F)	/* ATA Low Port Pin Data/Set Data Register */
+#define MCF_GPIO_PPDSDR_FEC1H	MCF_REG08(0xFC0A4040)	/* FEC1 High Port Pin Data/Set Data Register */
+#define MCF_GPIO_PPDSDR_FEC1L	MCF_REG08(0xFC0A4041)	/* FEC1 Low Port Pin Data/Set Data Register */
+#define MCF_GPIO_PPDSDR_FBADH	MCF_REG08(0xFC0A4044)	/* Flexbus AD High Port Pin Data/Set Data Register */
+#define MCF_GPIO_PPDSDR_FBADMH	MCF_REG08(0xFC0A4045)	/* Flexbus AD Med-High Port Pin Data/Set Data Register */
+#define MCF_GPIO_PPDSDR_FBADML	MCF_REG08(0xFC0A4046)	/* Flexbus AD Med-Low Port Pin Data/Set Data Register */
+#define MCF_GPIO_PPDSDR_FBADL	MCF_REG08(0xFC0A4047)	/* Flexbus AD Low Port Pin Data/Set Data Register */
+#define MCF_GPIO_PCLRR_FEC0H	MCF_REG08(0xFC0A4048)	/* FEC0 High Port Clear Output Data Register */
+#define MCF_GPIO_PCLRR_FEC0L	MCF_REG08(0xFC0A4049)	/* FEC0 Low Port Pin Data/Set Data Register */
+#define MCF_GPIO_PCLRR_SSI	MCF_REG08(0xFC0A404A)	/* SSI Port Clear Output Data Register */
+#define MCF_GPIO_PCLRR_FBCTL	MCF_REG08(0xFC0A404B)	/* Flexbus Control Port Clear Output Data Register */
+#define MCF_GPIO_PCLRR_BE	MCF_REG08(0xFC0A404C)	/* Flexbus Byte Enable Port Clear Output Data Register */
+#define MCF_GPIO_PCLRR_CS	MCF_REG08(0xFC0A404D)	/* Flexbus Chip-Select Port Clear Output Data Register */
+#define MCF_GPIO_PCLRR_DMA	MCF_REG08(0xFC0A404E)	/* DMA Port Clear Output Data Register */
+#define MCF_GPIO_PCLRR_FECI2C	MCF_REG08(0xFC0A404F)	/* FEC1 / I2C Port Clear Output Data Register */
+#define MCF_GPIO_PCLRR_UART	MCF_REG08(0xFC0A4051)	/* UART Port Clear Output Data Register */
+#define MCF_GPIO_PCLRR_DSPI	MCF_REG08(0xFC0A4052)	/* DSPI Port Clear Output Data Register */
+#define MCF_GPIO_PCLRR_TIMER	MCF_REG08(0xFC0A4053)	/* Timer Port Clear Output Data Register */
+#define MCF_GPIO_PCLRR_PCI	MCF_REG08(0xFC0A4054)	/* PCI Port Clear Output Data Register */
+#define MCF_GPIO_PCLRR_USB	MCF_REG08(0xFC0A4055)	/* USB Port Clear Output Data Register */
+#define MCF_GPIO_PCLRR_ATAH	MCF_REG08(0xFC0A4056)	/* ATA High Port Clear Output Data Register */
+#define MCF_GPIO_PCLRR_ATAL	MCF_REG08(0xFC0A4057)	/* ATA Low Port Clear Output Data Register */
+#define MCF_GPIO_PCLRR_FEC1H	MCF_REG08(0xFC0A4058)	/* FEC1 High Port Clear Output Data Register */
+#define MCF_GPIO_PCLRR_FEC1L	MCF_REG08(0xFC0A4059)	/* FEC1 Low Port Clear Output Data Register */
+#define MCF_GPIO_PCLRR_FBADH	MCF_REG08(0xFC0A405C)	/* Flexbus AD High Port Clear Output Data Register */
+#define MCF_GPIO_PCLRR_FBADMH	MCF_REG08(0xFC0A405D)	/* Flexbus AD Med-High Port Clear Output Data Register */
+#define MCF_GPIO_PCLRR_FBADML	MCF_REG08(0xFC0A405E)	/* Flexbus AD Med-Low Port Clear Output Data Register */
+#define MCF_GPIO_PCLRR_FBADL	MCF_REG08(0xFC0A405F)	/* Flexbus AD Low Port Clear Output Data Register */
+#define MCF_GPIO_PAR_FEC	MCF_REG08(0xFC0A4060)	/* FEC Pin Assignment Register */
+#define MCF_GPIO_PAR_DMA	MCF_REG08(0xFC0A4061)	/* DMA Pin Assignment Register */
+#define MCF_GPIO_PAR_FBCTL	MCF_REG08(0xFC0A4062)	/* Flexbus Control Pin Assignment Register */
+#define MCF_GPIO_PAR_DSPI	MCF_REG08(0xFC0A4063)	/* DSPI Pin Assignment Register */
+#define MCF_GPIO_PAR_BE		MCF_REG08(0xFC0A4064)	/* Flexbus Byte-Enable Pin Assignment Register */
+#define MCF_GPIO_PAR_CS		MCF_REG08(0xFC0A4065)	/* Flexbus Chip-Select Pin Assignment Register */
+#define MCF_GPIO_PAR_TIMER	MCF_REG08(0xFC0A4066)	/* Time Pin Assignment Register */
+#define MCF_GPIO_PAR_USB	MCF_REG08(0xFC0A4067)	/* USB Pin Assignment Register */
+#define MCF_GPIO_PAR_UART	MCF_REG08(0xFC0A4069)	/* UART Pin Assignment Register */
+#define MCF_GPIO_PAR_FECI2C	MCF_REG16(0xFC0A406A)	/* FEC / I2C Pin Assignment Register */
+#define MCF_GPIO_PAR_SSI	MCF_REG16(0xFC0A406C)	/* SSI Pin Assignment Register */
+#define MCF_GPIO_PAR_ATA	MCF_REG16(0xFC0A406E)	/* ATA Pin Assignment Register */
+#define MCF_GPIO_PAR_IRQ	MCF_REG08(0xFC0A4070)	/* IRQ Pin Assignment Register */
+#define MCF_GPIO_PAR_PCI	MCF_REG16(0xFC0A4072)	/* PCI Pin Assignment Register */
+#define MCF_GPIO_MSCR_SDRAM	MCF_REG08(0xFC0A4074)	/* SDRAM Mode Select Control Register */
+#define MCF_GPIO_MSCR_PCI	MCF_REG08(0xFC0A4075)	/* PCI Mode Select Control Register */
+#define MCF_GPIO_DSCR_I2C	MCF_REG08(0xFC0A4078)	/* I2C Drive Strength Control Register */
+#define MCF_GPIO_DSCR_FLEXBUS	MCF_REG08(0xFC0A4079)	/* FLEXBUS Drive Strength Control Register */
+#define MCF_GPIO_DSCR_FEC	MCF_REG08(0xFC0A407A)	/* FEC Drive Strength Control Register */
+#define MCF_GPIO_DSCR_UART	MCF_REG08(0xFC0A407B)	/* UART Drive Strength Control Register */
+#define MCF_GPIO_DSCR_DSPI	MCF_REG08(0xFC0A407C)	/* DSPI Drive Strength Control Register */
+#define MCF_GPIO_DSCR_TIMER	MCF_REG08(0xFC0A407D)	/* TIMER Drive Strength Control Register */
+#define MCF_GPIO_DSCR_SSI	MCF_REG08(0xFC0A407E)	/* SSI Drive Strength Control Register */
+#define MCF_GPIO_DSCR_DMA	MCF_REG08(0xFC0A407F)	/* DMA Drive Strength Control Register */
+#define MCF_GPIO_DSCR_DEBUG	MCF_REG08(0xFC0A4080)	/* DEBUG Drive Strength Control Register */
+#define MCF_GPIO_DSCR_RESET	MCF_REG08(0xFC0A4081)	/* RESET Drive Strength Control Register */
+#define MCF_GPIO_DSCR_IRQ	MCF_REG08(0xFC0A4082)	/* IRQ Drive Strength Control Register */
+#define MCF_GPIO_DSCR_USB	MCF_REG08(0xFC0A4083)	/* USB Drive Strength Control Register */
+#define MCF_GPIO_DSCR_ATA	MCF_REG08(0xFC0A4084)	/* ATA Drive Strength Control Register */
+
+/* Bit definitions and macros for PODR_FEC0H */
+#define MCF_GPIO_PODR_FEC0H_PODR0	(0x01)	/* FEC0_CRS / ULPI_DATA6 */
+#define MCF_GPIO_PODR_FEC0H_PODR1	(0x02)	/* FEC0_RXD0 / FEC0_RMII_RXD0 */
+#define MCF_GPIO_PODR_FEC0H_PODR2	(0x04)	/* FEC0_RXDV/FEC0_RMII_CRS_DV */
+#define MCF_GPIO_PODR_FEC0H_PODR3	(0x08)	/* FEC0_RXCLK / ULPI_DATA1 */
+#define MCF_GPIO_PODR_FEC0H_PODR4	(0x10)	/* FEC0_COL / ULPI_DATA7 */
+#define MCF_GPIO_PODR_FEC0H_PODR5	(0x20)	/* FEC0_TXD0 / FEC0_RMII_TXD0 */
+#define MCF_GPIO_PODR_FEC0H_PODR6	(0x40)	/* FEC0_TXEN / FEC0_RMII_TXEN */
+#define MCF_GPIO_PODR_FEC0H_PODR7	(0x80)	/* FEC0_TXCLK / FEC0_RMII_REF_CLK */
+
+/* Bit definitions and macros for PODR_FEC0L */
+#define MCF_GPIO_PODR_FEC0L_PODR0	(0x01)	/* FEC0_RXER / FEC0_RMII_RXER */
+#define MCF_GPIO_PODR_FEC0L_PODR1	(0x02)	/* FEC0_RXD1 / FEC0_RMII_RXD1 */
+#define MCF_GPIO_PODR_FEC0L_PODR2	(0x04)	/* FEC0_RXD2 / ULPI_DATA4 */
+#define MCF_GPIO_PODR_FEC0L_PODR3	(0x08)	/* FEC0_RXD3 / ULPI_DATA5 */
+#define MCF_GPIO_PODR_FEC0L_PODR4	(0x10)	/* FEC0_TXER / ULPI_DATA0 */
+#define MCF_GPIO_PODR_FEC0L_PODR5	(0x20)	/* FEC0_TXD1 / FEC0_RMII_TXD1 */
+#define MCF_GPIO_PODR_FEC0L_PODR6	(0x40)	/* FEC0_TXD2 / ULPI_DATA2 */
+#define MCF_GPIO_PODR_FEC0L_PODR7	(0x80)	/* FEC0_TXD3 / ULPI_DATA3 */
+
+/* Bit definitions and macros for PODR_SSI */
+#define MCF_GPIO_PODR_SSI_PODR0		(0x01)	/* SSI_TXD / U1TXD */
+#define MCF_GPIO_PODR_SSI_PODR1		(0x02)	/* SSI_RXD / U1RXD */
+#define MCF_GPIO_PODR_SSI_PODR2		(0x04)	/* SSI_FS / U1RTS */
+#define MCF_GPIO_PODR_SSI_PODR3		(0x08)	/* SSI_BCLK / U1CTS */
+#define MCF_GPIO_PODR_SSI_PODR4		(0x10)	/* SSI_MCLK */
+
+/* Bit definitions and macros for PODR_FBCTL */
+#define MCF_GPIO_PODR_FBCTL_PODR0	(0x01)	/* FB_TS / FB_ALE / FB_TBST */
+#define MCF_GPIO_PODR_FBCTL_PODR1	(0x02)	/* FB_RW */
+#define MCF_GPIO_PODR_FBCTL_PODR2	(0x04)	/* FB_TA */
+#define MCF_GPIO_PODR_FBCTL_PODR3	(0x08)	/* FB_OE */
+
+/* Bit definitions and macros for PODR_BE */
+#define MCF_GPIO_PODR_BE_PODR0		(0x01)	/* FB_BE/BWE0 / FB_SIZ0 */
+#define MCF_GPIO_PODR_BE_PODR1		(0x02)	/* FB_BE/BWE1 / FB_SIZ1 */
+#define MCF_GPIO_PODR_BE_PODR2		(0x04)	/* FB_BE/BWE2 / FB_SIZ2 */
+#define MCF_GPIO_PODR_BE_PODR3		(0x08)	/* FB_BE/BWE3 / FB_SIZ3 */
+
+/* Bit definitions and macros for PODR_CS */
+#define MCF_GPIO_PODR_CS_PODR1		(0x02)	/* FB_CS1 */
+#define MCF_GPIO_PODR_CS_PODR2		(0x04)	/* FB_CS2 */
+#define MCF_GPIO_PODR_CS_PODR3		(0x08)	/* FB_CS3 */
+
+/* Bit definitions and macros for PODR_DMA */
+#define MCF_GPIO_PODR_DMA_PODR0		(0x01)	/* DREQ0 */
+#define MCF_GPIO_PODR_DMA_PODR1		(0x02)	/* DACK0 / DSPI_PCS3 */
+#define MCF_GPIO_PODR_DMA_PODR2		(0x04)	/* DREQ1 / USB_CLKIN */
+#define MCF_GPIO_PODR_DMA_PODR3		(0x08)	/* DACK1 / ULPI_DIR */
+
+/* Bit definitions and macros for PODR_FECI2C */
+#define MCF_GPIO_PODR_FECI2C_PODR0	(0x01)	/* I2C_SDA / U2RXD */
+#define MCF_GPIO_PODR_FECI2C_PODR1	(0x02)	/* I2C_SCL / U2TXD */
+#define MCF_GPIO_PODR_FECI2C_PODR2	(0x04)	/* FEC0_MDIO */
+#define MCF_GPIO_PODR_FECI2C_PODR3	(0x08)	/* FEC0_MDC */
+#define MCF_GPIO_PODR_FECI2C_PODR4	(0x10)	/* FEC1_MDIO / ATA_DIOW */
+#define MCF_GPIO_PODR_FECI2C_PODR5	(0x20)	/* FEC1_MDC / ATA_DIOR */
+
+/* Bit definitions and macros for PODR_UART */
+#define MCF_GPIO_PODR_UART_PODR0	(0x01)	/* U1TXD */
+#define MCF_GPIO_PODR_UART_PODR1	(0x02)	/* U1RXD */
+#define MCF_GPIO_PODR_UART_PODR2	(0x04)	/* U1RTS */
+#define MCF_GPIO_PODR_UART_PODR3	(0x08)	/* U0CTS */
+#define MCF_GPIO_PODR_UART_PODR4	(0x10)	/* U1TXD */
+#define MCF_GPIO_PODR_UART_PODR5	(0x20)	/* U1RXD */
+#define MCF_GPIO_PODR_UART_PODR6	(0x40)	/* U1RTS */
+#define MCF_GPIO_PODR_UART_PODR7	(0x80)	/* U1CTS */
+
+/* Bit definitions and macros for PODR_DSPI */
+#define MCF_GPIO_PODR_DSPI_PODR0	(0x01)	/* DSPI_SOUT / SBF_DO */
+#define MCF_GPIO_PODR_DSPI_PODR1	(0x02)	/* DSPI_SIN / SBF_DI */
+#define MCF_GPIO_PODR_DSPI_PODR2	(0x04)	/* DSPI_SCK / SBF_CK */
+#define MCF_GPIO_PODR_DSPI_PODR3	(0x08)	/* DSPI_PCS0/SS */
+#define MCF_GPIO_PODR_DSPI_PODR4	(0x10)	/* DSPI_PCS1 / SBF_CS */
+#define MCF_GPIO_PODR_DSPI_PODR5	(0x20)	/* DSPI_PCS2 */
+#define MCF_GPIO_PODR_DSPI_PODR6	(0x40)	/* DSPI_PCS5/SS */
+
+/* Bit definitions and macros for PODR_TIMER */
+#define MCF_GPIO_PODR_TIMER_PODR0	(0x01)	/* T0IN / T0OUT / U2RTS */
+#define MCF_GPIO_PODR_TIMER_PODR1	(0x02)	/* T1IN / T1OUT / U2CTS */
+#define MCF_GPIO_PODR_TIMER_PODR2	(0x04)	/* T2IN / T2OUT / U2TXD */
+#define MCF_GPIO_PODR_TIMER_PODR3	(0x08)	/* T3IN / T3OUT / U2RXD */
+
+/* Bit definitions and macros for PODR_PCI */
+#define MCF_GPIO_PODR_PCI_PODR0		(0x01)	/* PCI_REQ0/PCI_EXTGNT */
+#define MCF_GPIO_PODR_PCI_PODR1		(0x02)	/* PCI_REQ1 */
+#define MCF_GPIO_PODR_PCI_PODR2		(0x04)	/* PCI_REQ2 */
+#define MCF_GPIO_PODR_PCI_PODR3		(0x08)	/* PCI_REQ3 / ATA_INTR */
+#define MCF_GPIO_PODR_PCI_PODR4		(0x10)	/* PCI_GNT0/PCI_EXTREQ */
+#define MCF_GPIO_PODR_PCI_PODR5		(0x20)	/* PCI_GNT1 /  */
+#define MCF_GPIO_PODR_PCI_PODR6		(0x40)	/* PCI_GNT2 /  */
+#define MCF_GPIO_PODR_PCI_PODR7		(0x80)	/* PCI_GNT3 / ATA_DMACK */
+
+/* Bit definitions and macros for PODR_USB */
+#define MCF_GPIO_PODR_USB_PODR0		(0x01)	/* USB_VBUS_OC / ULPI_STP */
+#define MCF_GPIO_PODR_USB_PODR1		(0x02)	/* USB_VBUS_EN / USB_PULLUP / ULPI_NXT */
+
+/* Bit definitions and macros for PODR_ATAH */
+#define MCF_GPIO_PODR_ATAH_PODR0	(0x01)	/* ATA_DA0 */
+#define MCF_GPIO_PODR_ATAH_PODR1	(0x02)	/* ATA_DA1 */
+#define MCF_GPIO_PODR_ATAH_PODR2	(0x04)	/* ATA_DA2 */
+#define MCF_GPIO_PODR_ATAH_PODR3	(0x08)	/* ATA_CS0 */
+#define MCF_GPIO_PODR_ATAH_PODR4	(0x10)	/* ATA_CS1 */
+#define MCF_GPIO_PODR_ATAH_PODR5	(0x20)	/* ATA_BUFFER_EN */
+
+/* Bit definitions and macros for PODR_ATAL */
+#define MCF_GPIO_PODR_ATAL_PODR0	(0x01)	/* ATA_IORDY */
+#define MCF_GPIO_PODR_ATAL_PODR1	(0x02)	/* ATA_DMARQ */
+#define MCF_GPIO_PODR_ATAL_PODR2	(0x04)	/* ATA_RESET */
+
+/* Bit definitions and macros for PODR_FEC1H */
+#define MCF_GPIO_PODR_FEC1H_PODR0	(0x01)	/* FEC1_CRS / ATA_DATA6 */
+#define MCF_GPIO_PODR_FEC1H_PODR1	(0x02)	/* FEC1_RXD0 / FEC1_RMII_RXD0 / ATA_DATA13 */
+#define MCF_GPIO_PODR_FEC1H_PODR2	(0x04)	/* FEC1_RXDV / FEC1_RMII_CRS_DV / ATA_DATA15 */
+#define MCF_GPIO_PODR_FEC1H_PODR3	(0x08)	/* FEC1_RXCLK / ATA_DATA5 */
+#define MCF_GPIO_PODR_FEC1H_PODR4	(0x10)	/* FEC1_COL / ATA_DATA7 */
+#define MCF_GPIO_PODR_FEC1H_PODR5	(0x20)	/* FEC1_TXD0 / FEC1_RMII_TXD0 / ATA_DATA9 */
+#define MCF_GPIO_PODR_FEC1H_PODR6	(0x40)	/* FEC1_TXEN / FEC1_RMII_TXEN / ATA_DATA8 */
+#define MCF_GPIO_PODR_FEC1H_PODR7	(0x80)	/* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */
+
+/* Bit definitions and macros for PODR_FEC1L */
+#define MCF_GPIO_PODR_FEC1L_PODR0	(0x01)	/* FEC1_RXER / FEC1_RMII_RXER / ATA_DATA12 */
+#define MCF_GPIO_PODR_FEC1L_PODR1	(0x02)	/* FEC1_RXD1 / FEC1_RMII_RXD1 / ATA_DATA14 */
+#define MCF_GPIO_PODR_FEC1L_PODR2	(0x04)	/* FEC1_RXD2 / ATA_DATA3 */
+#define MCF_GPIO_PODR_FEC1L_PODR3	(0x08)	/* FEC1_RXD3 / ATA_DATA4 */
+#define MCF_GPIO_PODR_FEC1L_PODR4	(0x10)	/* FEC1_TXER / ATA_DATA0 */
+#define MCF_GPIO_PODR_FEC1L_PODR5	(0x20)	/* FEC1_TXD1 / FEC1_RMII_TXD1 / ATA_DATA10 */
+#define MCF_GPIO_PODR_FEC1L_PODR6	(0x40)	/* FEC1_TXD2 / ATA_DATA1 */
+#define MCF_GPIO_PODR_FEC1L_PODR7	(0x80)	/* FEC1_TXD3 / ATA_DATA2 */
+
+/* Bit definitions and macros for PODR_FBADH */
+#define MCF_GPIO_PODR_FBADH_PODR0	(0x01)	/* FB_AD24 */
+#define MCF_GPIO_PODR_FBADH_PODR1	(0x02)	/* FB_AD25 */
+#define MCF_GPIO_PODR_FBADH_PODR2	(0x04)	/* FB_AD26 */
+#define MCF_GPIO_PODR_FBADH_PODR3	(0x08)	/* FB_AD27 */
+#define MCF_GPIO_PODR_FBADH_PODR4	(0x10)	/* FB_AD28 */
+#define MCF_GPIO_PODR_FBADH_PODR5	(0x20)	/* FB_AD29 */
+#define MCF_GPIO_PODR_FBADH_PODR6	(0x40)	/* FB_AD30 */
+#define MCF_GPIO_PODR_FBADH_PODR7	(0x80)	/* FB_AD31 */
+
+/* Bit definitions and macros for PODR_FBADMH */
+#define MCF_GPIO_PODR_FBADMH_PODR0	(0x01)	/* FB_AD16 */
+#define MCF_GPIO_PODR_FBADMH_PODR1	(0x02)	/* FB_AD17 */
+#define MCF_GPIO_PODR_FBADMH_PODR2	(0x04)	/* FB_AD18 */
+#define MCF_GPIO_PODR_FBADMH_PODR3	(0x08)	/* FB_AD19 */
+#define MCF_GPIO_PODR_FBADMH_PODR4	(0x10)	/* FB_AD20 */
+#define MCF_GPIO_PODR_FBADMH_PODR5	(0x20)	/* FB_AD21 */
+#define MCF_GPIO_PODR_FBADMH_PODR6	(0x40)	/* FB_AD22 */
+#define MCF_GPIO_PODR_FBADMH_PODR7	(0x80)	/* FB_AD23 */
+
+/* Bit definitions and macros for PODR_FBADML */
+#define MCF_GPIO_PODR_FBADML_PODR0	(0x01)	/* FB_AD8 */
+#define MCF_GPIO_PODR_FBADML_PODR1	(0x02)	/* FB_AD9 */
+#define MCF_GPIO_PODR_FBADML_PODR2	(0x04)	/* FB_AD10 */
+#define MCF_GPIO_PODR_FBADML_PODR3	(0x08)	/* FB_AD11 */
+#define MCF_GPIO_PODR_FBADML_PODR4	(0x10)	/* FB_AD12 */
+#define MCF_GPIO_PODR_FBADML_PODR5	(0x20)	/* FB_AD13 */
+#define MCF_GPIO_PODR_FBADML_PODR6	(0x40)	/* FB_AD14 */
+#define MCF_GPIO_PODR_FBADML_PODR7	(0x80)	/* FB_AD15 */
+
+/* Bit definitions and macros for PODR_FBADL */
+#define MCF_GPIO_PODR_FBADL_PODR0	(0x01)	/* FB_AD0 */
+#define MCF_GPIO_PODR_FBADL_PODR1	(0x02)	/* FB_AD1 */
+#define MCF_GPIO_PODR_FBADL_PODR2	(0x04)	/* FB_AD2 */
+#define MCF_GPIO_PODR_FBADL_PODR3	(0x08)	/* FB_AD3 */
+#define MCF_GPIO_PODR_FBADL_PODR4	(0x10)	/* FB_AD4 */
+#define MCF_GPIO_PODR_FBADL_PODR5	(0x20)	/* FB_AD5 */
+#define MCF_GPIO_PODR_FBADL_PODR6	(0x40)	/* FB_AD6 */
+#define MCF_GPIO_PODR_FBADL_PODR7	(0x80)	/* FB_AD7 */
+
+/* Bit definitions and macros for PDDR_FEC0H */
+#define MCF_GPIO_PDDR_FEC0H_PDDR0	(0x01)	/* FEC0_CRS / ULPI_DATA6 */
+#define MCF_GPIO_PDDR_FEC0H_PDDR1	(0x02)	/* FEC0_RXD0 / FEC0_RMII_RXD0 */
+#define MCF_GPIO_PDDR_FEC0H_PDDR2	(0x04)	/* FEC0_RXDV/FEC0_RMII_CRS_DV */
+#define MCF_GPIO_PDDR_FEC0H_PDDR3	(0x08)	/* FEC0_RXCLK / ULPI_DATA1 */
+#define MCF_GPIO_PDDR_FEC0H_PDDR4	(0x10)	/* FEC0_COL / ULPI_DATA7 */
+#define MCF_GPIO_PDDR_FEC0H_PDDR5	(0x20)	/* FEC0_TXD0 / FEC0_RMII_TXD0 */
+#define MCF_GPIO_PDDR_FEC0H_PDDR6	(0x40)	/* FEC0_TXEN / FEC0_RMII_TXEN */
+#define MCF_GPIO_PDDR_FEC0H_PDDR7	(0x80)	/* FEC0_TXCLK / FEC0_RMII_REF_CLK */
+
+/* Bit definitions and macros for PDDR_FEC0L */
+#define MCF_GPIO_PDDR_FEC0L_PDDR0	(0x01)	/* FEC0_RXER / FEC0_RMII_RXER */
+#define MCF_GPIO_PDDR_FEC0L_PDDR1	(0x02)	/* FEC0_RXD1 / FEC0_RMII_RXD1 */
+#define MCF_GPIO_PDDR_FEC0L_PDDR2	(0x04)	/* FEC0_RXD2 / ULPI_DATA4 */
+#define MCF_GPIO_PDDR_FEC0L_PDDR3	(0x08)	/* FEC0_RXD3 / ULPI_DATA5 */
+#define MCF_GPIO_PDDR_FEC0L_PDDR4	(0x10)	/* FEC0_TXER / ULPI_DATA0 */
+#define MCF_GPIO_PDDR_FEC0L_PDDR5	(0x20)	/* FEC0_TXD1 / FEC0_RMII_TXD1 */
+#define MCF_GPIO_PDDR_FEC0L_PDDR6	(0x40)	/* FEC0_TXD2 / ULPI_DATA2 */
+#define MCF_GPIO_PDDR_FEC0L_PDDR7	(0x80)	/* FEC0_TXD3 / ULPI_DATA3 */
+
+/* Bit definitions and macros for PDDR_SSI */
+#define MCF_GPIO_PDDR_SSI_PDDR0		(0x01)	/* SSI_TXD / U1TXD */
+#define MCF_GPIO_PDDR_SSI_PDDR1		(0x02)	/* SSI_RXD / U1RXD */
+#define MCF_GPIO_PDDR_SSI_PDDR2		(0x04)	/* SSI_FS / U1RTS */
+#define MCF_GPIO_PDDR_SSI_PDDR3		(0x08)	/* SSI_BCLK / U1CTS */
+#define MCF_GPIO_PDDR_SSI_PDDR4		(0x10)	/* SSI_MCLK */
+
+/* Bit definitions and macros for PDDR_FBCTL */
+#define MCF_GPIO_PDDR_FBCTL_PDDR0	(0x01)	/* FB_TS / FB_ALE / FB_TBST */
+#define MCF_GPIO_PDDR_FBCTL_PDDR1	(0x02)	/* FB_RW */
+#define MCF_GPIO_PDDR_FBCTL_PDDR2	(0x04)	/* FB_TA */
+#define MCF_GPIO_PDDR_FBCTL_PDDR3	(0x08)	/* FB_OE */
+
+/* Bit definitions and macros for PDDR_BE */
+#define MCF_GPIO_PDDR_BE_PDDR0		(0x01)	/* FB_BE/BWE0 / FB_SIZ0 */
+#define MCF_GPIO_PDDR_BE_PDDR1		(0x02)	/* FB_BE/BWE1 / FB_SIZ1 */
+#define MCF_GPIO_PDDR_BE_PDDR2		(0x04)	/* FB_BE/BWE2 / FB_SIZ2 */
+#define MCF_GPIO_PDDR_BE_PDDR3		(0x08)	/* FB_BE/BWE3 / FB_SIZ3 */
+
+/* Bit definitions and macros for PDDR_CS */
+#define MCF_GPIO_PDDR_CS_PDDR1		(0x02)	/* FB_CS1 */
+#define MCF_GPIO_PDDR_CS_PDDR2		(0x04)	/* FB_CS2 */
+#define MCF_GPIO_PDDR_CS_PDDR3		(0x08)	/* FB_CS3 */
+
+/* Bit definitions and macros for PDDR_DMA */
+#define MCF_GPIO_PDDR_DMA_PDDR0		(0x01)	/* DREQ0 */
+#define MCF_GPIO_PDDR_DMA_PDDR1		(0x02)	/* DACK0 / DSPI_PCS3 */
+#define MCF_GPIO_PDDR_DMA_PDDR2		(0x04)	/* DREQ1 / USB_CLKIN */
+#define MCF_GPIO_PDDR_DMA_PDDR3		(0x08)	/* DACK1 / ULPI_DIR */
+
+/* Bit definitions and macros for PDDR_FECI2C */
+#define MCF_GPIO_PDDR_FECI2C_PDDR0	(0x01)	/* I2C_SDA / U2RXD */
+#define MCF_GPIO_PDDR_FECI2C_PDDR1	(0x02)	/* I2C_SCL / U2TXD */
+#define MCF_GPIO_PDDR_FECI2C_PDDR2	(0x04)	/* FEC0_MDIO */
+#define MCF_GPIO_PDDR_FECI2C_PDDR3	(0x08)	/* FEC0_MDC */
+#define MCF_GPIO_PDDR_FECI2C_PDDR4	(0x10)	/* FEC1_MDIO / ATA_DIOW */
+#define MCF_GPIO_PDDR_FECI2C_PDDR5	(0x20)	/* FEC1_MDC / ATA_DIOR */
+
+/* Bit definitions and macros for PDDR_UART */
+#define MCF_GPIO_PDDR_UART_PDDR0	(0x01)	/* U1TXD */
+#define MCF_GPIO_PDDR_UART_PDDR1	(0x02)	/* U1RXD */
+#define MCF_GPIO_PDDR_UART_PDDR2	(0x04)	/* U1RTS */
+#define MCF_GPIO_PDDR_UART_PDDR3	(0x08)	/* U0CTS */
+#define MCF_GPIO_PDDR_UART_PDDR4	(0x10)	/* U1TXD */
+#define MCF_GPIO_PDDR_UART_PDDR5	(0x20)	/* U1RXD */
+#define MCF_GPIO_PDDR_UART_PDDR6	(0x40)	/* U1RTS */
+#define MCF_GPIO_PDDR_UART_PDDR7	(0x80)	/* U1CTS */
+
+/* Bit definitions and macros for PDDR_DSPI */
+#define MCF_GPIO_PDDR_DSPI_PDDR0	(0x01)	/* DSPI_SOUT / SBF_DO */
+#define MCF_GPIO_PDDR_DSPI_PDDR1	(0x02)	/* DSPI_SIN / SBF_DI */
+#define MCF_GPIO_PDDR_DSPI_PDDR2	(0x04)	/* DSPI_SCK / SBF_CK */
+#define MCF_GPIO_PDDR_DSPI_PDDR3	(0x08)	/* DSPI_PCS0/SS */
+#define MCF_GPIO_PDDR_DSPI_PDDR4	(0x10)	/* DSPI_PCS1 / SBF_CS */
+#define MCF_GPIO_PDDR_DSPI_PDDR5	(0x20)	/* DSPI_PCS2 */
+#define MCF_GPIO_PDDR_DSPI_PDDR6	(0x40)	/* DSPI_PCS5/SS */
+
+/* Bit definitions and macros for PDDR_TIMER */
+#define MCF_GPIO_PDDR_TIMER_PDDR0	(0x01)	/* T0IN / T0OUT / U2RTS */
+#define MCF_GPIO_PDDR_TIMER_PDDR1	(0x02)	/* T1IN / T1OUT / U2CTS */
+#define MCF_GPIO_PDDR_TIMER_PDDR2	(0x04)	/* T2IN / T2OUT / U2TXD */
+#define MCF_GPIO_PDDR_TIMER_PDDR3	(0x08)	/* T3IN / T3OUT / U2RXD */
+
+/* Bit definitions and macros for PDDR_PCI */
+#define MCF_GPIO_PDDR_PCI_PDDR0		(0x01)	/* PCI_REQ0/PCI_EXTGNT */
+#define MCF_GPIO_PDDR_PCI_PDDR1		(0x02)	/* PCI_REQ1 */
+#define MCF_GPIO_PDDR_PCI_PDDR2		(0x04)	/* PCI_REQ2 */
+#define MCF_GPIO_PDDR_PCI_PDDR3		(0x08)	/* PCI_REQ3 / ATA_INTR */
+#define MCF_GPIO_PDDR_PCI_PDDR4		(0x10)	/* PCI_GNT0/PCI_EXTREQ */
+#define MCF_GPIO_PDDR_PCI_PDDR5		(0x20)	/* PCI_GNT1 /  */
+#define MCF_GPIO_PDDR_PCI_PDDR6		(0x40)	/* PCI_GNT2 /  */
+#define MCF_GPIO_PDDR_PCI_PDDR7		(0x80)	/* PCI_GNT3 / ATA_DMACK */
+
+/* Bit definitions and macros for PDDR_USB */
+#define MCF_GPIO_PDDR_USB_PDDR0		(0x01)	/* USB_VBUS_OC / ULPI_STP */
+#define MCF_GPIO_PDDR_USB_PDDR1		(0x02)	/* USB_VBUS_EN / USB_PULLUP / ULPI_NXT */
+
+/* Bit definitions and macros for PDDR_ATAH */
+#define MCF_GPIO_PDDR_ATAH_PDDR0	(0x01)	/* ATA_DA0 */
+#define MCF_GPIO_PDDR_ATAH_PDDR1	(0x02)	/* ATA_DA1 */
+#define MCF_GPIO_PDDR_ATAH_PDDR2	(0x04)	/* ATA_DA2 */
+#define MCF_GPIO_PDDR_ATAH_PDDR3	(0x08)	/* ATA_CS0 */
+#define MCF_GPIO_PDDR_ATAH_PDDR4	(0x10)	/* ATA_CS1 */
+#define MCF_GPIO_PDDR_ATAH_PDDR5	(0x20)	/* ATA_BUFFER_EN */
+
+/* Bit definitions and macros for PDDR_ATAL */
+#define MCF_GPIO_PDDR_ATAL_PDDR0	(0x01)	/* ATA_IORDY */
+#define MCF_GPIO_PDDR_ATAL_PDDR1	(0x02)	/* ATA_DMARQ */
+#define MCF_GPIO_PDDR_ATAL_PDDR2	(0x04)	/* ATA_RESET */
+
+/* Bit definitions and macros for PDDR_FEC1H */
+#define MCF_GPIO_PDDR_FEC1H_PDDR0	(0x01)	/* FEC1_CRS / ATA_DATA6 */
+#define MCF_GPIO_PDDR_FEC1H_PDDR1	(0x02)	/* FEC1_RXD0 / FEC1_RMII_RXD0 / ATA_DATA13 */
+#define MCF_GPIO_PDDR_FEC1H_PDDR2	(0x04)	/* FEC1_RXDV / FEC1_RMII_CRS_DV / ATA_DATA15 */
+#define MCF_GPIO_PDDR_FEC1H_PDDR3	(0x08)	/* FEC1_RXCLK / ATA_DATA5 */
+#define MCF_GPIO_PDDR_FEC1H_PDDR4	(0x10)	/* FEC1_COL / ATA_DATA7 */
+#define MCF_GPIO_PDDR_FEC1H_PDDR5	(0x20)	/* FEC1_TXD0 / FEC1_RMII_TXD0 / ATA_DATA9 */
+#define MCF_GPIO_PDDR_FEC1H_PDDR6	(0x40)	/* FEC1_TXEN / FEC1_RMII_TXEN / ATA_DATA8 */
+#define MCF_GPIO_PDDR_FEC1H_PDDR7	(0x80)	/* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */
+
+/* Bit definitions and macros for PDDR_FEC1L */
+#define MCF_GPIO_PDDR_FEC1L_PDDR0	(0x01)	/* FEC1_RXER / FEC1_RMII_RXER / ATA_DATA12 */
+#define MCF_GPIO_PDDR_FEC1L_PDDR1	(0x02)	/* FEC1_RXD1 / FEC1_RMII_RXD1 / ATA_DATA14 */
+#define MCF_GPIO_PDDR_FEC1L_PDDR2	(0x04)	/* FEC1_RXD2 / ATA_DATA3 */
+#define MCF_GPIO_PDDR_FEC1L_PDDR3	(0x08)	/* FEC1_RXD3 / ATA_DATA4 */
+#define MCF_GPIO_PDDR_FEC1L_PDDR4	(0x10)	/* FEC1_TXER / ATA_DATA0 */
+#define MCF_GPIO_PDDR_FEC1L_PDDR5	(0x20)	/* FEC1_TXD1 / FEC1_RMII_TXD1 / ATA_DATA10 */
+#define MCF_GPIO_PDDR_FEC1L_PDDR6	(0x40)	/* FEC1_TXD2 / ATA_DATA1 */
+#define MCF_GPIO_PDDR_FEC1L_PDDR7	(0x80)	/* FEC1_TXD3 / ATA_DATA2 */
+
+/* Bit definitions and macros for PDDR_FBADH */
+#define MCF_GPIO_PDDR_FBADH_PDDR0	(0x01)	/* FB_AD24 */
+#define MCF_GPIO_PDDR_FBADH_PDDR1	(0x02)	/* FB_AD25 */
+#define MCF_GPIO_PDDR_FBADH_PDDR2	(0x04)	/* FB_AD26 */
+#define MCF_GPIO_PDDR_FBADH_PDDR3	(0x08)	/* FB_AD27 */
+#define MCF_GPIO_PDDR_FBADH_PDDR4	(0x10)	/* FB_AD28 */
+#define MCF_GPIO_PDDR_FBADH_PDDR5	(0x20)	/* FB_AD29 */
+#define MCF_GPIO_PDDR_FBADH_PDDR6	(0x40)	/* FB_AD30 */
+#define MCF_GPIO_PDDR_FBADH_PDDR7	(0x80)	/* FB_AD31 */
+
+/* Bit definitions and macros for PDDR_FBADMH */
+#define MCF_GPIO_PDDR_FBADMH_PDDR0	(0x01)	/* FB_AD16 */
+#define MCF_GPIO_PDDR_FBADMH_PDDR1	(0x02)	/* FB_AD17 */
+#define MCF_GPIO_PDDR_FBADMH_PDDR2	(0x04)	/* FB_AD18 */
+#define MCF_GPIO_PDDR_FBADMH_PDDR3	(0x08)	/* FB_AD19 */
+#define MCF_GPIO_PDDR_FBADMH_PDDR4	(0x10)	/* FB_AD20 */
+#define MCF_GPIO_PDDR_FBADMH_PDDR5	(0x20)	/* FB_AD21 */
+#define MCF_GPIO_PDDR_FBADMH_PDDR6	(0x40)	/* FB_AD22 */
+#define MCF_GPIO_PDDR_FBADMH_PDDR7	(0x80)	/* FB_AD23 */
+
+/* Bit definitions and macros for PDDR_FBADML */
+#define MCF_GPIO_PDDR_FBADML_PDDR0	(0x01)	/* FB_AD8 */
+#define MCF_GPIO_PDDR_FBADML_PDDR1	(0x02)	/* FB_AD9 */
+#define MCF_GPIO_PDDR_FBADML_PDDR2	(0x04)	/* FB_AD10 */
+#define MCF_GPIO_PDDR_FBADML_PDDR3	(0x08)	/* FB_AD11 */
+#define MCF_GPIO_PDDR_FBADML_PDDR4	(0x10)	/* FB_AD12 */
+#define MCF_GPIO_PDDR_FBADML_PDDR5	(0x20)	/* FB_AD13 */
+#define MCF_GPIO_PDDR_FBADML_PDDR6	(0x40)	/* FB_AD14 */
+#define MCF_GPIO_PDDR_FBADML_PDDR7	(0x80)	/* FB_AD15 */
+
+/* Bit definitions and macros for PDDR_FBADL */
+#define MCF_GPIO_PDDR_FBADL_PDDR0	(0x01)	/* FB_AD0 */
+#define MCF_GPIO_PDDR_FBADL_PDDR1	(0x02)	/* FB_AD1 */
+#define MCF_GPIO_PDDR_FBADL_PDDR2	(0x04)	/* FB_AD2 */
+#define MCF_GPIO_PDDR_FBADL_PDDR3	(0x08)	/* FB_AD3 */
+#define MCF_GPIO_PDDR_FBADL_PDDR4	(0x10)	/* FB_AD4 */
+#define MCF_GPIO_PDDR_FBADL_PDDR5	(0x20)	/* FB_AD5 */
+#define MCF_GPIO_PDDR_FBADL_PDDR6	(0x40)	/* FB_AD6 */
+#define MCF_GPIO_PDDR_FBADL_PDDR7	(0x80)	/* FB_AD7 */
+
+/* Bit definitions and macros for PPDSDR_FEC0H */
+#define MCF_GPIO_PPDSDR_FEC0H_PPDR0	(0x01)	/* FEC0_CRS / ULPI_DATA6 */
+#define MCF_GPIO_PPDSDR_FEC0H_PPDR1	(0x02)	/* FEC0_RXD0 / FEC0_RMII_RXD0 */
+#define MCF_GPIO_PPDSDR_FEC0H_PPDR2	(0x04)	/* FEC0_RXDV / FEC0_RMII_CRS_DV */
+#define MCF_GPIO_PPDSDR_FEC0H_PPDR3	(0x08)	/* FEC0_RXCLK / ULPI_DATA1 */
+#define MCF_GPIO_PPDSDR_FEC0H_PPDR4	(0x10)	/* FEC0_COL / ULPI_DATA7 */
+#define MCF_GPIO_PPDSDR_FEC0H_PPDR5	(0x20)	/* FEC0_TXD0 / FEC0_RMII_TXD0 */
+#define MCF_GPIO_PPDSDR_FEC0H_PPDR6	(0x40)	/* FEC0_TXEN / FEC0_RMII_TXEN */
+#define MCF_GPIO_PPDSDR_FEC0H_PPDR7	(0x80)	/* FEC0_TXCLK / FEC0_RMII_REF_CLK */
+
+/* Bit definitions and macros for PPDSDR_FEC0L */
+#define MCF_GPIO_PPDSDR_FEC0L_PCLRR0	(0x01)	/* FEC0_RXER / FEC0_RMII_RXER */
+#define MCF_GPIO_PPDSDR_FEC0L_PCLRR1	(0x02)	/* FEC0_RXD1 / FEC0_RMII_RXD1 */
+#define MCF_GPIO_PPDSDR_FEC0L_PCLRR2	(0x04)	/* FEC0_RXD2 / ULPI_DATA4 */
+#define MCF_GPIO_PPDSDR_FEC0L_PCLRR3	(0x08)	/* FEC0_RXD3 / ULPI_DATA5 */
+#define MCF_GPIO_PPDSDR_FEC0L_PCLRR4	(0x10)	/* FEC0_TXER / ULPI_DATA0 */
+#define MCF_GPIO_PPDSDR_FEC0L_PCLRR5	(0x20)	/* FEC0_TXD1 / FEC0_RMII_TXD1 */
+#define MCF_GPIO_PPDSDR_FEC0L_PCLRR6	(0x40)	/* FEC0_TXD2 / ULPI_DATA2 */
+#define MCF_GPIO_PPDSDR_FEC0L_PCLRR7	(0x80)	/* FEC0_TXD3 / ULPI_DATA3 */
+
+/* Bit definitions and macros for PPDSDR_SSI */
+#define MCF_GPIO_PPDSDR_SSI_PPDR0	(0x01)	/* SSI_TXD / U1TXD */
+#define MCF_GPIO_PPDSDR_SSI_PPDR1	(0x02)	/* SSI_RXD / U1RXD */
+#define MCF_GPIO_PPDSDR_SSI_PPDR2	(0x04)	/* SSI_FS / U1RTS */
+#define MCF_GPIO_PPDSDR_SSI_PPDR3	(0x08)	/* SSI_BCLK / U1CTS */
+#define MCF_GPIO_PPDSDR_SSI_PPDR4	(0x10)	/* SSI_MCLK */
+
+/* Bit definitions and macros for PPDSDR_FBCTL */
+#define MCF_GPIO_PPDSDR_FBCTL_PPDR0	(0x01)	/* FB_TS / FB_ALE / FB_TBST */
+#define MCF_GPIO_PPDSDR_FBCTL_PPDR1	(0x02)	/* FB_RW */
+#define MCF_GPIO_PPDSDR_FBCTL_PPDR2	(0x04)	/* FB_TA */
+#define MCF_GPIO_PPDSDR_FBCTL_PPDR3	(0x08)	/* FB_OE */
+
+/* Bit definitions and macros for PPDSDR_BE */
+#define MCF_GPIO_PPDSDR_BE_PPDR0	(0x01)	/* FB_BE/BWE0 / FB_SIZ0 */
+#define MCF_GPIO_PPDSDR_BE_PPDR1	(0x02)	/* FB_BE/BWE1 / FB_SIZ1 */
+#define MCF_GPIO_PPDSDR_BE_PPDR2	(0x04)	/* FB_BE/BWE2 / FB_SIZ2 */
+#define MCF_GPIO_PPDSDR_BE_PPDR3	(0x08)	/* FB_BE/BWE3 / FB_SIZ3 */
+
+/* Bit definitions and macros for PPDSDR_CS */
+#define MCF_GPIO_PPDSDR_CS_PPDR1	(0x02)	/* FB_CS1 */
+#define MCF_GPIO_PPDSDR_CS_PPDR2	(0x04)	/* FB_CS2 */
+#define MCF_GPIO_PPDSDR_CS_PPDR3	(0x08)	/* FB_CS3 */
+
+/* Bit definitions and macros for PPDSDR_DMA */
+#define MCF_GPIO_PPDSDR_DMA_PPDR0	(0x01)	/* DREQ0 */
+#define MCF_GPIO_PPDSDR_DMA_PPDR1	(0x02)	/* DACK0 / DSPI_PCS3 */
+#define MCF_GPIO_PPDSDR_DMA_PPDR2	(0x04)	/* DREQ1 / USB_CLKIN */
+#define MCF_GPIO_PPDSDR_DMA_PPDR3	(0x08)	/* DACK1 / ULPI_DIR */
+
+/* Bit definitions and macros for PPDSDR_FECI2C */
+#define MCF_GPIO_PPDSDR_FECI2C_PPDR0	(0x01)	/* I2C_SDA / U2RXD */
+#define MCF_GPIO_PPDSDR_FECI2C_PPDR1	(0x02)	/* I2C_SCL / U2TXD */
+#define MCF_GPIO_PPDSDR_FECI2C_PPDR2	(0x04)	/* FEC0_MDIO */
+#define MCF_GPIO_PPDSDR_FECI2C_PPDR3	(0x08)	/* FEC0_MDC */
+#define MCF_GPIO_PPDSDR_FECI2C_PPDR4	(0x10)	/* FEC1_MDIO / ATA_DIOW */
+#define MCF_GPIO_PPDSDR_FECI2C_PPDR5	(0x20)	/* FEC1_MDC / ATA_DIOR */
+
+/* Bit definitions and macros for PPDSDR_UART */
+#define MCF_GPIO_PPDSDR_UART_PPDR0	(0x01)	/* U1TXD */
+#define MCF_GPIO_PPDSDR_UART_PPDR1	(0x02)	/* U1RXD */
+#define MCF_GPIO_PPDSDR_UART_PPDR2	(0x04)	/* U1RTS */
+#define MCF_GPIO_PPDSDR_UART_PPDR3	(0x08)	/* U0CTS */
+#define MCF_GPIO_PPDSDR_UART_PPDR4	(0x10)	/* U1TXD */
+#define MCF_GPIO_PPDSDR_UART_PPDR5	(0x20)	/* U1RXD */
+#define MCF_GPIO_PPDSDR_UART_PPDR6	(0x40)	/* U1RTS */
+#define MCF_GPIO_PPDSDR_UART_PPDR7	(0x80)	/* U1CTS */
+
+/* Bit definitions and macros for PPDSDR_DSPI */
+#define MCF_GPIO_PPDSDR_DSPI_PPDR0	(0x01)	/* DSPI_SOUT / SBF_DO */
+#define MCF_GPIO_PPDSDR_DSPI_PPDR1	(0x02)	/* DSPI_SIN / SBF_DI */
+#define MCF_GPIO_PPDSDR_DSPI_PPDR2	(0x04)	/* DSPI_SCK / SBF_CK */
+#define MCF_GPIO_PPDSDR_DSPI_PPDR3	(0x08)	/* DSPI_PCS0/SS */
+#define MCF_GPIO_PPDSDR_DSPI_PPDR4	(0x10)	/* DSPI_PCS1 / SBF_CS */
+#define MCF_GPIO_PPDSDR_DSPI_PPDR5	(0x20)	/* DSPI_PCS2 */
+#define MCF_GPIO_PPDSDR_DSPI_PPDR6	(0x40)	/* DSPI_PCS5/SS */
+
+/* Bit definitions and macros for PPDSDR_TIMER */
+#define MCF_GPIO_PPDSDR_TIMER_PPDR0	(0x01)	/* T0IN / T0OUT / U2RTS */
+#define MCF_GPIO_PPDSDR_TIMER_PPDR1	(0x02)	/* T1IN / T1OUT / U2CTS */
+#define MCF_GPIO_PPDSDR_TIMER_PPDR2	(0x04)	/* T2IN / T2OUT / U2TXD */
+#define MCF_GPIO_PPDSDR_TIMER_PPDR3	(0x08)	/* T3IN / T3OUT / U2RXD */
+
+/* Bit definitions and macros for PPDSDR_PCI */
+#define MCF_GPIO_PPDSDR_PCI_PPDR0	(0x01)	/* PCI_REQ0/PCI_EXTGNT */
+#define MCF_GPIO_PPDSDR_PCI_PPDR1	(0x02)	/* PCI_REQ1 */
+#define MCF_GPIO_PPDSDR_PCI_PPDR2	(0x04)	/* PCI_REQ2 */
+#define MCF_GPIO_PPDSDR_PCI_PPDR3	(0x08)	/* PCI_REQ3 / ATA_INTR */
+#define MCF_GPIO_PPDSDR_PCI_PPDR4	(0x10)	/* PCI_GNT0/PCI_EXTREQ */
+#define MCF_GPIO_PPDSDR_PCI_PPDR5	(0x20)	/* PCI_GNT1 /  */
+#define MCF_GPIO_PPDSDR_PCI_PPDR6	(0x40)	/* PCI_GNT2 /  */
+#define MCF_GPIO_PPDSDR_PCI_PPDR7	(0x80)	/* PCI_GNT3 / ATA_DMACK */
+
+/* Bit definitions and macros for PPDSDR_USB */
+#define MCF_GPIO_PPDSDR_USB_PPDR0	(0x01)	/* USB_VBUS_OC / ULPI_STP */
+#define MCF_GPIO_PPDSDR_USB_PPDR1	(0x02)	/* USB_VBUS_EN / USB_PULLUP / ULPI_NXT */
+
+/* Bit definitions and macros for PPDSDR_ATAH */
+#define MCF_GPIO_PPDSDR_ATAH_PPDR0	(0x01)	/* ATA_DA0 */
+#define MCF_GPIO_PPDSDR_ATAH_PPDR1	(0x02)	/* ATA_DA1 */
+#define MCF_GPIO_PPDSDR_ATAH_PPDR2	(0x04)	/* ATA_DA2 */
+#define MCF_GPIO_PPDSDR_ATAH_PPDR3	(0x08)	/* ATA_CS0 */
+#define MCF_GPIO_PPDSDR_ATAH_PPDR4	(0x10)	/* ATA_CS1 */
+#define MCF_GPIO_PPDSDR_ATAH_PPDR5	(0x20)	/* ATA_BUFFER_EN */
+
+/* Bit definitions and macros for PPDSDR_ATAL */
+#define MCF_GPIO_PPDSDR_ATAL_PPDR0	(0x01)	/* ATA_IORDY */
+#define MCF_GPIO_PPDSDR_ATAL_PPDR1	(0x02)	/* ATA_DMARQ */
+#define MCF_GPIO_PPDSDR_ATAL_PPDR2	(0x04)	/* ATA_RESET */
+
+/* Bit definitions and macros for PPDSDR_FEC1H */
+#define MCF_GPIO_PPDSDR_FEC1H_PPDR0	(0x01)	/* FEC1_CRS / ATA_DATA6 */
+#define MCF_GPIO_PPDSDR_FEC1H_PPDR1	(0x02)	/* FEC1_RXD0 / FEC1_RMII_RXD0 / ATA_DATA13 */
+#define MCF_GPIO_PPDSDR_FEC1H_PPDR2	(0x04)	/* FEC1_RXDV / FEC1_RMII_CRS_DV / ATA_DATA15 */
+#define MCF_GPIO_PPDSDR_FEC1H_PPDR3	(0x08)	/* FEC1_RXCLK / ATA_DATA5 */
+#define MCF_GPIO_PPDSDR_FEC1H_PPDR4	(0x10)	/* FEC1_COL / ATA_DATA7 */
+#define MCF_GPIO_PPDSDR_FEC1H_PPDR5	(0x20)	/* FEC1_TXD0 / FEC1_RMII_TXD0 / ATA_DATA9 */
+#define MCF_GPIO_PPDSDR_FEC1H_PPDR6	(0x40)	/* FEC1_TXEN / FEC1_RMII_TXEN / ATA_DATA8 */
+#define MCF_GPIO_PPDSDR_FEC1H_PPDR7	(0x80)	/* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */
+
+/* Bit definitions and macros for PPDSDR_FEC1L */
+#define MCF_GPIO_PPDSDR_FEC1L_PPDR0	(0x01)	/* FEC1_RXER / FEC1_RMII_RXER / ATA_DATA12 */
+#define MCF_GPIO_PPDSDR_FEC1L_PPDR1	(0x02)	/* FEC1_RXD1 / FEC1_RMII_RXD1 / ATA_DATA14 */
+#define MCF_GPIO_PPDSDR_FEC1L_PPDR2	(0x04)	/* FEC1_RXD2 / ATA_DATA3 */
+#define MCF_GPIO_PPDSDR_FEC1L_PPDR3	(0x08)	/* FEC1_RXD3 / ATA_DATA4 */
+#define MCF_GPIO_PPDSDR_FEC1L_PPDR4	(0x10)	/* FEC1_TXER / ATA_DATA0 */
+#define MCF_GPIO_PPDSDR_FEC1L_PPDR5	(0x20)	/* FEC1_TXD1 / FEC1_RMII_TXD1 / ATA_DATA10 */
+#define MCF_GPIO_PPDSDR_FEC1L_PPDR6	(0x40)	/* FEC1_TXD2 / ATA_DATA1 */
+#define MCF_GPIO_PPDSDR_FEC1L_PPDR7	(0x80)	/* FEC1_TXD3 / ATA_DATA2 */
+
+/* Bit definitions and macros for PPDSDR_FBADH */
+#define MCF_GPIO_PPDSDR_FBADH_PPDR0	(0x01)	/* FB_AD24 */
+#define MCF_GPIO_PPDSDR_FBADH_PPDR1	(0x02)	/* FB_AD25 */
+#define MCF_GPIO_PPDSDR_FBADH_PPDR2	(0x04)	/* FB_AD26 */
+#define MCF_GPIO_PPDSDR_FBADH_PPDR3	(0x08)	/* FB_AD27 */
+#define MCF_GPIO_PPDSDR_FBADH_PPDR4	(0x10)	/* FB_AD28 */
+#define MCF_GPIO_PPDSDR_FBADH_PPDR5	(0x20)	/* FB_AD29 */
+#define MCF_GPIO_PPDSDR_FBADH_PPDR6	(0x40)	/* FB_AD30 */
+#define MCF_GPIO_PPDSDR_FBADH_PPDR7	(0x80)	/* FB_AD31 */
+
+/* Bit definitions and macros for PPDSDR_FBADMH */
+#define MCF_GPIO_PPDSDR_FBADMH_PPDR0	(0x01)	/* FB_AD16 */
+#define MCF_GPIO_PPDSDR_FBADMH_PPDR1	(0x02)	/* FB_AD17 */
+#define MCF_GPIO_PPDSDR_FBADMH_PPDR2	(0x04)	/* FB_AD18 */
+#define MCF_GPIO_PPDSDR_FBADMH_PPDR3	(0x08)	/* FB_AD19 */
+#define MCF_GPIO_PPDSDR_FBADMH_PPDR4	(0x10)	/* FB_AD20 */
+#define MCF_GPIO_PPDSDR_FBADMH_PPDR5	(0x20)	/* FB_AD21 */
+#define MCF_GPIO_PPDSDR_FBADMH_PPDR6	(0x40)	/* FB_AD22 */
+#define MCF_GPIO_PPDSDR_FBADMH_PPDR7	(0x80)	/* FB_AD23 */
+
+/* Bit definitions and macros for PPDSDR_FBADML */
+#define MCF_GPIO_PPDSDR_FBADML_PPDR0	(0x01)	/* FB_AD8 */
+#define MCF_GPIO_PPDSDR_FBADML_PPDR1	(0x02)	/* FB_AD9 */
+#define MCF_GPIO_PPDSDR_FBADML_PPDR2	(0x04)	/* FB_AD10 */
+#define MCF_GPIO_PPDSDR_FBADML_PPDR3	(0x08)	/* FB_AD11 */
+#define MCF_GPIO_PPDSDR_FBADML_PPDR4	(0x10)	/* FB_AD12 */
+#define MCF_GPIO_PPDSDR_FBADML_PPDR5	(0x20)	/* FB_AD13 */
+#define MCF_GPIO_PPDSDR_FBADML_PPDR6	(0x40)	/* FB_AD14 */
+#define MCF_GPIO_PPDSDR_FBADML_PPDR7	(0x80)	/* FB_AD15 */
+
+/* Bit definitions and macros for PPDSDR_FBADL */
+#define MCF_GPIO_PPDSDR_FBADL_PPDR0	(0x01)	/* FB_AD0 */
+#define MCF_GPIO_PPDSDR_FBADL_PPDR1	(0x02)	/* FB_AD1 */
+#define MCF_GPIO_PPDSDR_FBADL_PPDR2	(0x04)	/* FB_AD2 */
+#define MCF_GPIO_PPDSDR_FBADL_PPDR3	(0x08)	/* FB_AD3 */
+#define MCF_GPIO_PPDSDR_FBADL_PPDR4	(0x10)	/* FB_AD4 */
+#define MCF_GPIO_PPDSDR_FBADL_PPDR5	(0x20)	/* FB_AD5 */
+#define MCF_GPIO_PPDSDR_FBADL_PPDR6	(0x40)	/* FB_AD6 */
+#define MCF_GPIO_PPDSDR_FBADL_PPDR7	(0x80)	/* FB_AD7 */
+
+/* Bit definitions and macros for PCLRR_FEC0H */
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR0	(0x01)	/* FEC0_CRS / ULPI_DATA6 */
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR1	(0x02)	/* FEC0_RXD0 / FEC0_RMII_RXD0 */
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR2	(0x04)	/* FEC0_RXDV/FEC0_RMII_CRS_DV */
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR3	(0x08)	/* FEC0_RXCLK / ULPI_DATA1 */
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR4	(0x10)	/* FEC0_COL / ULPI_DATA7 */
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR5	(0x20)	/* FEC0_TXD0 / FEC0_RMII_TXD0 */
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR6	(0x40)	/* FEC0_TXEN / FEC0_RMII_TXEN */
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR7	(0x80)	/* FEC0_TXCLK / FEC0_RMII_REF_CLK */
+
+/* Bit definitions and macros for PCLRR_FEC0L */
+#define MCF_GPIO_PCLRR_FEC0L_PPDR0	(0x01)	/* FEC0_RXER / FEC0_RMII_RXER */
+#define MCF_GPIO_PCLRR_FEC0L_PPDR1	(0x02)	/* FEC0_RXD1 / FEC0_RMII_RXD1 */
+#define MCF_GPIO_PCLRR_FEC0L_PPDR2	(0x04)	/* FEC0_RXD2 / ULPI_DATA4 */
+#define MCF_GPIO_PCLRR_FEC0L_PPDR3	(0x08)	/* FEC0_RXD3 / ULPI_DATA5 */
+#define MCF_GPIO_PCLRR_FEC0L_PPDR4	(0x10)	/* FEC0_TXER / ULPI_DATA0 */
+#define MCF_GPIO_PCLRR_FEC0L_PPDR5	(0x20)	/* FEC0_TXD1 / FEC0_RMII_TXD1 */
+#define MCF_GPIO_PCLRR_FEC0L_PPDR6	(0x40)	/* FEC0_TXD2 / ULPI_DATA2 */
+#define MCF_GPIO_PCLRR_FEC0L_PPDR7	(0x80)	/* FEC0_TXD3 / ULPI_DATA3 */
+
+/* Bit definitions and macros for PCLRR_SSI */
+#define MCF_GPIO_PCLRR_SSI_PCLRR0	(0x01)	/* SSI_TXD / U1TXD */
+#define MCF_GPIO_PCLRR_SSI_PCLRR1	(0x02)	/* SSI_RXD / U1RXD */
+#define MCF_GPIO_PCLRR_SSI_PCLRR2	(0x04)	/* SSI_FS / U1RTS */
+#define MCF_GPIO_PCLRR_SSI_PCLRR3	(0x08)	/* SSI_BCLK / U1CTS */
+#define MCF_GPIO_PCLRR_SSI_PCLRR4	(0x10)	/* SSI_MCLK */
+
+/* Bit definitions and macros for PCLRR_FBCTL */
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR0	(0x01)	/* FB_TS / FB_ALE / FB_TBST */
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR1	(0x02)	/* FB_RW */
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR2	(0x04)	/* FB_TA */
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR3	(0x08)	/* FB_OE */
+
+/* Bit definitions and macros for PCLRR_BE */
+#define MCF_GPIO_PCLRR_BE_PCLRR0	(0x01)	/* FB_BE/BWE0 / FB_SIZ0 */
+#define MCF_GPIO_PCLRR_BE_PCLRR1	(0x02)	/* FB_BE/BWE1 / FB_SIZ1 */
+#define MCF_GPIO_PCLRR_BE_PCLRR2	(0x04)	/* FB_BE/BWE2 / FB_SIZ2 */
+#define MCF_GPIO_PCLRR_BE_PCLRR3	(0x08)	/* FB_BE/BWE3 / FB_SIZ3 */
+
+/* Bit definitions and macros for PCLRR_CS */
+#define MCF_GPIO_PCLRR_CS_PCLRR1	(0x02)	/* FB_CS1 */
+#define MCF_GPIO_PCLRR_CS_PCLRR2	(0x04)	/* FB_CS2 */
+#define MCF_GPIO_PCLRR_CS_PCLRR3	(0x08)	/* FB_CS3 */
+
+/* Bit definitions and macros for PCLRR_DMA */
+#define MCF_GPIO_PCLRR_DMA_PCLRR0	(0x01)	/* DREQ0 */
+#define MCF_GPIO_PCLRR_DMA_PCLRR1	(0x02)	/* DACK0 / DSPI_PCS3 */
+#define MCF_GPIO_PCLRR_DMA_PCLRR2	(0x04)	/* DREQ1 / USB_CLKIN */
+#define MCF_GPIO_PCLRR_DMA_PCLRR3	(0x08)	/* DACK1 / ULPI_DIR */
+
+/* Bit definitions and macros for PCLRR_FECI2C */
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR0	(0x01)	/* I2C_SDA / U2RXD */
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR1	(0x02)	/* I2C_SCL / U2TXD */
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR2	(0x04)	/* FEC0_MDIO */
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR3	(0x08)	/* FEC0_MDC */
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR4	(0x10)	/* FEC1_MDIO / ATA_DIOW */
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR5	(0x20)	/* FEC1_MDC / ATA_DIOR */
+
+/* Bit definitions and macros for PCLRR_UART */
+#define MCF_GPIO_PCLRR_UART_PCLRR0	(0x01)	/* U1TXD */
+#define MCF_GPIO_PCLRR_UART_PCLRR1	(0x02)	/* U1RXD */
+#define MCF_GPIO_PCLRR_UART_PCLRR2	(0x04)	/* U1RTS */
+#define MCF_GPIO_PCLRR_UART_PCLRR3	(0x08)	/* U0CTS */
+#define MCF_GPIO_PCLRR_UART_PCLRR4	(0x10)	/* U1TXD */
+#define MCF_GPIO_PCLRR_UART_PCLRR5	(0x20)	/* U1RXD */
+#define MCF_GPIO_PCLRR_UART_PCLRR6	(0x40)	/* U1RTS */
+#define MCF_GPIO_PCLRR_UART_PCLRR7	(0x80)	/* U1CTS */
+
+/* Bit definitions and macros for PCLRR_DSPI */
+#define MCF_GPIO_PCLRR_DSPI_PCLRR0	(0x01)	/* DSPI_SOUT / SBF_DO */
+#define MCF_GPIO_PCLRR_DSPI_PCLRR1	(0x02)	/* DSPI_SIN / SBF_DI */
+#define MCF_GPIO_PCLRR_DSPI_PCLRR2	(0x04)	/* DSPI_SCK / SBF_CK */
+#define MCF_GPIO_PCLRR_DSPI_PCLRR3	(0x08)	/* DSPI_PCS0/SS */
+#define MCF_GPIO_PCLRR_DSPI_PCLRR4	(0x10)	/* DSPI_PCS1 / SBF_CS */
+#define MCF_GPIO_PCLRR_DSPI_PCLRR5	(0x20)	/* DSPI_PCS2 */
+#define MCF_GPIO_PCLRR_DSPI_PCLRR6	(0x40)	/* DSPI_PCS5/SS */
+
+/* Bit definitions and macros for PCLRR_TIMER */
+#define MCF_GPIO_PCLRR_TIMER_PCLRR0	(0x01)	/* T0IN / T0OUT / U2RTS */
+#define MCF_GPIO_PCLRR_TIMER_PCLRR1	(0x02)	/* T1IN / T1OUT / U2CTS */
+#define MCF_GPIO_PCLRR_TIMER_PCLRR2	(0x04)	/* T2IN / T2OUT / U2TXD */
+#define MCF_GPIO_PCLRR_TIMER_PCLRR3	(0x08)	/* T3IN / T3OUT / U2RXD */
+
+/* Bit definitions and macros for PCLRR_PCI */
+#define MCF_GPIO_PCLRR_PCI_PCLRR0	(0x01)	/* PCI_REQ0/PCI_EXTGNT */
+#define MCF_GPIO_PCLRR_PCI_PCLRR1	(0x02)	/* PCI_REQ1 */
+#define MCF_GPIO_PCLRR_PCI_PCLRR2	(0x04)	/* PCI_REQ2 */
+#define MCF_GPIO_PCLRR_PCI_PCLRR3	(0x08)	/* PCI_REQ3 / ATA_INTR */
+#define MCF_GPIO_PCLRR_PCI_PCLRR4	(0x10)	/* PCI_GNT0/PCI_EXTREQ */
+#define MCF_GPIO_PCLRR_PCI_PCLRR5	(0x20)	/* PCI_GNT1 /  */
+#define MCF_GPIO_PCLRR_PCI_PCLRR6	(0x40)	/* PCI_GNT2 /  */
+#define MCF_GPIO_PCLRR_PCI_PCLRR7	(0x80)	/* PCI_GNT3 / ATA_DMACK */
+
+/* Bit definitions and macros for PCLRR_USB */
+#define MCF_GPIO_PCLRR_USB_PCLRR0	(0x01)	/* USB_VBUS_OC / ULPI_STP */
+#define MCF_GPIO_PCLRR_USB_PCLRR1	(0x02)	/* USB_VBUS_EN / USB_PULLUP / ULPI_NXT */
+
+/* Bit definitions and macros for PCLRR_ATAH */
+#define MCF_GPIO_PCLRR_ATAH_PCLRR0	(0x01)	/* ATA_DA0 */
+#define MCF_GPIO_PCLRR_ATAH_PCLRR1	(0x02)	/* ATA_DA1 */
+#define MCF_GPIO_PCLRR_ATAH_PCLRR2	(0x04)	/* ATA_DA2 */
+#define MCF_GPIO_PCLRR_ATAH_PCLRR3	(0x08)	/* ATA_CS0 */
+#define MCF_GPIO_PCLRR_ATAH_PCLRR4	(0x10)	/* ATA_CS1 */
+#define MCF_GPIO_PCLRR_ATAH_PCLRR5	(0x20)	/* ATA_BUFFER_EN */
+
+/* Bit definitions and macros for PCLRR_ATAL */
+#define MCF_GPIO_PCLRR_ATAL_PCLRR0	(0x01)	/* ATA_IORDY */
+#define MCF_GPIO_PCLRR_ATAL_PCLRR1	(0x02)	/* ATA_DMARQ */
+#define MCF_GPIO_PCLRR_ATAL_PCLRR2	(0x04)	/* ATA_RESET */
+
+/* Bit definitions and macros for PCLRR_FEC1H */
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR0	(0x01)	/* FEC1_CRS / ATA_DATA6 */
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR1	(0x02)	/* FEC1_RXD0 / FEC1_RMII_RXD0 / ATA_DATA13 */
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR2	(0x04)	/* FEC1_RXDV / FEC1_RMII_CRS_DV / ATA_DATA15 */
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR3	(0x08)	/* FEC1_RXCLK / ATA_DATA5 */
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR4	(0x10)	/* FEC1_COL / ATA_DATA7 */
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR5	(0x20)	/* FEC1_TXD0 / FEC1_RMII_TXD0 / ATA_DATA9 */
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR6	(0x40)	/* FEC1_TXEN / FEC1_RMII_TXEN / ATA_DATA8 */
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR7	(0x80)	/* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */
+
+/* Bit definitions and macros for PCLRR_FEC1L */
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR0	(0x01)	/* FEC1_RXER / FEC1_RMII_RXER / ATA_DATA12 */
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR1	(0x02)	/* FEC1_RXD1 / FEC1_RMII_RXD1 / ATA_DATA14 */
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR2	(0x04)	/* FEC1_RXD2 / ATA_DATA3 */
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR3	(0x08)	/* FEC1_RXD3 / ATA_DATA4 */
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR4	(0x10)	/* FEC1_TXER / ATA_DATA0 */
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR5	(0x20)	/* FEC1_TXD1 / FEC1_RMII_TXD1 / ATA_DATA10 */
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR6	(0x40)	/* FEC1_TXD2 / ATA_DATA1 */
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR7	(0x80)	/* FEC1_TXD3 / ATA_DATA2 */
+
+/* Bit definitions and macros for PCLRR_FBADH */
+#define MCF_GPIO_PCLRR_FBADH_PCLRR0	(0x01)	/* FB_AD24 */
+#define MCF_GPIO_PCLRR_FBADH_PCLRR1	(0x02)	/* FB_AD25 */
+#define MCF_GPIO_PCLRR_FBADH_PCLRR2	(0x04)	/* FB_AD26 */
+#define MCF_GPIO_PCLRR_FBADH_PCLRR3	(0x08)	/* FB_AD27 */
+#define MCF_GPIO_PCLRR_FBADH_PCLRR4	(0x10)	/* FB_AD28 */
+#define MCF_GPIO_PCLRR_FBADH_PCLRR5	(0x20)	/* FB_AD29 */
+#define MCF_GPIO_PCLRR_FBADH_PCLRR6	(0x40)	/* FB_AD30 */
+#define MCF_GPIO_PCLRR_FBADH_PCLRR7	(0x80)	/* FB_AD31 */
+
+/* Bit definitions and macros for PCLRR_FBADMH */
+#define MCF_GPIO_PCLRR_FBADMH_PCLRR0	(0x01)	/* FB_AD16 */
+#define MCF_GPIO_PCLRR_FBADMH_PCLRR1	(0x02)	/* FB_AD17 */
+#define MCF_GPIO_PCLRR_FBADMH_PCLRR2	(0x04)	/* FB_AD18 */
+#define MCF_GPIO_PCLRR_FBADMH_PCLRR3	(0x08)	/* FB_AD19 */
+#define MCF_GPIO_PCLRR_FBADMH_PCLRR4	(0x10)	/* FB_AD20 */
+#define MCF_GPIO_PCLRR_FBADMH_PCLRR5	(0x20)	/* FB_AD21 */
+#define MCF_GPIO_PCLRR_FBADMH_PCLRR6	(0x40)	/* FB_AD22 */
+#define MCF_GPIO_PCLRR_FBADMH_PCLRR7	(0x80)	/* FB_AD23 */
+
+/* Bit definitions and macros for PCLRR_FBADML */
+#define MCF_GPIO_PCLRR_FBADML_PCLRR0	(0x01)	/* FB_AD8 */
+#define MCF_GPIO_PCLRR_FBADML_PCLRR1	(0x02)	/* FB_AD9 */
+#define MCF_GPIO_PCLRR_FBADML_PCLRR2	(0x04)	/* FB_AD10 */
+#define MCF_GPIO_PCLRR_FBADML_PCLRR3	(0x08)	/* FB_AD11 */
+#define MCF_GPIO_PCLRR_FBADML_PCLRR4	(0x10)	/* FB_AD12 */
+#define MCF_GPIO_PCLRR_FBADML_PCLRR5	(0x20)	/* FB_AD13 */
+#define MCF_GPIO_PCLRR_FBADML_PCLRR6	(0x40)	/* FB_AD14 */
+#define MCF_GPIO_PCLRR_FBADML_PCLRR7	(0x80)	/* FB_AD15 */
+
+/* Bit definitions and macros for PCLRR_FBADL */
+#define MCF_GPIO_PCLRR_FBADL_PCLRR0	(0x01)	/* FB_AD0 */
+#define MCF_GPIO_PCLRR_FBADL_PCLRR1	(0x02)	/* FB_AD1 */
+#define MCF_GPIO_PCLRR_FBADL_PCLRR2	(0x04)	/* FB_AD2 */
+#define MCF_GPIO_PCLRR_FBADL_PCLRR3	(0x08)	/* FB_AD3 */
+#define MCF_GPIO_PCLRR_FBADL_PCLRR4	(0x10)	/* FB_AD4 */
+#define MCF_GPIO_PCLRR_FBADL_PCLRR5	(0x20)	/* FB_AD5 */
+#define MCF_GPIO_PCLRR_FBADL_PCLRR6	(0x40)	/* FB_AD6 */
+#define MCF_GPIO_PCLRR_FBADL_PCLRR7	(0x80)	/* FB_AD7 */
+
+/* Bit definitions and macros for PAR_FEC */
+#define MCF_GPIO_PAR_FEC_FEC0(x)	(((x)&0x07))
+#define MCF_GPIO_PAR_FEC_FEC1(x)	(((x)&0x07)<<4)
+#define MCF_GPIO_PAR_FEC_FEC1_MASK	(0x8F)
+#define MCF_GPIO_PAR_FEC_FEC1_MII	(0x70)
+#define MCF_GPIO_PAR_FEC_FEC1_RMII_GPIO	(0x30)
+#define MCF_GPIO_PAR_FEC_FEC1_RMII_ATA	(0x20)
+#define MCF_GPIO_PAR_FEC_FEC1_ATA	(0x10)
+#define MCF_GPIO_PAR_FEC_FEC1_GPIO	(0x00)
+#define MCF_GPIO_PAR_FEC_FEC0_MASK	(0xF8)
+#define MCF_GPIO_PAR_FEC_FEC0_MII	(0x07)
+#define MCF_GPIO_PAR_FEC_FEC0_RMII_GPIO	(0x03)
+#define MCF_GPIO_PAR_FEC_FEC0_RMII_ULPI	(0x02)
+#define MCF_GPIO_PAR_FEC_FEC0_ULPI	(0x01)
+#define MCF_GPIO_PAR_FEC_FEC0_GPIO	(0x00)
+
+/* Bit definitions and macros for PAR_DMA */
+#define MCF_GPIO_PAR_DMA_DREQ0		(0x01)
+#define MCF_GPIO_PAR_DMA_DACK0(x)	(((x)&0x03)<<2)
+#define MCF_GPIO_PAR_DMA_DREQ1(x)	(((x)&0x03)<<4)
+#define MCF_GPIO_PAR_DMA_DACK1(x)	(((x)&0x03)<<6)
+#define MCF_GPIO_PAR_DMA_DACK1_MASK	(0x3F)
+#define MCF_GPIO_PAR_DMA_DACK1_DACK1	(0xC0)
+#define MCF_GPIO_PAR_DMA_DACK1_ULPI_DIR	(0x40)
+#define MCF_GPIO_PAR_DMA_DACK1_GPIO	(0x00)
+#define MCF_GPIO_PAR_DMA_DREQ1_MASK	(0xCF)
+#define MCF_GPIO_PAR_DMA_DREQ1_DREQ1	(0x30)
+#define MCF_GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10)
+#define MCF_GPIO_PAR_DMA_DREQ1_GPIO	(0x00)
+#define MCF_GPIO_PAR_DMA_DACK0_MASK	(0xF3)
+#define MCF_GPIO_PAR_DMA_DACK0_DACK1	(0x0C)
+#define MCF_GPIO_PAR_DMA_DACK0_ULPI_DIR	(0x04)
+#define MCF_GPIO_PAR_DMA_DACK0_GPIO	(0x00)
+#define MCF_GPIO_PAR_DMA_DREQ0_DREQ0	(0x01)
+#define MCF_GPIO_PAR_DMA_DREQ0_GPIO	(0x00)
+
+/* Bit definitions and macros for PAR_FBCTL */
+#define MCF_GPIO_PAR_FBCTL_TS(x)	(((x)&0x03)<<3)
+#define MCF_GPIO_PAR_FBCTL_RW		(0x20)
+#define MCF_GPIO_PAR_FBCTL_TA		(0x40)
+#define MCF_GPIO_PAR_FBCTL_OE		(0x80)
+#define MCF_GPIO_PAR_FBCTL_OE_OE	(0x80)
+#define MCF_GPIO_PAR_FBCTL_OE_GPIO	(0x00)
+#define MCF_GPIO_PAR_FBCTL_TA_TA	(0x40)
+#define MCF_GPIO_PAR_FBCTL_TA_GPIO	(0x00)
+#define MCF_GPIO_PAR_FBCTL_RW_RW	(0x20)
+#define MCF_GPIO_PAR_FBCTL_RW_GPIO	(0x00)
+#define MCF_GPIO_PAR_FBCTL_TS_MASK	(0xE7)
+#define MCF_GPIO_PAR_FBCTL_TS_TS	(0x18)
+#define MCF_GPIO_PAR_FBCTL_TS_ALE	(0x10)
+#define MCF_GPIO_PAR_FBCTL_TS_TBST	(0x08)
+#define MCF_GPIO_PAR_FBCTL_TS_GPIO	(0x80)
+
+/* Bit definitions and macros for PAR_DSPI */
+#define MCF_GPIO_PAR_DSPI_SCK		(0x01)
+#define MCF_GPIO_PAR_DSPI_SOUT		(0x02)
+#define MCF_GPIO_PAR_DSPI_SIN		(0x04)
+#define MCF_GPIO_PAR_DSPI_PCS0		(0x08)
+#define MCF_GPIO_PAR_DSPI_PCS1		(0x10)
+#define MCF_GPIO_PAR_DSPI_PCS2		(0x20)
+#define MCF_GPIO_PAR_DSPI_PCS5		(0x40)
+#define MCF_GPIO_PAR_DSPI_PCS5_PCS5	(0x40)
+#define MCF_GPIO_PAR_DSPI_PCS5_GPIO	(0x00)
+#define MCF_GPIO_PAR_DSPI_PCS2_PCS2	(0x20)
+#define MCF_GPIO_PAR_DSPI_PCS2_GPIO	(0x00)
+#define MCF_GPIO_PAR_DSPI_PCS1_PCS1	(0x10)
+#define MCF_GPIO_PAR_DSPI_PCS1_GPIO	(0x00)
+#define MCF_GPIO_PAR_DSPI_PCS0_PCS0	(0x08)
+#define MCF_GPIO_PAR_DSPI_PCS0_GPIO	(0x00)
+#define MCF_GPIO_PAR_DSPI_SIN_SIN	(0x04)
+#define MCF_GPIO_PAR_DSPI_SIN_GPIO	(0x00)
+#define MCF_GPIO_PAR_DSPI_SOUT_SOUT	(0x02)
+#define MCF_GPIO_PAR_DSPI_SOUT_GPIO	(0x00)
+#define MCF_GPIO_PAR_DSPI_SCK_SCK	(0x01)
+#define MCF_GPIO_PAR_DSPI_SCK_GPIO	(0x00)
+
+/* Bit definitions and macros for PAR_BE */
+#define MCF_GPIO_PAR_BE_BE0		(0x01)
+#define MCF_GPIO_PAR_BE_BE1		(0x04)
+#define MCF_GPIO_PAR_BE_BE2(x)		(((x)&0x03)<<4)
+#define MCF_GPIO_PAR_BE_BE3(x)		(((x)&0x03)<<6)
+#define MCF_GPIO_PAR_BE_BE3_MASK	(0x3F)
+#define MCF_GPIO_PAR_BE_BE3_BE3		(0xC0)
+#define MCF_GPIO_PAR_BE_BE3_TSIZ1	(0x80)
+#define MCF_GPIO_PAR_BE_BE3_GPIO	(0x00)
+#define MCF_GPIO_PAR_BE_BE2_MASK	(0xCF)
+#define MCF_GPIO_PAR_BE_BE2_BE2		(0x30)
+#define MCF_GPIO_PAR_BE_BE2_TSIZ0	(0x20)
+#define MCF_GPIO_PAR_BE_BE2_GPIO	(0x00)
+#define MCF_GPIO_PAR_BE_BE1_BE1		(0x04)
+#define MCF_GPIO_PAR_BE_BE1_GPIO	(0x00)
+#define MCF_GPIO_PAR_BE_BE0_BE0		(0x01)
+#define MCF_GPIO_PAR_BE_BE0_GPIO	(0x00)
+
+/* Bit definitions and macros for PAR_CS */
+#define MCF_GPIO_PAR_CS_CS1		(0x02)
+#define MCF_GPIO_PAR_CS_CS2		(0x04)
+#define MCF_GPIO_PAR_CS_CS3		(0x08)
+#define MCF_GPIO_PAR_CS_CS3_CS3		(0x08)
+#define MCF_GPIO_PAR_CS_CS3_GPIO	(0x00)
+#define MCF_GPIO_PAR_CS_CS2_CS2		(0x04)
+#define MCF_GPIO_PAR_CS_CS2_GPIO	(0x00)
+#define MCF_GPIO_PAR_CS_CS1_CS1		(0x02)
+#define MCF_GPIO_PAR_CS_CS1_GPIO	(0x00)
+
+/* Bit definitions and macros for PAR_TIMER */
+#define MCF_GPIO_PAR_TIMER_T0IN(x)	(((x)&0x03))
+#define MCF_GPIO_PAR_TIMER_T1IN(x)	(((x)&0x03)<<2)
+#define MCF_GPIO_PAR_TIMER_T2IN(x)	(((x)&0x03)<<4)
+#define MCF_GPIO_PAR_TIMER_T3IN(x)	(((x)&0x03)<<6)
+#define MCF_GPIO_PAR_TIMER_T3IN_MASK	(0x3F)
+#define MCF_GPIO_PAR_TIMER_T3IN_T3IN	(0xC0)
+#define MCF_GPIO_PAR_TIMER_T3IN_T3OUT	(0x80)
+#define MCF_GPIO_PAR_TIMER_T3IN_U2RXD	(0x40)
+#define MCF_GPIO_PAR_TIMER_T3IN_GPIO	(0x00)
+#define MCF_GPIO_PAR_TIMER_T2IN_MASK	(0xCF)
+#define MCF_GPIO_PAR_TIMER_T2IN_T2IN	(0x30)
+#define MCF_GPIO_PAR_TIMER_T2IN_T2OUT	(0x20)
+#define MCF_GPIO_PAR_TIMER_T2IN_U2TXD	(0x10)
+#define MCF_GPIO_PAR_TIMER_T2IN_GPIO	(0x00)
+#define MCF_GPIO_PAR_TIMER_T1IN_MASK	(0xF3)
+#define MCF_GPIO_PAR_TIMER_T1IN_T1IN	(0x0C)
+#define MCF_GPIO_PAR_TIMER_T1IN_T1OUT	(0x08)
+#define MCF_GPIO_PAR_TIMER_T1IN_U2CTS	(0x04)
+#define MCF_GPIO_PAR_TIMER_T1IN_GPIO	(0x00)
+#define MCF_GPIO_PAR_TIMER_T0IN_MASK	(0xFC)
+#define MCF_GPIO_PAR_TIMER_T0IN_T0IN	(0x03)
+#define MCF_GPIO_PAR_TIMER_T0IN_T0OUT	(0x02)
+#define MCF_GPIO_PAR_TIMER_T0IN_U2RTS	(0x01)
+#define MCF_GPIO_PAR_TIMER_T0IN_GPIO	(0x00)
+
+/* Bit definitions and macros for PAR_USB */
+#define MCF_GPIO_PAR_USB_VBUSOC(x)		(((x)&0x03))
+#define MCF_GPIO_PAR_USB_VBUSEN(x)		(((x)&0x03)<<2)
+#define MCF_GPIO_PAR_USB_VBUSEN_MASK		(0xF3)
+#define MCF_GPIO_PAR_USB_VBUSEN_VBUSEN		(0x0C)
+#define MCF_GPIO_PAR_USB_VBUSEN_USBPULLUP	(0x08)
+#define MCF_GPIO_PAR_USB_VBUSEN_ULPI_NXT	(0x04)
+#define MCF_GPIO_PAR_USB_VBUSEN_GPIO		(0x00)
+#define MCF_GPIO_PAR_USB_VBUSOC_MASK		(0xFC)
+#define MCF_GPIO_PAR_USB_VBUSOC_VBUSOC		(0x03)
+#define MCF_GPIO_PAR_USB_VBUSOC_ULPI_STP	(0x01)
+#define MCF_GPIO_PAR_USB_VBUSOC_GPIO		(0x00)
+
+/* Bit definitions and macros for PAR_UART */
+#define MCF_GPIO_PAR_UART_U0TXD		(0x01)
+#define MCF_GPIO_PAR_UART_U0RXD		(0x02)
+#define MCF_GPIO_PAR_UART_U0RTS		(0x04)
+#define MCF_GPIO_PAR_UART_U0CTS		(0x08)
+#define MCF_GPIO_PAR_UART_U1TXD		(0x10)
+#define MCF_GPIO_PAR_UART_U1RXD		(0x20)
+#define MCF_GPIO_PAR_UART_U1RTS		(0x40)
+#define MCF_GPIO_PAR_UART_U1CTS		(0x80)
+#define MCF_GPIO_PAR_UART_U1CTS_U1CTS	(0x80)
+#define MCF_GPIO_PAR_UART_U1CTS_GPIO	(0x00)
+#define MCF_GPIO_PAR_UART_U1RTS_U1RTS	(0x40)
+#define MCF_GPIO_PAR_UART_U1RTS_GPIO	(0x00)
+#define MCF_GPIO_PAR_UART_U1RXD_U1RXD	(0x20)
+#define MCF_GPIO_PAR_UART_U1RXD_GPIO	(0x00)
+#define MCF_GPIO_PAR_UART_U1TXD_U1TXD	(0x10)
+#define MCF_GPIO_PAR_UART_U1TXD_GPIO	(0x00)
+#define MCF_GPIO_PAR_UART_U0CTS_U0CTS	(0x08)
+#define MCF_GPIO_PAR_UART_U0CTS_GPIO	(0x00)
+#define MCF_GPIO_PAR_UART_U0RTS_U0RTS	(0x04)
+#define MCF_GPIO_PAR_UART_U0RTS_GPIO	(0x00)
+#define MCF_GPIO_PAR_UART_U0RXD_U0RXD	(0x02)
+#define MCF_GPIO_PAR_UART_U0RXD_GPIO	(0x00)
+#define MCF_GPIO_PAR_UART_U0TXD_U0TXD	(0x01)
+#define MCF_GPIO_PAR_UART_U0TXD_GPIO	(0x00)
+
+/* Bit definitions and macros for PAR_FECI2C */
+#define MCF_GPIO_PAR_FECI2C_SDA(x)	(((x)&0x0003))
+#define MCF_GPIO_PAR_FECI2C_SCL(x)	(((x)&0x0003)<<2)
+#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x)	(((x)&0x0003))
+#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x)	(((x)&0x0003)<<2)
+#define MCF_GPIO_PAR_FECI2C_MDIO0	(0x0010)
+#define MCF_GPIO_PAR_FECI2C_MDC0	(0x0040)
+#define MCF_GPIO_PAR_FECI2C_MDIO1(x)	(((x)&0x0003)<<8)
+#define MCF_GPIO_PAR_FECI2C_MDC1(x)	(((x)&0x0003)<<10)
+#define MCF_GPIO_PAR_FECI2C_MDC1_MASK	(0xF3FF)
+#define MCF_GPIO_PAR_FECI2C_MDC1_MDC1	(0x0C00)
+#define MCF_GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800)
+#define MCF_GPIO_PAR_FECI2C_MDC1_GPIO	(0x0000)
+#define MCF_GPIO_PAR_FECI2C_MDIO1_MASK	(0xFCFF)
+#define MCF_GPIO_PAR_FECI2C_MDIO1_MDIO1	(0x0300)
+#define MCF_GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200)
+#define MCF_GPIO_PAR_FECI2C_MDIO1_GPIO	(0x0000)
+#define MCF_GPIO_PAR_FECI2C_MDC0_MDC0	(0x0040)
+#define MCF_GPIO_PAR_FECI2C_MDC0_GPIO	(0x0000)
+#define MCF_GPIO_PAR_FECI2C_MDIO0_MDIO0	(0x0010)
+#define MCF_GPIO_PAR_FECI2C_MDIO0_GPIO	(0x0000)
+#define MCF_GPIO_PAR_FECI2C_SCL_MASK	(0xFFF3)
+#define MCF_GPIO_PAR_FECI2C_SCL_SCL	(0x000C)
+#define MCF_GPIO_PAR_FECI2C_SCL_U2TXD	(0x0004)
+#define MCF_GPIO_PAR_FECI2C_SCL_GPIO	(0x0000)
+#define MCF_GPIO_PAR_FECI2C_SDA_MASK	(0xFFFC)
+#define MCF_GPIO_PAR_FECI2C_SDA_SDA	(0x0003)
+#define MCF_GPIO_PAR_FECI2C_SDA_U2RXD	(0x0001)
+#define MCF_GPIO_PAR_FECI2C_SDA_GPIO	(0x0000)
+
+/* Bit definitions and macros for PAR_SSI */
+#define MCF_GPIO_PAR_SSI_MCLK		(0x0001)
+#define MCF_GPIO_PAR_SSI_STXD(x)	(((x)&0x0003)<<2)
+#define MCF_GPIO_PAR_SSI_SRXD(x)	(((x)&0x0003)<<4)
+#define MCF_GPIO_PAR_SSI_FS(x)		(((x)&0x0003)<<6)
+#define MCF_GPIO_PAR_SSI_BCLK(x)	(((x)&0x0003)<<8)
+#define MCF_GPIO_PAR_SSI_BCLK_MASK	(0xFCFF)
+#define MCF_GPIO_PAR_SSI_BCLK_BCLK	(0x0300)
+#define MCF_GPIO_PAR_SSI_BCLK_U1CTS	(0x0200)
+#define MCF_GPIO_PAR_SSI_BCLK_GPIO	(0x0000)
+#define MCF_GPIO_PAR_SSI_FS_MASK	(0xFF3F)
+#define MCF_GPIO_PAR_SSI_FS_FS		(0x00C0)
+#define MCF_GPIO_PAR_SSI_FS_U1RTS	(0x0080)
+#define MCF_GPIO_PAR_SSI_FS_GPIO	(0x0000)
+#define MCF_GPIO_PAR_SSI_SRXD_MASK	(0xFFCF)
+#define MCF_GPIO_PAR_SSI_SRXD_SRXD	(0x0030)
+#define MCF_GPIO_PAR_SSI_SRXD_U1RXD	(0x0020)
+#define MCF_GPIO_PAR_SSI_SRXD_GPIO	(0x0000)
+#define MCF_GPIO_PAR_SSI_STXD_MASK	(0xFFF3)
+#define MCF_GPIO_PAR_SSI_STXD_STXD	(0x000C)
+#define MCF_GPIO_PAR_SSI_STXD_U1TXD	(0x0008)
+#define MCF_GPIO_PAR_SSI_STXD_GPIO	(0x0000)
+#define MCF_GPIO_PAR_SSI_MCLK_MCLK	(0x0001)
+#define MCF_GPIO_PAR_SSI_MCLK_GPIO	(0x0000)
+
+/* Bit definitions and macros for PAR_ATA */
+#define MCF_GPIO_PAR_ATA_IORDY		(0x0001)
+#define MCF_GPIO_PAR_ATA_DMARQ		(0x0002)
+#define MCF_GPIO_PAR_ATA_RESET		(0x0004)
+#define MCF_GPIO_PAR_ATA_DA0		(0x0020)
+#define MCF_GPIO_PAR_ATA_DA1		(0x0040)
+#define MCF_GPIO_PAR_ATA_DA2		(0x0080)
+#define MCF_GPIO_PAR_ATA_CS0		(0x0100)
+#define MCF_GPIO_PAR_ATA_CS1		(0x0200)
+#define MCF_GPIO_PAR_ATA_BUFEN		(0x0400)
+#define MCF_GPIO_PAR_ATA_BUFEN_BUFEN	(0x0400)
+#define MCF_GPIO_PAR_ATA_BUFEN_GPIO	(0x0000)
+#define MCF_GPIO_PAR_ATA_CS1_CS1	(0x0200)
+#define MCF_GPIO_PAR_ATA_CS1_GPIO	(0x0000)
+#define MCF_GPIO_PAR_ATA_CS0_CS0	(0x0100)
+#define MCF_GPIO_PAR_ATA_CS0_GPIO	(0x0000)
+#define MCF_GPIO_PAR_ATA_DA2_DA2	(0x0080)
+#define MCF_GPIO_PAR_ATA_DA2_GPIO	(0x0000)
+#define MCF_GPIO_PAR_ATA_DA1_DA1	(0x0040)
+#define MCF_GPIO_PAR_ATA_DA1_GPIO	(0x0000)
+#define MCF_GPIO_PAR_ATA_DA0_DA0	(0x0020)
+#define MCF_GPIO_PAR_ATA_DA0_GPIO	(0x0000)
+#define MCF_GPIO_PAR_ATA_RESET_RESET	(0x0004)
+#define MCF_GPIO_PAR_ATA_RESET_GPIO	(0x0000)
+#define MCF_GPIO_PAR_ATA_DMARQ_DMARQ	(0x0002)
+#define MCF_GPIO_PAR_ATA_DMARQ_GPIO	(0x0000)
+#define MCF_GPIO_PAR_ATA_IORDY_IORDY	(0x0001)
+#define MCF_GPIO_PAR_ATA_IORDY_GPIO	(0x0000)
+
+/* Bit definitions and macros for PAR_IRQ */
+#define MCF_GPIO_PAR_IRQ_IRQ1		(0x02)
+#define MCF_GPIO_PAR_IRQ_IRQ4		(0x10)
+#define MCF_GPIO_PAR_IRQ_IRQ4_IRQ4	(0x10)
+#define MCF_GPIO_PAR_IRQ_IRQ4_GPIO	(0x00)
+#define MCF_GPIO_PAR_IRQ_IRQ1_IRQ1	(0x02)
+#define MCF_GPIO_PAR_IRQ_IRQ1_GPIO	(0x00)
+
+/* Bit definitions and macros for PAR_PCI */
+#define MCF_GPIO_PAR_PCI_REQ0		(0x0001)
+#define MCF_GPIO_PAR_PCI_REQ1		(0x0004)
+#define MCF_GPIO_PAR_PCI_REQ2		(0x0010)
+#define MCF_GPIO_PAR_PCI_REQ3(x)	(((x)&0x0003)<<6)
+#define MCF_GPIO_PAR_PCI_GNT0		(0x0100)
+#define MCF_GPIO_PAR_PCI_GNT1		(0x0400)
+#define MCF_GPIO_PAR_PCI_GNT2		(0x1000)
+#define MCF_GPIO_PAR_PCI_GNT3(x)	(((x)&0x0003)<<14)
+#define MCF_GPIO_PAR_PCI_GNT3_MASK	(0x3FFF)
+#define MCF_GPIO_PAR_PCI_GNT3_GNT3	(0xC000)
+#define MCF_GPIO_PAR_PCI_GNT3_ATA_DMACK	(0x8000)
+#define MCF_GPIO_PAR_PCI_GNT3_GPIO	(0x0000)
+#define MCF_GPIO_PAR_PCI_GNT2_GNT2	(0x1000)
+#define MCF_GPIO_PAR_PCI_GNT2_GPIO	(0x0000)
+#define MCF_GPIO_PAR_PCI_GNT1_GNT1	(0x0400)
+#define MCF_GPIO_PAR_PCI_GNT1_GPIO	(0x0000)
+#define MCF_GPIO_PAR_PCI_GNT0_GNT0	(0x0100)
+#define MCF_GPIO_PAR_PCI_GNT0_GPIO	(0x0000)
+#define MCF_GPIO_PAR_PCI_REQ3_MASK	(0xFF3F)
+#define MCF_GPIO_PAR_PCI_REQ3_REQ3	(0x00C0)
+#define MCF_GPIO_PAR_PCI_REQ3_ATA_INTRQ	(0x0080)
+#define MCF_GPIO_PAR_PCI_REQ3_GPIO	(0x0000)
+#define MCF_GPIO_PAR_PCI_REQ2_REQ2	(0x0010)
+#define MCF_GPIO_PAR_PCI_REQ2_GPIO	(0x0000)
+#define MCF_GPIO_PAR_PCI_REQ1_REQ1	(0x0040)
+#define MCF_GPIO_PAR_PCI_REQ1_GPIO	(0x0000)
+#define MCF_GPIO_PAR_PCI_REQ0_REQ0	(0x0001)
+#define MCF_GPIO_PAR_PCI_REQ0_GPIO	(0x0000)
+
+/* Bit definitions and macros for MSCR_SDRAM */
+#define MCF_GPIO_MSCR_SDRAM_SDCTL(x)		(((x)&0x03))
+#define MCF_GPIO_MSCR_SDRAM_SDCLK(x)		(((x)&0x03)<<2)
+#define MCF_GPIO_MSCR_SDRAM_SDDQS(x)		(((x)&0x03)<<4)
+#define MCF_GPIO_MSCR_SDRAM_SDDATA(x)		(((x)&0x03)<<6)
+#define MCF_GPIO_MSCR_SDRAM_SDDATA_MASK		(0x3F)
+#define MCF_GPIO_MSCR_SDRAM_SDDATA_DDR1		(0xC0)
+#define MCF_GPIO_MSCR_SDRAM_SDDATA_DDR2		(0x80)
+#define MCF_GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR	(0x40)
+#define MCF_GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR	(0x00)
+#define MCF_GPIO_MSCR_SDRAM_SDDQS_MASK		(0xCF)
+#define MCF_GPIO_MSCR_SDRAM_SDDQS_DDR1		(0x30)
+#define MCF_GPIO_MSCR_SDRAM_SDDQS_DDR2		(0x20)
+#define MCF_GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR	(0x10)
+#define MCF_GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR	(0x00)
+#define MCF_GPIO_MSCR_SDRAM_SDCLK_MASK		(0xF3)
+#define MCF_GPIO_MSCR_SDRAM_SDCLK_DDR1		(0x0C)
+#define MCF_GPIO_MSCR_SDRAM_SDCLK_DDR2		(0x08)
+#define MCF_GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR	(0x04)
+#define MCF_GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR	(0x00)
+#define MCF_GPIO_MSCR_SDRAM_SDCTL_MASK		(0xFC)
+#define MCF_GPIO_MSCR_SDRAM_SDCTL_DDR1		(0x03)
+#define MCF_GPIO_MSCR_SDRAM_SDCTL_DDR2		(0x02)
+#define MCF_GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR	(0x01)
+#define MCF_GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR	(0x00)
+
+/* Bit definitions and macros for MSCR_PCI */
+#define MCF_GPIO_MSCR_PCI_PCI		(0x01)
+#define MCF_GPIO_MSCR_PCI_PCI_HI_66MHZ	(0x01)
+#define MCF_GPIO_MSCR_PCI_PCI_LO_33MHZ	(0x00)
+
+/* Bit definitions and macros for DSCR_I2C */
+#define MCF_GPIO_DSCR_I2C_I2C(x)	(((x)&0x03))
+#define MCF_GPIO_DSCR_I2C_I2C_LOAD_50PF	(0x03)
+#define MCF_GPIO_DSCR_I2C_I2C_LOAD_30PF	(0x02)
+#define MCF_GPIO_DSCR_I2C_I2C_LOAD_20PF	(0x01)
+#define MCF_GPIO_DSCR_I2C_I2C_LOAD_10PF	(0x00)
+
+/* Bit definitions and macros for DSCR_FLEXBUS */
+#define MCF_GPIO_DSCR_FLEXBUS_FBADL(x)		(((x)&0x03))
+#define MCF_GPIO_DSCR_FLEXBUS_FBADH(x)		(((x)&0x03)<<2)
+#define MCF_GPIO_DSCR_FLEXBUS_FBCTL(x)		(((x)&0x03)<<4)
+#define MCF_GPIO_DSCR_FLEXBUS_FBCLK(x)		(((x)&0x03)<<6)
+#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF	(0xC0)
+#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30P	(0x80)
+#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF	(0x40)
+#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF	(0x00)
+#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF	(0x30)
+#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF	(0x20)
+#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF	(0x10)
+#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF	(0x00)
+#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF	(0x0C)
+#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF	(0x08)
+#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF	(0x04)
+#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF	(0x00)
+#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF	(0x03)
+#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF	(0x02)
+#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF	(0x01)
+#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF	(0x00)
+
+/* Bit definitions and macros for DSCR_FEC */
+#define MCF_GPIO_DSCR_FEC_FEC0(x)		(((x)&0x03))
+#define MCF_GPIO_DSCR_FEC_FEC1(x)		(((x)&0x03)<<2)
+#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_50PF	(0x0C)
+#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_30PF	(0x08)
+#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_20PF	(0x04)
+#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_10PF	(0x00)
+#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_50PF	(0x03)
+#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_30PF	(0x02)
+#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_20PF	(0x01)
+#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_10PF	(0x00)
+
+/* Bit definitions and macros for DSCR_UART */
+#define MCF_GPIO_DSCR_UART_UART0(x)		(((x)&0x03))
+#define MCF_GPIO_DSCR_UART_UART1(x)		(((x)&0x03)<<2)
+#define MCF_GPIO_DSCR_UART_UART1_LOAD_50PF	(0x0C)
+#define MCF_GPIO_DSCR_UART_UART1_LOAD_30PF	(0x08)
+#define MCF_GPIO_DSCR_UART_UART1_LOAD_20PF	(0x04)
+#define MCF_GPIO_DSCR_UART_UART1_LOAD_10PF	(0x00)
+#define MCF_GPIO_DSCR_UART_UART0_LOAD_50PF	(0x03)
+#define MCF_GPIO_DSCR_UART_UART0_LOAD_30PF	(0x02)
+#define MCF_GPIO_DSCR_UART_UART0_LOAD_20PF	(0x01)
+#define MCF_GPIO_DSCR_UART_UART0_LOAD_10PF	(0x00)
+
+/* Bit definitions and macros for DSCR_DSPI */
+#define MCF_GPIO_DSCR_DSPI_DSPI(x)		(((x)&0x03))
+#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_50PF	(0x03)
+#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_30PF	(0x02)
+#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_20PF	(0x01)
+#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_10PF	(0x00)
+
+/* Bit definitions and macros for DSCR_TIMER */
+#define MCF_GPIO_DSCR_TIMER_TIMER(x)		(((x)&0x03))
+#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_50PF	(0x03)
+#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_30PF	(0x02)
+#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_20PF	(0x01)
+#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_10PF	(0x00)
+
+/* Bit definitions and macros for DSCR_SSI */
+#define MCF_GPIO_DSCR_SSI_SSI(x)	(((x)&0x03))
+#define MCF_GPIO_DSCR_SSI_SSI_LOAD_50PF	(0x03)
+#define MCF_GPIO_DSCR_SSI_SSI_LOAD_30PF	(0x02)
+#define MCF_GPIO_DSCR_SSI_SSI_LOAD_20PF (0x01)
+#define MCF_GPIO_DSCR_SSI_SSI_LOAD_10PF (0x00)
+
+/* Bit definitions and macros for DSCR_DMA */
+#define MCF_GPIO_DSCR_DMA_DMA(x)	(((x)&0x03))
+#define MCF_GPIO_DSCR_DMA_DMA_LOAD_50PF	(0x03)
+#define MCF_GPIO_DSCR_DMA_DMA_LOAD_30PF	(0x02)
+#define MCF_GPIO_DSCR_DMA_DMA_LOAD_20PF	(0x01)
+#define MCF_GPIO_DSCR_DMA_DMA_LOAD_10PF	(0x00)
+
+/* Bit definitions and macros for DSCR_DEBUG */
+#define MCF_GPIO_DSCR_DEBUG_DEBUG(x)		(((x)&0x03))
+#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF	(0x03)
+#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF	(0x02)
+#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF	(0x01)
+#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF	(0x00)
+
+/* Bit definitions and macros for DSCR_RESET */
+#define MCF_GPIO_DSCR_RESET_RESET(x)		(((x)&0x03))
+#define MCF_GPIO_DSCR_RESET_RESET_LOAD_50PF	(0x03)
+#define MCF_GPIO_DSCR_RESET_RESET_LOAD_30PF	(0x02)
+#define MCF_GPIO_DSCR_RESET_RESET_LOAD_20PF	(0x01)
+#define MCF_GPIO_DSCR_RESET_RESET_LOAD_10PF	(0x00)
+
+/* Bit definitions and macros for DSCR_IRQ */
+#define MCF_GPIO_DSCR_IRQ_IRQ(x)	(((x)&0x03))
+#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_50PF	(0x03)
+#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_30PF	(0x02)
+#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_20PF	(0x01)
+#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_10PF	(0x00)
+
+/* Bit definitions and macros for DSCR_USB */
+#define MCF_GPIO_DSCR_USB_USB(x)	(((x)&0x03))
+#define MCF_GPIO_DSCR_USB_USB_LOAD_50PF	(0x03)
+#define MCF_GPIO_DSCR_USB_USB_LOAD_30PF	(0x02)
+#define MCF_GPIO_DSCR_USB_USB_LOAD_20PF	(0x01)
+#define MCF_GPIO_DSCR_USB_USB_LOAD_10PF	(0x00)
+
+/* Bit definitions and macros for DSCR_ATA */
+#define MCF_GPIO_DSCR_ATA_ATA(x)	(((x)&0x03))
+#define MCF_GPIO_DSCR_ATA_ATA_LOAD_50PF	(0x03)
+#define MCF_GPIO_DSCR_ATA_ATA_LOAD_30PF	(0x02)
+#define MCF_GPIO_DSCR_ATA_ATA_LOAD_20PF	(0x01)
+#define MCF_GPIO_DSCR_ATA_ATA_LOAD_10PF	(0x00)
+
+/********************************************************************/
+
+#endif /* __MCF5445X_GPIO_H__ */
--- /dev/null
+++ b/include/asm-m68k/mcf5445x_i2c.h
@@ -0,0 +1,39 @@
+/*
+ * Matt Waddel Matt.Waddel@freescale.com
+ *
+ * Copyright Freescale Semiconductor, Inc. 2007
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MCF5445X_I2C_H__
+#define __MCF5445X_I2C_H__
+
+/*********************************************************************
+*
+* I2C Module (I2C)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_I2C_I2ADR	(volatile u8 *)(0xFC058000)
+#define MCF_I2C_I2FDR	(volatile u8 *)(0xFC058004)
+#define MCF_I2C_I2CR	(volatile u8 *)(0xFC058008)
+#define MCF_I2C_I2SR	(volatile u8 *)(0xFC05800C)
+#define MCF_I2C_I2DR	(volatile u8 *)(0xFC058010)
+
+/* Bit definitions and macros for I2AR */
+#define MCF_I2C_I2AR_ADR(x)	(((x)&0x7F)<<1)
+
+/* Bit definitions and macros for I2FDR */
+#define MCF_I2C_I2FDR_IC(x)	(((x)&0x3F))
+
+/* Bit definitions and macros for I2DR */
+#define MCF_I2C_I2DR_DATA(x)	(x)
+
+/********************************************************************/
+
+#endif /* __MCF5445X_I2C_H__ */
--- /dev/null
+++ b/include/asm-m68k/mcf5445x_intc.h
@@ -0,0 +1,724 @@
+/*
+ * Matt Waddel Matt.Waddel@freescale.com
+ *
+ * Copyright Freescale Semiconductor, Inc. 2007
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MCF5445X_INTC_H__
+#define __MCF5445X_INTC_H__
+
+/*********************************************************************
+*
+* Interrupt Controller (INTC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_INTC0_IPRH          MCF_REG32(0xFC048000)
+#define MCF_INTC0_IPRL          MCF_REG32(0xFC048004)
+#define MCF_INTC0_IMRH          MCF_REG32(0xFC048008)
+#define MCF_INTC0_IMRL          MCF_REG32(0xFC04800C)
+#define MCF_INTC0_INTFRCH       MCF_REG32(0xFC048010)
+#define MCF_INTC0_INTFRCL       MCF_REG32(0xFC048014)
+#define MCF_INTC0_ICONFIG       MCF_REG16(0xFC04801A)
+#define MCF_INTC0_SIMR          MCF_REG08(0xFC04801C)
+#define MCF_INTC0_CIMR          MCF_REG08(0xFC04801D)
+#define MCF_INTC0_CLMASK        MCF_REG08(0xFC04801E)
+#define MCF_INTC0_SLMASK        MCF_REG08(0xFC04801F)
+#define MCF_INTC0_ICR1          MCF_REG08(0xFC048041)
+#define MCF_INTC0_ICR2          MCF_REG08(0xFC048042)
+#define MCF_INTC0_ICR3          MCF_REG08(0xFC048043)
+#define MCF_INTC0_ICR4          MCF_REG08(0xFC048044)
+#define MCF_INTC0_ICR5          MCF_REG08(0xFC048045)
+#define MCF_INTC0_ICR6          MCF_REG08(0xFC048046)
+#define MCF_INTC0_ICR7          MCF_REG08(0xFC048047)
+#define MCF_INTC0_ICR8          MCF_REG08(0xFC048048)
+#define MCF_INTC0_ICR9          MCF_REG08(0xFC048049)
+#define MCF_INTC0_ICR10         MCF_REG08(0xFC04804A)
+#define MCF_INTC0_ICR11         MCF_REG08(0xFC04804B)
+#define MCF_INTC0_ICR12         MCF_REG08(0xFC04804C)
+#define MCF_INTC0_ICR13         MCF_REG08(0xFC04804D)
+#define MCF_INTC0_ICR14         MCF_REG08(0xFC04804E)
+#define MCF_INTC0_ICR15         MCF_REG08(0xFC04804F)
+#define MCF_INTC0_ICR16         MCF_REG08(0xFC048050)
+#define MCF_INTC0_ICR17         MCF_REG08(0xFC048051)
+#define MCF_INTC0_ICR18         MCF_REG08(0xFC048052)
+#define MCF_INTC0_ICR19         MCF_REG08(0xFC048053)
+#define MCF_INTC0_ICR20         MCF_REG08(0xFC048054)
+#define MCF_INTC0_ICR21         MCF_REG08(0xFC048055)
+#define MCF_INTC0_ICR22         MCF_REG08(0xFC048056)
+#define MCF_INTC0_ICR23         MCF_REG08(0xFC048057)
+#define MCF_INTC0_ICR24         MCF_REG08(0xFC048058)
+#define MCF_INTC0_ICR25         MCF_REG08(0xFC048059)
+#define MCF_INTC0_ICR26         MCF_REG08(0xFC04805A)
+#define MCF_INTC0_ICR27         MCF_REG08(0xFC04805B)
+#define MCF_INTC0_ICR28         MCF_REG08(0xFC04805C)
+#define MCF_INTC0_ICR29         MCF_REG08(0xFC04805D)
+#define MCF_INTC0_ICR30         MCF_REG08(0xFC04805E)
+#define MCF_INTC0_ICR31         MCF_REG08(0xFC04805F)
+#define MCF_INTC0_ICR32         MCF_REG08(0xFC048060)
+#define MCF_INTC0_ICR33         MCF_REG08(0xFC048061)
+#define MCF_INTC0_ICR34         MCF_REG08(0xFC048062)
+#define MCF_INTC0_ICR35         MCF_REG08(0xFC048063)
+#define MCF_INTC0_ICR36         MCF_REG08(0xFC048064)
+#define MCF_INTC0_ICR37         MCF_REG08(0xFC048065)
+#define MCF_INTC0_ICR38         MCF_REG08(0xFC048066)
+#define MCF_INTC0_ICR39         MCF_REG08(0xFC048067)
+#define MCF_INTC0_ICR40         MCF_REG08(0xFC048068)
+#define MCF_INTC0_ICR41         MCF_REG08(0xFC048069)
+#define MCF_INTC0_ICR42         MCF_REG08(0xFC04806A)
+#define MCF_INTC0_ICR43         MCF_REG08(0xFC04806B)
+#define MCF_INTC0_ICR44         MCF_REG08(0xFC04806C)
+#define MCF_INTC0_ICR45         MCF_REG08(0xFC04806D)
+#define MCF_INTC0_ICR46         MCF_REG08(0xFC04806E)
+#define MCF_INTC0_ICR47         MCF_REG08(0xFC04806F)
+#define MCF_INTC0_ICR48         MCF_REG08(0xFC048070)
+#define MCF_INTC0_ICR49         MCF_REG08(0xFC048071)
+#define MCF_INTC0_ICR50         MCF_REG08(0xFC048072)
+#define MCF_INTC0_ICR51         MCF_REG08(0xFC048073)
+#define MCF_INTC0_ICR52         MCF_REG08(0xFC048074)
+#define MCF_INTC0_ICR53         MCF_REG08(0xFC048075)
+#define MCF_INTC0_ICR54         MCF_REG08(0xFC048076)
+#define MCF_INTC0_ICR55         MCF_REG08(0xFC048077)
+#define MCF_INTC0_ICR56         MCF_REG08(0xFC048078)
+#define MCF_INTC0_ICR57         MCF_REG08(0xFC048079)
+#define MCF_INTC0_ICR58         MCF_REG08(0xFC04807A)
+#define MCF_INTC0_ICR59         MCF_REG08(0xFC04807B)
+#define MCF_INTC0_ICR60         MCF_REG08(0xFC04807C)
+#define MCF_INTC0_ICR61         MCF_REG08(0xFC04807D)
+#define MCF_INTC0_ICR62         MCF_REG08(0xFC04807E)
+#define MCF_INTC0_ICR63         MCF_REG08(0xFC04807F)
+#define MCF_INTC0_SWIACK        MCF_REG08(0xFC0480E0)
+#define MCF_INTC0_L1IACK        MCF_REG08(0xFC0480E4)
+#define MCF_INTC0_L2IACK        MCF_REG08(0xFC0480E8)
+#define MCF_INTC0_L3IACK        MCF_REG08(0xFC0480EC)
+#define MCF_INTC0_L4IACK        MCF_REG08(0xFC0480F0)
+#define MCF_INTC0_L5IACK        MCF_REG08(0xFC0480F4)
+#define MCF_INTC0_L6IACK        MCF_REG08(0xFC0480F8)
+#define MCF_INTC0_L7IACK        MCF_REG08(0xFC0480FC)
+#define MCF_INTC1_IPRH          MCF_REG32(0xFC04C000)
+#define MCF_INTC1_IPRL          MCF_REG32(0xFC04C004)
+#define MCF_INTC1_IMRH          MCF_REG32(0xFC04C008)
+#define MCF_INTC1_IMRL          MCF_REG32(0xFC04C00C)
+#define MCF_INTC1_INTFRCH       MCF_REG32(0xFC04C010)
+#define MCF_INTC1_INTFRCL       MCF_REG32(0xFC04C014)
+#define MCF_INTC1_ICONFIG       MCF_REG16(0xFC04C01A)
+#define MCF_INTC1_SIMR          MCF_REG08(0xFC04C01C)
+#define MCF_INTC1_CIMR          MCF_REG08(0xFC04C01D)
+#define MCF_INTC1_CLMASK        MCF_REG08(0xFC04C01E)
+#define MCF_INTC1_SLMASK        MCF_REG08(0xFC04C01F)
+#define MCF_INTC1_ICR1          MCF_REG08(0xFC04C041)
+#define MCF_INTC1_ICR2          MCF_REG08(0xFC04C042)
+#define MCF_INTC1_ICR3          MCF_REG08(0xFC04C043)
+#define MCF_INTC1_ICR4          MCF_REG08(0xFC04C044)
+#define MCF_INTC1_ICR5          MCF_REG08(0xFC04C045)
+#define MCF_INTC1_ICR6          MCF_REG08(0xFC04C046)
+#define MCF_INTC1_ICR7          MCF_REG08(0xFC04C047)
+#define MCF_INTC1_ICR8          MCF_REG08(0xFC04C048)
+#define MCF_INTC1_ICR9          MCF_REG08(0xFC04C049)
+#define MCF_INTC1_ICR10         MCF_REG08(0xFC04C04A)
+#define MCF_INTC1_ICR11         MCF_REG08(0xFC04C04B)
+#define MCF_INTC1_ICR12         MCF_REG08(0xFC04C04C)
+#define MCF_INTC1_ICR13         MCF_REG08(0xFC04C04D)
+#define MCF_INTC1_ICR14         MCF_REG08(0xFC04C04E)
+#define MCF_INTC1_ICR15         MCF_REG08(0xFC04C04F)
+#define MCF_INTC1_ICR16         MCF_REG08(0xFC04C050)
+#define MCF_INTC1_ICR17         MCF_REG08(0xFC04C051)
+#define MCF_INTC1_ICR18         MCF_REG08(0xFC04C052)
+#define MCF_INTC1_ICR19         MCF_REG08(0xFC04C053)
+#define MCF_INTC1_ICR20         MCF_REG08(0xFC04C054)
+#define MCF_INTC1_ICR21         MCF_REG08(0xFC04C055)
+#define MCF_INTC1_ICR22         MCF_REG08(0xFC04C056)
+#define MCF_INTC1_ICR23         MCF_REG08(0xFC04C057)
+#define MCF_INTC1_ICR24         MCF_REG08(0xFC04C058)
+#define MCF_INTC1_ICR25         MCF_REG08(0xFC04C059)
+#define MCF_INTC1_ICR26         MCF_REG08(0xFC04C05A)
+#define MCF_INTC1_ICR27         MCF_REG08(0xFC04C05B)
+#define MCF_INTC1_ICR28         MCF_REG08(0xFC04C05C)
+#define MCF_INTC1_ICR29         MCF_REG08(0xFC04C05D)
+#define MCF_INTC1_ICR30         MCF_REG08(0xFC04C05E)
+#define MCF_INTC1_ICR31         MCF_REG08(0xFC04C05F)
+#define MCF_INTC1_ICR32         MCF_REG08(0xFC04C060)
+#define MCF_INTC1_ICR33         MCF_REG08(0xFC04C061)
+#define MCF_INTC1_ICR34         MCF_REG08(0xFC04C062)
+#define MCF_INTC1_ICR35         MCF_REG08(0xFC04C063)
+#define MCF_INTC1_ICR36         MCF_REG08(0xFC04C064)
+#define MCF_INTC1_ICR37         MCF_REG08(0xFC04C065)
+#define MCF_INTC1_ICR38         MCF_REG08(0xFC04C066)
+#define MCF_INTC1_ICR39         MCF_REG08(0xFC04C067)
+#define MCF_INTC1_ICR40         MCF_REG08(0xFC04C068)
+#define MCF_INTC1_ICR41         MCF_REG08(0xFC04C069)
+#define MCF_INTC1_ICR42         MCF_REG08(0xFC04C06A)
+#define MCF_INTC1_ICR43         MCF_REG08(0xFC04C06B)
+#define MCF_INTC1_ICR44         MCF_REG08(0xFC04C06C)
+#define MCF_INTC1_ICR45         MCF_REG08(0xFC04C06D)
+#define MCF_INTC1_ICR46         MCF_REG08(0xFC04C06E)
+#define MCF_INTC1_ICR47         MCF_REG08(0xFC04C06F)
+#define MCF_INTC1_ICR48         MCF_REG08(0xFC04C070)
+#define MCF_INTC1_ICR49         MCF_REG08(0xFC04C071)
+#define MCF_INTC1_ICR50         MCF_REG08(0xFC04C072)
+#define MCF_INTC1_ICR51         MCF_REG08(0xFC04C073)
+#define MCF_INTC1_ICR52         MCF_REG08(0xFC04C074)
+#define MCF_INTC1_ICR53         MCF_REG08(0xFC04C075)
+#define MCF_INTC1_ICR54         MCF_REG08(0xFC04C076)
+#define MCF_INTC1_ICR55         MCF_REG08(0xFC04C077)
+#define MCF_INTC1_ICR56         MCF_REG08(0xFC04C078)
+#define MCF_INTC1_ICR57         MCF_REG08(0xFC04C079)
+#define MCF_INTC1_ICR58         MCF_REG08(0xFC04C07A)
+#define MCF_INTC1_ICR59         MCF_REG08(0xFC04C07B)
+#define MCF_INTC1_ICR60         MCF_REG08(0xFC04C07C)
+#define MCF_INTC1_ICR61         MCF_REG08(0xFC04C07D)
+#define MCF_INTC1_ICR62         MCF_REG08(0xFC04C07E)
+#define MCF_INTC1_ICR63         MCF_REG08(0xFC04C07F)
+#define MCF_INTC1_SWIACK        MCF_REG08(0xFC04C0E0)
+#define MCF_INTC1_L1IACK        MCF_REG08(0xFC04C0E4)
+#define MCF_INTC1_L2IACK        MCF_REG08(0xFC04C0E8)
+#define MCF_INTC1_L3IACK        MCF_REG08(0xFC04C0EC)
+#define MCF_INTC1_L4IACK        MCF_REG08(0xFC04C0F0)
+#define MCF_INTC1_L5IACK        MCF_REG08(0xFC04C0F4)
+#define MCF_INTC1_L6IACK        MCF_REG08(0xFC04C0F8
+#define MCF_INTC1_L7IACK        MCF_REG08(0xFC04C0FC)
+
+/* Parameterized register read/write macros for multiple registers */
+#define MCF_INTC0_ICR(x)        MCF_REG08(0xFC048041+((x-1)*0x001))
+#define MCF_INTC0_LIACK(x)      MCF_REG08(0xFC0480E4+((x-1)*0x004))
+#define MCF_INTC1_ICR(x)        MCF_REG08(0xFC04C041+((x-1)*0x001))
+#define MCF_INTC1_LIACK(x)      MCF_REG08(0xFC04C0E4+((x-1)*0x004))
+
+/* Parameterized register read/write macros for multiple modules */
+#define MCF_INTC_IPRH(x)        MCF_REG32(0xFC048000+((x)*0x4000))
+#define MCF_INTC_IPRL(x)        MCF_REG32(0xFC048004+((x)*0x4000))
+#define MCF_INTC_IMRH(x)        MCF_REG32(0xFC048008+((x)*0x4000))
+#define MCF_INTC_IMRL(x)        MCF_REG32(0xFC04800C+((x)*0x4000))
+#define MCF_INTC_INTFRCH(x)     MCF_REG32(0xFC048010+((x)*0x4000))
+#define MCF_INTC_INTFRCL(x)     MCF_REG32(0xFC048014+((x)*0x4000))
+#define MCF_INTC_ICONFIG(x)     MCF_REG16(0xFC04801A+((x)*0x4000))
+#define MCF_INTC_SIMR(x)        MCF_REG08(0xFC04801C+((x)*0x4000))
+#define MCF_INTC_CIMR(x)        MCF_REG08(0xFC04801D+((x)*0x4000))
+#define MCF_INTC_CLMASK(x)      MCF_REG08(0xFC04801E+((x)*0x4000))
+#define MCF_INTC_SLMASK(x)      MCF_REG08(0xFC04801F+((x)*0x4000))
+#define MCF_INTC_ICR1(x)        MCF_REG08(0xFC048041+((x)*0x4000))
+#define MCF_INTC_ICR2(x)        MCF_REG08(0xFC048042+((x)*0x4000))
+#define MCF_INTC_ICR3(x)        MCF_REG08(0xFC048043+((x)*0x4000))
+#define MCF_INTC_ICR4(x)        MCF_REG08(0xFC048044+((x)*0x4000))
+#define MCF_INTC_ICR5(x)        MCF_REG08(0xFC048045+((x)*0x4000))
+#define MCF_INTC_ICR6(x)        MCF_REG08(0xFC048046+((x)*0x4000))
+#define MCF_INTC_ICR7(x)        MCF_REG08(0xFC048047+((x)*0x4000))
+#define MCF_INTC_ICR8(x)        MCF_REG08(0xFC048048+((x)*0x4000))
+#define MCF_INTC_ICR9(x)        MCF_REG08(0xFC048049+((x)*0x4000))
+#define MCF_INTC_ICR10(x)       MCF_REG08(0xFC04804A+((x)*0x4000))
+#define MCF_INTC_ICR11(x)       MCF_REG08(0xFC04804B+((x)*0x4000))
+#define MCF_INTC_ICR12(x)       MCF_REG08(0xFC04804C+((x)*0x4000))
+#define MCF_INTC_ICR13(x)       MCF_REG08(0xFC04804D+((x)*0x4000))
+#define MCF_INTC_ICR14(x)       MCF_REG08(0xFC04804E+((x)*0x4000))
+#define MCF_INTC_ICR15(x)       MCF_REG08(0xFC04804F+((x)*0x4000))
+#define MCF_INTC_ICR16(x)       MCF_REG08(0xFC048050+((x)*0x4000))
+#define MCF_INTC_ICR17(x)       MCF_REG08(0xFC048051+((x)*0x4000))
+#define MCF_INTC_ICR18(x)       MCF_REG08(0xFC048052+((x)*0x4000))
+#define MCF_INTC_ICR19(x)       MCF_REG08(0xFC048053+((x)*0x4000))
+#define MCF_INTC_ICR20(x)       MCF_REG08(0xFC048054+((x)*0x4000))
+#define MCF_INTC_ICR21(x)       MCF_REG08(0xFC048055+((x)*0x4000))
+#define MCF_INTC_ICR22(x)       MCF_REG08(0xFC048056+((x)*0x4000))
+#define MCF_INTC_ICR23(x)       MCF_REG08(0xFC048057+((x)*0x4000))
+#define MCF_INTC_ICR24(x)       MCF_REG08(0xFC048058+((x)*0x4000))
+#define MCF_INTC_ICR25(x)       MCF_REG08(0xFC048059+((x)*0x4000))
+#define MCF_INTC_ICR26(x)       MCF_REG08(0xFC04805A+((x)*0x4000))
+#define MCF_INTC_ICR27(x)       MCF_REG08(0xFC04805B+((x)*0x4000))
+#define MCF_INTC_ICR28(x)       MCF_REG08(0xFC04805C+((x)*0x4000))
+#define MCF_INTC_ICR29(x)       MCF_REG08(0xFC04805D+((x)*0x4000))
+#define MCF_INTC_ICR30(x)       MCF_REG08(0xFC04805E+((x)*0x4000))
+#define MCF_INTC_ICR31(x)       MCF_REG08(0xFC04805F+((x)*0x4000))
+#define MCF_INTC_ICR32(x)       MCF_REG08(0xFC048060+((x)*0x4000))
+#define MCF_INTC_ICR33(x)       MCF_REG08(0xFC048061+((x)*0x4000))
+#define MCF_INTC_ICR34(x)       MCF_REG08(0xFC048062+((x)*0x4000))
+#define MCF_INTC_ICR35(x)       MCF_REG08(0xFC048063+((x)*0x4000))
+#define MCF_INTC_ICR36(x)       MCF_REG08(0xFC048064+((x)*0x4000))
+#define MCF_INTC_ICR37(x)       MCF_REG08(0xFC048065+((x)*0x4000))
+#define MCF_INTC_ICR38(x)       MCF_REG08(0xFC048066+((x)*0x4000))
+#define MCF_INTC_ICR39(x)       MCF_REG08(0xFC048067+((x)*0x4000))
+#define MCF_INTC_ICR40(x)       MCF_REG08(0xFC048068+((x)*0x4000))
+#define MCF_INTC_ICR41(x)       MCF_REG08(0xFC048069+((x)*0x4000))
+#define MCF_INTC_ICR42(x)       MCF_REG08(0xFC04806A+((x)*0x4000))
+#define MCF_INTC_ICR43(x)       MCF_REG08(0xFC04806B+((x)*0x4000))
+#define MCF_INTC_ICR44(x)       MCF_REG08(0xFC04806C+((x)*0x4000))
+#define MCF_INTC_ICR45(x)       MCF_REG08(0xFC04806D+((x)*0x4000))
+#define MCF_INTC_ICR46(x)       MCF_REG08(0xFC04806E+((x)*0x4000))
+#define MCF_INTC_ICR47(x)       MCF_REG08(0xFC04806F+((x)*0x4000))
+#define MCF_INTC_ICR48(x)       MCF_REG08(0xFC048070+((x)*0x4000))
+#define MCF_INTC_ICR49(x)       MCF_REG08(0xFC048071+((x)*0x4000))
+#define MCF_INTC_ICR50(x)       MCF_REG08(0xFC048072+((x)*0x4000))
+#define MCF_INTC_ICR51(x)       MCF_REG08(0xFC048073+((x)*0x4000))
+#define MCF_INTC_ICR52(x)       MCF_REG08(0xFC048074+((x)*0x4000))
+#define MCF_INTC_ICR53(x)       MCF_REG08(0xFC048075+((x)*0x4000))
+#define MCF_INTC_ICR54(x)       MCF_REG08(0xFC048076+((x)*0x4000))
+#define MCF_INTC_ICR55(x)       MCF_REG08(0xFC048077+((x)*0x4000))
+#define MCF_INTC_ICR56(x)       MCF_REG08(0xFC048078+((x)*0x4000))
+#define MCF_INTC_ICR57(x)       MCF_REG08(0xFC048079+((x)*0x4000))
+#define MCF_INTC_ICR58(x)       MCF_REG08(0xFC04807A+((x)*0x4000))
+#define MCF_INTC_ICR59(x)       MCF_REG08(0xFC04807B+((x)*0x4000))
+#define MCF_INTC_ICR60(x)       MCF_REG08(0xFC04807C+((x)*0x4000))
+#define MCF_INTC_ICR61(x)       MCF_REG08(0xFC04807D+((x)*0x4000))
+#define MCF_INTC_ICR62(x)       MCF_REG08(0xFC04807E+((x)*0x4000))
+#define MCF_INTC_ICR63(x)       MCF_REG08(0xFC04807F+((x)*0x4000))
+#define MCF_INTC_SWIACK(x)      MCF_REG08(0xFC0480E0+((x)*0x4000))
+#define MCF_INTC_L1IACK(x)      MCF_REG08(0xFC0480E4+((x)*0x4000))
+#define MCF_INTC_L2IACK(x)      MCF_REG08(0xFC0480E8+((x)*0x4000))
+#define MCF_INTC_L3IACK(x)      MCF_REG08(0xFC0480EC+((x)*0x4000))
+#define MCF_INTC_L4IACK(x)      MCF_REG08(0xFC0480F0+((x)*0x4000))
+#define MCF_INTC_L5IACK(x)      MCF_REG08(0xFC0480F4+((x)*0x4000))
+#define MCF_INTC_L6IACK(x)      MCF_REG08(0xFC0480F8+((x)*0x4000))
+#define MCF_INTC_L7IACK(x)      MCF_REG08(0xFC0480FC+((x)*0x4000))
+
+/* Bit definitions and macros for IPRH */
+#define MCF_INTC_IPRH_INT32     (0x00000001)
+#define MCF_INTC_IPRH_INT33     (0x00000002)
+#define MCF_INTC_IPRH_INT34     (0x00000004)
+#define MCF_INTC_IPRH_INT35     (0x00000008)
+#define MCF_INTC_IPRH_INT36     (0x00000010)
+#define MCF_INTC_IPRH_INT37     (0x00000020)
+#define MCF_INTC_IPRH_INT38     (0x00000040)
+#define MCF_INTC_IPRH_INT39     (0x00000080)
+#define MCF_INTC_IPRH_INT40     (0x00000100)
+#define MCF_INTC_IPRH_INT41     (0x00000200)
+#define MCF_INTC_IPRH_INT42     (0x00000400)
+#define MCF_INTC_IPRH_INT43     (0x00000800)
+#define MCF_INTC_IPRH_INT44     (0x00001000)
+#define MCF_INTC_IPRH_INT45     (0x00002000)
+#define MCF_INTC_IPRH_INT46     (0x00004000)
+#define MCF_INTC_IPRH_INT47     (0x00008000)
+#define MCF_INTC_IPRH_INT48     (0x00010000)
+#define MCF_INTC_IPRH_INT49     (0x00020000)
+#define MCF_INTC_IPRH_INT50     (0x00040000)
+#define MCF_INTC_IPRH_INT51     (0x00080000)
+#define MCF_INTC_IPRH_INT52     (0x00100000)
+#define MCF_INTC_IPRH_INT53     (0x00200000)
+#define MCF_INTC_IPRH_INT54     (0x00400000)
+#define MCF_INTC_IPRH_INT55     (0x00800000)
+#define MCF_INTC_IPRH_INT56     (0x01000000)
+#define MCF_INTC_IPRH_INT57     (0x02000000)
+#define MCF_INTC_IPRH_INT58     (0x04000000)
+#define MCF_INTC_IPRH_INT59     (0x08000000)
+#define MCF_INTC_IPRH_INT60     (0x10000000)
+#define MCF_INTC_IPRH_INT61     (0x20000000)
+#define MCF_INTC_IPRH_INT62     (0x40000000)
+#define MCF_INTC_IPRH_INT63     (0x80000000)
+
+/* Bit definitions and macros for IPRL */
+#define MCF_INTC_IPRL_INT0      (0x00000001)
+#define MCF_INTC_IPRL_INT1      (0x00000002)
+#define MCF_INTC_IPRL_INT2      (0x00000004)
+#define MCF_INTC_IPRL_INT3      (0x00000008)
+#define MCF_INTC_IPRL_INT4      (0x00000010)
+#define MCF_INTC_IPRL_INT5      (0x00000020)
+#define MCF_INTC_IPRL_INT6      (0x00000040)
+#define MCF_INTC_IPRL_INT7      (0x00000080)
+#define MCF_INTC_IPRL_INT8      (0x00000100)
+#define MCF_INTC_IPRL_INT9      (0x00000200)
+#define MCF_INTC_IPRL_INT10     (0x00000400)
+#define MCF_INTC_IPRL_INT11     (0x00000800)
+#define MCF_INTC_IPRL_INT12     (0x00001000)
+#define MCF_INTC_IPRL_INT13     (0x00002000)
+#define MCF_INTC_IPRL_INT14     (0x00004000)
+#define MCF_INTC_IPRL_INT15     (0x00008000)
+#define MCF_INTC_IPRL_INT16     (0x00010000)
+#define MCF_INTC_IPRL_INT17     (0x00020000)
+#define MCF_INTC_IPRL_INT18     (0x00040000)
+#define MCF_INTC_IPRL_INT19     (0x00080000)
+#define MCF_INTC_IPRL_INT20     (0x00100000)
+#define MCF_INTC_IPRL_INT21     (0x00200000)
+#define MCF_INTC_IPRL_INT22     (0x00400000)
+#define MCF_INTC_IPRL_INT23     (0x00800000)
+#define MCF_INTC_IPRL_INT24     (0x01000000)
+#define MCF_INTC_IPRL_INT25     (0x02000000)
+#define MCF_INTC_IPRL_INT26     (0x04000000)
+#define MCF_INTC_IPRL_INT27     (0x08000000)
+#define MCF_INTC_IPRL_INT28     (0x10000000)
+#define MCF_INTC_IPRL_INT29     (0x20000000)
+#define MCF_INTC_IPRL_INT30     (0x40000000)
+#define MCF_INTC_IPRL_INT31     (0x80000000)
+
+/* Bit definitions and macros for IMRH */
+#define MCF_INTC_IMRH_INT_MASK32    (0x00000001)
+#define MCF_INTC_IMRH_INT_MASK33    (0x00000002)
+#define MCF_INTC_IMRH_INT_MASK34    (0x00000004)
+#define MCF_INTC_IMRH_INT_MASK35    (0x00000008)
+#define MCF_INTC_IMRH_INT_MASK36    (0x00000010)
+#define MCF_INTC_IMRH_INT_MASK37    (0x00000020)
+#define MCF_INTC_IMRH_INT_MASK38    (0x00000040)
+#define MCF_INTC_IMRH_INT_MASK39    (0x00000080)
+#define MCF_INTC_IMRH_INT_MASK40    (0x00000100)
+#define MCF_INTC_IMRH_INT_MASK41    (0x00000200)
+#define MCF_INTC_IMRH_INT_MASK42    (0x00000400)
+#define MCF_INTC_IMRH_INT_MASK43    (0x00000800)
+#define MCF_INTC_IMRH_INT_MASK44    (0x00001000)
+#define MCF_INTC_IMRH_INT_MASK45    (0x00002000)
+#define MCF_INTC_IMRH_INT_MASK46    (0x00004000)
+#define MCF_INTC_IMRH_INT_MASK47    (0x00008000)
+#define MCF_INTC_IMRH_INT_MASK48    (0x00010000)
+#define MCF_INTC_IMRH_INT_MASK49    (0x00020000)
+#define MCF_INTC_IMRH_INT_MASK50    (0x00040000)
+#define MCF_INTC_IMRH_INT_MASK51    (0x00080000)
+#define MCF_INTC_IMRH_INT_MASK52    (0x00100000)
+#define MCF_INTC_IMRH_INT_MASK53    (0x00200000)
+#define MCF_INTC_IMRH_INT_MASK54    (0x00400000)
+#define MCF_INTC_IMRH_INT_MASK55    (0x00800000)
+#define MCF_INTC_IMRH_INT_MASK56    (0x01000000)
+#define MCF_INTC_IMRH_INT_MASK57    (0x02000000)
+#define MCF_INTC_IMRH_INT_MASK58    (0x04000000)
+#define MCF_INTC_IMRH_INT_MASK59    (0x08000000)
+#define MCF_INTC_IMRH_INT_MASK60    (0x10000000)
+#define MCF_INTC_IMRH_INT_MASK61    (0x20000000)
+#define MCF_INTC_IMRH_INT_MASK62    (0x40000000)
+#define MCF_INTC_IMRH_INT_MASK63    (0x80000000)
+
+/* Bit definitions and macros for IMRL */
+#define MCF_INTC_IMRL_INT_MASK0     (0x00000001)
+#define MCF_INTC_IMRL_INT_MASK1     (0x00000002)
+#define MCF_INTC_IMRL_INT_MASK2     (0x00000004)
+#define MCF_INTC_IMRL_INT_MASK3     (0x00000008)
+#define MCF_INTC_IMRL_INT_MASK4     (0x00000010)
+#define MCF_INTC_IMRL_INT_MASK5     (0x00000020)
+#define MCF_INTC_IMRL_INT_MASK6     (0x00000040)
+#define MCF_INTC_IMRL_INT_MASK7     (0x00000080)
+#define MCF_INTC_IMRL_INT_MASK8     (0x00000100)
+#define MCF_INTC_IMRL_INT_MASK9     (0x00000200)
+#define MCF_INTC_IMRL_INT_MASK10    (0x00000400)
+#define MCF_INTC_IMRL_INT_MASK11    (0x00000800)
+#define MCF_INTC_IMRL_INT_MASK12    (0x00001000)
+#define MCF_INTC_IMRL_INT_MASK13    (0x00002000)
+#define MCF_INTC_IMRL_INT_MASK14    (0x00004000)
+#define MCF_INTC_IMRL_INT_MASK15    (0x00008000)
+#define MCF_INTC_IMRL_INT_MASK16    (0x00010000)
+#define MCF_INTC_IMRL_INT_MASK17    (0x00020000)
+#define MCF_INTC_IMRL_INT_MASK18    (0x00040000)
+#define MCF_INTC_IMRL_INT_MASK19    (0x00080000)
+#define MCF_INTC_IMRL_INT_MASK20    (0x00100000)
+#define MCF_INTC_IMRL_INT_MASK21    (0x00200000)
+#define MCF_INTC_IMRL_INT_MASK22    (0x00400000)
+#define MCF_INTC_IMRL_INT_MASK23    (0x00800000)
+#define MCF_INTC_IMRL_INT_MASK24    (0x01000000)
+#define MCF_INTC_IMRL_INT_MASK25    (0x02000000)
+#define MCF_INTC_IMRL_INT_MASK26    (0x04000000)
+#define MCF_INTC_IMRL_INT_MASK27    (0x08000000)
+#define MCF_INTC_IMRL_INT_MASK28    (0x10000000)
+#define MCF_INTC_IMRL_INT_MASK29    (0x20000000)
+#define MCF_INTC_IMRL_INT_MASK30    (0x40000000)
+#define MCF_INTC_IMRL_INT_MASK31    (0x80000000)
+
+/* Bit definitions and macros for INTFRCH */
+#define MCF_INTC_INTFRCH_INTFRC32   (0x00000001)
+#define MCF_INTC_INTFRCH_INTFRC33   (0x00000002)
+#define MCF_INTC_INTFRCH_INTFRC34   (0x00000004)
+#define MCF_INTC_INTFRCH_INTFRC35   (0x00000008)
+#define MCF_INTC_INTFRCH_INTFRC36   (0x00000010)
+#define MCF_INTC_INTFRCH_INTFRC37   (0x00000020)
+#define MCF_INTC_INTFRCH_INTFRC38   (0x00000040)
+#define MCF_INTC_INTFRCH_INTFRC39   (0x00000080)
+#define MCF_INTC_INTFRCH_INTFRC40   (0x00000100)
+#define MCF_INTC_INTFRCH_INTFRC41   (0x00000200)
+#define MCF_INTC_INTFRCH_INTFRC42   (0x00000400)
+#define MCF_INTC_INTFRCH_INTFRC43   (0x00000800)
+#define MCF_INTC_INTFRCH_INTFRC44   (0x00001000)
+#define MCF_INTC_INTFRCH_INTFRC45   (0x00002000)
+#define MCF_INTC_INTFRCH_INTFRC46   (0x00004000)
+#define MCF_INTC_INTFRCH_INTFRC47   (0x00008000)
+#define MCF_INTC_INTFRCH_INTFRC48   (0x00010000)
+#define MCF_INTC_INTFRCH_INTFRC49   (0x00020000)
+#define MCF_INTC_INTFRCH_INTFRC50   (0x00040000)
+#define MCF_INTC_INTFRCH_INTFRC51   (0x00080000)
+#define MCF_INTC_INTFRCH_INTFRC52   (0x00100000)
+#define MCF_INTC_INTFRCH_INTFRC53   (0x00200000)
+#define MCF_INTC_INTFRCH_INTFRC54   (0x00400000)
+#define MCF_INTC_INTFRCH_INTFRC55   (0x00800000)
+#define MCF_INTC_INTFRCH_INTFRC56   (0x01000000)
+#define MCF_INTC_INTFRCH_INTFRC57   (0x02000000)
+#define MCF_INTC_INTFRCH_INTFRC58   (0x04000000)
+#define MCF_INTC_INTFRCH_INTFRC59   (0x08000000)
+#define MCF_INTC_INTFRCH_INTFRC60   (0x10000000)
+#define MCF_INTC_INTFRCH_INTFRC61   (0x20000000)
+#define MCF_INTC_INTFRCH_INTFRC62   (0x40000000)
+#define MCF_INTC_INTFRCH_INTFRC63   (0x80000000)
+
+/* Bit definitions and macros for INTFRCL */
+#define MCF_INTC_INTFRCL_INTFRC0    (0x00000001)
+#define MCF_INTC_INTFRCL_INTFRC1    (0x00000002)
+#define MCF_INTC_INTFRCL_INTFRC2    (0x00000004)
+#define MCF_INTC_INTFRCL_INTFRC3    (0x00000008)
+#define MCF_INTC_INTFRCL_INTFRC4    (0x00000010)
+#define MCF_INTC_INTFRCL_INTFRC5    (0x00000020)
+#define MCF_INTC_INTFRCL_INTFRC6    (0x00000040)
+#define MCF_INTC_INTFRCL_INTFRC7    (0x00000080)
+#define MCF_INTC_INTFRCL_INTFRC8    (0x00000100)
+#define MCF_INTC_INTFRCL_INTFRC9    (0x00000200)
+#define MCF_INTC_INTFRCL_INTFRC10   (0x00000400)
+#define MCF_INTC_INTFRCL_INTFRC11   (0x00000800)
+#define MCF_INTC_INTFRCL_INTFRC12   (0x00001000)
+#define MCF_INTC_INTFRCL_INTFRC13   (0x00002000)
+#define MCF_INTC_INTFRCL_INTFRC14   (0x00004000)
+#define MCF_INTC_INTFRCL_INTFRC15   (0x00008000)
+#define MCF_INTC_INTFRCL_INTFRC16   (0x00010000)
+#define MCF_INTC_INTFRCL_INTFRC17   (0x00020000)
+#define MCF_INTC_INTFRCL_INTFRC18   (0x00040000)
+#define MCF_INTC_INTFRCL_INTFRC19   (0x00080000)
+#define MCF_INTC_INTFRCL_INTFRC20   (0x00100000)
+#define MCF_INTC_INTFRCL_INTFRC21   (0x00200000)
+#define MCF_INTC_INTFRCL_INTFRC22   (0x00400000)
+#define MCF_INTC_INTFRCL_INTFRC23   (0x00800000)
+#define MCF_INTC_INTFRCL_INTFRC24   (0x01000000)
+#define MCF_INTC_INTFRCL_INTFRC25   (0x02000000)
+#define MCF_INTC_INTFRCL_INTFRC26   (0x04000000)
+#define MCF_INTC_INTFRCL_INTFRC27   (0x08000000)
+#define MCF_INTC_INTFRCL_INTFRC28   (0x10000000)
+#define MCF_INTC_INTFRCL_INTFRC29   (0x20000000)
+#define MCF_INTC_INTFRCL_INTFRC30   (0x40000000)
+#define MCF_INTC_INTFRCL_INTFRC31   (0x80000000)
+
+/* Bit definitions and macros for ICONFIG */
+#define MCF_INTC_ICONFIG_EMASK      (0x0020)
+#define MCF_INTC_ICONFIG_ELVLPRI1   (0x0200)
+#define MCF_INTC_ICONFIG_ELVLPRI2   (0x0400)
+#define MCF_INTC_ICONFIG_ELVLPRI3   (0x0800)
+#define MCF_INTC_ICONFIG_ELVLPRI4   (0x1000)
+#define MCF_INTC_ICONFIG_ELVLPRI5   (0x2000)
+#define MCF_INTC_ICONFIG_ELVLPRI6   (0x4000)
+#define MCF_INTC_ICONFIG_ELVLPRI7   (0x8000)
+
+/* Bit definitions and macros for SIMR */
+#define MCF_INTC_SIMR_SIMR(x)   (((x)&0x7F))
+
+/* Bit definitions and macros for CIMR */
+#define MCF_INTC_CIMR_CIMR(x)   (((x)&0x7F))
+
+/* Bit definitions and macros for CLMASK */
+#define MCF_INTC_CLMASK_CLMASK(x)   (((x)&0x0F))
+
+/* Bit definitions and macros for SLMASK */
+#define MCF_INTC_SLMASK_SLMASK(x)   (((x)&0x0F))
+
+/* Bit definitions and macros for ICR group */
+#define MCF_INTC_ICR_IL(x)      (((x)&0x07))
+
+/* Bit definitions and macros for ICR1 */
+#define MCF_INTC_ICR1_IL(x)     (((x)&0x07))
+
+/* Bit definitions and macros for ICR2 */
+#define MCF_INTC_ICR2_IL(x)     (((x)&0x07))
+
+/* Bit definitions and macros for ICR3 */
+#define MCF_INTC_ICR3_IL(x)     (((x)&0x07))
+
+/* Bit definitions and macros for ICR4 */
+#define MCF_INTC_ICR4_IL(x)     (((x)&0x07))
+
+/* Bit definitions and macros for ICR5 */
+#define MCF_INTC_ICR5_IL(x)     (((x)&0x07))
+
+/* Bit definitions and macros for ICR6 */
+#define MCF_INTC_ICR6_IL(x)     (((x)&0x07))
+
+/* Bit definitions and macros for ICR7 */
+#define MCF_INTC_ICR7_IL(x)     (((x)&0x07))
+
+/* Bit definitions and macros for ICR8 */
+#define MCF_INTC_ICR8_IL(x)     (((x)&0x07))
+
+/* Bit definitions and macros for ICR9 */
+#define MCF_INTC_ICR9_IL(x)     (((x)&0x07))
+
+/* Bit definitions and macros for ICR10 */
+#define MCF_INTC_ICR10_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR11 */
+#define MCF_INTC_ICR11_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR12 */
+#define MCF_INTC_ICR12_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR13 */
+#define MCF_INTC_ICR13_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR14 */
+#define MCF_INTC_ICR14_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR15 */
+#define MCF_INTC_ICR15_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR16 */
+#define MCF_INTC_ICR16_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR17 */
+#define MCF_INTC_ICR17_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR18 */
+#define MCF_INTC_ICR18_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR19 */
+#define MCF_INTC_ICR19_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR20 */
+#define MCF_INTC_ICR20_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR21 */
+#define MCF_INTC_ICR21_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR22 */
+#define MCF_INTC_ICR22_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR23 */
+#define MCF_INTC_ICR23_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR24 */
+#define MCF_INTC_ICR24_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR25 */
+#define MCF_INTC_ICR25_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR26 */
+#define MCF_INTC_ICR26_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR27 */
+#define MCF_INTC_ICR27_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR28 */
+#define MCF_INTC_ICR28_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR29 */
+#define MCF_INTC_ICR29_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR30 */
+#define MCF_INTC_ICR30_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR31 */
+#define MCF_INTC_ICR31_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR32 */
+#define MCF_INTC_ICR32_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR33 */
+#define MCF_INTC_ICR33_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR34 */
+#define MCF_INTC_ICR34_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR35 */
+#define MCF_INTC_ICR35_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR36 */
+#define MCF_INTC_ICR36_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR37 */
+#define MCF_INTC_ICR37_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR38 */
+#define MCF_INTC_ICR38_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR39 */
+#define MCF_INTC_ICR39_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR40 */
+#define MCF_INTC_ICR40_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR41 */
+#define MCF_INTC_ICR41_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR42 */
+#define MCF_INTC_ICR42_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR43 */
+#define MCF_INTC_ICR43_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR44 */
+#define MCF_INTC_ICR44_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR45 */
+#define MCF_INTC_ICR45_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR46 */
+#define MCF_INTC_ICR46_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR47 */
+#define MCF_INTC_ICR47_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR48 */
+#define MCF_INTC_ICR48_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR49 */
+#define MCF_INTC_ICR49_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR50 */
+#define MCF_INTC_ICR50_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR51 */
+#define MCF_INTC_ICR51_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR52 */
+#define MCF_INTC_ICR52_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR53 */
+#define MCF_INTC_ICR53_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR54 */
+#define MCF_INTC_ICR54_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR55 */
+#define MCF_INTC_ICR55_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR56 */
+#define MCF_INTC_ICR56_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR57 */
+#define MCF_INTC_ICR57_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR58 */
+#define MCF_INTC_ICR58_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR59 */
+#define MCF_INTC_ICR59_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR60 */
+#define MCF_INTC_ICR60_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR61 */
+#define MCF_INTC_ICR61_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR62 */
+#define MCF_INTC_ICR62_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for ICR63 */
+#define MCF_INTC_ICR63_IL(x)    (((x)&0x07))
+
+/* Bit definitions and macros for SWIACK */
+#define MCF_INTC_SWIACK_VECTOR(x)   (x)
+
+/* Bit definitions and macros for LIACK group */
+#define MCF_INTC_LIACK_VECTOR(x)    (x)
+
+/* Bit definitions and macros for L1IACK */
+#define MCF_INTC_L1IACK_VECTOR(x)   (x)
+
+/* Bit definitions and macros for L2IACK */
+#define MCF_INTC_L2IACK_VECTOR(x)   (x)
+
+/* Bit definitions and macros for L3IACK */
+#define MCF_INTC_L3IACK_VECTOR(x)   (x)
+
+/* Bit definitions and macros for L4IACK */
+#define MCF_INTC_L4IACK_VECTOR(x)   (x)
+
+/* Bit definitions and macros for L5IACK */
+#define MCF_INTC_L5IACK_VECTOR(x)   (x)
+
+/* Bit definitions and macros for L6IACK */
+#define MCF_INTC_L6IACK_VECTOR(x)   (x)
+
+/* Bit definitions and macros for L7IACK */
+#define MCF_INTC_L7IACK_VECTOR(x)   (x)
+
+/********************************************************************/
+
+#endif /* __MCF5445X_INTC_H__ */
--- /dev/null
+++ b/include/asm-m68k/mcf5445x_pci.h
@@ -0,0 +1,238 @@
+/*
+ * Kurt Mahan kmahan@freescale.com
+ *
+ * Copyright Freescale Semiconductor, Inc. 2007
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MCF5445X_PCI_H__
+#define __MCF5445X_PCI_H__
+
+/*********************************************************************
+*
+* PCI Bus Controller (PCI)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PCI_PCIIDR          MCF_REG32(0xFC0A8000)
+#define MCF_PCI_PCISCR          MCF_REG32(0xFC0A8004)
+#define MCF_PCI_PCICCRIR        MCF_REG32(0xFC0A8008)
+#define MCF_PCI_PCICR1          MCF_REG32(0xFC0A800C)
+#define MCF_PCI_PCIBAR0         MCF_REG32(0xFC0A8010)
+#define MCF_PCI_PCIBAR1         MCF_REG32(0xFC0A8014)
+#define MCF_PCI_PCIBAR2         MCF_REG32(0xFC0A8018)
+#define MCF_PCI_PCIBAR3         MCF_REG32(0xFC0A801C)
+#define MCF_PCI_PCIBAR4         MCF_REG32(0xFC0A8020)
+#define MCF_PCI_PCIBAR5         MCF_REG32(0xFC0A8024)
+#define MCF_PCI_PCISID          MCF_REG32(0xFC0A802C)
+#define MCF_PCI_PCICR2          MCF_REG32(0xFC0A803C)
+#define MCF_PCI_PCIGSCR         MCF_REG32(0xFC0A8060)
+#define MCF_PCI_PCITBATR0A      MCF_REG32(0xFC0A8064)
+#define MCF_PCI_PCITBATR1A      MCF_REG32(0xFC0A8068)
+#define MCF_PCI_PCITCR          MCF_REG32(0xFC0A806C)
+#define MCF_PCI_PCIIW0BTAR      MCF_REG32(0xFC0A8070)
+#define MCF_PCI_PCIIW1BTAR      MCF_REG32(0xFC0A8074)
+#define MCF_PCI_PCIIW2BTAR      MCF_REG32(0xFC0A8078)
+#define MCF_PCI_PCIIWCR         MCF_REG32(0xFC0A8080)
+#define MCF_PCI_PCIICR          MCF_REG32(0xFC0A8084)
+#define MCF_PCI_PCIISR          MCF_REG32(0xFC0A8088)
+#define MCF_PCI_PCITCR2         MCF_REG32(0xFC0A808C)
+#define MCF_PCI_PCITBATR0       MCF_REG32(0xFC0A8090)
+#define MCF_PCI_PCITBATR1       MCF_REG32(0xFC0A8094)
+#define MCF_PCI_PCITBATR2       MCF_REG32(0xFC0A8098)
+#define MCF_PCI_PCITBATR3       MCF_REG32(0xFC0A809C)
+#define MCF_PCI_PCITBATR4       MCF_REG32(0xFC0A80A0)
+#define MCF_PCI_PCITBATR5       MCF_REG32(0xFC0A80A4)
+#define MCF_PCI_PCICAR          MCF_REG32(0xFC0A80F8)
+
+/* Parameterized register read/write macros for multiple registers */
+#define MCF_PCI_PCIIWBTAR(x)    MCF_REG32(0xFC0A8070+((x)*0x004))
+
+/* Bit definitions and macros for PCIIDR */
+#define MCF_PCI_PCIIDR_VENDORID(x)      (((x)&0x0000FFFF))
+#define MCF_PCI_PCIIDR_DEVICEID(x)      (((x)&0x0000FFFF)<<16)
+
+/* Bit definitions and macros for PCISCR */
+#define MCF_PCI_PCISCR_M        (0x00000002)
+#define MCF_PCI_PCISCR_B        (0x00000004)
+#define MCF_PCI_PCISCR_SP       (0x00000008)
+#define MCF_PCI_PCISCR_MW       (0x00000010)
+#define MCF_PCI_PCISCR_PER      (0x00000040)
+#define MCF_PCI_PCISCR_S        (0x00000100)
+#define MCF_PCI_PCISCR_F        (0x00000200)
+#define MCF_PCI_PCISCR_C        (0x00100000)
+#define MCF_PCI_PCISCR_66M      (0x00200000)
+#define MCF_PCI_PCISCR_R        (0x00400000)
+#define MCF_PCI_PCISCR_FC       (0x00800000)
+#define MCF_PCI_PCISCR_DP       (0x01000000)
+#define MCF_PCI_PCISCR_DT(x)    (((x)&0x00000003)<<25)
+#define MCF_PCI_PCISCR_TS       (0x08000000)
+#define MCF_PCI_PCISCR_TR       (0x10000000)
+#define MCF_PCI_PCISCR_MA       (0x20000000)
+#define MCF_PCI_PCISCR_SE       (0x40000000)
+#define MCF_PCI_PCISCR_PE       (0x80000000)
+
+/* Bit definitions and macros for PCICCRIR */
+#define MCF_PCI_PCICCRIR_REVID(x)       (((x)&0x000000FF))
+#define MCF_PCI_PCICCRIR_CLASSCODE(x)   (((x)&0x00FFFFFF)<<8)
+
+/* Bit definitions and macros for PCICR1 */
+#define MCF_PCI_PCICR1_CACHELINESIZE(x)     (((x)&0x0000000F))
+#define MCF_PCI_PCICR1_LATTIMER(x)          (((x)&0x000000FF)<<8)
+#define MCF_PCI_PCICR1_HEADERTYPE(x)        (((x)&0x000000FF)<<16)
+#define MCF_PCI_PCICR1_BIST(x)              (((x)&0x000000FF)<<24)
+
+/* Bit definitions and macros for PCIBAR0 */
+#define MCF_PCI_PCIBAR0_IO          (0x00000001)
+#define MCF_PCI_PCIBAR0_RANGE(x)    (((x)&0x00000003)<<1)
+#define MCF_PCI_PCIBAR0_PREF        (0x00000008)
+#define MCF_PCI_PCIBAR0_BAR0(x)     (((x)&0x00003FFF)<<18)
+
+/* Bit definitions and macros for PCIBAR1 */
+#define MCF_PCI_PCIBAR1_IO          (0x00000001)
+#define MCF_PCI_PCIBAR1_PREF        (0x00000008)
+#define MCF_PCI_PCIBAR1_BAR1(x)     (((x)&0x00000FFF)<<20)
+
+/* Bit definitions and macros for PCIBAR2 */
+#define MCF_PCI_PCIBAR2_IO          (0x00000001)
+#define MCF_PCI_PCIBAR2_RANGE(x)    (((x)&0x00000003)<<1)
+#define MCF_PCI_PCIBAR2_PREF        (0x00000008)
+#define MCF_PCI_PCIBAR2_BAR2(x)     (((x)&0x000003FF)<<22)
+
+/* Bit definitions and macros for PCIBAR3 */
+#define MCF_PCI_PCIBAR3_IO          (0x00000001)
+#define MCF_PCI_PCIBAR3_PREF        (0x00000008)
+#define MCF_PCI_PCIBAR3_BAR3(x)     (((x)&0x000000FF)<<24)
+
+/* Bit definitions and macros for PCIBAR4 */
+#define MCF_PCI_PCIBAR4_IO          (0x00000001)
+#define MCF_PCI_PCIBAR4_RANGE(x)    (((x)&0x00000003)<<1)
+#define MCF_PCI_PCIBAR4_PREF        (0x00000008)
+#define MCF_PCI_PCIBAR4_BAR4(x)     (((x)&0x0000001F)<<27)
+
+/* Bit definitions and macros for PCIBAR5 */
+#define MCF_PCI_PCIBAR5_IO          (0x00000001)
+#define MCF_PCI_PCIBAR5_PREF        (0x00000008)
+#define MCF_PCI_PCIBAR5_BAR5(x)     (((x)&0x0000000F)<<28)
+
+/* Bit definitions and macros for PCISID */
+#define MCF_PCI_PCISID_VENDORID(x)      (((x)&0x0000FFFF))
+#define MCF_PCI_PCISID_ID(x)            (((x)&0x0000FFFF)<<16)
+
+/* Bit definitions and macros for PCICR2 */
+#define MCF_PCI_PCICR2_INTLINE(x)   (((x)&0x000000FF))
+#define MCF_PCI_PCICR2_INTPIN(x)    (((x)&0x000000FF)<<8)
+#define MCF_PCI_PCICR2_MINGNT(x)    (((x)&0x000000FF)<<16)
+#define MCF_PCI_PCICR2_MAXLAT(x)    (((x)&0x000000FF)<<24)
+
+/* Bit definitions and macros for PCIGSCR */
+#define MCF_PCI_PCIGSCR_PR      (0x00000001)
+#define MCF_PCI_PCIGSCR_SEE     (0x00001000)
+#define MCF_PCI_PCIGSCR_PEE     (0x00002000)
+#define MCF_PCI_PCIGSCR_SE      (0x10000000)
+#define MCF_PCI_PCIGSCR_PE      (0x20000000)
+
+/* Bit definitions and macros for PCITBATR0A */
+#define MCF_PCI_PCITBATR0A_EN           (0x00000001)
+#define MCF_PCI_PCITBATR0A_BAT0(x)      (((x)&0x00003FFF)<<18)
+
+/* Bit definitions and macros for PCITBATR1A */
+#define MCF_PCI_PCITBATR1A_EN           (0x00000001)
+#define MCF_PCI_PCITBATR1A_BAT1(x)      (((x)&0x00000FFF)<<20)
+
+/* Bit definitions and macros for PCITCR */
+#define MCF_PCI_PCITCR_WCT(x)   (((x)&0x000000FF))
+#define MCF_PCI_PCITCR_WCD      (0x00000100)
+#define MCF_PCI_PCITCR_P        (0x00010000)
+#define MCF_PCI_PCITCR_PID      (0x00020000)
+#define MCF_PCI_PCITCR_LD       (0x01000000)
+
+/* Bit definitions and macros for PCIIWBTAR group */
+#define MCF_PCI_PCIIWBTAR_WBA(x)    ((((x)&0xFF000000)))
+#define MCF_PCI_PCIIWBTAR_WAM(x)    ((((x)&0xFF000000)
+#define MCF_PCI_PCIIWBTAR_WTA(x)    ((((x)&0xFF000000)
+
+/* Bit definitions and macros for PCIIW0BTAR */
+#define MCF_PCI_PCIIW0BTAR_WBA(x)   ((((x)&0xFF000000)))
+#define MCF_PCI_PCIIW0BTAR_WAM(x)   ((((x)&0xFF000000)
+#define MCF_PCI_PCIIW0BTAR_WTA(x)   ((((x)&0xFF000000)
+
+/* Bit definitions and macros for PCIIWCR */
+#define MCF_PCI_PCIIWCR_WINCTRL2(x)             (((x)&0x0000000F)<<8)
+#define MCF_PCI_PCIIWCR_WINCTRL1(x)             (((x)&0x0000000F)<<16)
+#define MCF_PCI_PCIIWCR_WINCTRL0(x)             (((x)&0x0000000F)<<24)
+#define MCF_PCI_PCIIWCR_WINCTRL0_ENABLE         (0x01000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD        (0x01000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE      (0x03000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL       (0x05000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_IO             (0x09000000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD        (0x00010000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_ENABLE         (0x00010000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE      (0x00030000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL       (0x00050000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_IO             (0x00090000)
+#define MCF_PCI_PCIIWCR_WINCTRL2_ENABLE         (0x00000100)
+#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD        (0x00000100)
+#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE      (0x00000300)
+#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL       (0x00000500)
+#define MCF_PCI_PCIIWCR_WINCTRL2_IO             (0x00000900)
+
+/* Bit definitions and macros for PCIICR */
+#define MCF_PCI_PCIICR_MAXRETRY(x)      (((x)&0x000000FF))
+#define MCF_PCI_PCIICR_TAE              (0x01000000)
+#define MCF_PCI_PCIICR_IAE              (0x02000000)
+#define MCF_PCI_PCIICR_REE              (0x04000000)
+
+/* Bit definitions and macros for PCIISR */
+#define MCF_PCI_PCIISR_TA       (0x01000000)
+#define MCF_PCI_PCIISR_IA       (0x02000000)
+#define MCF_PCI_PCIISR_RE       (0x04000000)
+
+/* Bit definitions and macros for PCITCR2 */
+#define MCF_PCI_PCITCR2_CR      (0x00000001)
+#define MCF_PCI_PCITCR2_B0E     (0x00000100)
+#define MCF_PCI_PCITCR2_B1E     (0x00000200)
+#define MCF_PCI_PCITCR2_B2E     (0x00000400)
+#define MCF_PCI_PCITCR2_B3E     (0x00000800)
+#define MCF_PCI_PCITCR2_B4E     (0x00001000)
+#define MCF_PCI_PCITCR2_B5E     (0x00002000)
+
+/* Bit definitions and macros for PCITBATR0 */
+#define MCF_PCI_PCITBATR0_EN        (0x00000001)
+#define MCF_PCI_PCITBATR0_BAT0(x)   (((x)&0x00003FFF)<<18)
+
+/* Bit definitions and macros for PCITBATR1 */
+#define MCF_PCI_PCITBATR1_EN        (0x00000001)
+#define MCF_PCI_PCITBATR1_BAT1(x)   (((x)&0x00000FFF)<<20)
+
+/* Bit definitions and macros for PCITBATR2 */
+#define MCF_PCI_PCITBATR2_EN        (0x00000001)
+#define MCF_PCI_PCITBATR2_BAT2(x)   (((x)&0x000003FF)<<22)
+
+/* Bit definitions and macros for PCITBATR3 */
+#define MCF_PCI_PCITBATR3_EN        (0x00000001)
+#define MCF_PCI_PCITBATR3_BAT3(x)   (((x)&0x000000FF)<<24)
+
+/* Bit definitions and macros for PCITBATR4 */
+#define MCF_PCI_PCITBATR4_EN        (0x00000001)
+#define MCF_PCI_PCITBATR4_BAT4(x)   (((x)&0x0000001F)<<27)
+
+/* Bit definitions and macros for PCITBATR5 */
+#define MCF_PCI_PCITBATR5_EN        (0x00000001)
+#define MCF_PCI_PCITBATR5_BAT5(x)   (((x)&0x0000000F)<<28)
+
+/* Bit definitions and macros for PCICAR */
+#define MCF_PCI_PCICAR_DWORD(x)     ((x)&0x000000FC)
+#define MCF_PCI_PCICAR_FUNCNUM(x)   (((x)&0x00000007)<<8)
+#define MCF_PCI_PCICAR_DEVNUM(x)    (((x)&0x0000001F)<<11)
+#define MCF_PCI_PCICAR_BUSNUM(x)    (((x)&0x000000FF)<<16)
+#define MCF_PCI_PCICAR_E            (0x80000000)
+
+/********************************************************************/
+
+#endif /* __MCF5445X_PCI_H__ */
--- /dev/null
+++ b/include/asm-m68k/mcf5445x_pciarb.h
@@ -0,0 +1,40 @@
+/*
+ * Kurt Mahan kmahan@freescale.com
+ *
+ * Copyright Freescale Semiconductor, Inc. 2007
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MCF5445X_PCIARB_H__
+#define __MCF5445X_PCIARB_H__
+
+/*********************************************************************
+*
+* PCI Arbiter Module (PCIARB)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PCIARB_PACR         	MCF_REG32(0xFC0AC000)
+#define MCF_PCIARB_PASR         	MCF_REG32(0xFC0AC004)
+
+/* Bit definitions and macros for PACR */
+#define MCF_PCIARB_PACR_INTMPRI         (0x00000001)
+#define MCF_PCIARB_PACR_EXTMPRI(x)      (((x)&0x0000001F)<<1)
+#define MCF_PCIARB_PACR_RA              (0x00008000)
+#define MCF_PCIARB_PACR_INTMINTEN       (0x00010000)
+#define MCF_PCIARB_PACR_EXTMINTEN(x)    (((x)&0x0000001F)<<17)
+#define MCF_PCIARB_PACR_PKMD            (0x40000000)
+#define MCF_PCIARB_PACR_DS              (0x80000000)
+
+/* Bit definitions and macros for PASR */
+#define MCF_PCIARB_PASR_ITLMBK      	(0x00010000)
+#define MCF_PCIARB_PASR_EXTMBK(x)   	(((x)&0x0000001F)<<17)
+
+/********************************************************************/
+
+#endif /* __MCF5445X_PCIARB_H__ */
--- /dev/null
+++ b/include/asm-m68k/mcf5445x_sdramc.h
@@ -0,0 +1,115 @@
+/*
+ * Matt Waddel Matt.Waddel@freescale.com
+ *
+ * Copyright Freescale Semiconductor, Inc. 2007
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MCF5445X_SDRAMC_H__
+#define __MCF5445X_SDRAMC_H__
+
+/*********************************************************************
+*
+* SDRAM Controller (SDRAMC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SDRAMC_SDMR         (*(vuint32 *)(0xFC0B8000))   /* SDRAM Mode/Extended Mode Register */
+#define MCF_SDRAMC_SDCR         (*(vuint32 *)(0xFC0B8004))   /* SDRAM Control Register */
+#define MCF_SDRAMC_SDCFG1       (*(vuint32 *)(0xFC0B8008))   /* SDRAM Configuration Register 1 */
+#define MCF_SDRAMC_SDCFG2       (*(vuint32 *)(0xFC0B800C))   /* SDRAM Configuration Register 2 */
+#define MCF_SDRAMC_SDCS0        (*(vuint32 *)(0xFC0B8110))   /* SDRAM Chip Select Register */
+#define MCF_SDRAMC_SDCS1        (*(vuint32 *)(0xFC0B8114))   /* SDRAM Chip Select Register */
+
+/* Parameterized register read/write macros for multiple registers */
+#define MCF_SDRAMC_SDCS(x)      (*(vuint32 *)(0xFC0B8110+((x)*0x004)))   /* SDRAM Chip Select Register */
+
+/* Bit definitions and macros for SDMR */
+#define MCF_SDRAMC_SDMR_DDR2_AD(x)      (((x)&0x00003FFF))      /* Address for DDR2 */
+#define MCF_SDRAMC_SDMR_CMD             (0x00010000)            /* Command */
+#define MCF_SDRAMC_SDMR_AD(x)           (((x)&0x00000FFF)<<18)  /* Address */
+#define MCF_SDRAMC_SDMR_BK(x)           (((x)&0x00000003)<<30)  /* Bank Address */
+#define MCF_SDRAMC_SDMR_BK_LMR          (0x00000000)
+#define MCF_SDRAMC_SDMR_BK_LEMR         (0x40000000)
+
+/* Bit definitions and macros for SDCR */
+#define MCF_SDRAMC_SDCR_DPD             (0x00000001)            /* Deep Power-Down Mode */
+#define MCF_SDRAMC_SDCR_IPALL           (0x00000002)            /* Initiate Precharge All */
+#define MCF_SDRAMC_SDCR_IREF            (0x00000004)            /* Initiate Refresh */
+#define MCF_SDRAMC_SDCR_DQS_OE(x)       (((x)&0x00000003)<<10)  /* DQS Output Enable */
+#define MCF_SDRAMC_SDCR_MEM_PS          (0x00002000)            /* Data Port Size */
+#define MCF_SDRAMC_SDCR_REF_CNT(x)      (((x)&0x0000003F)<<16)  /* Periodic Refresh Counter */
+#define MCF_SDRAMC_SDCR_OE_RULE         (0x00400000)            /* Drive Rule Selection */
+#define MCF_SDRAMC_SDCR_ADDR_MUX(x)     (((x)&0x00000003)<<24)  /* Internal Address Mux Select */
+#define MCF_SDRAMC_SDCR_DDR2_MODE       (0x08000000)            /* DDR2 Mode Select */
+#define MCF_SDRAMC_SDCR_REF_EN          (0x10000000)            /* Refresh Enable */
+#define MCF_SDRAMC_SDCR_DDR_MODE        (0x20000000)            /* DDR Mode Select */
+#define MCF_SDRAMC_SDCR_CKE             (0x40000000)            /* Clock Enable */
+#define MCF_SDRAMC_SDCR_MODE_EN         (0x80000000)            /* SDRAM Mode Register Programming Enable */
+#define MCF_SDRAMC_SDCR_DQS_OE_BOTH     (0x00000C00)
+
+/* Bit definitions and macros for SDCFG1 */
+#define MCF_SDRAMC_SDCFG1_WT_LAT(x)     (((x)&0x00000007)<<4)   /* Write Latency */
+#define MCF_SDRAMC_SDCFG1_REF2ACT(x)    (((x)&0x0000000F)<<8)   /* Refresh to active delay */
+#define MCF_SDRAMC_SDCFG1_PRE2ACT(x)    (((x)&0x00000007)<<12)  /* Precharge to active delay */
+#define MCF_SDRAMC_SDCFG1_ACT2RW(x)     (((x)&0x00000007)<<16)  /* Active to read/write delay */
+#define MCF_SDRAMC_SDCFG1_RD_LAT(x)     (((x)&0x0000000F)<<20)  /* Read CAS Latency */
+#define MCF_SDRAMC_SDCFG1_SWT2RWP(x)    (((x)&0x00000007)<<24)  /* Single write to read/write/precharge delay */
+#define MCF_SDRAMC_SDCFG1_SRD2RWP(x)    (((x)&0x0000000F)<<28)  /* Single read to read/write/precharge delay */
+
+/* Bit definitions and macros for SDCFG2 */
+#define MCF_SDRAMC_SDCFG2_BL(x)         (((x)&0x0000000F)<<16)  /* Burst Length */
+#define MCF_SDRAMC_SDCFG2_BRD2W(x)      (((x)&0x0000000F)<<20)  /* Burst read to write delay */
+#define MCF_SDRAMC_SDCFG2_BWT2RWP(x)    (((x)&0x0000000F)<<24)  /* Burst write to read/write/precharge delay */
+#define MCF_SDRAMC_SDCFG2_BRD2RP(x)     (((x)&0x0000000F)<<28)  /* Burst read to read/precharge delay */
+
+/* Bit definitions and macros for SDCS group */
+#define MCF_SDRAMC_SDCS_CSSZ(x)         (((x)&0x0000001F))      /* Chip-Select Size */
+#define MCF_SDRAMC_SDCS_CSBA(x)         (((x)&0x00000FFF)<<20)  /* Chip-Select Base Address */
+#define MCF_SDRAMC_SDCS_BA(x)           ((x)&0xFFF00000)
+#define MCF_SDRAMC_SDCS_CSSZ_DISABLE    (0x00000000)
+#define MCF_SDRAMC_SDCS_CSSZ_1MBYTE     (0x00000013)
+#define MCF_SDRAMC_SDCS_CSSZ_2MBYTE     (0x00000014)
+#define MCF_SDRAMC_SDCS_CSSZ_4MBYTE     (0x00000015)
+#define MCF_SDRAMC_SDCS_CSSZ_8MBYTE     (0x00000016)
+#define MCF_SDRAMC_SDCS_CSSZ_16MBYTE    (0x00000017)
+#define MCF_SDRAMC_SDCS_CSSZ_32MBYTE    (0x00000018)
+#define MCF_SDRAMC_SDCS_CSSZ_64MBYTE    (0x00000019)
+#define MCF_SDRAMC_SDCS_CSSZ_128MBYTE   (0x0000001A)
+#define MCF_SDRAMC_SDCS_CSSZ_256MBYTE   (0x0000001B)
+#define MCF_SDRAMC_SDCS_CSSZ_512MBYTE   (0x0000001C)
+#define MCF_SDRAMC_SDCS_CSSZ_1GBYTE     (0x0000001D)
+#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE     (0x0000001E)
+#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE     (0x0000001F)
+
+/* Bit definitions and macros for SDCS0 */
+#define MCF_SDRAMC_SDCS0_CSSZ(x)            (((x)&0x0000001F))      /* Chip-Select Size */
+#define MCF_SDRAMC_SDCS0_CSBA(x)            (((x)&0x00000FFF)<<20)  /* Chip-Select Base Address */
+#define MCF_SDRAMC_SDCS0_BA(x)              ((x)&0xFFF00000)
+#define MCF_SDRAMC_SDCS0_CSSZ_DISABLE       (0x00000000)
+#define MCF_SDRAMC_SDCS0_CSSZ_1MBYTE        (0x00000013)
+#define MCF_SDRAMC_SDCS0_CSSZ_2MBYTE        (0x00000014)
+#define MCF_SDRAMC_SDCS0_CSSZ_4MBYTE        (0x00000015)
+#define MCF_SDRAMC_SDCS0_CSSZ_8MBYTE        (0x00000016)
+#define MCF_SDRAMC_SDCS0_CSSZ_16MBYTE       (0x00000017)
+#define MCF_SDRAMC_SDCS0_CSSZ_32MBYTE       (0x00000018)
+#define MCF_SDRAMC_SDCS0_CSSZ_64MBYTE       (0x00000019)
+#define MCF_SDRAMC_SDCS0_CSSZ_128MBYTE      (0x0000001A)
+#define MCF_SDRAMC_SDCS0_CSSZ_256MBYTE      (0x0000001B)
+#define MCF_SDRAMC_SDCS0_CSSZ_512MBYTE      (0x0000001C)
+#define MCF_SDRAMC_SDCS0_CSSZ_1GBYTE        (0x0000001D)
+#define MCF_SDRAMC_SDCS0_CSSZ_2GBYTE        (0x0000001E)
+#define MCF_SDRAMC_SDCS0_CSSZ_4GBYTE        (0x0000001F)
+
+/* Bit definitions and macros for SDCS1 */
+#define MCF_SDRAMC_SDCS1_CSSZ(x)    (((x)&0x0000001F))      /* Chip-Select Size */
+#define MCF_SDRAMC_SDCS1_CSBA(x)    (((x)&0x00000FFF)<<20)  /* Chip-Select Base Address */
+
+/********************************************************************/
+
+#endif /* __MCF5445X_SDRAMC_H__ */
--- /dev/null
+++ b/include/asm-m68k/mcf5445x_ssi.h
@@ -0,0 +1,187 @@
+/*
+ * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
+ *
+ * Copyright Freescale Semiconductor, Inc. 2007
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MCF5445X_SSI_H__
+#define __MCF5445X_SSI_H__
+
+/*********************************************************************
+*
+* Synchronous Serial Interface (SSI)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SSI_TX0             MCF_REG32(0xFC0BC000)
+#define MCF_SSI_TX1             MCF_REG32(0xFC0BC004)
+#define MCF_SSI_RX0             MCF_REG32(0xFC0BC008)
+#define MCF_SSI_RX1             MCF_REG32(0xFC0BC00C)
+#define MCF_SSI_CR              MCF_REG32(0xFC0BC010)
+#define MCF_SSI_ISR             MCF_REG32(0xFC0BC014)
+#define MCF_SSI_IER             MCF_REG32(0xFC0BC018)
+#define MCF_SSI_TCR             MCF_REG32(0xFC0BC01C)
+#define MCF_SSI_RCR             MCF_REG32(0xFC0BC020)
+#define MCF_SSI_CCR             MCF_REG32(0xFC0BC024)
+#define MCF_SSI_FCSR            MCF_REG32(0xFC0BC02C)
+#define MCF_SSI_ACR             MCF_REG32(0xFC0BC038)
+#define MCF_SSI_ACADD           MCF_REG32(0xFC0BC03C)
+#define MCF_SSI_ACDAT           MCF_REG32(0xFC0BC040)
+#define MCF_SSI_ATAG            MCF_REG32(0xFC0BC044)
+#define MCF_SSI_TMASK           MCF_REG32(0xFC0BC048)
+#define MCF_SSI_RMASK           MCF_REG32(0xFC0BC04C)
+
+/* Parameterized register read/write macros for multiple registers */
+#define MCF_SSI_TX(x)           MCF_REG32(0xFC0BC000+((x)*0x004))
+#define MCF_SSI_RX(x)           MCF_REG32(0xFC0BC008+((x)*0x004))
+
+/* Bit definitions and macros for TX group */
+#define MCF_SSI_TX_SSI_TX(x)    (x)
+
+/* Bit definitions and macros for TX0 */
+#define MCF_SSI_TX0_SSI_TX(x)   (x)
+
+/* Bit definitions and macros for TX1 */
+#define MCF_SSI_TX1_SSI_TX(x)   (x)
+
+/* Bit definitions and macros for RX group */
+#define MCF_SSI_RX_SSI_RX(x)    (x)
+
+/* Bit definitions and macros for RX0 */
+#define MCF_SSI_RX0_SSI_RX(x)   (x)
+
+/* Bit definitions and macros for RX1 */
+#define MCF_SSI_RX1_SSI_RX(x)   (x)
+
+/* Bit definitions and macros for CR */
+#define MCF_SSI_CR_SSI_EN       (0x00000001)
+#define MCF_SSI_CR_TE           (0x00000002)
+#define MCF_SSI_CR_RE           (0x00000004)
+#define MCF_SSI_CR_NET          (0x00000008)
+#define MCF_SSI_CR_SYN          (0x00000010)
+#define MCF_SSI_CR_I2S(x)       (((x)&0x00000003)<<5)
+#define MCF_SSI_CR_MCE          (0x00000080)
+#define MCF_SSI_CR_TCH          (0x00000100)
+#define MCF_SSI_CR_CIS          (0x00000200)
+#define MCF_SSI_CR_I2S_NORMAL   (0x00000000)
+#define MCF_SSI_CR_I2S_MASTER   (0x00000020)
+#define MCF_SSI_CR_I2S_SLAVE    (0x00000040)
+
+/* Bit definitions and macros for ISR */
+#define MCF_SSI_ISR_TFE0        (0x00000001)
+#define MCF_SSI_ISR_TFE1        (0x00000002)
+#define MCF_SSI_ISR_RFF0        (0x00000004)
+#define MCF_SSI_ISR_RFF1        (0x00000008)
+#define MCF_SSI_ISR_RLS         (0x00000010)
+#define MCF_SSI_ISR_TLS         (0x00000020)
+#define MCF_SSI_ISR_RFS         (0x00000040)
+#define MCF_SSI_ISR_TFS         (0x00000080)
+#define MCF_SSI_ISR_TUE0        (0x00000100)
+#define MCF_SSI_ISR_TUE1        (0x00000200)
+#define MCF_SSI_ISR_ROE0        (0x00000400)
+#define MCF_SSI_ISR_ROE1        (0x00000800)
+#define MCF_SSI_ISR_TDE0        (0x00001000)
+#define MCF_SSI_ISR_TDE1        (0x00002000)
+#define MCF_SSI_ISR_RDR0        (0x00004000)
+#define MCF_SSI_ISR_RDR1        (0x00008000)
+#define MCF_SSI_ISR_RXT         (0x00010000)
+#define MCF_SSI_ISR_CMDDU       (0x00020000)
+#define MCF_SSI_ISR_CMDAU       (0x00040000)
+
+/* Bit definitions and macros for IER */
+#define MCF_SSI_IER_TFE0        (0x00000001)
+#define MCF_SSI_IER_TFE1        (0x00000002)
+#define MCF_SSI_IER_RFF0        (0x00000004)
+#define MCF_SSI_IER_RFF1        (0x00000008)
+#define MCF_SSI_IER_RLS         (0x00000010)
+#define MCF_SSI_IER_TLS         (0x00000020)
+#define MCF_SSI_IER_RFS         (0x00000040)
+#define MCF_SSI_IER_TFS         (0x00000080)
+#define MCF_SSI_IER_TUE0        (0x00000100)
+#define MCF_SSI_IER_TUE1        (0x00000200)
+#define MCF_SSI_IER_ROE0        (0x00000400)
+#define MCF_SSI_IER_ROE1        (0x00000800)
+#define MCF_SSI_IER_TDE0        (0x00001000)
+#define MCF_SSI_IER_TDE1        (0x00002000)
+#define MCF_SSI_IER_RDR0        (0x00004000)
+#define MCF_SSI_IER_RDR1        (0x00008000)
+#define MCF_SSI_IER_RXT         (0x00010000)
+#define MCF_SSI_IER_CMDU        (0x00020000)
+#define MCF_SSI_IER_CMDAU       (0x00040000)
+#define MCF_SSI_IER_TIE         (0x00080000)
+#define MCF_SSI_IER_TDMAE       (0x00100000)
+#define MCF_SSI_IER_RIE         (0x00200000)
+#define MCF_SSI_IER_RDMAE       (0x00400000)
+
+/* Bit definitions and macros for TCR */
+#define MCF_SSI_TCR_TEFS        (0x00000001)
+#define MCF_SSI_TCR_TFSL        (0x00000002)
+#define MCF_SSI_TCR_TFSI        (0x00000004)
+#define MCF_SSI_TCR_TSCKP       (0x00000008)
+#define MCF_SSI_TCR_TSHFD       (0x00000010)
+#define MCF_SSI_TCR_TXDIR       (0x00000020)
+#define MCF_SSI_TCR_TFDIR       (0x00000040)
+#define MCF_SSI_TCR_TFEN0       (0x00000080)
+#define MCF_SSI_TCR_TFEN1       (0x00000100)
+#define MCF_SSI_TCR_TXBIT0      (0x00000200)
+
+/* Bit definitions and macros for RCR */
+#define MCF_SSI_RCR_REFS        (0x00000001)
+#define MCF_SSI_RCR_RFSL        (0x00000002)
+#define MCF_SSI_RCR_RFSI        (0x00000004)
+#define MCF_SSI_RCR_RSCKP       (0x00000008)
+#define MCF_SSI_RCR_RSHFD       (0x00000010)
+#define MCF_SSI_RCR_RFEN0       (0x00000080)
+#define MCF_SSI_RCR_RFEN1       (0x00000100)
+#define MCF_SSI_RCR_RXBIT0      (0x00000200)
+#define MCF_SSI_RCR_RXEXT       (0x00000400)
+
+/* Bit definitions and macros for CCR */
+#define MCF_SSI_CCR_PM(x)       (((x)&0x000000FF))
+#define MCF_SSI_CCR_DC(x)       (((x)&0x0000001F)<<8)
+#define MCF_SSI_CCR_WL(x)       (((x)&0x0000000F)<<13)
+#define MCF_SSI_CCR_PSR         (0x00020000)
+#define MCF_SSI_CCR_DIV2        (0x00040000)
+
+/* Bit definitions and macros for FCSR */
+#define MCF_SSI_FCSR_TFWM0(x)       (((x)&0x0000000F))
+#define MCF_SSI_FCSR_RFWM0(x)       (((x)&0x0000000F)<<4)
+#define MCF_SSI_FCSR_TFCNT0(x)      (((x)&0x0000000F)<<8)
+#define MCF_SSI_FCSR_RFCNT0(x)      (((x)&0x0000000F)<<12)
+#define MCF_SSI_FCSR_TFWM1(x)       (((x)&0x0000000F)<<16)
+#define MCF_SSI_FCSR_RFWM1(x)       (((x)&0x0000000F)<<20)
+#define MCF_SSI_FCSR_TFCNT1(x)      (((x)&0x0000000F)<<24)
+#define MCF_SSI_FCSR_RFCNT1(x)      (((x)&0x0000000F)<<28)
+
+/* Bit definitions and macros for ACR */
+#define MCF_SSI_ACR_AC97EN      (0x00000001)
+#define MCF_SSI_ACR_FV          (0x00000002)
+#define MCF_SSI_ACR_TIF         (0x00000004)
+#define MCF_SSI_ACR_RD          (0x00000008)
+#define MCF_SSI_ACR_WR          (0x00000010)
+#define MCF_SSI_ACR_FRDIV(x)    (((x)&0x0000003F)<<5)
+
+/* Bit definitions and macros for ACADD */
+#define MCF_SSI_ACADD_SSI_ACADD(x)      (((x)&0x0007FFFF))
+
+/* Bit definitions and macros for ACDAT */
+#define MCF_SSI_ACDAT_SSI_ACDAT(x)      (((x)&0x0007FFFF))
+
+/* Bit definitions and macros for ATAG */
+#define MCF_SSI_ATAG_DDI_ATAG(x)    (((x)&0x0000FFFF))
+
+/* Bit definitions and macros for TMASK */
+#define MCF_SSI_TMASK_SSI_TMASK(x)      (x)
+
+/* Bit definitions and macros for RMASK */
+#define MCF_SSI_RMASK_SSI_RMASK(x)      (x)
+
+/********************************************************************/
+
+#endif /* __MCF5445X_SSI_H__ */
--- /dev/null
+++ b/include/asm-m68k/mcf5445x_usb.h
@@ -0,0 +1,49 @@
+/*
+ * Duck Schmid duck@freescale.com
+ *
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <asm/mcfsim.h>
+
+/* ehci_arc_hc_driver.flags value */
+#define FSL_PLATFORM_HC_FLAGS (HCD_USB2 | HCD_MEMORY)
+
+static inline int fsl_platform_verify(struct platform_device *pdev)
+{
+	return 0;
+}
+
+static inline void fsl_platform_usb_setup(struct usb_hcd *hcd)
+{
+}
+
+static inline void fsl_platform_set_host_mode(struct usb_hcd *hcd)
+{
+	unsigned int temp;
+	struct fsl_usb2_platform_data *pdata;
+	struct fsl_usb_host_regs *regs;
+
+	pdata = hcd->self.controller->platform_data;
+	regs = pdata->regs;
+
+	if (pdata->xcvr_ops && pdata->xcvr_ops->set_host)
+		pdata->xcvr_ops->set_host();
+
+	/* set host mode and select "big endian" */
+	temp = fsl_readl(&regs->usbmode);
+	fsl_writel(temp | USBMODE_CM_HOST | USBMODE_ES, &regs->usbmode);
+
+	pr_debug("%s: set usbmode to 0x%x\n\n", __FUNCTION__,
+		fsl_readl(&regs->usbmode));
+
+}