From 8481cdf6f96dc16cbcc129d046c021d17a891274 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Sun, 27 Jul 2014 11:00:32 +0100 Subject: [PATCH 48/57] GPIO: ralink: add mt7621 gpio controller Signed-off-by: John Crispin --- arch/mips/Kconfig | 3 + drivers/gpio/Kconfig | 6 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-mt7621.c | 177 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 187 insertions(+) create mode 100644 drivers/gpio/gpio-mt7621.c --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -455,6 +455,9 @@ config RALINK select RESET_CONTROLLER select PINCTRL select PINCTRL_RT2880 + select ARCH_HAS_RESET_CONTROLLER + select RESET_CONTROLLER + select ARCH_REQUIRE_GPIOLIB config SGI_IP22 bool "SGI IP22 (Indy/Indigo2)" --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -898,6 +898,12 @@ config GPIO_BCM_KONA help Turn on GPIO support for Broadcom "Kona" chips. +config GPIO_MT7621 + bool "Mediatek GPIO Support" + depends on SOC_MT7620 || SOC_MT7621 + help + Say yes here to support the Mediatek SoC GPIO device + comment "USB GPIO expanders:" config GPIO_VIPERBOARD --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -107,3 +107,5 @@ obj-$(CONFIG_GPIO_XILINX) += gpio-xilinx obj-$(CONFIG_GPIO_XTENSA) += gpio-xtensa.o obj-$(CONFIG_GPIO_ZEVIO) += gpio-zevio.o obj-$(CONFIG_GPIO_ZYNQ) += gpio-zynq.o +obj-$(CONFIG_GPIO_MT7621) += gpio-mt7621.o + --- /dev/null +++ b/drivers/gpio/gpio-mt7621.c @@ -0,0 +1,354 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2009-2011 Gabor Juhos + * Copyright (C) 2013 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MTK_MAX_BANK 3 +#define MTK_BANK_WIDTH 32 + +enum mediatek_gpio_reg { + GPIO_REG_CTRL = 0, + GPIO_REG_POL, + GPIO_REG_DATA, + GPIO_REG_DSET, + GPIO_REG_DCLR, + GPIO_REG_REDGE, + GPIO_REG_FEDGE, + GPIO_REG_HLVL, + GPIO_REG_LLVL, + GPIO_REG_STAT, + GPIO_REG_EDGE, +}; + +static void __iomem *mediatek_gpio_membase; +static int mediatek_gpio_irq; +static struct irq_domain *mediatek_gpio_irq_domain; +static atomic_t irq_refcount = ATOMIC_INIT(0); + +struct mtk_gc { + struct gpio_chip chip; + spinlock_t lock; + int bank; + u32 rising; + u32 falling; +} *gc_map[MTK_MAX_BANK]; + +static inline struct mtk_gc +*to_mediatek_gpio(struct gpio_chip *chip) +{ + struct mtk_gc *mgc; + + mgc = container_of(chip, struct mtk_gc, chip); + + return mgc; +} + +static inline void +mtk_gpio_w32(struct mtk_gc *rg, u8 reg, u32 val) +{ + iowrite32(val, mediatek_gpio_membase + (reg * 0x10) + (rg->bank * 0x4)); +} + +static inline u32 +mtk_gpio_r32(struct mtk_gc *rg, u8 reg) +{ + return ioread32(mediatek_gpio_membase + (reg * 0x10) + (rg->bank * 0x4)); +} + +static void +mediatek_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct mtk_gc *rg = to_mediatek_gpio(chip); + + mtk_gpio_w32(rg, (value) ? GPIO_REG_DSET : GPIO_REG_DCLR, BIT(offset)); +} + +static int +mediatek_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct mtk_gc *rg = to_mediatek_gpio(chip); + + return !!(mtk_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset)); +} + +static int +mediatek_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + struct mtk_gc *rg = to_mediatek_gpio(chip); + unsigned long flags; + u32 t; + + spin_lock_irqsave(&rg->lock, flags); + t = mtk_gpio_r32(rg, GPIO_REG_CTRL); + t &= ~BIT(offset); + mtk_gpio_w32(rg, GPIO_REG_CTRL, t); + spin_unlock_irqrestore(&rg->lock, flags); + + return 0; +} + +static int +mediatek_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct mtk_gc *rg = to_mediatek_gpio(chip); + unsigned long flags; + u32 t; + + spin_lock_irqsave(&rg->lock, flags); + t = mtk_gpio_r32(rg, GPIO_REG_CTRL); + t |= BIT(offset); + mtk_gpio_w32(rg, GPIO_REG_CTRL, t); + mediatek_gpio_set(chip, offset, value); + spin_unlock_irqrestore(&rg->lock, flags); + + return 0; +} + +static int +mediatek_gpio_get_direction(struct gpio_chip *chip, unsigned offset) +{ + struct mtk_gc *rg = to_mediatek_gpio(chip); + unsigned long flags; + u32 t; + + spin_lock_irqsave(&rg->lock, flags); + t = mtk_gpio_r32(rg, GPIO_REG_CTRL); + spin_unlock_irqrestore(&rg->lock, flags); + + if (t & BIT(offset)) + return 0; + + return 1; +} + +static int +mediatek_gpio_to_irq(struct gpio_chip *chip, unsigned pin) +{ + struct mtk_gc *rg = to_mediatek_gpio(chip); + + return irq_create_mapping(mediatek_gpio_irq_domain, pin + (rg->bank * MTK_BANK_WIDTH)); +} + +static int +mediatek_gpio_bank_probe(struct platform_device *pdev, struct device_node *bank) +{ + const __be32 *id = of_get_property(bank, "reg", NULL); + struct mtk_gc *rg = devm_kzalloc(&pdev->dev, + sizeof(struct mtk_gc), GFP_KERNEL); + + if (!rg || !id || be32_to_cpu(*id) > MTK_MAX_BANK) + return -ENOMEM; + + gc_map[be32_to_cpu(*id)] = rg; + + memset(rg, 0, sizeof(struct mtk_gc)); + + spin_lock_init(&rg->lock); + + rg->chip.dev = &pdev->dev; + rg->chip.label = dev_name(&pdev->dev); + rg->chip.of_node = bank; + rg->chip.base = MTK_BANK_WIDTH * be32_to_cpu(*id); + rg->chip.ngpio = MTK_BANK_WIDTH; + rg->chip.direction_input = mediatek_gpio_direction_input; + rg->chip.direction_output = mediatek_gpio_direction_output; + rg->chip.get_direction = mediatek_gpio_get_direction; + rg->chip.get = mediatek_gpio_get; + rg->chip.set = mediatek_gpio_set; + if (mediatek_gpio_irq_domain) + rg->chip.to_irq = mediatek_gpio_to_irq; + rg->bank = be32_to_cpu(*id); + + /* set polarity to low for all gpios */ + mtk_gpio_w32(rg, GPIO_REG_POL, 0); + + dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio); + + return gpiochip_add(&rg->chip); +} + +static void +mediatek_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + int i; + + for (i = 0; i < MTK_MAX_BANK; i++) { + struct mtk_gc *rg = gc_map[i]; + unsigned long pending; + int bit; + + if (!rg) + continue; + + pending = mtk_gpio_r32(rg, GPIO_REG_STAT); + + for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) { + u32 map = irq_find_mapping(mediatek_gpio_irq_domain, (MTK_BANK_WIDTH * i) + bit); + + generic_handle_irq(map); + mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit)); + } + } +} + +static void +mediatek_gpio_irq_unmask(struct irq_data *d) +{ + int pin = d->hwirq; + int bank = pin / 32; + struct mtk_gc *rg = gc_map[bank]; + unsigned long flags; + u32 rise, fall; + + if (!rg) + return; + + rise = mtk_gpio_r32(rg, GPIO_REG_REDGE); + fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE); + + spin_lock_irqsave(&rg->lock, flags); + mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(d->hwirq) & rg->rising)); + mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(d->hwirq) & rg->falling)); + spin_unlock_irqrestore(&rg->lock, flags); +} + +static void +mediatek_gpio_irq_mask(struct irq_data *d) +{ + int pin = d->hwirq; + int bank = pin / 32; + struct mtk_gc *rg = gc_map[bank]; + unsigned long flags; + u32 rise, fall; + + if (!rg) + return; + + rise = mtk_gpio_r32(rg, GPIO_REG_REDGE); + fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE); + + spin_lock_irqsave(&rg->lock, flags); + mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(d->hwirq)); + mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(d->hwirq)); + spin_unlock_irqrestore(&rg->lock, flags); +} + +static int +mediatek_gpio_irq_type(struct irq_dat
From d41850b2bd8ad77636e344c5fed1ebda0d77a9bc Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 10 Feb 2016 16:17:29 -0800
Subject: [PATCH] drm/vc4: Add support for feeding DSI encoders from the pixel
 valve.

Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/vc4/vc4_crtc.c | 30 +++++++++++++++++-------------
 drivers/gpu/drm/vc4/vc4_regs.h |  2 ++
 2 files changed, 19 insertions(+), 13 deletions(-)

--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -210,38 +210,40 @@ static u32 vc4_get_fifo_full_level(u32 f
 }
 
 /*
- * Returns the clock select bit for the connector attached to the
- * CRTC.
+ * Returns the encoder attached to the CRTC.
+ *
+ * VC4 can only scan out to one encoder at a type, while the DRM core
+ * allows drivers to push pixels to more than one encoder from the
+ * same CRTC.
  */
-static int vc4_get_clock_select(struct drm_crtc *crtc)
+static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
 {
 	struct drm_connector *connector;
 
 	drm_for_each_connector(connector, crtc->dev) {
 		if (connector->state->crtc == crtc) {
-			struct drm_encoder *encoder = connector->encoder;
-			struct vc4_encoder *vc4_encoder =
-				to_vc4_encoder(encoder);
-
-			return vc4_encoder->clock_select;
+			return connector->encoder;
 		}
 	}
 
-	return -1;
+	return NULL;
 }
 
 static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct vc4_dev *vc4 = to_vc4_dev(dev);
+	struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
+	struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 	struct drm_crtc_state *state = crtc->state;
 	struct drm_display_mode *mode = &state->adjusted_mode;
 	bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 	u32 vactive = (mode->vdisplay >> (interlace ? 1 : 0));
-	u32 format = PV_CONTROL_FORMAT_24;
-	bool debug_dump_regs = false;
-	int clock_select = vc4_get_clock_select(crtc);
+	bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
+		       vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
+	u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
+	bool debug_dump_regs = true;
 
 	if (debug_dump_regs) {
 		DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
@@ -289,6 +291,7 @@ static void vc4_crtc_mode_set_nofb(struc
 
 	CRTC_WRITE(PV_V_CONTROL,
 		   PV_VCONTROL_CONTINUOUS |
+		   (is_dsi ? PV_VCONTROL_DSI : 0) |
 		   (interlace ? PV_VCONTROL_INTERLACE : 0));
 
 	CRTC_WRITE(PV_CONTROL,
@@ -298,7 +301,8 @@ static void vc4_crtc_mode_set_nofb(struc
 		   PV_CONTROL_CLR_AT_START |
 		   PV_CONTROL_TRIGGER_UNDERFLOW |
 		   PV_CONTROL_WAIT_HSTART |
-		   VC4_SET_FIELD(clock_select, PV_CONTROL_CLK_SELECT) |
+		   VC4_SET_FIELD(vc4_encoder->clock_select,
+				 PV_CONTROL_CLK_SELECT) |
 		   PV_CONTROL_FIFO_CLR |
 		   PV_CONTROL_EN);
 
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -184,6 +184,8 @@
 
 #define PV_V_CONTROL				0x04
 # define PV_VCONTROL_INTERLACE			BIT(4)
+# define PV_VCONTROL_DSI			BIT(3)
+# define PV_VCONTROL_COMMAND			BIT(2)
 # define PV_VCONTROL_CONTINUOUS			BIT(1)
 # define PV_VCONTROL_VIDEN			BIT(0)
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-08 23:07:36 +0000