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From c4374e446b6957234432d5c3f5d5f89f1acb807d Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Thu, 7 Nov 2019 12:25:27 +0000
Subject: [PATCH] fixup! clk-raspberrypi: Also support v3d clock
---
drivers/clk/bcm/clk-raspberrypi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/drivers/clk/bcm/clk-raspberrypi.c
+++ b/drivers/clk/bcm/clk-raspberrypi.c
@@ -474,7 +474,7 @@ raspberrypi_register_pll_divider(struct
* PLLH's channels have a fixed divide by 10 afterwards, which
* is what our consumers are actually using.
*/
- if (data->fixed_divider != 1) {
+ if (data->fixed_divider != 0) {
struct clk_lookup *lookup;
struct clk_hw *clk = clk_hw_register_fixed_factor(rpi->dev,
data->divider_name,
@@ -559,7 +559,7 @@ static const struct raspberrypi_clk_desc
.source_pll = "osc",
.divider_name = "pllb_arm",
.lookup = "cpu0",
- .fixed_divider = 2,
+ .fixed_divider = 1,
.clock_id = RPI_FIRMWARE_ARM_CLK_ID,
.flags = CLK_SET_RATE_PARENT),
};
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