1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
|
From 60dfcaef2e9fb7fd79b7a87c25cd520b82c6dd02 Mon Sep 17 00:00:00 2001
From: Stefan Wahren <wahrenst@gmx.net>
Date: Sat, 4 May 2019 17:06:15 +0200
Subject: [PATCH 543/703] hwrng: iproc-rng200: Add BCM2838 support
The HWRNG on the BCM2838 is compatible to iproc-rng200, so add the
support to this driver instead of bcm2835-rng.
Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
---
drivers/char/hw_random/Kconfig | 4 +-
drivers/char/hw_random/iproc-rng200.c | 81 +++++++++++++++++++++++++--
2 files changed, 79 insertions(+), 6 deletions(-)
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -89,11 +89,11 @@ config HW_RANDOM_BCM2835
config HW_RANDOM_IPROC_RNG200
tristate "Broadcom iProc/STB RNG200 support"
- depends on ARCH_BCM_IPROC || ARCH_BRCMSTB
+ depends on ARCH_BCM_IPROC || ARCH_BCM2835 || ARCH_BRCMSTB
default HW_RANDOM
---help---
This driver provides kernel-side support for the RNG200
- hardware found on the Broadcom iProc and STB SoCs.
+ hardware found on the Broadcom iProc, BCM2838 and STB SoCs.
To compile this driver as a module, choose M here: the
module will be called iproc-rng200
--- a/drivers/char/hw_random/iproc-rng200.c
+++ b/drivers/char/hw_random/iproc-rng200.c
@@ -29,6 +29,7 @@
#define RNG_CTRL_RNG_RBGEN_MASK 0x00001FFF
#define RNG_CTRL_RNG_RBGEN_ENABLE 0x00000001
#define RNG_CTRL_RNG_RBGEN_DISABLE 0x00000000
+#define RNG_CTRL_RNG_DIV_CTRL_SHIFT 13
#define RNG_SOFT_RESET_OFFSET 0x04
#define RNG_SOFT_RESET 0x00000001
@@ -36,16 +37,23 @@
#define RBG_SOFT_RESET_OFFSET 0x08
#define RBG_SOFT_RESET 0x00000001
+#define RNG_TOTAL_BIT_COUNT_OFFSET 0x0C
+
+#define RNG_TOTAL_BIT_COUNT_THRESHOLD_OFFSET 0x10
+
#define RNG_INT_STATUS_OFFSET 0x18
#define RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK 0x80000000
#define RNG_INT_STATUS_STARTUP_TRANSITIONS_MET_IRQ_MASK 0x00020000
#define RNG_INT_STATUS_NIST_FAIL_IRQ_MASK 0x00000020
#define RNG_INT_STATUS_TOTAL_BITS_COUNT_IRQ_MASK 0x00000001
+#define RNG_INT_ENABLE_OFFSET 0x1C
+
#define RNG_FIFO_DATA_OFFSET 0x20
#define RNG_FIFO_COUNT_OFFSET 0x24
#define RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK 0x000000FF
+#define RNG_FIFO_COUNT_RNG_FIFO_THRESHOLD_SHIFT 8
struct iproc_rng200_dev {
struct hwrng rng;
@@ -166,6 +174,64 @@ static int iproc_rng200_init(struct hwrn
return 0;
}
+static int bcm2838_rng200_read(struct hwrng *rng, void *buf, size_t max,
+ bool wait)
+{
+ struct iproc_rng200_dev *priv = to_rng_priv(rng);
+ u32 max_words = max / sizeof(u32);
+ u32 num_words, count, val;
+
+ /* ensure warm up period has elapsed */
+ while (1) {
+ val = ioread32(priv->base + RNG_TOTAL_BIT_COUNT_OFFSET);
+ if (val > 16)
+ break;
+ cpu_relax();
+ }
+
+ /* ensure fifo is not empty */
+ while (1) {
+ num_words = ioread32(priv->base + RNG_FIFO_COUNT_OFFSET) &
+ RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK;
+ if (num_words)
+ break;
+ if (!wait)
+ return 0;
+ cpu_relax();
+ }
+
+ if (num_words > max_words)
+ num_words = max_words;
+
+ for (count = 0; count < num_words; count++) {
+ ((u32 *)buf)[count] = ioread32(priv->base +
+ RNG_FIFO_DATA_OFFSET);
+ }
+
+ return num_words * sizeof(u32);
+}
+
+static int bcm2838_rng200_init(struct hwrng *rng)
+{
+ struct iproc_rng200_dev *priv = to_rng_priv(rng);
+ uint32_t val;
+
+ if (ioread32(priv->base + RNG_CTRL_OFFSET) & RNG_CTRL_RNG_RBGEN_MASK)
+ return 0;
+
+ /* initial numbers generated are "less random" so will be discarded */
+ val = 0x40000;
+ iowrite32(val, priv->base + RNG_TOTAL_BIT_COUNT_THRESHOLD_OFFSET);
+ /* min fifo count to generate full interrupt */
+ val = 2 << RNG_FIFO_COUNT_RNG_FIFO_THRESHOLD_SHIFT;
+ iowrite32(val, priv->base + RNG_FIFO_COUNT_OFFSET);
+ /* enable the rng - 1Mhz sample rate */
+ val = (0x3 << RNG_CTRL_RNG_DIV_CTRL_SHIFT) | RNG_CTRL_RNG_RBGEN_MASK;
+ iowrite32(val, priv->base + RNG_CTRL_OFFSET);
+
+ return 0;
+}
+
static void iproc_rng200_cleanup(struct hwrng *rng)
{
struct iproc_rng200_dev *priv = to_rng_priv(rng);
@@ -202,10 +268,16 @@ static int iproc_rng200_probe(struct pla
return PTR_ERR(priv->base);
}
- priv->rng.name = "iproc-rng200",
- priv->rng.read = iproc_rng200_read,
- priv->rng.init = iproc_rng200_init,
- priv->rng.cleanup = iproc_rng200_cleanup,
+ priv->rng.name = pdev->name;
+ priv->rng.cleanup = iproc_rng200_cleanup;
+
+ if (of_device_is_compatible(dev->of_node, "brcm,bcm2838-rng200")) {
+ priv->rng.init = bcm2838_rng200_init;
+ priv->rng.read = bcm2838_rng200_read;
+ } else {
+ priv->rng.init = iproc_rng200_init;
+ priv->rng.read = iproc_rng200_read;
+ }
/* Register driver */
ret = devm_hwrng_register(dev, &priv->rng);
@@ -222,6 +294,7 @@ static int iproc_rng200_probe(struct pla
static const struct of_device_id iproc_rng200_of_match[] = {
{ .compatible = "brcm,bcm7278-rng200", },
{ .compatible = "brcm,iproc-rng200", },
+ { .compatible = "brcm,bcm2838-rng200"},
{},
};
MODULE_DEVICE_TABLE(of, iproc_rng200_of_match);
|
