1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
|
From 42c792400770ec57cafce87cb9594a948d6c0700 Mon Sep 17 00:00:00 2001
From: Marc Kleine-Budde <mkl@pengutronix.de>
Date: Sat, 2 Jan 2021 21:38:58 +0100
Subject: [PATCH] overlays: Add overlay for Seeed Studio CAN BUS FD
HAT v1 (based on mcp2517fd)
This patch adds the overlay for the Seeed Studio CAN BUS FD HAT v1 with two CAN
FD Channels (based on mcp2517fd).
https://www.seeedstudio.com/2-Channel-CAN-BUS-FD-Shield-for-Raspberry-Pi-p-4072.html
The overlay was generated by:
ovmerge -c spi1-1cs-overlay.dts,cs0_pin=18,cs0_spidev=false \
mcp251xfd-overlay.dts,spi0-0,interrupt=25 \
mcp251xfd-overlay.dts,spi1-0,interrupt=24
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
arch/arm/boot/dts/overlays/Makefile | 1 +
arch/arm/boot/dts/overlays/README | 8 +
.../overlays/seeed-can-fd-hat-v1-overlay.dts | 138 ++++++++++++++++++
3 files changed, 147 insertions(+)
create mode 100644 arch/arm/boot/dts/overlays/seeed-can-fd-hat-v1-overlay.dts
--- a/arch/arm/boot/dts/overlays/Makefile
+++ b/arch/arm/boot/dts/overlays/Makefile
@@ -159,6 +159,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
sc16is752-spi1.dtbo \
sdhost.dtbo \
sdio.dtbo \
+ seeed-can-fd-hat-v1.dtbo \
seeed-can-fd-hat-v2.dtbo \
sh1106-spi.dtbo \
smi.dtbo \
--- a/arch/arm/boot/dts/overlays/README
+++ b/arch/arm/boot/dts/overlays/README
@@ -2460,6 +2460,14 @@ Info: This overlay is now deprecated.
Load: <Deprecated>
+Name: seeed-can-fd-hat-v1
+Info: Overlay for Seeed Studio CAN BUS FD HAT with two CAN FD channels
+ (based on the mcp2517fd).
+ https://www.seeedstudio.com/2-Channel-CAN-BUS-FD-Shield-for-Raspberry-Pi-p-4072.html
+Load: dtoverlay=seeed-can-fd-hat-v1
+Params: <None>
+
+
Name: seeed-can-fd-hat-v2
Info: Overlay for Seeed Studio CAN BUS FD HAT with two CAN FD channels
(based on the mcp2518fd) and an RTC.
--- /dev/null
+++ b/arch/arm/boot/dts/overlays/seeed-can-fd-hat-v1-overlay.dts
@@ -0,0 +1,138 @@
+// redo: ovmerge -c spi1-1cs-overlay.dts,cs0_pin=18,cs0_spidev=false mcp251xfd-overlay.dts,spi0-0,interrupt=25 mcp251xfd-overlay.dts,spi1-0,interrupt=24
+
+// Device tree overlay for https://www.seeedstudio.com/2-Channel-CAN-BUS-FD-Shield-for-Raspberry-Pi-p-4072.html
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/bcm2835.h>
+
+/ {
+ compatible = "brcm,bcm2835";
+ fragment@0 {
+ target = <&gpio>;
+ __overlay__ {
+ spi1_pins: spi1_pins {
+ brcm,pins = <19 20 21>;
+ brcm,function = <3>;
+ };
+ spi1_cs_pins: spi1_cs_pins {
+ brcm,pins = <18>;
+ brcm,function = <1>;
+ };
+ };
+ };
+ fragment@1 {
+ target = <&spi1>;
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins &spi1_cs_pins>;
+ cs-gpios = <&gpio 18 1>;
+ status = "okay";
+ spidev@0 {
+ compatible = "spidev";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-max-frequency = <125000000>;
+ status = "disabled";
+ };
+ };
+ };
+ fragment@2 {
+ target = <&aux>;
+ __overlay__ {
+ status = "okay";
+ };
+ };
+ fragment@3 {
+ target = <&spidev0>;
+ __overlay__ {
+ status = "disabled";
+ };
+ };
+ fragment@4 {
+ target = <&gpio>;
+ __overlay__ {
+ mcp251xfd_pins: mcp251xfd_spi0_0_pins {
+ brcm,pins = <25>;
+ brcm,function = <BCM2835_FSEL_GPIO_IN>;
+ };
+ };
+ };
+ fragment@5 {
+ target-path = "/clocks";
+ __overlay__ {
+ clk_mcp251xfd_osc: mcp251xfd-spi0-0-osc {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <40000000>;
+ };
+ };
+ };
+ fragment@6 {
+ target = <&spi0>;
+ __overlay__ {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mcp251xfd@0 {
+ compatible = "microchip,mcp251xfd";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcp251xfd_pins>;
+ spi-max-frequency = <20000000>;
+ interrupt-parent = <&gpio>;
+ interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk_mcp251xfd_osc>;
+ };
+ };
+ };
+ fragment@7 {
+ target-path = "spi1/spidev@0";
+ __overlay__ {
+ status = "disabled";
+ };
+ };
+ fragment@8 {
+ target = <&gpio>;
+ __overlay__ {
+ mcp251xfd_pins_1: mcp251xfd_spi1_0_pins {
+ brcm,pins = <24>;
+ brcm,function = <BCM2835_FSEL_GPIO_IN>;
+ };
+ };
+ };
+ fragment@9 {
+ target-path = "/clocks";
+ __overlay__ {
+ clk_mcp251xfd_osc_1: mcp251xfd-spi1-0-osc {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <40000000>;
+ };
+ };
+ };
+ fragment@10 {
+ target = <&spi1>;
+ __overlay__ {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mcp251xfd@0 {
+ compatible = "microchip,mcp251xfd";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcp251xfd_pins_1>;
+ spi-max-frequency = <20000000>;
+ interrupt-parent = <&gpio>;
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk_mcp251xfd_osc_1>;
+ };
+ };
+ };
+};
|