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Content-Disposition: inline; filename="950-0715-vc4_hdmi-Adjust-CEC-ref-clock-based-on-its-input-clo.patch"
Last-Modified: Tue, 04 Mar 2025 09:21:35 GMT
Expires: Fri, 02 Mar 2035 09:21:35 GMT
ETag: "f6145e4ff50500fefdfac72d0e38f60704c696e4"

From 32e84f4f525e2a0d7dc021b5795df34407096b0e Mon Sep 17 00:00:00 2001
From: Dom Cobley <popcornmix@gmail.com>
Date: Thu, 7 May 2020 18:16:08 +0100
Subject: [PATCH] vc4_hdmi: Adjust CEC ref clock based on its input
 clock

2711 uses a fixed 27MHz input, earlier models use the HSM clock

Signed-off-by: Dom Cobley <popcornmix@gmail.com>
---
 drivers/gpu/drm/vc4/vc4_hdmi.c | 11 ++++++++---
 drivers/gpu/drm/vc4/vc4_hdmi.h |  3 +++
 2 files changed, 11 insertions(+), 3 deletions(-)

--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -79,6 +79,7 @@
 # define VC4_HD_M_ENABLE			BIT(0)
 
 #define CEC_CLOCK_FREQ 40000
+#define VC4_HSM_CLOCK 163682864
 
 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 {
@@ -755,8 +756,7 @@ static u32 vc4_hdmi_calc_hsm_clock(struc
 	 * needs to be a bit higher than the pixel clock rate
 	 * (generally 148.5Mhz).
 	 */
-
-	return 163682864;
+	return VC4_HSM_CLOCK;
 }
 
 static u32 vc5_hdmi_calc_hsm_clock(struct vc4_hdmi *vc4_hdmi, unsigned long pixel_rate)
@@ -1400,6 +1400,7 @@ static int vc4_hdmi_cec_init(struct vc4_
 	struct cec_connector_info conn_info;
 	struct platform_device *pdev = vc4_hdmi->pdev;
 	u32 value;
+	u32 clk_cnt;
 	int ret;
 
 	if (!vc4_hdmi->variant->cec_available)
@@ -1424,8 +1425,9 @@ static int vc4_hdmi_cec_init(struct vc4_
 	 * divider: the hsm_clock rate and this divider setting will
 	 * give a 40 kHz CEC clock.
 	 */
+	clk_cnt = vc4_hdmi->variant->cec_input_clock / CEC_CLOCK_FREQ;
 	value |= VC4_HDMI_CEC_ADDR_MASK |
-		 (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
+		 ((clk_cnt-1) << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
 	HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
 	ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0),
 					vc4_cec_irq_handler,
@@ -1770,6 +1772,7 @@ static int vc4_hdmi_dev_remove(struct pl
 
 static const struct vc4_hdmi_variant bcm2835_variant = {
 	.max_pixel_clock	= 162000000,
+	.cec_input_clock	= VC4_HSM_CLOCK,
 	.audio_available	= true,
 	.cec_available		= true,
 	.registers		= vc4_hdmi_fields,
@@ -1794,6 +1797,7 @@ static const struct vc4_hdmi_variant bcm
 	.id			= 0,
 	.audio_available	= true,
 	.max_pixel_clock	= 297000000,
+	.cec_input_clock	= 27000000,
 	.registers		= vc5_hdmi_hdmi0_fields,
 	.num_registers		= ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
 	.phy_lane_mapping	= {
@@ -1821,6 +1825,7 @@ static const struct vc4_hdmi_variant bcm
 	.id			= 1,
 	.audio_available	= true,
 	.max_pixel_clock	= 297000000,
+	.cec_input_clock	= 27000000,
 	.registers		= vc5_hdmi_hdmi1_fields,
 	.num_registers		= ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
 	.phy_lane_mapping	= {
--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -48,6 +48,9 @@ struct vc4_hdmi_variant {
 	/* Maximum pixel clock supported by the controller (in Hz) */
 	unsigned long long max_pixel_clock;
 
+	/* Input clock frequency of CEC block (in Hz) */
+	unsigned long cec_input_clock;
+
 	/* List of the registers available on that variant */
 	const struct vc4_hdmi_register *registers;
 
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<a id='n303' href='#n303'>303</a>
<a id='n304' href='#n304'>304</a>
<a id='n305' href='#n305'>305</a>
<a id='n306' href='#n306'>306</a>
<a id='n307' href='#n307'>307</a>
<a id='n308' href='#n308'>308</a>
<a id='n309' href='#n309'>309</a>
<a id='n310' href='#n310'>310</a>
<a id='n311' href='#n311'>311</a>
<a id='n312' href='#n312'>312</a>
<a id='n313' href='#n313'>313</a>
<a id='n314' href='#n314'>314</a>
<a id='n315' href='#n315'>315</a>
<a id='n316' href='#n316'>316</a>
<a id='n317' href='#n317'>317</a>
<a id='n318' href='#n318'>318</a>
<a id='n319' href='#n319'>319</a>
<a id='n320' href='#n320'>320</a>
<a id='n321' href='#n321'>321</a>
<a id='n322' href='#n322'>322</a>
<a id='n323' href='#n323'>323</a>
<a id='n324' href='#n324'>324</a>
<a id='n325' href='#n325'>325</a>
<a id='n326' href='#n326'>326</a>
<a id='n327' href='#n327'>327</a>
<a id='n328' href='#n328'>328</a>
<a id='n329' href='#n329'>329</a>
<a id='n330' href='#n330'>330</a>
<a id='n331' href='#n331'>331</a>
<a id='n332' href='#n332'>332</a>
<a id='n333' href='#n333'>333</a>
<a id='n334' href='#n334'>334</a>
<a id='n335' href='#n335'>335</a>
<a id='n336' href='#n336'>336</a>
<a id='n337' href='#n337'>337</a>
<a id='n338' href='#n338'>338</a>
<a id='n339' href='#n339'>339</a>
<a id='n340' href='#n340'>340</a>
<a id='n341' href='#n341'>341</a>
<a id='n342' href='#n342'>342</a>
<a id='n343' href='#n343'>343</a>
<a id='n344' href='#n344'>344</a>
<a id='n345' href='#n345'>345</a>
<a id='n346' href='#n346'>346</a>
<a id='n347' href='#n347'>347</a>
<a id='n348' href='#n348'>348</a>
<a id='n349' href='#n349'>349</a>
<a id='n350' href='#n350'>350</a>
<a id='n351' href='#n351'>351</a>
<a id='n352' href='#n352'>352</a>
<a id='n353' href='#n353'>353</a>
<a id='n354' href='#n354'>354</a>
<a id='n355' href='#n355'>355</a>
<a id='n356' href='#n356'>356</a>
<a id='n357' href='#n357'>357</a>
<a id='n358' href='#n358'>358</a>
<a id='n359' href='#n359'>359</a>
<a id='n360' href='#n360'>360</a>
<a id='n361' href='#n361'>361</a>
<a id='n362' href='#n362'>362</a>
<a id='n363' href='#n363'>363</a>
<a id='n364' href='#n364'>364</a>
<a id='n365' href='#n365'>365</a>
<a id='n366' href='#n366'>366</a>
<a id='n367' href='#n367'>367</a>
<a id='n368' href='#n368'>368</a>
<a id='n369' href='#n369'>369</a>
<a id='n370' href='#n370'>370</a>
<a id='n371' href='#n371'>371</a>
<a id='n372' href='#n372'>372</a>
<a id='n373' href='#n373'>373</a>
<a id='n374' href='#n374'>374</a>
<a id='n375' href='#n375'>375</a>
<a id='n376' href='#n376'>376</a>
<a id='n377' href='#n377'>377</a>
<a id='n378' href='#n378'>378</a>
<a id='n379' href='#n379'>379</a>
<a id='n380' href='#n380'>380</a>
<a id='n381' href='#n381'>381</a>
<a id='n382' href='#n382'>382</a>
<a id='n383' href='#n383'>383</a>
<a id='n384' href='#n384'>384</a>
<a id='n385' href='#n385'>385</a>
<a id='n386' href='#n386'>386</a>
<a id='n387' href='#n387'>387</a>
<a id='n388' href='#n388'>388</a>
<a id='n389' href='#n389'>389</a>
<a id='n390' href='#n390'>390</a>
<a id='n391' href='#n391'>391</a>
<a id='n392' href='#n392'>392</a>
<a id='n393' href='#n393'>393</a>
<a id='n394' href='#n394'>394</a>
<a id='n395' href='#n395'>395</a>
<a id='n396' href='#n396'>396</a>
<a id='n397' href='#n397'>397</a>
<a id='n398' href='#n398'>398</a>
<a id='n399' href='#n399'>399</a>
<a id='n400' href='#n400'>400</a>
<a id='n401' href='#n401'>401</a>
<a id='n402' href='#n402'>402</a>
<a id='n403' href='#n403'>403</a>
<a id='n404' href='#n404'>404</a>
<a id='n405' href='#n405'>405</a>
<a id='n406' href='#n406'>406</a>
<a id='n407' href='#n407'>407</a>
<a id='n408' href='#n408'>408</a>
<a id='n409' href='#n409'>409</a>
<a id='n410' href='#n410'>410</a>
<a id='n411' href='#n411'>411</a>
<a id='n412' href='#n412'>412</a>
<a id='n413' href='#n413'>413</a>
<a id='n414' href='#n414'>414</a>
<a id='n415' href='#n415'>415</a>
<a id='n416' href='#n416'>416</a>
<a id='n417' href='#n417'>417</a>
<a id='n418' href='#n418'>418</a>
<a id='n419' href='#n419'>419</a>
<a id='n420' href='#n420'>420</a>
<a id='n421' href='#n421'>421</a>
<a id='n422' href='#n422'>422</a>
<a id='n423' href='#n423'>423</a>
<a id='n424' href='#n424'>424</a>
<a id='n425' href='#n425'>425</a>
<a id='n426' href='#n426'>426</a>
<a id='n427' href='#n427'>427</a>
<a id='n428' href='#n428'>428</a>
<a id='n429' href='#n429'>429</a>
<a id='n430' href='#n430'>430</a>
<a id='n431' href='#n431'>431</a>
<a id='n432' href='#n432'>432</a>
<a id='n433' href='#n433'>433</a>
<a id='n434' href='#n434'>434</a>
<a id='n435' href='#n435'>435</a>
<a id='n436' href='#n436'>436</a>
<a id='n437' href='#n437'>437</a>
<a id='n438' href='#n438'>438</a>
<a id='n439' href='#n439'>439</a>
<a id='n440' href='#n440'>440</a>
<a id='n441' href='#n441'>441</a>
<a id='n442' href='#n442'>442</a>
<a id='n443' href='#n443'>443</a>
<a id='n444' href='#n444'>444</a>
<a id='n445' href='#n445'>445</a>
<a id='n446' href='#n446'>446</a>
<a id='n447' href='#n447'>447</a>
<a id='n448' href='#n448'>448</a>
<a id='n449' href='#n449'>449</a>
<a id='n450' href='#n450'>450</a>
<a id='n451' href='#n451'>451</a>
<a id='n452' href='#n452'>452</a>
<a id='n453' href='#n453'>453</a>
<a id='n454' href='#n454'>454</a>
<a id='n455' href='#n455'>455</a>
<a id='n456' href='#n456'>456</a>
<a id='n457' href='#n457'>457</a>
<a id='n458' href='#n458'>458</a>
<a id='n459' href='#n459'>459</a>
<a id='n460' href='#n460'>460</a>
<a id='n461' href='#n461'>461</a>
<a id='n462' href='#n462'>462</a>
<a id='n463' href='#n463'>463</a>
<a id='n464' href='#n464'>464</a>
<a id='n465' href='#n465'>465</a>
<a id='n466' href='#n466'>466</a>
<a id='n467' href='#n467'>467</a>
<a id='n468' href='#n468'>468</a>
<a id='n469' href='#n469'>469</a>
<a id='n470' href='#n470'>470</a>
<a id='n471' href='#n471'>471</a>
<a id='n472' href='#n472'>472</a>
<a id='n473' href='#n473'>473</a>
<a id='n474' href='#n474'>474</a>
<a id='n475' href='#n475'>475</a>
<a id='n476' href='#n476'>476</a>
<a id='n477' href='#n477'>477</a>
<a id='n478' href='#n478'>478</a>
<a id='n479' href='#n479'>479</a>
<a id='n480' href='#n480'>480</a>
<a id='n481' href='#n481'>481</a>
<a id='n482' href='#n482'>482</a>
<a id='n483' href='#n483'>483</a>
<a id='n484' href='#n484'>484</a>
<a id='n485' href='#n485'>485</a>
<a id='n486' href='#n486'>486</a>
<a id='n487' href='#n487'>487</a>
<a id='n488' href='#n488'>488</a>
<a id='n489' href='#n489'>489</a>
<a id='n490' href='#n490'>490</a>
<a id='n491' href='#n491'>491</a>
<a id='n492' href='#n492'>492</a>
<a id='n493' href='#n493'>493</a>
<a id='n494' href='#n494'>494</a>
<a id='n495' href='#n495'>495</a>
<a id='n496' href='#n496'>496</a>
<a id='n497' href='#n497'>497</a>
<a id='n498' href='#n498'>498</a>
<a id='n499' href='#n499'>499</a>
<a id='n500' href='#n500'>500</a>
<a id='n501' href='#n501'>501</a>
<a id='n502' href='#n502'>502</a>
<a id='n503' href='#n503'>503</a>
<a id='n504' href='#n504'>504</a>
<a id='n505' href='#n505'>505</a>
<a id='n506' href='#n506'>506</a>
<a id='n507' href='#n507'>507</a>
<a id='n508' href='#n508'>508</a>
<a id='n509' href='#n509'>509</a>
<a id='n510' href='#n510'>510</a>
<a id='n511' href='#n511'>511</a>
<a id='n512' href='#n512'>512</a>
<a id='n513' href='#n513'>513</a>
<a id='n514' href='#n514'>514</a>
<a id='n515' href='#n515'>515</a>
<a id='n516' href='#n516'>516</a>
<a id='n517' href='#n517'>517</a>
<a id='n518' href='#n518'>518</a>
<a id='n519' href='#n519'>519</a>
<a id='n520' href='#n520'>520</a>
<a id='n521' href='#n521'>521</a>
<a id='n522' href='#n522'>522</a>
<a id='n523' href='#n523'>523</a>
<a id='n524' href='#n524'>524</a>
<a id='n525' href='#n525'>525</a>
<a id='n526' href='#n526'>526</a>
<a id='n527' href='#n527'>527</a>
<a id='n528' href='#n528'>528</a>
<a id='n529' href='#n529'>529</a>
<a id='n530' href='#n530'>530</a>
<a id='n531' href='#n531'>531</a>
<a id='n532' href='#n532'>532</a>
<a id='n533' href='#n533'>533</a>
<a id='n534' href='#n534'>534</a>
<a id='n535' href='#n535'>535</a>
<a id='n536' href='#n536'>536</a>
<a id='n537' href='#n537'>537</a>
<a id='n538' href='#n538'>538</a>
<a id='n539' href='#n539'>539</a>
<a id='n540' href='#n540'>540</a>
<a id='n541' href='#n541'>541</a>
<a id='n542' href='#n542'>542</a>
<a id='n543' href='#n543'>543</a>
<a id='n544' href='#n544'>544</a>
<a id='n545' href='#n545'>545</a>
<a id='n546' href='#n546'>546</a>
<a id='n547' href='#n547'>547</a>
<a id='n548' href='#n548'>548</a>
<a id='n549' href='#n549'>549</a>
<a id='n550' href='#n550'>550</a>
<a id='n551' href='#n551'>551</a>
<a id='n552' href='#n552'>552</a>
<a id='n553' href='#n553'>553</a>
<a id='n554' href='#n554'>554</a>
<a id='n555' href='#n555'>555</a>
<a id='n556' href='#n556'>556</a>
<a id='n557' href='#n557'>557</a>
<a id='n558' href='#n558'>558</a>
<a id='n559' href='#n559'>559</a>
<a id='n560' href='#n560'>560</a>
<a id='n561' href='#n561'>561</a>
<a id='n562' href='#n562'>562</a>
<a id='n563' href='#n563'>563</a>
<a id='n564' href='#n564'>564</a>
<a id='n565' href='#n565'>565</a>
<a id='n566' href='#n566'>566</a>
<a id='n567' href='#n567'>567</a>
<a id='n568' href='#n568'>568</a>
<a id='n569' href='#n569'>569</a>
<a id='n570' href='#n570'>570</a>
<a id='n571' href='#n571'>571</a>
<a id='n572' href='#n572'>572</a>
<a id='n573' href='#n573'>573</a>
<a id='n574' href='#n574'>574</a>
<a id='n575' href='#n575'>575</a>
<a id='n576' href='#n576'>576</a>
<a id='n577' href='#n577'>577</a>
<a id='n578' href='#n578'>578</a>
<a id='n579' href='#n579'>579</a>
<a id='n580' href='#n580'>580</a>
<a id='n581' href='#n581'>581</a>
<a id='n582' href='#n582'>582</a>
<a id='n583' href='#n583'>583</a>
<a id='n584' href='#n584'>584</a>
<a id='n585' href='#n585'>585</a>
<a id='n586' href='#n586'>586</a>
<a id='n587' href='#n587'>587</a>
<a id='n588' href='#n588'>588</a>
<a id='n589' href='#n589'>589</a>
<a id='n590' href='#n590'>590</a>
<a id='n591' href='#n591'>591</a>
<a id='n592' href='#n592'>592</a>
<a id='n593' href='#n593'>593</a>
<a id='n594' href='#n594'>594</a>
<a id='n595' href='#n595'>595</a>
<a id='n596' href='#n596'>596</a>
<a id='n597' href='#n597'>597</a>
<a id='n598' href='#n598'>598</a>
<a id='n599' href='#n599'>599</a>
<a id='n600' href='#n600'>600</a>
<a id='n601' href='#n601'>601</a>
<a id='n602' href='#n602'>602</a>
<a id='n603' href='#n603'>603</a>
<a id='n604' href='#n604'>604</a>
<a id='n605' href='#n605'>605</a>
<a id='n606' href='#n606'>606</a>
<a id='n607' href='#n607'>607</a>
<a id='n608' href='#n608'>608</a>
<a id='n609' href='#n609'>609</a>
<a id='n610' href='#n610'>610</a>
<a id='n611' href='#n611'>611</a>
<a id='n612' href='#n612'>612</a>
<a id='n613' href='#n613'>613</a>
<a id='n614' href='#n614'>614</a>
<a id='n615' href='#n615'>615</a>
<a id='n616' href='#n616'>616</a>
<a id='n617' href='#n617'>617</a>
<a id='n618' href='#n618'>618</a>
<a id='n619' href='#n619'>619</a>
<a id='n620' href='#n620'>620</a>
<a id='n621' href='#n621'>621</a>
<a id='n622' href='#n622'>622</a>
<a id='n623' href='#n623'>623</a>
<a id='n624' href='#n624'>624</a>
<a id='n625' href='#n625'>625</a>
<a id='n626' href='#n626'>626</a>
<a id='n627' href='#n627'>627</a>
<a id='n628' href='#n628'>628</a>
<a id='n629' href='#n629'>629</a>
<a id='n630' href='#n630'>630</a>
<a id='n631' href='#n631'>631</a>
<a id='n632' href='#n632'>632</a>
<a id='n633' href='#n633'>633</a>
<a id='n634' href='#n634'>634</a>
<a id='n635' href='#n635'>635</a>
<a id='n636' href='#n636'>636</a>
<a id='n637' href='#n637'>637</a>
<a id='n638' href='#n638'>638</a>
<a id='n639' href='#n639'>639</a>
<a id='n640' href='#n640'>640</a>
<a id='n641' href='#n641'>641</a>
<a id='n642' href='#n642'>642</a>
<a id='n643' href='#n643'>643</a>
<a id='n644' href='#n644'>644</a>
<a id='n645' href='#n645'>645</a>
<a id='n646' href='#n646'>646</a>
<a id='n647' href='#n647'>647</a>
<a id='n648' href='#n648'>648</a>
<a id='n649' href='#n649'>649</a>
<a id='n650' href='#n650'>650</a>
<a id='n651' href='#n651'>651</a>
<a id='n652' href='#n652'>652</a>
<a id='n653' href='#n653'>653</a>
<a id='n654' href='#n654'>654</a>
<a id='n655' href='#n655'>655</a>
<a id='n656' href='#n656'>656</a>
<a id='n657' href='#n657'>657</a>
<a id='n658' href='#n658'>658</a>
<a id='n659' href='#n659'>659</a>
<a id='n660' href='#n660'>660</a>
<a id='n661' href='#n661'>661</a>
<a id='n662' href='#n662'>662</a>
<a id='n663' href='#n663'>663</a>
<a id='n664' href='#n664'>664</a>
<a id='n665' href='#n665'>665</a>
<a id='n666' href='#n666'>666</a>
<a id='n667' href='#n667'>667</a>
<a id='n668' href='#n668'>668</a>
<a id='n669' href='#n669'>669</a>
<a id='n670' href='#n670'>670</a>
<a id='n671' href='#n671'>671</a>
<a id='n672' href='#n672'>672</a>
<a id='n673' href='#n673'>673</a>
<a id='n674' href='#n674'>674</a>
<a id='n675' href='#n675'>675</a>
<a id='n676' href='#n676'>676</a>
<a id='n677' href='#n677'>677</a>
<a id='n678' href='#n678'>678</a>
<a id='n679' href='#n679'>679</a>
<a id='n680' href='#n680'>680</a>
<a id='n681' href='#n681'>681</a>
<a id='n682' href='#n682'>682</a>
<a id='n683' href='#n683'>683</a>
<a id='n684' href='#n684'>684</a>
<a id='n685' href='#n685'>685</a>
<a id='n686' href='#n686'>686</a>
<a id='n687' href='#n687'>687</a>
<a id='n688' href='#n688'>688</a>
<a id='n689' href='#n689'>689</a>
<a id='n690' href='#n690'>690</a>
<a id='n691' href='#n691'>691</a>
<a id='n692' href='#n692'>692</a>
<a id='n693' href='#n693'>693</a>
<a id='n694' href='#n694'>694</a>
<a id='n695' href='#n695'>695</a>
<a id='n696' href='#n696'>696</a>
<a id='n697' href='#n697'>697</a>
<a id='n698' href='#n698'>698</a>
<a id='n699' href='#n699'>699</a>
<a id='n700' href='#n700'>700</a>
<a id='n701' href='#n701'>701</a>
<a id='n702' href='#n702'>702</a>
<a id='n703' href='#n703'>703</a>
<a id='n704' href='#n704'>704</a>
<a id='n705' href='#n705'>705</a>
<a id='n706' href='#n706'>706</a>
<a id='n707' href='#n707'>707</a>
<a id='n708' href='#n708'>708</a>
<a id='n709' href='#n709'>709</a>
<a id='n710' href='#n710'>710</a>
<a id='n711' href='#n711'>711</a>
<a id='n712' href='#n712'>712</a>
<a id='n713' href='#n713'>713</a>
<a id='n714' href='#n714'>714</a>
<a id='n715' href='#n715'>715</a>
<a id='n716' href='#n716'>716</a>
<a id='n717' href='#n717'>717</a>
<a id='n718' href='#n718'>718</a>
<a id='n719' href='#n719'>719</a>
<a id='n720' href='#n720'>720</a>
<a id='n721' href='#n721'>721</a>
<a id='n722' href='#n722'>722</a>
<a id='n723' href='#n723'>723</a>
<a id='n724' href='#n724'>724</a>
<a id='n725' href='#n725'>725</a>
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</pre></td>
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.highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */</style><div class="highlight"><pre><span></span>From 4d9470c29736bf81bdb0d21da24cf350b1e99402 Mon Sep 17 00:00:00 2001
From: Jim Quinlan &lt;james.quinlan@broadcom.com&gt;
Date: Mon, 16 Dec 2019 12:01:09 +0100
Subject: [PATCH] PCI: brcmstb: Add Broadcom STB PCIe host controller
 driver

commit c0452137034bda8f686dd9a2e167949bfffd6776 upstream.

This adds a basic driver for Broadcom&#39;s STB PCIe controller, for now
aimed at Raspberry Pi 4&#39;s SoC, bcm2711.

Signed-off-by: Jim Quinlan &lt;james.quinlan@broadcom.com&gt;
Co-developed-by: Nicolas Saenz Julienne &lt;nsaenzjulienne@suse.de&gt;
Signed-off-by: Nicolas Saenz Julienne &lt;nsaenzjulienne@suse.de&gt;
[lorenzo.pieralisi@arm.com: updated brcm_pcie_get_rc_bar2_size_and_offset()according to https://lore.kernel.org/linux-pci/be8ddb33a7360af1815cf686f77f3f0913d02be3.camel@suse.de]
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Reviewed-by: Andrew Murray &lt;andrew.murray@arm.com&gt;
Reviewed-by: Jeremy Linton &lt;jeremy.linton@arm.com&gt;
<span class="gd">---</span>
 drivers/pci/controller/Kconfig        |   8 +
 drivers/pci/controller/Makefile       |   1 +
 drivers/pci/controller/pcie-brcmstb.c | 755 ++++++++++++++++++++++++++
 3 files changed, 764 insertions(+)
 create mode 100644 drivers/pci/controller/pcie-brcmstb.c

<span class="gd">--- a/drivers/pci/controller/Kconfig</span>
<span class="gi">+++ b/drivers/pci/controller/Kconfig</span>
<span class="gu">@@ -281,6 +281,14 @@ config VMD</span>
 	  To compile this driver as a module, choose M here: the
 	  module will be called vmd.
 
<span class="gi">+config PCIE_BRCMSTB</span>
<span class="gi">+	tristate &quot;Broadcom Brcmstb PCIe host controller&quot;</span>
<span class="gi">+	depends on ARCH_BCM2835 || COMPILE_TEST</span>
<span class="gi">+	depends on OF</span>
<span class="gi">+	help</span>
<span class="gi">+	  Say Y here to enable PCIe host controller support for</span>
<span class="gi">+	  Broadcom STB based SoCs, like the Raspberry Pi 4.</span>
<span class="gi">+</span>
 config PCI_HYPERV_INTERFACE
 	tristate &quot;Hyper-V PCI Interface&quot;
 	depends on X86 &amp;&amp; HYPERV &amp;&amp; PCI_MSI &amp;&amp; PCI_MSI_IRQ_DOMAIN &amp;&amp; X86_64
<span class="gd">--- a/drivers/pci/controller/Makefile</span>
<span class="gi">+++ b/drivers/pci/controller/Makefile</span>
<span class="gu">@@ -30,6 +30,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-medi</span>
 obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
 obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
 obj-$(CONFIG_VMD) += vmd.o
<span class="gi">+obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o</span>
 # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
 obj-y				+= dwc/
 
<span class="gd">--- /dev/null</span>
<span class="gi">+++ b/drivers/pci/controller/pcie-brcmstb.c</span>
<span class="gu">@@ -0,0 +1,755 @@</span>
<span class="gi">+// SPDX-License-Identifier: GPL-2.0+</span>
<span class="gi">+/* Copyright (C) 2009 - 2019 Broadcom */</span>
<span class="gi">+</span>
<span class="gi">+#include &lt;linux/bitfield.h&gt;</span>
<span class="gi">+#include &lt;linux/clk.h&gt;</span>
<span class="gi">+#include &lt;linux/compiler.h&gt;</span>
<span class="gi">+#include &lt;linux/delay.h&gt;</span>
<span class="gi">+#include &lt;linux/init.h&gt;</span>
<span class="gi">+#include &lt;linux/interrupt.h&gt;</span>
<span class="gi">+#include &lt;linux/io.h&gt;</span>
<span class="gi">+#include &lt;linux/ioport.h&gt;</span>
<span class="gi">+#include &lt;linux/irqdomain.h&gt;</span>
<span class="gi">+#include &lt;linux/kernel.h&gt;</span>
<span class="gi">+#include &lt;linux/list.h&gt;</span>
<span class="gi">+#include &lt;linux/log2.h&gt;</span>
<span class="gi">+#include &lt;linux/module.h&gt;</span>
<span class="gi">+#include &lt;linux/of_address.h&gt;</span>
<span class="gi">+#include &lt;linux/of_irq.h&gt;</span>
<span class="gi">+#include &lt;linux/of_pci.h&gt;</span>
<span class="gi">+#include &lt;linux/of_platform.h&gt;</span>
<span class="gi">+#include &lt;linux/pci.h&gt;</span>
<span class="gi">+#include &lt;linux/printk.h&gt;</span>
<span class="gi">+#include &lt;linux/sizes.h&gt;</span>
<span class="gi">+#include &lt;linux/slab.h&gt;</span>
<span class="gi">+#include &lt;linux/string.h&gt;</span>
<span class="gi">+#include &lt;linux/types.h&gt;</span>
<span class="gi">+</span>
<span class="gi">+#include &quot;../pci.h&quot;</span>
<span class="gi">+</span>
<span class="gi">+/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */</span>
<span class="gi">+#define BRCM_PCIE_CAP_REGS				0x00ac</span>
<span class="gi">+</span>
<span class="gi">+/* Broadcom STB PCIe Register Offsets */</span>
<span class="gi">+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1				0x0188</span>
<span class="gi">+#define  PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK	0xc</span>
<span class="gi">+#define  PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN			0x0</span>
<span class="gi">+</span>
<span class="gi">+#define PCIE_RC_CFG_PRIV1_ID_VAL3			0x043c</span>
<span class="gi">+#define  PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK	0xffffff</span>
<span class="gi">+</span>
<span class="gi">+#define PCIE_RC_DL_MDIO_ADDR				0x1100</span>
<span class="gi">+#define PCIE_RC_DL_MDIO_WR_DATA				0x1104</span>
<span class="gi">+#define PCIE_RC_DL_MDIO_RD_DATA				0x1108</span>
<span class="gi">+</span>
<span class="gi">+#define PCIE_MISC_MISC_CTRL				0x4008</span>
<span class="gi">+#define  PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK		0x1000</span>
<span class="gi">+#define  PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK	0x2000</span>
<span class="gi">+#define  PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK	0x300000</span>
<span class="gi">+#define  PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_128		0x0</span>
<span class="gi">+#define  PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK		0xf8000000</span>
<span class="gi">+</span>
<span class="gi">+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO		0x400c</span>
<span class="gi">+#define PCIE_MEM_WIN0_LO(win)	\</span>
<span class="gi">+		PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)</span>
<span class="gi">+</span>
<span class="gi">+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI		0x4010</span>
<span class="gi">+#define PCIE_MEM_WIN0_HI(win)	\</span>
<span class="gi">+		PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)</span>
<span class="gi">+</span>
<span class="gi">+#define PCIE_MISC_RC_BAR1_CONFIG_LO			0x402c</span>
<span class="gi">+#define  PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK		0x1f</span>
<span class="gi">+</span>
<span class="gi">+#define PCIE_MISC_RC_BAR2_CONFIG_LO			0x4034</span>
<span class="gi">+#define  PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK		0x1f</span>
<span class="gi">+#define PCIE_MISC_RC_BAR2_CONFIG_HI			0x4038</span>
<span class="gi">+</span>
<span class="gi">+#define PCIE_MISC_RC_BAR3_CONFIG_LO			0x403c</span>
<span class="gi">+#define  PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK		0x1f</span>
<span class="gi">+</span>
<span class="gi">+#define PCIE_MISC_PCIE_CTRL				0x4064</span>
<span class="gi">+#define  PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK	0x1</span>
<span class="gi">+</span>
<span class="gi">+#define PCIE_MISC_PCIE_STATUS				0x4068</span>
<span class="gi">+#define  PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK		0x80</span>
<span class="gi">+#define  PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK	0x20</span>
<span class="gi">+#define  PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK	0x10</span>
<span class="gi">+#define  PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK	0x40</span>
<span class="gi">+</span>
<span class="gi">+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT		0x4070</span>
<span class="gi">+#define  PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK	0xfff00000</span>
<span class="gi">+#define  PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK	0xfff0</span>
<span class="gi">+#define PCIE_MEM_WIN0_BASE_LIMIT(win)	\</span>
<span class="gi">+		PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4)</span>
<span class="gi">+</span>
<span class="gi">+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI			0x4080</span>
<span class="gi">+#define  PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK	0xff</span>
<span class="gi">+#define PCIE_MEM_WIN0_BASE_HI(win)	\</span>
<span class="gi">+		PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8)</span>
<span class="gi">+</span>
<span class="gi">+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI			0x4084</span>
<span class="gi">+#define  PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK	0xff</span>
<span class="gi">+#define PCIE_MEM_WIN0_LIMIT_HI(win)	\</span>
<span class="gi">+		PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)</span>
<span class="gi">+</span>
<span class="gi">+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG					0x4204</span>
<span class="gi">+#define  PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK	0x2</span>
<span class="gi">+#define  PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK		0x08000000</span>
<span class="gi">+</span>
<span class="gi">+#define PCIE_MSI_INTR2_STATUS				0x4500</span>
<span class="gi">+#define PCIE_MSI_INTR2_CLR				0x4508</span>
<span class="gi">+#define PCIE_MSI_INTR2_MASK_SET				0x4510</span>
<span class="gi">+#define PCIE_MSI_INTR2_MASK_CLR				0x4514</span>
<span class="gi">+</span>
<span class="gi">+#define PCIE_EXT_CFG_DATA				0x8000</span>
<span class="gi">+</span>
<span class="gi">+#define PCIE_EXT_CFG_INDEX				0x9000</span>
<span class="gi">+#define  PCIE_EXT_BUSNUM_SHIFT				20</span>
<span class="gi">+#define  PCIE_EXT_SLOT_SHIFT				15</span>
<span class="gi">+#define  PCIE_EXT_FUNC_SHIFT				12</span>
<span class="gi">+</span>
<span class="gi">+#define PCIE_RGR1_SW_INIT_1				0x9210</span>
<span class="gi">+#define  PCIE_RGR1_SW_INIT_1_PERST_MASK			0x1</span>
<span class="gi">+#define  PCIE_RGR1_SW_INIT_1_INIT_MASK			0x2</span>
<span class="gi">+</span>
<span class="gi">+/* PCIe parameters */</span>
<span class="gi">+#define BRCM_NUM_PCIE_OUT_WINS		0x4</span>
<span class="gi">+</span>
<span class="gi">+/* MDIO registers */</span>
<span class="gi">+#define MDIO_PORT0			0x0</span>
<span class="gi">+#define MDIO_DATA_MASK			0x7fffffff</span>
<span class="gi">+#define MDIO_PORT_MASK			0xf0000</span>
<span class="gi">+#define MDIO_REGAD_MASK			0xffff</span>
<span class="gi">+#define MDIO_CMD_MASK			0xfff00000</span>
<span class="gi">+#define MDIO_CMD_READ			0x1</span>
<span class="gi">+#define MDIO_CMD_WRITE			0x0</span>
<span class="gi">+#define MDIO_DATA_DONE_MASK		0x80000000</span>
<span class="gi">+#define MDIO_RD_DONE(x)			(((x) &amp; MDIO_DATA_DONE_MASK) ? 1 : 0)</span>
<span class="gi">+#define MDIO_WT_DONE(x)			(((x) &amp; MDIO_DATA_DONE_MASK) ? 0 : 1)</span>
<span class="gi">+#define SSC_REGS_ADDR			0x1100</span>
<span class="gi">+#define SET_ADDR_OFFSET			0x1f</span>
<span class="gi">+#define SSC_CNTL_OFFSET			0x2</span>
<span class="gi">+#define SSC_CNTL_OVRD_EN_MASK		0x8000</span>
<span class="gi">+#define SSC_CNTL_OVRD_VAL_MASK		0x4000</span>
<span class="gi">+#define SSC_STATUS_OFFSET		0x1</span>
<span class="gi">+#define SSC_STATUS_SSC_MASK		0x400</span>
<span class="gi">+#define SSC_STATUS_PLL_LOCK_MASK	0x800</span>
<span class="gi">+</span>
<span class="gi">+/* Internal PCIe Host Controller Information.*/</span>
<span class="gi">+struct brcm_pcie {</span>
<span class="gi">+	struct device		*dev;</span>
<span class="gi">+	void __iomem		*base;</span>
<span class="gi">+	struct clk		*clk;</span>
<span class="gi">+	struct pci_bus		*root_bus;</span>
<span class="gi">+	struct device_node	*np;</span>
<span class="gi">+	bool			ssc;</span>
<span class="gi">+	int			gen;</span>
<span class="gi">+};</span>
<span class="gi">+</span>
<span class="gi">+/*</span>
<span class="gi">+ * This is to convert the size of the inbound &quot;BAR&quot; region to the</span>
<span class="gi">+ * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE</span>
<span class="gi">+ */</span>
<span class="gi">+static int brcm_pcie_encode_ibar_size(u64 size)</span>
<span class="gi">+{</span>
<span class="gi">+	int log2_in = ilog2(size);</span>
<span class="gi">+</span>
<span class="gi">+	if (log2_in &gt;= 12 &amp;&amp; log2_in &lt;= 15)</span>
<span class="gi">+		/* Covers 4KB to 32KB (inclusive) */</span>
<span class="gi">+		return (log2_in - 12) + 0x1c;</span>
<span class="gi">+	else if (log2_in &gt;= 16 &amp;&amp; log2_in &lt;= 35)</span>
<span class="gi">+		/* Covers 64KB to 32GB, (inclusive) */</span>
<span class="gi">+		return log2_in - 15;</span>
<span class="gi">+	/* Something is awry so disable */</span>
<span class="gi">+	return 0;</span>
<span class="gi">+}</span>
<span class="gi">+</span>
<span class="gi">+static u32 brcm_pcie_mdio_form_pkt(int port, int regad, int cmd)</span>
<span class="gi">+{</span>
<span class="gi">+	u32 pkt = 0;</span>
<span class="gi">+</span>
<span class="gi">+	pkt |= FIELD_PREP(MDIO_PORT_MASK, port);</span>
<span class="gi">+	pkt |= FIELD_PREP(MDIO_REGAD_MASK, regad);</span>
<span class="gi">+	pkt |= FIELD_PREP(MDIO_CMD_MASK, cmd);</span>
<span class="gi">+</span>
<span class="gi">+	return pkt;</span>
<span class="gi">+}</span>
<span class="gi">+</span>
<span class="gi">+/* negative return value indicates error */</span>
<span class="gi">+static int brcm_pcie_mdio_read(void __iomem *base, u8 port, u8 regad, u32 *val)</span>
<span class="gi">+{</span>
<span class="gi">+	int tries;</span>
<span class="gi">+	u32 data;</span>
<span class="gi">+</span>
<span class="gi">+	writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ),</span>
<span class="gi">+		   base + PCIE_RC_DL_MDIO_ADDR);</span>
<span class="gi">+	readl(base + PCIE_RC_DL_MDIO_ADDR);</span>
<span class="gi">+</span>
<span class="gi">+	data = readl(base + PCIE_RC_DL_MDIO_RD_DATA);</span>
<span class="gi">+	for (tries = 0; !MDIO_RD_DONE(data) &amp;&amp; tries &lt; 10; tries++) {</span>
<span class="gi">+		udelay(10);</span>
<span class="gi">+		data = readl(base + PCIE_RC_DL_MDIO_RD_DATA);</span>
<span class="gi">+	}</span>
<span class="gi">+</span>
<span class="gi">+	*val = FIELD_GET(MDIO_DATA_MASK, data);</span>
<span class="gi">+	return MDIO_RD_DONE(data) ? 0 : -EIO;</span>
<span class="gi">+}</span>
<span class="gi">+</span>
<span class="gi">+/* negative return value indicates error */</span>
<span class="gi">+static int brcm_pcie_mdio_write(void __iomem *base, u8 port,</span>
<span class="gi">+				u8 regad, u16 wrdata)</span>
<span class="gi">+{</span>
<span class="gi">+	int tries;</span>
<span class="gi">+	u32 data;</span>
<span class="gi">+</span>
<span class="gi">+	writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE),</span>
<span class="gi">+		   base + PCIE_RC_DL_MDIO_ADDR);</span>
<span class="gi">+	readl(base + PCIE_RC_DL_MDIO_ADDR);</span>
<span class="gi">+	writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA);</span>
<span class="gi">+</span>
<span class="gi">+	data = readl(base + PCIE_RC_DL_MDIO_WR_DATA);</span>
<span class="gi">+	for (tries = 0; !MDIO_WT_DONE(data) &amp;&amp; tries &lt; 10; tries++) {</span>
<span class="gi">+		udelay(10);</span>
<span class="gi">+		data = readl(base + PCIE_RC_DL_MDIO_WR_DATA);</span>
<span class="gi">+	}</span>
<span class="gi">+</span>
<span class="gi">+	return MDIO_WT_DONE(data) ? 0 : -EIO;</span>
<span class="gi">+}</span>
<span class="gi">+</span>
<span class="gi">+/*</span>
<span class="gi">+ * Configures device for Spread Spectrum Clocking (SSC) mode; a negative</span>
<span class="gi">+ * return value indicates error.</span>
<span class="gi">+ */</span>
<span class="gi">+static int brcm_pcie_set_ssc(struct brcm_pcie *pcie)</span>
<span class="gi">+{</span>
<span class="gi">+	int pll, ssc;</span>
<span class="gi">+	int ret;</span>
<span class="gi">+	u32 tmp;</span>
<span class="gi">+</span>
<span class="gi">+	ret = brcm_pcie_mdio_write(pcie-&gt;base, MDIO_PORT0, SET_ADDR_OFFSET,</span>
<span class="gi">+				   SSC_REGS_ADDR);</span>
<span class="gi">+	if (ret &lt; 0)</span>
<span class="gi">+		return ret;</span>
<span class="gi">+</span>
<span class="gi">+	ret = brcm_pcie_mdio_read(pcie-&gt;base, MDIO_PORT0,</span>
<span class="gi">+				  SSC_CNTL_OFFSET, &amp;tmp);</span>
<span class="gi">+	if (ret &lt; 0)</span>
<span class="gi">+		return ret;</span>
<span class="gi">+</span>
<span class="gi">+	u32p_replace_bits(&amp;tmp, 1, SSC_CNTL_OVRD_EN_MASK);</span>
<span class="gi">+	u32p_replace_bits(&amp;tmp, 1, SSC_CNTL_OVRD_VAL_MASK);</span>
<span class="gi">+	ret = brcm_pcie_mdio_write(pcie-&gt;base, MDIO_PORT0,</span>
<span class="gi">+				   SSC_CNTL_OFFSET, tmp);</span>
<span class="gi">+	if (ret &lt; 0)</span>
<span class="gi">+		return ret;</span>
<span class="gi">+</span>
<span class="gi">+	usleep_range(1000, 2000);</span>
<span class="gi">+	ret = brcm_pcie_mdio_read(pcie-&gt;base, MDIO_PORT0,</span>
<span class="gi">+				  SSC_STATUS_OFFSET, &amp;tmp);</span>
<span class="gi">+	if (ret &lt; 0)</span>
<span class="gi">+		return ret;</span>
<span class="gi">+</span>
<span class="gi">+	ssc = FIELD_GET(SSC_STATUS_SSC_MASK, tmp);</span>
<span class="gi">+	pll = FIELD_GET(SSC_STATUS_PLL_LOCK_MASK, tmp);</span>
<span class="gi">+</span>
<span class="gi">+	return ssc &amp;&amp; pll ? 0 : -EIO;</span>
<span class="gi">+}</span>
<span class="gi">+</span>
<span class="gi">+/* Limits operation to a specific generation (1, 2, or 3) */</span>
<span class="gi">+static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen)</span>
<span class="gi">+{</span>
<span class="gi">+	u16 lnkctl2 = readw(pcie-&gt;base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);</span>
<span class="gi">+	u32 lnkcap = readl(pcie-&gt;base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);</span>
<span class="gi">+</span>
<span class="gi">+	lnkcap = (lnkcap &amp; ~PCI_EXP_LNKCAP_SLS) | gen;</span>
<span class="gi">+	writel(lnkcap, pcie-&gt;base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);</span>
<span class="gi">+</span>
<span class="gi">+	lnkctl2 = (lnkctl2 &amp; ~0xf) | gen;</span>
<span class="gi">+	writew(lnkctl2, pcie-&gt;base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);</span>
<span class="gi">+}</span>
<span class="gi">+</span>
<span class="gi">+static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,</span>
<span class="gi">+				       unsigned int win, u64 cpu_addr,</span>
<span class="gi">+				       u64 pcie_addr, u64 size)</span>
<span class="gi">+{</span>
<span class="gi">+	u32 cpu_addr_mb_high, limit_addr_mb_high;</span>
<span class="gi">+	phys_addr_t cpu_addr_mb, limit_addr_mb;</span>
<span class="gi">+	int high_addr_shift;</span>
<span class="gi">+	u32 tmp;</span>
<span class="gi">+</span>
<span class="gi">+	/* Set the base of the pcie_addr window */</span>
<span class="gi">+	writel(lower_32_bits(pcie_addr), pcie-&gt;base + PCIE_MEM_WIN0_LO(win));</span>
<span class="gi">+	writel(upper_32_bits(pcie_addr), pcie-&gt;base + PCIE_MEM_WIN0_HI(win));</span>
<span class="gi">+</span>
<span class="gi">+	/* Write the addr base &amp; limit lower bits (in MBs) */</span>
<span class="gi">+	cpu_addr_mb = cpu_addr / SZ_1M;</span>
<span class="gi">+	limit_addr_mb = (cpu_addr + size - 1) / SZ_1M;</span>
<span class="gi">+</span>
<span class="gi">+	tmp = readl(pcie-&gt;base + PCIE_MEM_WIN0_BASE_LIMIT(win));</span>
<span class="gi">+	u32p_replace_bits(&amp;tmp, cpu_addr_mb,</span>
<span class="gi">+			  PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK);</span>
<span class="gi">+	u32p_replace_bits(&amp;tmp, limit_addr_mb,</span>
<span class="gi">+			  PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK);</span>
<span class="gi">+	writel(tmp, pcie-&gt;base + PCIE_MEM_WIN0_BASE_LIMIT(win));</span>
<span class="gi">+</span>
<span class="gi">+	/* Write the cpu &amp; limit addr upper bits */</span>
<span class="gi">+	high_addr_shift =</span>
<span class="gi">+		HWEIGHT32(PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK);</span>
<span class="gi">+</span>
<span class="gi">+	cpu_addr_mb_high = cpu_addr_mb &gt;&gt; high_addr_shift;</span>
<span class="gi">+	tmp = readl(pcie-&gt;base + PCIE_MEM_WIN0_BASE_HI(win));</span>
<span class="gi">+	u32p_replace_bits(&amp;tmp, cpu_addr_mb_high,</span>
<span class="gi">+			  PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK);</span>
<span class="gi">+	writel(tmp, pcie-&gt;base + PCIE_MEM_WIN0_BASE_HI(win));</span>
<span class="gi">+</span>
<span class="gi">+	limit_addr_mb_high = limit_addr_mb &gt;&gt; high_addr_shift;</span>
<span class="gi">+	tmp = readl(pcie-&gt;base + PCIE_MEM_WIN0_LIMIT_HI(win));</span>
<span class="gi">+	u32p_replace_bits(&amp;tmp, limit_addr_mb_high,</span>
<span class="gi">+			  PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK);</span>
<span class="gi">+	writel(tmp, pcie-&gt;base + PCIE_MEM_WIN0_LIMIT_HI(win));</span>
<span class="gi">+}</span>
<span class="gi">+</span>
<span class="gi">+/* The controller is capable of serving in both RC and EP roles */</span>
<span class="gi">+static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)</span>
<span class="gi">+{</span>
<span class="gi">+	void __iomem *base = pcie-&gt;base;</span>
<span class="gi">+	u32 val = readl(base + PCIE_MISC_PCIE_STATUS);</span>
<span class="gi">+</span>
<span class="gi">+	return !!FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK, val);</span>
<span class="gi">+}</span>
<span class="gi">+</span>
<span class="gi">+static bool brcm_pcie_link_up(struct brcm_pcie *pcie)</span>
<span class="gi">+{</span>
<span class="gi">+	u32 val = readl(pcie-&gt;base + PCIE_MISC_PCIE_STATUS);</span>
<span class="gi">+	u32 dla = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK, val);</span>
<span class="gi">+	u32 plu = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK, val);</span>
<span class="gi">+</span>
<span class="gi">+	return dla &amp;&amp; plu;</span>
<span class="gi">+}</span>
<span class="gi">+</span>
<span class="gi">+/* Configuration space read/write support */</span>
<span class="gi">+static inline int brcm_pcie_cfg_index(int busnr, int devfn, int reg)</span>
<span class="gi">+{</span>
<span class="gi">+	return ((PCI_SLOT(devfn) &amp; 0x1f) &lt;&lt; PCIE_EXT_SLOT_SHIFT)</span>
<span class="gi">+		| ((PCI_FUNC(devfn) &amp; 0x07) &lt;&lt; PCIE_EXT_FUNC_SHIFT)</span>
<span class="gi">+		| (busnr &lt;&lt; PCIE_EXT_BUSNUM_SHIFT)</span>
<span class="gi">+		| (reg &amp; ~3);</span>
<span class="gi">+}</span>
<span class="gi">+</span>
<span class="gi">+static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,</span>
<span class="gi">+					int where)</span>
<span class="gi">+{</span>
<span class="gi">+	struct brcm_pcie *pcie = bus-&gt;sysdata;</span>
<span class="gi">+	void __iomem *base = pcie-&gt;base;</span>
<span class="gi">+	int idx;</span>
<span class="gi">+</span>
<span class="gi">+	/* Accesses to the RC go right to the RC registers if slot==0 */</span>
<span class="gi">+	if (pci_is_root_bus(bus))</span>
<span class="gi">+		return PCI_SLOT(devfn) ? NULL : base + where;</span>
<span class="gi">+</span>
<span class="gi">+	/* For devices, write to the config space index register */</span>
<span class="gi">+	idx = brcm_pcie_cfg_index(bus-&gt;number, devfn, 0);</span>
<span class="gi">+	writel(idx, pcie-&gt;base + PCIE_EXT_CFG_INDEX);</span>
<span class="gi">+	return base + PCIE_EXT_CFG_DATA + where;</span>
<span class="gi">+}</span>
<span class="gi">+</span>
<span class="gi">+static struct pci_ops brcm_pcie_ops = {</span>
<span class="gi">+	.map_bus = brcm_pcie_map_conf,</span>
<span class="gi">+	.read = pci_generic_config_read,</span>
<span class="gi">+	.write = pci_generic_config_write,</span>
<span class="gi">+};</span>
<span class="gi">+</span>
<span class="gi">+static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie, u32 val)</span>
<span class="gi">+{</span>
<span class="gi">+	u32 tmp;</span>
<span class="gi">+</span>
<span class="gi">+	tmp = readl(pcie-&gt;base + PCIE_RGR1_SW_INIT_1);</span>
<span class="gi">+	u32p_replace_bits(&amp;tmp, val, PCIE_RGR1_SW_INIT_1_INIT_MASK);</span>
<span class="gi">+	writel(tmp, pcie-&gt;base + PCIE_RGR1_SW_INIT_1);</span>
<span class="gi">+}</span>
<span class="gi">+</span>
<span class="gi">+static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie, u32 val)</span>
<span class="gi">+{</span>
<span class="gi">+	u32 tmp;</span>
<span class="gi">+</span>
<span class="gi">+	tmp = readl(pcie-&gt;base + PCIE_RGR1_SW_INIT_1);</span>
<span class="gi">+	u32p_replace_bits(&amp;tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK);</span>
<span class="gi">+	writel(tmp, pcie-&gt;base + PCIE_RGR1_SW_INIT_1);</span>
<span class="gi">+}</span>
<span class="gi">+</span>
<span class="gi">+static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie,</span>
<span class="gi">+							u64 *rc_bar2_size,</span>
<span class="gi">+							u64 *rc_bar2_offset)</span>
<span class="gi">+{</span>
<span class="gi">+	struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);</span>
<span class="gi">+	struct device *dev = pcie-&gt;dev;</span>
<span class="gi">+	struct resource_entry *entry;</span>
<span class="gi">+</span>
<span class="gi">+	entry = resource_list_first_type(&amp;bridge-&gt;dma_ranges, IORESOURCE_MEM);</span>
<span class="gi">+	if (!entry)</span>
<span class="gi">+		return -ENODEV;</span>
<span class="gi">+</span>
<span class="gi">+</span>
<span class="gi">+	/*</span>
<span class="gi">+	 * The controller expects the inbound window offset to be calculated as</span>
<span class="gi">+	 * the difference between PCIe&#39;s address space and CPU&#39;s. The offset</span>
<span class="gi">+	 * provided by the firmware is calculated the opposite way, so we</span>
<span class="gi">+	 * negate it.</span>
<span class="gi">+	 */</span>
<span class="gi">+	*rc_bar2_offset = -entry-&gt;offset;</span>
<span class="gi">+	*rc_bar2_size = 1ULL &lt;&lt; fls64(entry-&gt;res-&gt;end - entry-&gt;res-&gt;start);</span>
<span class="gi">+</span>
<span class="gi">+	/*</span>
<span class="gi">+	 * We validate the inbound memory view even though we should trust</span>
<span class="gi">+	 * whatever the device-tree provides. This is because of an HW issue on</span>
<span class="gi">+	 * early Raspberry Pi 4&#39;s revisions (bcm2711). It turns out its</span>
<span class="gi">+	 * firmware has to dynamically edit dma-ranges due to a bug on the</span>
<span class="gi">+	 * PCIe controller integration, which prohibits any access above the</span>
<span class="gi">+	 * lower 3GB of memory. Given this, we decided to keep the dma-ranges</span>
<span class="gi">+	 * in check, avoiding hard to debug device-tree related issues in the</span>
<span class="gi">+	 * future:</span>
<span class="gi">+	 *</span>
<span class="gi">+	 * The PCIe host controller by design must set the inbound viewport to</span>
<span class="gi">+	 * be a contiguous arrangement of all of the system&#39;s memory.  In</span>
<span class="gi">+	 * addition, its size mut be a power of two.  To further complicate</span>
<span class="gi">+	 * matters, the viewport must start on a pcie-address that is aligned</span>
<span class="gi">+	 * on a multiple of its size.  If a portion of the viewport does not</span>
<span class="gi">+	 * represent system memory -- e.g. 3GB of memory requires a 4GB</span>
<span class="gi">+	 * viewport -- we can map the outbound memory in or after 3GB and even</span>
<span class="gi">+	 * though the viewport will overlap the outbound memory the controller</span>
<span class="gi">+	 * will know to send outbound memory downstream and everything else</span>
<span class="gi">+	 * upstream.</span>
<span class="gi">+	 *</span>
<span class="gi">+	 * For example:</span>
<span class="gi">+	 *</span>
<span class="gi">+	 * - The best-case scenario, memory up to 3GB, is to place the inbound</span>
<span class="gi">+	 *   region in the first 4GB of pcie-space, as some legacy devices can</span>
<span class="gi">+	 *   only address 32bits. We would also like to put the MSI under 4GB</span>
<span class="gi">+	 *   as well, since some devices require a 32bit MSI target address.</span>
<span class="gi">+	 *</span>
<span class="gi">+	 * - If the system memory is 4GB or larger we cannot start the inbound</span>
<span class="gi">+	 *   region at location 0 (since we have to allow some space for</span>
<span class="gi">+	 *   outbound memory @ 3GB). So instead it will  start at the 1x</span>
<span class="gi">+	 *   multiple of its size</span>
<span class="gi">+	 */</span>
<span class="gi">+	if (!*rc_bar2_size || *rc_bar2_offset % *rc_bar2_size ||</span>
<span class="gi">+	    (*rc_bar2_offset &lt; SZ_4G &amp;&amp; *rc_bar2_offset &gt; SZ_2G)) {</span>
<span class="gi">+		dev_err(dev, &quot;Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n&quot;,</span>
<span class="gi">+			*rc_bar2_size, *rc_bar2_offset);</span>
<span class="gi">+		return -EINVAL;</span>
<span class="gi">+	}</span>
<span class="gi">+</span>
<span class="gi">+	return 0;</span>
<span class="gi">+}</span>
<span class="gi">+</span>
<span class="gi">+static int brcm_pcie_setup(struct brcm_pcie *pcie)</span>
<span class="gi">+{</span>
<span class="gi">+	struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);</span>
<span class="gi">+	u64 rc_bar2_offset, rc_bar2_size;</span>
<span class="gi">+	void __iomem *base = pcie-&gt;base;</span>
<span class="gi">+	struct device *dev = pcie-&gt;dev;</span>
<span class="gi">+	struct resource_entry *entry;</span>
<span class="gi">+	unsigned int scb_size_val;</span>
<span class="gi">+	bool ssc_good = false;</span>
<span class="gi">+	struct resource *res;</span>
<span class="gi">+	int num_out_wins = 0;</span>
<span class="gi">+	u16 nlw, cls, lnksta;</span>
<span class="gi">+	int i, ret;</span>
<span class="gi">+	u32 tmp;</span>
<span class="gi">+</span>
<span class="gi">+	/* Reset the bridge */</span>
<span class="gi">+	brcm_pcie_bridge_sw_init_set(pcie, 1);</span>
<span class="gi">+</span>
<span class="gi">+	usleep_range(100, 200);</span>
<span class="gi">+</span>
<span class="gi">+	/* Take the bridge out of reset */</span>
<span class="gi">+	brcm_pcie_bridge_sw_init_set(pcie, 0);</span>
<span class="gi">+</span>
<span class="gi">+	tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);</span>
<span class="gi">+	tmp &amp;= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;</span>
<span class="gi">+	writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);</span>
<span class="gi">+	/* Wait for SerDes to be stable */</span>
<span class="gi">+	usleep_range(100, 200);</span>
<span class="gi">+</span>
<span class="gi">+	/* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */</span>
<span class="gi">+	u32p_replace_bits(&amp;tmp, 1, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK);</span>
<span class="gi">+	u32p_replace_bits(&amp;tmp, 1, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK);</span>
<span class="gi">+	u32p_replace_bits(&amp;tmp, PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_128,</span>
<span class="gi">+			  PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK);</span>
<span class="gi">+	writel(tmp, base + PCIE_MISC_MISC_CTRL);</span>
<span class="gi">+</span>
<span class="gi">+	ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &amp;rc_bar2_size,</span>
<span class="gi">+						    &amp;rc_bar2_offset);</span>
<span class="gi">+	if (ret)</span>
<span class="gi">+		return ret;</span>
<span class="gi">+</span>
<span class="gi">+	tmp = lower_32_bits(rc_bar2_offset);</span>
<span class="gi">+	u32p_replace_bits(&amp;tmp, brcm_pcie_encode_ibar_size(rc_bar2_size),</span>
<span class="gi">+			  PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK);</span>
<span class="gi">+	writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);</span>
<span class="gi">+	writel(upper_32_bits(rc_bar2_offset),</span>
<span class="gi">+	       base + PCIE_MISC_RC_BAR2_CONFIG_HI);</span>
<span class="gi">+</span>
<span class="gi">+	scb_size_val = rc_bar2_size ?</span>
<span class="gi">+		       ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */</span>
<span class="gi">+	tmp = readl(base + PCIE_MISC_MISC_CTRL);</span>
<span class="gi">+	u32p_replace_bits(&amp;tmp, scb_size_val,</span>
<span class="gi">+			  PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK);</span>
<span class="gi">+	writel(tmp, base + PCIE_MISC_MISC_CTRL);</span>
<span class="gi">+</span>
<span class="gi">+	/* disable the PCIe-&gt;GISB memory window (RC_BAR1) */</span>
<span class="gi">+	tmp = readl(base + PCIE_MISC_RC_BAR1_CONFIG_LO);</span>
<span class="gi">+	tmp &amp;= ~PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK;</span>
<span class="gi">+	writel(tmp, base + PCIE_MISC_RC_BAR1_CONFIG_LO);</span>
<span class="gi">+</span>
<span class="gi">+	/* disable the PCIe-&gt;SCB memory window (RC_BAR3) */</span>
<span class="gi">+	tmp = readl(base + PCIE_MISC_RC_BAR3_CONFIG_LO);</span>
<span class="gi">+	tmp &amp;= ~PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK;</span>
<span class="gi">+	writel(tmp, base + PCIE_MISC_RC_BAR3_CONFIG_LO);</span>
<span class="gi">+</span>
<span class="gi">+	/* Mask all interrupts since we are not handling any yet */</span>
<span class="gi">+	writel(0xffffffff, pcie-&gt;base + PCIE_MSI_INTR2_MASK_SET);</span>
<span class="gi">+</span>
<span class="gi">+	/* clear any interrupts we find on boot */</span>
<span class="gi">+	writel(0xffffffff, pcie-&gt;base + PCIE_MSI_INTR2_CLR);</span>
<span class="gi">+</span>
<span class="gi">+	if (pcie-&gt;gen)</span>
<span class="gi">+		brcm_pcie_set_gen(pcie, pcie-&gt;gen);</span>
<span class="gi">+</span>
<span class="gi">+	/* Unassert the fundamental reset */</span>
<span class="gi">+	brcm_pcie_perst_set(pcie, 0);</span>
<span class="gi">+</span>
<span class="gi">+	/*</span>
<span class="gi">+	 * Give the RC/EP time to wake up, before trying to configure RC.</span>
<span class="gi">+	 * Intermittently check status for link-up, up to a total of 100ms.</span>
<span class="gi">+	 */</span>
<span class="gi">+	for (i = 0; i &lt; 100 &amp;&amp; !brcm_pcie_link_up(pcie); i += 5)</span>
<span class="gi">+		msleep(5);</span>
<span class="gi">+</span>
<span class="gi">+	if (!brcm_pcie_link_up(pcie)) {</span>
<span class="gi">+		dev_err(dev, &quot;link down\n&quot;);</span>
<span class="gi">+		return -ENODEV;</span>
<span class="gi">+	}</span>
<span class="gi">+</span>
<span class="gi">+	if (!brcm_pcie_rc_mode(pcie)) {</span>
<span class="gi">+		dev_err(dev, &quot;PCIe misconfigured; is in EP mode\n&quot;);</span>
<span class="gi">+		return -EINVAL;</span>
<span class="gi">+	}</span>
<span class="gi">+</span>
<span class="gi">+	resource_list_for_each_entry(entry, &amp;bridge-&gt;windows) {</span>
<span class="gi">+		res = entry-&gt;res;</span>
<span class="gi">+</span>
<span class="gi">+		if (resource_type(res) != IORESOURCE_MEM)</span>
<span class="gi">+			continue;</span>
<span class="gi">+</span>
<span class="gi">+		if (num_out_wins &gt;= BRCM_NUM_PCIE_OUT_WINS) {</span>
<span class="gi">+			dev_err(pcie-&gt;dev, &quot;too many outbound wins\n&quot;);</span>
<span class="gi">+			return -EINVAL;</span>
<span class="gi">+		}</span>
<span class="gi">+</span>
<span class="gi">+		brcm_pcie_set_outbound_win(pcie, num_out_wins, res-&gt;start,</span>
<span class="gi">+					   res-&gt;start - entry-&gt;offset,</span>
<span class="gi">+					   resource_size(res));</span>
<span class="gi">+		num_out_wins++;</span>
<span class="gi">+	}</span>
<span class="gi">+</span>
<span class="gi">+	/*</span>
<span class="gi">+	 * For config space accesses on the RC, show the right class for</span>
<span class="gi">+	 * a PCIe-PCIe bridge (the default setting is to be EP mode).</span>
<span class="gi">+	 */</span>
<span class="gi">+	tmp = readl(base + PCIE_RC_CFG_PRIV1_ID_VAL3);</span>
<span class="gi">+	u32p_replace_bits(&amp;tmp, 0x060400,</span>
<span class="gi">+			  PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK);</span>
<span class="gi">+	writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3);</span>
<span class="gi">+</span>
<span class="gi">+	if (pcie-&gt;ssc) {</span>
<span class="gi">+		ret = brcm_pcie_set_ssc(pcie);</span>
<span class="gi">+		if (ret == 0)</span>
<span class="gi">+			ssc_good = true;</span>
<span class="gi">+		else</span>
<span class="gi">+			dev_err(dev, &quot;failed attempt to enter ssc mode\n&quot;);</span>
<span class="gi">+	}</span>
<span class="gi">+</span>
<span class="gi">+	lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);</span>
<span class="gi">+	cls = FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta);</span>
<span class="gi">+	nlw = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta);</span>
<span class="gi">+	dev_info(dev, &quot;link up, %s x%u %s\n&quot;,</span>
<span class="gi">+		 PCIE_SPEED2STR(cls + PCI_SPEED_133MHz_PCIX_533),</span>
<span class="gi">+		 nlw, ssc_good ? &quot;(SSC)&quot; : &quot;(!SSC)&quot;);</span>
<span class="gi">+</span>
<span class="gi">+	/* PCIe-&gt;SCB endian mode for BAR */</span>
<span class="gi">+	tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);</span>
<span class="gi">+	u32p_replace_bits(&amp;tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN,</span>
<span class="gi">+		PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK);</span>
<span class="gi">+	writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);</span>
<span class="gi">+</span>
<span class="gi">+	/*</span>
<span class="gi">+	 * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1</span>
<span class="gi">+	 * is enabled =&gt; setting the CLKREQ_DEBUG_ENABLE field to 1.</span>
<span class="gi">+	 */</span>
<span class="gi">+	tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);</span>
<span class="gi">+	tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;</span>
<span class="gi">+	writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);</span>
<span class="gi">+</span>
<span class="gi">+	return 0;</span>
<span class="gi">+}</span>
<span class="gi">+</span>
<span class="gi">+/* L23 is a low-power PCIe link state */</span>
<span class="gi">+static void brcm_pcie_enter_l23(struct brcm_pcie *pcie)</span>
<span class="gi">+{</span>
<span class="gi">+	void __iomem *base = pcie-&gt;base;</span>
<span class="gi">+	int l23, i;</span>
<span class="gi">+	u32 tmp;</span>
<span class="gi">+</span>
<span class="gi">+	/* Assert request for L23 */</span>
<span class="gi">+	tmp = readl(base + PCIE_MISC_PCIE_CTRL);</span>
<span class="gi">+	u32p_replace_bits(&amp;tmp, 1, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK);</span>
<span class="gi">+	writel(tmp, base + PCIE_MISC_PCIE_CTRL);</span>
<span class="gi">+</span>
<span class="gi">+	/* Wait up to 36 msec for L23 */</span>
<span class="gi">+	tmp = readl(base + PCIE_MISC_PCIE_STATUS);</span>
<span class="gi">+	l23 = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK, tmp);</span>
<span class="gi">+	for (i = 0; i &lt; 15 &amp;&amp; !l23; i++) {</span>
<span class="gi">+		usleep_range(2000, 2400);</span>
<span class="gi">+		tmp = readl(base + PCIE_MISC_PCIE_STATUS);</span>
<span class="gi">+		l23 = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK,</span>
<span class="gi">+				tmp);</span>
<span class="gi">+	}</span>
<span class="gi">+</span>
<span class="gi">+	if (!l23)</span>
<span class="gi">+		dev_err(pcie-&gt;dev, &quot;failed to enter low-power link state\n&quot;);</span>
<span class="gi">+}</span>
<span class="gi">+</span>
<span class="gi">+static void brcm_pcie_turn_off(struct brcm_pcie *pcie)</span>
<span class="gi">+{</span>
<span class="gi">+	void __iomem *base = pcie-&gt;base;</span>
<span class="gi">+	int tmp;</span>
<span class="gi">+</span>
<span class="gi">+	if (brcm_pcie_link_up(pcie))</span>
<span class="gi">+		brcm_pcie_enter_l23(pcie);</span>
<span class="gi">+	/* Assert fundamental reset */</span>
<span class="gi">+	brcm_pcie_perst_set(pcie, 1);</span>
<span class="gi">+</span>
<span class="gi">+	/* Deassert request for L23 in case it was asserted */</span>
<span class="gi">+	tmp = readl(base + PCIE_MISC_PCIE_CTRL);</span>
<span class="gi">+	u32p_replace_bits(&amp;tmp, 0, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK);</span>
<span class="gi">+	writel(tmp, base + PCIE_MISC_PCIE_CTRL);</span>
<span class="gi">+</span>
<span class="gi">+	/* Turn off SerDes */</span>
<span class="gi">+	tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);</span>
<span class="gi">+	u32p_replace_bits(&amp;tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);</span>
<span class="gi">+	writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);</span>
<span class="gi">+</span>
<span class="gi">+	/* Shutdown PCIe bridge */</span>
<span class="gi">+	brcm_pcie_bridge_sw_init_set(pcie, 1);</span>
<span class="gi">+}</span>
<span class="gi">+</span>
<span class="gi">+static void __brcm_pcie_remove(struct brcm_pcie *pcie)</span>
<span class="gi">+{</span>
<span class="gi">+	brcm_pcie_turn_off(pcie);</span>
<span class="gi">+	clk_disable_unprepare(pcie-&gt;clk);</span>
<span class="gi">+	clk_put(pcie-&gt;clk);</span>
<span class="gi">+}</span>
<span class="gi">+</span>
<span class="gi">+static int brcm_pcie_remove(struct platform_device *pdev)</span>
<span class="gi">+{</span>
<span class="gi">+	struct brcm_pcie *pcie = platform_get_drvdata(pdev);</span>
<span class="gi">+</span>
<span class="gi">+	pci_stop_root_bus(pcie-&gt;root_bus);</span>
<span class="gi">+	pci_remove_root_bus(pcie-&gt;root_bus);</span>
<span class="gi">+	__brcm_pcie_remove(pcie);</span>
<span class="gi">+</span>
<span class="gi">+	return 0;</span>
<span class="gi">+}</span>
<span class="gi">+</span>
<span class="gi">+static int brcm_pcie_probe(struct platform_device *pdev)</span>
<span class="gi">+{</span>
<span class="gi">+	struct device_node *np = pdev-&gt;dev.of_node;</span>
<span class="gi">+	struct pci_host_bridge *bridge;</span>
<span class="gi">+	struct brcm_pcie *pcie;</span>
<span class="gi">+	struct pci_bus *child;</span>
<span class="gi">+	struct resource *res;</span>
<span class="gi">+	int ret;</span>
<span class="gi">+</span>
<span class="gi">+	bridge = devm_pci_alloc_host_bridge(&amp;pdev-&gt;dev, sizeof(*pcie));</span>
<span class="gi">+	if (!bridge)</span>
<span class="gi">+		return -ENOMEM;</span>
<span class="gi">+</span>
<span class="gi">+	pcie = pci_host_bridge_priv(bridge);</span>
<span class="gi">+	pcie-&gt;dev = &amp;pdev-&gt;dev;</span>
<span class="gi">+	pcie-&gt;np = np;</span>
<span class="gi">+</span>
<span class="gi">+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);</span>
<span class="gi">+	pcie-&gt;base = devm_ioremap_resource(&amp;pdev-&gt;dev, res);</span>
<span class="gi">+	if (IS_ERR(pcie-&gt;base))</span>
<span class="gi">+		return PTR_ERR(pcie-&gt;base);</span>
<span class="gi">+</span>
<span class="gi">+	pcie-&gt;clk = devm_clk_get_optional(&amp;pdev-&gt;dev, &quot;sw_pcie&quot;);</span>
<span class="gi">+	if (IS_ERR(pcie-&gt;clk))</span>
<span class="gi">+		return PTR_ERR(pcie-&gt;clk);</span>
<span class="gi">+</span>
<span class="gi">+	ret = of_pci_get_max_link_speed(np);</span>
<span class="gi">+	pcie-&gt;gen = (ret &lt; 0) ? 0 : ret;</span>
<span class="gi">+</span>
<span class="gi">+	pcie-&gt;ssc = of_property_read_bool(np, &quot;brcm,enable-ssc&quot;);</span>
<span class="gi">+</span>
<span class="gi">+	ret = pci_parse_request_of_pci_ranges(pcie-&gt;dev, &amp;bridge-&gt;windows,</span>
<span class="gi">+					      &amp;bridge-&gt;dma_ranges, NULL);</span>
<span class="gi">+	if (ret)</span>
<span class="gi">+		return ret;</span>
<span class="gi">+</span>
<span class="gi">+	ret = clk_prepare_enable(pcie-&gt;clk);</span>
<span class="gi">+	if (ret) {</span>
<span class="gi">+		dev_err(&amp;pdev-&gt;dev, &quot;could not enable clock\n&quot;);</span>
<span class="gi">+		return ret;</span>
<span class="gi">+	}</span>
<span class="gi">+</span>
<span class="gi">+	ret = brcm_pcie_setup(pcie);</span>
<span class="gi">+	if (ret)</span>
<span class="gi">+		goto fail;</span>
<span class="gi">+</span>
<span class="gi">+	bridge-&gt;dev.parent = &amp;pdev-&gt;dev;</span>
<span class="gi">+	bridge-&gt;busnr = 0;</span>
<span class="gi">+	bridge-&gt;ops = &amp;brcm_pcie_ops;</span>
<span class="gi">+	bridge-&gt;sysdata = pcie;</span>
<span class="gi">+	bridge-&gt;map_irq = of_irq_parse_and_map_pci;</span>
<span class="gi">+	bridge-&gt;swizzle_irq = pci_common_swizzle;</span>
<span class="gi">+</span>
<span class="gi">+	ret = pci_scan_root_bus_bridge(bridge);</span>
<span class="gi">+	if (ret &lt; 0) {</span>
<span class="gi">+		dev_err(pcie-&gt;dev, &quot;Scanning root bridge failed\n&quot;);</span>
<span class="gi">+		goto fail;</span>
<span class="gi">+	}</span>
<span class="gi">+</span>
<span class="gi">+	pci_assign_unassigned_bus_resources(bridge-&gt;bus);</span>
<span class="gi">+	list_for_each_entry(child, &amp;bridge-&gt;bus-&gt;children, node)</span>
<span class="gi">+		pcie_bus_configure_settings(child);</span>
<span class="gi">+	pci_bus_add_devices(bridge-&gt;bus);</span>
<span class="gi">+	platform_set_drvdata(pdev, pcie);</span>
<span class="gi">+	pcie-&gt;root_bus = bridge-&gt;bus;</span>
<span class="gi">+</span>
<span class="gi">+	return 0;</span>
<span class="gi">+fail:</span>
<span class="gi">+	__brcm_pcie_remove(pcie);</span>
<span class="gi">+	return ret;</span>
<span class="gi">+}</span>
<span class="gi">+</span>
<span class="gi">+static const struct of_device_id brcm_pcie_match[] = {</span>
<span class="gi">+	{ .compatible = &quot;brcm,bcm2711-pcie&quot; },</span>
<span class="gi">+	{},</span>
<span class="gi">+};</span>
<span class="gi">+MODULE_DEVICE_TABLE(of, brcm_pcie_match);</span>
<span class="gi">+</span>
<span class="gi">+static struct platform_driver brcm_pcie_driver = {</span>
<span class="gi">+	.probe = brcm_pcie_probe,</span>
<span class="gi">+	.remove = brcm_pcie_remove,</span>
<span class="gi">+	.driver = {</span>
<span class="gi">+		.name = &quot;brcm-pcie&quot;,</span>
<span class="gi">+		.of_match_table = brcm_pcie_match,</span>
<span class="gi">+	},</span>
<span class="gi">+};</span>
<span class="gi">+module_platform_driver(brcm_pcie_driver);</span>
<span class="gi">+</span>
<span class="gi">+MODULE_LICENSE(&quot;GPL&quot;);</span>
<span class="gi">+MODULE_DESCRIPTION(&quot;Broadcom STB PCIe RC driver&quot;);</span>
<span class="gi">+MODULE_AUTHOR(&quot;Broadcom&quot;);</span>
</pre></div>
</code></pre></td></tr></table>
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