1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
|
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "ath79.dtsi"
/ {
compatible = "qca,ar7240";
#address-cells = <1>;
#size-cells = <1>;
chosen {
bootargs = "console=ttyS0,115200";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "mips,mips24Kc";
clocks = <&pll ATH79_CLK_CPU>;
reg = <0>;
};
};
extosc: ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "ref";
clock-frequency = <40000000>;
};
ahb: ahb {
apb {
ddr_ctrl: memory-controller@18000000 {
compatible = "qca,ar9132-ddr-controller",
"qca,ar7240-ddr-controller";
reg = <0x18000000 0x100>;
#qca,ddr-wb-channel-cells = <1>;
};
uart: uart@18020000 {
compatible = "ns16550a";
reg = <0x18020000 0x20>;
interrupts = <3>;
clocks = <&pll ATH79_CLK_AHB>;
clock-names = "uart";
reg-io-width = <4>;
reg-shift = <2>;
no-loopback-test;
};
gpio: gpio@18040000 {
compatible = "qca,ar7240-gpio",
"qca,ar7100-gpio";
reg = <0x18040000 0x28>;
interrupts = <2>;
ngpios = <18>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pinmux: pinmux@18040028 {
compatible = "pinctrl-single";
reg = <0x18040028 0x8>;
pinctrl-single,bit-per-mux;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x1>;
#pinctrl-cells = <2>;
jtag_disable_pins: pinmux_jtag_disable_pins {
pinctrl-single,bits = <0x0 0x1 0x1>;
};
switch_led_disable_pins: pinmux_switch_led_disable_pins {
pinctrl-single,bits = <0x0 0x0 0xf8>;
};
clks_disable_pins: pinmux_clks_disable_pins {
pinctrl-single,bits = <0x0 0x0 0x81f00>;
};
};
pll: pll-controller@18050000 {
compatible = "qca,ar7240-pll", "syscon";
reg = <0x18050000 0x3c>;
clocks = <&extosc>;
clock-names = "ref";
#clock-cells = <1>;
clock-output-names = "cpu", "ddr", "ahb";
};
wdt: wdt@18060008 {
compatible = "qca,ar7130-wdt";
reg = <0x18060008 0x8>;
interrupts = <4>;
clocks = <&pll ATH79_CLK_AHB>;
clock-names = "wdt";
};
rst: reset-controller@1806001c {
compatible = "qca,ar7240-reset",
"qca,ar7100-reset";
reg = <0x1806001c 0x4>;
#reset-cells = <1>;
};
pcie: pcie-controller@180c0000 {
compatible = "qcom,ar7240-pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0x0>;
reg = <0x180c0000 0x1000>, /* CRP */
<0x180f0000 0x100>, /* CTRL */
<0x14000000 0x1000>; /* CFG */
reg-names = "crp_base", "ctrl_base", "cfg_base";
ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000 /* pci memory */
0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
interrupt-parent = <&cpuintc>;
interrupts = <2>;
resets = <&rst 6>, <&rst 7>;
reset-names = "hc", "phy";
device_type = "pci";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 1>;
interrupt-map = <0 0 0 0 &pcie 0>;
status = "disabled";
};
};
spi: spi@1f000000 {
compatible = "qca,ar7240-spi",
"qca,ar7100-spi";
reg = <0x1f000000 0x10>;
clocks = <&pll ATH79_CLK_AHB>;
clock-names = "ahb";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
};
};
&cpuintc {
qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
<&ddr_ctrl 0>, <&ddr_ctrl 1>;
};
|
