blob: 2355ad7e7768de3794c371e1ae9736eb9f125491 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
|
--- a/arch/mips/ath79/gpio.c
+++ b/arch/mips/ath79/gpio.c
@@ -185,15 +185,24 @@ void __init ath79_gpio_output_select(uns
{
void __iomem *base = ath79_gpio_base;
unsigned long flags;
- unsigned int reg;
+ unsigned int reg, reg_base;
+ unsigned long gpio_count;
u32 t, s;
- BUG_ON(!soc_is_ar934x());
+ if (soc_is_ar934x()) {
+ gpio_count = AR934X_GPIO_COUNT;
+ reg_base = AR934X_GPIO_REG_OUT_FUNC0;
+ } else if (soc_is_qca955x()) {
+ gpio_count = QCA955X_GPIO_COUNT;
+ reg_base = QCA955X_GPIO_REG_OUT_FUNC0;
+ } else {
+ BUG();
+ }
- if (gpio >= AR934X_GPIO_COUNT)
+ if (gpio >= gpio_count)
return;
- reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4);
+ reg = reg_base + 4 * (gpio / 4);
s = 8 * (gpio % 4);
spin_lock_irqsave(&ath79_gpio_lock, flags);
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -786,6 +786,14 @@
#define AR934X_GPIO_REG_OUT_FUNC5 0x40
#define AR934X_GPIO_REG_FUNC 0x6c
+#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c
+#define QCA955X_GPIO_REG_OUT_FUNC1 0x30
+#define QCA955X_GPIO_REG_OUT_FUNC2 0x34
+#define QCA955X_GPIO_REG_OUT_FUNC3 0x38
+#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c
+#define QCA955X_GPIO_REG_OUT_FUNC5 0x40
+#define QCA955X_GPIO_REG_FUNC 0x6c
+
#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c
#define QCA956X_GPIO_REG_OUT_FUNC1 0x30
#define QCA956X_GPIO_REG_OUT_FUNC2 0x34
@@ -907,6 +915,8 @@
#define AR934X_GPIO_OUT_EXT_LNA0 46
#define AR934X_GPIO_OUT_EXT_LNA1 47
+#define QCA955X_GPIO_OUT_GPIO 0
+
/*
* MII_CTRL block
*/
|
