/* * $Id: quirks.c,v 1.5 1998/05/02 19:24:14 mj Exp $ * * This file contains work-arounds for many known PCI hardware * bugs. Devices present only on certain architectures (host * bridges et cetera) should be handled in arch-specific code. * * Copyright (c) 1999 Martin Mares * * The bridge optimization stuff has been removed. If you really * have a silly BIOS which is unable to set your host bridge right, * use the PowerTweak utility (see http://powertweak.sourceforge.net). */ #include #include #include #include #include #include #include #undef DEBUG /* Deal with broken BIOS'es that neglect to enable passive release, which can cause problems in combination with the 82441FX/PPro MTRRs */ static void __init quirk_passive_release(struct pci_dev *dev) { struct pci_dev *d = NULL; unsigned char dlc; /* We have to make sure a particular bit is set in the PIIX3 ISA bridge, so we have to go out and find it. */ while ((d = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { pci_read_config_byte(d, 0x82, &dlc); if (!(dlc & 1<<1)) { printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", d->slot_name); dlc |= 1<<1; pci_write_config_byte(d, 0x82, dlc); } } } /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround but VIA don't answer queries. If you happen to have good contacts at VIA ask them for me please -- Alan This appears to be BIOS not version dependent. So presumably there is a chipset level fix */ int isa_dma_bridge_buggy; /* Exported */ static void __init quirk_isa_dma_hangs(struct pci_dev *dev) { if (!isa_dma_bridge_buggy) { isa_dma_bridge_buggy=1; printk(KERN_INFO "Activating ISA DMA hang workarounds.\n"); } } int pci_pci_problems; /* * Chipsets where PCI->PCI transfers vanish or hang */ static void __init quirk_nopcipci(struct pci_dev *dev) { if((pci_pci_problems&PCIPCI_FAIL)==0) { printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n"); pci_pci_problems|=PCIPCI_FAIL; } } /* * Triton requires workarounds to be used by the drivers */ static void __init quirk_triton(struct pci_dev *dev) { if((pci_pci_problems&PCIPCI_TRITON)==0) { printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); pci_pci_problems|=PCIPCI_TRITON; } } /* * VIA Apollo KT133 needs PCI latency patch * Made according to a windows driver based patch by George E. Breese * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on which * Mr Breese based his work. * * Updated based on further information from the site and also on * information provided by VIA */ static void __init quirk_vialatency(struct pci_dev *dev) { struct pci_dev *p; u8 rev; u8 busarb; /* Ok we have a potential problem chipset here. Now see if we have a buggy southbridge */ p=pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); if(p!=NULL) { pci_read_config_byte(p, PCI_CLASS_REVISION, &rev); /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ /* Check for buggy part revisions */ if (rev < 0x40 || rev > 0x42) return; } else { p = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); if(p==NULL) /* No problem parts */ return; pci_read_config_byte(p, PCI_CLASS_REVISION, &rev); /* Check for buggy part revisions */ if (rev < 0x10 || rev > 0x12) return; } /* * Ok we have the problem. Now set the PCI master grant to * occur every master grant. The apparent bug is that under high * PCI load (quite common in Linux of course) you can get data * loss when the CPU is held off the bus for 3 bus master requests * This happens to include the IDE controllers.... * * VIA only apply this fix when an SB Live! is present but under * both Linux and Windows this isnt enough, and we have seen * corruption without SB Live! but with things like 3 UDMA IDE * controllers. So we ignore that bit of the VIA recommendation.. */ pci_read_config_byte(dev, 0x76, &busarb); /* Set bit 4 and bi 5 of byte 76 to 0x01 "Master priority rotation on every PCI master grant */ busarb &= ~(1<<5); busarb |= (1<<4); pci_write_config_byte(dev, 0x76, busarb); printk(KERN_INFO "Applying VIA southbridge workaround.\n"); } /* * VIA Apollo VP3 needs ETBF on BT848/878 */ static void __init quirk_viaetbf(struct pci_dev *dev) { if((pci_pci_problems&PCIPCI_VIAETBF)==0) { printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); pci_pci_problems|=PCIPCI_VIAETBF; } } static void __init quirk_vsfx(struct pci_dev *dev) { if((pci_pci_problems&PCIPCI_VSFX)==0) { printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); pci_pci_problems|=PCIPCI_VSFX; } } /* * Ali Magik requires workarounds to be used by the drivers * that DMA to AGP space. Latency must be set to 0xA and triton * workaround applied too * [Info kindly provided by ALi] */ static void __init quirk_alimagik(struct pci_dev *dev) { if((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); pci_pci_problems|=PCIPCI_ALIMAGIK|PCIPCI_TRITON; } } /* * Natoma has some interesting boundary conditions with Zoran stuff * at least */ static void __init quirk_natoma(struct pci_dev *dev) { if((pci_pci_problems&PCIPCI_NATOMA)==0) { printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); pci_pci_problems|=PCIPCI_NATOMA; } } /* * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. * If it's needed, re-allocate the region. */ static void __init quirk_s3_64M(struct pci_dev *dev) { struct resource *r = &dev->resource[0]; if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { r->start = 0; r->end = 0x3ffffff; } } static void __init quirk_io_region(struct pci_dev *dev, unsigned region, unsigned size, int nr) { region &= ~(size-1); if (region) { struct resource *res = dev->resource + nr; res->name = dev->name; res->start = region; res->end = region + size - 1; res->flags = IORESOURCE_IO; pci_claim_resource(dev, nr); } } /* * ATI Northbridge setups MCE the processor if you even * read somewhere between 0x3b0->0x3bb or read 0x3d3 */ static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev) { printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n"); request_region(0x3b0, 0x0C, "RadeonIGP"); request_region(0x3d3, 0x01, "RadeonIGP"); } /* * Let's make the southbridge information explicit instead * of having to worry about people probing the ACPI areas, * for example.. (Yes, it happens, and if you read the wrong * ACPI register it will put the machine to sleep with no * way of waking it up again. Bummer). * * ALI M7101: Two IO regions pointed to by words at * 0xE0 (64 bytes of ACPI registers) * 0xE2 (32 bytes of SMB registers) */ static void __init quirk_ali7101_acpi(struct pci_dev *dev) { u16 region; pci_read_config_word(dev, 0xE0, ®ion); quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES); pci_read_config_word(dev, 0xE2, ®ion); quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1); } /* * PIIX4 ACPI: Two IO regions pointed to by longwords at * 0x40 (64 bytes of ACPI registers) * 0x90 (32 bytes of SMB registers) */ static void __init quirk_piix4_acpi(struct pci_dev *dev) { u32 region; pci_read_config_dword(dev, 0x40, ®ion); quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES); pci_read_config_dword(dev, 0x90, ®ion); quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1); } /* * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at * 0x40 (128 bytes of ACPI, GPIO & TCO registers) * 0x58 (64 bytes of GPIO I/O space) */ static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev) { u32 region; pci_read_config_dword(dev, 0x40, ®ion); quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES); pci_read_config_dword(dev, 0x58, ®ion); quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1); } /* * VIA ACPI: One IO region pointed to by longword at * 0x48 or 0x20 (256 bytes of ACPI registers) */ static void __init quirk_vt82c586_acpi(struct pci_dev *dev) { u8 rev; u32 region; pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev); if (rev & 0x10) { pci_read_config_dword(dev, 0x48, ®ion); region &= PCI_BASE_ADDRESS_IO_MASK; quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES); } } /* * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at * 0x48 (256 bytes of ACPI registers) * 0x70 (128 bytes of hardware monitoring register) * 0x90 (16 bytes of SMB registers) */ static void __init quirk_vt82c686_acpi(struct pci_dev *dev) { u16 hm; u32 smb; quirk_vt82c586_acpi(dev); pci_read_config_word(dev, 0x70, &hm); hm &= PCI_BASE_ADDRESS_IO_MASK; quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1); pci_read_config_dword(dev, 0x90, &smb); smb &= PCI_BASE_ADDRESS_IO_MASK; quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2); } #ifdef CONFIG_X86_IO_APIC /* * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip * devices to the external APIC. * * TODO: When we have device-specific interrupt routers, * this code will go away from quirks. */ static void __init quirk_via_ioapic(struct pci_dev *dev) { u8 tmp; if (nr_ioapics < 1) tmp = 0; /* nothing routed to external APIC */ else tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ printk(KERN_INFO "PCI: %sbling Via external APIC routing\n", tmp == 0 ? "Disa" : "Ena"); /* Offset 0x58: External APIC IRQ output control */ pci_write_config_byte (dev, 0x58, tmp); } #endif /* CONFIG_X86_IO_APIC */ /* * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature: * when written, it makes an internal connection to the PIC. * For these devices, this register is defined to be 4 bits wide. * Normally this is fine. However for IO-APIC motherboards, or * non-x86 architectures (yes Via exists on PPC among other places), * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get * interrupts delivered properly. * * TODO: When we have device-specific interrupt routers, * quirk_via_irqpic will go away from quirks. */ /* * FIXME: it is questionable that quirk_via_acpi * is needed. It shows up as an ISA bridge, and does not * support the PCI_INTERRUPT_LINE register at all. Therefore * it seems like setting the pci_dev's 'irq' to the * value of the ACPI SCI interrupt is only done for convenience. * -jgarzik */ static void __init quirk_via_acpi(struct pci_dev *d) { /* * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ u8 irq; pci_read_config_byte(d, 0x42, &irq); irq &= 0xf; if (irq && (irq != 2)) d->irq = irq; } static void __init quirk_via_irqpic(struct pci_dev *dev) { u8 irq, new_irq = dev->irq & 0xf; pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); if (new_irq != irq) { printk(KERN_INFO "PCI: Via IRQ fixup for %s, from %d to %d\n", dev->slot_name, irq, new_irq); udelay(15); pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); } } /* * PIIX3 USB: We have to disable USB interrupts that are * hardwired to PIRQD# and may be shared with an * external device. * * Legacy Support Register (LEGSUP): * bit13: USB PIRQ Enable (USBPIRQDEN), * bit4: Trap/SMI On IRQ Enable (USBSMIEN). * * We mask out all r/wc bits, too. */ static void __init quirk_piix3_usb(struct pci_dev *dev) { u16 legsup; pci_read_config_word(dev, 0xc0, &legsup); legsup &= 0x50ef; pci_write_config_word(dev, 0xc0, legsup); } /* * VIA VT82C598 has its device ID settable and many BIOSes * set it to the ID of VT82C597 for backward compatibility. * We need to switch it off to be able to recognize the real * type of the chip. */ static void __init quirk_vt82c598_id(struct pci_dev *dev) { pci_write_config_byte(dev, 0xfc, 0); pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); } /* * CardBus controllers have a legacy base address that enables them * to respond as i82365 pcmcia controllers. We don't want them to * do this even if the Linux CardBus driver is not loaded, because * the Linux i82365 driver does not (and should not) handle CardBus. */ static void __init quirk_cardbus_legacy(struct pci_dev *dev) { if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class) return; pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); } /* * The AMD io apic can hang the box when an apic irq is masked. * We check all revs >= B0 (yet not in the pre production!) as the bug * is currently marked NoFix * * We have multiple reports of hangs with this chipset that went away with * noapic specified. For the moment we assume its the errata. We may be wrong * of course. However the advice is demonstrably good even if so.. */ static void __init quirk_amd_ioapic(struct pci_dev *dev) { u8 rev; pci_read_config_byte(dev, PCI_REVISION_ID, &rev); if(rev >= 0x02) { printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n"); printk(KERN_WARNING " : booting with the \"noapic\" option.\n"); } } /* * Following the PCI ordering rules is optional on the AMD762. I'm not * sure what the designers were smoking but let's not inhale... * * To be fair to AMD, it follows the spec by default, its BIOS people * who turn it off! */ static void __init quirk_amd_ordering(struct pci_dev *dev) { u32 pcic; pci_read_config_dword(dev, 0x4C, &pcic); if((pcic&6)!=6) { pcic |= 6; printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n"); pci_write_config_dword(dev, 0x4C, pcic); pci_read_config_dword(dev, 0x84, &pcic); pcic |= (1<<23); /* Required in this mode */ pci_write_config_dword(dev, 0x84, pcic); } } #ifdef CONFIG_X86_IO_APIC #define AMD8131_revA0 0x01 #define AMD8131_revB0 0x11 #define AMD8131_MISC 0x40 #define AMD8131_NIOAMODE_BIT 0 static void __init quirk_amd_8131_ioapic(struct pci_dev *dev) { unsigned char revid, tmp; if (nr_ioapics == 0) return; pci_read_config_byte(dev, PCI_REVISION_ID, &revid); if (revid == AMD8131_revA0 || revid == AMD8131_revB0) { printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n"); pci_read_config_byte( dev, AMD8131_MISC, &tmp); tmp &= ~(1 << AMD8131_NIOAMODE_BIT); pci_write_config_byte( dev, AMD8131_MISC, tmp); } } #endif /* * DreamWorks provided workaround for Dunord I-3000 problem * * This card decodes and responds to addresses not apparently * assigned to it. We force a larger allocation to ensure that * nothing gets put too close to it. */ static void __init quirk_dunord ( struct pci_dev * dev ) { struct resource * r = & dev -> resource [ 1 ]; r -> start = 0; r -> end = 0xffffff; } static void __init quirk_transparent_bridge(struct pci_dev *dev) { dev->transparent = 1; } /* * Common misconfiguration of the MediaGX/Geode PCI master that will * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 * datasheets found at http://www.national.com/ds/GX for info on what * these bits do. */ static void __init quirk_mediagx_master(struct pci_dev *dev) { u8 reg; pci_read_config_byte(dev, 0x41, ®); if (reg & 2) { reg &= ~2; printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); pci_write_config_byte(dev, 0x41, reg); } } /* * As per PCI spec, ignore base address registers 0-3 of the IDE controllers * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and * secondary channels respectively). If the device reports Compatible mode * but does use BAR0-3 for address decoding, we assume that firmware has * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374). * Exceptions 
--- a/src/lvm.c
+++ b/src/lvm.c
@@ -31,6 +31,9 @@
 /* limit for table tag-method chains (to avoid loops) */
 #define MAXTAGLOOP	100
 
+#ifdef __GNUC__
+#define COMPUTED_GOTO 1
+#endif
 
 /*
  * If 'obj' is a string, it is tried to be interpreted as a number.
@@ -562,12 +565,63 @@ static inline int arith_mode( const TVal
     ARITH_OP1_END
 #endif
 
+#ifdef COMPUTED_GOTO
+#define OPCODE_TARGET(op) DO_OP_##op:
+#define CALL_OPCODE(op) goto *opcodes[op];
+#define OPCODE_PTR(op) [OP_##op] = &&DO_OP_##op
+#else
+#define OPCODE_TARGET(op) case OP_##op:
+#define CALL_OPCODE(op) switch (op)
+#endif
+
 
 void luaV_execute (lua_State *L, int nexeccalls) {
   LClosure *cl;
   StkId base;
   TValue *k;
   const Instruction *pc;
+#ifdef COMPUTED_GOTO
+  static const void *opcodes[] = {
+   OPCODE_PTR(MOVE),
+   OPCODE_PTR(LOADK),
+   OPCODE_PTR(LOADBOOL),
+   OPCODE_PTR(LOADNIL),
+   OPCODE_PTR(GETUPVAL),
+   OPCODE_PTR(GETGLOBAL),
+   OPCODE_PTR(GETTABLE),
+   OPCODE_PTR(SETGLOBAL),
+   OPCODE_PTR(SETUPVAL),
+   OPCODE_PTR(SETTABLE),
+   OPCODE_PTR(NEWTABLE),
+   OPCODE_PTR(SELF),
+   OPCODE_PTR(ADD),
+   OPCODE_PTR(SUB),
+   OPCODE_PTR(MUL),
+   OPCODE_PTR(DIV),
+   OPCODE_PTR(MOD),
+   OPCODE_PTR(POW),
+   OPCODE_PTR(UNM),
+   OPCODE_PTR(NOT),
+   OPCODE_PTR(LEN),
+   OPCODE_PTR(CONCAT),
+   OPCODE_PTR(JMP),
+   OPCODE_PTR(EQ),
+   OPCODE_PTR(LT),
+   OPCODE_PTR(LE),
+   OPCODE_PTR(TEST),
+   OPCODE_PTR(TESTSET),
+   OPCODE_PTR(CALL),
+   OPCODE_PTR(TAILCALL),
+   OPCODE_PTR(RETURN),
+   OPCODE_PTR(FORLOOP),
+   OPCODE_PTR(FORPREP),
+   OPCODE_PTR(TFORLOOP),
+   OPCODE_PTR(SETLIST),
+   OPCODE_PTR(CLOSE),
+   OPCODE_PTR(CLOSURE),
+   OPCODE_PTR(VARARG)
+  };
+#endif
  reentry:  /* entry point */
   lua_assert(isLua(L->ci));
   pc = L->savedpc;
@@ -592,33 +646,33 @@ void luaV_execute (lua_State *L, int nex
     lua_assert(base == L->base && L->base == L->ci->base);
     lua_assert(base <= L->top && L->top <= L->stack + L->stacksize);
     lua_assert(L->top == L->ci->top || luaG_checkopenop(i));
-    switch (GET_OPCODE(i)) {
-      case OP_MOVE: {
+    CALL_OPCODE(GET_OPCODE(i)) {
+      OPCODE_TARGET(MOVE) {
         setobjs2s(L, ra, RB(i));
         continue;
       }
-      case OP_LOADK: {
+      OPCODE_TARGET(LOADK) {
         setobj2s(L, ra, KBx(i));
         continue;
       }
-      case OP_LOADBOOL: {
+      OPCODE_TARGET(LOADBOOL) {
         setbvalue(ra, GETARG_B(i));
         if (GETARG_C(i)) pc++;  /* skip next instruction (if C) */
         continue;
       }
-      case OP_LOADNIL: {
+      OPCODE_TARGET(LOADNIL) {
         TValue *rb = RB(i);
         do {
           setnilvalue(rb--);
         } while (rb >= ra);
         continue;
       }
-      case OP_GETUPVAL: {
+      OPCODE_TARGET(GETUPVAL) {
         int b = GETARG_B(i);
         setobj2s(L, ra, cl->upvals[b]->v);
         continue;
       }
-      case OP_GETGLOBAL: {
+      OPCODE_TARGET(GETGLOBAL) {
         TValue g;
         TValue *rb = KBx(i);
         sethvalue(L, &g, cl->env);
@@ -626,88 +680,88 @@ void luaV_execute (lua_State *L, int nex
         Protect(luaV_gettable(L, &g, rb, ra));
         continue;
       }
-      case OP_GETTABLE: {
+      OPCODE_TARGET(GETTABLE) {
         Protect(luaV_gettable(L, RB(i), RKC(i), ra));
         continue;
       }
-      case OP_SETGLOBAL: {
+      OPCODE_TARGET(SETGLOBAL) {
         TValue g;
         sethvalue(L, &g, cl->env);
         lua_assert(ttisstring(KBx(i)));
         Protect(luaV_settable(L, &g, KBx(i), ra));
         continue;
       }
-      case OP_SETUPVAL: {
+      OPCODE_TARGET(SETUPVAL) {
         UpVal *uv = cl->upvals[GETARG_B(i)];
         setobj(L, uv->v, ra);
         luaC_barrier(L, uv, ra);
         continue;
       }
-      case OP_SETTABLE: {
+      OPCODE_TARGET(SETTABLE) {
         Protect(luaV_settable(L, ra, RKB(i), RKC(i)));
         continue;
       }
-      case OP_NEWTABLE: {
+      OPCODE_TARGET(NEWTABLE) {
         int b = GETARG_B(i);
         int c = GETARG_C(i);
         sethvalue(L, ra, luaH_new(L, luaO_fb2int(b), luaO_fb2int(c)));
         Protect(luaC_checkGC(L));
         continue;
       }
-      case OP_SELF: {
+      OPCODE_TARGET(SELF) {
         StkId rb = RB(i);
         setobjs2s(L, ra+1, rb);
         Protect(luaV_gettable(L, rb, RKC(i), ra));
         continue;
       }
-      case OP_ADD: {
+      OPCODE_TARGET(ADD) {
         TValue *rb = RKB(i), *rc= RKC(i);
         arith_op_continue( luai_numadd, try_addint, luai_vectadd );
         Protect(Arith(L, ra, rb, rc, TM_ADD)); \
         continue;
       }
-      case OP_SUB: {
+      OPCODE_TARGET(SUB) {
         TValue *rb = RKB(i), *rc= RKC(i);
         arith_op_continue( luai_numsub, try_subint, luai_vectsub );
         Protect(Arith(L, ra, rb, rc, TM_SUB));
         continue;
       }
-      case OP_MUL: {
+      OPCODE_TARGET(MUL) {
         TValue *rb = RKB(i), *rc= RKC(i);
         arith_op_continue(luai_nummul, try_mulint, luai_vectmul);
         Protect(Arith(L, ra, rb, rc, TM_MUL));
         continue;
       }
-      case OP_DIV: {
+      OPCODE_TARGET(DIV) {
         TValue *rb = RKB(i), *rc= RKC(i);
         arith_op_continue(luai_numdiv, try_divint, luai_vectdiv);
         Protect(Arith(L, ra, rb, rc, TM_DIV));
         continue;
       }
-      case OP_MOD: {
+      OPCODE_TARGET(MOD) {
         TValue *rb = RKB(i), *rc= RKC(i);
         arith_op_continue_scalar(luai_nummod, try_modint);  /* scalars only */
         Protect(Arith(L, ra, rb, rc, TM_MOD));
         continue;
       }
-      case OP_POW: {
+      OPCODE_TARGET(POW) {
         TValue *rb = RKB(i), *rc= RKC(i);
         arith_op_continue(luai_numpow, try_powint, luai_vectpow);
         Protect(Arith(L, ra, rb, rc, TM_POW));
         continue;
       }
-      case OP_UNM: {
+      OPCODE_TARGET(UNM) {
         TValue *rb = RB(i);
         arith_op1_continue(luai_numunm, try_unmint, luai_vectunm);
         Protect(Arith(L, ra, rb, rb, TM_UNM));
         continue;
       }
-      case OP_NOT: {
+      OPCODE_TARGET(NOT) {
         int res = l_isfalse(RB(i));  /* next assignment may change this value */
         setbvalue(ra, res);
         continue;
       }
-      case OP_LEN: {
+      OPCODE_TARGET(LEN) {
         const TValue *rb = RB(i);
         switch (ttype(rb)) {
           case LUA_TTABLE: {
@@ -727,18 +781,18 @@ void luaV_execute (lua_State *L, int nex
         }
         continue;
       }
-      case OP_CONCAT: {
+      OPCODE_TARGET(CONCAT) {
         int b = GETARG_B(i);
         int c = GETARG_C(i);
         Protect(luaV_concat(L, c-b+1, c); luaC_checkGC(L));
         setobjs2s(L, RA(i), base+b);
         continue;
       }
-      case OP_JMP: {
+      OPCODE_TARGET(JMP) {
         dojump(L, pc, GETARG_sBx(i));
         continue;
       }
-      case OP_EQ: {
+      OPCODE_TARGET(EQ) {
         TValue *rb = RKB(i);
         TValue *rc = RKC(i);
         Protect(
@@ -748,7 +802,7 @@ void luaV_execute (lua_State *L, int nex
         pc++;
         continue;
       }
-      case OP_LT: {
+      OPCODE_TARGET(LT) {
         Protect(
           if (luaV_lessthan(L, RKB(i), RKC(i)) == GETARG_A(i))
             dojump(L, pc, GETARG_sBx(*pc));
@@ -756,7 +810,7 @@ void luaV_execute (lua_State *L, int nex
         pc++;
         continue;
       }
-      case OP_LE: {
+      OPCODE_TARGET(LE) {
         Protect(
           if (lessequal(L, RKB(i), RKC(i)) == GETARG_A(i))
             dojump(L, pc, GETARG_sBx(*pc));
@@ -764,13 +818,13 @@ void luaV_execute (lua_State *L, int nex
         pc++;
         continue;
       }
-      case OP_TEST: {
+      OPCODE_TARGET(TEST) {
         if (l_isfalse(ra) != GETARG_C(i))
           dojump(L, pc, GETARG_sBx(*pc));
         pc++;
         continue;
       }
-      case OP_TESTSET: {
+      OPCODE_TARGET(TESTSET) {
         TValue *rb = RB(i);
         if (l_isfalse(rb) != GETARG_C(i)) {
           setobjs2s(L, ra, rb);
@@ -779,7 +833,7 @@ void luaV_execute (lua_State *L, int nex
         pc++;
         continue;
       }
-      case OP_CALL: {
+      OPCODE_TARGET(CALL) {
         int b = GETARG_B(i);
         int nresults = GETARG_C(i) - 1;
         if (b != 0) L->top = ra+b;  /* else previous instruction set top */
@@ -800,7 +854,7 @@ void luaV_execute (lua_State *L, int nex
           }
         }
       }
-      case OP_TAILCALL: {
+      OPCODE_TARGET(TAILCALL) {
         int b = GETARG_B(i);
         if (b != 0) L->top = ra+b;  /* else previous instruction set top */
         L->savedpc = pc;
@@ -832,7 +886,7 @@ void luaV_execute (lua_State *L, int nex
           }
         }
       }
-      case OP_RETURN: {
+      OPCODE_TARGET(RETURN) {
         int b = GETARG_B(i);
         if (b != 0) L->top = ra+b-1;
         if (L->openupval) luaF_close(L, base);
@@ -847,7 +901,7 @@ void luaV_execute (lua_State *L, int nex
           goto reentry;
         }
       }
-      case OP_FORLOOP: {
+      OPCODE_TARGET(FORLOOP) {
         /* If start,step and limit are all integers, we don't need to check
          * against overflow in the looping.
          */
@@ -875,7 +929,7 @@ void luaV_execute (lua_State *L, int nex
         }
         continue;
       }
-      case OP_FORPREP: {
+      OPCODE_TARGET(FORPREP) {
         const TValue *init = ra;
         const TValue *plimit = ra+1;
         const TValue *pstep = ra+2;
@@ -898,7 +952,7 @@ void luaV_execute (lua_State *L, int nex
         dojump(L, pc, GETARG_sBx(i));
         continue;
       }
-      case OP_TFORLOOP: {
+      OPCODE_TARGET(TFORLOOP) {
         StkId cb = ra + 3;  /* call base */
         setobjs2s(L, cb+2, ra+2);
         setobjs2s(L, cb+1, ra+1);
@@ -914,7 +968,7 @@ void luaV_execute (lua_State *L, int nex
         pc++;
         continue;
       }
-      case OP_SETLIST: {
+      OPCODE_TARGET(SETLIST) {
         int n = GETARG_B(i);
         int c = GETARG_C(i);
         int last;
@@ -936,11 +990,11 @@ void luaV_execute (lua_State *L, int nex
         }
         continue;
       }
-      case OP_CLOSE: {
+      OPCODE_TARGET(CLOSE) {
         luaF_close(L, ra);
         continue;
       }
-      case OP_CLOSURE: {
+      OPCODE_TARGET(CLOSURE) {
         Proto *p;
         Closure *ncl;
         int nup, j;
@@ -960,7 +1014,7 @@ void luaV_execute (lua_State *L, int nex
         Protect(luaC_checkGC(L));
         continue;
       }
-      case OP_VARARG: {
+      OPCODE_TARGET(VARARG) {
         int b = GETARG_B(i) - 1;
         int j;
         CallInfo *ci = L->ci;
generated by cgit v1.2.3 (git 2.25.1) at 2026-02-20 23:30:07 +0000