module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); parameter CLKPOL2 = 1; parameter CLKPOL3 = 1; parameter [36863:0] INIT = 36864'bx; input CLK2; input CLK3; input [8:0] A1ADDR; output [71:0] A1DATA; input A1EN; input [8:0] B1ADDR; input [71:0] B1DATA; input [7:0] B1EN; wire [15:0] A1ADDR_16 = {A1ADDR, 6'b0}; wire [15:0] B1ADDR_16 = {B1ADDR, 6'b0}; wire [7:0] DIP, DOP; wire [63:0] DI, DO; assign A1DATA = { DOP[7], DO[63:56], DOP[6], DO[55:48], DOP[5], DO[47:40], DOP[4], DO[39:32], DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] }; assign { DIP[7], DI[63:56], DIP[6], DI[55:48], DIP[5], DI[47:40], DIP[4], DI[39:32], DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA; RAMB36E1 #( .RAM_MODE("SDP"), .READ_WIDTH_A(72), .WRITE_WIDTH_B(72), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST"), .IS_CLKARDCLK_INVERTED(!CLKPOL2), .IS_CLKBWRCLK_INVERTED(!CLKPOL3), `include "brams_init_36.vh" .SIM_DEVICE("7SERIES") ) _TECHMAP_REPLACE_ ( .DOBDO(DO[63:32]), .DOADO(DO[31:0]), .DOPBDOP(DOP[7:4]), .DOPADOP(DOP[3:0]), .DIBDI(DI[63:32]), .DIADI(DI[31:0]), .DIPBDIP(DIP[7:4]), .DIPADIP(DIP[3:0]), .ADDRARDADDR(A1ADDR_16), .CLKARDCLK(CLK2), .ENARDEN(A1EN), .REGCEAREGCE(|1), .RSTRAMARSTRAM(|0), .RSTREGARSTREG(|0), .WEA(4'b0), .ADDRBWRADDR(B1ADDR_16), .CLKBWRCLK(CLK3), .ENBWREN(|1), .REGCEB(|0), .RSTRAMB(|0), .RSTREGB(|0), .WEBWE(B1EN) ); endmodule // ------------------------------------------------------------------------ module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); parameter CLKPOL2 = 1; parameter CLKPOL3 = 1; parameter [18431:0] INIT = 18432'bx; input CLK2; input CLK3; input [8:0] A1ADDR; output [35:0] A1DATA; input A1EN; input [8:0] B1ADDR; input [35:0] B1DATA; input [3:0] B1EN; wire [13:0] A1ADDR_14 = {A1ADDR, 5'b0}; wire [13:0] B1ADDR_14 = {B1ADDR, 5'b0}; wire [3:0] DIP, DOP; wire [31:0] DI, DO; assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] }; assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA; RAMB18E1 #( .RAM_MODE("SDP"), .READ_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST"), .IS_CLKARDCLK_INVERTED(!CLKPOL2), .IS_CLKBWRCLK_INVERTED(!CLKPOL3), `include "brams_init_18.vh" .SIM_DEVICE("7SERIES") ) _TECHMAP_REPLACE_ ( .DOBDO(DO[31:16]), .DOADO(DO[15:0]), .DOPBDOP(DOP[3:2]), .DOPADOP(DOP[1:0]), .DIBDI(DI[31:16]), .DIADI(DI[15:0]), .DIPBDIP(DIP[3:2]), .DIPADIP(DIP[1:0]), .ADDRARDADDR(A1ADDR_14), .CLKARDCLK(CLK2), .ENARDEN(A1EN), .REGCEAREGCE(|1), .RSTRAMARSTRAM(|0), .RSTREGARSTREG(|0), .WEA(2'b0), .ADDRBWRADDR(B1ADDR_14), .CLKBWRCLK(CLK3), .ENBWREN(|1), .REGCEB(|0), .RSTRAMB(|0), .RSTREGB(|0), .WEBWE(B1EN) ); endmodule // ------------------------------------------------------------------------ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); parameter CFG_ABITS = 10; parameter CFG_DBITS = 36; parameter CFG_ENABLE_B = 4; parameter CLKPOL2 = 1; parameter CLKPOL3 = 1; parameter [36863:0] INIT = 36864'bx; input CLK2; input CLK3; input [CFG_ABITS-1:0] A1ADDR; output [CFG_DBITS-1:0] A1DATA; input A1EN; input [CFG_ABITS-1:0] B1ADDR; input [CFG_DBITS-1:0] B1DATA; input [CFG_ENABLE_B-1:0] B1EN; wire [15:0] A1ADDR_16 = A1ADDR << (15 - CFG_ABITS); wire [15:0] B1ADDR_16 = B1ADDR << (15 - CFG_ABITS); wire [7:0] B1EN_8 = B1EN; wire [3:0] DIP, DOP; wire [31:0] DI, DO; wire [31:0] DOBDO; wire [3:0] DOPBDOP; assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] }; assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA; generate if (CFG_DBITS > 8) begin RAMB36E1 #( .RAM_MODE("TDP"), .READ_WIDTH_A(CFG_DBITS), .READ_WIDTH_B(CFG_DBITS), .WRITE_WIDTH_A(CFG_DBITS), .WRITE_WIDTH_B(CFG_DBITS), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST"), .IS_CLKARDCLK_INVERTED(!CLKPOL2), .IS_CLKBWRCLK_INVERTED(!CLKPOL3), `include "brams_init_36.vh" .SIM_DEVICE("7SERIES") ) _TECHMAP_REPLACE_ ( .DIADI(32'd0), .DIPADIP(4'd0), .DOADO(DO[31:0]), .DOPADOP(DOP[3:0]), .ADDRARDADDR(A1ADDR_16), .CLKARDCLK(CLK2), .ENARDEN(A1EN), .REGCEAREGCE(|1), .RSTRAMARSTRAM(|0), .RSTREGARSTREG(|0), .WEA(4'b0), .DIBDI(DI), .DIPBDIP(DIP), .DOBDO(DOBDO), .DOPBDOP(DOPBDOP), .ADDRBWRADDR(B1ADDR_16), .CLKBWRCLK(CLK3), .ENBWREN(|1), .REGCEB(|0), .RSTRAMB(|0), .RSTREGB(|0), .WEBWE(B1EN_8) ); end else begin RAMB36E1 #( .RAM_MODE("TDP"), .READ_WIDTH_A(CFG_DBITS), .READ_WIDTH_B(CFG_DBITS), .WRITE_WIDTH_A(CFG_DBITS), .WRITE_WIDTH_B(CFG_DBITS), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST"), .IS_CLKARDCLK_INVERTED(!CLKPOL2), .IS_CLKBWRCLK_INVERTED(!CLKPOL3), `include "brams_init_32.vh" .SIM_DEVICE("7SERIES") ) _TECHMAP_REPLACE_ ( .DIADI(32'd0), .DIPADIP(4'd0), .DOADO(DO[31:0]), .DOPADOP(DOP[3:0]), .ADDRARDADDR(A1ADDR_16), .CLKARDCLK(CLK2), .ENARDEN(A1EN), .REGCEAREGCE(|1), .RSTRAMARSTRAM(|0), .RSTREGARSTREG(|0), .WEA(4'b0), .DIBDI(DI), .DIPBDIP(DIP), .DOBDO(DOBDO), .DOPBDOP(DOPBDOP), .ADDRBWRADDR(B1ADDR_16), .CLKBWRCLK(CLK3), .ENBWREN(|1), .REGCEB(|0), .RSTRAMB(|0), .RSTREGB(|0), .WEBWE(B1EN_8) ); end endgenerate endmodule // ------------------------------------------------------------------------ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); parameter CFG_ABITS = 10; parameter CFG_DBITS = 18; parameter CFG_ENABLE_B = 2; parameter CLKPOL2 = 1; parameter CLKPOL3 = 1; parameter [18431:0] INIT = 18432'bx; input CLK2; input CLK3; input [CFG_ABITS-1:0] A1ADDR; output [CFG_DBITS-1:0] A1DATA; input A1EN; input [CFG_ABITS-1:0] B1ADDR; input [CFG_DBITS-1:0] B1DATA; input [CFG_ENABLE_B-1:0] B1EN; wire [13:0] A1ADDR_14 = A1ADDR << (14 - CFG_ABITS); wire [13:0] B1ADDR_14 = B1ADDR << (14 - CFG_ABITS); wire [3:0] B1EN_4 = B1EN; wire [1:0] DIP, DOP; wire [15:0] DI, DO; wire [15:0] DOBDO; wire [1:0] DOPBDOP; assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] }; assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA; generate if (CFG_DBITS > 8) begin RAMB18E1 #( .RAM_MODE("TDP"), .READ_WIDTH_A(CFG_DBITS), .READ_WIDTH_B(CFG_DBITS), .WRITE_WIDTH_A(CFG_DBITS), .WRITE_WIDTH_B(CFG_DBITS), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST"), .IS_CLKARDCLK_INVERTED(!CLKPOL2), .IS_CLKBWRCLK_INVERTED(!CLKPOL3), `include "brams_init_18.vh" .SIM_DEVICE("7SERIES") ) _TECHMAP_REPLACE_ ( .DIADI(16'b0), .DIPADIP(2'b0), .DOADO(DO), .DOPADOP(DOP), .ADDRARDADDR(A1ADDR_14), .CLKARDCLK(CLK2), .ENARDEN(A1EN), .REGCEAREGCE(|1), .RSTRAMARSTRAM(|0), .RSTREGARSTREG(|0), .WEA(2'b0), .DIBDI(DI), .DIPBDIP(DIP), .DOBDO(DOBDO), .DOPBDOP(DOPBDOP), .ADDRBWRADDR(B1ADDR_14), .CLKBWRCLK(CLK3), .ENBWREN(|1), .REGCEB(|0), .RSTRAMB(|0), .RSTREGB(|0), .WEBWE(B1EN_4) ); end else begin RAMB18E1 #( .RAM_MODE("TDP"), .READ_WIDTH_A(CFG_DBITS), .READ_WIDTH_B(CFG_DBITS), .WRITE_WIDTH_A(CFG_DBITS), .WRITE_WIDTH_B(CFG_DBITS), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST"), .IS_CLKARDCLK_INVERTED(!CLKPOL2), .IS_CLKBWRCLK_INVERTED(!CLKPOL3), `include "brams_init_16.vh" .SIM_DEVICE("7SERIES") ) _TECHMAP_REPLACE_ ( .DIADI(16'b0), .DIPADIP(2'b0), .DOADO(DO), .DOPADOP(DOP), .ADDRARDADDR(A1ADDR_14), .CLKARDCLK(CLK2), .ENARDEN(A1EN), .REGCEAREGCE(|1), .RSTRAMARSTRAM(|0), .RSTREGARSTREG(|0), .WEA(2'b0), .DIBDI(DI), .DIPBDIP(DIP), .DOBDO(DOBDO), .DOPBDOP(DOPBDOP), .ADDRBWRADDR(B1ADDR_14), .CLKBWRCLK(CLK3), .ENBWREN(|1), .REGCEB(|0), .RSTRAMB(|0), .RSTREGB(|0), .WEBWE(B1EN_4) ); end endgenerate endmodule id='n133' href='#n133'>133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 
/*
 * lib/cache_mngt.c	Cache Management
 *
 *	This library is free software; you can redistribute it and/or
 *	modify it under the terms of the GNU Lesser General Public
 *	License as published by the Free Software Foundation version 2.1
 *	of the License.
 *
 * Copyright (c) 2003-2008 Thomas Graf <tgraf@suug.ch>
 */

/**
 * @ingroup core
 * @defgroup cache_mngt Caching
 * @{
 */

#include <netlink-local.h>
#include <netlink/netlink.h>
#include <netlink/cache.h>
#include <netlink/utils.h>

static struct nl_cache_ops *cache_ops;

/**
 * @name Cache Operations Sets
 * @{
 */

/**
 * Lookup the set cache operations of a certain cache type
 * @arg name		name of the cache type
 *
 * @return The cache operations or NULL if no operations
 *         have been registered under the specified name.
 */
struct nl_cache_ops *nl_cache_ops_lookup(const char *name)
{
	struct nl_cache_ops *ops;

	for (ops = cache_ops; ops; ops = ops->co_next)
		if (!strcmp(ops->co_name, name))
			return ops;

	return NULL;
}

/**
 * Associate a message type to a set of cache operations
 * @arg protocol		netlink protocol
 * @arg msgtype			netlink message type
 *
 * Associates the specified netlink message type with
 * a registered set of cache operations.
 *
 * @return The cache operations or NULL if no association
 *         could be made.
 */
struct nl_cache_ops *nl_cache_ops_associate(int protocol, int msgtype)
{
	int i;
	struct nl_cache_ops *ops;

	for (ops = cache_ops; ops; ops = ops->co_next) {
		if (ops->co_protocol != protocol)
			continue;

		for (i = 0; ops->co_msgtypes[i].mt_id >= 0; i++)
			if (ops->co_msgtypes[i].mt_id == msgtype)
				return ops;
	}

	return NULL;
}

#ifdef disabled

/**
 * Lookup message type cache association
 * @arg ops			cache operations
 * @arg msgtype			netlink message type
 *
 * Searches for a matching message type association ing the specified
 * cache operations.
 *
 * @return A message type association or NULL.
 */
struct nl_msgtype *nl_msgtype_lookup(struct nl_cache_ops *ops, int msgtype)
{
	int i;

	for (i = 0; ops->co_msgtypes[i].mt_id >= 0; i++)
		if (ops->co_msgtypes[i].mt_id == msgtype)
			return &ops->co_msgtypes[i];

	return NULL;
}

static struct nl_cache_ops *cache_ops_lookup_for_obj(struct nl_object_ops *obj_ops)
{
	struct nl_cache_ops *ops;

	for (ops = cache_ops; ops; ops = ops->co_next)
		if (ops->co_obj_ops == obj_ops)
			return ops;

	return NULL;

}

/**
 * Call a function for each registered cache operation
 * @arg cb		Callback function to be called
 * @arg arg		User specific argument.
 */
void nl_cache_ops_foreach(void (*cb)(struct nl_cache_ops *, void *), void *arg)
{
	struct nl_cache_ops *ops;

	for (ops = cache_ops; ops; ops = ops->co_next)
		cb(ops, arg);
}
#endif

/**
 * Register a set of cache operations
 * @arg ops		cache operations
 *
 * Called by users of caches to announce the avaibility of
 * a certain cache type.
 *
 * @return 0 on success or a negative error code.
 */
int nl_cache_mngt_register(struct nl_cache_ops *ops)
{
	if (!ops->co_name || !ops->co_obj_ops)
		return -NLE_INVAL;

	if (nl_cache_ops_lookup(ops->co_name))
		return -NLE_EXIST;

	ops->co_next = cache_ops;
	cache_ops = ops;

	NL_DBG(1, "Registered cache operations %s\n", ops->co_name);

	return 0;
}

/**
 * Unregister a set of cache operations
 * @arg ops		cache operations
 *
 * Called by users of caches to announce a set of
 * cache operations is no longer available. The
 * specified cache operations must have been registered
 * previously using nl_cache_mngt_register()
 *
 * @return 0 on success or a negative error code
 */
int nl_cache_mngt_unregister(struct nl_cache_ops *ops)
{
	struct nl_cache_ops *t, **tp;

	for (tp = &cache_ops; (t=*tp) != NULL; tp = &t->co_next)
		if (t == ops)
			break;

	if (!t)
		return -NLE_NOCACHE;

	NL_DBG(1, "Unregistered cache operations %s\n", ops->co_name);

	*tp = t->co_next;
	return 0;
}

/** @} */

/**
 * @name Global Cache Provisioning/Requiring
 * @{
 */
#ifdef disabled
/**
 * Provide a cache for global use
 * @arg cache		cache to provide
 *
 * Offers the specified cache to be used by other modules.
 * Only one cache per type may be shared at a time,
 * a previsouly provided caches will be overwritten.
 */
void nl_cache_mngt_provide(struct nl_cache *cache)
{
	struct nl_cache_ops *ops;

	ops = cache_ops_lookup_for_obj(cache->c_ops->co_obj_ops);
	if (!ops)
		BUG();
	else
		ops->co_major_cache = cache;
}

/**
 * Unprovide a cache for global use
 * @arg cache		cache to unprovide
 *
 * Cancels the offer to use a cache globally. The
 * cache will no longer be returned via lookups but
 * may still be in use.
 */
void nl_cache_mngt_unprovide(struct nl_cache *cache)
{
	struct nl_cache_ops *ops;

	ops = cache_ops_lookup_for_obj(cache->c_ops->co_obj_ops);
	if (!ops)
		BUG();
	else if (ops->co_major_cache == cache)
		ops->co_major_cache = NULL;
}

/**
 * Demand the use of a global cache
 * @arg name		name of the required object type
 *
 * Trys to find a cache of the specified type for global
 * use.
 *
 * @return A cache provided by another subsystem of the
 *         specified type marked to be available.
 */
struct nl_cache *nl_cache_mngt_require(const char *name)
{
	struct nl_cache_ops *ops;

	ops = nl_cache_ops_lookup(name);
	if (!ops || !ops->co_major_cache) {
		fprintf(stderr, "Application BUG: Your application must "
			"call nl_cache_mngt_provide() and\nprovide a valid "
			"%s cache to be used for internal lookups.\nSee the "
			" API documentation for more details.\n", name);

		return NULL;
	}
	
	return ops->co_major_cache;
}

#endif
/** @} */

/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-13 21:23:48 +0000