#include #include #include #include #include #include #include #include #include #include #include "cpu.h" #include "amd.h" int start_svm(struct cpuinfo_x86 *c); /* * Pre-canned values for overriding the CPUID features * and extended features masks. * * Currently supported processors: * * "fam_0f_rev_c" * "fam_0f_rev_d" * "fam_0f_rev_e" * "fam_0f_rev_f" * "fam_0f_rev_g" * "fam_10_rev_b" * "fam_10_rev_c" * "fam_11_rev_b" */ static char opt_famrev[14]; string_param("cpuid_mask_cpu", opt_famrev); /* Finer-grained CPUID feature control. */ static unsigned int opt_cpuid_mask_ecx, opt_cpuid_mask_edx; integer_param("cpuid_mask_ecx", opt_cpuid_mask_ecx); integer_param("cpuid_mask_edx", opt_cpuid_mask_edx); static unsigned int opt_cpuid_mask_ext_ecx, opt_cpuid_mask_ext_edx; integer_param("cpuid_mask_ext_ecx", opt_cpuid_mask_ext_ecx); integer_param("cpuid_mask_ext_edx", opt_cpuid_mask_ext_edx); static inline void wrmsr_amd(unsigned int index, unsigned int lo, unsigned int hi) { asm volatile ( "wrmsr" : /* No outputs */ : "c" (index), "a" (lo), "d" (hi), "D" (0x9c5a203a) ); } /* * Mask the features and extended features returned by CPUID. Parameters are * set from the boot line via two methods: * * 1) Specific processor revision string * 2) User-defined masks * * The processor revision string parameter has precedene. */ static void __devinit set_cpuidmask(struct cpuinfo_x86 *c) { static unsigned int feat_ecx, feat_edx; static unsigned int extfeat_ecx, extfeat_edx; static enum { not_parsed, no_mask, set_mask } status; if (status == no_mask) return; if (status == set_mask) goto setmask; ASSERT((status == not_parsed) && (smp_processor_id() == 0)); status = no_mask; if (opt_cpuid_mask_ecx | opt_cpuid_mask_edx | opt_cpuid_mask_ext_ecx | opt_cpuid_mask_ext_edx) { feat_ecx = opt_cpuid_mask_ecx ? : ~0U; feat_edx = opt_cpuid_mask_edx ? : ~0U; extfeat_ecx = opt_cpuid_mask_ext_ecx ? : ~0U; extfeat_edx = opt_cpuid_mask_ext_edx ? : ~0U; } else if (*opt_famrev == '\0') { return; } else if (!strcmp(opt_famrev, "fam_0f_rev_c")) { feat_ecx = AMD_FEATURES_K8_REV_C_ECX; feat_edx = AMD_FEATURES_K8_REV_C_EDX; extfeat_ecx = AMD_EXTFEATURES_K8_REV_C_ECX; extfeat_edx = AMD_EXTFEATURES_K8_REV_C_EDX; } else if (!strcmp(opt_famrev, "fam_0f_rev_d")) { feat_ecx = AMD_FEATURES_K8_REV_D_ECX; feat_edx = AMD_FEATURES_K8_REV_D_EDX; extfeat_ecx = AMD_EXTFEATURES_K8_REV_D_ECX; extfeat_edx = AMD_EXTFEATURES_K8_REV_D_EDX; } else if (!strcmp(opt_famrev, "fam_0f_rev_e")) { feat_ecx = AMD_FEATURES_K8_REV_E_ECX; feat_edx = AMD_FEATURES_K8_REV_E_EDX; extfeat_ecx = AMD_EXTFEATURES_K8_REV_E_ECX; extfeat_edx = AMD_EXTFEATURES_K8_REV_E_EDX; } else if (!strcmp(opt_famrev, "fam_0f_rev_f")) { feat_ecx = AMD_FEATURES_K8_REV_F_ECX; feat_edx = AMD_FEATURES_K8_REV_F_EDX; extfeat_ecx = AMD_EXTFEATURES_K8_REV_F_ECX; extfeat_edx = AMD_EXTFEATURES_K8_REV_F_EDX; } else if (!strcmp(opt_famrev, "fam_0f_rev_g")) { feat_ecx = AMD_FEATURES_K8_REV_G_ECX; feat_edx = AMD_FEATURES_K8_REV_G_EDX; extfeat_ecx = AMD_EXTFEATURES_K8_REV_G_ECX; extfeat_edx = AMD_EXTFEATURES_K8_REV_G_EDX; } else if (!strcmp(opt_famrev, "fam_10_rev_b")) { feat_ecx = AMD_FEATURES_FAM10h_REV_B_ECX; feat_edx = AMD_FEATURES_FAM10h_REV_B_EDX; extfeat_ecx = AMD_EXTFEATURES_FAM10h_REV_B_ECX; extfeat_edx = AMD_EXTFEATURES_FAM10h_REV_B_EDX; } else if (!strcmp(opt_famrev, "fam_10_rev_c")) { feat_ecx = AMD_FEATURES_FAM10h_REV_C_ECX; feat_edx = AMD_FEATURES_FAM10h_REV_C_EDX; extfeat_ecx = AMD_EXTFEATURES_FAM10h_REV_C_ECX; extfeat_edx = AMD_EXTFEATURES_FAM10h_REV_C_EDX; } else if (!strcmp(opt_famrev, "fam_11_rev_b")) { feat_ecx = AMD_FEATURES_FAM11h_REV_B_ECX; feat_edx = AMD_FEATURES_FAM11h_REV_B_EDX; extfeat_ecx = AMD_EXTFEATURES_FAM11h_REV_B_ECX; extfeat_edx = AMD_EXTFEATURES_FAM11h_REV_B_EDX; } else { printk("Invalid processor string: %s\n", opt_famrev); printk("CPUID will not be masked\n"); return; } status = set_mask; printk("Writing CPUID feature mask ECX:EDX -> %08Xh:%08Xh\n", feat_ecx, feat_edx); printk("Writing CPUID extended feature mask ECX:EDX -> %08Xh:%08Xh\n", extfeat_ecx, extfeat_edx); setmask: /* FIXME check if processor supports CPUID masking */ /* AMD processors prior to family 10h required a 32-bit password */ if (c->x86 >= 0x10) { wrmsr(MSR_K8_FEATURE_MASK, feat_edx, feat_ecx); wrmsr(MSR_K8_EXT_FEATURE_MASK, extfeat_edx, extfeat_ecx); } else if (c->x86 == 0x0f) { wrmsr_amd(MSR_K8_FEATURE_MASK, feat_edx, feat_ecx); wrmsr_amd(MSR_K8_EXT_FEATURE_MASK, extfeat_edx, extfeat_ecx); } } /* * amd_flush_filter={on,off}. Forcibly Enable or disable the TLB flush * filter on AMD 64-bit processors. */ static int flush_filter_force; static void flush_filter(char *s) { if (!strcmp(s, "off")) flush_filter_force = -1; if (!strcmp(s, "on")) flush_filter_force = 1; } custom_param("amd_flush_filter", flush_filter); #define num_physpages 0 /* * B step AMD K6 before B 9730xxxx have hardware bugs that can cause * misexecution of code under Linux. Owners of such processors should * contact AMD for precise details and a CPU swap. * * See http://www.multimania.com/poulot/k6bug.html * http://www.amd.com/K6/k6docs/revgd.html * * The following test is erm.. interesting. AMD neglected to up * the chip setting when fixing the bug but they also tweaked some * performance at the same time.. */ extern void vide(void); __asm__(".text\n.align 4\nvide: ret"); /* Can this system suffer from TSC drift due to C1 clock ramping? */ static int c1_ramping_may_cause_clock_drift(struct cpuinfo_x86 *c) { if (c->x86 < 0xf) { /* * TSC drift doesn't exist on 7th Gen or less * However, OS still needs to consider effects * of P-state changes on TSC */ return 0; } else if (cpuid_edx(0x80000007) & (1<<8)) { /* * CPUID.AdvPowerMgmtInfo.TscInvariant * EDX bit 8, 8000_0007 * Invariant TSC on 8th Gen or newer, use it * (assume all cores have invariant TSC) */ return 0; } return 1; } /* * Disable C1-Clock ramping if enabled in PMM7.CpuLowPwrEnh on 8th-generation * cores only. Assume BIOS has setup all Northbridges equivalently. */ static void disable_c1_ramping(void) { u8 pmm7; int node, nr_nodes
#
# Copyright (C) 2008-2011 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#

FIREWIRE_MENU:=FireWire support

define KernelPackage/firewire
  SUBMENU:=$(FIREWIRE_MENU)
  TITLE:=Support for FireWire (new stack)
  DEPENDS:=@PCI_SUPPORT +kmod-lib-crc-itu-t
  KCONFIG:=CONFIG_FIREWIRE
  FILES:=$(LINUX_DIR)/drivers/firewire/firewire-core.ko
endef

define KernelPackage/firewire/description
 Kernel support for FireWire (new stack)
endef

$(eval $(call KernelPackage,firewire))


define KernelPackage/firewire-net
  SUBMENU:=$(FIREWIRE_MENU)
  TITLE:=Support for IP networking over FireWire
  DEPENDS:=kmod-firewire
  KCONFIG:=CONFIG_FIREWIRE_NET
  FILES:=$(LINUX_DIR)/drivers/firewire/firewire-net.ko
  AUTOLOAD:=$(call AutoProbe,firewire-net)
endef

define KernelPackage/firewire-net/description
 Kernel support for IPv4 over FireWire
endef

$(eval $(call KernelPackage,firewire-net))


define KernelPackage/firewire-ohci
  SUBMENU:=$(FIREWIRE_MENU)
  TITLE:=Support for OHCI-1394 controllers
  DEPENDS:=kmod-firewire
  KCONFIG:= \
	CONFIG_FIREWIRE_OHCI \
	CONFIG_FIREWIRE_OHCI_DEBUG=n \
	CONFIG_FIREWIRE_OHCI_REMOTE_DMA=n
  FILES:=$(LINUX_DIR)/drivers/firewire/firewire-ohci.ko
  AUTOLOAD:=$(call AutoProbe,firewire-ohci)
endef


define KernelPackage/firewire-ohci/description
 Kernel support for FireWire OHCI-1394 controllers
endef

$(eval $(call KernelPackage,firewire-ohci))


define KernelPackage/firewire-sbp2
  SUBMENU:=$(FIREWIRE_MENU)
  TITLE:=Support for SBP-2 devices over FireWire
  DEPENDS:=kmod-firewire +kmod-scsi-core
  KCONFIG:=CONFIG_FIREWIRE_SBP2
  FILES:=$(LINUX_DIR)/drivers/firewire/firewire-sbp2.ko
  AUTOLOAD:=$(call AutoProbe,firewire-sbp2)
endef

define KernelPackage/firewire-sbp2/description
 Kernel support for SBP-2 devices over FireWire
endef

$(eval $(call KernelPackage,firewire-sbp2))
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-19 15:04:23 +0000