// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "ath79.dtsi"
/ {
compatible = "qca,ar9340";
#address-cells = <1>;
#size-cells = <1>;
aliases {
serial0 = &uart;
};
chosen {
bootargs = "console=ttyS0,115200";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "mips,mips74Kc";
clocks = <&pll ATH79_CLK_CPU>;
reg = <0>;
};
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
ref: ref {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-output-names = "ref";
};
};
ahb: ahb {
compatible = "simple-bus";
ranges;
#address-cells = <1>;
#size-cells = <1>;
apb: apb {
compatible = "simple-bus";
ranges;
#address-cells = <1>;
#size-cells = <1>;
ddr_ctrl: memory-controller@18000000 {
compatible = "qca,ar9340-ddr-controller",
"qca,ar7240-ddr-controller";
reg = <0x18000000 0x12c>;
#qca,ddr-wb-channel-cells = <1>;
};
uart: uart@18020000 {
compatible = "ns16550a";
reg = <0x18020000 0x2c>;
interrupts = <3>;
clocks = <&pll ATH79_CLK_REF>;
clock-names = "uart";
reg-io-width = <4>;
reg-shift = <2>;
no-loopback-test;
};
gpio: gpio@18040000 {
compatible = "qca,ar9340-gpio";
reg = <0x18040000 0x28>;
interrupts = <2>;
ngpios = <23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pinmux: pinmux@1804002c {
compatible = "pinctrl-single";
reg = <0x1804002c 0x44>;
#size-cells = <0>;
pinctrl-single,bit-per-mux;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x1>;
#pinctrl-cells = <2>;
jtag_disable_pins: pinmux_jtag_disable_pins {
pinctrl-single,bits = <0x40 0x2 0x2>;
};
};
pll: pll-controller@18050000 {
compatible = "qca,ar9340-pll", "syscon";
reg = <0x18050000 0x4c>;
#clock-cells = <1>;
clocks = <&ref>;
clock-names = "ref";
clock-output-names = "cpu", "ddr", "ahb";
};
wdt: wdt@18060008 {
compatible = "qca,ar9340-wdt", "qca,ar7130-wdt";
reg = <0x18060008 0x8>;
interrupts = <4>;
clocks = <&pll ATH79_CLK_AHB>;
clock-names = "wdt";
};
rst: reset-controller@1806001c {
compatible = "qca,ar9340-reset", "qca,ar7100-reset";
reg = <0x1806001c 0x4>;
#reset-cells = <1>;
};
hs_uart: uart@18500000 {
compatible = "qca,ar9330-uart";
reg = <0x18500000 0x14>;
interrupts = <6>;
interrupt-parent = <&miscintc>;
clocks = <&pll ATH79_CLK_UART1>;
clock-names = "uart";
status = "disabled";
};
};
gmac: gmac@18070000 {
compatible = "qca,ar9340-gmac";
reg = <0x18070000 0x14>;
};
wmac: wmac@18100000 {
compatible = "qca,ar9340-wmac";
reg = <0x18100000 0x20000>;
status = "disabled";
};
usb: usb@1b000000 {
compatible = "generic-ehci";
reg = <0x1b000000 0x1d8>;
interrupts = <3>;
resets = <&rst 5>;
reset-names = "usb-host";
has-transaction-translator;
caps-offset = <0x100>;
phy-names = "usb-phy";
phys = <&usb_phy>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
hub_port: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
};
nand: nand@1b000200 {
compatible = "qca,ar934x-nand";
reg = <0x1b000200 0xb8>;
interrupts = <21>;
interrupt-parent = <&miscintc>;
resets = <&rst 14>;
reset-names = "nand";
nand-ecc-mode = "hw";
status = "disabled";
};
spi: spi@1f000000 {
compatible = "qca,ar934x-spi";
reg = <0x1f000000 0x1c>;
clocks = <&pll ATH79_CLK_AHB>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
usb_phy: usb-phy {
compatible = "qca,ar9340-usb-phy", "qca,ar7200-usb-phy";
reset-names = "usb-phy-analog", "usb-phy", "usb-suspend-override";
resets = <&rst 11>, <&rst 4>, <&rst 3>;
#phy-cells = <0>;
status = "disabled";
};
};
&mdio0 {
compatible = "qca,ar9340-mdio";
};
ð0 {
compatible = "qca,ar9340-eth", "syscon";
pll-data = <0x16000000 0x00000101 0x00001616>;
pll-reg = <0x4 0x2c 17>;
pll-handle = <&pll>;
resets = <&rst 9>, <&rst 22>;
reset-names = "mac", "mdio";
clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
clock-names = "eth", "mdio";
};
&mdio1 {
status = "okay";
compatible = "qca,ar9340-mdio";
resets = <&rst 23>;
reset-names = "mdio";
builtin-switch;
builtin_switch: switch0@1f {
compatible = "qca,ar8229";
reg = <0x1f>;
resets = <&rst 8>;
reset-names = "switch";
phy-mode = "gmii";
qca,mib-poll-interval = <500>;
qca,phy4-mii-enable;
mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
swphy0: ethernet-phy@0 {
reg = <0>;
phy-mode = "mii";
};
swphy4: ethernet-phy@4 {
reg = <4>;
phy-mode = "mii";
};
};
};
};
ð1 {
compatible = "qca,ar9340-eth", "syscon";
resets = <&rst 13>;
reset-names = "mac";
clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
clock-names = "eth", "mdio";
phy-mode = "gmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
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#
# Copyright (C) 2009 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
# $Id: Makefile 6562 2009-10-05 08:30:14 ghd $
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=compcache
PKG_VERSION:=0.6.2
PKG_RELEASE:=$(PKG_VERSION)-1
PKG_SOURCE_URL:=http://compcache.googlecode.com/files/
PKG_MD5SUM:=27aec78dc50e34fb800c74e879057743
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
include $(INCLUDE_DIR)/package.mk
define KernelPackage/compcache
SUBMENU:=Other modules
DEPENDS:=@LINUX_2_6 @BUSYBOX_CONFIG_SWAPONOFF
TITLE:=Driver for compressed ram swap device
VERSION:=$(LINUX_VERSION)-$(BOARD)-$(LINUX_RELEASE)+$(PKG_RELEASE)
FILES:=$(PKG_BUILD_DIR)/ramzswap.$(LINUX_KMOD_SUFFIX) \
$(PKG_BUILD_DIR)/sub-projects/compression/lzo-kmod/lzo1x.$(LINUX_KMOD_SUFFIX)
endef
include $(INCLUDE_DIR)/kernel-defaults.mk
LZO = sub-projects/compression/lzo-kmod
RZSC = sub-projects/rzscontrol
BUILDFLAGS:=-DCONFIG_RAMZSWAP_STATS \
-I$(PKG_BUILD_DIR)/$(LZO) \
-Wall
RZSCFLAGS:=-I$(PKG_BUILD_DIR)/$(RZSC)/../include \
-I$(PKG_BUILD_DIR)/$(RZSC)/../..
define Build/Compile
$(MAKE) $(KERNEL_MAKEOPTS) EXTRA_CFLAGS="$(BUILDFLAGS)" M="$(PKG_BUILD_DIR)" modules
$(TARGET_CC) $(TARGET_CFLAGS) $(RZSCFLAGS) $(PKG_BUILD_DIR)/$(RZSC)/rzscontrol.c -o $(PKG_BUILD_DIR)/rzscontrol
endef
define KernelPackage/compcache/install
$(INSTALL_DIR) $(1)/etc/config
$(INSTALL_DATA) ./files/compcache.config $(1)/etc/config/compcache
$(SED) 's,%ENABLED%,$(if $(CONFIG_COMPCACHE_ENABLE),1,0),g' \
-e 's,%RAM_REPORTED%,$(call qstrip,$(CONFIG_COMPCACHE_RAM_REPORTED)),g' \
-e 's,%BACKUP_DEV%,$(call qstrip,$(CONFIG_COMPCACHE_BACKUP_DEV)),g' \
$(1)/etc/config/compcache
$(INSTALL_DIR) $(1)/etc/init.d
$(INSTALL_BIN) ./files/compcache.init $(1)/etc/init.d/compcache
$(INSTALL_DIR) $(1)/sbin
$(INSTALL_BIN) $(PKG_BUILD_DIR)/rzscontrol $(1)/sbin/rzscontrol
endef
define KernelPackage/compcache/config
source "$(SOURCE)/Config.in"
endef
$(eval $(call KernelPackage,compcache))
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