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From 3f33626ac7037bd62df9391e899f50e076e58cf7 Mon Sep 17 00:00:00 2001
From: zachary <zhangzg@marvell.com>
Date: Wed, 25 Oct 2017 15:50:29 +0800
Subject: [PATCH] fix: clock: a3700: change pwm clock for 600/600 and 1200/750
preset
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This patch is to change pwm clock from 100MHz to 50MHz for 600/600 and
1200/750 preset to align with other presets.
Change-Id: I067e189043be8c776bd3e7015a06f8ddf2590b96
Signed-off-by: zachary <zhangzg@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/45513
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Hua Jing <jinghua@marvell.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
---
wtmi/clock.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/wtmi/clock.c b/wtmi/clock.c
index 97c2825..1a1f0c6 100644
--- a/wtmi/clock.c
+++ b/wtmi/clock.c
@@ -447,7 +447,7 @@ static struct clock_cfg clk_cfg_all[] = {\
/* NorthBridge */\
{{TBG_A_S, TBG_B_S, TBG_B_S, TBG_B_S, TBG_A_P, TBG_A_P, TBG_A_P,\
TBG_B_S, TBG_B_S, TBG_A_P, TBG_B_S, TBG_A_P, TBG_B_S},\
- {2, 5, 2, 4, 1, 2, 6, 2}, /* DIV0 */\
+ {4, 5, 2, 4, 1, 2, 6, 2}, /* DIV0 */\
{1, 5, 2, 5, 2, 3, 2, 2, 3}, /* DIV1 */\
{4, 1, 5, 1, 3, 1, 2, 0, 0, 1} }, /* DIV2 */\
/* SouthBridge */\
@@ -495,7 +495,7 @@ static struct clock_cfg clk_cfg_all[] = {\
/* NorthBridge */\
{{TBG_B_S, TBG_B_S, TBG_B_S, TBG_B_S, TBG_B_S, TBG_B_S, TBG_B_S,\
TBG_B_S, TBG_A_S, TBG_B_S, TBG_A_P, TBG_B_S, TBG_A_S},\
- {3, 4, 3, 4, 1, 1, 5, 1}, /* DIV0 */\
+ {6, 4, 3, 4, 1, 1, 5, 1}, /* DIV0 */\
{1, 6, 3, 4, 1, 6, 1, 1, 6}, /* DIV1 */\
{4, 1, 6, 1, 3, 1, 3, 0, 0, 1} }, /* DIV2 */\
/* SouthBridge */\
--
2.30.2
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