aboutsummaryrefslogtreecommitdiffstats
path: root/include
ModeNameSize
-rw-r--r--autotools.mk5124logstatsplain
-rw-r--r--cmake.mk2211logstatsplain
-rw-r--r--debug.mk843logstatsplain
-rw-r--r--depends.mk1241logstatsplain
-rw-r--r--device_table.txt173logstatsplain
-rw-r--r--download.mk5245logstatsplain
-rw-r--r--feeds.mk754logstatsplain
-rw-r--r--host-build.mk5502logstatsplain
-rw-r--r--host.mk1980logstatsplain
-rw-r--r--image.mk9254logstatsplain
-rw-r--r--kernel-build.mk4155logstatsplain
-rw-r--r--kernel-defaults.mk7208logstatsplain
-rw-r--r--kernel-version.mk1034logstatsplain
-rw-r--r--kernel.mk7341logstatsplain
-rw-r--r--ltqtapi.mk421logstatsplain
-rw-r--r--netfilter.mk15179logstatsplain
-rw-r--r--nls.mk1050logstatsplain
-rw-r--r--package-bin.mk783logstatsplain
-rw-r--r--package-defaults.mk3645logstatsplain
-rw-r--r--package-dumpinfo.mk2112logstatsplain
-rw-r--r--package-ipkg.mk7353logstatsplain
-rw-r--r--package.mk10211logstatsplain
-rw-r--r--prereq-build.mk4651logstatsplain
-rw-r--r--prereq.mk1140logstatsplain
-rw-r--r--quilt.mk5274logstatsplain
-rw-r--r--scan.mk2788logstatsplain
-rw-r--r--scons.mk492logstatsplain
-rw-r--r--shell.sh529logstatsplain
d---------site3190logstatsplain
-rw-r--r--subdir.mk3489logstatsplain
-rw-r--r--target.mk10258logstatsplain
-rw-r--r--toolchain-build.mk567logstatsplain
-rw-r--r--toplevel.mk6422logstatsplain
-rw-r--r--uclibc++.mk341logstatsplain
-rw-r--r--unpack.mk2346logstatsplain
-rw-r--r--verbose.mk1470logstatsplain
-rw-r--r--version.mk2850logstatsplain
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-12 16:35:20 +0000
RE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ``` yosys – Yosys Open SYnthesis Suite =================================== This is a framework for RTL synthesis tools. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base. Yosys is free software licensed under the ISC license (a GPL compatible license that is similar in terms to the MIT license or the 2-clause BSD license). Web Site and Other Resources ============================ More information and documentation can be found on the Yosys web site: - http://www.clifford.at/yosys/ The "Documentation" page on the web site contains links to more resources, including a manual that even describes some of the Yosys internals: - http://www.clifford.at/yosys/documentation.html The file `CodingReadme` in this directory contains additional information for people interested in using the Yosys C++ APIs. Users interested in formal verification might want to use the formal verification front-end for Yosys, SymbiYosys: - https://symbiyosys.readthedocs.io/en/latest/ - https://github.com/YosysHQ/SymbiYosys Setup ====== You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make. TCL, readline and libffi are optional (see ``ENABLE_*`` settings in Makefile). Xdot (graphviz) is used by the ``show`` command in yosys to display schematics. For example on Ubuntu Linux 16.04 LTS the following commands will install all prerequisites for building yosys: $ sudo apt-get install build-essential clang bison flex \ libreadline-dev gawk tcl-dev libffi-dev git \ graphviz xdot pkg-config python3 libboost-system-dev \ libboost-python-dev libboost-filesystem-dev zlib1g-dev Similarily, on Mac OS X Homebrew can be used to install dependencies: $ brew tap Homebrew/bundle && brew bundle or MacPorts: $ sudo port install bison flex readline gawk libffi \ git graphviz pkgconfig python36 boost zlib tcl On FreeBSD use the following command to install all prerequisites: # pkg install bison flex readline gawk libffi\ git graphviz pkgconf python3 python36 tcl-wrapper boost-libs On FreeBSD system use gmake instead of make. To run tests use: % MAKE=gmake CC=cc gmake test For Cygwin use the following command to install all prerequisites, or select these additional packages: setup-x86_64.exe -q --packages=bison,flex,gcc-core,gcc-g++,git,libffi-devel,libreadline-devel,make,pkg-config,python3,tcl-devel,boost-build,zlib-devel There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well as a source distribution for Visual Studio. Visit the Yosys download page for more information: http://www.clifford.at/yosys/download.html To configure the build system to use a specific compiler, use one of $ make config-clang $ make config-gcc For other compilers and build configurations it might be necessary to make some changes to the config section of the Makefile. $ vi Makefile # ..or.. $ vi Makefile.conf To build Yosys simply type 'make' in this directory. $ make $ sudo make install Note that this also downloads, builds and installs ABC (using yosys-abc as executable name). Tests are located in the tests subdirectory and can be executed using the test target. Note that you need gawk as well as a recent version of iverilog (i.e. build from git). Then, execute tests via: $ make test Getting Started =============== Yosys can be used with the interactive command shell, with synthesis scripts or with command line arguments. Let's perform a simple synthesis job using the interactive command shell: $ ./yosys yosys> the command ``help`` can be used to print a list of all available commands and ``help <command>`` to print details on the specified command: yosys> help help reading and elaborating the design using the Verilog frontend: yosys> read -sv tests/simple/fiedler-cooley.v yosys> hierarchy -top up3down5 writing the design to the console in Yosys's internal format: yosys> write_ilang convert processes (``always`` blocks) to netlist elements and perform some simple optimizations: yosys> proc; opt display design netlist using ``xdot``: yosys> show the same thing using ``gv`` as postscript viewer: yosys> show -format ps -viewer gv translating netlist to gate logic and perform some simple optimizations: yosys> techmap; opt write design netlist to a new Verilog file: yosys> write_verilog synth.v or using a simple synthesis script: $ cat synth.ys read -sv tests/simple/fiedler-cooley.v hierarchy -top up3down5 proc; opt; techmap; opt write_verilog synth.v $ ./yosys synth.ys If ABC is enabled in the Yosys build configuration and a cell library is given in the liberty file ``mycells.lib``, the following synthesis script will synthesize for the given cell library: # read design read -sv tests/simple/fiedler-cooley.v hierarchy -top up3down5 # the high-level stuff proc; fsm; opt; memory; opt # mapping to internal cell library techmap; opt # mapping flip-flops to mycells.lib dfflibmap -liberty mycells.lib # mapping logic to mycells.lib abc -liberty mycells.lib # cleanup clean If you do not have a liberty file but want to test this synthesis script, you can use the file ``examples/cmos/cmos_cells.lib`` from the yosys sources as simple example. Liberty file downloads for and information about free and open ASIC standard cell libraries can be found here: - http://www.vlsitechnology.org/html/libraries.html - http://www.vlsitechnology.org/synopsys/vsclib013.lib The command ``synth`` provides a good default synthesis script (see ``help synth``): read -sv tests/simple/fiedler-cooley.v synth -top up3down5 # mapping to target cells dfflibmap -liberty mycells.lib abc -liberty mycells.lib clean The command ``prep`` provides a good default word-level synthesis script, as used in SMT-based formal verification. Unsupported Verilog-2005 Features ================================= The following Verilog-2005 features are not supported by Yosys and there are currently no plans to add support for them: - Non-synthesizable language features as defined in IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002 - The ``tri``, ``triand`` and ``trior`` net types - The ``config`` and ``disable`` keywords and library map files Verilog Attributes and non-standard features ============================================ - The ``full_case`` attribute on case statements is supported (also the non-standard ``// synopsys full_case`` directive) - The ``parallel_case`` attribute on case statements is supported (also the non-standard ``// synopsys parallel_case`` directive) - The ``// synopsys translate_off`` and ``// synopsys translate_on`` directives are also supported (but the use of ``` `ifdef .. `endif ``` is strongly recommended instead). - The ``nomem2reg`` attribute on modules or arrays prohibits the automatic early conversion of arrays to separate registers. This is potentially dangerous. Usually the front-end has good reasons for converting an array to a list of registers. Prohibiting this step will likely result in incorrect synthesis results. - The ``mem2reg`` attribute on modules or arrays forces the early conversion of arrays to separate registers. - The ``nomeminit`` attribute on modules or arrays prohibits the creation of initialized memories. This effectively puts ``mem2reg`` on all memories that are written to in an ``initial`` block and are not ROMs. - The ``nolatches`` attribute on modules or always-blocks prohibits the generation of logic-loops for latches. Instead all not explicitly assigned values default to x-bits. This does not affect clocked storage elements such as flip-flops. - The ``nosync`` attribute on registers prohibits the generation of a storage element. The register itself will always have all bits set to 'x' (undefined). The variable may only be used as blocking assigned temporary variable within an always block. This is mostly used internally by Yosys to synthesize Verilog functions and access arrays. - The ``onehot`` attribute on wires mark them as one-hot state register. This is used for example for memory port sharing and set by the fsm_map pass. - The ``blackbox`` attribute on modules is used to mark empty stub modules